So the C28x core handles up to 15 interrupts, starting from the backend, interrupts 13 and 14 come directly from CPU on-chip timers 1 and 2. One interrupt is dedicated to the non-maskable interrupts and then interrupts 1 through 12 are coming from the PIE, Concerto interrupt scheme is similar to the Delfino. It features a peripheral interrupt expansion module that multiplexes interrupts from a number of peripherals into a single CPU interrupt. As for Delfino, the PIE can support up to 96 interrupts in an 8x12 configuration, on Concerto, 70 of these interrupts are used instead. The PIE module provides additional control before the interrupt reaches the C28x CPU. Interrupts in the core are automatically prioritized by the C28 hardware. Prioritization for all interrupts will be found in the system control guide specific to the particular device family. So Group 1, which corresponds to CPU INT1 has the highest priority. Within each group, there are eight interrupts with an INT by 1, with INT by 1 being the highest priority and INT by 8 having the lowest. Again, the Concerto supports up to 70 interrupts and it is still based on a fixed priority, but it is possible to implement software prioritization interrupts, an application note is available on how to do this. There are three external interrupts available, these are XINT1, XINT2 and XINT3. Any of the 64 GPIOs can be used to trigger one of these external sources as an interrupt. The C28x external interrupts are tapped after the input synchronization and qualification circuits of the GPIO multiplexer. These XINT interrupts can be configured as either negative edge triggered, positive edge triggered or negative and positive edge triggered. Each of the three external interrupts has its own 16-bit counter that starts counting when a valid interrupt edge is detected and resets when another valid edge is detected.