The legacy C28x CPU is a 32-bit fixed point CPU that performs arithmetic, Boolean logic, multiply and shift operations, when performing signed math, the CPU uses the two’s complement notation. Control engine is based on the C28x plus floating point (C28x plus FPU) processor which extends the capabilities of the C28x core to the 32-bit fixed point core by adding registers and instructions to support IEEE single precision 754 floating point operations. Native floating point brings many advantages, not only performance wise, it is generally more robust, meaning it is less error prone than fixed point math. It can also do the same math operations or functions as fixed point with significantly fewer instructions. Engineers usually start the development with floating point then translate their code into fixed point before implementing them in their final designs. By eliminating the need for this conversion, TI has reduced development times, as well as prevent most scaling and saturation issues, with easier development and faster time to market. Through benchmarks against other C28x processors, floating point instructions help reduce cycle count for math functions by up to 52%. Double precision operations will require support libraries however. Note that no changes have been made to the C28x plus FPU based instructions, pipeline or memory bus architecture. Therefore, programs written for the C28x plus FPU such as the existing Delfino designs are completely compatible with the Concerto core. The Viterbi CRC and complex arithmetic unit (or VCU) further enhances the digital signal processing capability of the C28x CPU core. The VCU comes with its own resources and details will be covered later on in this presentation. The base CPU features include circular addressing and a modified Harvard architecture that enables instructions and data fetches to be performed in parallel. The CPU can read instructions and data while it writes data simultaneously to maintain the single cycle instruction operation across the pipeline. As a RISC processor, the Concerto performs single cycle instruction, execution and register, to register operations. The Concerto C28x comes with three CPU timers, which are exactly the same as what is on the Piccolo series of devices. Also the C28x memory map is accessible outside of the CPU by the memory interface, which connects the CPU logic to memories, peripherals or other interfaces. The memory interface includes separate buses for program space and data space. This means an instruction can be fetched from program memory while data memory is being accessed at the same time. Control peripherals and communication peripherals are accessible through the data bus, as well. Although the analog-to-digital converter, the comparator and the temp sensors are not part of the control subsystem, they can be accessed through the CIB, this is short for the “Common Interface Bus” and this is accessible from all four masters, namely C28x CPU, the C28X DMA, the M3 CPU and the M3 DMA simultaneously. Accesses will be arbitrated by a round robin arbitration mechanism, which is similar to the RAM wrapper arbitration. Although the Concerto device supports CAN modules, these are mapped to the M3 side, so they are mapped to the master side of the system, these cannot be accessed from the control side. Also the EPI that is used to interface to external memory or FPGA is also owned by the host subsystem and cannot be accessed directly through the C28x. At reset all the GPIO pins belonging to the M3 MUX system. The M3 is responsible for allocating pins to the C28x MUX, once these pins have been allocated, the assignment can be locked for safety. Also, there is no system Watchdog on the C28x side but there is an NMI Watchdog.