The Concerto is based on 65 nanometer, F021 flash technology, the M3 master system and the C28x control system operate from independent flash banks. The C28x flash is 512 kBytes that are split into 14 distinct sectors, eight of these sectors are 8K each and the other six are 32K each, it cannot be accessed from the DMA. The exact flash access time has not yet been characterized, but the flash technology used in the F28M35x devices should have an overall cycle time of about 25 nanoseconds or translated to about 40 MHz. This number takes into account ECC error detections and overhead due to correction as well as any overhead associated with performance acceleration, mechanisms and caching. To boost code execution performance, acceleration hardware has been added, it consists of 128-bit wide two level pre-fetch mechanisms. After the first 128-bit wide fetch, the flash interface will fetch ahead the next 128-bit wide word while the currently fetched instructions are fed to the CPU. In theory, 128-bit word can hold four 32-bit instructions or eight 16-bit instructions. Hence, this system can provide near single cycle performance even if the flash wait states are as high as three or four cycle access. As a comparison, C2000 devices such as the Delfino class running at the same 150 MHz and using similar acceleration techniques only achieve about 60% efficiency or about 90 MHz effective. Therefore, the F28M35x flash offers about 50% more performance over the C2000 devices. Although the M3 benefits from the 128 byte instruction cache, it is not implemented on the C28x control system flash interface because real time control code is not as cache-friendly as the application code that may be run on the master system. Only the 16 byte data cache has been implemented on the control side. During a flash memory operation, and these are write, page erase or mass erase, access to the flash memory is inhibited. Although the M3 flash bank can only be programmed by the M3 and C28x flash banks can only be programmed by the C28x, both processor cores share the same pump, there is a flash semaphore for pump ownership. The C28x bank flash registers are mapped in C28x space and M3 flash bank registers on the M3 side, by default on reset, the flash pump is mapped to the M3. For the C28x to program its own bank, it must request access to flash pump and the clock control registers via these semaphores. For the ECC security feature, a future session will cover the safety aspects of these devices.