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The control side RAM has 100 kBytes of RAM and it is split into 14 distinct blocks again, M0 and M1 are 2 kBytes each, whereas the other 12 blocks are 8 kBytes each. Two additional 2 kByte blocks are reserved for the inter-processor communication, the M2C and the C2M that are at the bottom of this slide. M2C is for the M3, to control side exchange and C2M is for the C28x to the M3 exchange, the L blocks are dedicated. So what does this means? At the beginning, all the eight shared RAM blocks mapped to the M3 side. For control, one might need 4 by 8, so 32 kBytes, it can re-map S1, S3, S5 and S7 to the C28x side. Moving forward, if one needs more memory, it can allocate the whole shared RAM. Now just one allocates the other blocks S0, S2, S4 and S6 for the DSP side. And, again, TI will cover more of the safety features in an upcoming presentation.
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