The DMA in Concerto is primarily used to reduce CPU bandwidth for data movement, but another feature of the C28X DMA is that it has the ability to orthogonally re-arrange data as it is transferred for more streamlined processing, the Concerto DMA looks very similar to the Delfino DMA. The DMA module is an event based machine, meaning it requires a peripheral interrupt trigger to start the DMA transfer. The sources for this can be the ADC sequencers from the common interface bus, an external interrupt that can be triggered by any of the GPIOs, the McBSP on the device can also trigger a DMA transfer, interrupts from CPU timers and the ePWM start-up conversion signals, either ePWM A or B, or external interrupt on 1, 2 or 3, that can come from any of the 64 GPIOs. There is no mechanism within the module itself to start memory transfers periodically, but the I-timer interrupt trigger source can essentially create periodic time driven transfers. The interrupt trigger source for each of the six DMA channels can be configured separately and each channel contains its own independent PIE interrupt to let the CPU know when a DMA transfer is either started or completed. Another thing is five of the six channels are exactly the same while Channel 1 has one additional feature, this channel can be configured at a higher priority than all of the other channels. The DMA can transfer data to and from some RAM zones like the shared memory blocks, including S0 to S7, following the rules given by each block ownership. DMA can also transfer from L2 and L3, the dedicated memory blocks, there are also message RAM blocks that are dedicated to the inter-processor communication. Dedicated blocks L0 and L1 and M0 and M1 cannot be used neither as source nor a destination by the DMA controller, again, flash and ROM are not accessible via DMA on this device. The peripheral interrupts can also be used to trigger a DMA, but the other peripherals on the device such as the I2C interface, the SPI, the eCAP and the eQEP, these are excluded from DMA visibility. The DMA itself consists of a four-stage pipeline, the one exception to this is when a DMA channel is configured to have one of the McBSPs as its data source. A read of a McBSP DRR register stalls the DMA bus for one cycle during the read portion of the transfer. Also the DMA channels can be configured with a word of either 16 or 32 bits and the transfer is defined as a number, up to 64K burst to transfer. The burst is defined as the smallest entity to transfer a time, it can be configured for each channel for one of the 32 words.