The upper left plot shows ADC basic operation. The upper right and lower pictures illustrate varying degrees of complexity in the measurement to compensate for errors. Example: with a 1MHz clock source, it would take 41µs to measure a 40 mV signal and 200µs to measure a 200 mV signal. If the range of the voltage is known, then the ADC ramp can be started at a non-zero value. This first picture shows the example of what was just covered. As this slide shows, the DAC ramping up and the end of conversion are represented when the crossover occurs. Each step represents one LSB of the DAC or one 1mV in what will be called the Y-axis, and one clock period in the X-axis or the time axis. This second picture shows users the ability to change the direction of the RAMP. The purpose of this is to address the voltage inertia error that was pointed out previously when describing the overdrive error within the comparator. This third picture shows two additional ramps or sweeps to account for offsets within the signal chain. There are three main points to take away from this slide. First, the RAMP is flexible and it can be done in either the up or down direction. Secondly, the conversion time is a function of the voltage being measured but not constrained to starting at zero. If customers know what the voltage level is, they can start at a non-zero level to, in a sense, decrease the sampling time or the time it takes to create a conversion. This is exemplified here on the right-hand side of the picture where after the first two measurements are made, the user or the application knows roughly where the voltage is. So instead of starting back at zero, it can start now at a higher level and get to the desired voltage more quickly, hence, increasing the response time of making a measurement. The third and probably most important point to make about this third picture is that the mechanism is automated. Users simply need to configure the mode, the direction of the RAMP, and the process for determining or completing the conversion is handled completely within the surrounding logic within the Analog Pool.