During a conversion, the SAR ADC is normally in one of two different phases, “tracking” or “converting.” Establishing the faster conversion rate requires programming the device to a faster SAR clock frequency. During the tracking phase, the ADC's sampling capacitor is connected to the external pin input through the analog multiplexer. When a conversion is initiated by the selected start-of-conversion source, the sampling capacitor is disconnected from the input, and the SAR conversion is performed. To speed up the conversion time and allow enough tracking time, the SAR clock must be set to a higher rate. The ADC contains a subset of the multiplexing features found on the C8051F34A. Only the positive channel (AIN+) of the ADC is available, meaning that only single ended measurements are possible (from AIN+ to GND). When developing code for the C8051T620/T320/T321 on the C8051F34A, the five LSBs of the AMX0N register should always be written to 11111b (binary). This will select GND as the negative input on the C8051F34A’s ADC and perform a single-ended measurement. In addition to the 1x gain setting of the C8051F34A's ADC, C8051T620/T320/T321 devices have a gain setting of 0.5x. If the CNVSTR pin is used to begin conversions on the ADC, it is important to note the differences in timing between the different families. On the C8051F34A, the rising edge of CNVSTR always ends tracking mode and begins a conversion. On other devices, when the AD0TM bit is set to 0, conversions are initiated on the rising edge of CNVSTR, and tracking occurs when CNVSTR is low. On the ‘T620/T320/T321, if AD0TM is set to 1, tracking occurs any time a conversion is not in progress and lasts an additional three SAR clocks after the rising edge of CNVSTR.