Here is an animated presentation of the three basic DDS building blocks in action. Note the accumulator, angle-to-amplitude converter and DAC. Also shown is the phase wheel for demonstrating the construction of a sinusoidal output signal based on the instantaneous accumulator values. This DDS example uses a 6-bit accumulator (N equals 6) and 5-bit DAC (D equals 5), even though this violates the so-called D plus 3 rule. Recall the D plus 3 rule, which requires the angle to amplitude converter input bus to be at least 3 bits greater than the DAC input bus in order to guarantee half LSB amplitude precision when converting from angle to amplitude. For this demonstration, however, violation of the D plus 3 rule causes no harm. The DDS frequency is based on the system clock frequency and is set by the FTW. For this demonstration the value of the FTW, denoted by the variable M, is 7. The demonstration begins with accumulator cleared. That is, the accumulator output is 0 prior to the first system clock edge. The first cycle of the system clock causes the accumulator to increase by the value of the FTW, 7 in this case. This appears as a counter-clockwise rotation about the phase wheel and defines a particular angle relative to 0. The sine of this angle corresponds to a particular point on a sine wave. The angle to amplitude converter scales the sine of this angle so that it corresponds to D-bit range of the DAC. Note that the DAC range spans the diameter of the phase wheel. The DDS has now generated one DAC input sample which spans a interval equal to 1 period of the system clock (1 over fs). The next 3 cycles of the system clock continue the process. That is, advancing the accumulator and subsequently rotating the phase wheel, generating the sine component of the resulting angle, and applying the appropriate scaling based on the DAC range. At this point, the demonstration ceases to explicitly show the system clock cycles, but keep in mind the system clock continues to operate in the background. As such, the demonstration continues to show the advancement of the phase wheel over several more system clock cycles. Note when the accumulator rolled over there was a residue or remainder, which carried into the next accumulation cycle. The DDS has now built up approximately one and a quarter cycles of a sample sinusoid at the output of the angle-to-amplitude converter. These sinusoidal samples are delivered in sequence to the input of the DAC. At the DAC output we see the analog representation of the digital input samples. The DAC holds each sample for 1 period of the system clock. Hence, the stair-step appearance of the DAC output. This is the zero-order hold effect imposed by the DAC, which results in the sinc envelope distortion in the frequency domain. The sampled DAC output signal passes through a reconstruction filter, which typically exhibits a lowpass frequency response, but a bandpass response is also feasible. The result is a smooth sinusoid at the output of the reconstruction filter with a frequency equal to the average roll over rate of the accumulator as defined by the standard DDS equation. The smooth sinusoid produced by the DDS can be used as a carrier signal for analog mixing or any application requiring a sinusoidal signal source, especially applications that have a need for digital frequency tuning. Applications requiring a tunable clock source are feasible by employing a comparator at the output of the reconstruction filter. The comparator converts the DDS output sinusoid to a square wave suitable for clocking applications. The time domain plot shows an overlay of the primary signals involved in the generation of the DDS output. The first is the output of the angle-to-amplitude converter or vector data, which is the sinusoid in purely digital form, that is, a time sequence of numerical values. The next signal is the DAC output showing its stair-step nature, a consequence of the DAC’s zero-order hold function. The third signal is the filtered DAC output, which results in a smooth sinusoid. Of particular interest, note the zero-crossing of the sinusoid does not necessarily coincide with the DAC samples. This is because the filter effectively performs a real-time interpolation between the DAC samples and yields a sinusoid with a frequency equivalent to the average rollover rate of the accumulator. The final signal is square wave generated by the comparator output, which switches at the zero-crossing points of the filtered DAC output.