During a write sequence, an SMBus master writes data to a slave device. The slave in this transfer will be a receiver during the address Byte, and a receiver during all data Bytes. When slave events are enabled (INH = 0), the interface enters slave receiver mode when a START followed by a slave address and direction bit (WRITE in this case) is received. If hardware ACK generation is disabled, upon entering slave receiver mode, an interrupt is generated and the ACKRQ bit is set. The software must respond to the received slave address with an ACK, or ignore the received slave address with a NACK. If hardware ACK generation is enabled, the hardware will apply the ACK for a slave address which matches the criteria set up by SMB0ADR and SMB0ADM. The interrupt will occur after the ACK cycle.