During a write sequence, an SMBus master writes data to a slave device. The master in this transfer will be a transmitter during the address Byte, and a transmitter during all data Bytes. The SMBus interface generates the START condition and transmits the first Byte containing the address of the target slave and the data direction bit. In this case the data direction bit (R/W) will be logic 0 (WRITE). The master then transmits one or more Bytes of serial data. After each Byte is transmitted, an acknowledge bit is generated by the slave. The transfer is ended when the STO bit is set and a STOP is generated. The interface will switch to master receiver mode if SMB0DAT is not written following a master transmitter interrupt. Two transmit data Bytes are shown above, though any number of Bytes may be transmitted. Notice that all of the “data Byte transferred” interrupts occur after the ACK cycle in this mode, regardless of whether hardware ACK generation is enabled.