Datenblatt für MAX11101 von Analog Devices Inc./Maxim Integrated

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MAX11101
14-Bit, +5V, 200ksps ADC with 10µA Shutdown
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19-6047; Rev 1; 1/12
Ordering Information appears at end of data sheet.
General Description
The MAX11101 low-power, 14-bit analog-to-digital con-
verter (ADC) features a successive approximation ADC,
automatic power-down, fast 1.1Fs wake-up, and a high-
speed SPI/QSPI™/MICROWIRE®-compatible interface.
The MAX11101 operates with a single +5V analog supply
and features a separate digital supply, allowing direct
interfacing with 2.7V to 5.25V digital logic.
At the maximum sampling rate of 200ksps, the MAX11101
typically consumes 2.45mA. Power consumption is typi-
cally 12.25mW (VAVDD = VDVDD = 5V) at a 200ksps
(max) sampling rate. AutoShutdown™ reduces supply
current to 140FA at 10ksps and to less than 10FA at
reduced sampling rates.
Excellent dynamic performance and low power, com-
bined with ease of use and small package size (10-pin
FMAXM and 12-bump WLP), make the MAX11101 ideal
for battery-powered and data-acquisition applications
or for other circuits with demanding power consumption
and space requirements.
Applications
Motor Control
Industrial Process Control
Industrial I/O Modules
Data-Acquisition Systems
Thermocouple Measurements
Accelerometer Measurements
Portable- and Battery-Powered Equipment
Features
S 14-Bit Resolution, 1 LSB DNL
S +5V Single-Supply Operation
S Adjustable Logic Level (2.7V to 5.25V)
S Input Voltage Range: 0 to VREF
S Internal Track-and-Hold, 4MHz Input Bandwidth
S SPI/QSPI/MICROWIRE-Compatible Serial Interface
S Small 10-Pin µMAX and WLP Packages
S Low Power
2.45mA at 200ksps
140µA at 10ksps
0.1µA in Power-Down Mode
QSPI is a trademark of Motorola, Inc.
MICROWIRE is a registered trademark of National Semiconductor Corp.
AutoShutdown is a trademark and µMAX is a registered trademark of Maxim Integrated Products, Inc.
Functional Diagram
For related parts and recommended products to use with this part, refer to: www.maxim-ic.com/MAX11101.related
AIN
TRACK-AND-
HOLD
14-BIT SAR
ADC
CONTROL
DVDD
DGND
CS
AGND
AVDD
REF
DOUT
SCLK
MAX11101
OUTPUT
BUFFER
For pricing, delivery, and ordering information, please contact Maxim Direct at 1-888-629-4642,
or visit Maxim’s website at www.maxim-ic.com.
[MAXI/VI
����������������������������������������������������������������� Maxim Integrated Products 2
MAX11101
14-Bit, +5V, 200ksps ADC with 10µA Shutdown
AVDD to AGND .......................................................-0.3V to +6V
DVDD to DGND ....................................................... -0.3V to +6V
DGND to AGND ...................................................-0.3V to +0.3V
AIN, REF to AGND ............................... -0.3V to (VAVDD + 0.3V)
SCLK, CS to DGND .................................................-0.3V to +6V
DOUT to DGND .................................... -0.3V to (VDVDD + 0.3V)
Maximum Current Into Any Pin ....................................... Q50mA
Continuous Power Dissipation (TA = +70NC)
FMAX (derate 5.6mW/NC above +70NC) .....................444mW
WLP (derate 16.1mW/NC above +70NC)......1300mW (Note 1)
Operating Temperature Range .......................... -40NC to +85NC
Maximum Junction Temperature .....................................+150NC
Storage Temperature Range ............................ -65NC to +150NC
Lead Temperature (FMAX only; soldering, 10s) .............+300NC
Soldering Temperature (reflow) ......................................+260NC
ABSOLUTE MAXIMUM RATINGS
Stresses beyond those listed under “Absolute Maximum Ratings” may cause permanent damage to the device. These are stress ratings only, and functional opera-
tion of the device at these or any other conditions beyond those indicated in the operational sections of the specifications is not implied. Exposure to absolute
maximum rating conditions for extended periods may affect device reliability.
ELECTRICAL CHARACTERISTICS
(VAVDD = VDVDD = 4.75V to 5.25V, fSCLK = 4.8MHz (50% duty cycle), 24 clocks/conversion (200ksps), VREF = 4.096V, TA = TMIN to
TMAX, unless otherwise noted. Typical values are at TA = +25°C.)
Note 1: All WLP devices are 100% production tested at TA = +25NC. Specifications over temperature limits are guaranteed by
design and characterization..
PARAMETER SYMBOL CONDITIONS MIN TYP MAX UNITS
DC ACCURACY (Note 2)
Resolution 14 Bits
Relative Accuracy INL (Note 3) -1 +1 LSB
Differential Nonlinearity DNL No missing codes over temperature -1 ±0.5 +1 LSB
Transition Noise RMS noise Q0.32 LSBRMS
Offset Error 0.2 1 mV
Gain Error (Note 4) Q0.002 ±0.01 %FSR
Offset Drift 0.4 ppm/°C
Gain Drift (Note 4) 0.2 ppm/°C
DYNAMIC SPECIFICATIONS (1kHz sine wave, 4.096VP-P) (Note 2)
Signal-to-Noise Plus Distortion SINAD 81 84 dB
Signal-to-Noise Ratio SNR 82 84 dB
Total Harmonic Distortion THD -99 -86 dB
Spurious-Free Dynamic Range SFDR 87 101 dB
Full-Power Bandwidth -3dB point 4 MHz
Full-Linear Bandwidth SINAD > 81dB 20 kHz
CONVERSION RATE
Conversion Time tCONV (Note 5) 5 240 Fs
Serial Clock Frequency fSCLK 0.1 4.8 MHz
Aperture Delay 15 ns
Aperture Jitter < 50 ps
Sample Rate fSfSCLK/24 200 ksps
Track/Hold Acquisition Time tACQ 1.1 Fs
[MAXI/VI
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MAX11101
14-Bit, +5V, 200ksps ADC with 10µA Shutdown
ELECTRICAL CHARACTERISTICS (continued)
(VAVDD = VDVDD = 4.75V to 5.25V, fSCLK = 4.8MHz (50% duty cycle), 24 clocks/conversion (200ksps), VREF = 4.096V, TA = TMIN to
TMAX, unless otherwise noted. Typical values are at TA = +25°C.)
PARAMETER SYMBOL CONDITIONS MIN TYP MAX UNITS
ANALOG INPUT (AIN)
Input Range VAIN 0 VREF V
Input Leakage Current SCLK idle 0.01 1 FA
EXTERNAL REFERENCE
Input Voltage Range VREF 3.8 VAVDD V
Input Current IREF
VREF = 4.096V, fSCLK = 4.8MHz 60 150
FAVREF = 4.096V, SCLK idle 0.01 10
CS = DVDD, SCLK idle 0.01
DIGITAL INPUTS (SCLK, CS)
Input High Voltage VIH VDVDD = 2.7V to 5.25V 0.7 x
VDVDD V
Input Low Voltage VIL VDVDD = 2.7V to 5.25V 0.3 x
VDVDD V
Input Leakage Current IIN VIN = 0 to VDVDD Q0.1 Q1FA
Input Hysteresis VHYST 0.2 V
Input Capacitance CIN 15 pF
DIGITAL OUTPUT (DOUT)
Output High Voltage VOH ISOURCE = 0.5mA, VDVDD = 2.7V to 5.25V VDVDD
- 0.25 V
Output Low Voltage VOL ISINK = 2mA, VDVDD = 2.7V to 5.25V 0.4 V
Three-State Output Leakage
Current ILCS = DVDD Q0.1 Q10 FA
Three-State Output Capacitance COUT CS = DVDD 15 pF
POWER SUPPLIES
Analog Supply VAVDD 4.75 5.25 V
Digital Supply VDVDD 2.7 5.25 V
Analog Supply Current IAVDD CS = DGND, 200ksps 1.85 2.5 mA
Digital Supply Current IDVDD
CS = DGND,
DOUT = all zeros, 200ksps 0.6 1.0 mA
Shutdown Supply Current IAVDD +
IDVDD
CS = DVDD, SCLK = idle 0.1 10 FA
Power-Supply Rejection Ratio PSRR VAVDD = VDVDD = 4.75V to 5.25V, full-
scale input (Note 6) 68 dB
[MAXI/VI
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MAX11101
14-Bit, +5V, 200ksps ADC with 10µA Shutdown
TIMING CHARACTERISTICS
(VAVDD = VDVDD = 4.75V to 5.25V, fSCLK = 4.8MHz (50% duty cycle), 24 clocks/conversion (200ksps), VREF = 4.096V, TA = TMIN to
TMAX, unless otherwise noted. Typical values are at TA = +25°C.) (See Figure 1, Figure 2, Figure 3, and Figure 6.)
TIMING CHARACTERISTICS
(VAVDD = 4.75V to 5.25V, VDVDD = 2.7V to 5.25V, fSCLK = 4.8MHz (50% duty cycle), 24 clocks/conversion (200ksps), VREF = +4.096V,
TA = TMIN to TMAX, unless otherwise noted. Typical values are at TA = +25°C.) (See Figure 1, Figure 2, Figure 3, and Figure 6.)
Note 2: VAVDD = VDVDD = +5V.
Note 3: Relative accuracy is the deviation of the analog value at any code from its theoretical value after the full-scale range has
been calibrated.
Note 4: Offset and reference errors nulled.
Note 5: Conversion time is defined as the number of clock cycles multiplied by the clock period; clock has 50% duty cycle.
Note 6: Defined as the change in positive full scale caused by a Q5% variation in the nominal supply voltage.
PARAMETER SYMBOL CONDITIONS MIN TYP MAX UNITS
Acquisition Time tACQ 1.1 Fs
SCLK to DOUT Valid tDO CDOUT = 50pF 50 ns
CS Fall to DOUT Enable tDV CDOUT = 50pF 80 ns
CS Rise to DOUT Disable tTR CDOUT = 50pF 80 ns
CS Pulse Width tCSW 50 ns
CS Fall to SCLK Rise Setup tCSS 100 ns
CS Rise to SCLK Rise Hold tCSH 0 ns
SCLK High Pulse Width tCH 65 ns
SCLK Low Pulse Width tCL 65 ns
SCLK Period tCP 208 ns
PARAMETER SYMBOL CONDITIONS MIN TYP MAX UNITS
Acquisition Time tACQ 1.1 Fs
SCLK to DOUT Valid tDO CDOUT = 50pF 100 ns
CS Fall to DOUT Enable tDV CDOUT = 50pF 100 ns
CS Rise to DOUT Disable tTR CDOUT = 50pF 80 ns
CS Pulse Width tCSW 50 ns
CS Fall to SCLK Rise Setup tCSS 100 ns
CS Rise to SCLK Rise Hold tCSH 0 ns
SCLK High Pulse Width tCH 65 ns
SCLK Low Pulse Width tCL 65 ns
SCLK Period tCP 208 ns
����������������������������������������������������������������� Maxim Integrated Products 5
MAX11101
14-Bit, +5V, 200ksps ADC with 10µA Shutdown
Typical Operating Characteristics
(VAVDD = VDVDD = 5V, fSCLK = 4.8MHz, CLOAD = 50pF, VREF = +4.096V, TA = +25°C, unless otherwise noted.)
DIFFERENTIAL NONLINEARITY (DNL)
vs. CODE
MAX11101 toc02
OUTPUT CODE (DECIMAL)
DNL (LSB)
122888192
14336102406144
4096
2048
-0.4
-0.3
-0.2
-0.1
0
0.1
0.2
0.3
0.4
0.5
-1.5
0 16384
INTEGRAL NONLINEARITY (INL)
vs. CODE
MAX11101 toc01
OUTPUT CODE (DECIMAL)
INL (LSB)
122888192
14336102406144
4096
2048
-0.4
-0.3
-0.2
-0.1
0
0.1
0.2
0.3
0.4
0.5
-0.5
0 16384
INL AND DNL
vs. ANALOG SUPPLY VOLTAGE
MAX11101 toc03
VAVDD (V)
INL AND DNL (LSB)
5.155.054.954.85
0.5
-0.5
4.75 5.25
MAX INL
MIN INL
MIN DNL
-0.3
-0.1
0.1
0.3
MAX DNL
-140
-100
-120
-60
-80
-20
-40
0
04020 60 8010 5030 70 90 100
MAX11101 FFT
MAX11101 toc05
FREQUENCY (kHz)
MAGNITUDE (dB)
90
0
0.1 100101
SINAD VS. FREQUENCY
30
10
70
50
100
40
20
80
60
MAX11101 toc06
FREQUENCY (kHz)
SINAD (dB)
fSAMPLE = 200kHz
INL AND DNL vs. TEMPERATURE
MAX11101 toc04
TEMPERATURE (°C)
INL AND DNL (LSB)
603510-15-40 85
MAX INL
MAX DNL
MIN INL
MIN DNL
-0.3
-0.1
0.1
0.3
0.5
-0.5
110
0
10
SFDR VS. FREQUENCY
MAX11101 toc07
FREQUENCY (kHz)
SFDR (dB)
20
30
40
50
60
70
80
90
100
0.1 100101
fSAMPLE = 200kHz
0
-110
-100
THD VS. FREQUENCY
MAX11101 toc08
FREQUENCY (kHz)
THD (dB)
-90
-80
-70
-60
-50
-40
-30
-20
-10
0.1 100101
fSAMPLE = 200kHz
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MAX11101
14-Bit, +5V, 200ksps ADC with 10µA Shutdown
Typical Operating Characteristics (continued)
(VAVDD = VDVDD = 5V, fSCLK = 4.8MHz, CLOAD = 50pF, VREF = +4.096V, TA = +25°C, unless otherwise noted.)
SUPPLY CURRENT
vs. TEMPERATURE
MAX11101 toc11
SUPPLY CURRENT (mA)
0.5
1.0
1.5
2.0
2.5
0
TEMPERATURE (°C)
603510-15-40 85
IDVDD
IAVDD
ANALOG SUPPLY CURRENT
vs. SUPPLY VOLTAGE
MAX11101 toc10
IAVDD (mA)
1.82
1.84
1.86
1.88
1.90
1.80
VAVDD (V)
5.155.054.954.854.75 5.25
0
150
100
50
200
250
300
350
400
450
-40 10-15 35 60 85
SHUTDOWN SUPPLY CURRENT
VS. TEMPERATURE
MAX11101 toc13
TEMPERATURE (°C)
ISHDN (nA)
VAVDD = VDVDD = +5V
OFFSET ERROR
vs. ANALOG SUPPLY VOLTAGE
MAX11101 toc14
OFFSET ERROR (µV)
-300
-100
100
300
500
-500
VAVDD (V)
5.155.054.954.854.75 5.25
0
4
2
8
6
12
10
14
18
16
20
4.75 4.85 4.95 5.05 5.15 5.25
MAX11101 toc12
SUPPLY VOLTAGE (V)
ISHDN (nA)
SHUTDOWN SUPPLY CURRENT
VS. SUPPLY VOLTAGE
SAMPLE RATE (ksps)
10010
0.0010
0.0100
0.1000
1.0000
10.0000
0.0001
1 1000
SUPPLY CURRENT vs. SAMPLE RATE
MAX11101 toc09
SUPPLY CURRENT (mA)
IAVDD
IDVDD
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MAX11101
14-Bit, +5V, 200ksps ADC with 10µA Shutdown
Typical Operating Characteristics (continued)
(VAVDD = VDVDD = 5V, fSCLK = 4.8MHz, CLOAD = 50pF, VREF = +4.096V, TA = +25°C, unless otherwise noted.)
SIGNAL-TO-NOISE RATIO (SNR) AND
SIGNAL-TO-NOISE AND DISTORTION
RATIO (SINAD) vs. TEMPERATURE
MAX11100 toc18
SNR AND SINAD (dB)
84.7
84.9
85.1
85.3
85.5
84.5
TEMPERATURE (°C)
603510-15-40 85
SINAD
SNR
fIN = 1kHz
GAIN ERROR
vs. ANALOG SUPPLY VOLTAGE
MAX11101 toc16
GAIN ERROR (%FS)
-0.006
-0.002
0.002
0.006
0.010
-0.010
VAVDD (V)
5.155.054.954.854.75 5.25
GAIN ERROR vs. TEMPERATURE
MAX11101 toc17
GAIN ERROR (%FS)
-0.006
-0.002
0.002
0.006
0.010
-0.010
TEMPERATURE (°C)
603510-15-40 85
OFFSET ERROR vs. TEMPERATURE
MAX11101 toc15
OFFSET ERROR (µV)
-300
-100
100
300
500
-500
TEMPERATURE (°C)
603510-15-40 85
, MAXI/VI [MAXIM [MAXI/VI
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MAX11101
14-Bit, +5V, 200ksps ADC with 10µA Shutdown
Pin Configurations
Pin Description
PIN NAME FUNCTION
WLP µMAX
A1, B2 6 REF External Reference Voltage Input. Sets the analog voltage range. Bypass to AGND with a 4.7FF
capacitor.
A2 7 AVDD Analog +5V Supply Voltage. Bypass to AGND with a 0.1FF capacitor.
A3, B1,
C2 4, 8 AGND Analog Ground
A4 10 SCLK Serial Clock Input. SCLK drives the conversion process and clocks out data at data rates up to
4.8MHz.
B3 2 DGND Digital Ground
B4 9 CS
Active Low Chip Select Input. Forcing CS high places the MAX11101 in shutdown with a typical
current of 0.1FA. A high-to-low transition on CS activates normal operating mode and initiates a
conversion.
C1 5 AIN Analog Input
C3 3 DVDD Digital Supply Voltage. Bypass to DGND with a 0.1FF capacitor.
C4 1 DOUT Serial Data Output. Data changes state on SCLK’s falling edge. DOUT is high impedance when
CS is high.
MAX11101
MAX11101
TOP VIEW
+
µMAX
2DGND
1DOUT
DVDD 3
AGND
AIN
CS
SCLK
AGND
AVDD
REF
4
5
9
10
8
7
6
TOP VIEW
(BUMP SIDE DOWN)
WLP
+
1 2 34
A
B
C
DOUTAIN
CSAGND
SCLKREF
AGND DVDD
REFDGND
AVDD AGND
[MAXI/VI
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MAX11101
14-Bit, +5V, 200ksps ADC with 10µA Shutdown
Detailed Description
The MAX11101 includes an input track-and-hold (T/H)
and successive-approximation register (SAR) circuitry to
convert an analog input signal to a digital 14-bit output.
Figure 4 shows the MAX11101 in its simplest configura-
tion. The serial interface requires only three digital lines
(SCLK, CS, and DOUT) and provides an easy interface
to microprocessors (FPs).
The MAX11101 has two power modes: normal and shut-
down. Driving CS high places the MAX11101 in shut-
down, reducing the supply current to 0.1FA (typ), while
pulling CS low places the MAX11101 in normal operating
mode. Falling edges on CS initiate conversions that are
driven by SCLK. The conversion result is available at
DOUT in unipolar serial format. The serial data stream
consists of eight zeros followed by the data bits (MSB
first). Figure 3 shows the interface-timing diagram.
Analog Input
Figure 5 illustrates the input sampling architecture of the
ADC. The voltage applied at REF sets the full-scale input
voltage.
Track-and-Hold (T/H)
In track mode, the analog signal is acquired on the inter-
nal hold capacitor. In hold mode, the T/H switches open
and the capacitive DAC samples the analog input.
Figure 1. Load Circuits for DOUT Enable Time and SCLK to
DOUT Delay Time
Figure 2. Load Circuits for DOUT Disable Time
Figure 3. Detailed Serial Interface Timing
DOUT
a) VOL TO VOH b) HIGH-Z TO VOL AND VOH TO VOL
DOUT
1mA
1mA
DGND DGND
CLOAD = 50pF CLOAD = 50pF
VDD
DOUT
a) VOH TO HIGH-Z b) VOL TO HIGH-Z
DOUT
1mA
1mA
DGND DGND
CLOAD = 50pF CLOAD = 50pF
VDD
SCLK
DOUT
tCSS
tCH
tCL
tDV
tCSH
tCSW
tTR
tDO
tCP
CS
[MAXIM ’VMXI/w
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MAX11101
14-Bit, +5V, 200ksps ADC with 10µA Shutdown
During the acquisition, the analog input (AIN) charges
capacitor CDAC. The acquisition interval ends on the
falling edge of the sixth clock cycle (Figure 6). At this
instant, the T/H switches open. The retained charge on
CDAC represents a sample of the input.
In hold mode, the capacitive digital-to-analog converter
(DAC) adjusts during the remainder of the conversion
cycle to restore node ZERO to zero within the limits of
14-bit resolution. At the end of the conversion, force CS
high and then low to reset the input side of the CDAC
switches back to AIN, and charge CDAC to the input
signal again.
The time required for the T/H to acquire an input signal is
a function of how quickly its input capacitance is charged.
If the input signal’s source impedance is high, the acqui-
sition time lengthens and more time must be allowed
between conversions. The acquisition time (tACQ) is the
maximum time the device takes to acquire the signal. Use
the following formula to calculate acquisition time:
tACQ = 11(RS + RIN) x 35pF
where RIN = 800I, RS = the input signal’s source
impedance, and tACQ is never less than 1.1Fs. A source
impedance less than 1kI does not significantly affect the
ADC’s performance.
To improve the input signal bandwidth under AC condi-
tions, drive AIN with a wideband buffer (> 4MHz) that
can drive the ADC’s input capacitance and settle quickly.
Input Bandwidth
The ADC’s input tracking circuitry has a 4MHz small-
signal bandwidth, so it is possible to digitize high-speed
transient events and measure periodic signals with
bandwidths exceeding the ADC’s sampling rate by using
undersampling techniques. To avoid aliasing of unwant-
ed high-frequency signals into the frequency band of
interest, use anti-alias filtering.
Analog Input Protection
Internal protection diodes, which clamp the analog input to
AVDD and/or AGND, allow the input to swing from VAGND -
0.3V to VAVDD + 0.3V, without damaging the device.
If the analog input exceeds 300mV beyond the supplies,
limit the input current to 10mA.
Digital Interface
Initialization After Power-Up
and Starting a Conversion
The digital interface consists of two inputs, SCLK and
CS, and one output, DOUT. A logic-high on CS places
the MAX11101 in shutdown (autoshutdown) and places
DOUT in a high-impedance state. A logic-low on CS
places the MAX11101 in the fully powered mode.
To start a conversion, pull CS low. A falling edge on CS
initiates an acquisition. SCLK drives the A/D conversion
and shifts out the conversion results (MSB first) at DOUT.
Timing and Control
Conversion-start and data-read operations are con-
trolled by the CS and SCLK digital inputs (Figure 6
and Figure 7). Ensure that the duty cycle on SCLK is
between 40% and 60% at 4.8MHz (the maximum clock
frequency). For lower clock frequencies, ensure that
the minimum high and low times are at least 65ns.
Conversions with SCLK rates less than 100kHz may
result in reduced accuracy due to leakage.
Note: Coupling between SCLK and the analog inputs
(AIN and REF) may result in an offset. Variations in
frequency, duty cycle, or other aspects of the clock
signal’s shape result in changing offset.
Figure 4. Typical Operating Circuit
Figure 5. Equivalent Input Circuit
SCLK
DOUT
AGND
DGND
AIN
REF
AVDD
DVDD
DOUT
SCLK
CS
AIN
VREF
+5V
+5V
4.7µF
0.1µF
0.1µF
GND
MAX11101
CS
CDAC 32pF RIN
800Ω
HOLD
HOLD
CSWITCH
3pF
AIN
REF
GND
ZERO
CAPACITIVE DAC
AUTOZERO
RAIL
TRACK
TRACK
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���������������������������������������������������������������� Maxim Integrated Products 11
MAX11101
14-Bit, +5V, 200ksps ADC with 10µA Shutdown
A CS falling edge initiates an acquisition sequence. The
analog input is stored in the capacitive DAC, DOUT
changes from high impedance to logic-low, and the ADC
begins to convert after the sixth clock cycle. SCLK drives
the conversion process and shifts out the conversion
result on DOUT.
SCLK begins shifting out the data (MSB first) after the fall-
ing edge of the 8th SCLK pulse. Twenty-four falling clock
edges are needed to shift out the eight leading zeros, 14
data bits, and 2 sub-bits (S1 and S0). Extra clock pulses
occurring after the conversion result has been clocked
out, and prior to the rising edge of CS, produce trail-
ing zeros at DOUT and have no effect on the converter
operation.
Force CS high after reading the conversion’s LSB to
reset the internal registers and place the MAX11101 in
shutdown. For maximum throughput, force CS low again
to initiate the next conversion immediately after the speci-
fied minimum time (tCSW).
Note: Forcing CS high in the middle of a conversion
immediately aborts the conversion and places the
MAX11101 in shutdown.
Figure 6. External Timing Diagram
Figure 7. Shutdown Sequence
CS
SCLK 2016 24
1214 86
DOUT D13 D12 D11 D10 D9 D8 D7 S1 S0D6 D3 D2 D1 D0D5 D4
tCSH
tTR
tDO
tACQ
tCSS
tCH
tCL
tDN
COMPLETE CONVERSION SEQUENCE
CONVERSION 0 CONVERSION 1
POWERED UPPOWERED UP POWERED DOWN
DOUT
CS
���������������������������������������������������������������� Maxim Integrated Products 12
MAX11101
14-Bit, +5V, 200ksps ADC with 10µA Shutdown
Output Coding and Transfer Function
The data output from the MAX11101 is binary and Figure 8
depicts the nominal transfer function. Code transitions
occur halfway between successive-integer LSB values
(VREF = 4.096V and 1 LSB = 250FV or 4.096V/16384).
Applications Information
External Reference
The MAX11101 requires an external reference with a volt-
age range between 3.8V and AVDD. Connect the exter-
nal reference directly to REF. Bypass REF to AGND with
a 4.7FF capacitor. When not using a low-ESR bypass
capacitor, use a 0.1FF ceramic capacitor in parallel with
the 4.7FF capacitor. Noise on the reference degrades
conversion accuracy.
The input impedance at REF is 40I for DC currents.
During a conversion, the external reference at REF must
deliver 100FA of DC load current and have an output
impedance of 10I or less.
For optimal performance, buffer the reference through
an op amp and bypass the REF input. Consider the
MAX11101’s equivalent input noise (80FVRMS) when
choosing a reference.
Input Buffer
Most applications require an input buffer amplifier to
achieve 14-bit accuracy. If the input signal is multi-
plexed, switch the input channel immediately after acqui-
sition, rather than near the end of or after a conversion
(Figure 9). This allows the maximum time for the input
buffer amplifier to respond to a large step change in the
input signal. The input amplifier must have a slew rate of
at least 2V/Fs to complete the required output voltage
change before the beginning of the acquisition time.
At the beginning of the acquisition, the internal sampling
capacitor array connects to AIN (the amplifier output),
causing some output disturbance. Ensure that the sampled
voltage has settled before the end of the acquisition time.
Digital Noise
Digital noise can couple to AIN and REF. The conversion
clock (SCLK) and other digital signals active during input
acquisition contribute noise to the conversion result. Noise
signals synchronous with the sampling interval result in
an effective input offset. Asynchronous signals produce
random noise on the input, whose high-frequency compo-
nents may be aliased into the frequency band of interest.
Minimize noise by presenting a low impedance (at the
frequencies contained in the noise signal) at the inputs.
This requires bypassing AIN to AGND, or buffering the
input with an amplifier that has a small-signal bandwidth
of several MHz, or preferably both. AIN has about 4MHz
of bandwidth.
Distortion
Avoid degrading dynamic performance by choosing an
amplifier with distortion much less than the MAX11101’s
total harmonic distortion (THD = -99dB at 1kHz) at
frequencies of interest. If the chosen amplifier has
insufficient common-mode rejection, which results in
degraded THD performance, use the inverting configu-
ration (positive input grounded) to eliminate errors from
this source. Low temperature-coefficient, gain-setting
resistors reduce linearity errors caused by resistance
changes due to self-heating. To reduce linearity errors
due to finite amplifier gain, use amplifier circuits with suf-
ficient loop gain at the frequencies of interest.
DC Accuracy
To improve DC accuracy, choose a buffer with an offset
much less than the MAX11101’s offset (1mV (max) for
+5V supply), or whose offset can be trimmed while main-
taining stability over the required temperature range.
Figure 8. Unipolar Transfer Function, Full Scale (FS) = VREF,
Zero Scale (ZS) = GND
OUTPUT CODE
FULL-SCALE
TRANSITION
11 . . . 111
11 . . . 110
11 . . . 101
00 . . . 011
00 . . . 010
00 . . . 001
00 . . . 000
123
0FS
FS - 3/2 LSB
FS = VREF
INPUT VOLTAGE (LSB)
1LSB = VREF
16384
[MAXIM + i E [MAXI/VI
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MAX11101
14-Bit, +5V, 200ksps ADC with 10µA Shutdown
Figure 9. Change Multiplexer Input Near Beginning of Conversion to Allow Time for Slewing and Settling
Serial Interfaces
The MAX11101’s interface is fully compatible with SPI,
QSPI, and MICROWIRE standard serial interfaces.
If a serial interface is available, establish the CPU’s
serial interface as master, so that the CPU generates the
serial clock for the MAX11101. Select a clock frequency
between 100kHz and 4.8MHz:
1) Use a general-purpose I/O line on the CPU to pull CS
low.
2) Activate SCLK for a minimum of 24 clock cycles. The
serial data stream of eight leading zeros followed by
the MSB of the conversion result begins at the fall-
ing edge of CS. DOUT transitions on SCLK’s falling
edge and the output is available in MSB-first format.
Observe the SCLK to DOUT valid timing characteris-
tic. Clock data into the FP on SCLK’s rising edge.
3) Pull CS high at or after the 24th falling clock edge. If
CS remains low, trailing zeros are clocked out after
the 2 sub-bits, S1 and S0.
4) With CS high, wait at least 50ns (tCSW) before starting a
new conversion by pulling CS low. A conversion can be
aborted by pulling CS high before the conversion ends.
Wait at least 50ns before starting a new conversion.
Data can be output in three 8-bit sequences or continu-
ously. The bytes contain the results of the conversion pad-
ded with eight leading zeros before the MSB. If the serial
clock has not been idled after the sub-bits (S1 and S0) and
CS has been kept low, DOUT sends trailing zeros.
A0
A1
CLK
CHANGE MUX INPUT HERE
CONVERSION
IN1
A0 A1
IN2
IN3
IN4
OUT
ACQUISITION
4-TO-1
MUX
AIN
CS
MAX11101
CS
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MAX11101
14-Bit, +5V, 200ksps ADC with 10µA Shutdown
SPI and MICROWIRE Interfaces
When using the SPI (Figure 10a) or MICROWIRE (Figure 10b)
interfaces, set CPOL = 0 and CPHA = 0. Conversion
begins with a falling edge on CS (Figure 10c). Three con-
secutive 8-bit readings are necessary to obtain the entire
14-bit result from the ADC. DOUT data transitions on
the serial clock’s falling edge. The first 8-bit data stream
contains all leading zeros. The second 8-bit data stream
contains the MSB through D6. The third 8-bit data stream
contains D5 through D0 followed by S1 and S0.
Figure 10a. SPI Connections
Figure 10b. MICROWIRE Connections
Figure 10c. SPI/MICROWIRE Interface Timing Sequence (CPOL = CPHA =0)
SCLK
DOUT
I/O
SCK
MISO
SPI VDD
SS
MAX11101
CS
DOUT*
CS
SCLK
1ST BYTE READ 2ND BYTE READ
*WHEN CS IS HIGH, DOUT = HIGH-Z
MSB
HIGH-Z
3RD BYTE READ
LSB
S1 S0D5 D4 D3 D2 D1 D0
2420
1612
8
641
D13 D12 D11 D10 D9 D8 D7 D6 D5
000000 00
MAX11101
CS
MICROWIRE
SCLK
DOUT
I/O
SK
SI
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MAX11101
14-Bit, +5V, 200ksps ADC with 10µA Shutdown
QSPI Interface
Using the high-speed QSPI interface with CPOL = 0 and
CPHA = 0, the MAX11101 supports a maximum fSCLK
of 4.8MHz. Figure 11a shows the MAX11101 connected
to a QSPI master and Figure 11b shows the associated
interface timing.
PIC16 with SSP Module and PIC17 Interface
The MAX11101 is compatible with a PIC16/PIC17 micro-
controller (FC) using the synchronous serial-port (SSP)
module.
To establish SPI communication, connect the controller
as shown in Figure 12a. Configure the PIC16/PIC17 as
system master, by initializing its synchronous serial-port
control register (SSPCON) and synchronous serial-port
status register (SSPSTAT) to the bit patterns shown in
Table 1 and Table 2.
In SPI mode, the PIC16/PIC17 FC allows 8 bits of data
to be synchronously transmitted and received simulta-
neously. Three consecutive 8-bit readings (Figure 12b)
are necessary to obtain the entire 14-bit result from the
ADC. DOUT data transitions on the serial clock’s falling
edge and is clocked into the FC on SCLK’s rising edge.
The first 8-bit data stream contains all zeros. The second
8-bit data stream contains the MSB through D6. The third
8-bit data stream contains bits D5 through D0 followed
by S1 and S0.
Figure 11a. QSPI Connections
Figure 11b. QSPI Interface Timing Sequence (CPOL = CPHA = 0)
Figure 12a. SPI Interface Connection for a PIC16/PIC17
CS
QSPI
SCLK
DOUT
CS
SCK
MISO
VDD
SS
MAX11101
DOUT*
CS
SCLK
*WHEN CS IS HIGH, DOUT = HIGH-Z
MSB
2016
D13 D12 D11 D10 D9 D8 D7 HIGH-Z
S1 S0
24
1214 86
D6 D3 D2 D1
LSB
D5 D4
END OF
ACQUISITION D0
SCK
SDI
GND
PIC16/17
I/O
SCLK
DOUT
CS
VDD VDD
MAX11101
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MAX11101
14-Bit, +5V, 200ksps ADC with 10µA Shutdown
Table 1. Detailed SSPCON Register Contents
Table 2. Detailed SSPSTAT Register Contents
Figure 12b. SPI Interface Timing with PIC16/PIC17 in Master Mode (CKE = 1, CKP = 0, SMP = 0, SSPM3 - SSPM0 =0001)
CONTROL BIT MAX11101
SETTINGS SYNCHRONOUS SERIAL-PORT CONTROL REGISTER (SSPCON)
WCOL BIT 7 XWrite Collision Detection Bit
SSPOV BIT 6 XReceive Overflow Detect Bit
SSPEN BIT 5 1
Synchronous Serial-Port Enable Bit:
0: Disables serial port and configures these pins as I/O port pins.
1: Enables serial port and configures SCK, SDO, and SCI pins as serial port pins.
CKP BIT 4 0Clock Polarity Select Bit. CKP = 0 for SPI master mode selection.
SSPM3 BIT 3 0
Synchronous Serial-Port Mode Select Bit. Sets SPI master mode and selects fCLK = fOSC/16
SSPM2 BIT 2 0
SSPM1 BIT 1 0
SSPM0 BIT 0 1
CONTROL BIT MAX11101
SETTINGS SYNCHRONOUS SERIAL-PORT CONTROL REGISTER (SSPSTAT)
SMP BIT 7 0SPI Data Input Sample Phase. Input data is sampled at the middle of the data output time.
CKE BIT 6 1SPI Clock Edge Select Bit. Data will be transmitted on the rising edge of the serial clock.
D/A BIT 5 XData Address Bit
PBIT 4 XSTOP Bit
SBIT 3 XSTART Bit
R/W BIT 2 XRead/Write Bit Information
UA BIT 1 XUpdate Address
BF BIT 0 XBuffer Full Status Bit
DOUT*
CS
SCLK
1ST BYTE READ 2ND BYTE READ
*WHEN CS IS HIGH, DOUT = HIGH-Z
MSB
HIGH-Z
3RD BYTE READ
LSB
S1 S0D5 D4 D3 D2 D1 D0
2420
1612
D13 D12 D11 D10 D9 D8 D7 D6
000000 00 D5
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MAX11101
14-Bit, +5V, 200ksps ADC with 10µA Shutdown
Definitions
Integral Nonlinearity
Integral nonlinearity (INL) is the deviation of the values
on an actual transfer function from a straight line. This
straight line can be either a best-fit straight line fit or a line
drawn between the end points of the transfer function,
once offset and gain errors have been nullified. The static
linearity parameters for the MAX11101 are measured
using the endpoint method.
Differential Nonlinearity
Differential nonlinearity (DNL) is the difference between
an actual step width and the ideal value of 1 LSB. A DNL
error specification of 1 LSB guarantees no missing codes
and a monotonic transfer function.
Aperture Definitions
Aperture jitter (tAJ) is the sample-to-sample variation in
the time between samples. Aperture delay (tAD) is the
time between the falling edge of the sampling clock and
the instant when the actual sample is taken.
Signal-to-Noise Ratio
For a waveform perfectly reconstructed from digital
samples, signal-to-noise ratio (SNR) is the ratio of the
full-scale analog input (RMS value) to the RMS quantiza-
tion error (residual error). The ideal, theoretical minimum
analog-to-digital noise is caused by quantization noise
error only and results directly from the ADCs resolution
(N bits):
SNR = (6.02 x N + 1.76)dB
In reality, there are other noise sources besides quantiza-
tion noise: thermal noise, reference noise, clock jitter, etc.
SNR is computed by taking the ratio of the RMS signal to
the RMS noise, which includes all spectral components
minus the fundamental, the first five harmonics, and the
DC offset.
Signal-to-Noise Plus Distortion
Signal-to-noise plus distortion (SINAD) is the ratio of the
fundamental input frequency’s RMS amplitude to the
RMS equivalent of all the other ADC output signals.
( )
RMS
RMS
Signal
SINAD(dB) 20 log Noise Distortion

= ×

+


Effective Number of Bits
Effective number of bits (ENOB) indicate the global
accuracy of an ADC at a specific input frequency and
sampling rate. An ideal ADC error consists of quantiza-
tion noise only. With an input range equal to the full-scale
range of the ADC, calculate the effective number of bits
as follows:
ENOB = (SINAD – 1.76)/6.02
Figure 13 shows the effective number of bits as a function
of the MAX11101’s input frequency.
Total Harmonic Distortion
Total harmonic distortion (THD) is the ratio of the RMS
sum of the first five harmonics of the input signal to the
fundamental itself. This is expressed as:
2222
2345
VVVV
THD 20 log V1

+++

= ×



where V1 is the fundamental amplitude and V2 through
V5 are the 2nd- through 5th-order harmonics.
Spurious-Free Dynamic Range
Spurious-free dynamic range (SFDR) is the ratio of the
RMS amplitude of the fundamental (maximum signal
component) to the RMS value of the next largest fre-
quency component.
Figure 13. Effective Number of Bits vs. Input Frequency
0.1 10 100
MAX11101 Fig13
INPUT FREQUENCY (kHz)
EFFECTIVE NUMBER OF BITS
1
14
0
2
4
6
8
12
10
fSAMPLE = 200kHz
[MAXIM [MAXI/VI
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MAX11101
14-Bit, +5V, 200ksps ADC with 10µA Shutdown
Supplies, Layout, Grounding and Bypassing
Use PCBs with separate analog and digital ground
planes. Do not use wire-wrap boards. Connect the two
ground planes together at the MAX11101. Isolate the
digital supply from the analog with a low-value resistor
(10I) or ferrite bead when the analog and digital sup-
plies come from the same source (Figure 14).
Constraints on sequencing the power supplies and
inputs are as follows:
U Apply AGND before DGND.
U Apply AIN and REF after AVDD and AGND are present.
U DVDD is independent of the supply sequencing.
Ensure that digital return currents do not pass through
the analog ground and that return-current paths are
low impedance. A 5mA current flowing through a PCB
ground trace impedance of only 0.05I creates an error
voltage of about 250FV, 1 LSB error with a 4V full-scale
system.
The board layout should ensure that digital and analog
signal lines are kept separate. Do not run analog and dig-
ital (especially the SCLK and DOUT) lines parallel to one
another. If one must cross another, do so at right angles.
The ADCs high-speed comparator is sensitive to high-
frequency noise on the AVDD power supply. Bypass an
excessively noisy supply to the analog ground plane with
a 0.1FF capacitor in parallel with a 1FF to 10FF low-ESR
capacitor. Keep capacitor leads short for best supply-
noise rejection.
Ordering Information
Chip Information
PROCESS: BiCMOS
Package Information
For the latest package outline information and land patterns
(footprints), go to www.maxim-ic.com/packages. Note that a
“+”, “#”, or “-” in the package code indicates RoHS status only.
Package drawings may show a different suffix character, but
the drawing pertains to the package regardless of RoHS status.
Figure 14. Powering AVDD and DVDD from a Single Supply
+Denotes a lead(Pb)-free/RoHS-compliant package.
PART TEMP RANGE PIN-PACKAGE
MAX11101EUB+ -40NC to +85NC 10 FMAX
MAX11101EWC+ -40NC to +85NC12 WLP
PACKAGE
TYPE
PACKAGE
CODE
OUTLINE
NO.
LAND
PATTERN NO.
10 FMAX U10+2 21-0061 90-0330
12 WLP W121A2+1 21-0009
Refer to
Application
Note 1891
SCLK
DOUT
AGND
DGND
AIN
10Ω
REF
AVDD
DVDD
DOUT
SCLK
CS
AIN
VREF
+5V
4.7µF
0.1µF
0.1µF
GND
MAX11101
CS
MAX11101
14-Bit, +5V, 200ksps ADC with 10µA Shutdown
Maxim cannot assume responsibility for use of any circuitry other than circuitry entirely embodied in a Maxim product. No circuit patent licenses are implied.
Maxim reserves the right to change the circuitry and specifications without notice at any time. The parametric values (min and max limits) shown in the Electrical
Characteristics table are guaranteed. Other parametric values quoted in this data sheet are provided for guidance.
Maxim Integrated Products, 120 San Gabriel Drive, Sunnyvale, CA 94086 408-737-7600 19
© 2012 Maxim Integrated Products Maxim is a registered trademark of Maxim Integrated Products, Inc.
Revision History
REVISION
NUMBER
REVISION
DATE DESCRIPTION PAGES
CHANGED
0 9/11 Initial release —
1 1/12 Revised the Absolute Maximum Ratings and Electrical Characteristics. 2–4