Datenblatt für SY89312V von Microchip Technology

www.micrel.com
SY89312V
3.3V/5V, 4GHz PECL/ECL
÷2 Clock Generator
Precision Edge®
Precision Edge is a registered trademark of Micrel, Inc.
Micrel Inc. • 2180 Fortune Drive • San Jose, CA 95131 • USA • tel +1 (408) 944-0800 • fax + 1 (408) 474-1000 • http://www.micrel.com
June 25, 2013
Revision 2.0
hbwhelp@micrel.com or (408) 955-1690
General Description
The SY89312V is an integrated
÷
2
divider with differential
clock inputs. It is functionally equivalent to the
SY100EP32V but in an ultra-small 8-pin QFN package
that features a 70% smaller footprint.
The VBB pin, an internally generated voltage supply, is
available for this device only. For single-ended input
conditions, the unused differential input is connected to VBB
as a switching reference voltage. VBB can also bias AC-
coupled inputs. When used, decouple VBB and VCC via a
0.01
µ
F
capacitor and limit current sourcing or sinking to
0.5mA. When not in use, VBB should be left open.
The reset pin is asynchronous and is asserted when it is
high. Upon power-up, the internal flip-flops will be in a
random state; the reset allows for the synchronous use of
multiple SY89312Vs in a system.
Datasheets and support documentation are available on
Micrel’s web site at: www.micrel.com.
Precision Edge®
Features
• Guaranteed AC performance over temperature and
voltage:
• >4GHz fMAX input
• <160ps tr/tf
• <440ps tpd
• 3.3V and 5V power supply operation
• 100k ECL/PECL-compatible I/O
• Internal 75KΩ input pull-down resistors
• Wide operating temperature range: –40°C to +85°C
• Available in ultra-small 8-pin 2mm × 2mm QFN package
Truth Table(1)
CLK /CLK RESET Q /Q
X X H L H
L F F
Note:
1. F = Divide by 2 function.
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Ordering Information
Part Number Package Type Operating Range Package Marking Lead Finish
SY89312VMGTR
(2)
8-pin 2mm × 2mm QFN Industrial 312 with Pb-Free Bar Line Indicator Pb-Free NiPdAu
Note:
2. Pb-Free package is recommended for new designs.
Pin Configuration
8-Pin 2mm × 2mm QFN
Pin Description
Pin Number
Pin Name
Type
Pin Function
2, 3 CLK, /CLK 100K
ECL/PECL
Input
Differential PECL/ECL Input: Internal 75kΩ pull-down resistor. If left open, pin
defaults LOW (see Input Interface Applications section for single-ended inputs).
7, 6 Q, /Q 100K
ECL/PECL
Output
Differential PECL/ECL Output: Output CLK input divided by 2 (see Output
Interface Applications section for recommendations on terminations).
8 VCC Positive Power
Supply Positive Power Supply: Bypass with 0.1
F//0.01F low ES
citors.
5 VEE, ePad Negative
Power Supply Negative Power Supply: VEE and exposed pad (ePad) must be tied to most
negative supply. For PECL/LVPECL connect to ground.
4 VBB Reference
Voltage
Output
Bias Reference Voltage: VCC–1.4V. Used as reference voltage for single- ended
inputs or AC-coupling to the CLK, /CLK inputs. Maximum sink/source is ±0.5mA
(see Input Interface Applications section).
1 Reset 100k
ECL/PECL
Input Single-Ended Input: PECL/ECL asynchronous reset.
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Absolute Maximum Ratings(3)
Supply Voltage (VCC − VEE) ..................................... +6.0V
Input Voltage (VIN) ............................................ −0.5V to VCC
LVPECL Output Current (IOUT)
Continuous ............................................................ 50mA
Surge .................................................................. 100mA
Current (VBB)
Source or Sink on VBB(6) ..................................... ±1.5mA
Lead Temperature (soldering, 20s) ............................ 260°C
Storage Temperature (Ts) ......................... −65°C to +150°C
Operating Ratings(4)
Supply Voltage (VCC − VEE) ......................... +3.0 to +3.6V
Ambient Temperature (TA) .......................... –40°C to +85°C
Package Thermal Resistance(5)
QFN (θJA)
Still Air ......................................................... 93°C/W
500lfpm ....................................................... 87°C/W
QFN (ψJB)
Junction-to-Board ........................................ 56°C/W
PECL/ECL (100K) DC Electrical Characteristics
VCC = +3.3V ±10% or +5V ±10% and VEE = 0V; VCC = 0V and VEE = –3.3V ±10% or –5V ±10%; RL = 50Ω to VCC – 2V;
TA = –40°C to +85°C unless otherwise stated.
Symbol Parameter Condition Min. Typ. Max. Units
IEE Power Supply Current
Maximum VCC, no load
—
30
42
mA
VOH Output HIGH Voltage VCC – 1.145
— VCC – 0.895
V
VOL Output LOW Voltage VCC – 1.945
— VCC – 1.695
V
VIH Input HIGH Voltage VCC – 1.225
— VCC – 0.88
V
VIL Input LOW Voltage VCC – 1.945
— VCC – 1.625
V
VIHCMR Input HIGH Voltage Common
Mode Range(7) VEE + 2.0 — VCC V
VBB Bias Voltage VCC – 1.525
VCC – 1.425
VCC – 1.325
V
IIH Input HIGH Current — — 150
∝
A
IIL Input LOW Current CLK 0.5 — —
∝
A
Input LOW Current /CLK –150 — —
Notes:
3. Permanent device damage may occur if absolute maximum ratings are exceeded. This is a stress rating only and functional operation is not implied
at conditions other than those detailed in the operational sections of this data sheet. Exposure to absolute maximum rating conditions for extended
periods may affect device reliability.
4. The data sheet limits are not guaranteed if the device is operated beyond the operating ratings.
5. Package thermal resistance assumes exposed pad is soldered (or equivalent) to the devices most negative potential on the PCB.
6. Due to the limited drive capability use for input of the same package only.
7. VIHCMR (minimum) varies 1:1 with VEE, (maximum) varies 1:1 with VCC.
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AC Electrical Characteristics(8)
PECL: VCC = +3.3V ±10% or +5V ±10% and VEE = GND; ECL: VEE = –3.3V ±10% or –5V ±10% and VCC = GND; RL = 50Ω to VCC – 2V;
TA = –40°C to +85°C unless otherwise stated.
Symbol Parameter Condition Min. Typ. Max. Units
fMAX Maximum Input Frequency 4 — — GHz
tpd Propagation Delay to Output
Differential RESET, CLK ➝ Q, /Q 250 275 440 ps
tRR Set/Reset Recovery 200 100 — ps
tPW Minimum Pulse Width RESET 550 200 — ps
tJITTER Cycle-to-Cycle RMS Jitter — — 1 psRMS
VPP Input Voltage Swing (Differential) 150 800 1200 mV
tr, tf Output Rise/Fall Times Q, /Q (20% to 80%) 50 100 160 ps
Note:
8. Measured using a 750mV source, 50% duty cycle clock source
Timing Diagram
Input Interface Applications
Figure 1. Single-Ended LVPECL Input (Terminating Unused Input)
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LVPECL Output Interface Applications
Figure 2. Parallel Thevenin-Equivalent Termination
Figure 3. Three Resistor “Y Termination”
Figure 4. Terminating Unused I/O
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Package Information(9, 10, 11, 12)
8-Pin 2mm × 2mm QFN Package
Note:
9. Package information is correct as of the publication date. For updates and most current information, go to www.micrel.com.
10. Package meets Level 1 qualifications.
11. All parts are dry packaged before shipment.
12. Exposed pads must be soldered to the most negative plane, equivalent to device VBB, for proper thermal management.
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June 25, 2013
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TEL +1 (408) 944-0800 FAX +1 (408) 474-1000 WEB http://www.micrel.com
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