Datenblatt für TDA7498L von STMicroelectronics

‘ ’I monugmemed
PowerSSO-36
exposed pad up
Features
• 80 W + 80 W output power at THD = 10% with RL = 6 Ω and VCC = 32 V
• 70 W + 70 W output power at THD = 10% with RL = 8 Ω and VCC = 34 V
• Wide-range single-supply operation (14 - 36 V)
• High efficiency (η = 90%)
• Four selectable, fixed gain settings of nominally 25.6 dB, 31.6 dB, 35.1 dB and
37.6 dB
• Differential inputs minimize common-mode noise
• Standby and mute features
• Short-circuit protection
• Thermal overload protection
• Externally synchronizable
Description
The TDA7498L is a dual BTL class-D audio amplifier with single power supply
designed for home systems and active speaker applications.
It comes in a 36-pin PowerSSO package with exposed pad up (EPU) to facilitate
mounting a separate heatsink.
Product status link
TDA7498L
Product summary
Order code TDA7498LTR
Temperature
range -40 to 85 °C
Package PowerSSO36
(EPU)
Packing Tape and reel
80 watt + 80 watt dual BTL class-D audio amplifier
TDA7498L
Datasheet
DS6539 - Rev 6 - June 2020
For further information contact your local STMicroelectronics sales office.
www.st.com
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1Device block diagram
Figure 1. Internal block diagram (showing one channel only) shows the block diagram of one of the two identical
channels of the TDA7498L.
Figure 1. Internal block diagram (showing one channel only)
TDA7498L
Device block diagram
DS6539 - Rev 6 page 2/23
333333333333333333 zzzzzzzzzzzzzzzzzz
2Pin description
2.1 Pinout
Figure 2. Pin connections (top view, PCB view)
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
28
29
30
31
32
33
34
35
36
19
20
21
22
23
24
25
26
27
VSS SUB_GND
OUTPB
OUTPB
PGNDB
PGNDB
PVCCB
PVCCB
OUTNB
OUTNB
OUTNA
OUTNA
PVCCA
PVCCA
PGNDA
PGNDA
OUTPA
OUTPA
PGND
VDDPW
STBY
MUTE
INPA
INNA
ROSC
SYNCLK
VDDS
SGND
DIAG
SVR
GAIN0
GAIN1
INPB
INNB
VREF
SVCC
EP, exposed pad
Conn ect to ground
TDA7498L
Pin description
DS6539 - Rev 6 page 3/23
2.2 Pin list
Table 1. Pin description list
Number Name Type Description
1 SUB_GND PWR Connect to the frame
2,3 OUTPB O Positive PWM for right channel
4,5 PGNDB PWR Power stage ground for right channel
6,7 PVCCB PWR Power supply for right channel
8,9 OUTNB O Negative PWM output for right channel
10,11 OUTNA O Negative PWM output for left channel
12,13 PVCCA PWR Power supply for left channel
14,15 PGNDA PWR Power stage ground for left channel
16,17 OUTPA O Positive PWM output for left channel
18 PGND PWR Power stage ground
19 VDDPW O 3.3-V (nominal) regulator output referred to ground for power stage
20 STBY I Standby mode control
21 MUTE I Mute mode control
22 INPA I Positive differential input of left channel
23 INNA I Negative differential input of left channel
24 ROSC O Master oscillator frequency-setting pin
25 SYNCLK I/O Clock in/out for external oscillator
26 VDDS O 3.3-V (nominal) regulator output referred to ground for signal blocks
27 SGND PWR Signal ground
28 DIAG O Open-drain diagnostic output
29 SVR O Supply voltage rejection
30 GAIN0 I Gain setting input 1
31 GAIN1 I Gain setting input 2
32 INPB I Positive differential input of right channel
33 INNB I Negative differential input of right channel
34 VREF O Half VDDS (nominal) referred to ground
35 SVCC PWR Signal power supply decoupling
36 VSS O 3.3-V (nominal) regulator output referred to power supply
- EP - Exposed pad for heatsink, to be connected to ground
TDA7498L
Pin list
DS6539 - Rev 6 page 4/23
3Electrical specifications
3.1 Absolute maximum ratings
Table 2. Absolute maximum ratings
Symbol Parameter Value Unit
VCC_MAX DC supply voltage for pins PVCCA, PVCCB, SVCC 45 V
VL_MAX Voltage limits for input pins STBY, MUTE, INNA, INPA, INNB, INPB,
GAIN0, GAIN1 -0.3 to 3.6 V
Tj_MAX Operating junction temperature 0 to 150 °C
Tstg Storage temperature -40 to 150 °C
Note: warning: stresses beyond those listed under “Absolute maximum ratings” make cause permanent damage to the
device. These are stress ratings only, and functional operation of the device at these or any other conditions
beyond those indicated under “Recommended operating condition” are not implied. Exposure to absolute
maximum rated conditions for extended periods may affect device reliability. In the real application, the power
supply with the nominal value rated in the recommended operating conditions may rise beyond the maximum
operating condition for a short time when no or very low current is sunk (amplifier in mute state). In this case the
reliability of the device is guaranteed, provided that the absolute maximum rating is not exceeded.
3.2 Thermal data
Table 3. Thermal data
Symbol Parameter Min. Typ. Max. Unit
Rth j-case Thermal resistance, junction to case - 2 3 °C/W
3.3 Recommended operating conditions
Table 4. Recommended operating conditions
Symbol Parameter Min. Typ. Max. Unit
VCC Supply voltage for pins PVCCA, PVCCB 14 - 36 V
Tamb Ambient operating temperature -20 - 85 °C
TDA7498L
Electrical specifications
DS6539 - Rev 6 page 5/23
3.4 Electrical characteristics
Unless otherwise stated, the values in the table below are specified for the conditions: VCC = 32 V, RL = 6 Ω,
ROSC = R3 = 39 kΩ, C8 = 100 nF, f = 1 kHz, GV = 25.6 dB Tamb = 25 °C.
Table 5. Electrical characteristics
Symbol Parameter Test conditions Min. Typ. Max. Unit
IqTotal quiescent current No LC filter, no load - 40 60 mA
IqSTBY Quiescent current in standby - - 1 10 µA
VOS Output offset voltage
Play mode -100 - 100
mV
Mute mode -60 - 60
IOCP Overcurrent protection threshold RL = 0 Ω 5.0 6.0 - A
TjS Junction temperature at thermal shutdown - - 150 - °C
RiInput resistance Differential input 48 60 - kΩ
VOVP Overvoltage protection threshold - 42 43 - V
VUVP Undervoltage protection threshold - - - 8 V
RdsON Power transistor on-resistance
High side - 0.2 -
Ω
Low side - 0.2 -
PoOutput power
THD = 10% - 80 -
W
THD = 1% - 65 -
PoOutput power RL = 8 Ω, THD = 10%, VCC = 32 V - 65 - W
PDDissipated power Po = 80 W + 80 W, THD = 10% - 16 - W
η Efficiency Po = 80 W + 80 W - 90 - %
THD Total harmonic distortion Po = 1 W - 0.1 - %
GVClosed-loop gain
GAIN0 = L, GAIN1 = L 24.6 25.6 26.6
dB
GAIN0 = L, GAIN1 = H 30.6 31.6 32.6
GAIN0 = H, GAIN1 = L 34.1 35.1 36.1
GAIN0 = H, GAIN1 = H 36.6 37.6 38.6
ΔGVGain matching - -1 - 1 dB
CTCrosstalk f = 1 kHz, Po = 1 W 50 70 - dB
eN Total input noise
A Curve, GV = 20 dB - 15 -
µV
f = 22 Hz to 22 kHz - 25 50
SVRR Supply voltage rejection ratio
fr = 100 Hz, Vr = 0.5 Vpp,
CSVR = 10 µF - 70 - dB
Tr, TfRise and fall times - - 50 - ns
fSW Switching frequency Internal oscillator 290 310 330 kHz
fSWR Output switching frequency range
With internal oscillator (1) 250 - 400
kHz
With external oscillator (2) 250 - 400
VinH Digital input high (H)
-
2.3 - -
V
VinL Digital input low (L) - - 0.8
TDA7498L
Electrical characteristics
DS6539 - Rev 6 page 6/23
Symbol Parameter Test conditions Min. Typ. Max. Unit
VSTBY
Pin STBY voltage high (H)
-
2.7 - -
V
Pin STBY voltage low (L) - - 0.5
VMUTE
Pin MUTE voltage high (H)
-
2.5 - -
V
Pin MUTE voltage low (L) - - 0.8
AMUTE Mute attenuation VMUTE < 0.8 V - 70 - dB
1. fSW = 106 / ((16 * ROSC + 182) * 4) kHz, fSYNCLK = 2 * fSW with R3 = 39 kΩ (see Figure 20. Application
circuit).
2. fSW = fSYNCLK / 2 with the external oscillator.
TDA7498L
Electrical characteristics
DS6539 - Rev 6 page 7/23
o B a
4Characterization curves
Figure 20. Application circuit shows the test circuit with which the characterization curves, shown in the next
sections, were measured. Figure 3. Test board below shows the PCB layout.
4.1 PCB layout
Figure 3. Test board
Top view
Bottom view
Top copp er
Bottom coppe r
4.2 Characterization curves
Unless otherwise stated the measurements were made under the following conditions:
TDA7498L
Characterizations
DS6539 - Rev 6 page 8/23
VCC = 32 V, f = 1 kHz, GV = 25.6 dB, ROSC = 39 kΩ, COSC = 100 nF, Tamb = 25 °C
4.2.1 For RL = 6 Ω
Figure 4. Output power vs. supply voltage Figure 5. THD vs. output power (1 kHz)
0.001
10
0.002
0.005
0.01
0.02
0.05
0.1
0.2
0.5
1
2
5
%
100m 90200m 500m 1 2 5 10 20 50
W
Figure 6. THD vs. output power (100 Hz)
0.001
10
0.002
0.005
0.01
0.02
0.05
0.1
0.2
0.5
1
2
5
%
100m 90200m 500m 1 2 5 10 20 50
W
Figure 7. THD vs. frequency (1 W)
0.005
1
0.01
0.02
0.05
0.1
0.2
0.5
%
20 20k50 100 200 500 1k 2k 5k 10k
Hz
TDA7498L
Characterization curves
DS6539 - Rev 6 page 9/23
”1L4 ¥m¢ H ~ V‘T: #wm
Figure 8. THD vs. frequency (100 mW)
0.01
1
0.02
0.05
0.1
0.2
0.5
%
20 20k50 100 200 500 1k 2k 5k 10k
Hz
Figure 9. Frequency response
-3
+3
-2.5
-2
-1.5
-1
-0.5
+0
+0.5
+1
+1.5
+2
+2.5
d
B
r
A
20 20k50 100 200 500 1k 2k 5k 10k
Hz
Figure 10. FFT performance (0 dBFS)
-150
+0
-140
-130
-120
-110
-100
-90
-80
-70
-60
-50
-40
-30
-20
-10
d
B
r
A
20 20k50 100 200 500 1k 2k 5k 10k
Hz
Figure 11. FFT performance (0 dBFS)
-150
+0
-140
-130
-120
-110
-100
-90
-80
-70
-60
-50
-40
-30
-20
-10
d
B
r
A
20 20k50 100 200 500 1k 2k 5k 10k
Hz
TDA7498L
Characterization curves
DS6539 - Rev 6 page 10/23
WWW 7 .7. #1 mmnmummmo- ....... u; 10 15 mum-M
4.2.2 For RL = 8 Ω
Figure 12. Output power vs. supply voltage Figure 13. THD vs. output power (1 kHz)
0.001
10
0.002
0.005
0.01
0.02
0.05
0.1
0.2
0.5
1
2
5
%
100m 90200m 500m 1 2 5 10 20 50
W
Figure 14. THD vs. output power (100 Hz)
0.001
10
0.002
0.005
0.01
0.02
0.05
0.1
0.2
0.5
1
2
5
%
100m 90200m 500m 1 2 5 10 20 50
W
Figure 15. THD vs. frequency (1 W)
0.005
1
0.01
0.02
0.05
0.1
0.2
0.5
%
20 20k50 100 200 500 1k 2k 5k 10k
Hz
TDA7498L
Characterization curves
DS6539 - Rev 6 page 11/23
’11 7
Figure 16. THD vs. frequency (100 mW)
0.01
1
0.02
0.05
0.1
0.2
0.5
%
20 20k50 100 200 500 1k 2k 5k 10k
Hz
Figure 17. Frequency response
-3
+3
-2.5
-2
-1.5
-1
-0.5
+0
+0.5
+1
+1.5
+2
+2.5
d
B
r
A
20 20k50 100 200 500 1k 2k 5k 10k
Hz
Figure 18. FFT performance (0 dB)
-150
+0
-140
-130
-120
-110
-100
-90
-80
-70
-60
-50
-40
-30
-20
-10
d
B
r
A
20 20k50 100 200 500 1k 2k 5k 10k
Hz
Figure 19. FFT performance (-60 dB)
-150
+0
-140
-130
-120
-110
-100
-90
-80
-70
-60
-50
-40
-30
-20
-10
d
B
r
A
20 20k50 100 200 500 1k 2k 5k 10k
Hz
TDA7498L
Characterization curves
DS6539 - Rev 6 page 12/23
u numo um
5Application information
5.1 Application circuit
Figure 20. Application circuit
L+
R+
R-
VCC
GND
L+
L-
R+
R-
TDA7498L
MUTE
S TBY
3V3 POWE R S UP P LY
S ingle-En de d
*
*
*
*
*
Input
CLAS S-D AMP LIFIER
*
*
*
*
S ingle-Ende d
Input
Load=6 ohm
For
For
FREQ UENCY S HIF T
OUTP UT
INPUT
L-
*
LC FILTER COMPONENT
Load L1,L2,L3,L4 C20,C26 C18,C22,C24,C28
6 ohm
8 ohm
22 uH
22 uH 470 nF
680 nF
220 nF
220 nF
C5
100nF
R3
39K
L4
22 uH
C1
1uF
C2
1uF
C11
1u F
C12
1uF
C8
100nF
C25
100nF
C19
100nF
C27
330pF
R6
22 R
C40
220nF
C41
220nF
C21
330pF
R5
22 R
C42
220nF
C43
220nF
C3
1n F
C4
1nF
C13
1nF
C14
1nF
32
INPB
36
VSS
9
OUTNB
5
PGNDB
7
PVCCB
3
OUTP B
10
OUTNA
12
PVCCA
14
PGNDA
16
OUTP A
33
INNB
8
OUTNB
4
PGNDB
21
MUTE
6
PVCCB
2
OUTP B
29
SVR
11
OUTNA
1
SUB_GND
22
INPA
23
INNA
27
SGND
26
VDDS
28
DIAG
19
VDDPW
18
PGND
20
STBY
24
ROS C
31
GAIN1
35
SVCC
30
GAIN0
25
SYNCLK
17
OUTP A
15
PGNDA
34
VREF
13
PVCCA
IC1
TDA7498L
R1
100k
R7
22R
C6
100nF
R4
12 0k
R2
33k
R8
6.8k
C26
680nF
C10
100nF
C20
680nF
J 6
J 5
2
1
3
S1
2
1
3
S2
C9
100nF
C29
2.2uF
2GND
1
OUT
3
IN
IC2
L49 31CZ33
+
C15
2.2uF
16V
1
2
J 2
J 8
J 7
+
C7
2.2uF
16V
+
C23
2200uF
50 V
L3
22 uH
L1
22 uH
L2
22 uH
C17
10 uF
10V
C16
10uF
10V
D1
18V
1
2
3
Q1
R9
120K
J 4
C30
1u F
C31
1uF
R14
47 k
R15
8R
C28
220nF
R16
8R
C24
220nF
R17
8R
C18
220nF
R18
8R
C22
220nF
SYNC
1
2
3
4
J 3
2
4
1
3
J 1
R13
68 k
DIAG
SGNDSGNDSGND
SGND
SGND
SGNDSGND
SGND
SGND
SGNDSGND
SGNDSGND
SGNDSGNDSGND
SGNDSGND
SGNDSGND
VDDS
VDDS
VCC
SGND SGND
SGND
SGND
SGND
SGND
3V3
3V3
SGND
SGND
SGND
SGND
SGND
SGND
SGND
FS
FS
FS
5.2 Mode selection
The three operating modes of the TDA7498L are set by the two inputs, STBY (pin 20) and MUTE (pin 21).
• Standby mode: all circuits are turned off, very low current consumption.
• Mute mode: inputs are connected to ground and the positive and negative PWM outputs are at 50% duty
cycle.
• Play mode: the amplifiers are active.
The protection functions of the TDA7498L are enabled by pulling down the voltages of the STBY and MUTE
inputs shown in Figure 21. Standby and mute circuits. The input current of the corresponding pins must be limited
to 200 µA.
Table 6. Mode settings
Mode STBY MUTE
Standby L (1) X (don’t care)
Mute H (1) L
Play H H
1. Drive levels defined in Table 5. Electrical characteristics
TDA7498L
Application information
DS6539 - Rev 6 page 13/23
mum A5“ inflnflAA/H'm A? VV UV U VU U UU V V ' in nflflflAAnn W V W U UKJ mud-by "wk a PM mm sand-hr loam“ I
Figure 21. Standby and mute circuits
Figure 22. Turn on/off sequence for minimizing speaker “pop”
5.3 Gain settings
The gain of the TDA7498L is set by the two inputs, GAIN0 (pin 30) and GAIN1 (pin31). Internally, the gain is set
by changing the feedback resistors of the amplifier.
Table 7. Gain settings
GAIN0 GAIN1 Nominal gain, Gv (dB)
L L 25.6
L H 31.6
H L 35.6
H H 37.6
TDA7498L
Gain settings
DS6539 - Rev 6 page 14/23
Rf N "‘9‘“ —| l—o—N- signal 0 Input Ri pin Av(dB)‘ -3 n mm>
5.4 Input resistance and capacitance
The input impedance is set by an internal resistor Ri = 60 kΩ (typical). An input capacitor (Ci) is required to couple
the AC input signal.
The equivalent circuit and frequency response of the input components are shown in Figure 23. Input circuit and
frequency response. For Ci = 470 nF the high-pass filter cutoff frequency is below 20 Hz:
fC = 1 / (2 * π * Ri * Ci)
Figure 23. Input circuit and frequency response
5.5 Internal and external clocks
The clock of the class-D amplifier can be generated internally or can be driven by an external source.
If two or more class-D amplifiers are used in the same system, it is recommended that all devices operate at the
same clock frequency. This can be implemented by using one TDA7498L as master clock, while the other devices
are in slave mode, that is, externally clocked. The clock interconnect is via pin SYNCLK of each device. As
explained below, SYNCLK is an output in master mode and an input in slave mode.
5.5.1 Master mode (internal clock)
Using the internal oscillator, the output switching frequency, fSW, is controlled by the resistor, ROSC, connected to
pin ROSC:
fSW = 106 / [(ROSC * 16 + 182) * 4] kHz
where ROSC is in kΩ.
In master mode, pin SYNCLK is used as a clock output pin whose frequency is:
fSYNCLK = 2 * fSW
TDA7498L
Input resistance and capacitance
DS6539 - Rev 6 page 15/23
MUD — 22w 1 m,“ ,, ZZOnF 330pF EZDHF A7DHF Enhm 22mm 3 EZDHF 220nF ZZUH Enhm mm D —
For master mode to operate correctly then resistor ROSC must be less than 60 kΩ as given below in Table 8. How
to set up SYNCLK.
5.5.2 Slave mode (external clock)
In order to accept an external clock input the pin ROSC must be left open, that is, floating. This forces pin
SYNCLK to be internally configured as an input as given in Table 8. How to set up SYNCLK.
The output switching frequency of the slave devices is:
fSW = fSYNCLK / 2
Table 8. How to set up SYNCLK
Mode ROSC SYNCLK
Master ROSC < 60 kΩ Output
Slave Floating (not connected) Input
Figure 24. Master and slave connection
5.6 Output low-pass filter
To avoid EMI problems, it may be necessary to use a low-pass filter before the speaker. The cutoff frequency
should be larger than 22 kHz and much lower than the output switching frequency. It is necessary to choose the L
and C component values depending on the loudspeaker impedance. Some typical values, which give a cutoff
frequency of 27 kHz, are shown in Figure 25. Typical LC filter for an 8 Ω speaker and Figure 26. Typical LC filter
for a 6 Ω speaker below.
Figure 25. Typical LC filter for an 8 Ω speaker
TDA7498L
Output low-pass filter
DS6539 - Rev 6 page 16/23
WM} ,3 w 22uH w. W new :7 3305* 220nF 630m: :: sonm 220hm T ZZOHF :: 220m: 22uH 30M! mm 1:,» —
Figure 26. Typical LC filter for a 6 Ω speaker
5.7 Protection functions
The TDA7498L is fully protected against overvoltages, undervoltages, overcurrents and thermal overloads as
explained here.
Overvoltage protection (OVP)
If the supply voltage exceeds the value for VOVP given in Table 5. Electrical characteristics , the overvoltage
protection is activated which forces the outputs to the high-impedance state. When the supply voltage falls back
to within the operating range, the device restarts.
Undervoltage protection (UVP)
If the supply voltage drops below the value for VUVP given in Table 5. Electrical characteristics , the undervoltage
protection is activated which forces the outputs to the high-impedance state. When the supply voltage falls back
to within the operating range, the device restarts.
Overcurrent protection (OCP)
If the output current exceeds the value for IOCP given in Table 5. Electrical characteristics , the overcurrent
protection is activated which forces the outputs to the high-impedance state. Periodically, the device attempts to
restart. If the overcurrent condition is still present then the OCP remains active. The restart time, TOC, is
determined by the RC components connected to pin STBY.
Thermal protection (OTP)
If the junction temperature, Tj, reaches 145 °C (nominally), the device goes to mute mode and the positive and
negative PWM outputs are forced to 50% duty cycle. If the junction temperature reaches the value for Tj given in
Table 5. Electrical characteristics , the device shuts down and the output is forced to the high-impedance state.
When the device cools sufficiently, the device restarts.
5.8 Diagnostic output
The output pin DIAG is an open drain transistor. When any protection is activated it switches to the high-
impedance state. The pin can be connected to a power supply (< 36 V) by a pull-up resistor whose value is limited
by the maximum sinking current (200 µA) of the pin.
TDA7498L
Protection functions
DS6539 - Rev 6 page 17/23
Figure 27. Behavior of pin DIAG for various protection conditions
TDA7498L
Protection logic
R1
DIAG
VDD
VDD
Overcurrent
prot ection
Restart Restart
OV, UV, OT
prot ection
TDA7498L
Diagnostic output
DS6539 - Rev 6 page 18/23
TonIEw
6Package information
In order to meet environmental requirements, ST offers these devices in different grades of ECOPACK packages,
depending on their level of environmental compliance. ECOPACK specifications, grade definitions and product
status are available at: www.st.com. ECOPACK is an ST trademark.
6.1 PowerSSO-36 EPU package information
Figure 28. PowerSSO-36 EPU package outline
TDA7498L
Package information
DS6539 - Rev 6 page 19/23
Table 9. PowerSSO-36 EPU package mechanical data
Symbol
mm inches
Min. Typ. Max. Min. Typ. Max.
A2.15 - 2.45 0.085 - 0.096
A2 2.15 - 2.35 0.085 - 0.093
a1 0 - 0.10 0 - 0.004
b 0.18 - 0.36 0.007 - 0.014
c 0.23 - 0.32 0.009 - 0.013
D 10.10 - 10.50 0.398 - 0.413
E 7.40 - 7.60 0.291 - 0.299
e - 0.5 - - 0.020 -
e3 - 8.5 - - 0.335 -
F - 2.3 - - 0.091 -
G - - 0.10 - - 0.004
H 10.10 - 10.50 0.398 - 0.413
h - - 0.40 - - 0.016
k 0 - 8 degrees 0 - 8 degrees
L 0.55 - 0.85 0.022 - 0.033
M - 4.30 - - 0.169 -
N - - 10 degrees - - 10 degrees
O - 1.20 - - 0.047 -
Q - 0.80 - - 0.031 -
S - 2.90 - - 0.114 -
T - 3.65 - - 0.144 -
U - 1.00 - - 0.039 -
X 4.10 - 4.70 0.161 - 0.185
Y 6.50 - 7.10 0.193 - 0.280
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DS6539 - Rev 6 page 20/23
Revision history
Table 10. Document revision history
Date Revision Changes
04-Dec-2009 1 Initial release.
02-Jul-2010 2
Removed datasheet preliminary status, updated Section Features list and Table
1. Device summary
Updated minimum supply voltage and temperature range in Table 5.
Recommended operating conditions
Updated typical power output for 8 Ω to 32 V in Table 6. Electrical specifications
12-Sep-2011 3 Updated OUTNA in Table 2. Pin description list; minor textual updates
09-Sep-2015 4 Updated VCC_MAX in Table 3. Absolute maximum ratings and dimension L in
Table 10. PowerSSO-36 EPU package mechanical data
24-Jan-2019 5 Updated product summary table in cover page
26-Jul-2020 6 Updated Figure 28 and Y min. value in Table 9
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Contents
1Device block diagram..............................................................2
2Pin description ....................................................................3
2.1 Pinout ........................................................................3
2.2 Pin list ........................................................................4
3Electrical specifications ...........................................................5
3.1 Absolute maximum ratings.......................................................5
3.2 Thermal data ..................................................................5
3.3 Recommended operating conditions ..............................................5
3.4 Electrical specifications .........................................................6
4Characterization curves............................................................8
4.1 PCB layout ....................................................................8
4.2 Characterization curves .........................................................8
4.2.1 For RL = 6 Ω ............................................................9
4.2.2 For RL = 8 Ω ...........................................................11
5Application information...........................................................13
5.1 Application circuit .............................................................13
5.2 Mode selection ...............................................................13
5.3 Gain setting ..................................................................14
5.4 Input resistance and capacitance ................................................15
5.5 Internal and external clocks .....................................................15
5.5.1 Master mode (internal clock) ...............................................15
5.5.2 Slave mode (external clock) ...............................................16
5.6 Output low-pass filter ..........................................................16
5.7 Protection functions ...........................................................17
5.8 Diagnostic output..............................................................17
6Package information..............................................................19
6.1 PowerSSO-36 EPU package information..........................................19
Revision history .......................................................................21
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Contents
DS6539 - Rev 6 page 22/23
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