Datenblatt für TS3L501E von Texas Instruments

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1!. B X E I TEXAS INSTRUMENTS

SEL

LED_A0

LED_B1

LED_B0

LED_A1

LED_A2LED_B2

LED_C1

LED_C0

LED_C2

Control Logic

POWER DOWN

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Folder

Order

Now

Technical

Documents

Tools &

Software

Support &

Community

An IMPORTANT NOTICE at the end of this data sheet addresses availability, warranty, changes, use in safety-critical applications,

intellectual property matters and other important disclaimers. PRODUCTION DATA.

TS3L501E

SCDS307C –SEPTEMBER 2010–REVISED DECEMBER 2017

TS3L501E 8-Channel SPDT/16-Bit to 8-Bit Multiplexer and Demultiplexer

Ethernet LAN Switch With Power-Down Mode

1 Features

1• Integrated Power-Down Mode

• Wide Bandwidth (BW = 600 MHz Typical)

• Low Crosstalk (XTALK = –37 dB Typical

at 250 MHz)

• Low Bit-to-Bit Skew (tsk(o) = 100 ps Maximum)

• Low and Flat ON-State Resistance

(ron = 4 ΩTypical, ron(flat) = 0.5 ΩTypical)

• Low Input and Output Capacitance

(CON = 9 pF Typical)

• Rail-to-Rail Switching on Data I/O Ports

(0 V to 3.6 V)

• VCC Operating Range From 3 V to 3.6 V

• Support Power-Down Mode

• Latch-Up Performance Exceeds 100 mA Per

JESD 78, Class II

• ESD Performance (A, B, C, LED pins)

– ±4-kV IEC61000-4-2, Contact Discharge

– 6-kV Human Body Model Per JESD22-A114E

(Switch I/O pins to GND)

• ESD Performance (All pins)

– 2-kV Human Body Model Per JESD22-A114E

2 Applications

• 10, 100, and 1000 Base-T Signal Switching

• Differential (LVDS, LVPECL) Signal Switching

• Audio and Video Switching

• Hub and Router Signal Switching

3 Description

The TS3L501E is a 8-channel SPDT analog switch or

16-bit to 8-bit multiplexer or demultiplexer LAN switch

with a single select (SEL) input and Power-Down

Mode input. The device provides additional I/Os for

switching status indicating LED signals and includes

high ESD protection. SEL input controls the data path

of the multiplexer or demultiplexer. Power-down input

can put the device into the standby mode for

minimizing current consumption per mode selection.

The device provides a low and flat ON-state

resistance (ron) and an excellent ON-state resistance

match. Low input or output capacitance, high

bandwidth, low skew, and low crosstalk among

channels make this device suitable for various LAN

applications, such as 10/100/1000 Base-T. This

device can be used to replace mechanical relays in

LAN applications. It also can be used to route signals

from a 10/100 Base-T Ethernet transceiver to the RJ-

45 LAN connectors in laptops or in docking stations.

It is characterized for operation over the free-air

temperature range of –40ºC to 85ºC.

Device Information(1)

PART NUMBER PACKAGE BODY SIZE (NOM)

TS3L501E WQFN (42) 9.00 mm × 3.50 mm

(1) For all available packages, see the orderable addendum at

the end of the data sheet.

Functional Block Diagram

l TEXAS INSTRUMENTS

TS3L501E

SCDS307C –SEPTEMBER 2010–REVISED DECEMBER 2017

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Product Folder Links: TS3L501E

Table of Contents

1 Features.................................................................. 1

2 Applications ........................................................... 1

3 Description ............................................................. 1

4 Revision History..................................................... 2

5 Pin Configuration and Functions......................... 3

6 Specifications......................................................... 5

6.1 Absolute Maximum Ratings ..................................... 5

6.2 ESD Ratings.............................................................. 5

6.3 Recommended Operating Conditions....................... 5

6.4 Thermal Information.................................................. 6

6.5 Electrical Characteristics for 1000 Base-T Ethernet

Switching.................................................................... 6

6.6 Electrical Characteristics for 10/100 Base-T Ethernet

Switching.................................................................... 6

6.7 Switching Characteristics.......................................... 7

6.8 Dynamic Characteristics ........................................... 7

6.9 Typical Characteristics.............................................. 8

7 Parameter Measurement Information .................. 9

7.1 Enable and Disable Times........................................ 9

7.2 Skew ....................................................................... 10

7.3 HP8753ES Setup.................................................... 11

7.4 HP8753ES Setup.................................................... 12

7.5 HP8753ES Setup.................................................... 13

8 Detailed Description............................................ 14

8.1 Overview ................................................................. 14

8.2 Functional Block Diagram....................................... 14

8.3 Feature Description................................................. 14

8.4 Device Functional Modes........................................ 14

9 Application and Implementation ........................ 15

9.1 Application Information............................................ 15

9.2 Typical Application ................................................. 15

10 Power Supply Recommendations ..................... 17

11 Layout................................................................... 17

11.1 Layout Guidelines ................................................. 17

11.2 Layout Example .................................................... 18

12 Device and Documentation Support ................. 19

12.1 Documentation Support ........................................ 19

12.2 Receiving Notification of Documentation Updates 19

12.3 Community Resources.......................................... 19

12.4 Trademarks........................................................... 19

12.5 Electrostatic Discharge Caution............................ 19

12.6 Glossary................................................................ 19

13 Mechanical, Packaging, and Orderable

Information ........................................................... 19

4 Revision History

NOTE: Page numbers for previous revisions may differ from page numbers in the current version.

Changes from Revision B (May 2016) to Revision C Page

• Added pin numbers 4, 8, 14, 21, 30, 39 to VDD in the Pin Functions table ............................................................................ 4

Changes from Revision A (September 2010) to Revision B Page

• Added ESD Ratings table, Feature Description section, Device Functional Modes,Application and Implementation

section, Power Supply Recommendations section, Layout section, Device and Documentation Support section, and

Mechanical, Packaging, and Orderable Information section.................................................................................................. 1

• Removed Ordering Information table .................................................................................................................................... 1

@@@@@@@@@@@ ® ® SW S": DEDDDDDDDEEDEEE ‘5‘ TEXAS INSTRUMENTS

17 22

VDD

SEL

LED_A0

LED_ A1

LED_ B0

VDD

LED_B1

LED_C0

LED_C1

VDD

LED_A2

LED_ B2

LED_ C2

Exposed

Center Pad

(GND)

TS3L501E

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5 Pin Configuration and Functions

RUA Package

42-Pin WQFN

Top View

The exposed center pad must be connected to GND.

Pin Functions

PIN I/O DESCRIPTION

NAME NO.

A02 I/O Port A Common I/O signal path

A13 I/O Port A Common I/O signal path

A26 I/O Port A Common I/O signal path

A37 I/O Port A Common I/O signal path

A49 I/O Port A Common I/O signal path

A510 I/O Port A Common I/O signal path

A611 I/O Port A Common I/O signal path

A712 I/O Port A Common I/O signal path

B038 I/O Port B I/O signal path

B137 I/O Port B I/O signal path

B234 I/O Port B I/O signal path

B333 I/O Port B I/O signal path

B429 I/O Port B I/O signal path

B528 I/O Port B I/O signal path

B625 I/O Port B I/O signal path

l TEXAS INSTRUMENTS

TS3L501E

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Pin Functions (continued)

PIN I/O DESCRIPTION

NAME NO.

B724 I/O Port B I/O signal path

C036 I/O Port C I/O signal path

C135 I/O Port C I/O signal path

C232 I/O Port C I/O signal path

C331 I/O Port C I/O signal path

C427 I/O Port C I/O signal path

C526 I/O Port C I/O signal path

C623 I/O Port C I/O signal path

C722 I/O Port C I/O signal path

GND Exposed Center Pad — Ground

LED_A015 I/O Port A LED I/O Common signal path, (may also be used as a general

purpose signal path)

LED_A116 I/O Port A LED Common I/O signal path, (may also be used as a general

purpose signal path)

LED_A242 I/O Port A LED Common I/O signal path, (may also be used as a general

purpose signal path)

LED_B017 I/O Port B LED I/O signal path, (may also be used as a general purpose

signal path)

LED_B118 I/O Port B LED I/O signal path, (may also be used as a general purpose

signal path)

LED_B241 I/O Port B LED I/O signal path, (may also be used as a general purpose

signal path)

LED_C019 I/O Port C LED I/O signal path, (may also be used as a general purpose

signal path)

LED_C120 I/O Port C LED I/O signal path, (may also be used as a general purpose

signal path)

LED_C240 I/O Port C LED I/O signal path, (may also be used as a general purpose

signal path)

PD 5 Input Power Down Input, Active High

SEL 13 Input Select Input

VDD 1, 4, 8, 14, 21, 30, 39 — Power

l TEXAS INSTRUMENTS

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SCDS307C –SEPTEMBER 2010–REVISED DECEMBER 2017

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(1) Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. These are stress ratings

only, which do not imply functional operation of the device at these or any other conditions beyond those indicated under Recommended

Operating Conditions. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.

(2) All voltages are with respect to ground, unless otherwise specified.

(3) The input and output voltage ratings may be exceeded if the input and output clamp-current ratings are observed.

(4) VIand VOare used to denote specific conditions for VI/O.

(5) IIand IOare used to denote specific conditions for II/O.

6 Specifications

6.1 Absolute Maximum Ratings

over operating free-air temperature range (unless otherwise noted)(1)

MIN MAX UNIT

VDD Supply voltage –0.5 4.6 V

VIN Control input voltage(2) (3) –0.5 7 V

VI/O Switch I/O voltage(2) (3) (4) –0.5 7 V

IIK Control input clamp current VIN < 0 –50 mA

II/OK I/O port clamp current VI/O < 0 –50 mA

II/O ON-state switch current(5) ±128 mA

Continuous current through VDD or GND ±100 mA

Tstg Storage temperature –65 150 °C

(1) JEDEC document JEP155 states that 500-V HBM allows safe manufacturing with a standard ESD control process.

(2) JEDEC document JEP157 states that 250-V CDM allows safe manufacturing with a standard ESD control process.

6.2 ESD Ratings

VALUE UNIT

V(ESD) Electrostatic discharge

Human-body model (HBM), per

ANSI/ESDA/JEDEC JS-001(1)

All pins except 1, 4, 5, 8,

13, 14, 21, 30, and 39 ±6000

VPins 1, 4, 5, 8, 13, 14, 21,

30, and 39 ±2000

Charged-device model (CDM), per JEDEC specification JESD22-C101(2) ±1500

(1) All unused control inputs of the device must be held at VDD or GND to ensure proper device operation. See the TI application report,

Implications of Slow or Floating CMOS Inputs,SCBA004.

6.3 Recommended Operating Conditions

over operating free-air temperature range (unless otherwise noted)(1)

MIN MAX UNIT

VDD Supply voltage 3 3.6 V

VIH High-level control input voltage (SEL) 2 5.5 V

VIL Low-level control input voltage (SEL) 0 0.8 V

VIN Input voltage (SEL) 0 5.5 V

VI/O Input or output voltage 0 VDD V

TAOperating free-air temperature –40 85 °C

l TEXAS INSTRUMENTS

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(1) For more information about traditional and new thermal metrics, see the Semiconductor and IC Package Thermal Metrics application

report.

(2) The package thermal impedance is calculated in accordance with JESD 51-7.

6.4 Thermal Information

THERMAL METRIC(1)

TS3L501E

UNITRUA (WQFN)

42 PINS

RθJA Junction-to-ambient thermal resistance(2) 30.9 °C/W

RθJC(top) Junction-to-case (top) thermal resistance 12.8 °C/W

RθJB Junction-to-board thermal resistance 5.2 °C/W

ψJT Junction-to-top characterization parameter 0.2 °C/W

ψJB Junction-to-board characterization parameter 5 °C/W

RθJC(bot) Junction-to-case (bottom) thermal resistance 1.5 °C/W

(1) VI, VO, II, and IOrefer to I/O pins. VIN refers to the control inputs.

(2) All typical values are at VDD = 3.3 V (unless otherwise noted), TA= 25°C.

(3) ron(flat) is the difference of ron in a given channel at specified voltages.

(4) Δron is the difference of ron from center (A4, A5) ports to any other port.

6.5 Electrical Characteristics for 1000 Base-T Ethernet Switching

for 1000 Base-T Ethernet switching over recommended operating free-air temperature range, VDD = 3.3 V ± 0.3 V

(unless otherwise noted)

PARAMETER TEST CONDITIONS(1) MIN TYP(2) MAX UNIT

VIK SEL, PD VDD = 3.6 V, IIN = –18 mA –0.7 –1.2 V

IIH SEL, PD VDD = 3.6 V, VIN = VDD ±2 μA

IIL SEL, PD VDD = 3.6 V, VIN = GND ±1 μA

IOFF SEL, PD VDD = 0 V, VIN = 0 to 3.6 V ±1 μA

ICC VDD = 3.6 V, II/O = 0, switch ON or OFF 250 600 μA

ICC_PD VDD = 3.6 V, VIN = 3.6 V, PD = high 1

CIN SEL, PD f = 1 MHz, VIN = 0 2.6 3 pF

COFF B or C port VI= 0,f = 1 MHz, outputs open, switch OFF 3 4 pF

CON VI= 0,f = 1 MHz, outputs open, switch ON 9 9.8 pF

ron VDD = 3 V, 1.5 V ≤VI≤VDD, IO= –40 mA 4 8 Ω

ron(flat) (3) VDD = 3 V, VI= 1.5 V and VDD, IO= –40 mA 0.7 Ω

Δron (4) VDD = 3 V, 1.5 V ≤VI≤VDD, IO= –40 mA 0.8 1.5 Ω

(1) VI, VO, II, and IOrefer to I/O pins. VIN refers to the control inputs.

(2) All typical values are at VDD = 3.3 V (unless otherwise noted), TA= 25°C.

(3) ron(flat) is the difference of ron in a given channel at specified voltages.

(4) Δron is the difference of ron from center (A4, A5) ports to any other port.

6.6 Electrical Characteristics for 10/100 Base-T Ethernet Switching

for 10/100 Base-T Ethernet switching over recommended operating free-air temperature range, VDD = 3.3 V ± 0.3 V

(unless otherwise noted)

PARAMETER TEST CONDITIONS(1) MIN TYP(2) MAX UNIT

VIK SEL, PD VDD = 3.6 V, IIN = –18 mA –0.7 –1.2 V

IIH SEL, PD VDD = 3.6 V, VIN = VDD ±2 μA

IIL SEL, PD VDD = 3.6 V, VIN = GND ±1 μA

IOFF SEL, PD VDD = 0 V, VIN = 0 to 3.6 V ±1 μA

ICC VDD = 3.6 V, II/O = 0, switch ON or OFF 250 600 μA

ICC_PD VDD = 3.6 V, VIN = 3.6 V, PD = high 1

CIN SEL, PD f = 1 MHz, VIN = 0 2.6 3.0 pF

COFF B or C port VI= 0,f = 10 MHz, outputs open, switch OFF 3 4 pF

CON VI= 0,f = 10 MHz, outputs open, switch ON 9 9.8 pF

ron VDD = 3 V, 1.25 V ≤VI≤VDD, IO= –10 mA to –30 mA 4 6 Ω

ron(flat) (3) VDD = 3 V, VI= 1.25 V and VDD, IO= –10 mA to –30 mA 0.5 Ω

Δron (4) VDD = 3 V, 1.25 V ≤VI≤VDD, IO= –10 mA to –30 mA 0.8 1.5 Ω

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(1) All typical values are at VDD = 3.3 V (unless otherwise noted), TA= 25°C.

(2) The propagation delay is the calculated RC time constant of the typical ON-state resistance of the switch and the specified load

capacitance when driven by an ideal voltage source (zero output impedance).

(3) Output skew between center port (A4to A5) to any other port

(4) Skew between opposite transitions of the same output in a given device |tPHL – tPLH|

(5) Device enable/disable time from PD

6.7 Switching Characteristics

over recommended operating free-air temperature range, VDD = 3.3 V ± 0.3 V, RL= 200 Ω, CL= 10 pF

(unless otherwise noted) (see Figure 5 and Figure 6)

PARAMETER FROM

(INPUT) TO

(OUTPUT) MIN TYP(1) MAX UNIT

tpd (2) A or B/C B/C or A 0.3 ns

tPZH, tPZL SEL A or B/C 0.5 15 ns

tPHZ, tPLZ SEL A or B/C 0.9 9 ns

tsk(o) (3) A or B/C B/C or A 50 100 ps

tsk(p) (4) A or B/C B/C or A 50 100 ps

tON/tOFF(5) PD A or B/C 250 ns

(1) All typical values are at VCC = 3.3 V (unless otherwise noted), TA= 25°C.

6.8 Dynamic Characteristics

over recommended operating free-air temperature range, VDD = 3.3 V ± 0.3 V (unless otherwise noted)

PARAMETER TEST CONDITIONS TYP(1) UNIT

XTALK RL= 50 Ω, f = 250 MHz, see Figure 8 –37 dB

OIRR RL= 50 Ω, f = 250 MHz, see Figure 9 –37 dB

BW See Figure 7 600 MHz

l TEXAS INSTRUMENTS

3.5

2.5

1.5

0.5

0 0.5 1 1.5 2 2.5 3 3.5 4

V -InputVoltage-V

R -On-Resistance-

ON W

-19.97

-29.97

-39.97

-49.97

-59.97

-69.97

-79.97

-89.97

-99.97

-109.97

1.00E+6 10.00E+6 100.00E+6 1.00E+9 10.00E+9

f-Frequency-Hz

Attenuation-dB

-14

-24

-34

-44

-54

-64

-74

-84

-94

1.00E+6 10.00E+6 100.00E+6 1.00E+9 10.00E+9

f-Frequency-Hz

Attenuation-dB

f - Frequency - Hz

Gain - dB

-16

-14

-12

-10

-8

-6

-4

-2

1.00E+06 10.00E+06 100.00E+06 1.00E+09 10.00E+09

TS3L501E

SCDS307C –SEPTEMBER 2010–REVISED DECEMBER 2017

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6.9 Typical Characteristics

Figure 1. Gain vs Frequency Figure 2. OFF Isolation vs Frequency

Figure 3. Crosstalk vs Frequency Figure 4. ron (Ω) vs Vcom (V)

‘5‘ TEXAS INSTRUMENTS En sz F'ZL

(see Note A)

TEST CIRCUIT

2×VDD

Open

GND

NOTES: A. CLincludes probe and jig capacitance.

B. Waveform 1 is for an output with internal conditions such that the output is low, except when disabled by the output control.

Waveform 2 is for an output with internal conditions such that the output is high, except when disabled by the output control.

C. All input pulses are supplied by generators having the following characteristics: PRR≤10 MHz, ZO= 50 W, tr≤2.5 ns, tf≤2.5 ns.

D. The outputs are measured one at a time, with one transition per measurement.

E. tPLZ and tPHZ are the same as tdis.

F. tPZL and tPZH are the same as ten.

50 W

VG1

VDD

DUT

50 W

VIN

50 W

VG2 50 W

TEST RL

S1 VD

VDD Vin

tPLZ/tPZL 2×VDD 200 WGND 10 pF 0.3 V

Input Generator

Input Generator VO

tPHZ/tPZH

3.3 V

3.3 V GND 200 WVDD 10 pF 0.3 V

tPZL

VOH - 0.3 V

VOLTAGE WAVEFORMS

ENABLE AND DISABLE TIMES

VDD/2

Output Control

(VIN)1.25 V

2.5 V

VOH

VOL + 0.3 V

VOH

VOL

0 V

1.25 V

tPZH

tPLZ

tPHZ

Output

Waveform 2

S1 at GND

(see Note B)

Output

Waveform 1

S1 at 2 VDD

(see Note B)

VOL

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7 Parameter Measurement Information

7.1 Enable and Disable Times

Figure 5. Test Circuit and Voltage Waveforms

_________ ____a

(see Note A)

TEST CIRCUIT

2×VDD

Open

GND

VOH

VOL

VOLTAGE WAVEFORMS

OUTPUT SKEW (tsk(o))

Data Out at

YB1or YB2

NOTES: A. CLincludes probe and jig capacitance.

B. Waveform 1 is for an output with internal conditions such that the output is low, except when disabled by the output control.

Waveform 2 is for an output with internal conditions such that the output is high, except when disabled by the output control.

C. All input pulses are supplied by generators having the following characteristics: PRR≤10 MHz, ZO= 50 W, tr≤2.5 ns, tf≤2.5 ns.

D. The outputs are measured one at a time, with one transition per measurement.

50 W

VG1

VDD

DUT

50 W

VIN

50 W

VG2 50 W

TEST RL

S1 CL

3.3 V ±0.3 V

VDD Vin

tsk(p)

tsk(o)

3.3 V ±0.3 V

Open

200 W

VDD or GND

10 pF

Input Generator

Input Generator VO

(VOH + VOL)/2

VOH

VOL

Data Out at

XB1or XB2

(VOH + VOL)/2

3.5 V

1.5 V

Data In at

Ax or Ay 2.5 V

tPLHx tPHLx

tsk(o) tsk(o)

tPLHy tPHLy

tsk(o) = t PLHy - t PLHx or t PHLy - t PHLx

VOH

VOL

VOLTAGE WAVEFORMS

PULSE SKEW [tsk(p)]

Output (VOH + VOL)/2

Input 2.5 V

tPLH tPHL

tsk(p) = t PHL - t PLH

3.5 V

1.5 V

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7.2 Skew

Figure 6. Test Circuit and Voltage Waveforms

l TEXAS INSTRUMENTS “HF.

Network Analyzer

(HP8753ES)

EXT TRIGGER

BIAS

P1 P2

DUT

SEL

0B1

VSEL

VDD

VBIAS

CL= 10 pF

(see Note A)

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Skew (continued)

A. CLincludes probe and jig capacitance.

Figure 7. Test Circuit for Frequency Response (BW)

Frequency response is measured at the output of the ON channel. For example, when VSEL = 0 and A0is the

input, the output is measured at 0B1. All unused analog I/O ports are left open.

7.3 HP8753ES Setup

Average = 4

RBW = 3 kHz

VBIAS = 0.35 V

ST=2s

P1 = 0 dBM

l TEXAS INSTRUMENTS i T

Network Analyzer

(HP8753ES)

RL= 50 W

EXT TRIGGER

BIAS

P1 P2

DUT

SEL

0B1

VSEL

VDD

VBIAS

1B2

1B1

RL= 50 W

2B1

3B1

0B2

3B2

2B2

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HP8753ES Setup (continued)

A. CLincludes probe and jig capacitance.

B. A 50-Ωtermination resistor is needed to match the loading of the network analyzer.

Figure 8. Test Circuit for Crosstalk (XTALK)

Crosstalk is measured at the output of the nonadjacent ON channel. For example, when VSEL = 0 and A1is the

input, the output is measured at A3. All unused analog input (A) ports are connected to GND, and output (B)

ports are left open.

7.4 HP8753ES Setup

Average = 4

RBW = 3 kHz

VBIAS = 0.35 V

ST=2s

P1 = 0 dBM

l TEXAS INSTRUMENTS

Network Analyzer

(HP8753ES)

RL= 50 W

EXT TRIGGER

BIAS

P1 P2

DUT

SEL

0B1

VSEL

VDD

VBIAS

0B2

A11B1

1B2

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HP8753ES Setup (continued)

A. CLincludes probe and jig capacitance.

B. A 50-Ωtermination resistor is needed to match the loading of the network analyzer.

Figure 9. Test Circuit for OFF Isolation (OIRR)

OFF isolation is measured at the output of the OFF channel. For example, when VSEL = GND and A1is the input,

the output is measured at 1B2. All unused analog input (A) ports are connected to ground, and output (B) ports

are left open.

7.5 HP8753ES Setup

Average = 4

RBW = 3 kHz

VBIAS = 0.35 V

ST=2s

P1 = 0 dBM

l TEXAS INSTRUMENTS

SEL

LED_A0

LED_B1

LED_B0

LED_A1

LED_A2LED_B2

LED_C1

LED_C0

LED_C2

Control Logic

POWER DOWN

TS3L501E

SCDS307C –SEPTEMBER 2010–REVISED DECEMBER 2017

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8 Detailed Description

8.1 Overview

The TS3L501E is a 8-channel SPDT analog switch or 16-bit to 8-bit multiplexer/demultiplexer LAN switch with a

single select (SEL) input and Power Down Mode input. The device provides additional I/Os for switching status

indicating LED signals and includes high ESD protection. SEL input controls the data path of the

multiplexer/demultiplexer. Power Down input can put the device into the standby mode for minimizing current

consumption per mode selection.

The device provides a low and flat ON-state resistance (ron) and an excellent ON-state resistance match. Low

input/output capacitance, high bandwidth, low skew, and low crosstalk among channels make this device suitable

for various LAN applications, such as 10/100/1000 Base-T. This device can be used to replace mechanical

relays in LAN applications. It also can be used to route signals from a 10/100 Base-T Ethernet transceiver to the

RJ-45 LAN connectors in laptops or in docking stations.

8.2 Functional Block Diagram

Figure 10. Logic Diagram (Positive Logic)

8.3 Feature Description

The TS3L501E device switches and pin out are optimized for ethernet application but the device can used for

many applications where a multi-channel, 1:2 SPDT, high bandwidth switch is needed.

8.4 Device Functional Modes

The TS3L501E supports a power down mode which reduces the current consumption of the device and places

all the signal paths in a high impedance state. To place the TS3L501E in power down mode, set the PD pin with

a logic high voltage as seen in Table 1.

Table 1. Function Table

PD SEL FUNCTION

L L Anto Bn, LED_Anto LED_Bn

L H Anto Cn, LED_Anto LED_Cn

H X Hi-Z

l TEXAS INSTRUMENTS

RJ45 Port 1

RJ45 Port 2

SEL

Gigabit

Ethernet

PHY

Processor TS3L501E

VDD

GND

GPIO

7 7

LED 1

LED 2

LED_BN

LED_CN

LED_AN

GPIO

TS3L501E

www.ti.com

SCDS307C –SEPTEMBER 2010–REVISED DECEMBER 2017

Product Folder Links: TS3L501E

9 Application and Implementation

NOTE

Information in the following applications sections is not part of the TI component

specification, and TI does not warrant its accuracy or completeness. TI’s customers are

responsible for determining suitability of components for their purposes. Customers should

validate and test their design implementation to confirm system functionality.

9.1 Application Information

There are many Local Area Network (LAN) applications in which the ethernet hubs or controllers have a limited

number of I/Os or need to route signals from a single ethernet PHY to multiple ethernet jacks. The TS3L501E

solution can effectively expand the limited I/Os by switching between multiple ethernet jacks to interface them to

a single ethernet PHY.

The LED_An, LED_Bn,and LED_Cnpins are rated the same as the other signal path pins so you may use these

pins as extra data paths if needed.

9.2 Typical Application

Figure 11. Typical Application Schematic

l TEXAS INSTRUMENTS

f - Frequency - Hz

Gain - dB

-16

-14

-12

-10

-8

-6

-4

-2

1.00E+06 10.00E+06 100.00E+06 1.00E+09 10.00E+09

TS3L501E

SCDS307C –SEPTEMBER 2010–REVISED DECEMBER 2017

www.ti.com

Product Folder Links: TS3L501E

Typical Application (continued)

9.2.1 Design Requirements

Ensure that all of the signals passing through the switch are within the recommended operating ranges. To

ensure proper performance, see Recommended Operating Conditions.

9.2.2 Detailed Design Procedure

The TS3L501E can be properly operated without any external components.

TI recommends that the digital control pins SEL and PD be pulled up to VCC or down to GND to avoid undesired

switch positions that could result from the floating pin.

Connect the exposed thermal pad to ground.

9.2.3 Application Curve

Figure 12. Gain vs Frequency

l TEXAS INSTRUMENTS

Signal 1

GND Plane

Power Plane

Signal 2

TS3L501E

www.ti.com

SCDS307C –SEPTEMBER 2010–REVISED DECEMBER 2017

Product Folder Links: TS3L501E

10 Power Supply Recommendations

Power to the device is supplied through the VDD pins. TI recommends placing a bypass capacitor as close to the

supply pin (VCC) as possible to help smooth out lower frequency noise to provide better load regulation across

the frequency spectrum.

All VDD pins are internally connected. One PCB layout option is to connect one of the VDD to the power supply

and leave the other VDD pins open.

Supply the TS3L501E VDD pins with the recommended voltage before appling a signal voltage to the I/O signal

paths to avoid violating the recommended opperating condition I/O voltage 0-VDD

11 Layout

11.1 Layout Guidelines

• TI recommends keeping the high-speed signals as short as possible.

• Each via introduces discontinuities in the transmission line of the signal and increases the chance of picking

up interference from the other layers of the board. Be careful when designing test points on twisted pair lines;

through-hole pins are not recommended.

• When it becomes necessary to turn 90°, use two 45° turns or an arc instead of making a single 90° turn. This

reduces reflections on the signal traces by minimizing impedance discontinuities.

• Do not route traces under or near crystals, oscillators, clock signal generators, switching regulators, mounting

holes, magnetic devices or ICs that use or duplicate clock signals.

• Avoid stubs on the high-speed signals because they cause signal reflections. If a stub is unavoidable, then

the stub must be less than 200 mm.

• Route all high-speed signal traces over continuous GND planes, with no interruptions. Avoid crossing over

anti-etch, commonly found with plane splits.

• Due to high-frequency signals, a printed-circuit board with at least four layers is recommended; two signal

layers separated by a ground and power layer as shown in Figure 13.

• The majority of signal traces must run on a single layer, preferably Signal 1. Immediately next to this layer

should be the GND plane, which is solid with no cuts. Avoid running signal traces across a split in the ground

or power plane. When running across split planes is unavoidable, sufficient decoupling must be used.

Minimizing the number of signal vias reduces EMI by reducing inductance at high frequencies.

Figure 13. Four-Layer Board Stackup

{L} TEXAS INSTRUMENTS TTT J J J J J J J J L L L JJFJJJ FJFJJ FJJ

201918 21

404142 39

Exposed Center

Pad

(GND)

To System

System

To System

System

To System

VDD

0603

TS3L501E

SCDS307C –SEPTEMBER 2010–REVISED DECEMBER 2017

www.ti.com

Product Folder Links: TS3L501E

11.2 Layout Example

Figure 14. Layout Example

l TEXAS INSTRUMENTS

TS3L501E

www.ti.com

SCDS307C –SEPTEMBER 2010–REVISED DECEMBER 2017

Product Folder Links: TS3L501E

12 Device and Documentation Support

12.1 Documentation Support

12.1.1 Related Documentation

For related documentation, see the following:

Implications of Slow or Floating CMOS Inputs,SCBA004

12.2 Receiving Notification of Documentation Updates

To receive notification of documentation updates, navigate to the device product folder on ti.com. In the upper

right corner, click on Alert me to register and receive a weekly digest of any product information that has

changed. For change details, review the revision history included in any revised document.

12.3 Community Resources

The following links connect to TI community resources. Linked contents are provided "AS IS" by the respective

contributors. They do not constitute TI specifications and do not necessarily reflect TI's views; see TI's Terms of

Use.

TI E2E™ Online Community TI's Engineer-to-Engineer (E2E) Community. Created to foster collaboration

among engineers. At e2e.ti.com, you can ask questions, share knowledge, explore ideas and help

solve problems with fellow engineers.

Design Support TI's Design Support Quickly find helpful E2E forums along with design support tools and

contact information for technical support.

12.4 Trademarks

E2E is a trademark of Texas Instruments.

All other trademarks are the property of their respective owners.

12.5 Electrostatic Discharge Caution

This integrated circuit can be damaged by ESD. Texas Instruments recommends that all integrated circuits be handled with

appropriate precautions. Failure to observe proper handling and installation procedures can cause damage.

ESD damage can range from subtle performance degradation to complete device failure. Precision integrated circuits may be more

susceptible to damage because very small parametric changes could cause the device not to meet its published specifications.

12.6 Glossary

SLYZ022 —TI Glossary.

This glossary lists and explains terms, acronyms, and definitions.

13 Mechanical, Packaging, and Orderable Information

The following pages include mechanical, packaging, and orderable information. This information is the most

current data available for the designated devices. This data is subject to change without notice and revision of

this document. For browser-based versions of this data sheet, refer to the left-hand navigation.

I TEXAS INSTRUMENTS Samples

PACKAGE OPTION ADDENDUM

www.ti.com 10-Dec-2020

Addendum-Page 1

PACKAGING INFORMATION

Orderable Device Status

(1)

Package Type Package

Drawing Pins Package

Qty Eco Plan

(2)

Lead finish/

Ball material

(6)

MSL Peak Temp

(3)

Op Temp (°C) Device Marking

(4/5)

Samples

TS3L501ERUAR ACTIVE WQFN RUA 42 3000 RoHS & Green NIPDAU Level-2-260C-1 YEAR -40 to 85 TK501E

(1) The marketing status values are defined as follows:

ACTIVE: Product device recommended for new designs.

LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.

NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design.

PREVIEW: Device has been announced but is not in production. Samples may or may not be available.

OBSOLETE: TI has discontinued the production of the device.

(2) RoHS: TI defines "RoHS" to mean semiconductor products that are compliant with the current EU RoHS requirements for all 10 RoHS substances, including the requirement that RoHS substance

do not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, "RoHS" products are suitable for use in specified lead-free processes. TI may

reference these types of products as "Pb-Free".

RoHS Exempt: TI defines "RoHS Exempt" to mean products that contain lead but are compliant with EU RoHS pursuant to a specific EU RoHS exemption.

Green: TI defines "Green" to mean the content of Chlorine (Cl) and Bromine (Br) based flame retardants meet JS709B low halogen requirements of <=1000ppm threshold. Antimony trioxide based

flame retardants must also meet the <=1000ppm threshold requirement.

(3) MSL, Peak Temp. - The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature.

(4) There may be additional marking, which relates to the logo, the lot trace code information, or the environmental category on the device.

(5) Multiple Device Markings will be inside parentheses. Only one Device Marking contained in parentheses and separated by a "~" will appear on a device. If a line is indented then it is a continuation

of the previous line and the two combined represent the entire Device Marking for that device.

(6) Lead finish/Ball material - Orderable Devices may have multiple material finish options. Finish options are separated by a vertical ruled line. Lead finish/Ball material values may wrap to two

lines if the finish value exceeds the maximum column width.

Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information

provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and

continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals.

TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited information may not be available for release.

In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI to Customer on an annual basis.

I TEXAS INSTRUMENTS REEL DIMENSIONS TAPE DIMENSIONS 7 “K0 '«m» Reel Diame|er AD Dimension deswgned to accommodate the componem wwdlh E0 Dimension desxgned to accommodate the componenl \ength KO Dimenslun deswgned to accommodate the componem thickness 7 w OveraH wwdm loe earner cape i p1 Pitch between successwe cavuy cemers f T Reel Width (W1) QUADRANT ASSIGNMENTS FOR PIN 1 ORIENTATION IN TAPE O O O D O O D O Sprockemoles ,,,,,,,,,,, ‘ User Direcllon 0' Feed Pockel Quadrams

TAPE AND REEL INFORMATION

*All dimensions are nominal

Device Package

Type Package

Drawing Pins SPQ Reel

Diameter

(mm)

Reel

Width

W1 (mm)

(mm) B0

(mm) K0

(mm) P1

(mm) W

(mm) Pin1

Quadrant

TS3L501ERUAR WQFN RUA 42 3000 330.0 16.4 3.8 9.3 1.0 8.0 16.0 Q1

PACKAGE MATERIALS INFORMATION

www.ti.com 15-Apr-2020

Pack Materials-Page 1

I TEXAS INSTRUMENTS TAPE AND REEL BOX DIMENSIONS

*All dimensions are nominal

Device Package Type Package Drawing Pins SPQ Length (mm) Width (mm) Height (mm)

TS3L501ERUAR WQFN RUA 42 3000 358.0 335.0 35.0

TS3L501ERUAR WQFN RUA 42 3000 367.0 367.0 38.0

PACKAGE MATERIALS INFORMATION

www.ti.com 15-Apr-2020

Pack Materials-Page 2

www.ti.com

GENERIC PACKAGE VIEW

This image is a representation of the package family, actual package may vary.

Refer to the product data sheet for package details.

WQFN - 0.8 mm max heightRUA 42

PLASTIC QUAD FLATPACK - NO LEAD

9 x 3.5, 0.5 mm pitch

4226504/A

I 1 i :E 41+ , CCCCCCCCECCCCCCCC\ , [a Q ‘ 7 m \ i a 4 “73333333333333? ,TT , Vt Lrw r|m|L ﬂﬂ

www.ti.com

PACKAGE OUTLINE

3.6

3.4

9.1

8.9

0.8

0.6

0.05

0.00

2X 8

38X 0.5

2X 1.5

42X 0.5

0.3

42X 0.3

0.2

7.55 0.1

2.05 0.1

(0.1) TYP

WQFN - 0.8 mm max heightRUA0042A

PLASTIC QUAD FLATPACK - NO LEAD

4219139/A 03/2020

0.08 C

0.1 C A B

0.05

NOTES:

1. All linear dimensions are in millimeters. Any dimensions in parenthesis are for reference only. Dimensioning and tolerancing

per ASME Y14.5M.

2. This drawing is subject to change without notice.

3. The package thermal pad must be soldered to the printed circuit board for thermal and mechanical performance.

PIN 1 INDEX AREA

SEATING PLANE

PIN 1 ID

SYMM

EXPOSED

THERMAL PAD

SYMM

18 21

SCALE 1.800

/5 7 7 7,7,7 fig? Cpcho v (L EB@** L11 F: l 7 mfg? WEEEE , w‘l g 3F, 87 M Him ““7 o ”7 $$ﬁ$%@$x\7 v7¢

www.ti.com

EXAMPLE BOARD LAYOUT

38X (0.5)

(R0.05) TYP

0.05 MAX

ALL AROUND

0.05 MIN

ALL AROUND

1.17 TYP

(0.775)

TYP

42X (0.6)

42X (0.25)

(3.3)

(8.8)(7.55)

(2.05)

( 0.2) TYP

VIA

(3.525) TYP

WQFN - 0.8 mm max heightRUA0042A

PLASTIC QUAD FLATPACK - NO LEAD

4219139/A 03/2020

NOTES: (continued)

4. This package is designed to be soldered to a thermal pad on the board. For more information, see Texas Instruments literature

number SLUA271 (www.ti.com/lit/slua271).

5. Vias are optional depending on application, refer to device data sheet. If any vias are implemented, refer to their locations shown

on this view. It is recommended that vias under paste be filled, plugged or tented.

SYMM

LAND PATTERN EXAMPLE

EXPOSED METAL SHOWN

SCALE: 10X

SEE SOLDER MASK

DETAIL

18 21

METAL EDGE

SOLDER MASK

OPENING

EXPOSED

METAL

METAL UNDER

SOLDER MASK

OPENING

EXPOSED

METAL

NON SOLDER MASK

DEFINED

(PREFERRED)

SOLDER MASK DEFINED

SOLDER MASK DETAILS

ﬂ 4 j * ﬂ mmgﬁmmagmmﬁ Ev? “““ E 8+; x? H‘mjrﬁi maﬁa 7 E V E E E % ﬂat? $¢$$$$$ “““ P

www.ti.com

EXAMPLE STENCIL DESIGN

12X (0.92)

12X (0.97)

(0.585)

TYP

(0.56) TYP

42X (0.6)

42X (0.25)

38X (0.5)

(3.3)

(8.8)

(R0.05) TYP

WQFN - 0.8 mm max heightRUA0042A

PLASTIC QUAD FLATPACK - NO LEAD

4219139/A 03/2020

NOTES: (continued)

6. Laser cutting apertures with trapezoidal walls and rounded corners may offer better paste release. IPC-7525 may have alternate

design recommendations.

SOLDER PASTE EXAMPLE

BASED ON 0.125 MM THICK STENCIL

SCALE: 12X

EXPOSED PAD 43

69% PRINTED SOLDER COVERAGE BY AREA UNDER PACKAGE

SYMM

18 21

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Datenblatt für TS3L501E von Texas Instruments

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