Datenblatt für MC74HC10A von onsemi

© Semiconductor Components Industries, LLC, 2013
May, 2013 − Rev. 2
1Publication Order Number:
MC74HC10A/D
MC74HC10A
Triple 3-Input NAND Gate
High−Performance Silicon−Gate CMOS
The MC74HC10A is identical in pinout to the LS10. The device
inputs are compatible with Standard CMOS outputs; with pullup
resistors, they are compatible with LSTTL outputs.
Features
•Output Drive Capability: 10 LSTTL Loads
•Outputs Directly Interface to CMOS, NMOS and TTL
•Operating Voltage Range: 2 to 6 V
•Low Input Current: 1 mA
•High Noise Immunity Characteristic of CMOS Devices
•In Compliance With the Requirements Defined JEDEC
Standard No. 7 A
•Chip Complexity: 36 FETs or 9 Equivalent Gates
•These are Pb−Free Devices
LOGIC DIAGRAM
PIN 14 = VCC
PIN 7 = GND
Y = ABC
A1
B1
C1
A2
B2
C2
A3
B3
C3
Y1
1
2
13
Y2
Y3
3
4
5
9
10
11
12
6
8
PIN ASSIGNMENT
11
12
13
14
8
9
105
4
3
2
1
7
6
B3
C3
Y1
C1
VCC
Y3
A3
B2
A2
B1
A1
GND
Y2
C2
MARKING
DIAGRAMS
A = Assembly Location
WL, L = Wafer Lot
YY, Y = Year
WW, W = Work Week
G or = Pb−Free Package
L
L
H
H
L
H
L
H
FUNCTION TABLE
Inputs Output
AB
H
H
H
L
Y
See detailed ordering and shipping information in the package
dimensions section on page 4 of this data sheet.
ORDERING INFORMATION
http://onsemi.com
TSSOP−14
DT SUFFIX
CASE 948G
14
1
SOIC−14
D SUFFIX
CASE 751A
14
1
HC10AG
AWLYWW
1
14
HC
10A
ALYW
1
14
(Note: Microdot may be in either location)
MC74HC10A
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2
MAXIMUM RATINGS*
Symbol Parameter Value Unit
VCC DC Supply Voltage (Referenced to GND) – 0.5 to + 7.0 V
Vin DC Input Voltage (Referenced to GND) – 0.5 to VCC + 0.5 V
Vout DC Output Voltage (Referenced to GND) – 0.5 to VCC + 0.5 V
Iin DC Input Current, per Pin ±20 mA
Iout DC Output Current, per Pin ±25 mA
ICC DC Supply Current, VCC and GND Pins ±50 mA
PDPower Dissipation in Still Air SOIC Package†
TSSOP Package†
500
450
mW
Tstg Storage Temperature – 65 to + 150 C
TLLead Temperature, 1 mm from Case for 10 Seconds
(SOIC or TSSOP Package) 260
C
Stresses exceeding Maximum Ratings may damage the device. Maximum Ratings are stress
ratings only. Functional operation above the Recommended Operating Conditions is not implied.
Extended exposure to stresses above the Recommended Operating Conditions may affect device
reliability.
†Derating — SOIC Package: –7 mW/C from 65 to 125C
TSSOP Package: − 6.1 mW/C from 65 to 125C
RECOMMENDED OPERATING CONDITIONS
Symbol Parameter Min Max Unit
VCC DC Supply Voltage (Referenced to GND) 2.0 6.0 V
Vin, Vout DC Input Voltage, Output Voltage (Referenced to GND) 0 VCC V
TAOperating Temperature, All Package Types – 55 + 125 C
tr, tfInput Rise and Fall Time VCC = 2.0 V
(Figure 1) VCC = 3.0 V
VCC = 4.5 V
VCC = 6.0 V
0
0
0
0
1000
600
500
400
ns
This device contains protection
circuitry to guard against damage
due to high static voltages or electric
fields. However, precautions must
be taken to avoid applications of any
voltage higher than maximum rated
voltages to this high−impedance cir-
cuit. For proper operation, Vin and
Vout should be constrained to the
range GND v (Vin or Vout) v VCC.
Unused inputs must always be
tied to an appropriate logic voltage
level (e.g., either GND or VCC).
Unused outputs must be left open.
MC74HC10A
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3
DC ELECTRICAL CHARACTERISTICS (Voltages Referenced to GND)
Symbol Parameter Test Conditions
VCC
V
Guaranteed Limit
Unit
– 55 to
25Cv 85Cv 125C
VIH Minimum High−Level Input
Voltage
Vout = 0.1 V or VCC – 0.1 V
|Iout| v 20 μA
2.0
3.0
4.5
6.0
1.5
2.1
3.15
4.2
1.5
2.1
3.15
4.2
1.5
2.1
3.15
4.2
V
VIL Maximum Low−Level Input
Voltage
Vout = 0.1 V or VCC – 0.1 V
|Iout| v 20 μA
2.0
3.0
4.5
6.0
0.5
0.9
1.35
1.8
0.5
0.9
1.35
1.8
0.5
0.9
1.35
1.8
V
VOH Minimum High−Level Output
Voltage
Vin = VIH or VIL
|Iout| v 20 μA
2.0
4.5
6.0
1.9
4.4
5.9
1.9
4.4
5.9
1.9
4.4
5.9
V
Vin = VIH or VIL |Iout| v 2.4 mA
|Iout| v 4.0 mA
|Iout| v 5.2 mA
3.0
4.5
6.0
2.48
3.98
5.48
2.34
3.84
5.34
2.20
3.70
5.20
VOL Maximum Low−Level Output
Voltage
Vin = VIH
|Iout| v 20 μA
2.0
4.5
6.0
0.1
0.1
0.1
0.1
0.1
0.1
0.1
0.1
0.1
V
Vin = VIH or VIL |Iout| v 2.4 mA
|Iout| v 4.0 mA
|Iout| v 5.2 mA
3.0
4.5
6.0
0.26
0.26
0.26
0.33
0.33
0.33
0.40
0.40
0.40
Iin Maximum Input Leakage Current Vin = VCC or GND 6.0 ±0.1 ±1.0 ±1.0 μA
ICC Maximum Quiescent Supply
Current (per Package)
Vin = VCC or GND
Iout = 0 μA
6.0 1 10 40 μA
AC ELECTRICAL CHARACTERISTICS (CL = 50 pF, Input tr = tf = 6 ns)
Symbol Parameter
VCC
V
Guaranteed Limit
Unit
– 55 to
25Cv 85Cv 125C
tPLH,
tPHL
Maximum Propagation Delay, Input A, B, or C to Output Y
(Figures 1 and 2)
2.0
3.0
4.5
6.0
95
45
19
16
120
60
24
20
145
75
29
25
ns
tTLH,
tTHL
Maximum Output Transition Time, Any Output
(Figures 1 and 2)
2.0
3.0
4.5
6.0
75
30
15
13
95
40
19
16
110
55
22
19
ns
Cin Maximum Input Capacitance — 10 10 10 pF
CPD Power Dissipation Capacitance (Per Gate)*
Typical @ 25°C, VCC = 5.0 V
pF
25
* Used to determine the no−load dynamic power consumption: PD = CPD VCC2f + ICC VCC.
ML a? ¥
MC74HC10A
http://onsemi.com
4
Y
B
C
Figure 1. Switching Waveforms
INPUT
A, B, OR C
OUTPUT Y
tftrVCC
GND
tPHL
tPLH
tTLH tTHL
90%
50%
10%
90%
50%
10%
A
EXPANDED LOGIC DIAGRAM
(1/3 OF THE DEVICE)
*Includes all probe and jig capacitance
CL*
TEST POINT
DEVICE
UNDER
TEST
OUTPUT
Figure 2. Test Circuit
ORDERING INFORMATION
Device Package Shipping†
MC74HC10ADTG TSSOP−14
(Pb−Free) 96 Units/Tube
MC74HC10ADG SOIC−14
(Pb−Free) 55 Units/Rail
MC74HC10ADR2G SOIC−14
(Pb−Free) 2500/Tape & Reel
MC74HC10ADTR2G TSSOP−14*
†For information on tape and reel specifications, including part orientation and tape sizes, please refer to our Tape and Reel Packaging
Specifications Brochure, BRD8011/D.
*This package is inherently Pb−Free.
0N Semiwndudw" m 1% £1 HHHHHHH T ‘5 fl 0 HHHHHHH mmaa mm [H N wn EDD Umm 4 ON Semxcunduchv and are Mademavk: av Semmanduclur Campunenls Inuwnaa LLC dba ON Samanauaxar Dr H: suaamanas m xna Umled sxaxaa andJm mhev comma: ON Semxcunduclar vesewe: we th| [a make change: wuhum Yunhev name [a any prnduns havem ON Semanduc‘m makes m7 wanamy represenlalmn m guarantee regardmg ma sumahmy at W; manuals can any pamcu‘av purpase nnv dues ON Semumndudm assume any Mammy ansmg mac xna apphcahan m we no any pmduclnv mum and :pecmcafly dwsc‘axms any and au Mammy mcmdmg wmnam hmma‘mn spema‘ cansequenha‘ m \nmdenla‘ damages ON Sammnauaxar dues nn| aanyay any hcense under Ms pa|em thls nar xna ngma av n|hers
SOIC−14 NB
CASE 751A−03
ISSUE L
DATE 03 FEB 2016
SCALE 1:1
1
14
GENERIC
MARKING DIAGRAM*
XXXXXXXXXG
AWLYWW
1
14
XXXXX = Specific Device Code
A = Assembly Location
WL = Wafer Lot
Y = Year
WW = Work Week
G = Pb−Free Package
*This information is generic. Please refer to
device data sheet for actual part marking.
Pb−Free indicator, “G” or microdot “ G”,
may or may not be present.
STYLES ON PAGE 2
NOTES:
1. DIMENSIONING AND TOLERANCING PER
ASME Y14.5M, 1994.
2. CONTROLLING DIMENSION: MILLIMETERS.
3. DIMENSION b DOES NOT INCLUDE DAMBAR
PROTRUSION. ALLOWABLE PROTRUSION
SHALL BE 0.13 TOTAL IN EXCESS OF AT
MAXIMUM MATERIAL CONDITION.
4. DIMENSIONS D AND E DO NOT INCLUDE
MOLD PROTRUSIONS.
5. MAXIMUM MOLD PROTRUSION 0.15 PER
SIDE.
H
14 8
71
M
0.25 B M
C
h
X 45
SEATING
PLANE
A1
A
M
_
S
A
M
0.25 B S
C
b
13X
B
A
E
D
e
DETAIL A
L
A3
DETAIL A
DIM MIN MAX MIN MAX
INCHESMILLIMETERS
D8.55 8.75 0.337 0.344
E3.80 4.00 0.150 0.157
A1.35 1.75 0.054 0.068
b0.35 0.49 0.014 0.019
L0.40 1.25 0.016 0.049
e1.27 BSC 0.050 BSC
A3 0.19 0.25 0.008 0.010
A1 0.10 0.25 0.004 0.010
M0 7 0 7
H5.80 6.20 0.228 0.244
h0.25 0.50 0.010 0.019
__ __
6.50
14X
0.58
14X
1.18
1.27
DIMENSIONS: MILLIMETERS
1
PITCH
SOLDERING FOOTPRINT*
*For additional information on our Pb−Free strategy and soldering
details, please download the ON Semiconductor Soldering and
Mounting Techniques Reference Manual, SOLDERRM/D.
0.10
MECHANICAL CASE OUTLINE
PACKAGE DIMENSIONS
ON Semiconductor and are trademarks of Semiconductor Components Industries, LLC dba ON Semiconductor or its subsidiaries in the United States and/or other countries.
ON Semiconductor reserves the right to make changes without further notice to any products herein. ON Semiconductor makes no warranty, representation or guarantee regarding
the suitability of its products for any particular purpose, nor does ON Semiconductor assume any liability arising out of the application or use of any product or circuit, and specifically
disclaims any and all liability, including without limitation special, consequential or incidental damages. ON Semiconductor does not convey any license under its patent rights nor the
rights of others.
98ASB42565B
DOCUMENT NUMBER:
DESCRIPTION:
Electronic versions are uncontrolled except when accessed directly from the Document Repository.
Printed versions are uncontrolled except when stamped “CONTROLLED COPY” in red.
PAGE 1 OF 2
SOIC−14 NB
© Semiconductor Components Industries, LLC, 2019 www.onsemi.com
ON Semxcunduclm and ave hademavks av Semxcanduclur Campunenls lnduslnes. uc dha ON Semxcanduclar Dr K: suhsxdmnes m xna Umled sxaxas andJm mhev cmm‘nes ON Semxcunduclar vesewes me “gm to make changes wuhum mnna. mouse to any pruduns necem ON Semanduc‘m makes nu wanamy. represenlalmn m guarantee regardmg ma sumahmly at W; manual: can any pamcu‘av purpase nnv dues ON Semumnduclm assume any Mammy snsmg mm xna aapncauan m use M any pmduclnv mum and specmcsl‘y dwsc‘axms any and an Mammy mc‘udmg wxlham hmma‘mn spema‘ cansequemm m \nmdeula‘ damages ON Semxmnduclar dues nn| away any hcense under Ms pa|EM nghls Ivar xna ngms av n|hers
SOIC−14
CASE 751A−03
ISSUE L
DATE 03 FEB 2016
STYLE 7:
PIN 1. ANODE/CATHODE
2. COMMON ANODE
3. COMMON CATHODE
4. ANODE/CATHODE
5. ANODE/CATHODE
6. ANODE/CATHODE
7. ANODE/CATHODE
8. ANODE/CATHODE
9. ANODE/CATHODE
10. ANODE/CATHODE
11. COMMON CATHODE
12. COMMON ANODE
13. ANODE/CATHODE
14. ANODE/CATHODE
STYLE 5:
PIN 1. COMMON CATHODE
2. ANODE/CATHODE
3. ANODE/CATHODE
4. ANODE/CATHODE
5. ANODE/CATHODE
6. NO CONNECTION
7. COMMON ANODE
8. COMMON CATHODE
9. ANODE/CATHODE
10. ANODE/CATHODE
11. ANODE/CATHODE
12. ANODE/CATHODE
13. NO CONNECTION
14. COMMON ANODE
STYLE 6:
PIN 1. CATHODE
2. CATHODE
3. CATHODE
4. CATHODE
5. CATHODE
6. CATHODE
7. CATHODE
8. ANODE
9. ANODE
10. ANODE
11. ANODE
12. ANODE
13. ANODE
14. ANODE
STYLE 1:
PIN 1. COMMON CATHODE
2. ANODE/CATHODE
3. ANODE/CATHODE
4. NO CONNECTION
5. ANODE/CATHODE
6. NO CONNECTION
7. ANODE/CATHODE
8. ANODE/CATHODE
9. ANODE/CATHODE
10. NO CONNECTION
11. ANODE/CATHODE
12. ANODE/CATHODE
13. NO CONNECTION
14. COMMON ANODE
STYLE 3:
PIN 1. NO CONNECTION
2. ANODE
3. ANODE
4. NO CONNECTION
5. ANODE
6. NO CONNECTION
7. ANODE
8. ANODE
9. ANODE
10. NO CONNECTION
11. ANODE
12. ANODE
13. NO CONNECTION
14. COMMON CATHODE
STYLE 4:
PIN 1. NO CONNECTION
2. CATHODE
3. CATHODE
4. NO CONNECTION
5. CATHODE
6. NO CONNECTION
7. CATHODE
8. CATHODE
9. CATHODE
10. NO CONNECTION
11. CATHODE
12. CATHODE
13. NO CONNECTION
14. COMMON ANODE
STYLE 8:
PIN 1. COMMON CATHODE
2. ANODE/CATHODE
3. ANODE/CATHODE
4. NO CONNECTION
5. ANODE/CATHODE
6. ANODE/CATHODE
7. COMMON ANODE
8. COMMON ANODE
9. ANODE/CATHODE
10. ANODE/CATHODE
11. NO CONNECTION
12. ANODE/CATHODE
13. ANODE/CATHODE
14. COMMON CATHODE
STYLE 2:
CANCELLED
ON Semiconductor and are trademarks of Semiconductor Components Industries, LLC dba ON Semiconductor or its subsidiaries in the United States and/or other countries.
ON Semiconductor reserves the right to make changes without further notice to any products herein. ON Semiconductor makes no warranty, representation or guarantee regarding
the suitability of its products for any particular purpose, nor does ON Semiconductor assume any liability arising out of the application or use of any product or circuit, and specifically
disclaims any and all liability, including without limitation special, consequential or incidental damages. ON Semiconductor does not convey any license under its patent rights nor the
rights of others.
98ASB42565B
DOCUMENT NUMBER:
DESCRIPTION:
Electronic versions are uncontrolled except when accessed directly from the Document Repository.
Printed versions are uncontrolled except when stamped “CONTROLLED COPY” in red.
PAGE 2 OF 2
SOIC−14 NB
© Semiconductor Components Industries, LLC, 2019 www.onsemi.com
0N Semiwndudw" m j I-QIEE O E}THHHHHHH E, a 5% Fair ‘0 Q015(0.uos)'ru® HHHHHHH 4" r7 i g E135 3-. n 46L 4 DETAILE/I mm: HHHHHHH XXXX r—fl a . ‘ |:| HHHHHHH |:| dewce Pb-F may :I |:| |:| ‘ E T “Tm W ON Samaanuuamy and are Mademavk: av Samanaucxar Cnmpunenls Inuwnas LLC dba ON Samanaucxar Dr H: suaamanas m xna Umled sxaxas andJm mhev comma: ON Samaanaucxar vesewe: we th| [a make change: wuhum Yunhev fights [a any prnduns havem ON Semanduc‘m makes m7 wanamy represenlalmn m guarantee regardmg ma sumahmy at W; manuals can any pamcu‘av purpase nnv dues ON Semumndudm assume any Mammy ansmg mac xna apphcahan m me no any pmduclnv mum and :pecmcafly dwsc‘axms any and au Mammy mcmdmg wmnam hmma‘mn spema‘ cansequenha‘ m \nmdenla‘ damages ON Sammnaucxar dues nn| convey any hcense under Ms pa|em nghls nar xna ngms av n|hers
TSSOP−14 WB
CASE 948G
ISSUE C
DATE 17 FEB 2016
SCALE 2:1
1
14
*This information is generic. Please refer to
device data sheet for actual part marking.
Pb−Free indicator, “G” or microdot “ G”,
may or may not be present.
DIM MIN MAX MIN MAX
INCHESMILLIMETERS
A4.90 5.10 0.193 0.200
B4.30 4.50 0.169 0.177
C−−− 1.20 −−− 0.047
D0.05 0.15 0.002 0.006
F0.50 0.75 0.020 0.030
G0.65 BSC 0.026 BSC
H0.50 0.60 0.020 0.024
J0.09 0.20 0.004 0.008
J1 0.09 0.16 0.004 0.006
K0.19 0.30 0.007 0.012
K1 0.19 0.25 0.007 0.010
L6.40 BSC 0.252 BSC
M0 8 0 8
NOTES:
1. DIMENSIONING AND TOLERANCING PER
ANSI Y14.5M, 1982.
2. CONTROLLING DIMENSION: MILLIMETER.
3. DIMENSION A DOES NOT INCLUDE MOLD
FLASH, PROTRUSIONS OR GATE BURRS.
MOLD FLASH OR GATE BURRS SHALL NOT
EXCEED 0.15 (0.006) PER SIDE.
4. DIMENSION B DOES NOT INCLUDE
INTERLEAD FLASH OR PROTRUSION.
INTERLEAD FLASH OR PROTRUSION SHALL
NOT EXCEED 0.25 (0.010) PER SIDE.
5. DIMENSION K DOES NOT INCLUDE DAMBAR
PROTRUSION. ALLOWABLE DAMBAR
PROTRUSION SHALL BE 0.08 (0.003) TOTAL
IN EXCESS OF THE K DIMENSION AT
MAXIMUM MATERIAL CONDITION.
6. TERMINAL NUMBERS ARE SHOWN FOR
REFERENCE ONLY.
7. DIMENSION A AND B ARE TO BE
DETERMINED AT DATUM PLANE −W−.
____
S
U0.15 (0.006) T
2X L/2
S
U
M
0.10 (0.004) V S
T
L−U−
SEATING
PLANE
0.10 (0.004)
−T−
SECTION N−N
DETAIL E
JJ1
K
K1
DETAIL E
F
M
−W−
0.25 (0.010)
8
14
7
1
PIN 1
IDENT.
H
G
A
D
C
B
S
U0.15 (0.006) T
−V−
14X REFK
N
N
GENERIC
MARKING DIAGRAM*
XXXX
XXXX
ALYWG
G
1
14
A = Assembly Location
L = Wafer Lot
Y = Year
W = Work Week
G= Pb−Free Package
7.06
14X
0.36 14X
1.26
0.65
DIMENSIONS: MILLIMETERS
1
PITCH
SOLDERING FOOTPRINT
(Note: Microdot may be in either location)
MECHANICAL CASE OUTLINE
PACKAGE DIMENSIONS
ON Semiconductor and are trademarks of Semiconductor Components Industries, LLC dba ON Semiconductor or its subsidiaries in the United States and/or other countries.
ON Semiconductor reserves the right to make changes without further notice to any products herein. ON Semiconductor makes no warranty, representation or guarantee regarding
the suitability of its products for any particular purpose, nor does ON Semiconductor assume any liability arising out of the application or use of any product or circuit, and specifically
disclaims any and all liability, including without limitation special, consequential or incidental damages. ON Semiconductor does not convey any license under its patent rights nor the
rights of others.
98ASH70246A
DOCUMENT NUMBER:
DESCRIPTION:
Electronic versions are uncontrolled except when accessed directly from the Document Repository.
Printed versions are uncontrolled except when stamped “CONTROLLED COPY” in red.
PAGE 1 OF 1
TSSOP−14 WB
© Semiconductor Components Industries, LLC, 2019 www.onsemi.com
a a e lrademavks av Semxcunduclm Cnmvnnems In "sine \ghlsmanumhernlpalems \rademavks Dav www menu cumrsuerguwaxem Mavkmg gm 9 www nnserm cum
www.onsemi.com
1
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