Datenblatt für CSD17309Q3 von Texas Instruments

V'.‘ ‘F. B X E ITEXAS INSTRUMENTS , V, W 1 r’ , ‘ L, ‘ H ”J 1 F} r’ 71 ‘ ’7 L, ”J ‘ W ‘ ‘ ,1 ‘ L, % 1 Is a am am
VGS - Gate-to-Source Voltage - V
RDS(on) - On-State Resistance - mΩ
0 1 2 3 4 5 6 7 8 9 10
0
2
4
6
8
10
12
14
16
TC = 25°C
TC = 125°C
G006
ID = 18A
Qg - Gate Charge - nC
0 2 4 6 8 10 12
0
1
2
3
4
5
6
7
8
1
3
5
7
G003
ID = 18A
VDS = 15V
1D
2D
3D
4
D
D
5
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7
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CSD17309Q3
SLPS261B –MARCH 2010–REVISED SEPTEMBER 2014
CSD17309Q3 30-V N-Channel NexFET™ Power MOSFET
1 Features Product Summary
1• Optimized for 5 V Gate Drive TA= 25°C TYPICAL VALUE UNIT
• Ultra-Low Qgand Qgd VDS Drain-to-Source Voltage 30 V
• Low Thermal Resistance QgGate Charge Total (4.5 V) 7.5 nC
Qgd Gate Charge Gate-to-Drain 1.7 nC
• Avalanche Rated
VGS = 3 V 6.3
• Pb Free Terminal Plating RDS(on) Drain-to-Source On-Resistance VGS = 4.5 V 4.9 mΩ
• RoHS Compliant VGS = 8 V 4.2
• Halogen Free VGS(th) Threshold Voltage 1.2 V
• SON 3.3 mm × 3.3 mm Plastic Package
.
2 Applications Ordering Information(1)
Device Media Qty Package Ship
• Notebook Point of Load
CSD17309Q3 13-Inch Reel 2500 SON 3.3 × 3.3 mm Tape and
• Point of Load Synchronous Buck in Networking, Plastic Package Reel
CSD17309Q3T 7-Inch Reel 250
Telecom, and Computing Systems
(1) For all available packages, see the orderable addendum at
the end of the data sheet.
3 Description
This 30 V, 4.2 mΩNexFET™ power MOSFET is Absolute Maximum Ratings
designed to minimize losses in power conversion TA= 25°C VALUE UNIT
applications and optimized for 5 V gate drive VDS Drain-to-Source Voltage 30 V
applications.
VGS Gate-to-Source Voltage +10 / –8 V
Top View Continuous Drain Current, TC= 25°C 60 A
IDContinuous Drain Current(1) 20 A
IDM Pulsed Drain Current, TA= 25°C(2) 112 A
PDPower Dissipation(1) 2.8 W
TJ, Operating Junction and –55 to 150 °C
Tstg Storage Temperature Range
Avalanche Energy, Single Pulse
EAS 162 mJ
ID= 57 A, L = 0.1 mH, RG= 25 Ω
(1) Typical RθJA = 45°C/W when mounted on a 1 inch2(6.45
cm2), 2 oz. (0.071 mm thick) Cu pad on a
0.06 inch (1.52 mm) thick FR4 PCB.
(2) Pulse duration ≤300 μs, duty cycle ≤2%.
Spacing
RDS(on) vs VGS Gate Charge
1
An IMPORTANT NOTICE at the end of this data sheet addresses availability, warranty, changes, use in safety-critical applications,
intellectual property matters and other important disclaimers. PRODUCTION DATA.
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SLPS261B –MARCH 2010–REVISED SEPTEMBER 2014
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Table of Contents
6.1 Trademarks............................................................... 8
1 Features.................................................................. 16.2 Electrostatic Discharge Caution................................ 8
2 Applications ........................................................... 16.3 Glossary.................................................................... 8
3 Description ............................................................. 17 Mechanical, Packaging, and Orderable
4 Revision History..................................................... 2Information ............................................................. 9
5 Specifications......................................................... 37.1 Q3 Package Dimensions .......................................... 9
5.1 Electrical Characteristics........................................... 37.2 Recommended PCB Pattern................................... 10
5.2 Thermal Information.................................................. 37.3 Recommended Stencil Opening ............................. 10
5.3 Typical MOSFET Characteristics.............................. 47.4 Q3 Tape and Reel Information................................ 11
6 Device and Documentation Support.................... 8
4 Revision History
Changes from Revision A (October 2010) to Revision B Page
• ................................................................................................................................................................................................ 1
• Added 7" reel to Ordering Information ................................................................................................................................... 1
• Updated mechanical information ........................................................................................................................................... 9
Changes from Original (March 2010) to Revision A Page
• Deleted the Package Marking Information section .............................................................................................................. 11
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SLPS261B –MARCH 2010–REVISED SEPTEMBER 2014
5 Specifications
5.1 Electrical Characteristics
(TA= 25°C unless otherwise stated)
PARAMETER TEST CONDITIONS MIN TYP MAX UNIT
STATIC CHARACTERISTICS
BVDSS Drain-to-Source Voltage VGS = 0 V, ID= 250 μA 30 V
IDSS Drain-to-Source Leakage Current VGS = 0 V, VDS = 24 V 1 μA
IGSS Gate-to-Source Leakage Current VDS = 0 V, VGS = +10 / –8 V 100 nA
VGS(th) Gate-to-Source Threshold Voltage VDS = VGS, ID= 250 μA 0.9 1.2 1.7 V
VGS = 3 V, ID= 18 A 6.3 8.5 mΩ
RDS(on) Drain-to-Source On-Resistance VGS = 4.5 V, ID= 18 A 4.9 6.3 mΩ
VGS = 8 V, ID= 18 A 4.2 5.4 mΩ
gƒs Transconductance VDS = 15 V, ID= 18 A 67 S
DYNAMIC CHARACTERISTICS
CISS Input Capacitance 1150 1440 pF
VGS = 0 V, VDS = 15 V,
COSS Output Capacitance 580 750 pF
ƒ = 1 MHz
CRSS Reverse Transfer Capacitance 43 56 pF
RgSeries Gate Resistance 1.2 2.4 Ω
QgGate Charge Total (4.5 V) 7.5 10 nC
Qgd Gate Charge Gate-to-Drain 1.7 nC
VDS = 15 V, ID= 18 A
Qgs Gate Charge Gate-to-Source 2.5 nC
Qg(th) Gate Charge at Vth 1.3 nC
QOSS Output Charge VDS = 13 V, VGS = 0 V 15 nC
td(on) Turn On Delay Time 6.1 ns
trRise Time 9.9 ns
VDS = 15 V, VGS = 4.5 V,
ID= 18 A , RG= 2 Ω
td(off) Turn Off Delay Time 13.2 ns
tƒFall Time 3.6 ns
DIODE CHARACTERISTICS
VSD Diode Forward Voltage IDS = 18 A, VGS = 0 V 0.85 1 V
Qrr Reverse Recovery Charge 30 nC
VDD = 13 V, IF= 18 A,
di/dt = 300 A/μs
trr Reverse Recovery Time 23 ns
5.2 Thermal Information
(TA= 25°C unless otherwise stated)
THERMAL METRIC MIN TYP MAX UNIT
RθJC Junction-to-Case Thermal Resistance(1) 2.0 °C/W
RθJA Junction-to-Ambient Thermal Resistance(1)(2) 57
(1) RθJC is determined with the device mounted on a 1 inch2(6.45 cm2), Cu pad on a 1.5 inches × 1.5 inches thick FR4 PCB. RθJC is
specified by design, whereas RθJA is determined by the user’s board design.
(2) Device mounted on FR4 material with 1 inch22-oz.Cu.
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l TEXAS INSTRUMENTS GATE Suurte GATE Suurce E : wflfl "' a , Pal / Gn‘z
t - Pulse Duration - s
p
0.001 0.01 0.1 1 10 100 1k
0.001
0.01
0.1
1
10
G012
Z - Normalized Thermal Impedance
qJA
Duty Cycle = t /t
1 2
t1
t2
Typical R = 139 C/W (min Cu)
T = P Z R
q
q q
JA
J JA JA
°
´ ´
P
Single Pulse
0.01
0.02
0.05
0.1
0.3
0.5
GATE Source
DRAIN
M0161-02
CSD17309Q3
SLPS261B –MARCH 2010–REVISED SEPTEMBER 2014
www.ti.com
Max RθJA = 57°C/W Max RθJA = 174°C/W
when mounted on when mounted on a
1 inch2(6.45 cm2) of minimum pad area of
2 oz. (0.071 mm thick) 2 oz. (0.071 mm thick)
Cu. Cu.
5.3 Typical MOSFET Characteristics
(TA= 25°C unless otherwise stated)
Figure 1. Transient Thermal Impedance
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l TEXAS INSTRUMENTS 50 bu Gum Ganz em Gum
Qg - Gate Charge - nC
0 2 4 6 8 10 12
0
1
2
3
4
5
6
7
8
1
3
5
7
G003
ID = 18A
VDS = 15V
VDS - Drain-to-Source Voltage - V
C - Capacitance - nF
0 5 10 15 20 25 30
0
0.5
1
1.5
2
2.5
3
Ciss = Cgd + Cgs
Coss = Cds + Cgd
Crss = CGgd
G004
f = 1MHz
VGS = 0V
VDS - Drain-to-Source Voltage - V
IDS - Drain-to-Source Current - A
0 0.2 0.4 0.6 0.8 1
0
5
10
15
20
25
30
35
40
45
50
VGS = 2.5V
VGS = 3V
VGS = 3.5V
VGS = 4.5V
VGS = 8V
G001
VGS - Gate-to-Source Voltage - V
IDS - Drain-to-Source Current - A
1 1.2 1.4 1.6 1.8 2 2.2 2.4 2.6 2.8 3
0
5
10
15
20
25
30
35
40
45
50
5
15
25
35
45
TC = 125°C
TC = 25°C
TC = -55°C
G002
VDS = 5V
CSD17309Q3
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SLPS261B –MARCH 2010–REVISED SEPTEMBER 2014
Typical MOSFET Characteristics (continued)
(TA= 25°C unless otherwise stated)
Figure 2. Saturation Characteristics Figure 3. Transfer Characteristics
Figure 4. Gate Charge Figure 5. Capacitance
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l TEXAS INSTRUMENTS 1a 16 Guns noun 1a 100 Gum ma
TC - Case Temperature - °C
Normalized On-State Resistance
-75 -25 25 75 125 175
0.2
0.4
0.6
0.8
1
1.2
1.4
1.6
G007
ID = 18A
VGS = 8V
VSD - Source-to-Drain Voltage - V
ISD - Source-to-Drain Current - A
0 0.2 0.4 0.6 0.8 1
0.0001
0.001
0.01
0.1
1
10
100
TC = 25°C
TC = 125°C
G008
TC - Case Temperature - °C
VGS(th) - Threshold Voltage - V
-75 -25 25 75 125 175
0
0.2
0.4
0.6
0.8
1
1.2
1.4
1.6
G005
ID = 250µA
VGS - Gate-to-Source Voltage - V
RDS(on) - On-State Resistance - mΩ
0 1 2 3 4 5 6 7 8 9 10
0
2
4
6
8
10
12
14
16
TC = 25°C
TC = 125°C
G006
ID = 18A
CSD17309Q3
SLPS261B –MARCH 2010–REVISED SEPTEMBER 2014
www.ti.com
Typical MOSFET Characteristics (continued)
(TA= 25°C unless otherwise stated)
Figure 6. Threshold Voltage vs Temperature Figure 7. On-State Resistance vs Gate-to-Source Voltage
Figure 8. Normalized On-State Resistance vs Temperature Figure 9. Typical Diode Forward Voltage
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l TEXAS INSTRUMENTS emu 1o Gnu
TC - Case Temperature - °C
IDS - Drain-to-Source Current - A
-50 -25 0 25 50 75 100 125 150 175
0
10
20
30
40
50
60
70
G011
VDS - Drain-to-Source Voltage - V
0.01 0.1 1 10 100
0.01
0.1
1
10
100
1k
1ms
10ms
11110
1s
DC
100ms
G009
Area Limited
by RDS(on)
Single Pulse
Typical RθJA = 139°C/W (min Cu)
IDS - Drain-to-Source Current - A
t(AV) - Time in Avalanche - ms
0.01 0.1 1 10 100
1
10
100
1k
TC = 25°C
TC = 125°C
G010
I(AV) - Peak Avalanche Current - A
CSD17309Q3
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SLPS261B –MARCH 2010–REVISED SEPTEMBER 2014
Typical MOSFET Characteristics (continued)
(TA= 25°C unless otherwise stated)
Figure 10. Maximum Safe Operating Area (SOA) Figure 11. Single Pulse Unclamped Inductive Switching
Figure 12. Maximum Drain Current vs Temperature
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SLPS261B –MARCH 2010–REVISED SEPTEMBER 2014
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6 Device and Documentation Support
6.1 Trademarks
NexFET is a trademark of Texas Instruments.
6.2 Electrostatic Discharge Caution
These devices have limited built-in ESD protection. The leads should be shorted together or the device placed in conductive foam
during storage or handling to prevent electrostatic damage to the MOS gates.
6.3 Glossary
SLYZ022 —TI Glossary.
This glossary lists and explains terms, acronyms, and definitions.
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l TEXAS INSTRUMENTS K D m fiozsw a; H I‘" .1 L 1 % g _ O ‘ m m:| ‘ E—J m KLWJWWL, ,,,,,,, m N L 7, . ,Efj L m \ m w I:m ‘ :I ‘ *f a \ m m \ |:., g 1 L V " w 4H1 4 M I?“ Top View Sxde Vxew Bollom Vxew i f L A W Jr #— ‘ C D Front V‘ew
CSD17309Q3
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SLPS261B –MARCH 2010–REVISED SEPTEMBER 2014
7 Mechanical, Packaging, and Orderable Information
The following pages include mechanical, packaging, and orderable information. This information is the most
current data available for the designated devices. This data is subject to change without notice and revision of
this document. For browser-based versions of this data sheet, refer to the left-hand navigation.
7.1 Q3 Package Dimensions
DIM MILLIMETERS INCHES
MIN NOM MAX MIN NOM MAX
A 0.950 1.000 1.100 0.037 0.039 0.043
A1 0.000 0.000 0.050 0.000 0.000 0.002
b 0.280 0.340 0.400 0.011 0.013 0.016
b1 0.310 NOM 0.012 NOM
c 0.150 0.200 0.250 0.006 0.008 0.010
D 3.200 3.300 3.400 0.126 0.130 0.134
D2 1.650 1.750 1.800 0.065 0.069 0.071
d 0.150 0.200 0.250 0.006 0.008 0.010
d1 0.300 0.350 0.400 0.012 0.014 0.016
E 3.200 3.300 3.400 0.126 0.130 0.134
E2 2.350 2.450 2.550 0.093 0.096 0.100
e 0.650 TYP 0.026
H 0.35 0.450 0.550 0.014 0.018 0.022
K 0.650 TYP 0.026 TYP
L 0.35 0.450 0.550 0.014 0.018 0.022
L1 0 — 0 0 — 0
θ0 — 0 0 — 0
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l TEXAS INSTRUMENTS 27122541 —-I F; 0150003) Ll m U $0410 171.9004» 3 500 :I 0.560 0 630 0.500 {X a) 4» 4-1.020-D [X 2) '71 K 3 C7. «0.340 (x a) 1 0.450 L 0.22;— 3 320 4—1AA5—> ? B 0750 I 0310(x6) ,| ,7DD JL
CSD17309Q3
SLPS261B –MARCH 2010–REVISED SEPTEMBER 2014
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7.2 Recommended PCB Pattern
For recommended circuit layout for PCB designs, see application note SLPA005 –Reducing Ringing Through
PCB Layout Techniques.
7.3 Recommended Stencil Opening
All dimensions are in mm, unless otherwise specified.
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4.00 ±0.10 (See Note 1) 2.00 ±0.05
3.60
3.60
1.30
1.75 ±0.10
M0144-01
8.00 ±0.10
12.00 +0.30
–0.10
5.50 ±0.05
Ø 1.50 +0.10
–0.00
CSD17309Q3
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SLPS261B –MARCH 2010–REVISED SEPTEMBER 2014
7.4 Q3 Tape and Reel Information
Notes:
1. 10 sprocket hole pitch cumulative tolerance ±0.2
2. Camber not to exceed 1 mm IN 100 mm, noncumulative over 250 mm
3. Material: black static dissipative polystyrene
4. All dimensions are in mm (unless otherwise specified).
5. Thickness: 0.30 ±0.05 mm
6. MSL1 260°C (IR and Convection) PbF-Reflow compatible
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PACKAGE OPTION ADDENDUM
www.ti.com 10-Dec-2020
Addendum-Page 1
PACKAGING INFORMATION
Orderable Device Status
(1)
Package Type Package
Drawing Pins Package
Qty Eco Plan
(2)
Lead finish/
Ball material
(6)
MSL Peak Temp
(3)
Op Temp (°C) Device Marking
(4/5)
Samples
CSD17309Q3 ACTIVE VSON-CLIP DQG 8 2500 RoHS-Exempt
& Green SN Level-1-260C-UNLIM -55 to 150 CSD17309
(1) The marketing status values are defined as follows:
ACTIVE: Product device recommended for new designs.
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design.
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.
OBSOLETE: TI has discontinued the production of the device.
(2) RoHS: TI defines "RoHS" to mean semiconductor products that are compliant with the current EU RoHS requirements for all 10 RoHS substances, including the requirement that RoHS substance
do not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, "RoHS" products are suitable for use in specified lead-free processes. TI may
reference these types of products as "Pb-Free".
RoHS Exempt: TI defines "RoHS Exempt" to mean products that contain lead but are compliant with EU RoHS pursuant to a specific EU RoHS exemption.
Green: TI defines "Green" to mean the content of Chlorine (Cl) and Bromine (Br) based flame retardants meet JS709B low halogen requirements of <=1000ppm threshold. Antimony trioxide based
flame retardants must also meet the <=1000ppm threshold requirement.
(3) MSL, Peak Temp. - The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature.
(4) There may be additional marking, which relates to the logo, the lot trace code information, or the environmental category on the device.
(5) Multiple Device Markings will be inside parentheses. Only one Device Marking contained in parentheses and separated by a "~" will appear on a device. If a line is indented then it is a continuation
of the previous line and the two combined represent the entire Device Marking for that device.
(6) Lead finish/Ball material - Orderable Devices may have multiple material finish options. Finish options are separated by a vertical ruled line. Lead finish/Ball material values may wrap to two
lines if the finish value exceeds the maximum column width.
Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information
provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and
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