Datenblatt für CDCLVP2106EVM von Texas Instruments

I TEXAS INSTRUMENTS
User's Guide
SCAU037–August 2009
Low Additive Phase Noise Clock Buffer Evaluation Board
Figure 1. CDCLVP2106EVM Evaluation Board
Features:
• Easy-to-use evaluation board to fan out low phase noise clocks
• Easy device setup
• Fast configuration
• Control pins configurable through jumpers
• Board powered at +2.5-V/+3.3-V
• Single-ended or differential input clocks
• CDCLVP2106 supports 12 LVPECL outputs; CDCLVP2106EVM supports four LVPECL outputs
Contents
1 General Description ......................................................................................................... 2
2 Signal Path and Control Circuitry ......................................................................................... 2
3 Getting Started .............................................................................................................. 2
4 Input Clock Selection ....................................................................................................... 2
5 Output Clock ................................................................................................................. 3
6 Schematics and Layout .................................................................................................... 3
List of Figures
1 CDCLVP2106EVM Evaluation Board .................................................................................... 1
2 CDCLVP2106EVM—Schematic .......................................................................................... 3
3 CDCLVP2106EVM—Schematic .......................................................................................... 4
4 CDCLVP2106EVM—Schematic .......................................................................................... 5
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General Description
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1 General Description
The CDCLVP2106 is a high-performance, low additive phase noise clock buffer. It has two universal input
buffers that support either single-ended or differential clock input. Each input feeds a bank of six LVPECL
outputs. The device also features on-chip bias generators that can provide the LVPECL common-mode
voltage to the device inputs.
This evaluation module (EVM) is designed to demonstrate the electrical performance of the CDCLVP2106.
This fully assembled and factory-tested evaluation board allows complete validation of the CDCLVP2106
device functionalities. Throughout this document, the acronym EVM and the phrases evaluation module
and evaluation board are synonymous with the CDCLVP2106EVM. See Figure 1 for an illustration of the
CDCLVP2106EVM.
For optimum performance, the board is equipped with 50-ΩSMA connectors and well-controlled, 50-Ω
impedance microstrip transmission lines.
2 Signal Path and Control Circuitry
The CDCLVP2106 supports single-ended inputs up to 200 MHz and differential inputs up to 2 GHz. The
device provides up to 12 LVPECL outputs operating at the input frequency. For more information about
the CDCLVP2106, see the CDCLVP2106 product data sheet available for download from the TI web site
(www.ti.com).
3 Getting Started
The CDCLVP2106EVM has self-explanatory labeling and uses similar naming conventions as the
CDCLVP2106 product data sheet. In this user's guide, all words in boldface and italic print reflect the
actual labeling on the EVM. The CDCLVP2106EVM can be used with either single-ended or differential
inputs.
3.1 Power-Supply Connections
Connect the power-supply source to the banana plug labeled VDD (P4), and connect the ground of the
power-supply source to GND (P5). There are decoupling capacitors and a ferrite bead to isolate the EVM
power from the CDCLVP2106 device power pins.
The CDCLVP2106EVM can use a supply voltage of 2.375 V to 3.6 V.
4 Input Clock Selection
The CDCLVP2106EVM offers users the option of receiving either a differential or single-ended clock as
the clock input. The default option is for the differential signal at both device inputs. The inputs can be
applied through the SMAs (J103, J104 or J105, J106). These inputs are ac-coupled to the device inputs.
The common-mode voltage for these inputs after the ac-coupling capacitors is provided by 50 Ω(R152,
R153 and R154, R155) to the device on-chip bias generator (VAC_REF) pins.
4.1 Configuring Single-ended Input
For a single-ended clock applied to IN0, remove capacitors C68 and C69 and replace them with 0-Ω
resistors of the same footprint. The single-ended signal should be applied to INP0 (J103) and the dc bias
voltage should be applied to INN0 (J104).
For a single-ended clock applied to IN1, remove capacitors C72 and C73 and replace them with 0-Ω
resistors of the same footprint. The single-ended signal should be applied to INP1 (J105) and the dc bias
voltage should be applied to INN1 (J106).
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Output Clock
5 Output Clock
The CDCLVP2106 generates up to 12 LVPECL outputs. Four outputs are available on the
CDCLVP2106EVM (outputs 0, 5, 6, and 11) through the following SMAs:
• J13, J23 for OUT0
• J17, J27 for OUT5
• J33, J32 for OUT6
• J39, J38 for OUT11
The LVPECL outputs are terminated with 150 Ωto ground and ac-coupled to the respective SMAs.
6 Schematics and Layout
Figure 2 through Figure 4 show the printed circuit board (PCB) schematics.
NOTE: Board layouts are not to scale. These figures are intended to show how the board is laid
out; they are not intended to be used for manufacturing CDCLVP2106EVM PCBs.
Figure 2. CDCLVP2106EVM—Schematic
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Schematics and Layout
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Figure 3. CDCLVP2106EVM—Schematic
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Schematics and Layout
Figure 4. CDCLVP2106EVM—Schematic
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Evaluation Board/Kit Important Notice
Texas Instruments (TI) provides the enclosed product(s) under the following conditions:
This evaluation board/kit is intended for use for ENGINEERING DEVELOPMENT, DEMONSTRATION, OR EVALUATION PURPOSES
ONLY and is not considered by TI to be a finished end-product fit for general consumer use. Persons handling the product(s) must have
electronics training and observe good engineering practice standards. As such, the goods being provided are not intended to be complete
in terms of required design-, marketing-, and/or manufacturing-related protective considerations, including product safety and environmental
measures typically found in end products that incorporate such semiconductor components or circuit boards. This evaluation board/kit does
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Should this evaluation board/kit not meet the specifications indicated in the User’s Guide, the board/kit may be returned within 30 days from
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This evaluation board/kit is intended for use for ENGINEERING DEVELOPMENT, DEMONSTRATION, OR EVALUATION PURPOSES
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EVM Warnings and Restrictions
It is important to operate this EVM within the input voltage range of –0.5 V to 4.0 V and the output voltage range of 0 V to 3.6 V.
Exceeding the specified input range may cause unexpected operation and/or irreversible damage to the EVM. If there are questions
concerning the input range, please contact a TI field representative prior to connecting the input power.
Applying loads outside of the specified output range may result in unintended operation and/or possible permanent damage to the EVM.
Please consult the EVM User's Guide prior to connecting any load to the EVM output. If there is uncertainty as to the load specification,
please contact a TI field representative.
During normal operation, some circuit components may have case temperatures greater than +120° C. The EVM is designed to operate
properly with certain components above +85° C as long as the input and output ranges are maintained. These components include but are
not limited to linear regulators, switching transistors, pass transistors, and current sense resistors. These types of devices can be identified
using the EVM schematic located in the EVM User's Guide. When placing measurement probes near these devices during operation,
please be aware that these devices may be very warm to the touch.
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