Datenblatt für CY62177EV30 MoBL von Infineon Technologies

'L ACYPRESS EMBEDDEDIN TOMORROW — Logic Block Diagram The CY62177EV30 is a high performance CMOS static RAM organized as 2M words by 16 bits and 4M words by 8 bits. This devrce features advanced circuit design to provide ultra low active current. It is ideal for providing More Battery Life‘M (MoBL ) in portable applications such as cellular telephones. The device also has an automatic power down feature that Significantly reduces power consumption by 99 percent when addresses are not toggling. The_device can also be put into stfldby rrLde when deselected (CE‘ H GH or CE2 LOW or both BH dBLE areHlGH). The inputand utputpinsu/o0 through Q1 high impedanc wig! deselected ), outputs are IGH . both 0‘” EVE . 5E To write to the device. takflhip Enables (E1 LO PM) and Write E le (WE) input LOW. If Byte (BLE) is LOW. the ta from l/O pins (I10D thro w tten into the loca ecfld on the address pin A20). Ii Byte High s LOW, then data (l/Oa through ”0‘5 location sp address pins (ALt from th Cflp Enables (CE an_d E) Low wfl Enable (B lfled_by_th
CY62177EV30 MoBL®
32-Mbit (2M × 16/4M × 8) Static RAM
Cypress Semiconductor Corporation • 198 Champion Court • San Jose,CA 95134-1709 • 408-943-2600
Document Number: 001-09880 Rev. *O Revised February 16, 2018
32-Mbit (2M × 16/4M × 8) Static RAM
Features
■Thin small outline package (TSOP) I configurable as 2M × 16
or as 4M × 8 static RAM (SRAM)
■Very high speed
❐55 ns
■Wide voltage range
❐2.2 V to 3.7 V
■Ultra low standby power
❐Typical standby current: 3 A
❐Maximum standby current: 25 A
■Ultra low active power
❐ Typical active current: 4.5 mA at f = 1 MHz
■Easy memory expansion with CE1, CE2, and OE Features
■Automatic power down when deselected
■Complementary Metal Oxide Semiconductor (CMOS) for
optimum speed and power
■Available in Pb-free 48-pin TSOP I package and 48-ball FBGA
package
Functional Description
The CY62177EV30 is a high performance CMOS static RAM
organized as 2M words by 16 bits and 4M words by 8 bits. This
device features advanced circuit design to provide ultra low
active current. It is ideal for providing More Battery Life
(MoBL®) in portable applications such as cellular telephones.
The device also has an automatic power down feature that
significantly reduces power consumption by 99 percent when
addresses are not toggling. The device can also be put into
standby mode when deselected (CE1 HIGH or CE2 LOW or both
BHE and BLE are HIGH). The input and output pins (I/O0 through
I/O15) are placed in a high impedance state when: deselected
(CE1HIGH or CE2 LOW), outputs are disabled (OE HIGH), both
Byte High Enable and Byte Low Enable are disabled (BHE, BLE
HIGH), or during a write operation (CE1 LOW, CE2 HIGH and WE
LOW).
To write to the device, take Chip Enables (CE1 LOW and CE2
HIGH) and Write Enable (WE) input LOW. If Byte Low Enable
(BLE) is LOW, then data from I/O pins (I/O0 through I/O7), is
written into the location specified on the address pins (A0 through
A20). If Byte High Enable (BHE) is LOW, then data from I/O pins
(I/O8 through I/O15) is written to the location specified on the
address pins (A0 through A20). To read from the device, take
Chip Enables (CE1 LOW and CE2 HIGH) and Output Enable
(OE) LOW while forcing the Write Enable (WE) HIGH. If Byte
Low Enable (BLE) is LOW, then data from the memory location
specified by the address pins appear on I/O0 to I/O7. If Byte High
Enable (BHE) is LOW, then data from memory appears on I/O8
to I/O15. See the Truth Table on page 11 for a complete
description of read and write modes.
Pin #13 of the 48 TSOP I package is an DNU pin that must be
left floating at all times to ensure proper application.
For a complete list of related resources, click here.
I/O
0
–I/O
7
ROW DECODER
A
8
A
7
A
6
A
5
A
2
SENSE AMPS
DATA IN
DRIVERS
OE
A
4
A
3
I/O
8
–I/O
15
WE
BLE
BHE
A
0
A
1
A
9
A
10
Power-
Down
Circuit
BHE
BLE
CE
2
CE
1
CE
2
CE
1
BYTE
COLUMN DECODER
A
11
A
12
A
13
A
14
A
15
A
16
A
17
A
18
A
19
A
20
2M × 16
RAM Array
Logic Block Diagram
CY62177EV30 MoBL®
Document Number: 001-09880 Rev. *O Page 2 of 19
Contents
Pin Configurations ........................................................... 3
Product Portfolio .............................................................. 3
Maximum Ratings ............................................................. 4
Operating Range ............................................................... 4
Electrical Characteristics ................................................. 4
Capacitance ...................................................................... 5
Thermal Resistance .......................................................... 5
AC Test Loads and Waveforms ....................................... 5
Data Retention Characteristics ....................................... 6
Data Retention Waveform ................................................ 6
Switching Characteristics ................................................ 7
Switching Waveforms ...................................................... 8
Truth Table ...................................................................... 11
Ordering Information ...................................................... 12
Ordering Code Definitions ......................................... 12
Package Diagram ............................................................ 13
Acronyms ........................................................................ 15
Document Conventions ................................................. 15
Units of Measure ....................................................... 15
Document History Page ................................................. 16
Sales, Solutions, and Legal Information ...................... 19
Worldwide Sales and Design Support ....................... 19
Products .................................................................... 19
PSoC® Solutions ...................................................... 19
Cypress Developer Community ................................. 19
Technical Support ..................................................... 19
MMMMM 000000 000000 000000 000000 000000 000000 000000 000000
CY62177EV30 MoBL®
Document Number: 001-09880 Rev. *O Page 3 of 19
Pin Configurations
Figure 1. 48-pin TSOP I pinout (Front View) [1, 2]
Figure 2. 48-ball FBGA pinout (Top View)
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
48
47
46
45
44
43
42
41
40
39
38
37
36
35
34
33
32
31
30
29
28
27
26
25
A15
A14
A13
A12
A11
A10
A9
A8
A19
A20
WE
CE2
DNU
BHE
BLE
A18
A17
A7
A6
A5
A4
A3
A2
A1
A16
BYTE
Vss
I/O15/A21
I/O7
I/O14
I/O6
I/O13
I/O5
I/O12
I/O4
Vcc
I/O11
I/O3
I/O10
I/O2
I/O9
I/O1
I/O8
I/O0
OE
Vss
CE1
A0
WE
A11
A10
A6
A0
A3CE1
I/O
10
I/O
8
I/O
9
A4
A5
I/O
11
I/O
13
I/O
12
I/O
14
I/O
15
V
SS
A9
A8
OE
Vss
A7
I/O
0
BHE
CE2
A17
A2
A1
BLE
V
CC
I/O
2
I/O
1
I/O
3
I/O
4
I/O
5I/O
6
I/O
7
A15
A
14
A13
A
12
A19
A18 A20
3
26
5
4
1
D
E
B
A
C
F
G
H
A16
NC
Vcc
Product Portfolio
Product VCC Range (V) Speed
(ns)
Power Dissipation
Operating ICC (mA) Standby ISB2 (A)
f = 1 MHz f = fMax
Min Typ [3] Max Typ [3] Max Typ [3] Max Typ [3] Max
CY62177EV30LL 2.2 3.0 3.7 55 4.5 5.5 35 45 3 25
Notes
1. DNU Pin# 13 needs to be left floating to ensure proper application.
2. The BYTE pin in the 48-pin TSOP I package has to be tied to VCC to use the device as a 2M × 16 SRAM.
The 48-pin TSOP I package can also be used as a 4M × 8 SRAM by tying the BYTE signal to VSS. In the 4M × 8 configuration, Pin 45 is A21, while BHE, BLE, and
I/O8 to I/O14 pins are not used.
3. Typical values are included for reference only and are not guaranteed or tested. Typical values are measured at VCC = VCC(typ), TA = 25 °C.
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CY62177EV30 MoBL®
Document Number: 001-09880 Rev. *O Page 4 of 19
Maximum Ratings
Exceeding maximum ratings may impair the useful life of the
device. These user guidelines are not tested.
Storage temperature ................................ –65 °C to +150 °C
Ambient temperature
with power applied ................................... –55 °C to +125 °C
Supply voltage
to ground potential [4, 5] ...............–0.3 V to VCC(max) + 0.3 V
DC voltage applied to outputs
in High Z state [4, 5] ......................–0.3 V to VCC(max) + 0.3 V
DC input voltage [4, 5] ................... –0.3 V to VCC(max) + 0.3 V
Output current into outputs (LOW) ............................. 20 mA
Static discharge voltage
(per MIL-STD-883, method 3015) ......................... > 2001 V
Latch up current ..................................................... > 200 mA
Operating Range
Device Range Ambient
Temperature VCC [6]
CY62177EV30LL Industrial –40 °C to +85 °C 2.2 V to 3.7 V
Electrical Characteristics
Over the Operating Range
Parameter Description Test Conditions 55 ns Unit
Min Typ [7] Max
VOH Output HIGH voltage IOH = –0.1 mA VCC = 2.20 V 2.0 – – V
IOH = –1.0 mA VCC = 2.70 V 2.4 – – V
VOL Output LOW voltage IOL = 0.1 mA VCC = 2.20 V – – 0.4 V
IOL = 2.1 mA VCC = 2.70 V – – 0.4 V
VIH Input HIGH voltage VCC = 2.2 V to 2.7 V 1.8 – VCC + 0.3 V
VCC= 2.7 V to 3.7 V 2.2 – VCC + 0.3 V
VIL Input LOW voltage VCC = 2.2 V to 2.7 V –0.3 – 0.6 V
VCC= 2.7 V to 3.7 V –0.3 – 0.7 [8] V
IIX Input leakage current GND < VI < VCC –1 – +1 A
IOZ Output leakage current GND < VO < VCC, Output Disabled –1 – +1 A
ICC VCC operating supply current f = fMax = 1/tRC VCC = VCC(max)
IOUT = 0 mA
CMOS levels
–3545mA
f = 1 MHz – 4.5 5.5 mA
ISB2 [9, 10] Automatic CE power down
current – CMOS inputs
CE1 > VCC – 0.2 V or CE2 < 0.2 V or
(BHE and BLE) > VCC – 0.2 V,
VIN > V CC – 0 .2 V o r V IN < 0 .2 V, f = 0,
VCC = 3.7 V
–325A
Notes
4. VIL(min) = –2.0 V for pulse durations less than 20 ns.
5. VIH(max) = VCC + 0.75 V for pulse durations less than 20 ns.
6. Full Device AC operation assumes a 100 s ramp time from 0 to VCC (min) and 200 s wait time after VCC stabilization.
7. Typical values are included for reference only and are not guaranteed or tested. Typical values are measured at VCC = VCC(typ), TA = 25 °C.
8. Under DC conditions the device meets a VIL of 0.8 V. However, in dynamic conditions Input LOW Voltage applied to the device must not be higher than 0.7 V.
9. The BYTE pin in the 48-pin TSOP I package has to be tied to VCC to use the device as a 2M × 16 SRAM.
The 48-pin TSOP I package can also be used as a 4M × 8 SRAM by tying the BYTE signal to VSS. In the 4M × 8 configuration, Pin 45 is A21, while BHE, BLE, and
I/O8 to I/O14 pins are not used.
10. Chip enables (CE1 and CE2), BYTE, and Byte Enables (BHE and BLE) need to be tied to CMOS levels to meet the ISB2/ICCDR spec. Other inputs can be left floating.
[m [m ALL INPUT PULSES
CY62177EV30 MoBL®
Document Number: 001-09880 Rev. *O Page 5 of 19
Capacitance
Parameter [11] Description Test Conditions Max Unit
CIN Input capacitance TA = 25 °C, f = 1 MHz, VCC = VCC(typ) 15 pF
COUT Output capacitance 15 pF
Thermal Resistance
Parameter [11] Description Test Conditions FBGA TSOP I Unit
JA Thermal resistance
(junction to ambient)
Still air, soldered on a 3 × 4.5 inch,
four-layer printed circuit board
38.10 55.91 C/W
JC Thermal resistance
(junction to case)
7.54 9.39 C/W
AC Test Loads and Waveforms
Figure 3. AC Test Loads and Waveforms
VCC VCC
OUTPUT
R2
30 pF
INCLUDING
JIG AND
SCOPE
GND
90%
10%
90%
10%
Rise Time = 1 V/ns Fall Time = 1 V/ns
OUTPUT V
Equivalent to: THEVENIN EQUIVALENT
ALL INPUT PULSES
RTH
R1
Parameter 2.5 V 3.3 V Unit
R1 16667 1103
R2 15385 1554
RTH 8000 645
VTH 1.20 1.75 V
Note
11. Tested initially and after any design or process changes that may affect these parameters.
\ x /\ I‘ wm w w \A O DATA RETENTION MODE—p # > \NH E m ‘ v w m‘ m m
CY62177EV30 MoBL®
Document Number: 001-09880 Rev. *O Page 6 of 19
Data Retention Characteristics
Over the Operating Range
Parameter Description Conditions Min Typ [12] Max Unit
VDR VCC for data retention 1.5 – – V
ICCDR [13] Data retention current VCC = 1.5 V,
CE1 > VCC – 0.2 V or CE2 < 0.2 V, or
(BHE and BLE) > VCC – 0.2 V,
VIN > VCC – 0.2 V or VIN < 0.2 V
––17A
tCDR[14] Chip deselect to data retention
time
0––ns
tR[15] Operation recovery time 55 – – ns
Data Retention Waveform
Figure 4. Data Retention Waveform [16]
t
CDR
V
DR
>1.5 V
DATA RETENTION MODE
t
R
CE
1
or
V
CC
BHE
.
BLE
or
V
CC(min)
V
CC(min)
CE
2
Notes
12. Typical values are included for reference only and are not guaranteed or tested. Typical values are measured at VCC = VCC(typ), TA = 25 °C.
13. Chip enables (CE1 and CE2), BYTE, Address Pin A20 and Byte Enables (BHE and BLE) need to be tied to CMOS levels to meet the ISB2/ICCDR spec. Other inputs
can be left floating.
14. Tested initially and after any design or process changes that may affect these parameters.
15. Full device operation requires linear VCC ramp from VDR to VCC(min) > 100 s or stable at VCC(min) > 100 s.
16. BHE.BLE is the AND of both BHE and BLE. Chip is deselected by either disabling the chip enable signals or by disabling both BHE and BLE.
CYPRESS ' mennm mnwmw — [21 22] «T E BHE BLE
CY62177EV30 MoBL®
Document Number: 001-09880 Rev. *O Page 7 of 19
Switching Characteristics
Over the Operating Range
Parameter [17, 18] Description 55 ns Unit
Min Max
Read Cycle
tRC Read cycle time 55 –ns
tAA Address to data valid –55 ns
tOHA Data hold from address change 6 – ns
tACE CE1 LOW and CE2 HIGH to data valid –55 ns
tDOE OE LOW to data valid –25 ns
tLZOE OE LOW to LOW Z [19] 5 – ns
tHZOE OE HIGH to High Z [19, 20] –18 ns
tLZCE CE1 LOW and CE2 HIGH to Low Z [19] 10 –ns
tHZCE CE1 HIGH and CE2 LOW to High Z [19, 20] –18 ns
tPU CE1 LOW and CE2 HIGH to power up 0 – ns
tPD CE1 HIGH and CE2 LOW to power down –55 ns
tDBE BLE/BHE LOW to data valid –55 ns
tLZBE BLE/BHE LOW to Low Z [19] 10 –ns
tHZBE BLE/BHE HIGH to HIGH Z [19, 20] –18 ns
Write Cycle [21, 22]
tWC Write cycle time 55 –ns
tSCE CE1 LOW and CE2 HIGH to write end 40 –ns
tAW Address setup to write end 40 –ns
tHA Address hold from write end 0 – ns
tSA Address setup to write start 0 – ns
tPWE WE pulse width 40 –ns
tBW BLE/BHE LOW to write end 40 –ns
tSD Data setup to write end 25 –ns
tHD Data hold from Write End 0 – ns
tHZWE WE LOW to High Z [19, 20] –20 ns
tLZWE WE HIGH to Low Z [19] 10 –ns
Notes
17. In an earlier revision of this device, under a specific application condition, READ and WRITE operations were limited to switching of the byte enable and/or chip enable
signals as described in the Application Note AN66311. However, the issue has been fixed and in production now, and hence, this Application Note is no longer
applicable. It is available for download on our website as it contains information on the date code of the parts, beyond which the fix has been in production.
18. Test conditions for all parameters other than tristate parameters assume signal transition time of 1 V/ns, timing reference levels of VCC(typ)/2, input pulse levels of 0
to VCC(typ), and output loading of the specified IOL/IOH as shown in Figure 3 on page 5.
19. At any given temperature and voltage condition, tHZCE is less than tLZCE, tHZBE is less than tLZBE, tHZOE is less than tLZOE, and tHZWE is less than tLZWE for any given
device.
20. tHZOE, tHZCE, tHZBE, and tHZWE transitions are measured when the outputs enter a high impedence state.
21. The internal Write time of the memory is defined by the overlap of WE, CE1 = VIL, BHE and/or BLE = VIL, and CE2 = VIH. All signals must be ACTIVE to initiate a write
and any of these signals can terminate a write by going INACTIVE. The data input setup and hold timing should be referenced to the edge of the signal that terminates
the write.
22. The minimum write pulse width for Write Cycle No. 3 (WE Controlled, OE LOW) should be sum of tSD and tHZWE.
The fl E BHE BLE WE
CY62177EV30 MoBL®
Document Number: 001-09880 Rev. *O Page 8 of 19
Switching Waveforms
Figure 5. Read Cycle No. 1 (Address Transition Controlled) [23, 24]
Figure 6. Read Cycle No. 2 (OE Controlled) [24, 25]
ADDRESS
DATA OUT PREVIOUS DATA VALID DATA VALID
tRC
tAA
tOHA
50%
50%
DATA VALID
tRC
tACE
tDOE
tLZOE
tLZCE
tPU
HIGH IMPEDANCE
tHZOE
tPD
tHZBE
tLZBE
tHZCE
tDBE
HIGH
ICC
ISB
IMPEDANCE
OE
CE1
ADDRESS
VCC
SUPPLY
CURRENT
BHE/BLE
DATA OUT
CE2
Notes
23. The device is continuously selected. OE, CE1 = VIL, BHE and/or BLE = VIL, and CE2 = VIH.
24. WE is HIGH for read cycle.
25. Address valid prior to or coincident with CE1, BHE, BLE transition LOW and CE2 transition HIGH.
{EMPRESS ' mennznmmnmw / Mule: 33 IE
CY62177EV30 MoBL®
Document Number: 001-09880 Rev. *O Page 9 of 19
Figure 7. Write Cycle No. 1 (WE Controlled) [26, 27, 28, 29]
Figure 8. Write Cycle No. 2 (CE1 or CE2 Controlled) [26, 27, 28, 29]
Switching Waveforms (continued)
t
HD
t
SD
t
PWE
t
SA
t
HA
t
AW
t
SCE
t
WC
t
HZOE
VALID DATA
t
BW
NOTE 29
ADDRESS
WE
DATA I/O
OE
BHE
/
BLE
CE
1
CE
2
tHD
tSD
tPWE
tHA
tAW
tSCE
tWC
tHZOE
VALID DATA
NOTE 29
tBW
tSA
ADDRESS
WE
DATA I/O
OE
BHE/BLE
CE1
CE2
Notes
26. The internal Write time of the memory is defined by the overlap of WE, CE1 = VIL, BHE and/or BLE = VIL, and CE2 = VIH. All signals must be ACTIVE to initiate a write
and any of these signals can terminate a write by going INACTIVE. The data input setup and hold timing should be referenced to the edge of the signal that terminates
the write.
27. Data I/O is high impedance if OE = VIH.
28. If CE1 goes HIGH and CE2 goes LOW simultaneously with WE = VIH, the output remains in a high impedance state.
29. During this period the I/Os are in output state and input signals should not be applied.
CY62177EV30 MoBL®
Document Number: 001-09880 Rev. *O Page 10 of 19
Figure 9. Write Cycle No. 3 (WE Controlled, OE LOW) [30]
Figure 10. Write Cycle No. 4 (BHE/BLE Controlled, OE LOW) [30, 32]
Switching Waveforms (continued)
VALID DATA
tHD
tSD
tLZWE
tPWE
tSA
tHA
tAW
tSCE
tWC
tHZWE
tBW
NOTE 31
ADDRESS
CE1
CE2
BHE/BLE
WE
DATA I/O
tHD
tSD
tSA
tHA
tAW
tWC
VALID DATA
tBW
tSCE
tPWE
NOTE 31
ADDRESS
CE1
CE2
BHE/BLE
WE
DATA I/O
Notes
30. If CE1 goes HIGH and CE2 goes LOW simultaneously with WE = VIH, the output remains in a high impedance state.
31. During this period the I/Os are in output state and input signals should not be applied.
32. The minimum write pulse width for Write Cycle No. 3 (WE controlled, OE LOW) should be sum of tSD and tHZWE.
CY62177EV30 MoBL®
Document Number: 001-09880 Rev. *O Page 11 of 19
Truth Table
CE1CE2WE OE BHE BLE Input/Output Mode Power
HX
[33] XXX
[33] X[33] High Z Deselect/Power Down Standby (ISB)
X[33] LXXX
[33] X[33] High Z Deselect/Power Down Standby (ISB)
X[33] X[33] X X H H High Z Deselect/Power Down Standby (ISB)
L H H L L L Data Out (I/O0–I/O15) Read Active (ICC)
L H H L H L High Z (I/O8–I/O15);
Data Out (I/O0–I/O7)
Read Active (ICC)
LHHLLHData Out (I/O
8–I/O15);
High Z (I/O0–I/O7)
Read Active (ICC)
LHLXLLData In (I/O
0–I/O15) Write Active (ICC)
L H L X H L High Z (I/O8–I/O15);
Data In (I/O0–I/O7)
Write Active (ICC)
LHLXLHData In (I/O
8–I/O15);
High Z (I/O0–I/O7)
Write Active (ICC)
L H H H L H High Z Output Disabled Active (ICC)
L H H H H L High Z Output Disabled Active (ICC)
L H H H L L High Z Output Disabled Active (ICC)
Note
33. The ‘X’ (Don’t care) state for the chip enables and byte enables in the truth table refer to the logic state (either HIGH or LOW). Intermediate voltage levels on these
pins is not permitted.
EL
CY62177EV30 MoBL®
Document Number: 001-09880 Rev. *O Page 12 of 19
Ordering Code Definitions
Ordering Information
Speed
(ns) Ordering Code
Package
Diagram Package Type Operating
Range
55 CY62177EV30LL-55ZXI 51-85183 48-pin TSOP I (12 × 18.4 × 1 mm) Pb-free Industrial
55 CY62177EV30LL-55BAXI 51-85191 48 ball FBGA (8 × 9.5 × 1.2 mm) Pb-free Industrial
Contact your local Cypress sales representative for availability of these parts.
Z = 48-pin TSOP I, BA = 48 ball FBGA
Temperature Grade:
I = Industrial
X = Pb-free
Package Type:
Speed Grade: 55 ns
Low Power
Voltage Range: V30 = 3 V (typical)
Process Technology: E = 90 nm
Bus Width = × 16
Density = 32-Mbit
621 = MoBL SRAM family
Company ID: CY = Cypress
621CY 7 V30 -55 Z,BA IXLLE7
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CY62177EV30 MoBL®
Document Number: 001-09880 Rev. *O Page 13 of 19
Package Diagram
Figure 11. 48-ball FBGA (8 × 9.5 × 1.2 mm) BA48J Package Outline, 51-85191
51-85191 *C
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CY62177EV30 MoBL®
Document Number: 001-09880 Rev. *O Page 14 of 19
Figure 12. 48-pin TSOP I (12 × 18.4 × 1 mm) Z48A Package Outline, 51-85183
Package Diagram (continued)
4
5
SEE DETAIL A
SEE DETAIL B
STANDARD PIN OUT (TOP VIEW)
REVERSE PIN OUT (TOP VIEW)
3
2X (N/2 TIPS)
B
B
N/2
0.20
D
D1
A
1
2
5
E
A
N/2 +1
2X
2X
B
N
0.10
0.10
SEATING PLANE
C
A1
e9
2X (N/2 TIPS)
0.10 C
A2
DETAIL A
0.08MM M C A-B
SECTION B-B
7c
b1
SEATING PLANE
PARALLEL TO
b6
0°
DETAIL B
BASE METAL
e/2
X = A OR B
X
GAUGE PLAN
E
0.25 BASIC
WITH PLATING
7
L
C
R
(c)
8
c1
1N
N/2 N/2 +1
3. PIN 1 IDENTIFIER FOR REVERSE PIN OUT (DIE DOWN): INK OR LASER MARK.
4. TO BE DETERMINED AT THE SEATING PLANE -C- . THE SEATING PLANE IS
LEADS ARE ALLOWED TO REST FREELY ON A FLAT HORIZONTAL SURFACE.
5. DIMENSIONS D1 AND E DO NOT INCLUDE MOLD PROTRUSION. ALLOWABLE
6. DIMENSION b DOES NOT INCLUDE DAMBAR PROTRUSION. ALLOWABLE DAMBAR
MATERIAL CONDITION. DAMBAR CANNOT BE LOCATED ON LOWER RADIUS OR
7. THESE DIMENSIONS APPLY TO THE FLAT SECTION OF THE LEAD BETWEEN
8. LEAD COPLANARITY SHALL BE WITHIN 0.10mm AS MEASURED FROM THE
9. DIMENSION "e" IS MEASURED AT THE CENTERLINE OF THE LEADS.
NOTES:
1. DIMENSIONS ARE IN MILLIMETERS (mm).
2. PIN 1 IDENTIFIER FOR STANDARD PIN OUT (DIE UP).
1.051.000.95
A2
N
R
0
L
e
c
D1
E
D
b
c1
b1
0.50 BASIC
0.60
0°
0.08
0.50
48
0.20
8
0.70
0.22
0.20
20.00 BASIC
18.40 BASIC
12.00 BASIC
0.10
0.17
0.10
0.17
0.21
0.27
0.16
0.23
A1
A
0.05 0.15
1.20
SYMBOL
MIN. MAX.
DIMENSIONS
NOM.
DEFINED AS THE PLANE OF CONTACT THAT IS MADE WHEN THE PACKAGE
MOLD PROTRUSION ON E IS 0.15mm PER SIDE AND ON D1 IS 0.25mm PER SIDE.
PROTRUSION SHALL BE 0.08mm TOTAL IN EXCESS OF b DIMENSION AT MAX.
THE FOOT. MINIMUM SPACE BETWEEN PROTRUSION AND AN ADJACENT LEAD
TO BE 0.07mm .
0.10mm AND 0.25mm FROM THE LEAD TIP.
SEATING PLANE.
10. JEDEC SPECIFICATION NO. REF: MO-142(D)DD.
51-85183 *F
CY62177EV30 MoBL®
Document Number: 001-09880 Rev. *O Page 15 of 19
Acronyms Document Conventions
Units of Measure
Acronym Description
BHE Byte High Enable
BLE Byte Low Enable
CE Chip Enable
CMOS Complementary Metal Oxide Semiconductor
I/O Input/Output
OE Output Enable
SRAM Static Random Access Memory
TSOP Thin Small Outline Package
WE Write Enable
Symbol Unit of Measure
°C degree Celsius
MHz megahertz
µA microampere
mA milliampere
ms millisecond
ns nanosecond
ohm
% percent
pF picofarad
ps picosecond
Vvolt
Wwatt
CY62177EV30 MoBL®
Document Number: 001-09880 Rev. *O Page 16 of 19
Document History Page
Document Title: CY62177EV30 MoBL®, 32-Mbit (2M × 16/4M × 8) Static RAM
Document Number: 001-09880
Revision ECN Orig. of
Change
Submission
Date Description of Change
** 498562 NXR 08/31/2006 New data sheet.
*A 2544845 VKN /
PYRS
07/29/2008 Added 48-pin TSOP I package related information in all instances across the
document.
Removed 45 ns speed bin related information in all instances across the
document.
Added 70 ns speed bin related information in all instances across the
document.
Updated Electrical Characteristics:
Added Note 10 and referred the same note in ISB2 parameter.
Updated Ordering Information:
Updated part numbers.
Updated Package Diagram:
Added spec 51-85183 *A.
*B 2589750 VKN /
PYRS
10/15/2008 Updated Pin Configurations:
Updated Figure 1 (Changed pin functions of pin 10 from NC to A20 and pin 13
from A20 to DNU).
*C 2668432 VKN /
PYRS
03/03/2009 Removed 70 ns speed bin related information in all instances across the
document.
Added 55 ns speed bin related information in all instances across the
document.
Replaced 3.6 V with 3.7 V in VCC range in all instances across the document.
Updated Electrical Characteristics:
Changed maximum value of ICC parameter from 30 mA to 45 mA
corresponding to Test Condition “f = f(max)”.
Changed maximum value of ICC parameter from 2.8 mA to 4.5 mA
corresponding to Test Condition “f = 1 MHz”.
Removed ISB1 parameter and its details.
Changed maximum value of ISB2 parameter from 17 A to 25 A.
Referred Note 9 in ISB2 parameter.
Updated Note 10.
*D 2779867 VKN 10/06/2009 Changed status from Preliminary to Final.
Updated Electrical Characteristics:
Added details of VIL parameter corresponding to Test Condition “For TSOP I
Package”.
Added Note 8 and referred the same note in maximum value of VIL parameter
corresponding to Test Condition “For TSOP I Package”.
Changed typical value of ICC parameter from 28 mA to 35 mA corresponding
to Test Condition “f = f(max)”.
Changed typical value of ICC parameter from 2.2 mA to 4.5 mA corresponding
to Test Condition “f = 1 MHz”.
Changed maximum value of ICC parameter from 4.5 mA to 5.5 mA
corresponding to Test Condition “f = 1 MHz”.
Updated Capacitance:
Changed maximum value of COUT parameter from 10 pF to 15 pF.
Updated Thermal Resistance:
Replaced TBD with values in FBGA column.
Updated Switching Characteristics:
Changed minimum value of tOHA parameter from 10 ns to 6 ns.
CY62177EV30 MoBL®
Document Number: 001-09880 Rev. *O Page 17 of 19
*E 2899662 AJU 03/26/2010 Updated Ordering Information:
Updated part numbers.
Updated Package Diagram:
spec 51-85191 – Changed revision from ** to *A.
spec 51-85183 – Changed revision from *A to *B.
*F 2927528 VKN 05/04/2010 Updated Electrical Characteristics:
Updated Note 10.
Updated Truth Table:
Added Note 33 and referred the same note in respective places.
Added Acronyms.
Updated to new template.
*G 3177000 AJU 02/18/2011 Removed 48-ball FBGA package related information in all instances in the
document.
Updated Features (Removed 48-ball FBGA package related information).
Updated Pin Configurations:
Removed 48-ball FBGA package related information.
Updated Note 1 (Replaced NC with DNU).
Updated Electrical Characteristics (Updated details in “Test Conditions”
column of ISB2 parameter).
Updated Thermal Resistance (Removed 48-ball FBGA package related
information).
Updated Data Retention Characteristics (Updated details in “Conditions”
column of ICCDR parameter).
Updated Ordering Information:
No change in part numbers.
Added Ordering Code Definitions.
Updated Package Diagram:
Removed spec 51-85191 *A.
Updated Acronyms.
Added Units of Measure.
Updated to new template.
*H 3295175 RAME 06/29/2011 Updated Functional Description:
Removed Note “For best practice recommendations, refer to the Cypress
application note System Design Guidelines.” and its reference.
Updated Package Diagram:
spec 51-85183 – Changed revision from *B to *C.
*I 3461953 TAVA 12/22/2011 Included 48-ball FBGA package related information in all instances in the
document.
Updated Ordering Information:
Updated part numbers.
Updated Package Diagram:
Added spec 51-85191 *B.
*J 4100342 VINI 08/21/2013 Updated Switching Characteristics:
Added Note 17 and referred the same note in “Parameter” column.
Updated Package Diagram:
spec 51-85191 – Changed revision from *B to *C.
Updated to new template.
Completing Sunset Review.
*K 4111710 NILE 09/12/2013 Updated Electrical Characteristics:
Updated Note 10.
Updated Data Retention Characteristics:
Updated Note 13.
Document History Page (continued)
Document Title: CY62177EV30 MoBL®, 32-Mbit (2M × 16/4M × 8) Static RAM
Document Number: 001-09880
Revision ECN Orig. of
Change
Submission
Date Description of Change
i CYPRESS mmm m mmnw Upda‘ed Eledrical Chara Updamd No:e10(lssue Updamd Swnchlng Char Aug} N 22 andirefe in WE C led, OE L Updam mg Wa Aug} nfle
CY62177EV30 MoBL®
Document Number: 001-09880 Rev. *O Page 18 of 19
*L 4355423 MEMJ 04/29/2014 Updated Electrical Characteristics:
Updated Note 10 (Issue is fixed so pin A20 can be left floating in standby).
Updated Switching Characteristics:
Added Note 22 and referred the same note in Write Cycle (for tPWE parameter
in WE Controlled, OE LOW condition).
Updated Switching Waveforms:
Added Note 32 and referred the same note in Figure 10 (for tPWE parameter
in WE Controlled, OE LOW condition).
*M 4567826 VINI 11/12/2014 Updated Features:
Included 48-ball FBGA package related information.
Updated Functional Description:
Added “For a complete list of related resources, click here.” at the end.
Updated Maximum Ratings:
Referred Notes 4, 5 in “Supply voltage to ground potential”.
Completing Sunset Review.
*N 5017414 VINI 11/17/2015 Updated Thermal Resistance:
Replaced “2-layer” with “four-layer” in “Test Conditions” column.
Changed value of JA parameter corresponding to TSOP I package from
44.66 C/W to 55.91 C/W.
Changed value of JC parameter corresponding to TSOP I package from
12.12 C/W to 9.39 C/W.
Updated Package Diagram:
spec 51-85183 – Changed revision from *C to *D.
Updated to new template.
Completing Sunset Review.
*O 6073315 VINI 02/16/2018 Updated Package Diagram:
spec 51-85183 – Changed revision from *D to *F.
Updated to new template.
Document History Page (continued)
Document Title: CY62177EV30 MoBL®, 32-Mbit (2M × 16/4M × 8) Static RAM
Document Number: 001-09880
Revision ECN Orig. of
Change
Submission
Date Description of Change
Document Number: 001-09880 Rev. *O Revised February 16, 2018 Page 19 of 19
MoBL is a registered trademark, and More Battery Life is a trademark, of Cypress Semiconductor Corporation.
CY62177EV30 MoBL®
© Cypress Semiconductor Corporation, 2006-2018. This document is the property of Cypress Semiconductor Corporation and its subsidiaries, including Spansion LLC ("Cypress"). This document,
including any software or firmware included or referenced in this document ("Software"), is owned by Cypress under the intellectual property laws and treaties of the United States and other countries
worldwide. Cypress reserves all rights under such laws and treaties and does not, except as specifically stated in this paragraph, grant any license under its patents, copyrights, trademarks, or other
intellectual property rights. If the Software is not accompanied by a license agreement and you do not otherwise have a written agreement with Cypress governing the use of the Software, then Cypress
hereby grants you a personal, non-exclusive, nontransferable license (without the right to sublicense) (1) under its copyright rights in the Software (a) for Software provided in source code form, to
modify and reproduce the Software solely for use with Cypress hardware products, only internally within your organization, and (b) to distribute the Software in binary code form externally to end users
(either directly or indirectly through resellers and distributors), solely for use on Cypress hardware product units, and (2) under those claims of Cypress's patents that are infringed by the Software (as
provided by Cypress, unmodified) to make, use, distribute, and import the Software solely for use with Cypress hardware products. Any other use, reproduction, modification, translation, or compilation
of the Software is prohibited.
TO THE EXTENT PERMITTED BY APPLICABLE LAW, CYPRESS MAKES NO WARRANTY OF ANY KIND, EXPRESS OR IMPLIED, WITH REGARD TO THIS DOCUMENT OR ANY SOFTWARE
OR ACCOMPANYING HARDWARE, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE. To the extent
permitted by applicable law, Cypress reserves the right to make changes to this document without further notice. Cypress does not assume any liability arising out of the application or use of any
product or circuit described in this document. Any information provided in this document, including any sample design information or programming code, is provided only for reference purposes. It is
the responsibility of the user of this document to properly design, program, and test the functionality and safety of any application made of this information and any resulting product. Cypress products
are not designed, intended, or authorized for use as critical components in systems designed or intended for the operation of weapons, weapons systems, nuclear installations, life-support devices or
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Cypress, the Cypress logo, Spansion, the Spansion logo, and combinations thereof, WICED, PSoC, CapSense, EZ-USB, F-RAM, and Traveo are trademarks or registered trademarks of Cypress in
the United States and other countries. For a more complete list of Cypress trademarks, visit cypress.com. Other names and brands may be claimed as property of their respective owners.
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