Datenblatt für DRV8800,01 von Texas Instruments

U Ordering & Technical Design a 3 Support 5 o . quahly documentation development (raming I TEXAS INSTRUMENTS 8Vto36V Jr
DRV880x DMOS Full-Bridge Motor Drivers
1 Features
• H-Bridge Motor Driver
• Low RDS(on) MOSFETs (0.4-Ω Typical)
• Low-Power Sleep Mode
• 100% PWM Duty Cycle Supported
• 8-V to 36-V Operating Supply Voltage Range
• Thermally Enhanced Surface-Mount Package
• Protection Features:
– VBB Undervoltage Lockout (UVLO)
– Charge Pump Undervoltage (CPUV)
– Overcurrent Protection (OCP)
– Short-to-Supply Protection
– Short-to-Ground Protection
– Overtemperature Warning (OTW)
– Overtemperature Shutdown (OTS)
– Fault Condition Indication Pin (nFAULT)
2 Applications
• Printers
• Industrial Automation
• Robotics
3 Description
The DRV880x provides a versatile motor driver
solution with a variety of capabilities. The device
contains a full H-bridge which can be used to drive
a brushed DC motor, one winding of a stepper motor,
or other devices such as solenoids. A simple PHASE-
ENABLE interface allows easy interfacing to controller
circuits.
The output stages use N-channel power MOSFETs
configured as an H-bridge. The DRV880x is capable
of peak output currents up to ±2.8 A and operating
voltages up to 36 V. An internal charge pump
generates the needed gate drive voltages.
A low-power sleep mode is provided which shuts
down internal circuitry to achieve a very low quiescent
current draw. This sleep mode can be set using a
dedicated nSLEEP pin.
Internal protection functions are provided for
undervoltage, charge pump fault, overcurrent, short-
to-supply, short-to-ground, and overtemperature. Fault
conditions are indicated through the nFAULT pin.
The DRV880x is packaged in a 16-pin WQFN
package with PowerPAD™ (Eco-friendly: RoHS & no
Sb/Br).
Device Information(1)
PART NUMBER PACKAGE BODY SIZE (NOM)
DRV8800 HTSSOP (16) 5.00 mm × 4.40 mm
WQFN (16) 4.00 mm × 4.00 mm
DRV8801 HTSSOP (16) 5.00 mm × 4.40 mm
WQFN (16) 4.00 mm × 4.00 mm
(1) For all available packages, see the orderable addendum at
the end of the data sheet.
PHASE
nSLEEP
8 V to 36 V
Controller
DRV8800/
DRV8801
Protection
Brushed DC
Motor Driver
ENABLE
nFAULT
M
Simplified Schematic
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An IMPORTANT NOTICE at the end of this data sheet addresses availability, warranty, changes, use in safety-critical applications,
intellectual property matters and other important disclaimers. PRODUCTION DATA.
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Table of Contents
1 Features............................................................................1
2 Applications..................................................................... 1
3 Description.......................................................................1
4 Revision History.............................................................. 2
5 Pin Configuration and Functions...................................3
6 Specifications.................................................................. 5
6.1 Absolute Maximum Ratings........................................ 5
6.2 ESD Ratings............................................................... 5
6.3 Recommended Operating Conditions.........................5
6.4 Thermal Information....................................................5
6.5 Electrical Characteristics.............................................6
6.6 Typical Characteristics................................................ 7
7 Parameter Measurement Information............................ 8
8 Detailed Description......................................................10
8.1 Overview................................................................... 10
8.2 Functional Block Diagrams....................................... 10
8.3 Feature Description...................................................11
8.4 Device Functional Modes..........................................13
9 Application and Implementation.................................. 16
9.1 Application Information............................................. 16
9.2 Typical Application.................................................... 16
9.3 Parallel Configuration ...............................................19
10 Power Supply Recommendations..............................23
10.1 Bulk Capacitance.................................................... 23
11 Layout........................................................................... 24
11.1 Layout Guidelines................................................... 24
11.2 Layout Example...................................................... 24
12 Device and Documentation Support..........................26
12.1 Related Links.......................................................... 26
12.2 Trademarks............................................................. 26
12.3 Electrostatic Discharge Caution..............................26
12.4 Glossary..................................................................26
13 Mechanical, Packaging, and Orderable
Information.................................................................... 26
4 Revision History
Changes from Revision J (July 2014) to Revision K (March 2021) Page
• Added missing GND pin reference to Pin Functions Table ................................................................................3
• Added SENSE pin to Pin Functions Table ......................................................................................................... 3
• Improved description for pins nFAULT, nSLEEP, VBB and VCP in Pin Functions Table ................................... 3
• Added entries for VCP and CP2 pins in Absolute Maximum Ratings table........................................................ 5
• Added VDD pin voltage limits and device’s PWM frequency limits to Recommended Operation Conditions
table.................................................................................................................................................................... 5
• Changed SLEEP to nSLEEP in PWM Control Timing Figure............................................................................. 8
• Added equation for VPROPI to help when connecting pin’s output to ADC in Feature Description ................12
• Provide additional information on SENSE pin behavior....................................................................................13
• Added device specific details to Control Logic Table .......................................................................................13
• Added die temperature estimation equation utilizing junction to ambient thermal impedance in Application and
Implementation section.....................................................................................................................................18
• Added information on using motor driver’s pulse width modulating modes in Application and Implementation
section.............................................................................................................................................................. 18
Changes from Revision I (January 2014) to Revision J (July 2014) Page
• Added ESD Ratings table, Feature Description section, Device Functional Modes, Application and
Implementation section, Power Supply Recommendations section, Layout section, Device and
Documentation Support section, and Mechanical, Packaging, and Orderable Information section .................. 5
Changes from Revision H (November 2013) to Revision I (January 2014) Page
• Added IOCP to ELECTRICAL CHARACTERISTICS........................................................................................... 6
• Changed Parameter Measurement Information ................................................................................................ 8
Changes from Revision G (October 2013) to Revision H (November 2013) Page
• Changed maximum junction temperature from 190°C to 150°C.........................................................................5
• Changed VTRP description/test conditions........................................................................................................ 6
• Changed Protection Circuitry section................................................................................................................. 6
• Changed Note in SENSE section..................................................................................................................... 13
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5 Pin Configuration and Functions
1
2
3
4
5
6
7
8
12
11
10
9
16
15
14
13
PHASE
PowerPAD
GND
nSLEEP
ENABLE
GND
CP2
CP1
OUT-
MODE
nFAULT
VREG
VCP
NC
OUT+
SENSE
VBB
Figure 5-1. DRV8800 RTY Package 16-Pin WQFN
Top View
MODE 1
nFAULT
VPROPI
VCP
1
2
3
4
5
6
7
8
12
11
10
9
16
15
14
13
PHASE
PowerPAD
GND
nSLEEP
ENABLE
GND
CP2
CP1
OUT-
MODE 2
OUT+
SENSE
VBB
Figure 5-2. DRV8801 RTY Package 16-Pin WQFN
Top View
1
2
3
4
16
15
14
13
nFAULT
PowerPAD
MODE
PHASE
GND
NC
VREG
VCP
GND
5
6
7
8
nSLEEP
ENABLE
OUT+
SENSE
12
11
10
9
CP2
CP1
OUT-
VBB
Figure 5-3. DRV8800 PWP Package 16-Pin HTSSOP
Top View
1
2
3
4
16
15
14
13
nFAULT
PowerPAD
MODE 1
PHASE
GND
MODE 2
VPROPI
VCP
GND
5
6
7
8
nSLEEP
ENABLE
OUT+
SENSE
12
11
10
9
CP2
CP1
OUT-
VBB
Figure 5-4. DRV8801 PWP Package 16-Pin HTSSOP
Top View
Table 5-1. Pin Functions
PIN
I/O DESCRIPTION
NAME DRV8800 DRV8801
WQFN HTSSOP WQFN HTSSOP
CP1 10 11 10 11 P
Charge pump switching node. Connect a 0.1-μF
X7R ceramic capacitor rated for VBB between
CP1 and CP2.
CP2 11 12 11 12 P
Charge pump switching node. Connect a 0.1-μF
X7R ceramic capacitor rated for VBB between
CP1 and CP2.
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Table 5-1. Pin Functions (continued)
PIN
I/O DESCRIPTION
NAME DRV8800 DRV8801
WQFN HTSSOP WQFN HTSSOP
ENABLE 4 6 4 6 I Enable logic input. Set high to enable the H-
bridge.
GND 2,12 4, 13 2, 12 4, 13 P Device ground
MODE 16 2 — — I Mode logic input
MODE 1 — — 16 2 I Mode logic input
MODE 2 — — 5 16 I Mode 2 logic input
NC 5 16 — — NC No connect
nFAULT 15 1 15 1 OD
Fault indication. Pulled logic low with fault
condition; open-drain output requires an external
pullup resistor.
nSLEEP 3 5 3 5 I
Sleep mode input. Logic high to enable device;
logic low to enter low-power sleep mode; internal
pulldown resistor.
OUT+ 6 7 6 7 O DMOS H-bridge output. Connect to motor
terminal.
OUT- 9 10 9 10 O DMOS H-bridge output. Connect to motor
terminal.
PHASE 1 3 1 3 I
WQFN Package: Phase logic input for direction
control.
HTSSOP Package: Phase logic input. Controls
the direction of the H-bridge.
SENSE 7 8 7 8 O (DRV8800)
IO (DRV8801) Sense Power Return
VBB 8 9 8 9 P
Driver supply voltage. Bypass to GND with 0.1-μF
ceramic capacitors plus a bulk capacitor rated for
VBB.
VCP 13 14 13 14 P Charge pump reservoir capacitor pin. Connect a
X7R, 0.1-μF, 16-V ceramic capacitor to VBB.
VREG 14 15 — — P Regulated voltage.
VPROPI — — 14 15 O Voltage output proportional to winding current.
PowerPAD — — — — — Exposed pad for thermal dissipation. Connect to
ground.
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6 Specifications
6.1 Absolute Maximum Ratings
over operating free-air temperature range (unless otherwise noted)(1)
MIN MAX UNIT
VBB Load supply voltage(2) –0.3 40 V
VCP and CP2 Charge Pump Voltage –0.3 VBB+17V V
Output current –2.8 2.8 A
VSense Sense voltage –500 500 mV
VBB to OUTx 36 V
OUTx to SENSE 36 V
VDD PHASE, ENABLE, MODE, MODE1, MODE2, nSLEEP and nFAULT(2) –0.3 7 V
Continuous total power dissipation See Section 6.4
TAOperating free-air temperature –40 85 °C
TJMaximum junction temperature 150 °C
Tstg Storage temperature –40 125 °C
(1) Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. These are stress ratings
only, and functional operation of the device at these or any other conditions beyond those indicated under Recommended Operating
Conditions is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
(2) All voltage values are with respect to network ground terminal.
6.2 ESD Ratings
VALUE UNIT
V(ESD) Electrostatic discharge
Human body model (HBM), per ANSI/ESDA/JEDEC JS-001, all pins(1) ±2000
V
Charged device model (CDM), per JEDEC specification JESD22-C101, all
pins(2)
±500
(1) JEDEC document JEP155 states that 500-V HBM allows safe manufacturing with a standard ESD control process.
(2) JEDEC document JEP157 states that 250-V CDM allows safe manufacturing with a standard ESD control process.
6.3 Recommended Operating Conditions
MIN NOM MAX UNIT
VIN Input voltage, VBB 8 32 38 V
VDD Logic Supply Voltage 0 5.5 V
f(PWM) Applied PMW signal (PHASE and ENABLE) 0 100 kHz
TAOperating free-air temperature –40 85 °C
6.4 Thermal Information
THERMAL METRIC(1)
DRV880x
UNITRTY (WQFN) PWP (HTSSOP)
16 PINS 16 PINS
RθJA Junction-to-ambient thermal resistance 38.1 43.9
°C/W
RθJC(top) Junction-to-case (top) thermal resistance 36.7 30.8
RθJB Junction-to-board thermal resistance 16.1 25.3
ψJT Junction-to-top characterization parameter 0.3 1.1
ψJB Junction-to-board characterization parameter 16.2 25
RθJC(bot) Junction-to-case (bottom) thermal resistance 4.1 5.6
(1) For more information about traditional and new thermal metrics, see the IC Package Thermal Metrics application report, SPRA953.
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6.5 Electrical Characteristics
over recommended operating conditions (unless otherwise noted)
PARAMETER TEST CONDITIONS MIN TYP MAX UNIT
IBB Motor supply current
fPWM < 50 kHz 6 mA
Charge pump on, Outputs disabled 3.2
Sleep mode 10 μA
VIH PHASE, ENABLE,
MODE input voltage
2V
VIL 0.8
VIH nSLEEP input voltage 2.7 V
VIL 0.8
IIH PHASE, MODE input current VIN = 2 V <1.0 20 μA
IIL VIN = 0.8 V –20 ≤–2.0 20
IIH ENABLE input current VIN = 2 V 40 100 μA
IIL VIN = 0.8 V 16 40
IIH nSLEEP input current VIN = 2.7 V 27 50 μA
IIL VIN = 0.8 V <1 10
VOL nFAULT output voltage Isink = 1 mA 0.4 V
VBBNFR VBB nFAULT release 8 V < VBB < 40 V 12 13.8 V
VIHys Input hysteresis, except nSLEEP 100 500 800 mV
rDS(on) Output ON-resistance
Source driver, IOUT = –2.8 A, TJ = 25°C 0.48
Ω
Source driver, IOUT = –2.8 A, TJ = 125°C 0.74 0.85
Sink driver, IOUT = 2.8 A, TJ = 25°C 0.35
Sink driver, IOUT = 2.8 A, TJ = 125°C 0.52 0.7
VTRP RSENSE voltage trip SENSE connected to ground through a 0.2-Ω
resistor 500 mV
VfBody diode forward voltage Source diode, If = –2.8 A 1.4 V
Sink diode, If = 2.8 A 1.4
tpd Propagation delay time PWM, Change to source or sink ON 600 ns
PWM, Change to source or sink OFF 100
tCOD Crossover delay 500 ns
DAGain Differential AMP gain Sense = 0.1 V to 0.4 V 5 V/V
PROTECTION CIRCUITRY
VUV UVLO threshold VBB increasing 6.5 7.5 V
IOCP Overcurrent threshold 3 A
tDEG Overcurrent deglitch time 3 µs
tOCP Overcurrent retry time 1.2 ms
TJW Thermal warning temperature Temperature increasing(1) 160 °C
TJTSD Thermal shutdown temperature Temperature increasing(2) 175 °C
(1) After the device reaches the thermal warning temperature of 160°C, the device will remain in thermal warning until the device cools to
145°C. This is known as the device's thermal warning hysteresis.
(2) After the device reaches the thermal shutdown temperature of 175°C, the device will remain in thermal shutdown until the device cools
to 160°C. This is known as the device's thermal shutdown hysteresis.
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6.6 Typical Characteristics
0
1
2
3
4
5
6
7
8
9
10
8 V 32 V 38 V
Quiescent Current (µA)
Supply Voltage
±40ƒC
25°C
125°C
C001
Figure 6-1. IVBBQ vs VBB
C002
Figure 6-2. RDS(ON) vs VBB (Normalized to VBB = 8
V)
0
10
20
30
40
50
60
5 V 15 V 25 V 35 V 45 V
Charge Pump Voltage (V)
Supply Voltage
C003
Figure 6-3. VCP vs VBB
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7 Parameter Measurement Information
nSLEEP
ENABLE
PHASE
MODE
VBB
VBB
VOUT-
VOUT+
IOUTX
0
0
0
6
1 5
32 4
7
8
9
1 2 3 4 5 6 7 8 9A
OUT+ OUT-
VIN
VIN
OUT-OUT+
ACharge Pump and VREG power on delay (~200 us)
Figure 7-1. PWM Control Timing
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tOCP
tDEG
IPEAK
IOCP
IOUTx
High-Z
VOUTA
VOUTB
Enable,
Source
or Sink
Charge Pump
Counter
NFAULT
Motor Lead
Short Condition
Normal DC
Motor Capacitance
Figure 7-2. Overcurrent Control Timing
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STRUMENTS
8 Detailed Description
8.1 Overview
The DRV880x devices are integrated motor driver solutions for brushed DC motors. The devices integrate a
DMOS H-bridge, protection circuitry, and simple digital interface. The devices can be powered with a supply
voltage between 8 and 36 V and are capable of providing an output current up to 2.8 A.
A PHASE-ENABLE interface allows for easy interfacing to the controller circuit. The PHASE input controls the
direction of the H-bridge and the ENABLE input specifies whether the H-bridge is enabled or not.
Two MODE pins allow for specifying which current decay method the device utilizes. MODE1 specifies between
fast decay or slow decay and MODE2 specifies between high side or low side slow decay.
The DRV8801 provides the option to monitor the motor winding current through a proportional voltage output.
8.2 Functional Block Diagrams
Outputs
Power
0.1 µF
Charge
Pump
OUT+
VBB
Pre-
driver
VCP
OUT-
VBB
Pre-
driver
VCP
BDC
VCP
CP1
CP2
VBB
0.1 µF
0.1 µF
Bulk
SENSE
VREG
GND
GND
PPAD
VCP
VBB
Regulators
RSENSE
MODE
NC
PHASE
ENABLE
nSLEEP
nFAULT
Core
Logic
Protection
Temperature
Sensor
Overcurrent
Monitoring
Voltage
Monitoring
Inputs
VMCU
0.22 µF
Optional
Figure 8-1. DRV8800 Functional Block Diagram
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Outputs
Power
0.1 µF
Charge
Pump
OUT+
VBB
Pre-
driver
VCP
OUT-
VBB
Pre-
driver
VCP
BDC
VCP
CP1
CP2
VBB
0.1 µF
0.1 µF
Bulk
SENSE
VPROPI
GND
GND
PPAD
VCP
VBB
Regulators
RSENSE
MODE 1
MODE 2
PHASE
ENABLE
nSLEEP
nFAULT
Core
Logic
Protection
Temperature
Sensor
Overcurrent
Monitoring
Voltage
Monitoring
Inputs
VMCU
5
x
Figure 8-2. DRV8801 Functional Block Diagram
8.3 Feature Description
8.3.1 Logic Inputs
TI recommends using a high-value pullup resistor when logic inputs are pulled up to VDD. This resistor limits
the current to the input in case an overvoltage event occurs. Logic inputs are nSLEEP, MODE, PHASE, and
ENABLE. Voltages higher than 7 V on any logic input can cause damage to the input structure.
8.3.2 VREG (DRV8800 Only)
This output represents a measurement of the internal regulator voltage. This pin should be left disconnected. A
voltage of approximately 7.5 V can be measured at this pin.
8.3.3 VPROPI (DRV8801 Only)
The analog output VPROPI offers SENSE current information as an analog voltage proportional to the current
flowing through the DC motor winding. This voltage can be used by an analog to digital converter and
microcontroller to accurately determine how much current is flowing through the controlled DC motor. See
Section 8.3.11 for guidance on selecting a SENSE resistor value.
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8.3.3.1 Connecting VPROPI Output to ADC
The analog output VPROPI varies proportionally with the SENSE voltage according to Equation 1. It’s important
to note even if VSENSE is negative VPROPI will remain at 0 V.
SENSE
VPROPI 5 V u
(1)
An RC network in series with the VPROPI output is recommended, if this voltage is to be sampled by an analog
to digital converter.
Figure 8-3. RC Network in Series With the VPROPI Output
It is imperative to realize that VPROPI will decrease to 0 V while the H-Bridge enters slow decay recirculation.
8.3.4 Charge Pump
The charge pump is used to generate a supply above VBB to drive the source-side DMOS gates. A 0.1-μF
ceramic monolithic capacitor should be connected between CP1 and CP2 for pumping purposes. A 0.1-μF
ceramic monolithic capacitor, CStorage, should be connected between VCP and VBB to act as a reservoir to run
the high-side DMOS devices. The VCP voltage level is internally monitored and, in the case of a fault condition,
the outputs of the device are disabled.
8.3.5 Shutdown
As a measure to protect the device, faults caused by very high junction temperatures or low voltage on VCP
disable the outputs of the device until the fault condition is removed. At power on, the UVLO circuit disables the
drivers.
8.3.6 Low-Power Mode
Control input nSLEEP is used to minimize power consumption when the DRV880x is not in use. A logic low on
the nSLEEP input disables much of the internal circuitry, including the internal voltage rails and charge pump. A
logic high on this input pin results in normal operation. When switching from low to high, the user should allow a
1-ms delay before applying PWM signals. This time is needed for the charge pump to stabilize.
8.3.7 Braking
The braking function is implemented by driving the device in slow-decay mode (MODE 1 pin is high) and
deasserting the enable to low. Because it is possible to drive current in both directions through the DMOS
switches, this configuration effectively shorts out the motor-generated BEMF as long as the ENABLE chop mode
is asserted. The maximum current can be approximated by VBEMF/RL. Care should be taken to ensure that the
maximum ratings of the device are not exceeded in worse-case braking situations – high-speed and high-inertia
loads.
8.3.8 Diagnostic Output
The nFAULT pin signals a problem with the chip via an open-drain output. A motor fault, undervoltage condition,
or TJ > 160°C drives the pin low. This output is not valid when nSLEEP puts the device into minimum power
dissipation mode (that is, nSLEEP is low). nFAULT stays asserted (nFAULT = L) until VBB reaches VBBNFR to
give the charge pump headroom to reach its undervoltage threshold. nFAULT is a status-only signal and does
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not affect any device functionality. The H-bridge portion still operates normally down to VBB = 8 V with nFAULT
asserted.
8.3.9 Thermal Shutdown (TSD)
Two die-temperature monitors are integrated on the chip. As die temperature increases toward the maximum, a
thermal warning signal is triggered at 160°C. This fault drives the nFAULT low, but does not disable the operation
of the chip. If the die temperature increases further, to approximately 175°C, the full-bridge outputs are disabled
until the internal temperature falls below a hysteresis of 15°C.
8.3.10 Overcurrent Protection
The current flowing through the high-side and low-side drivers is monitored to ensure that the motor lead is not
shorted to supply or ground. If a short is detected, the full-bridge outputs are turned off, flag nFAULT is driven
low, and a 1.2-ms fault timer is started. After this 1.2-ms period, tOCP , the device is then allowed to follow the
input commands and another turnon is attempted (nFAULT becomes high again during this attempt). If there is
still a fault condition, the cycle repeats. If after tOCP expires it is determined the short condition is not present,
normal operation resumes and nFAULT is deasserted.
8.3.11 SENSE
A low-value SENSE resistor is used to set an overcurrent threshold lower than the default maximum value
of 2.8 A and to provide a voltage for VPROPI (DRV8801 Only). This SENSE resistor must be connected
between the SENSE pin and ground. To minimize ground-trace IR drops in sensing the output current level, the
current-sensing resistor should have an independent ground return to the star ground point. This trace should be
as short as possible. For low-value sense resistors, the IR drops in the PCB can be significant, and should be
taken into account.
A direct connection to ground yields a SENSE voltage equal to zero. In that case, maximum current is 2.8 A and
VPROPI outputs 0 V. A resistor connected as explained before, will yield a VPROPI output as detailed in Section
8.3.3. Size the sense resistor such that voltage drop across the sense resistor is less than 500mV under normal
loading conditions. Any voltage equal or larger to 500 mV will signal the device to hi-Z the H-bridge output as
overcurrent trip threshold has been reached. In this case, device will enter recirculation as stipulated by the
MODE input pin. The device automatically retries with a period of t(OCP).
Equation 2 shows the value of the resistor to a particular current setting.
sense
trip
500 mV
RI
(2)
8.4 Device Functional Modes
8.4.1 Device Operation
The DRV880x supports a low power sleep mode through the nSLEEP pin. In this mode the device shuts down
a majority of the internal circuitry including the internal voltage rails and charge pump. Bringing the nSLEEP pin
HIGH will put the device back into its active state.
During normal operation the DRV880x is designed to operate a single brushed DC motor. The outputs are
connected to each side on the motor coil, allowing for full bidirectional control.
Table 8-1. Control Logic Table(1)
PINS OPERATION
PHASE ENABLE MODE 1 MODE 2 nSLEEP OUT+ OUT-
1 1 X X 1 H L Forward
0 1 X X 1 L H Reverse
X 0 1 0 1 L L Brake (slow decay)
X 0 1 1 1 H H Brake (slow decay)
1 0 0 X 1 L H Fast-decay synchronous
rectification(2)
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Table 8-1. Control Logic Table(1) (continued)
PINS OPERATION
PHASE ENABLE MODE 1 MODE 2 nSLEEP OUT+ OUT-
0 0 0 X 1 H L Fast-decay synchronous
rectification(2)
X X X X 0 Z Z Sleep mode
(1) X = Don’t care, Z = high impedance
(2) To prevent reversal of current during fast-decay synchronous rectification, outputs go to the high-impedance state as the current
approaches 0 A.
• MODE 1 (MODE on the DRV8800)
Input MODE 1 is used to toggle between fast-decay mode and slow-decay mode. A logic high puts the device
in slow-decay mode.
• MODE 2 (DRV8801 only)
MODE 2 is used to select which set of drivers (high side versus low side) is used during the slow-decay
recirculation. MODE 2 is meaningful only when MODE 1 is asserted high. A logic high on MODE 2 has
current recirculation through the high-side drivers. A logic low has current recirculation through the low-side
drivers.
8.4.1.1 Slow-Decay SR (Brake Mode)
In slow-decay mode, both low-side sinking drivers turn on, allowing the current to circulate through the H-
bridge’s low side (two sink drivers) and the load. Power dissipation I2R losses in one source and one sink DMOS
driver, as shown in Equation 7
8.4.1.2 Fast Decay With Synchronous Rectification
This decay mode is equivalent to a phase change where the opposite drivers are switched on. When in fast
decay, the motor current is not allowed to go negative (direction change). Instead, as the current approaches
zero, the drivers turn off. The power calculation is the same as the drive current calculation (see Equation 7).
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8.4.1.2.1
1
2
3
1
2
3
Drive Current
Slow decay with synchronous rectification (brake)
Fast decay with synchronous rectification (reverse)
VBB
Figure 8-4. Current Path DRV8800
1
2
3
Drive Current
Slow decay with synchronous rectification (brake) Low Side
Fast decay with synchronous rectification (reverse)
VBB
4
1
2
3
4 Slow decay with synchronous rectification (brake) High Side
Figure 8-5. Current Path DRV8801
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9 Application and Implementation
Note
Information in the following applications sections is not part of the TI component specification, and
TI does not warrant its accuracy or completeness. TI’s customers are responsible for determining
suitability of components for their purposes. Customers should validate and test their design
implementation to confirm system functionality.
9.1 Application Information
DRV880x device is used in medium voltage brushed DC motor control applications.
9.2 Typical Application
nFAULT
MODE
PHASE
GND
nSLEEP
ENABLE
OUT+
SENSE
1
2
4
3
5
6
7
8VBB 9
OUT- 10
CP1 11
CP2 12
GND 13
VCP 14
VREG 15
NC 16
PowerPAD 0
BDC
0.1 µF 100 µF
VBB
0.1 µF
0.1 µF
0.2 Ÿ
0.22 uF
Optional
DRV8800
Controller
GPIO
10NŸ
VMCU
VMCU
Figure 9-1. DRV8800 Typical Application Schematic
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nFAULT
MODE 1
PHASE
GND
nSLEEP
ENABLE
OUT+
SENSE
1
2
4
3
5
6
7
8VBB 9
OUT- 10
CP1 11
CP2 12
GND 13
VCP 14
VPROPI 15
MODE 2 16
PowerPAD 0
BDC
0.1µF 100µF
VBB
0.1 µF
0.1 µF
0.2 Ÿ
DRV8801
Controller
GPIO
10 NŸ
VMCU
VMCU 100 NŸ
1000 pF
RC Filter
ADC
Figure 9-2. DRV8801 Typical Application Schematic
9.2.1 Design Requirements
For this design example, use the parameters listed in Table 9-1 as the input parameters.
Table 9-1. Design Parameters
DESIGN
PARAMETER REFERENCE EXAMPLE
VALUE
Motor Voltage VBB 24 V
Motor RMS Current IRMS 0.8 A
Motor Startup Current ISTART 2 A
Motor Current Trip
Point ITRIP 2.5 A
9.2.2 Detailed Design Procedure
9.2.2.1 Motor Voltage
The motor voltage to use will depend on the ratings of the motor selected and the desired RPM. A higher voltage
spins a brushed DC motor faster with the same PWM duty cycle applied to the power FETs. A higher voltage
also increases the rate of current change through the inductive motor windings.
9.2.2.2 Power Dissipation
The power dissipation of the DRV880x is a function of the RMS motor current and the each output’s FET
resistance (RDS(ON)).
Power ≈ IRMS 2 x (High-Side RDS(ON) + Low-Side RDS(ON))(3)
For this example, the ambient temperature is 35°C, and the junction temperature reaches 65°C. At 65°C, the
sum of RDS(ON) is about 1Ω. With an example motor current of 0.8A, the dissipated power in the form of heat
will be 0.8 A2x 1 Ω = 0.64 W.
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The temperature that the DRV880x reaches will depend on the thermal resistance to the air and PCB. It is
important to solder the device PowerPAD to the PCB ground plane, with vias to the top and bottom board layers,
to dissipate heat into the PCB and reduce the device temperature. In the example used here, the DRV880x had
an effective thermal resistance RθJA of 47°C/W, and:
TJ = TA + (PD x RθJA) = 35°C + (0.64 W x 47°C/W) = 65°C (4)
9.2.2.3 Thermal Considerations
Although the DRV8800 and DRV8801 are rated at 2.8-A of current handling, the previous only holds true as long
as the internal temperature does not exceeds 170°C. In order to operate at this rate, the following measures
must be taken under consideration.
9.2.2.3.1 Junction-to-Ambiant Thermal Impedance (ƟJA)
At any given time during the steady state portion of the cycle, two FETs are enabled: A high side sourcing FET
and a low side sinking FET. The increase in die temperature above ambient can be estimated by Equation 5
o
2
die JA winding ON A
C
T, 5'6 7
W
u u
(5)
9.2.2.4 Motor Current Trip Point
When the voltage on pin SENSE exceeds VTRP (0.5 V), overcurrent is detected. The RSENSE resistor should be
sized to set the desired ITRIP level.
RSENSE = 0.5 V / ITRIP (6)
To set ITRIP to 2.5 A, RSENSE = 0.5 V / 2.5 A = 0.2 Ω.
To prevent false trips, ITRIP must be higher than regular operating current. Motor current during startup is typically
much higher than steady-state spinning, because the initial load torque is higher, and the absence of back-EMF
causes a higher voltage and extra current across the motor windings.
It can be beneficial to limit startup current by using series inductors on the DRV880x output, as that allows ITRIP
to be lower, and it may decrease the system’s required bulk capacitance. Startup current can also be limited by
ramping the forward drive duty cycle.
9.2.2.5 Sense Resistor Selection
For optimal performance, it is important for the sense resistor to be:
• Surface-mount
• Low inductance
• Rated for high enough power
• Placed closely to the motor driver
9.2.2.6 Drive Current
This current path is through the high-side sourcing DMOS driver, motor winding, and low-side sinking DMOS
driver. Power dissipation I2R losses in one source and one sink DMOS driver, as shown in Equation 7.
P = I (r Source + r Sink)
D
2
DS(on) DS(on)
(7)
9.2.3 Pulse-Width Modulating
9.2.3.1 Pulse-Width Modulating ENABLE
The most common H-Bridge direction/speed control scheme is to use a conventional GPIO output for the
PHASE (selects direction) and pulse-width modulate ENABLE for speed control.
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I TEXAS INSTRUMENTS a“ nu ma Nu-(M !rv hum) gm: um. a.» a» Mm. mm: M, a“ nu ma Nu-(M !rv hum) um um. >1.» M W M: M, m mama. W Izmunimz W“, m magma. W Inumnmzz W“, 04 m m. ’ w mm. mm , 2m cm 5‘.“ » ' cm 5‘.“ am mm m.- ..... p. . 2. 2. ”NJ 1 “W ;k m gm w... M. W, :w kw. m 5.» w”. w , ;k m gm w». M W, :w uw. m 5.» mm. w M m a..." w A“ vznum r‘ m a ”mg. m A“ m.“ r‘ v as v U“, Luv g as . v“, ‘ and mm. W m mm. ‘ cm 5‘... cm 5‘... um am m m ‘ \rfl- n n
9.2.3.2 Pulse-Width Modulating PHASE
Another technique is to use a speed/direction control scheme where ENABLE is connected to a GPIO output
and the PHASE is pulse-width modulated. In this case, both direction and speed are controlled with a single
signal. ENABLE is only used to disable the motor and stop all current flow.
When pulse-width modulating PHASE, a 50% duty cycle will stop the motor. Duty cycles above 50% will have
the motor moving on the clockwise direction with proportional control; 100% duty cycle represents full speed.
Duty cycles below 50% will have the motor rotating with a counter clockwise direction; 0% duty cycle represents
full speed.
9.2.4 Application Curves
Figure 9-3. Forward Drive, Fast Decay Figure 9-4. Reverse Drive, Fast Decay
Figure 9-5. Forward Drive, Slow Decay Figure 9-6. Reverse Drive, Slow Decay
9.3 Parallel Configuration
It is possible to drive higher than the 2.8 A of current by connecting more than one DRV8800 or DRV8801 in
parallel. To properly use this option the guidelines documented below must be followed.
Note
It is not recommended that one connect a DRV8800 in parallel with a DRV8801. Only place like
devices in the configuration outlined in this document
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I TEXAS INSTRUMENTS VBE VBE %% +45% %%5 %}i f %}i %% +45% %%E %}i f %}i
9.3.1 Parallel Connections
Figure 9-7 shows the signals that need to be connected together.
For DRV8801, ENABLE, PHASE, MODE 1, MODE 2, nSLEEP, OUT+, OUT-, SENSE, VBB and GND.
For DRV8800, ENABLE, PHASE, MODE, nSLEEP, OUT+, OUT-, SENSE, VBB and GND.
DRV8801
MODE 1
MODE 2
ENABLE
PHASE
nSLEEP
DRV8801
MODE 1
MODE 2
ENABLE
PHASE
nSLEEP
VBB
GND
OUT+
OUT-
SENSE
OUT+
OUT-
SENSE
DRV8800
MODE
ENABLE
PHASE
nSLEEP
DRV8800
MODE
ENABLE
PHASE
nSLEEP
VBB
GND
OUT+
OUT-
SENSE
OUT+
OUT-
SENSE
Figure 9-7. Functional Block Diagram (Connected Signals)
9.3.2 Non – Parallel Connections
Figure 9-8 shows the signals that should not be connected together and will be driven on an individual basis.
These are: VCP, CP1, CP2, and VPROPI (on the DRV8801)
CP2
CP1
VCP
DRV8800
VBB
CP2
CP1
VCP
DRV8801
VBB
CP2
CP1
VCP
DRV8800
VBB
CP2
CP1
VCP
DRV8801
VBB
VPROPI
VPROPI
Figure 9-8. Functional Block Diagram (Individual Signals)
9.3.3 Wiring nFAULT as Wired OR
Since nFAULT is an open drain output, multiple nFAULT outputs can be paralleled with a single resistor. The end
result is a wired OR configuration. When any individual nFAULT output goes to a logic low, the wired OR output
will go to the same logic low. There is no need to determine which device signaled the fault condition, as once
they are connected in parallel they function as a single device.
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Ti:
NFAULT
DRV8800/01
NFAULT
DRV8800/01
VDD
Figure 9-9. nFAULT as Wired OR
9.3.4 Electrical Considerations
9.3.4.1 Device Spacing
It is recommended that devices be connected as close as possible and with trace lengths as short as possible.
Doing this minimizes the potential of generating timing differences between devices. Although it may seem
like a harmful situation for the power stage, the DRV8800 and DRV8801 devices contain enough protection to
effectively deal with enable time skews from device to device. This consideration focuses on motion quality, as
total current needed for acceleration and proper speed control will only be available when all power stages are
brought online.
9.3.4.2 Recirculation Current Handling
During recirculation, it is not possible to synchronize all devices connected in parallel so that the current is
equally distributed. Also, during the asynchronous portion of the current decay, the body diode with the lowest
forward voltage will start conducting and sink all of the current. Said body diode is not meant to handle the new
increased current capacity and will be severely affected if allowed to sink current of said magnitude.
In order to assure proper operation when devices are connected in parallel, it is imperative that external schottky
diodes be used. These schottky diodes will conduct during the asynchronous portion of the recirculation mode
and will sink the inductive load current until the respective FET switches are brought online.
Schottky diodes should be connected as shown in Figure 9-10.
M
VBB
GND
DRV8800/01
DRV8800/01
DRV8800/01
VBB
VBB
Figure 9-10. Schottky Diodes Connection
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9.3.4.3 Sense Resistor Selection
The guideline for the SENSE resistor chosen doesn't change in parallel mode. As the goal of this configuration
is to evenly distribute the current load across multiple devices, each device should be configured with the same
ITRIP setting. Therefore, the same SENSE resistor should be used for all devices connected in parallel.
Connection of the SENSE resistors should be as shown in Figure 9-11.
DRV8800/01
DRV8800/01
SENSE
SENSE
Figure 9-11. SENSE Resistors Connection
9.3.4.4 Maximum System Current
The idea behind placing multiple DRV8800/01 devices in parallel is to increase maximum drive current. At first
glance, it may seem that the new increased ITRIP setting is given by Equation 8.
TRIP TRIP
SystemI I N u
(8)
Where:
N is the number of DRV8800/01 devices connected in parallel.
ITRIP is the individual ITRIP value per device.
However, although in theory accurate, due to tolerances in internal SENSE amplifier/comparator circuitry, the
system ITRIP should be expected to be less than the addition of all the individual ITRIP. The reason for this is
that as soon as one of the devices senses a current for which the H Bridge should be disabled, the remaining
devices will end up having to conduct the same current but with less capacity. Therefore, remaining devices are
expected to get disabled shortly after.
A good rule of thumb is to expect 90% of the theoretical maximum.
By way of example, if the system level requirements indicate that 6 A of current are required to meet the motion
control requirements, then:
6 A = (2.8 A x 0.9)N
N = (6 A) / (2.8 A x 0.9)
N = 2.38
In this example, three DRV8800/01 devices would be required to meet the safety needs of the system.
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10 Power Supply Recommendations
10.1 Bulk Capacitance
Having appropriate local bulk capacitance is an important factor in motor drive system design. It is generally
beneficial to have more bulk capacitance, while the disadvantages are increased cost and physical size.
The amount of local capacitance needed depends on a variety of factors, including:
• The highest current required by the motor system.
• The capacitance of the power supply and its ability to source current.
• The amount of parasitic inductance between the power supply and motor systems.
• The acceptable voltage ripple.
• The type of motor used (Brushed DC, Brushless DC, Stepper).
• The motor braking method.
The inductance between the power supply and motor drive system will limit the rate current can change from the
power supply. If the local bulk capacitance is too small, the system will respond to excessive current demands
or dumps from the motor with a change in voltage. When adequate bulk capacitance is used, the motor voltage
remains stable and high current can be quickly supplied.
The data sheet generally provides a recommended value, but system-level testing is required to determine the
appropriate sized bulk capacitor.
Local
Bulk Capacitor
Parasitic Wire
Inductance
+
±
Motor
Driver
Power Supply Motor Drive System
VBB
GND
+
IC Bypass
Capacitor
Figure 10-1. Example Setup of Motor Drive System With External Power Supply
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{y TEXAS INSTRUMENTS ~H— 000 000 000 OOO
11 Layout
11.1 Layout Guidelines
• The printed-circuit-board (PCB) should use a heavy ground plane. For optimal electrical and thermal
performance, the DRV880x must be soldered directly onto the board. On the underside of the DRV880x is
a thermal pad, which provides a path for enhanced thermal dissipation. The thermal pad should be soldered
directly to an exposed surface on the PCB. Thermal vias are used to transfer heat to other layers of the PCB.
• The load supply pin VBB, should be decoupled with an electrolytic capacitor (typically 100 µF) in parallel with
a ceramic capacitor (0.1 µF) placed as close as possible to the device.
• The ceramic capacitors (0.1 µF) between VCP and VBB and between CP1 and CP2 should be placed as
close as possible to the device.
• The SENSE resistor should be close as possible to the SENSE pin and ground return to minimize parasitic
inductance.
11.2 Layout Example
PHASE
GND
nSLEEP
ENABLE
VCP
VPROPI
nFAULT
MODE 1
+
0.2 Ÿ
GND
0.1 µF
BDC
GND
VBB
GND
GND
0.1 µF
0.1 µF
GND
CP2
CP1
OUT-
VBB
SENSE
OUT+
MODE 2
GND
GND
GND
Figure 11-1. RTY Layout Example
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I TEXAS INSTRUMENTS 0 000 000 000 000 000 !! ~H- Wiliiliii ~H~8 OOO
nFAULT MODE 2
MODE 1
PHASE
GND
nSLEEP
ENABLE
OUT+
SENSE
VPROPI
VCP
GND
CP2
CP1
OUT-
VBB
+
0.2 Ÿ
GND
0.1 µF
BDC
GND
VBB
GND
GND
0.1µF
0.1 µF
Figure 11-2. PWP Layout Example
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12 Device and Documentation Support
12.1 Related Links
The table below lists quick access links. Categories include technical documents, support and community
resources, tools and software, and quick access to sample or buy.
Table 12-1. Related Links
PARTS PRODUCT FOLDER SAMPLE & BUY TECHNICAL
DOCUMENTS
TOOLS &
SOFTWARE
SUPPORT &
COMMUNITY
DRV8800 Click here Click here Click here Click here Click here
DRV8801 Click here Click here Click here Click here Click here
12.2 Trademarks
PowerPAD™ is a trademark of Texas Instruments.
All trademarks are the property of their respective owners.
12.3 Electrostatic Discharge Caution
This integrated circuit can be damaged by ESD. Texas Instruments recommends that all integrated circuits be handled
with appropriate precautions. Failure to observe proper handling and installation procedures can cause damage.
ESD damage can range from subtle performance degradation to complete device failure. Precision integrated circuits may
be more susceptible to damage because very small parametric changes could cause the device not to meet its published
specifications.
12.4 Glossary
TI Glossary This glossary lists and explains terms, acronyms, and definitions.
13 Mechanical, Packaging, and Orderable Information
The following pages include mechanical, packaging, and orderable information. This information is the most
current data available for the designated devices. This data is subject to change without notice and revision of
this document. For browser-based versions of this data sheet, refer to the left-hand navigation.
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I TEXAS INSTRUMENTS Samples Samples Samples Samples Samples Samples Samples Samples
PACKAGE OPTION ADDENDUM
www.ti.com 10-Dec-2020
Addendum-Page 1
PACKAGING INFORMATION
Orderable Device Status
(1)
Package Type Package
Drawing Pins Package
Qty Eco Plan
(2)
Lead finish/
Ball material
(6)
MSL Peak Temp
(3)
Op Temp (°C) Device Marking
(4/5)
Samples
DRV8800PWP ACTIVE HTSSOP PWP 16 90 RoHS & Green NIPDAU Level-2-260C-1 YEAR -40 to 85 DRV8800
DRV8800PWPR ACTIVE HTSSOP PWP 16 2000 RoHS & Green NIPDAU Level-2-260C-1 YEAR -40 to 85 DRV8800
DRV8800RTYR ACTIVE QFN RTY 16 3000 RoHS & Green NIPDAU Level-3-260C-168 HR -40 to 85 DRV
8800
DRV8800RTYT ACTIVE QFN RTY 16 250 RoHS & Green NIPDAU Level-3-260C-168 HR -40 to 85 DRV
8800
DRV8801PWP ACTIVE HTSSOP PWP 16 90 RoHS & Green NIPDAU Level-2-260C-1 YEAR -40 to 85 DRV8801
DRV8801PWPR ACTIVE HTSSOP PWP 16 2000 RoHS & Green NIPDAU Level-2-260C-1 YEAR -40 to 85 DRV8801
DRV8801RTYR ACTIVE QFN RTY 16 3000 RoHS & Green NIPDAU Level-3-260C-168 HR -40 to 85 DRV
8801
DRV8801RTYT ACTIVE QFN RTY 16 250 RoHS & Green NIPDAU Level-3-260C-168 HR -40 to 85 DRV
8801
(1) The marketing status values are defined as follows:
ACTIVE: Product device recommended for new designs.
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design.
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.
OBSOLETE: TI has discontinued the production of the device.
(2) RoHS: TI defines "RoHS" to mean semiconductor products that are compliant with the current EU RoHS requirements for all 10 RoHS substances, including the requirement that RoHS substance
do not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, "RoHS" products are suitable for use in specified lead-free processes. TI may
reference these types of products as "Pb-Free".
RoHS Exempt: TI defines "RoHS Exempt" to mean products that contain lead but are compliant with EU RoHS pursuant to a specific EU RoHS exemption.
Green: TI defines "Green" to mean the content of Chlorine (Cl) and Bromine (Br) based flame retardants meet JS709B low halogen requirements of <=1000ppm threshold. Antimony trioxide based
flame retardants must also meet the <=1000ppm threshold requirement.
(3) MSL, Peak Temp. - The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature.
(4) There may be additional marking, which relates to the logo, the lot trace code information, or the environmental category on the device.
I TEXAS INSTRUMENTS
PACKAGE OPTION ADDENDUM
www.ti.com 10-Dec-2020
Addendum-Page 2
(5) Multiple Device Markings will be inside parentheses. Only one Device Marking contained in parentheses and separated by a "~" will appear on a device. If a line is indented then it is a continuation
of the previous line and the two combined represent the entire Device Marking for that device.
(6) Lead finish/Ball material - Orderable Devices may have multiple material finish options. Finish options are separated by a vertical ruled line. Lead finish/Ball material values may wrap to two
lines if the finish value exceeds the maximum column width.
Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information
provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and
continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals.
TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited information may not be available for release.
In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI to Customer on an annual basis.
OTHER QUALIFIED VERSIONS OF DRV8801 :
•Automotive: DRV8801-Q1
NOTE: Qualified Version Definitions:
•Automotive - Q100 devices qualified for high-reliability automotive applications targeting zero defects
I TEXAS INSTRUMENTS 5:. V.’
PACKAGE MATERIALS INFORMATION
www.ti.com 3-Jun-2022
TAPE AND REEL INFORMATION
Reel Width (W1)
REEL DIMENSIONS
A0
B0
K0
W
Dimension designed to accommodate the component length
Dimension designed to accommodate the component thickness
Overall width of the carrier tape
Pitch between successive cavity centers
Dimension designed to accommodate the component width
TAPE DIMENSIONS
K0 P1
B0 W
A0
Cavity
QUADRANT ASSIGNMENTS FOR PIN 1 ORIENTATION IN TAPE
Pocket Quadrants
Sprocket Holes
Q1 Q1Q2 Q2
Q3 Q3Q4 Q4 User Direction of Feed
P1
Reel
Diameter
*All dimensions are nominal
Device Package
Type Package
Drawing Pins SPQ Reel
Diameter
(mm)
Reel
Width
W1 (mm)
A0
(mm) B0
(mm) K0
(mm) P1
(mm) W
(mm) Pin1
Quadrant
DRV8800PWPR HTSSOP PWP 16 2000 330.0 12.4 6.9 5.6 1.6 8.0 12.0 Q1
DRV8800RTYR QFN RTY 16 3000 330.0 12.4 4.25 4.25 1.15 8.0 12.0 Q2
DRV8800RTYT QFN RTY 16 250 180.0 12.4 4.25 4.25 1.15 8.0 12.0 Q2
DRV8801PWPR HTSSOP PWP 16 2000 330.0 12.4 6.9 5.6 1.6 8.0 12.0 Q1
DRV8801RTYR QFN RTY 16 3000 330.0 12.4 4.25 4.25 1.15 8.0 12.0 Q2
DRV8801RTYT QFN RTY 16 250 180.0 12.4 4.25 4.25 1.15 8.0 12.0 Q2
Pack Materials-Page 1
PACKAGE MATERIALS INFORMATION
www.ti.com 3-Jun-2022
TAPE AND REEL BOX DIMENSIONS
Width (mm)
W
L
H
*All dimensions are nominal
Device Package Type Package Drawing Pins SPQ Length (mm) Width (mm) Height (mm)
DRV8800PWPR HTSSOP PWP 16 2000 350.0 350.0 43.0
DRV8800RTYR QFN RTY 16 3000 356.0 356.0 35.0
DRV8800RTYT QFN RTY 16 250 210.0 185.0 35.0
DRV8801PWPR HTSSOP PWP 16 2000 350.0 350.0 43.0
DRV8801RTYR QFN RTY 16 3000 356.0 356.0 35.0
DRV8801RTYT QFN RTY 16 250 210.0 185.0 35.0
Pack Materials-Page 2
I TEXAS INSTRUMENTS __________________ ‘(I(I“""""""""
PACKAGE MATERIALS INFORMATION
www.ti.com 3-Jun-2022
TUBE
L - Tube length
T - Tube
height
W - Tube
width
B - Alignment groove width
*All dimensions are nominal
Device Package Name Package Type Pins SPQ L (mm) W (mm) T (µm) B (mm)
DRV8800PWP PWP HTSSOP 16 90 530 10.2 3600 3.5
DRV8801PWP PWP HTSSOP 16 90 530 10.2 3600 3.5
Pack Materials-Page 3
GENERIC PACKAGE VIEW PWP 16 PowerPAD” TSSOP - 1.2 mm max height PLASTIC SMALL OUTLINE Images above are jusl a represenlalion of the package family, aclual package may vary Refel lo the product dala sheel for package details. 40732253.] I TEXAS INSTRI IMFNTS
PWP001BB
www.ti.com
PACKAGE OUTLINE
C
TYP
6.6
6.2
14X 0.65
16X 0.30
0.19
2X
4.55
(0.15) TYP
0 - 8
0.15
0.05
3.0
2.4
3.0
2.4
2X 0.95 MAX
NOTE 5
1.2 MAX
(1)
0.25
GAGE PLANE
0.75
0.50
A
NOTE 3
5.1
4.9
B4.5
4.3
4X 0.15 MAX
NOTE 5
4218971/A 01/2016
PowerPAD TSSOP - 1.2 mm max heightPWP0016B
PLASTIC SMALL OUTLINE
NOTES:
1. All linear dimensions are in millimeters. Any dimensions in parenthesis are for reference only. Dimensioning and tolerancing
per ASME Y14.5M.
2. This drawing is subject to change without notice.
3. This dimension does not include mold flash, protrusions, or gate burrs. Mold flash, protrusions, or gate burrs shall not
exceed 0.15 mm per side.
4. Reference JEDEC registration MO-153.
5. Features may not be present.
PowerPAD is a trademark of Texas Instruments.
TM
116
0.1 C A B
9
8
PIN 1 ID
AREA
SEATING PLANE
0.1 C
SEE DETAIL A
DETAIL A
TYPICAL
SCALE 2.400
THERMAL
PAD
PWP0016B
www.ti.com
EXAMPLE BOARD LAYOUT
(5.8)
0.05 MAX
ALL AROUND
0.05 MIN
ALL AROUND
16X (1.5)
16X (0.45)
14X (0.65)
(3.4)
NOTE 9
(5)
NOTE 9
(3)
(3)
( ) TYP
VIA
0.2
(1.1) TYP
(1.1)
TYP
4218971/A 01/2016
PowerPAD TSSOP - 1.2 mm max heightPWP0016B
PLASTIC SMALL OUTLINE
SYMM
SYMM
SEE DETAILS
LAND PATTERN EXAMPLE
SCALE:10X
1
89
16
METAL COVERED
BY SOLDER MASK
SOLDER MASK
DEFINED PAD
TM
NOTES: (continued)
6. Publication IPC-7351 may have alternate designs.
7. Solder mask tolerances between and around signal pads can vary based on board fabrication site.
8. This package is designed to be soldered to a thermal pad on the board. For more information, see Texas Instruments literature
numbers SLMA002 (www.ti.com/lit/slma002) and SLMA004 (www.ti.com/lit/slma004).
9. Size of metal pad may vary due to creepage requirement.
METAL
SOLDER MASK
OPENING
NON SOLDER MASK
DEFINED
SOLDER MASK DETAILS
PADS 1-16
SOLDER MASK
DEFINED
SOLDER MASK
METAL UNDER SOLDER MASK
OPENING
PWP0016B Emma:—
www.ti.com
EXAMPLE STENCIL DESIGN
16X (1.5)
16X (0.45)
(3)
(3)
BASED ON
0.125 THICK
STENCIL
14X (0.65)
(R ) TYP0.05
(5.8)
4218971/A 01/2016
PowerPAD TSSOP - 1.2 mm max heightPWP0016B
PLASTIC SMALL OUTLINE
2.54 X 2.540.175
2.74 X 2.740.15
3 X 3 (SHOWN)0.125
3.35 X 3.350.1
SOLDER STENCIL
OPENING
STENCIL
THICKNESS
NOTES: (continued)
10. Laser cutting apertures with trapezoidal walls and rounded corners may offer better paste release. IPC-7525 may have alternate
design recommendations.
11. Board assembly site may have different recommendations for stencil design.
TM
SYMM
SYMM
1
89
16
BASED ON
0.125 THICK
STENCIL
BY SOLDER MASK
METAL COVERED SEE TABLE FOR
DIFFERENT OPENINGS
FOR OTHER STENCIL
THICKNESSES
SOLDER PASTE EXAMPLE
EXPOSED PAD
100% PRINTED SOLDER COVERAGE BY AREA
SCALE:10X
MECHANICAL DATA “21 “416‘ JLASH" QJAD *LA JACK NO L:AJ 4226276/B 03/11 NOTES: A AH HHEC' dimensmrs c'e m m’hme‘er: Dimers’amnq c'vd tu‘erc'vc'mg per ASME w» 5 ‘994 R Tm drawmq \s sunjec' :a change wnrmr mm. C Omd Fu'pclck, Vm‘euds (an) package curflgyuimn T've :uckcge harm: pad must be su‘dered :o the hard ‘0' \hermo‘ urd mechjmcu perfarrrance See Us Pro Da:a sree: m detafls regc'd'vg U‘e exzused the’rvu‘ and dimersms E Fo‘s v/Mm c M07220 {FTEXAS INSTRUMENTS wwwxi .com
THERMAL PAD MECHANICAL DATA RTY i: QFRiM’S) P ”i370 QUAD TP/‘(LK {107 FM) TFERMAL iNFORNATiON ins packnqe i"ccrnorctes an exaesed :hermui pad mt is designed to be nttaenea drectiy to m externci heaisink Tne tnermai pcd must be soidered d'rectiy to tne pr'rited eirea’t board (Dcaiv Afier soder'ing‘ We pea een be used as a hemsmk, in additom tnioagt tte use at :hermai Vi :"e tnennai pcd ca" be atmenea aireetiy to the unpmpria’e :npaer aiene 5"owri in :he eie senamatie the device‘ or aiternetivaiy, ean De attac~ee te a spee'a naatsint stmetare designed into tee PCB ins des‘ optim’zes the neat i'ansfcr from the imeeratee eneat (c). Fo' 'ntennat'en en the Quad :iutpack AoiLnod (ow) package Inc is advantages. refer to Aeeieat'en iapert, OFN/SCV PCB Attaennent, Texas instruments ,iteratwe Ne stmi inis docurrerit is eveiiaeie a: wwwtieom ’ne cxpcsnd hc'ma acd ainensians ler tnis package are snewn in ma leiiewmg iiiastmtien 16 JUUL Wflflf BcHom View hxposec WE'mci Pad Dimersons 420627772/5 OS/H VOTE. A AH iiriear dimensions are 'n miHimete'S {if hams INSTRUMENTS www.ti.com
LAND PATTERN DATA ,_ s n \ e \ s s QTV (D’JAMQFV’NAO/ A) ASHC, QUAJ A A JACK \() AAD ExampAe Buurd LayeuA Exc'npe SAeneAA Des'AgrA GCZDWW SACACAA hACMCSS (NuAe E) *A A A \Me D A , n; A, x, A ‘ ‘ , A J , , r A ’ ‘ < o="" o="" k="" 7="" f="" f="" 3="" l="" a="" \="" _,="" a="" .n="" ,e="" a="" f="" a="" c:="" j="" .="" a="" a="" k="" j="" \="" )="" k,="" ,="" ,="" ,="" ,="" v="" m="" r="" {a="" a="" v="" a="" ,-="" \="" -="" a="" -="" \="">< -="" \="" 89%="" pramed="" suacer="" ccvercge="" \s="" \="" oewaer="" poe="" layout="" x="" exampae="" \="" (nme="" d)="" \="" scadc'="" mask="" opermg="" \="" a="" (neae="" ’)="" ,="" a="" dad="" geometry="" (ner="" c)="" y="" y="" 7=""> + NOTES A N AAneur d'TAensAuns are Ar W'A'Ame‘ers 3 TN: druwmg As sAmeeA Au Change mAheAAA not'Ace C PAADA'CafAmA APCi7ESA AS recummended fur uHerane des'grs. 3 TM puckcge As CESAgAAed Ao be soAdered 10 u AremmA puc er :he board ReAer Ao AppAcuAAun NULEA 0m FAcAst Packages, Texas nsl’AAmeMs Ateruhre Nu swm‘, and can Ane PrOCJd Dam sreeAs for spee'ne MermaA 'wfemcnon, vAu requwemems, cm recommerded boc'd aycAA: These ducnme'fls are eve'ebAe eA www AA co'rA (Mb //www.(A.com> Aasm cAAHg sperms mm ArcaczoAan waHs and mm romdmg Game's w A My bczzcr pasAc chcusc Customers sham curAacA meAr board asseway she Jor sAenmA des'AgrA recommenacmns Refer Ao AW: 7525 for sAenc des'Agr CONSAdem‘AOHS Customers s'mAAAd conmd theA’r boc'd fubrAcutAon sAAe Aer suAcer musk AeAemrees ' T ” IfigstEN'rs www. com
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