Datenblatt für MCP3001 Data Sheet von Microchip Technology

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Q ‘MICROCHIP MCP3001 iiiiiii

MCP3001

Features

• 10-bit resolution

• ±1 LSB max DNL

• ±1 LSB max INL

• On-chip sample and hold

• SPI™ serial interface (modes 0,0 and 1,1)

• Single supply operation: 2.7V - 5.5V

• 200 ksps sampling rate at 5V

• 75 ksps sampling rate at 2.7V

• Low power CMOS technology

- 5 nA typical standby current, 2 µA max

- 500 µA max active current at 5V

• Industrial temp range: -40°C to +85°C

• 8-pin PDIP, SOIC, MSOP and TSSOP packages

Applications

• Sensor Interface

• Process Control

• Data Acquisition

• Battery Operated Systems

Description

The Microchip Technology Inc. MCP3001 is a succes-

sive approximation 10-bit A/D converter (ADC) with on-

board sample and hold circuitry. The device provides a

single pseudo-differential input. Differential Nonlinear-

ity (DNL) and Integral Nonlinearity (INL) are both spec-

ified at ±1 LSB max. Communication with the device is

done using a simple serial interface compatible with the

SPI protocol. The device is capable of sample rates up

to 200 ksps at a clock rate of 2.8 MHz. The MCP3001

operates over a broad voltage range (2.7V - 5.5V).

Low current design permits operation with a typical

standby current of only 5 nA and a typical active current

of 400 µA. The device is offered in 8-pin PDIP, MSOP,

TSSOP and 150 mil SOIC packages.

Package Types

Functional Block Diagram

VREF

IN+

IN–

VSS

VDD

CLK

DOUT

CS/SHDN

PDIP, MSOP, SOIC, TSSOP

MCP3001

Illustration not to scale

Comparator

Sample

and

Hold

10-Bit SAR

DAC

Control Logic

CS/SHDN

VREF

IN+

IN-

VSS

VDD

CLK DOUT

Shift

2.7V 10-Bit A/D Converter with SPI™ Serial Interface

SPI™ is a trademark of Motorola Inc.

Max um Ra ngs"

MCP3001

1.0 ELECTRICAL

CHARACTERISTICS

1.1 Maximum Ratings*

VDD.........................................................................7.0V

All inputs and outputs w.r.t. VSS ...... -0.6V to VDD +0.6V

Storage temperature ..........................-65°C to +150°C

Ambient temp. with power applied .....-65°C to +125°C

ESD protection on all pins (HBM)........................> 4kV

*Notice: Stresses above those listed under “Maximum ratings”

may cause permanent damage to the device. This is a stress

rating only and functional operation of the device at those or

any other conditions above those indicated in the operational

listings of this specification is not implied. Exposure to maxi-

mum rating conditions for extended periods may affect device

reliability.

PIN FUNCTION TABLE

ELECTRICAL CHARACTERISTICS

Name Function

VDD +2.7V to 5.5V Power Supply

VSS Ground

IN+ Positive Analog Input

IN- Negative Analog Input

CLK Serial Clock

DOUT Serial Data Out

CS/SHDN Chip Select/Shutdown Input

VREF Reference Voltage Input

All parameters apply at VDD = 5V, VSS = 0V, VREF = 5V, TAMB = -40°C to +85°C, fSAMPLE = 200 ksps and fCLK = 14*fSAMPLE,

unless otherwise noted. Typical values apply for VDD = 5V, TAMB =25°C, unless otherwise noted.

Parameter Sym Min Typ Max Units Conditions

Conversion Rate:

Conversion Time tCONV — — 10 clock

cycles

Analog Input Sample Time tSAMPLE 1.5 clock

cycles

Throughput Rate fSAMPLE — — 200

75 ksps

ksps VDD = VREF = 5V

VDD = VREF = 2.7V

DC Accuracy:

Resolution 10 bits

Integral Nonlinearity INL — ±0.5 ±1 LSB

Differential Nonlinearity DNL — ±0.25 ±1 LSB No missing codes over tem-

perature

Offset Error — — ±1.5 LSB

Gain Error — — ±1 LSB

Dynamic Performance:

Total Harmonic Distortion THD — -76 — dB VIN = 0.1V to 4.9V@1 kHz

Signal to Noise and Distortion

(SINAD) SINAD — 61 — dB VIN = 0.1V to 4.9V@1 kHz

Spurious Free Dynamic Range SFDR — 80 — dB VIN = 0.1V to 4.9V@1 kHz

Reference Input:

Voltage Range VREF 0.25 — VDD VNote 2

Current Drain IREF —90

0.001 150

3µA

µA CS = VDD = 5V

Note 1: This parameter is guaranteed by characterization and not 100% tested.

2: See graph that relates linearity performance to VREF level.

3: Because the sample cap will eventually lose charge, clock rates below 10 kHz can affect linearity perfor-

mance, especially at elevated temperatures.

MCP3001

Temperature Ranges:

Specified Temperature Range TA-40 — +85 °C

Operating Temperature Range TA-40 — +85 °C

Storage Temperature Range TA-65 — +150 °C

Thermal Package Resistance:

Thermal Resistance, 8L-PDIP θJA —85—°C/W

Thermal Resistance, 8L-SOIC θJA —163—°C/W

Thermal Resistance, 8L-MSOP θJA —206—°C/W

Thermal Resistance, 8L-TSSOP θJA ——°C/W

Analog Inputs:

Input Voltage Range (IN+) IN+ IN- — VREF+IN- V

Input Voltage Range (IN-) IN- VSS-100 — VSS+100 mV

Leakage Current — 0.001 ±1 µA

Switch Resistance RSS —1K— ΩSee Figure 4-1

Sample Capacitor CSAMPLE — 20 — pF See Figure 4-1

Digital Input/Output:

Data Coding Format Straight Binary

High Level Input Voltage VIH 0.7 VDD —— V

Low Level Input Voltage VIL ——0.3 V

DD V

High Level Output Voltage VOH 4.1 — — V IOH = -1 mA, VDD = 4.5V

Low Level Output Voltage VOL ——0.4VI

OL = 1 mA, VDD = 4.5V

Input Leakage Current ILI -10 — 10 µA VIN = VSS or VDD

Output Leakage Current ILO -10 — 10 µA VOUT = VSS or VDD

Pin Capacitance

(all inputs/outputs) CIN, COUT — — 10 pF VDD = 5.0V (Note 1)

TAMB = 25°C, f = 1 MHz

Timing Parameters:

Clock Frequency fCLK ——2.8

1.05 MHz

MHz VDD = 5V (Note 3)

VDD = 2.7V (Note 3)

Clock High Time tHI 160 — — ns

Clock Low Time tLO 160 — — ns

CS Fall To First Rising CLK Edge tSUCS 100 — — ns

CLK Fall To Output Data Valid tDO — — 125

200 ns

ns VDD = 5V, See Figure 1-2

VDD = 2.7, See Figure 1-2

CLK Fall To Output Enable tEN — — 125

200 ns

ns VDD = 5V, See Figure 1-2

VDD = 2.7, See Figure 1-2

CS Rise To Output Disable tDIS — — 100 ns See test circuits, Figure 1-2

(Note 1)

CS Disable Time tCSH 350 — — ns

DOUT Rise Time tR— — 100 ns See test circuits, Figure 1-2

(Note 1)

DOUT Fall Time tF— — 100 ns See test circuits, Figure 1-2

(Note 1)

All parameters apply at VDD = 5V, VSS = 0V, VREF = 5V, TAMB = -40°C to +85°C, fSAMPLE = 200 ksps and fCLK = 14*fSAMPLE,

unless otherwise noted. Typical values apply for VDD = 5V, TAMB =25°C, unless otherwise noted.

Parameter Sym Min Typ Max Units Conditions

Note 1: This parameter is guaranteed by characterization and not 100% tested.

2: See graph that relates linearity performance to VREF level.

3: Because the sample cap will eventually lose charge, clock rates below 10 kHz can affect linearity perfor-

mance, especially at elevated temperatures.

MCP3001

FIGURE 1-1: Serial Timing.

Power Requirements:

Operating Voltage VDD 2.7 — 5.5 V

Operating Current IDD —400

210 500 µA

µA VDD = 5.0V, DOUT unloaded

VDD = 2.7V, DOUT unloaded

Standby Current IDDS —0.005 2 µACS = VDD = 5.0V

All parameters apply at VDD = 5V, VSS = 0V, VREF = 5V, TAMB = -40°C to +85°C, fSAMPLE = 200 ksps and fCLK = 14*fSAMPLE,

unless otherwise noted. Typical values apply for VDD = 5V, TAMB =25°C, unless otherwise noted.

Parameter Sym Min Typ Max Units Conditions

Note 1: This parameter is guaranteed by characterization and not 100% tested.

2: See graph that relates linearity performance to VREF level.

3: Because the sample cap will eventually lose charge, clock rates below 10 kHz can affect linearity perfor-

mance, especially at elevated temperatures.

CLK

tSUCS

tCSH

tHI tLO

DOUT

tEN tDO tRtF

LSB

MSB OUT

tDIS

Null BIT

HI-Z HI-Z

MCP3001

FIGURE 1-2: Test Circuits.

VIH

tDIS

DOUT

Waveform 1*

DOUT

Waveform 2†

90%

10%

* Waveform 1 is for an output with internal condi-

tions such that the output is high, unless disabled

by the output control.

† Waveform 2 is for an output with internal condi-

tions such that the output is low, unless disabled

by the output control.

Voltage Waveforms for tDIS

Test Point

1.4V

DOUT

Load circuit for tR, tF, tDO

3kΩ

CL = 30 pF

Test Point

DOUT

Load circuit for tDIS and tEN

3kΩ

30 pF

tDIS Waveform 2

tDIS Waveform 1

CLK

DOUT

tEN

Voltage Waveforms for tEN

tEN Waveform

VDD

VDD/2

VSS

DOUT

Voltage Waveforms for tR, tF

CLK

DOUT

tDO

Voltage Waveforms for tDO

VOH

VOL

MCP3001

2.0 TYPICAL PERFORMANCE CHARACTERISTICS

Note: Unless otherwise indicated, VDD = VREF = 5V, fSAMPLE = 200 ksps, fCLK = 14*Sample Rate, TA = 25°C

FIGURE 2-1: Integral Nonlinearity (INL) vs. Sample

Rate.

FIGURE 2-2: Integral Nonlinearity (INL) vs. VREF.

FIGURE 2-3: Integral Nonlinearity (INL) vs. Code

(Representative Part).

FIGURE 2-4: Integral Nonlinearity (INL) vs. Sample

Rate (VDD = 2.7V).

FIGURE 2-5: Integral Nonlinearity (INL) vs. VREF

(VDD = 2.7V).

FIGURE 2-6: Integral Nonlinearity (INL) vs. Code

(Representative Part, VDD = 2.7V).

Note: The graphs and tables provided following this note are a statistical summary based on a limited number of

samples and are provided for informational purposes only. The performance characteristics listed herein

are not tested or guaranteed. In some graphs or tables, the data presented may be outside the specified

operating range (e.g., outside specified power supply range) and therefore outside the warranted range.

-0.4

-0.3

-0.2

-0.1

0.0

0.1

0.2

0.3

0.4

0 25 50 75 100 125 150 175 200 225 250

Sample Rate (ksps)

INL (LSB)

Positive INL

Negative INL

-1.0

-0.8

-0.6

-0.4

-0.2

0.0

0.2

0.4

0.6

0.8

1.0

0123456

VREF (V)

INL (LSB)

Positive INL

Negative INL

-0.5

-0.4

-0.3

-0.2

-0.1

0.0

0.1

0.2

0.3

0.4

0.5

0 128 256 384 512 640 768 896 1024

Digital Code

INL (LSB)

VDD = VREF = 5V

fSAMPLE = 200 ksps

-0.4

-0.3

-0.2

-0.1

0.0

0.1

0.2

0.3

0.4

0 25 50 75 100

Sample Rate (ksps)

INL (LSB)

Positive INL

Negative INL

DD = VREF = 2.7V

-1.0

-0.8

-0.6

-0.4

-0.2

0.0

0.2

0.4

0.6

0.8

1.0

0.0 0.5 1.0 1.5 2.0 2.5 3.0

VREF (V)

INL (LSB)

Positive INL

Negative INL

VDD = VREF= 2.7V

fSAMPLE = 75 ksps

-0.50

-0.40

-0.30

-0.20

-0.10

0.00

0.10

0.20

0.30

0.40

0.50

0 128 256 384 512 640 768 896 1024

Digital Code

INL (LSB)

VDD = VREF = 2.7V

fSAMPLE = 75 ksps

MCP3001

Note: Unless otherwise indicated, VDD = VREF = 5V, fSAMPLE = 200 ksps, fCLK = 14*Sample Rate,TA = 25°C

FIGURE 2-7: Integral Nonlinearity (INL) vs.

Temperature.

FIGURE 2-8: Differential Nonlinearity (DNL) vs.

Sample Rate.

FIGURE 2-9: Differential Nonlinearity (DNL) vs.

VREF.

FIGURE 2-10: Integral Nonlinearity (INL) vs.

Temperature (VDD = 2.7V).

FIGURE 2-11: Differential Nonlinearity (DNL) vs.

Sample Rate (VDD = 2.7V).

FIGURE 2-12: Differential Nonlinearity (DNL) vs. VREF

(VDD = 2.7V).

-0.4

-0.3

-0.2

-0.1

0.0

0.1

0.2

0.3

0.4

-50 -25 0 25 50 75 100

Temperature (°C)

INL (LSB)

Positive INL

Negative INL

-0.4

-0.3

-0.2

-0.1

0.0

0.1

0.2

0.3

0.4

0 25 50 75 100 125 150 175 200 225 250

Sample Rate (ksps)

DNL (LSB)

Positive DNL

Negative DNL

-1.0

-0.8

-0.6

-0.4

-0.2

0.0

0.2

0.4

0.6

0.8

1.0

012345

VREF (V)

DNL (LSB)

Negative DNL

Positive DNL

-0.4

-0.3

-0.2

-0.1

0.0

0.1

0.2

0.3

0.4

-50-25 0 255075100

Temperature (°C)

INL (LSB)

Positive INL

VDD = VREF = 2.7V

fSAMPLE = 75 ksps

Negative INL

-0.4

-0.3

-0.2

-0.1

0.0

0.1

0.2

0.3

0.4

0 25 50 75 100

Sample Rate (ksps)

DNL (LSB)

Positive DNL

Negative DNL

VDD = VREF = 2.7V

-1.0

-0.8

-0.6

-0.4

-0.2

0.0

0.2

0.4

0.6

0.8

1.0

0.0 0.5 1.0 1.5 2.0 2.5 3.0

VREF(V)

DNL (LSB)

Positive DNL

Negative DNL

VDD = VREF = 2.7V

fSAMPLE = 75 ksps

MCP3001

Note: Unless otherwise indicated, VDD = VREF = 5V, fSAMPLE = 200 ksps, fCLK = 14*Sample Rate,TA = 25°C

FIGURE 2-13: Differential Nonlinearity (DNL) vs.

Code (Representative Part).

FIGURE 2-14: Differential Nonlinearity (DNL) vs.

Temperature.

FIGURE 2-15: Gain Error vs. VREF.

FIGURE 2-16: Differential Nonlinearity (DNL) vs.

Code (Representative Part, VDD = 2.7V).

FIGURE 2-17: Differential Nonlinearity (DNL) vs.

Temperature (VDD = 2.7V).

FIGURE 2-18: Offset Error vs. VREF.

-0.5

-0.4

-0.3

-0.2

-0.1

0.0

0.1

0.2

0.3

0.4

0.5

0 128 256 384 512 640 768 896 1024

Digital Code

DNL (LSB)

VDD = VREF = 5V

fSAMPLE = 200 ksps

-0.3

-0.2

-0.1

0.0

0.1

0.2

0.3

-50 -25 0 25 50 75 100

Temperature (°C)

DNL (LSB)

Positive DNL

Negative DNL

-1.0

-0.8

-0.6

-0.4

-0.2

0.0

0.2

0.4

0.6

0.8

1.0

012345

VREF(V)

Gain Error (LSB)

VDD = 2.7V

fSAMPLE = 75 ksps

VDD = 5V

fSAMPLE = 200 ksps

-0.5

-0.4

-0.3

-0.2

-0.1

0.0

0.1

0.2

0.3

0.4

0.5

0 128 256 384 512 640 768 896 1024

Digital Code

DNL (LSB)

VDD = VREF = 2.7V

fSAMPLE = 75 ksps

-0.3

-0.2

-0.1

0.0

0.1

0.2

0.3

-50 -25 0 25 50 75 100

Temperature (°C)

DNL (LSB)

Positive DNL

VDD = VREF = 2.7V

fSAMPLE = 75 ksps

Negative DNL

0.0 1.0 2.0 3.0 4.0 5.0

VREF (V)

Offset Error (LSB)

VDD = 5V

fSAMPLE = 200 ksps

VDD = 2.7V

fSAMPLE = 75 ksps

MCP3001

Note: Unless otherwise indicated, VDD = VREF = 5V, fSAMPLE = 200 ksps, fCLK = 14*Sample Rate,TA = 25°C

FIGURE 2-19: Gain Error vs. Temperature.

FIGURE 2-20: Signal to Noise Ratio (SNR) vs. Input

Frequency.

FIGURE 2-21: Total Harmonic Distortion (THD) vs.

Input Frequency.

FIGURE 2-22: Offset Error vs. Temperature.

FIGURE 2-23: Signal to Noise Ratio and Distortion

(SINAD) vs. Input Frequency.

FIGURE 2-24: Signal to Noise and Distortion

(SINAD) vs. Input Signal Level.

-0.4

-0.3

-0.2

-0.1

0.0

0.1

-50 -25 0 25 50 75 100

Temperature (°C)

Gain Error (LSB)

VDD = VREF = 5V

fSAMPLE = 200 ksps

VDD = VREF = 2.7V

fSAMPLE = 75 ksps

1 10 100

Input Frequency (kHz)

SNR (dB)

VDD = VREF = 2.7V

fSAMPLE = 75 ksps

VDD = VREF = 5V

fSAMPLE = 200 ksps

-100

-90

-80

-70

-60

-50

-40

-30

-20

-10

110100

Input Frequency (kHz)

THD (dB)

VDD = VREF = 5V

fSAMPLE = 200 ksps

VDD = VREF = 2.7V

fSAMPLE = 75 ksps

0.0

0.1

0.2

0.3

0.4

0.5

0.6

0.7

0.8

0.9

1.0

-50 -25 0 25 50 75 100

Temperature (°C)

Offset Error (LSB)

VDD = VREF = 5V

SAMPLE

= 200 ksps

VDD = VREF = 2.7V

fSAMPLE = 75 ksps

1 10 100

Input Frequency (kHz)

SINAD (dB)

VDD = VREF = 2.7V

fSAMPLE = 75 ksps VDD = VREF = 5V

fSAMPLE = 200 ksps

-40 -35 -30 -25 -20 -15 -10 -5 0

Input Signal Level (dB)

SINAD (dB)

VDD = VREF = 2.7V

fSAMPLE = 75 ksps

VDD = VREF = 5V

fSAMPLE = 200 ksps

MCP3001

Note: Unless otherwise indicated, VDD = VREF = 5V, fSAMPLE = 200 ksps, fCLK = 14*Sample Rate,TA = 25°C

FIGURE 2-25: Effective Number of Bits (ENOB) vs.

VREF.

FIGURE 2-26: Spurious Free Dynamic Range

(SFDR) vs. Input Frequency.

FIGURE 2-27: Frequency Spectrum of 10 kHz Input

(Representative Part).

FIGURE 2-28: Effective Number of Bits (ENOB) vs.

Input Frequency.

FIGURE 2-29: Power Supply Rejection (PSR) vs.

Ripple Frequency.

FIGURE 2-30: Frequency Spectrum of 1 kHz Input

(Representative Part, VDD = 2.7V).

9.0

9.1

9.2

9.3

9.4

9.5

9.6

9.7

9.8

9.9

10.0

0.0 1.0 2.0 3.0 4.0 5.0

VREF (V)

ENOB (rms)

VDD = VREF = 2.7V

fSAMPLE = 75 ksps

VDD = VREF = 5V

fSAMPLE = 200 ksps

100

110100

Input Frequency (kHz)

SFDR (dB)

VDD = VREF = 5V

fSAMPLE = 200 ksps

VDD = VREF = 2.7V

fSAMPLE = 75 ksps

-130

-120

-110

-100

-90

-80

-70

-60

-50

-40

-30

-20

-10

0 20000 40000 60000 80000 100000

Frequency (Hz)

Amplitude (dB)

VDD = VREF = 5V

fSAMPLE = 200 ksps

fINPUT = 10.0097 kHz

4096 points

8.0

8.2

8.4

8.6

8.8

9.0

9.2

9.4

9.6

9.8

10.0

1 10 100

Input Frequency (kHz)

ENOB (rms)

VDD = VREF = 2.7V

fSAMPLE = 75 ksps

VDD = VREF = 5V

fSAMPLE = 200 ksps

-80

-70

-60

-50

-40

-30

-20

-10

1 10 100 1000 10000

Ripple Frequency (kHz)

Power Supply Rejection (dB)

VDD = VREF = 5V

fSAMPLE = 200 ksps

-130

-120

-110

-100

-90

-80

-70

-60

-50

-40

-30

-20

-10

0 5000 10000 15000 20000 25000 30000 35000

Frequency (Hz)

Amplitude (dB)

VDD = VREF = 2.7V

fSAMPLE = 75 ksps

fINPUT = 1.00708 kHz

4096 points

MCP3001

Note: Unless otherwise indicated, VDD = VREF = 5V, fSAMPLE = 200 ksps, fCLK = 14*Sample Rate,TA = 25°C

FIGURE 2-31: IDD vs. VDD.

FIGURE 2-32: IDD vs. Clock Frequency.

FIGURE 2-33: IDD vs. Temperature.

FIGURE 2-34: IREF vs. VDD.

FIGURE 2-35: IREF vs. Clock Frequency.

FIGURE 2-36: IREF vs. Temperature.

100

150

200

250

300

350

400

450

500

2.02.53.03.54.04.55.05.56.0

VDD (V)

IDD (µA)

VREF = VDD

All points at fCLK = 2.8 MHz except

at VREF = VDD = 2.5V, fCLK

=1.05 MHz

100

150

200

250

300

350

400

450

500

10 100 1000 10000

Clock Frequency (kHz)

IDD (µA)

VDD = VREF = 5V

VDD = VREF = 2.7V

100

150

200

250

300

350

400

450

500

550

600

-50 -25 0 25 50 75 100

Temperature (°C)

IDD (µA)

VDD = VREF = 5V

fCLK = 2.8 MHz

VDD = VREF = 2.7V

fCLK = 1.05 MHz

100

110

120

2.0 2.5 3.0 3.5 4.0 4.5 5.0 5.5 6.0

VDD (V)

IREF

(µA)

VREF = VDD

All points at fCLK = 2.8 MHz except

at VREF = VDD = 2.5V, fCLK

= 1.05 MHz

100

110

120

10 100 1000 10000

Clock Frequency (kHz)

IREF

(µA)

VDD = VREF = 5V

VDD = VREF = 2.7V

100

110

120

-50-25 0 255075100

Temperature (°C)

IREF

(µA)

VDD = VREF = 5V

fCLK = 2.8 MHz

VDD = VREF = 2.7V

fCLK = 1.05 MHz

MCP3001

Note: Unless otherwise indicated, VDD = VREF = 5V, fSAMPLE = 200 ksps, fCLK = 14*Sample Rate,TA = 25°C

FIGURE 2-37: IDDS vs. VDD.

FIGURE 2-38: IDDS vs. Temperature.

FIGURE 2-39: Analog Input Leakage Current vs.

Temperature.

2.0 2.5 3.0 3.5 4.0 4.5 5.0 5.5 6.0

VDD (V)

IDDS (pA)

VREF = CS = VDD

0.01

0.10

1.00

10.00

100.00

-50 -25 0 25 50 75 100

Temperature (°C)

IDDS (nA)

VDD = VREF = CS = 5V

0.0

0.2

0.4

0.6

0.8

1.0

1.2

1.4

1.6

1.8

2.0

-50-25 0 255075100

Temperature (°C)

Analog Input Leakage (nA)

VDD = VREF = 5V

E + CS/SHDNQChig Select/Shutdown) CLK(Seria|Clock1 Reierence Ingut DoUT Serial Data output) Analog lnguls

MCP3001

3.0 PIN DESCRIPTIONS

3.1 IN+

Positive analog input. This input can vary from IN- to

VREF + IN-.

3.2 IN-

Negative analog input. This input can vary ±100 mV

from VSS.

3.3 CS/SHDN(Chip Select/Shutdown)

The CS/SHDN pin is used to initiate communication

with the device when pulled low and will end a conver-

sion and put the device in low power standby when

pulled high. The CS/SHDN pin must be pulled high

between conversions.

3.4 CLK (Serial Clock)

The SPI clock pin is used to initiate a conversion and to

clock out each bit of the conversion as it takes place.

See Section 6.2 for constraints on clock speed.

3.5 DOUT (Serial Data output)

The SPI serial data output pin is used to shift out the

results of the A/D conversion. Data will always change

on the falling edge of each clock as the conversion

takes place.

4.0 DEVICE OPERATION

The MCP3001 A/D converter employs a conventional

SAR architecture. With this architecture, a sample is

acquired on an internal sample/hold capacitor for

1.5 clock cycles starting on the first rising edge of the

serial clock after CS has been pulled low. Following this

sample time, the input switch of the converter opens

and the device uses the collected charge on the inter-

nal sample and hold capacitor to produce a serial 10-bit

digital output code. Conversion rates of 200 ksps are

possible on the MCP3001. See Section 6.2 for informa-

tion on minimum clock rates. Communication with the

device is done using a 3-wire SPI-compatible interface.

4.1 Analog Inputs

The MCP3001 provides a single pseudo-differential

input. The IN+ input can range from IN- to (VREF +IN-).

The IN- input is limited to ±100 mV from the VSS rail.

The IN- input can be used to cancel small signal com-

mon-mode noise which is present on both the IN+ and

IN- inputs.

For the A/D Converter to meet specification, the charge

holding capacitor, CSAMPLE must be given enough time

to acquire a 10-bit accurate voltage level during the

1.5 clock cycle sampling period. The analog input

model is shown in Figure 4-1.

In this diagram, it is shown that the source impedance

(RS) adds to the internal sampling switch, (RSS) imped-

ance, directly affecting the time that is required to

charge the capacitor, CSAMPLE. Consequently, a larger

source impedance increases the offset, gain, and inte-

gral linearity errors of the conversion.

Ideally, the impedance of the signal source should be

near zero. This is achievable with an operational ampli-

fier such as the MCP601, which has a closed loop out-

put impedance of tens of ohms. The adverse affects of

higher source impedances are shown in Figure 4-2.

If the voltage level of IN+ is equal to or less than IN-, the

resultant code will be 000h. If the voltage at IN+ is equal

to or greater than {[VREF + (IN-)] - 1 LSB}, then the out-

put code will be 3FFh. If the voltage level at IN- is more

than 1 LSB below VSS, then the voltage level at the IN+

input will have to go below VSS to see the 000h output

code. Conversely, if IN- is more than 1 LSB above Vss,

then the 3FFh code will not be seen unless the IN+

input level goes above VREF level.

4.2 Reference Input

The reference input (VREF) determines the analog input

voltage range and the LSB size, as shown below.

As the reference input is reduced, the LSB size is

reduced accordingly. The theoretical digital output code

produced by the A/D Converter is a function of the ana-

log input signal and the reference input as shown

below.

where:

VIN = analog input voltage = V(IN+) - V(IN-)

VREF = reference voltage

When using an external voltage reference device, the

system designer should always refer to the manufac-

turer’s recommendations for circuit layout. Any instabil-

ity in the operation of the reference device will have a

direct effect on the operation of the ADC.

LSB Size VREF

1024

-------------=

Digital Output Code 1024*VIN

VREF

------------------------=

MCP3001

FIGURE 4-1: Analog Input Model.

FIGURE 4-2: Maximum Clock Frequency vs. Input

Resistance (RS) to maintain less than a 0.1LSB

deviation in INL from nominal conditions.

CPIN

RSS CHx

7pF

VT = 0.6V

VT = 0.6V ILEAKAGE

Sampling

Switch

SS RS = 1 kΩ

CSAMPLE

= DAC capacitance

VSS

VDD

= 20 pF

±1 nA

Legend

VA = signal source

RSS = source impedance

CHx = input channel pad

CPIN = input pin capacitance

VT= threshold voltage

ILEAKAGE = leakage current at the pin

due to various junctions

SS = sampling switch

RS= sampling switch resistor

CSAMPLE = sample/hold capacitance

0.0

0.5

1.0

1.5

2.0

2.5

3.0

3.5

4.0

100 1000 10000

Input Resistance (Ohms)

Clock Frequency (MHz)

VDD = VREF = 5V

fSAMPLE = 200 ksps

VDD = VREF = 2.7V

fSAMPLE = 75 ksps

MCP3001

5.0 SERIAL COMMUNICATIONS

Communication with the device is done using a stan-

dard SPI compatible serial interface. Initiating commu-

nication with the MCP3001 begins with the CS going

low. If the device was powered up with the CS pin low,

it must be brought high and back low to initiate commu-

nication. The device will begin to sample the analog

input on the first rising edge after CS goes low. The

sample period will end in the falling edge of the second

clock, at which time the device will output a low null bit.

The next 10 clocks will output the result of the conver-

sion with MSB first, as shown in Figure 5-1. Data is

always output from the device on the falling edge of the

clock. If all 10 data bits have been transmitted and the

device continues to receive clocks while the CS is held

low, the device will output the conversion result LSB

first, as shown in Figure 5-2. If more clocks are pro-

vided to the device while CS is still low (after the LSB

first data has been transmitted), the device will clock

out zeros indefinitely.

If it is desired, the CS can be raised to end the conver-

sion period at any time during the transmission. Faster

conversion rates can be obtained by using this tech-

nique if not all the bits are captured before starting a

new cycle. Some system designers use this method by

capturing only the highest order 8 bits and ‘throwing

away’ the lower 2 bits.

FIGURE 5-1: Communication with MCP3001 (MSB first Format).

FIGURE 5-2: Communication with MCP3001 (LSB first Format).

CLK

DOUT

tCYC

Power

Down

tSUCS

tSAMPLE tCONV tDATA**

* After completing the data transfer, if further clocks are applied with CS low, the ADC will output LSB first data,

followed by zeros indefinitely. See Figure below.

** tDATA: during this time, the bias current and the comparator powers down and the reference input becomes a

high impedance node.

tCSH

B9 B8 B7 B6 B5 B4 B3 B2 B1 B0*

HI-Z HI-Z NULL

BIT B9 B8 B7 B6

NULL

BIT

CLK

DOUT

tCYC

Power Down

tSUCS

tSAMPLE tCONV tDATA**

* After completing the data transfer, if further clocks are applied with CS low, the ADC will output zeros indefi-

nitely.

** tDATA: during this time, the bias current and the comparator powers down and the reference input becomes a

high impedance node leaving the CLK running to clock out the LSB-first data or zeros.

tCSH

NULL

BIT B9 B8 B7 B6 B5 B4 B3 B2 B1 B0

HI-Z B1 B2 B3 B4 B5 B6 B7 B8 B9 HI-Z

Using the MCP3001 with Microconlroller SPI Ports

MCP3001

6.0 APPLICATIONS INFORMATION

6.1 Using the MCP3001 with

Microcontroller SPI Ports

With most microcontroller SPI ports, it is required to

clock out eight bits at a time. If this is the case, it will be

necessary to provide more clocks than are required for

the MCP3001. As an example, Figure 6-1 and

Figure 6-2 show how the MCP3001 can be interfaced

to a microcontroller with a standard SPI port. Since the

MCP3001 always clocks data out on the falling edge of

clock, the MCU SPI port must be configured to match

this operation. SPI Mode 0,0 (clock idles low) and SPI

Mode 1,1 (clock idles high) are both compatible with

the MCP3001. Figure 6-1 depicts the operation shown

in SPI Mode 0,0, which requires that the CLK from the

microcontroller idles in the ‘low’ state. As shown in the

diagram, the MSB is clocked out of the ADC on the fall-

ing edge of the third clock pulse. After the first eight

clocks have been sent to the device, the microcontrol-

ler’s receive buffer will contain two unknown bits (the

output is at high impedance for the first two clocks), the

null bit and the highest order five bits of the conversion.

After the second eight clocks have been sent to the

device, the MCU receive register will contain the lowest

order five bits and the B1-B4 bits repeated as the ADC

has begun to shift out LSB first data with the extra

clocks. Typical procedure would then call for the lower

order byte of data to be shifted right by three bits to

remove the extra B1-B4 bits. The B9-B5 bits are then

rotated 3 bits to the right with B7-B5 rotating from the

high order byte to the lower order byte. Easier manipu-

lation of the converted data can be obtained by using

this method.

Figure 6-2 shows SPI Mode 1,1 communication which

requires that the clock idles in the high state. As with

mode 0,0, the ADC outputs data on the falling edge of

the clock and the MCU latches data from the ADC in on

the rising edge of the clock.

FIGURE 6-1: SPI Communication with the MCP3001 using 8-bit segments (Mode 0,0: SCLK idles low).

FIGURE 6-2: SPI Communication with the MCP3001 using 8-bit segments (Mode 1,1: SCLK idles high).

CLK 910111213141516

DOUT

NULL

BIT B9 B8 B7 B6 B5 B4 B3 B2 B1 B0 B1 B2

HI-Z

B5 B4 B3 B2 B1 B0 B1 B2B9 B8 B7 B6??0

MCU latches data from ADC

Data is clocked out of

ADC on falling edges

on rising edges of SCLK

12345678

HI-Z

LSB first data begins

to come out

Data stored into MCU receive register

after transmission of first 8 bits Data stored into MCU receive register

after transmission of second 8 bits

CLK 9101112131415 16

DOUT

NULL

BIT B9 B8 B7 B6 B5 B4 B3 B2 B1 B0 B1 B2

HI-Z

B5 B4 B3 B2 B1 B0 B1 B2

B9 B8 B7 B6??0

MCU latches data from ADC

Data is clocked out of

ADC on falling edges

on rising edges of SCLK

1234567 8

LSB first data begins

to come out

HI-Z

Data stored into MCU receive register

after transmission of first 8 bits Data stored into MCU receive register

after transmission of second 8 bits

Maintaining Minimum Clock Speed Layout Considerations Buftering/Filtering the Analog Inguts

MCP3001

6.2 Maintaining Minimum Clock Speed

When the MCP3001 initiates the sample period, charge

is stored on the sample capacitor. When the sample

period is complete, the device converts one bit for each

clock that is received. It is important for the user to note

that a slow clock rate will allow charge to bleed off the

sample cap while the conversion is taking place. At

85°C (worst case condition), the part will maintain

proper charge on the sample cap for 700 µs at

VDD = 2.7V and 1.5 ms at VDD = 5V. This means that at

VDD = 2.7V, the time it takes to transmit the first 14

clocks must not exceed 700 µs. Failure to meet this cri-

terion may induce linearity errors into the conversion

outside the rated specifications.

6.3 Buffering/Filtering the Analog Inputs

If the signal source for the ADC is not a low impedance

source, it will have to be buffered or inaccurate conver-

sion results may occur. See Figure 4-2. It is also rec-

ommended that a filter be used to eliminate any signals

that may be aliased back into the conversion results.

This is illustrated in Figure 6-3 where an op amp is

used to drive, filter and gain the analog input of the

MCP3001. This amplifier provides a low impedance

source for the converter input and a low pass filter,

which eliminates unwanted high frequency noise.

Low pass (anti-aliasing) filters can be designed using

Microchip’s interactive FilterLab™ software. FilterLab

will calculate capacitor and resistor values, as well as

determine the number of poles that are required for the

application. For more information on filtering signals,

see the application note AN699 “Anti-Aliasing Analog

Filters for Data Acquisition Systems.”

FIGURE 6-3: The MCP601 operational amplifier is

used to implement a 2nd order anti-aliasing filter for

the signal being converted by the MCP3001.

6.4 Layout Considerations

When laying out a printed circuit board for use with

analog components, care should be taken to reduce

noise wherever possible. A bypass capacitor should

always be used with this device and should be placed

as close as possible to the device pin. A bypass capac-

itor value of 1 µF is recommended.

Digital and analog traces should be separated as much

as possible on the board and no traces should run

underneath the device or the bypass capacitor. Extra

precautions should be taken to keep traces with high

frequency signals (such as clock lines) as far as possi-

ble from analog traces.

Use of an analog ground plane is recommended in

order to keep the ground potential the same for all

devices on the board. Providing VDD connections to

devices in a “star” configuration can also reduce noise

by eliminating current return paths and associated

errors. See Figure 6-4. For more information on layout

tips when using ADC, refer to AN-688 “Layout Tips for

12-Bit A/D Converter Applications”.

FIGURE 6-4: VDD traces arranged in a ‘Star’

configuration in order to reduce errors caused by

current return paths.

MCP3001

VDD

10 µF

IN-

IN+

VIN

VREF

4.096V

Reference

1µF

10 µF

0.1 µF

MCP601

R3R4

MCP1541 CL

VDD

Connection

Device 1

Device 2

Device 3

Device 4

Package Marking Information Hfﬁfﬁﬂ LALuJLuJLJ HHHH UUUU HHHH ¢9C3 UHHU F‘Wﬁﬂﬂ 01 LALLALLALJ HHHH \SN UUUU HHHH ¢3

MCP3001

7.0 PACKAGING INFORMATION

7.1 Package Marking Information

Legend: XX...X Customer-specific information

Y Year code (last digit of calendar year)

YY Year code (last 2 digits of calendar year)

WW Week code (week of January 1 is week ‘01’)

NNN Alphanumeric traceability code

Pb-free JEDEC designator for Matte Tin (Sn)

*This package is Pb-free. The Pb-free JEDEC designator ( )

can be found on the outer packaging for this package.

Note: In the event the full Microchip part number cannot be marked on one line, it wi

be carried over to the next line, thus limiting the number of available

characters for customer-specific information.

XXXXXXXX

XXXXXNNN

YYWW

8-Lead PDIP (300 mil) Example:

8-Lead SOIC (150 mil) Example:

XXXXXXXX

XXXXYYWW

NNN

8-Lead TSSOP Example:

MCP3001

I/PNNN

0736

MCP3001

NNN

8-Lead MSOP Example:

XXXX

YYWW

NNN

XXXXXX

YWWNNN

3001

0716

NNN

3001I

725NNN

ISN 0736

MCP3001

8-Lead Plastic Dual In-Line (P) – 300 mil Body [PDIP]

otes:

. Pin 1 visual index feature may vary, but must be located with the hatched area.

. § Significant Characteristic.

. Dimensions D and E1 do not include mold flash or protrusions. Mold flash or protrusions shall not exceed .010" per side.

. Dimensioning and tolerancing per ASME Y14.5M.

BSC: Basic Dimension. Theoretically exact value shown without tolerances.

Note: For the most current package drawings, please see the Microchip Packaging Specification located at

http://www.microchip.com/packaging

Units INCHES

Dimension Limits MIN NOM MAX

Number of Pins N 8

Pitch e .100 BSC

Top to Seating Plane A – – .210

Molded Package Thickness A2 .115 .130 .195

Base to Seating Plane A1 .015 – –

Shoulder to Shoulder Width E .290 .310 .325

Molded Package Width E1 .240 .250 .280

Overall Length D .348 .365 .400

Tip to Seating Plane L .115 .130 .150

Lead Thickness c .008 .010 .015

Upper Lead Width b1 .040 .060 .070

Lower Lead Width b .014 .018 .022

Overall Row Spacing § eB – – .430

NOTE 1

Microchip Technology Drawing C04-018

MCP3001

8-Lead Plastic Small Outline (SN) – Narrow, 3.90 mm Body [SOIC]

otes:

. Pin 1 visual index feature may vary, but must be located within the hatched area.

. § Significant Characteristic.

. Dimensions D and E1 do not include mold flash or protrusions. Mold flash or protrusions shall not exceed 0.15 mm per side.

. Dimensioning and tolerancing per ASME Y14.5M.

BSC: Basic Dimension. Theoretically exact value shown without tolerances.

REF: Reference Dimension, usually without tolerance, for information purposes only.

Note: For the most current package drawings, please see the Microchip Packaging Specification located at

http://www.microchip.com/packaging

Units MILLMETERS

Dimension Limits MIN NOM MAX

Number of Pins N 8

Pitch e 1.27 BSC

Overall Height A – – 1.75

Molded Package Thickness A2 1.25 – –

Standoff §A1 0.10 – 0.25

Overall Width E 6.00 BSC

Molded Package Width E1 3.90 BSC

Overall Length D 4.90 BSC

Chamfer (optional) h 0.25 – 0.50

Foot Length L 0.40 – 1.27

Footprint L1 1.04 REF

Foot Angle φ0° – 8°

Lead Thickness c 0.17 – 0.25

Lead Width b 0.31 – 0.51

Mold Draft Angle Top α5° – 15°

Mold Draft Angle Bottom β5° – 15°

NOTE 1

12 3

Microchip Technology Drawing C04-057

, ,x MUD

MCP3001

8-Lead Plastic Micro Small Outline Package (MS) [MSOP]

otes:

. Pin 1 visual index feature may vary, but must be located within the hatched area.

. Dimensions D and E1 do not include mold flash or protrusions. Mold flash or protrusions shall not exceed 0.15 mm per side.

. Dimensioning and tolerancing per ASME Y14.5M.

BSC: Basic Dimension. Theoretically exact value shown without tolerances.

REF: Reference Dimension, usually without tolerance, for information purposes only.

Note: For the most current package drawings, please see the Microchip Packaging Specification located at

http://www.microchip.com/packaging

Units MILLIMETERS

Dimension Limits MIN NOM MAX

Number of Pins N 8

Pitch e 0.65 BSC

Overall Height A – – 1.10

Molded Package Thickness A2 0.75 0.85 0.95

Standoff A1 0.00 – 0.15

Overall Width E 4.90 BSC

Molded Package Width E1 3.00 BSC

Overall Length D 3.00 BSC

Foot Length L 0.40 0.60 0.80

Footprint L1 0.95 REF

Foot Angle φ0° – 8°

Lead Thickness c 0.08 – 0.23

Lead Width b 0.22 – 0.40

NOTE 1

L1 L

Microchip Technology Drawing C04-111

MCP3001

8-Lead Plastic Thin Shrink Small Outline (ST) – 4.4 mm Body [TSSOP]

otes:

. Pin 1 visual index feature may vary, but must be located within the hatched area.

. Dimensions D and E1 do not include mold flash or protrusions. Mold flash or protrusions shall not exceed 0.15 mm per side.

. Dimensioning and tolerancing per ASME Y14.5M.

BSC: Basic Dimension. Theoretically exact value shown without tolerances.

REF: Reference Dimension, usually without tolerance, for information purposes only.

Note: For the most current package drawings, please see the Microchip Packaging Specification located at

http://www.microchip.com/packaging

Units MILLIMETERS

Dimension Limits MIN NOM MAX

Number of Pins N 8

Pitch e 0.65 BSC

Overall Height A – – 1.20

Molded Package Thickness A2 0.80 1.00 1.05

Standoff A1 0.05 – 0.15

Overall Width E 6.40 BSC

Molded Package Width E1 4.30 4.40 4.50

Molded Package Length D 2.90 3.00 3.10

Foot Length L 0.45 0.60 0.75

Footprint L1 1.00 REF

Foot Angle φ0° – 8°

Lead Thickness c 0.09 – 0.20

Lead Width b 0.19 – 0.30

NOTE 1

L1 L

Microchip Technology Drawing C04-086

MCP3001

APPENDIX A: REVISION HISTORY

Revision C (January 2007)

This revision includes updates to the packaging

diagrams.

NOTES:

PART NO. /XX

MCP3001

PRODUCT IDENTIFICATION SYSTEM

To order or obtain information, e.g., on pricing or delivery, refer to the factory or the listed sales office.

PART NO. X/XX

PackageTemperature

Range

Device

Device: MCP3001: 10-Bit Serial A/D Converter

MCP3001T: 10-Bit Serial A/D Converter

(Tape and Reel) (SOIC and TSSOP only)

Temperature Range: I = -40°C to +85°C

Package: P = Plastic DIP (300 mil Body), 8-lead

SN = Plastic SOIC (150 mil Body), 8-lead

MS = Plastic Micro Small Outline (MSOP), 8-lead

ST = Plastic TSSOP (4.4 mm), 8-lead

Examples:

a) MCP3001-I/P: Industrial Temperature,

PDIP package.

b) MCP3001-I/SN: Industrial Temperature,

SOIC package.

c) MCP3001-I/ST: Industrial Temperature,

TSSOP package.

d) MCP3001-I/MS: Industrial Temperature,

MSOP package.

MCP3001

NOTES:

QUALITY MANAGEMENT SYSTEM CERTIFIED BY DNV = ISO/TS 16949:2002 =

Information contained in this publication regarding device

applications and the like is provided only for your convenience

and may be superseded by updates. It is your responsibility to

ensure that your application meets with your specifications.

MICROCHIP MAKES NO REPRESENTATIONS OR

WARRANTIES OF ANY KIND WHETHER EXPRESS OR

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Trademarks

The Microchip name and logo, the Microchip logo, Accuron,

dsPIC, KEELOQ, microID, MPLAB, PIC, PICmicro, PICSTART,

PRO MATE, PowerSmart, rfPIC, and SmartShunt are

registered trademarks of Microchip Technology Incorporated

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Company are registered trademarks of Microchip Technology

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All other trademarks mentioned herein are property of their

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Printed on recycled paper.

Note the following details of the code protection feature on Microchip devices:

• Microchip products meet the specification contained in their particular Microchip Data Sheet.

• Microchip believes that its family of products is one of the most secure families of its kind on the market today, when used in the

intended manner and under normal conditions.

• There are dishonest and possibly illegal methods used to breach the code protection feature. All of these methods, to our

knowledge, require using the Microchip products in a manner outside the operating specifications contained in Microchip’s Data

Sheets. Most likely, the person doing so is engaged in theft of intellectual property.

• Microchip is willing to work with the customer who is concerned about the integrity of their code.

• Neither Microchip nor any other semiconductor manufacturer can guarantee the security of their code. Code protection does not

mean that we are guaranteeing the product as “unbreakable.”

Code protection is constantly evolving. We at Microchip are committed to continuously improving the code protection features of our

products. Attempts to break Microchip’s code protection feature may be a violation of the Digital Millennium Copyright Act. If such acts

allow unauthorized access to your software or other copyrighted work, you may have a right to sue for relief under that Act.

Microchip received ISO/TS-16949:2002 certification for its worldwide

headquarters, design and wafer fabrication facilities in Chandler and

Tempe, Arizona, Gresham, Oregon and Mountain View, California. The

Company’s quality system processes and procedures are for its PIC®

MCUs and dsPIC DSCs, KEELOQ® code hopping devices, Serial

EEPROMs, microperipherals, nonvolatile memory and analog

products. In addition, Microchip’s quality system for the design and

manufacture of development systems is ISO 9001:2000 certified.

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Fax: 82-54-473-4302

Korea - Seoul

Tel: 82-2-554-7200

Fax: 82-2-558-5932 or

82-2-558-5934

Malaysia - Penang

Tel: 60-4-646-8870

Fax: 60-4-646-5086

Philippines - Manila

Tel: 63-2-634-9065

Fax: 63-2-634-9069

Singapore

Tel: 65-6334-8870

Fax: 65-6334-8850

Taiwan - Hsin Chu

Tel: 886-3-572-9526

Fax: 886-3-572-6459

Taiwan - Kaohsiung

Tel: 886-7-536-4818

Fax: 886-7-536-4803

Taiwan - Taipei

Tel: 886-2-2500-6610

Fax: 886-2-2508-0102

Thailand - Bangkok

Tel: 66-2-694-1351

Fax: 66-2-694-1350

EUROPE

Austria - Wels

Tel: 43-7242-2244-39

Fax: 43-7242-2244-393

Denmark - Copenhagen

Tel: 45-4450-2828

Fax: 45-4485-2829

France - Paris

Tel: 33-1-69-53-63-20

Fax: 33-1-69-30-90-79

Germany - Munich

Tel: 49-89-627-144-0

Fax: 49-89-627-144-44

Italy - Milan

Tel: 39-0331-742611

Fax: 39-0331-466781

Netherlands - Drunen

Tel: 31-416-690399

Fax: 31-416-690340

Spain - Madrid

Tel: 34-91-708-08-90

Fax: 34-91-708-08-91

UK - Wokingham

Tel: 44-118-921-5869

Fax: 44-118-921-5820

WORLDWIDE SALES AND SERVICE

12/08/06

Datenblatt für MCP3001 Data Sheet von Microchip Technology

INFORMATION

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