Datenblatt für STK11C88 von Infineon Technologies

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STK11C88
256 Kbit (32K x 8) SoftStore nvSRAM
Cypress Semiconductor Corporation • 198 Champion Court • San Jose,CA 95134-1709 • 408-943-2600
Document Number: 001-50591 Rev. *A Revised December 11, 2009
Features
■25 ns and 45 ns Access Times
■Pin Compatible with Industry Standard SRAMs
■Software initiated STORE and RECALL
■Automatic RECALL to SRAM on Power Up
■Unlimited Read and Write endurance
■Unlimited RECALL Cycles
■1,000,000 STORE Cycles
■100 year Data Retention
■Single 5V+10% Power Supply
■Commercial and Industrial Temperatures
■28-pin (300 mil and 330 mil) SOIC packages
■RoHS compliance
Functional Description
The Cypress STK11C88 is a 256 Kb fast static RAM with a
nonvolatile element in each memory cell. The embedded
nonvolatile elements incorporate QuantumTrap technology
producing the world’s most reliable nonvolatile memory. The
SRAM provides unlimited read and write cycles, while
independent, nonvolatile data resides in the highly reliable
QuantumTrap cell. Data transfers under Software control from
SRAM to the nonvolatile elements (the STORE operation). On
power up, data is automatically restored to the SRAM (the
RECALL operation) from the nonvolatile memory. RECALL
operations are also available under software control.
Logic Block Diagram
Not recommended for new designs.
In production to support ongoing production programs only.
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STK11C88
Document Number: 001-50591 Rev. *A Page 2 of 16
Contents
Features ............................................................................... 1
Functional Description ....................................................... 1
Logic Block Diagram .......................................................... 1
Contents .............................................................................. 2
Pin Configurations ............................................................. 3
Device Operation ................................................................ 4
SRAM Read ......................................................................... 4
SRAM Write ......................................................................... 4
Software STORE ................................................................. 4
Software RECALL ............................................................... 4
Hardware RECALL (Power Up) .......................................... 4
Hardware Protect ................................................................ 5
Noise Considerations ......................................................... 5
Low Average Active Power ................................................ 5
Best Practices ..................................................................... 5
Maximum Ratings ............................................................... 7
Operating Range ................................................................. 7
DC Electrical Characteristics ............................................ 7
Data Retention and Endurance ......................................... 7
Capacitance ........................................................................ 8
Thermal Resistance ............................................................ 8
AC Test Conditions ............................................................ 8
AC Switching Characteristics ........................................... 9
SRAM Read Cycle ........................................................ 9
Switching Waveforms ........................................................ 9
SRAM Write Cycle....................................................... 10
Switching Waveforms ...................................................... 10
STORE INHIBIT or Power Up RECALL ........................... 11
Switching Waveforms ...................................................... 11
Software Controlled STORE/RECALL Cycle .................. 12
Switching Waveforms ...................................................... 12
Part Numbering Nomenclature ........................................ 13
Ordering Information ........................................................ 13
Package Diagrams ............................................................ 14
Document History Page ................................................... 16
Sales, Solutions and Legal Information ......................... 16
Worldwide Sales and Design Support......................... 16
Products...................................................................... 16
Not recommended for new designs.
In production to support ongoing production programs only.
[+] Feedback
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STK11C88
Document Number: 001-50591 Rev. *A Page 3 of 16
Pin Configurations
Figure 1. Pin Diagram - 28-Pin SOIC
Table 1. Pin Definitions - 28-Pin SOIC
Pin Name Alt I/O Type Description
A0–A14 Input Address Inputs. Used to select one of the 32,768 bytes of the nvSRAM.
DQ0-DQ7Input or
Output Bidirectional Data I/O lines. Used as input or output lines depending on operation.
WE WInput Write Enable Input, Active LOW. When the chip is enabled and WE is LOW, data on the
I/O pins is written to the specific address location.
CE EInput Chip Enable Input, Active LOW. When LOW, selects the chip. When HIGH, deselects the
chip.
OE GInput Output Enable, Active LOW. The active LOW OE input enables the data output buffers
during read cycles. Deasserting OE HIGH causes the I/O pins to tristate.
VSS Ground Ground for the Device. The device is connected to the ground of the system.
VCC Power Supply Power Supply Inputs to the Device.
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Not recommended for new designs.
In production to support ongoing production programs only.
[+] Feedback
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STK11C88
Document Number: 001-50591 Rev. *A Page 4 of 16
Device Operation
The STK11C88 is a versatile memory chip that provides
several modes of operation. The STK11C88 can operate as a
standard 32K x 8 SRAM. A 32K x 8 array of nonvolatile storage
elements shadow the SRAM. SRAM data can be copied from
nonvolatile memory or nonvolatile data can be recalled to the
SRAM.
SRAM Read
The STK11C88 performs a READ cycle whenever CE and OE
are LOW, while WE is HIGH. The address specified on pins
A0–14 determines the 32,768 data bytes accessed. When the
READ is initiated by an address transition, the outputs are
valid after a delay of tAA (READ cycle 1). If the READ is
initiated by CE or OE, the outputs are valid at tACE or at tDOE,
whichever is later (READ cycle 2). The data outputs
repeatedly respond to address changes within the tAA access
time without the need for transitions on any control input pins,
and remain valid until another address change or until CE or
OE is brought HIGH.
SRAM Write
A WRITE cycle is performed whenever CE and WE are LOW.
The address inputs must be stable prior to entering the WRITE
cycle and must remain stable until either CE or WE goes HIGH
at the end of the cycle. The data on the common I/O pins
DQ0–7 are written into the memory if it has valid tSD, before the
end of a WE controlled WRITE or before the end of an CE
controlled WRITE. Keep OE HIGH during the entire WRITE
cycle to avoid data bus contention on common I/O lines. If OE
is left LOW, internal circuitry turns off the output buffers tHZWE
after WE goes LOW.
Software STORE
Data is transferred from the SRAM to the nonvolatile memory
by a software address sequence. The STK11C88 software
STORE cycle is initiated by executing sequential CE controlled
READ cycles from six specific address locations in exact
order. During the STORE cycle, an erase of the previous
nonvolatile data is first performed, followed by a program of
the nonvolatile elements. When a STORE cycle is initiated,
input and output are disabled until the cycle is completed.
Because a sequence of READs from specific addresses is
used for STORE initiation, it is important that no other READ
or WRITE accesses intervene in the sequence. If they
intervene, the sequence is aborted and no STORE or RECALL
takes place.
To initiate the software STORE cycle, the following READ
sequence is performed:
1. Read address 0x0E38, Valid READ
2. Read address 0x31C7, Valid READ
3. Read address 0x03E0, Valid READ
4. Read address 0x3C1F, Valid READ
5. Read address 0x303F, Valid READ
6. Read address 0x0FC0, Initiate STORE cycle
The software sequence is clocked with CE controlled READs.
When the sixth address in the sequence is entered, the
STORE cycle commences and the chip is disabled. It is
important that READ cycles and not WRITE cycles are used
in the sequence. It is not necessary that OE is LOW for a valid
sequence. After the tSTORE cycle time is fulfilled, the SRAM is
again activated for READ and WRITE operation.
Software RECALL
Data is transferred from the nonvolatile memory to the SRAM
by a software address sequence. A software RECALL cycle is
initiated with a sequence of READ operations in a manner
similar to the software STORE initiation. To initiate the
RECALL cycle, the following sequence of CE controlled READ
operations is performed:
1. Read address 0x0E38, Valid READ
2. Read address 0x31C7, Valid READ
3. Read address 0x03E0, Valid READ
4. Read address 0x3C1F, Valid READ
5. Read address 0x303F, Valid READ
6. Read address 0x0C63, Initiate RECALL cycle
Internally, RECALL is a two step procedure. First, the SRAM
data is cleared, and then the nonvolatile information is trans-
ferred into the SRAM cells. After the tRECALL cycle time, the
SRAM is once again ready for READ and WRITE operations.
The RECALL operation does not alter the data in the nonvol-
atile elements. The nonvolatile data can be recalled an
unlimited number of times.
Hardware RECALL (Power Up)
During power up or after any low power condition
(VCC<VRESET), an internal RECALL request is latched. When
VCC once again exceeds the sense voltage of VSWITCH, a
RECALL cycle is automatically initiated and takes tHRECALL to
complete.
If the STK11C88 is in a WRITE state at the end of power up
RECALL, the SRAM data is corrupted. To help avoid this
situation, a 10 Kohm resistor is connected either between WE
and system VCC or between CE and system VCC.
Not recommended for new designs.
In production to support ongoing production programs only.
[+] Feedback
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STK11C88
Document Number: 001-50591 Rev. *A Page 5 of 16
Hardware Protect
The STK11C88 offers hardware protection against inadvertent
STORE operation and SRAM WRITEs during low voltage condi-
tions. When VCC<VSWITCH, all externally initiated STORE opera-
tions and SRAM WRITEs are inhibited.
Noise Considerations
The STK11C88 is a high speed memory. It must have a high
frequency bypass capacitor of approximately 0.1 µF connected
between VCC and VSS, using leads and traces that are as short
as possible. As with all high speed CMOS ICs, careful routing of
power, ground, and signals help prevent noise problems.
Low Average Active Power
CMOS technology provides the STK11C88 the benefit of
drawing significantly less current when it is cycled at times longer
than 50 ns. Figure 2 and Figure 3 show the relationship between
ICC and READ or WRITE cycle time. Worst case current
consumption is shown for both CMOS and TTL input levels
(commercial temperature range, VCC = 5.5V, 100 percent duty
cycle on chip enable). Only standby current is drawn when the
chip is disabled. The overall average current drawn by the
STK11C88 depends on the following items:
1. The duty cycle of chip enable
2. The overall cycle rate for accesses
3. The ratio of READs to WRITEs
4. CMOS versus TTL input levels
5. The operating temperature
6. The VCC level
7. I/O loading
Best Practices
nvSRAM products have been used effectively for over 15 years.
While ease-of-use is one of the product’s main system values,
the experience gained working with hundreds of applications has
resulted in the following suggestions as best practices:
■The nonvolatile cells in a nvSRAM are programmed on the test
floor during final test and quality assurance. Incoming
inspection routines at customer or contract manufacturer’s
sites, sometimes, reprogram these values. Final NV patterns
are typically repeating patterns of AA, 55, 00, FF, A5, or 5A.
The end product’s firmware should not assume that a NV array
is in a set programmed state. Routines that check memory
content values to determine first time system configuration and
cold or warm boot status, should always program a unique NV
pattern (for example, a complex 4-byte pattern of 46 E6 49 53
hex or more random bytes) as part of the final system manufac-
turing test to ensure these system routines work consistently.
■Power up boot firmware routines should rewrite the nvSRAM
into the desired state. While the nvSRAM is shipped in a preset
state, best practice is to again rewrite the nvSRAM into the
desired state as a safeguard against events that might flip the
bit inadvertently (program bugs or incoming inspection
routines).
Figure 2. Icc (max) Reads
Figure 3. Icc (max) Writes
Not recommended for new designs.
In production to support ongoing production programs only.
[+] Feedback
a; CYPRESS lrnIo-M c: WE A1: ‘0 Data Data utput Data Output Data Output Data 0
STK11C88
Document Number: 001-50591 Rev. *A Page 6 of 16
Table 2. Software STORE/RECALL Mode Selection
CE WE A13 – A0Mode I/O Notes
L H 0x0E38
0x31C7
0x03E0
0x3C1F
0x303F
0x0FC0
Read SRAM
Read SRAM
Read SRAM
Read SRAM
Read SRAM
Nonvolatile STORE
Output Data
Output Data
Output Data
Output Data
Output Data
Output Data
[1, 2]
L H 0x0E38
0x31C7
0x03E0
0x3C1F
0x303F
0x0C63
Read SRAM
Read SRAM
Read SRAM
Read SRAM
Read SRAM
Nonvolatile RECALL
Output Data
Output Data
Output Data
Output Data
Output Data
Output Data
[1, 2]
Notes
1. The six consecutive addresses must be in the order listed. WE must be high during all six consecutive CE controlled cycles to enable a nonvolatile cycle.
2. While there are 15 addresses on the STK11C88, only the lower 14 are used to control software modes.
Not recommended for new designs.
In production to support ongoing production programs only.
[+] Feedback
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STK11C88
Document Number: 001-50591 Rev. *A Page 7 of 16
Maximum Ratings
Exceeding maximum ratings may shorten the useful life of the
device. These user guidelines are not tested.
Storage Temperature ................................. –65°C to +150°C
Temperature under bias.............................. –55°C to +125°C
Supply Voltage on VCC Relative to GND..........–0.5V to 7.0V
Voltage on Input Relative to Vss............–0.6V to VCC + 0.5V
Voltage on DQ0-7 ...................................–0.5V to Vcc + 0.5V
Power Dissipation ......................................................... 1.0W
DC Output Current (1 output at a time, 1s duration).... 15 mA
Operating Range
Range Ambient Temperature VCC
Commercial 0°C to +70°C 4.5V to 5.5V
Industrial -40°C to +85°C 4.5V to 5.5V
DC Electrical Characteristics
Over the operating range (VCC = 4.5V to 5.5V)
Parameter Description Test Conditions Min Max Unit
ICC1 Average VCC Current tRC = 25 ns
tRC = 45 ns
Dependent on output loading and cycle rate.
Values obtained without output loads.
IOUT = 0 mA.
Commercial 97
70 mA
mA
Industrial 100
70 mA
mA
ICC2 Average VCC Current
during STORE All Inputs Do Not Care, VCC = Max
Average current for duration tSTORE
3mA
ICC3 Average VCC Current
at tRC= 200 ns, 5V,
25°C Typical
WE > (VCC – 0.2V). All other inputs cycling.
Dependent on output loading and cycle rate. Values obtained
without output loads.
10 mA
ISB1[3] Average VCC Current
(Standby, Cycling
TTL Input Levels)
tRC=25ns, CE > VIH
tRC=45ns, CE > VIH
Commercial 30
22 mA
Industrial 31
23 mA
ISB2[3] VCC Standby Current
(Standby, Stable
CMOS Input Levels)
CE > (VCC – 0.2V). All others VIN < 0.2V or > (VCC – 0.2V). 750 μA
IIX Input Leakage
Current VCC = Max, VSS < VIN < VCC -1 +1 μA
IOZ Off State Output
Leakage Current VCC = Max, VSS < VIN < VCC, CE or OE > VIH or WE < VIL -5 +5 μA
VIH Input HIGH Voltage 2.2 VCC +
0.5 V
VIL Input LOW Voltage VSS –
0.5 0.8 V
VOH Output HIGH Voltage IOUT = –4 mA 2.4 V
VOL Output LOW Voltage IOUT = 8 mA 0.4 V
Data Retention and Endurance
Parameter Description Min Unit
DATARData Retention 100 Years
NVCNonvolatile STORE Operations 1,000 K
Not recommended for new designs.
In production to support ongoing production programs only.
[+] Feedback
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STK11C88
Document Number: 001-50591 Rev. *A Page 8 of 16
Capacitance
In the following table, the capacitance parameters are listed.[4]
Parameter Description Test Conditions Max Unit
CIN Input Capacitance TA = 25°C, f = 1 MHz,
VCC = 0 to 3.0 V 5pF
COUT Output Capacitance 7 pF
Thermal Resistance
In the following table, the thermal resistance parameters are listed.[4]
Parameter Description Test Conditions 28-SOIC
(300 mil) 28-SOIC
(330 mil) Unit
ΘJA Thermal Resistance
(Junction to Ambient) Test conditions follow standard test methods and
procedures for measuring thermal impedance,
per EIA / JESD51.
TBD TBD °C/W
ΘJC Thermal Resistance
(Junction to Case) TBD TBD °C/W
Figure 4. AC Test Loads
AC Test Conditions
5.0V
Output
30 pF
R1 480Ω
R2
255Ω
Input Pulse Levels..................................................0 V to 3 V
Input Rise and Fall Times (10% - 90%)........................ <5 ns
Input and Output Timing Reference Levels................... 1.5 V
Note
4. These parameters are guaranteed by design and are not tested.
Not recommended for new designs.
In production to support ongoing production programs only.
[+] Feedback
55 a] CYPRESS r‘gi)‘ H. 1: Address Controlled [5 Figure 6. SRAM Re r——>
STK11C88
Document Number: 001-50591 Rev. *A Page 9 of 16
AC Switching Characteristics
SRAM Read Cycle
Parameter Description 25 ns 45 ns Unit
Min Max Min Max
Cypress
Parameter Alt
tACE tELQV Chip Enable Access Time 25 45 ns
tRC [5] tAVAV, tELEH Read Cycle Time 25 45 ns
tAA [6] tAVQV Address Access Time 25 45 ns
tDOE tGLQV Output Enable to Data Valid 10 20 ns
tOHA [6] tAXQX Output Hold After Address Change 5 5 ns
tLZCE [7] tELQX Chip Enable to Output Active 5 5 ns
tHZCE [7] tEHQZ Chip Disable to Output Inactive 10 15 ns
tLZOE [7] tGLQX Output Enable to Output Active 0 0 ns
tHZOE [7] tGHQZ Output Disable to Output Inactive 10 15 ns
tPU [4] tELICCH Chip Enable to Power Active 0 0 ns
tPD [4] tEHICCL Chip Disable to Power Standby 25 45 ns
Switching Waveforms
Figure 5. SRAM Read Cycle 1: Address Controlled [5, 6]
Figure 6. SRAM Read Cycle 2: CE and OE Controlled [5]
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Notes
5. WE must be HIGH during SRAM Read Cycles and LOW during SRAM WRITE cycles.
6. I/O state assumes CE and OE < VIL and WE > VIH; device is continuously selected.
7. Measured ±200 mV from steady state output voltage.
Not recommended for new designs.
In production to support ongoing production programs only.
[+] Feedback
3‘“. aicYFBFSS. thwz — Controlled [a] [AW 7 ‘rw i 40:77 _ _. M—fi Flgure 55 7 e ‘7 cs #_7 — DATA OUT
STK11C88
Document Number: 001-50591 Rev. *A Page 10 of 16
SRAM Write Cycle
Parameter Description 25 ns 45 ns Unit
Min Max Min Max
Cypress
Parameter Alt
tWC tAVAV Write Cycle Time 25 45 ns
tPWE tWLWH, tWLEH Write Pulse Width 20 30 ns
tSCE tELWH, tELEH Chip Enable To End of Write 20 30 ns
tSD tDVWH, tDVEH Data Setup to End of Write 10 15 ns
tHD tWHDX, tEHDX Data Hold After End of Write 0 0 ns
tAW tAVWH, tAVEH Address Setup to End of Write 20 30 ns
tSA tAVWL, tAVEL Address Setup to Start of Write 0 0 ns
tHA tWHAX, tEHAX Address Hold After End of Write 0 0 ns
tHZWE [7,8] tWLQZ Write Enable to Output Disable 10 15 ns
tLZWE [7] tWHQX Output Active After End of Write 5 5 ns
Switching Waveforms
Figure 7. SRAM Write Cycle 1: WE Controlled [9]
Figure 8. SRAM Write Cycle 2: CE Controlled [9]
t
WC
t
SCE
t
HA
t
AW
t
SA
t
PWE
t
SD
t
HD
t
HZWE
t
LZWE
ADDRESS
CE
WE
DATA IN
DATA OUT
DATA VALID
HIGH IMPEDANCE
PREVIOUS DATA
t
WC
ADDRESS
t
SA
t
SCE
t
HA
t
AW
t
PWE
t
SD
t
HD
CE
WE
DATA IN
DATA OUT
HIGH IMPEDANCE
DATA VALID
Notes
8. If WE is Low when CE goes Low, the outputs remain in the high impedance state.
9. CE or WE must be greater than VIH during address transitions.
Not recommended for new designs.
In production to support ongoing production programs only.
[+] Feedback
a} CYPRESS ”no." ‘HRECALL RESTORE ‘sTonE HLHZ RESET SW‘TCH
STK11C88
Document Number: 001-50591 Rev. *A Page 11 of 16
STORE INHIBIT or Power Up RECALL
Parameter Alt Description STK11C88 Unit
Min Max
tHRECALL [10] tRESTORE Power up RECALL Duration 550 μs
tSTORE [6] tHLHZ STORE Cycle Duration 10 ms
VRESET Low Voltage Reset Level 3.6 V
VSWITCH Low Voltage Trigger Level 4.0 4.5 V
Switching Waveforms
Figure 9. STORE INHIBIT/Power Up RECALL
V
CC
V
SWITCH
V
RESET
POWER-UP RECALL
DQ (DATA OUT)
STORE INHIBIT
5V
tHRECALL
POWER-UP
RECALL
BROWN OUT
STORE INHIBIT
NO RECALL
(VCC DID NOT GO
BELOW VRESET)
BROWN OUT
STORE INHIBIT
NO RECALL
(VCC DID NOT GO
BELOW VRESET)
BROWN OUT
STORE INHIBIT
RECALL WHEN
VCC RETURNS
ABOVE VSWITCH
Note
10. tHRECALL starts from the time VCC rises above VSWITCH.
Not recommended for new designs.
In production to support ongoing production programs only.
[+] Feedback
a} CYPRESS nun.»
STK11C88
Document Number: 001-50591 Rev. *A Page 12 of 16
Software Controlled STORE/RECALL Cycle
The software controlled STORE/RECALL cycle follows. [11, 12]
Parameter Alt Description 25 ns 45 ns Unit
Min Max Min Max
tRC tAVAV STORE/RECALL Initiation Cycle Time 25 45 ns
tSA[11] tAVEL Address Setup Time 0 0 ns
tCW[11] tELEH Clock Pulse Width 20 30 ns
tHACE[11] tELAX Address Hold Time 20 20 ns
tRECALL[11] RECALL Duration 20 20 μs
Switching Waveforms
Figure 10. CE Controlled Software STORE/RECALL Cycle [12]
Notes
11. The software sequence is clocked on the falling edge of CE without involving OE (double clocking abort the sequence).
12. The six consecutive addresses must be read in the order listed in the Mode Selection table. WE must be HIGH during all six consecutive cycles.
Not recommended for new designs.
In production to support ongoing production programs only.
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55H alcmmss P (0 to 70°C) 1 - \nduslria‘ (-4010 85°C) Package: N = Plastic 28-pin 300 m S = Plastic 28«pln 330 are 1n production to support a 25 - 45 e Dia x J C 51 435026 Qp 2B 51 -85026 2 51 -85058 51 -85058 51 -8502 51-85 -SF25|TR 51- -SF25| K11CBB-NF45TR K11CBB-NF45 STK11CaB-SF45TR STK11CBB-SF45 STK11CBB-NF45IT STK11088-N STK11C88- STK11
STK11C88
Document Number: 001-50591 Rev. *A Page 13 of 16
Ordering Information
These parts are not recommended for new designs. They are in production to support ongoing production programs only.
Speed
(ns) Ordering Code Package Diagram Package Type Operating
Range
25 STK11C88-NF25TR 51-85026 28-Pin SOIC (300 mil) Commercial
STK11C88-NF25 51-85026 28-Pin SOIC (300 mil)
STK11C88-SF25TR 51-85058 28-Pin SOIC (330 mil)
STK11C88-SF25 51-85058 28-Pin SOIC (330 mil)
STK11C88-NF25ITR 51-85026 28-Pin SOIC (300 mil) Industrial
STK11C88-NF25I 51-85026 28-Pin SOIC (300 mil)
STK11C88-SF25ITR 51-85058 28-Pin SOIC (330 mil)
STK11C88-SF25I 51-85058 28-Pin SOIC (330 mil)
45 STK11C88-NF45TR 51-85026 28-Pin SOIC (300 mil) Commercial
STK11C88-NF45 51-85026 28-Pin SOIC (300 mil)
STK11C88-SF45TR 51-85058 28-Pin SOIC (330 mil)
STK11C88-SF45 51-85058 28-Pin SOIC (330 mil)
STK11C88-NF45ITR 51-85026 28-Pin SOIC (300 mil) Industrial
STK11C88-NF45I 51-85026 28-Pin SOIC (300 mil)
STK11C88-SF45ITR 51-85058 28-Pin SOIC (330 mil)
STK11C88-SF45I 51-85058 28-Pin SOIC (330 mil)
All parts are Pb-free. The above table contains Final information. Contact your local Cypress sales representative for availability of these parts
Speed:
45 - 45 ns
Package:
N = Plastic 28-pin 300 mil SOIC
Part Numbering Nomenclature
STK11C88 - N F 25 I TR
Temperature Range:
Blank - Commercial (0 to 70°C)
Lead Finish
F = 100% Sn (Matte Tin)
I - Industrial (-40 to 85°C)
Packaging Option:
TR = Tape and Reel
Blank = Tube
S = Plastic 28-pin 330 mil SOIC
25 - 25 ns
Not recommended for new designs.
In production to support ongoing production programs only.
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a; CYPRESS rrnIo-M swam pmwmwz \\\ 00 55 mm} PER 5mg
STK11C88
Document Number: 001-50591 Rev. *A Page 14 of 16
Package Diagrams
Figure 11. 28-Pin (300 mil) SOIC (51-85026)
51 85127 *A
PIN 1 ID
0.291[7.39]
0.300[7.62]
0.394[10.01]
0.419[10.64]
0.050[1.27]
TYP.
0.092[2.33]
0.105[2.67]
0.004[0.10]
0.0118[0.30]
SEATING PLANE
0.0091[0.23]
0.0125[3.17]
0.015[0.38]
0.050[1.27]
0.013[0.33]
0.019[0.48]
0.026[0.66]
0.032[0.81]
0.697[17.70]
0.713[18.11]
0.004[0.10]
114
15 28
*
*
*
PART #
S28.3 STANDARD PKG.
SZ28.3 LEAD FREE PKG.
MIN.
MAX.
NOTE :
1. JEDEC STD REF MO-119
2. BODY LENGTH DIMENSION DOES NOT INCLUDE MOLD PROTRUSION/END FLASH,BUT
MOLD PROTRUSION/END FLASH SHALL NOT EXCEED 0.010 in (0.254 mm) PER SIDE
3. DIMENSIONS IN INCHES
4. PACKAGE WEIGHT 0.85gms
DOES INCLUDE MOLD MISMATCH AND ARE MEASURED AT THE MOLD PARTING LINE.
51-85026-*D
Not recommended for new designs.
In production to support ongoing production programs only.
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a; CYPRESS ”no-M PIN 1 1D DIMENSIDNS IN INDHESEMM] m : MAX. HHHHHHHHHHHHHH - PACKAGE VEIGHT 079ng O ‘ fl.460[1l.$E4] U.4ED[12.192] 0 PART N < 7:322:23;="" [mm="" §\="" 1="" szheqilead="" free="" p="" —="" 9="" hhhhhhhhhhhhhh="" (q="" (2)="" @q="" seating="" plane="" q="" “jzhuezbej="" “jesus-491]="" 0="" $="" $0="" 0"="" i="" 0394(2‘397]="" 1="" 0.11m?="" 794]="" uasnnam]="" f="" «hymuumassl="" ~="" typ‘="" unaumfinfll="" —="" ‘="" g="" k.="" uusuuem="" nonmassj="" \="" q="" ‘="" '="">
STK11C88
Document Number: 001-50591 Rev. *A Page 15 of 16
Figure 12. 28-Pin (330 mil) SOIC (51-85058)
Package Diagrams (continued)
51-85058-*A
Not recommended for new designs.
In production to support ongoing production programs only.
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a; CYPRESS rrnlonM 9 Information section: “The reduction to supp “NM recommended w ucl‘won progr omy." O. $0 '5 representafi‘Qand .com Q .cypresscurbel ‘ 0g psoccypresscor$b \ o e 0% mm maul: zone n W "a,” cane 15mm an s cnpyngm w; an
Document Number: 001-50591 Rev. *A Revised December 11, 2009 Page 16 of 16
All products and company names mentioned in this document may be the trademarks of their respective holders.
STK11C88
© Cypress Semiconductor Corporation, 2008-2009. The information contained herein is subject to change without notice. Cypress Semiconductor Corporation assumes no responsibility for the use of
any circuitry other than circuitry embodied in a Cypress product. Nor does it convey or imply any license under patent or other rights. Cypress products are not warranted nor intended to be used for
medical, life support, life saving, critical control or safety applications, unless pursuant to an express written agreement with Cypress. Furthermore, Cypress does not authorize its products for use as
critical components in life-support systems where a malfunction or failure may reasonably be expected to result in significant injury to the user. The inclusion of Cypress products in life-support systems
application implies that the manufacturer assumes all risk of such use and in doing so indemnifies Cypress against all charges.
Any Source Code (software and/or firmware) is owned by Cypress Semiconductor Corporation (Cypress) and is protected by and subject to worldwide patent protection (United States and foreign),
United States copyright laws and international treaty provisions. Cypress hereby grants to licensee a personal, non-exclusive, non-transferable license to copy, use, modify, create derivative works of,
and compile the Cypress Source Code and derivative works for the sole purpose of creating custom software and or firmware in support of licensee product to be used only in conjunction with a Cypress
integrated circuit as specified in the applicable agreement. Any reproduction, modification, translation, compilation, or representation of this Source Code except as specified above is prohibited without
the express written permission of Cypress.
Disclaimer: CYPRESS MAKES NO WARRANTY OF ANY KIND, EXPRESS OR IMPLIED, WITH REGARD TO THIS MATERIAL, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES
OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE. Cypress reserves the right to make changes without further notice to the materials described herein. Cypress does not
assume any liability arising out of the application or use of any product or circuit described herein. Cypress does not authorize its products for use as critical components in life-support systems where
a malfunction or failure may reasonably be expected to result in significant injury to the user. The inclusion of Cypress’ product in a life-support systems application implies that the manufacturer
assumes all risk of such use and in doing so indemnifies Cypress against all charges.
Use may be limited by and subject to the applicable Cypress software license agreement.
Document History Page
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Document Title: STK11C88 256 Kbit (32K x 8) SoftStore nvSRAM
Document Number: 001-50591
Rev. ECN No. Orig. of
Change Submission
Date Description of Change
** 2625096 GVCH/PYRS 12/19/08 New data sheet
*A 2826441 GVCH 12/11/2009 Added following text in the Ordering Information section: “These parts
are not recommended for new designs. In production to support ongo-
ing production programs only.”
Added watermark in PDF stating “Not recommended for new designs.
In production to support ongoing production programs only.”
Added Contents on page 2.
Not recommended for new designs.
In production to support ongoing production programs only.
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