Datenblatt für TLE2141,42,44-EP von Texas Instruments

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1
FEATURES
1
2
3
4
8
7
6
5
1OUT
1IN-
1IN+
VCC-
VCC+
2OUT
2IN-
2IN+
TLE2142
D PACKAGE
(TOP VIEW)
NC – No internal connection
1
2
3
4
5
6
7
8
16
15
14
13
12
11
10
9
1OUT
1IN-
1IN+
VCC+
2IN+
2IN-
2OUT
NC
4OUT
4IN-
4IN+
VCC-
3IN+
3IN-
3OUT
NC
TLE2144
DW PACKAGE
(TOP VIEW)
1
2
3
4
8
7
6
5
OFFSET N1
IN-
IN+
VCC-
NC
VCC+
OUT
OFFSET N2
TLE2141
D PACKAGE
(TOP VIEW)
DESCRIPTION
TLE2141-EP
TLE2142-EP
TLE2144-EP
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........................................................................................................................................................................................................ SLOS577 – MAY 2008
Excalibur™ LOW-NOISE HIGH-SPEED PRECISION OPERATIONAL AMPLIFIER
2
•Controlled Baseline •Low Noise
– One Assembly Site – 10 Hz...15 nV/ √Hz
– One Test Site – 1 kHz...10.5 nV/ √Hz
– One Fabrication Site •10 000-pF Load Capability•Extended Temperature Performance of •20-mA (Min) Short-Circuit Output Current– 55 °C to 125 °C
•27-V/ µs Slew Rate (Min)•Enhanced Diminishing Manufacturing Sources
•High Gain-Bandwidth Product...5.9 MHz(DMS) Support
•Low V
IO
...900 µV (Max) at 25 °C•Enhanced Product-Change Notification
•Single or Split Supply...4 V to 44 V•Qualification Pedigree
(1)
•Fast Settling Time(1)
Component qualification in accordance with JEDEC and
– 340 ns to 0.1%industry standards to ensure reliable operation over anextended temperature range. This includes, but is not limited
– 400 ns to 0.01%to, Highly Accelerated Stress Test (HAST) or biased 85/85,
•Saturation Recovery...150 nstemperature cycle, autoclave or unbiased HAST,electromigration, bond intermetallic life, and mold compound
•Large Output Swing...life. Such qualification testing should not be viewed as
V
CC –
+ 0.1 V to V
CC+
– 1 Vjustifying use of this component beyond specifiedperformance and environmental limits.
The TLE214x devices are high-performance, internally compensated operational amplifiers built using the TexasInstruments complementary bipolar Excalibur™ process. They are pin-compatible upgrades to standard industryproducts.
The design incorporates an input stage that simultaneously achieves low audio-band noise of 10.5 nV/ √Hz with a10-Hz 1/f corner and symmetrical 40-V/ µs slew rate typically with loads up to 800 pF. The resulting low distortionand high power bandwidth are important in high-fidelity audio applications. A fast settling time of 340 ns to 0.1%of a 10-V step with a 2-k Ω/100-pF load is useful in fast actuator/positioning drivers. Under similar test conditions,settling time to 0.01% is 400 ns.
1
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications ofTexas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.
2Excalibur is a trademark of Texas Instruments.
PRODUCTION DATA information is current as of publication date.
Copyright © 2008, Texas Instruments IncorporatedProducts conform to specifications per the terms of the TexasInstruments standard warranty. Production processing does notnecessarily include testing of all parameters.
l TEXAS INSTRUMENTS
+
-
OUT
IN+
IN-
OFFSET N1
OFFSET N2
TLE2141-EP
TLE2142-EP
TLE2144-EP
SLOS577 – MAY 2008 ........................................................................................................................................................................................................
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The devices are stable with capacitive loads up to 10 nF, although the 6-MHz bandwidth decreases to 1.8 MHzat this high loading level. As such, the TLE214x are useful for low-droop sample-and-holds and direct buffering oflong cables, including 4-mA to 20-mA current loops.
The special design also exhibits an improved insensitivity to inherent integrated circuit component mismatches asis evidenced by a 900- µV maximum offset voltage and 1.7- µV/ °C typical drift. Minimum common-mode rejectionratio and supply-voltage rejection ratio are 85 dB and 90 dB, respectively.
Device performance is relatively independent of supply voltage over the ± 2-V to ± 22-V range. Inputs can operatebetween V
CC –
– 0.3 V to V
CC+
– 1.8 V without inducing phase reversal, although excessive input current may flowout of each input exceeding the lower common-mode input range. The all-npn output stage provides a nearlyrail-to-rail output swing of V
CC –
– 0.1 V to V
CC+
– 1 V under light current-loading conditions. The device cansustain shorts to either supply since output current is internally limited, but care must be taken to ensure thatmaximum package power dissipation is not exceeded.
Both versions can also be used as comparators. Differential inputs of V
CC ±
can be maintained without damage tothe device. Open-loop propagation delay with TTL supply levels is typically 200 ns. This gives a good indicationas to output stage saturation recovery when the device is driven beyond the limits of recommended output swing.
The TLE214x devices are available in industry-standard 8-pin and 16-pin small-outline packages. The devicesare characterized for operation from – 55 °C to 125 °C.
ORDERING INFORMATION
(1)
T
A
PACKAGE
(2)
ORDERABLE PART NUMBER TOP-SIDE MARKING
Single SOIC – D (8 pin) Reel of 2500 TLE2141MDREP 2141EP
– 55 °C to 125 °C Dual SOIC – D (8 pin) Reel of 2500 TLE2142MDREP
(3)
TBD
Quad SOIC – DW (16 pin) Reel of 2000 TLE2144MDWREP
(3)
TBD
(1) For the most current package and ordering information, see the Package Option Addendum at the end of this document, or see the TIweb site at www.ti.com .(2) Package drawings, thermal data, and symbolization are available at www.ti.com/packaging .(3) Product Preview. Contact your TI sales representative for availability.
SYMBOL
A. OFFSET N1 and OFFSET N2 are available only on the TLE2141.
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Q12
Q10
R1
Q3
R2
IN -
IN +
Q1 Q4
Q2
Q7
R5
C1
Q17
R11
R10 C2
Q16
R9
R4 R7
D1
Q5 Q8 Q13
D2
Q6
R3
R6
Q11
Q14 Q15
R8
VCC +
VCC -
R12
Q18
Q19
Q20
Q21
D5
Q24
C4
C3
R13
D3
D4
Q22
R14 R18 R19
R21
Q26
Q30
Q34
R24
Q37
R23
Q36
OUT
R20
R22
Q35
Q32
Q33
Q29
D7
D6
Q25 Q28
Q31
D8
Q27
Q23
R16
R15 R17
Q9
OFFSET N1
OFFSET N2
COMPONENT TLE2141 TLE2142 TLE2144
Transistors 46 65 130
Resistors 24 43 86
Diodes 814 28
Capacitors 4816
Epi-FET 112
DEVICE COMPONENT COUNT
TLE2141-EP
TLE2142-EP
TLE2144-EP
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........................................................................................................................................................................................................ SLOS577 – MAY 2008
EQUIVALENT SCHEMATIC
A. OFFSET N1 and OFFSET N2 are available only on the TLE2141.
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ABSOLUTE MAXIMUM RATINGS
(1)
RECOMMENDED OPERATING CONDITIONS
TLE2141-EP
TLE2142-EP
TLE2144-EP
SLOS577 – MAY 2008 ........................................................................................................................................................................................................
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over operating free-air temperature range (unless otherwise noted)
V
CC+
Supply voltage
(2)
22 V
V
CC –
Supply voltage – 22 V
V
ID
Differential input voltage
(3)
± 44 V
V
I
Input voltage range (any input) V
CC+
V to (V
CC –
– 0.3) V
I
I
Input current (each input) ± 1 mA
I
O
Output current ± 80 mA
Total current into V
CC+
80 mA
Total current out of V
CC –
80 mA
Duration of short-circuit current at (or below) 25 °C
(4)
Unlimited
D package 97.1 °C/Wθ
JA
Package thermal impedance
(5) (6)
DW package 57.3 °C/W
T
A
Operating free-air temperature range – 55 °C to 125 °C
T
stg
Storage temperature range
(7)
– 65 °C to 150 °C
Lead temperature 1,6 mm (1/16 inch) from case for 10 seconds 260 °C
(1) Stresses beyond those listed under absolute maximum ratings may cause permanent damage to the device. These are stress ratingsonly, and functional operation of the device at these or any other conditions beyond those indicated under recommended operatingconditions is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.(2) All voltage values, except differential voltages, are with respect to the midpoint between V
CC+
and V
CC –
.(3) Differential voltages are at IN+ with respect to IN – . Excessive current flows, if input, are brought below V
CC –
– 0.3 V.(4) The output may be shorted to either supply. Temperature and/or supply voltages must be limited to ensure that the maximum dissipationrating is not exceeded.(5) Maximum power dissipation is a function of T
J
(max), θ
JA
, and T
A
. The maximum allowable power dissipation at any allowable ambienttemperature is P
D
= (T
J
(max) – T
A
)/ θ
JA
. Operating at the absolute maximum T
J
of 150 °C can affect reliability.(6) The package thermal impedance is calculated in accordance with JESD 51-7.(7) Long-term high temperature storage and/or extended use at maximum recommended operating conditions may result in a reduction ofoverall device life. See http://www.ti.com/ep_quality for additional information on enhanced product packaging.
MIN MAX UNIT
V
CC ±
Supply voltage ± 2 ± 22 V
V
CC
= 5 V 0 2.7V
IC
Common-mode input voltage VV
CC ±
= ± 15 V – 15 12.7
T
A
Operating free-air temperature – 55 125 °C
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TLE2141 ELECTRICAL CHARACTERISTICS
TLE2141-EP
TLE2142-EP
TLE2144-EP
www.ti.com
........................................................................................................................................................................................................ SLOS577 – MAY 2008
V
CC
= 5 V, at specified free-air temperature (unless otherwise noted)
TLE2141PARAMETER TEST CONDITIONS T
A
(1)
UNITMIN TYP MAX
25 °C 225 1400V
IO
Input offset voltage V
O
= 2.5 V, R
S
= 50 Ω, V
IC
= 2.5 V µVFull range 2100
Temperature coefficient ofα
VIO
V
O
= 2.5 V, R
S
= 50 Ω, V
IC
= 2.5 V Full range 1.7 µV/ °Cinput offset voltage
25 °C 8 100I
IO
Input offset current V
O
= 2.5 V, R
S
= 50 Ω, V
IC
= 2.5 V nAFull range 250
25 °C – 0.8 – 2I
IB
Input bias current V
O
= 2.5 V, R
S
= 50 Ω, V
IC
= 2.5 V µAFull range – 2.3
– 0.3 to25 °C 0 to 3
3.2Common-mode inputV
ICR
R
S
= 50 ΩVvoltage range
– 0.3 toFull range 0 to 2.7
2.9
I
OH
= – 150 µA 3.9 4.1
I
OH
= – 1.5 mA 25 °C 3.8 4
I
OH
= – 15 mA 3.2 3.7V
OH
High-level output voltage VI
OH
= – 100 µA 3.75
I
OH
= – 1 mA Full range 3.65
I
OH
= – 10 mA 3.25
I
OL
= 150 µA 75 125
mVI
OL
= 1.5 mA 25 °C 150 225
I
OL
= 15 mA 1.2 1.6 VV
OL
Low-level output voltage
I
OL
= 100 µA 200
mVI
OL
= 1 mA Full range 250
I
OL
= 10 mA 1.25 V
25 °C 50 220Large-signal differential V
IC
= 2.5 V, R
L
= 2 k Ω,A
VD
V/mVvoltage amplification V
O
= 1 V to – 1.5 V
Full range 5
r
i
Input resistance 25 °C 70 M Ω
c
i
Input capacitance 25 °C 2.5 pF
z
o
Open-loop output impedance f = 1 MHz 25 °C 30 Ω
25 °C 85 118CMRR Common-mode rejection ratio V
IC
= V
ICR
(min), R
S
= 50 ΩdBFull range 80
25 °C 90 106Supply-voltage rejection ratiok
SVR
V
CC ±
= ± 2.5 V to ± 15 V, R
S
= 50 ΩdB(ΔV
CC ±
/ΔV
IO
)
Full range 85
25 °C 3.4 4.4I
CC
Supply current V
O
= 2.5 V, No load, V
IC
= 2.5 V mAFull range 4.6
(1) Full range is – 55 °C to 125 °C.
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TLE2141 OPERATING CHARACTERISTICS
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TLE2142-EP
TLE2144-EP
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V
CC
= 5 V, T
A
= 25 °C (unless otherwise noted)
TLE2141PARAMETER TEST CONDITIONS UNITMIN TYP MAX
SR+ Positive slew rate A
VD
= – 1, R
L
= 2 k Ω
(1)
, C
L
= 500 pF 45 V/ µs
SR – Negative slew rate A
VD
= – 1, R
L
= 2 k Ω
(1)
, C
L
= 500 pF 42 V/ µs
To 0.1% 0.16t
s
Settling time A
VD
= – 1, 2.5-V step µsTo 0.01% 0.22
f = 10 Hz 15V
n
Equivalent input noise voltage R
S
= 20 ΩnV/ √Hzf = 1 kHz 10.5
f = 0.1 Hz to 1 Hz 0.48Peak-to-peak equivalent inputV
N(PP)
µVnoise voltage
f = 0.1 Hz to 10 Hz 0.51
f = 10 Hz 1.92I
n
Equivalent input noise current pA/ √Hzf = 1 kHz 0.5
V
O
= 1 V to 3 V, R
L
= 2 k Ω
(1)
, A
VD
= 2,THD+N Total harmonic distortion plus noise 0.0052 %f = 10 kHz
B
1
Unity-gain bandwidth R
L
= 2 k Ω
(1)
, C
L
= 100 pF
(1)
5.9 MHz
Gain-bandwidth product R
L
= 2 k Ω
(1)
, C
L
= 100 pF
(1)
, f = 100 kHz 5.8 MHz
B
OM
Maximum output-swing bandwidth V
O(PP)
= 2 V, R
L
= 2 k Ω
(1)
, A
VD
= 1 660 kHz
φ
m
Phase margin at unity gain R
L
= 2 k Ω
(1)
, C
L
= 100 pF
(1)
57 °
(1) R
L
and C
L
terminated to 2.5 V.
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TLE2141 ELECTRICAL CHARACTERISTICS
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TLE2142-EP
TLE2144-EP
www.ti.com
........................................................................................................................................................................................................ SLOS577 – MAY 2008
V
CC
= ± 15 V, at specified free-air temperature (unless otherwise noted)
TLE2141PARAMETER TEST CONDITIONS T
A
(1)
UNITMIN TYP MAX
25 °C 200 900V
IO
Input offset voltage V
IC
= 0, R
S
= 50 ΩµVFull range 1700
Temperature coefficient ofα
VIO
V
IC
= 0, R
S
= 50 ΩFull range 1.7 µV/ °Cinput offset voltage
25 °C 7 100I
IO
Input offset current V
IC
= 0, R
S
= 50 ΩnAFull range 250
25 °C – 0.7 – 1.5I
IB
Input bias current V
IC
= 0, R
S
= 50 ΩµAFull range – 1.8
– 15 to – 15.3 to25 °C
13 13.2Common-mode inputV
ICR
R
S
= 50 ΩVvoltage range
– 15 to – 15.3 toFull range
12.7 12.9
I
O
= – 150 µA 13.8 14.1
I
O
= – 1.5 mA 25 °C 13.7 14
I
O
= – 15 mA 13.1 13.7Maximum positive peakV
OM+
Voutput voltage swing
I
O
= – 100 µA 13.7
I
O
= – 1 mA Full range 13.6
I
O
= – 10 mA 13.1
I
O
= 150 µA – 14.7 – 14.9
I
O
= 1.5 mA 25 °C – 14.5 – 14.8
I
O
= 15 mA – 13.4 – 13.8Maximum negative peakV
OM –
Voutput voltage swing
I
O
= 100 µA – 14.6
I
O
= 1 mA Full range – 14.5
I
O
= 10 mA – 13.4
25 °C 100 450Large-signal differentialA
VD
V
O
= ± 10 V, R
L
= 2 k ΩV/mVvoltage amplification
Full range 20
r
i
Input resistance 25 °C 65 M Ω
c
i
Input capacitance 25 °C 2.5 pF
z
o
Open-loop output impedance f = 1 MHz 25 °C 30 Ω
25 °C 85 108CMRR Common-mode rejection ratio V
IC
= V
ICR
(min), R
S
= 50 ΩdBFull range 80
25 °C 90 106Supply-voltage rejection ratiok
SVR
V
CC ±
= ± 2.5 V to ± 15 V, R
S
= 50 ΩdB(ΔV
CC ±
/ΔV
IO
)
Full range 85
V
ID
= 1 V – 25 – 50I
OS
Short-circuit output current V
O
= 0 25 °C mAV
ID
= – 1 V 20 31
25 °C 3.5 4.5I
CC
Supply current V
O
= 0, No load, V
IC
= 2.5 V mAFull range 4.7
(1) Full range is – 55 °C to 125 °C.
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l TEXAS INSTRUMENTS
TLE2141 OPERATING CHARACTERISTICS
TLE2141-EP
TLE2142-EP
TLE2144-EP
SLOS577 – MAY 2008 ........................................................................................................................................................................................................
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V
CC
= ± 15 V, T
A
= 25 °C (unless otherwise noted)
TLE2141PARAMETER TEST CONDITIONS UNITMIN TYP MAX
SR+ Positive slew rate A
VD
= – 1, R
L
= 2 k Ω, C
L
= 100 pF 27 45 V/ µs
SR – Negative slew rate A
VD
= – 1, R
L
= 2 k Ω, C
L
= 100 pF 27 42 V/ µs
To 0.1% 0.34t
s
Settling time A
VD
= – 1, 10-V step µsTo 0.01% 0.4
f = 10 Hz 15V
n
Equivalent input noise voltage R
S
= 20 ΩnV/ √Hzf = 1 kHz 10.5
f = 0.1 Hz to 1 Hz 0.48Peak-to-peak equivalent inputV
N(PP)
µVnoise voltage
f = 0.1 Hz to 10 Hz 0.51
f = 10 Hz 1.89I
n
Equivalent input noise current pA/ √Hzf = 1 kHz 0.47
THD+N Total harmonic distortion plus noise V
O(PP)
= 20 V, R
L
= 2 k Ω, A
VD
= 10, f = 10 kHz 0.01 %
B
1
Unity-gain bandwidth R
L
= 2 k Ω, C
L
= 100 pF 6 MHz
Gain-bandwidth product R
L
= 2 k Ω, C
L
= 100 pF, f = 100 kHz 5.9 MHz
B
OM
Maximum output-swing bandwidth V
O(PP)
= 20 V, A
VD
= 1, R
L
= 2 k Ω, C
L
= 100 pF 668 kHz
φ
m
Phase margin at unity gain R
L
= 2 k Ω, C
L
= 100 pF 58 °
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TLE2142 ELECTRICAL CHARACTERISTICS
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TLE2142-EP
TLE2144-EP
www.ti.com
........................................................................................................................................................................................................ SLOS577 – MAY 2008
V
CC
= 5 V, at specified free-air temperature (unless otherwise noted)
TLE2142PARAMETER TEST CONDITIONS T
A
(1)
UNITMIN TYP MAX
25 °C 220 1900V
IO
Input offset voltage V
O
= 2.5 V, R
S
= 50 Ω, V
IC
= 2.5 V µVFull range 2600
Temperature coefficient ofα
VIO
V
O
= 2.5 V, R
S
= 50 Ω, V
IC
= 2.5 V Full range 1.7 µV/ °Cinput offset voltage
25 °C 8 100I
IO
Input offset current V
O
= 2.5 V, R
S
= 50 Ω, V
IC
= 2.5 V nAFull range 200
25 °C – 0.8 – 2I
IB
Input bias current V
O
= 2.5 V, R
S
= 50 Ω, V
IC
= 2.5 V µAFull range – 2.3
– 0.3 to25 °C 0 to 3
3.2Common-mode inputV
ICR
R
S
= 50 ΩVvoltage range
– 0.3 toFull range 0 to 2.7
2.9
I
OH
= – 150 µA 3.9 4.1
I
OH
= – 1.5 mA 25 °C 3.8 4
I
OH
= – 15 mA 3.4 3.7V
OH
High-level output voltage VI
OH
= – 100 µA 3.75
I
OH
= – 1 mA Full range 3.65
I
OH
= – 10 mA 3.45
I
OL
= 150 µA 75 125
mVI
OL
= 1.5 mA 25 °C 150 225
I
OL
= 15 mA 1.2 1.4 VV
OL
Low-level output voltage
I
OL
= 100 µA 200
mVI
OL
= 1 mA Full range 250
I
OL
= 10 mA 1.25 V
25 °C 50 220Large-signal differentialA
VD
V
IC
= 2.5 V, R
L
= 2 k Ω, V
O
= 1 V to 1.5 V V/mVvoltage amplification
Full range 5
r
i
Input resistance 25 °C 70 M Ω
c
i
Input capacitance 25 °C 2.5 pF
z
o
Open-loop output impedance f = 1 MHz 25 °C 30 Ω
25 °C 85 118CMRR Common-mode rejection ratio V
IC
= V
ICR
(min), R
S
= 50 ΩdBFull range 80
25 °C 90 106Supply-voltage rejection ratiok
SVR
V
CC ±
= ± 2.5 V to ± 15 V, R
S
= 50 ΩdB(ΔV
CC ±
/ΔV
IO
)
Full range 85
25 °C 6.6 8.8I
CC
Supply current V
O
= 2.5 V, No load, V
IC
= 2.5 V mAFull range 9.2
(1) Full range is – 55 °C to 125 °C.
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TLE2142 OPERATING CHARACTERISTICS
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TLE2142-EP
TLE2144-EP
SLOS577 – MAY 2008 ........................................................................................................................................................................................................
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V
CC
= 5 V, T
A
= 25 °C (unless otherwise noted)
TLE2142PARAMETER TEST CONDITIONS UNITMIN TYP MAX
SR+ Positive slew rate A
VD
= – 1, R
L
= 2 k Ω
(1)
, C
L
= 500 pF 45 V/ µs
SR – Negative slew rate A
VD
= – 1, R
L
= 2 k Ω
(1)
, C
L
= 500 pF 42 V/ µs
To 0.1% 0.16t
s
Settling time A
VD
= – 1, 2.5-V step µsTo 0.01% 0.22
f = 10 Hz 15V
n
Equivalent input noise voltage R
S
= 20 ΩnV/ √Hzf = 1 kHz 10.5
f = 0.1 Hz to 1 Hz 0.48Peak-to-peak equivalent inputV
N(PP)
µVnoise voltage
f = 0.1 Hz to 10 Hz 0.51
f = 10 Hz 1.92I
n
Equivalent input noise current pA/ √Hzf = 1 kHz 0.5
V
O
= 1 V to 3 V, R
L
= 2 k Ω
(1)
, A
VD
= 2,THD+N Total harmonic distortion plus noise 0.0052 %f = 10 kHz
B
1
Unity-gain bandwidth R
L
= 2 k Ω
(1)
, C
L
= 100 pF 5.9 MHz
Gain-bandwidth product R
L
= 2 k Ω
(1)
, C
L
= 100 pF, f = 100 kHz 5.8 MHz
B
OM
Maximum output-swing bandwidth V
O(PP)
= 2 V, R
L
= 2 k Ω
(1)
, A
VD
= 1, C
L
= 100 pF 660 kHz
φ
m
Phase margin at unity gain R
L
= 2 k Ω
(1)
, C
L
= 100 pF 57 °
(1) R
L
terminated at 2.5 V.
10 Submit Documentation Feedback Copyright © 2008, Texas Instruments Incorporated
Product Folder Link(s): TLE2141-EP TLE2142-EP TLE2144-EP
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TLE2142 ELECTRICAL CHARACTERISTICS
TLE2141-EP
TLE2142-EP
TLE2144-EP
www.ti.com
........................................................................................................................................................................................................ SLOS577 – MAY 2008
V
CC
= ± 15 V, at specified free-air temperature (unless otherwise noted)
TLE2142PARAMETER TEST CONDITIONS T
A
(1)
UNITMIN TYP MAX
25 °C 290 1200V
IO
Input offset voltage V
IC
= 0, R
S
= 50 ΩµVFull range 2000
Temperature coefficient ofα
VIO
V
IC
= 0, R
S
= 50 ΩFull range 1.7 µV/ °Cinput offset voltage
25 °C 7 100I
IO
Input offset current V
IC
= 0, R
S
= 50 ΩnAFull range 250
25 °C – 0.7 – 1.5I
IB
Input bias current V
IC
= 0, R
S
= 50 ΩµAFull range – 1.8
– 15 to – 15.3 to25 °C
13 13.2Common-mode inputV
ICR
R
S
= 50 ΩVvoltage range
– 15 to – 15.3 toFull range
12.7 12.9
I
O
= – 150 µA 13.8 14.1
I
O
= – 1.5 mA 25 °C 13.7 14
I
O
= – 15 mA 13.3 13.7Maximum positive peakV
OM+
Voutput voltage swing
I
O
= – 100 µA 13.7
I
O
= – 1 mA Full range 13.6
I
O
= – 10 mA 13.3
I
O
= 150 µA – 14.7 – 14.9
I
O
= 1.5 mA 25 °C – 14.5 – 14.8
I
O
= 15 mA – 13.4 – 13.8Maximum negative peakV
OM –
Voutput voltage swing
I
O
= 100 µA – 14.6
I
O
= 1 mA Full range – 14.5
I
O
= 10 mA – 13.4
25 °C 100 450Large-signal differentialA
VD
V
O
= ± 10 V, R
L
= 2 k ΩV/mVvoltage amplification
Full range 20
r
i
Input resistance 25 °C 65 M Ω
c
i
Input capacitance 25 °C 2.5 pF
z
o
Open-loop output impedance f = 1 MHz 25 °C 30 Ω
25 °C 85 108CMRR Common-mode rejection ratio V
IC
= V
ICR
(min), R
S
= 50 ΩdBFull range 80
25 °C 90 106Supply-voltage rejection ratiok
SVR
V
CC ±
= ± 2.5 V to ± 15 V, R
S
= 50 ΩdB(ΔV
CC ±
/ΔV
IO
)
Full range 85
V
ID
= 1 V – 25 – 50I
OS
Short-circuit output current V
O
= 0 25 °C mAV
ID
= – 1 V 20 31
25 °C 6.9 9I
CC
Supply current V
O
= 0, No load, V
IC
= 2.5 V mAFull range 9.4
(1) Full range is – 55 °C to 125 °C.
Copyright © 2008, Texas Instruments Incorporated Submit Documentation Feedback 11
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l TEXAS INSTRUMENTS
TLE2142 OPERATING CHARACTERISTICS
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TLE2142-EP
TLE2144-EP
SLOS577 – MAY 2008 ........................................................................................................................................................................................................
www.ti.com
V
CC
= ± 15 V, T
A
= 25 °C (unless otherwise noted)
TLE2142PARAMETER TEST CONDITIONS UNITMIN TYP MAX
SR+ Positive slew rate A
VD
= – 1, R
L
= 2 k Ω, C
L
= 100 pF 27 45 V/ µs
SR – Negative slew rate A
VD
= – 1, R
L
= 2 k Ω, C
L
= 100 pF 27 42 V/ µs
To 0.1% 0.34t
s
Settling time A
VD
= – 1, 10-V step µsTo 0.01% 0.4
f = 10 Hz 15V
n
Equivalent input noise voltage R
S
= 20 ΩnV/ √Hzf = 1 kHz 10.5
f = 0.1 Hz to 1 Hz 0.48Peak-to-peak equivalent inputV
n(PP)
µVnoise voltage
f = 0.1 Hz to 10 Hz 0.51
f = 10 Hz 1.89I
n
Equivalent input noise current pA/ √Hzf = 1 kHz 0.47
THD+N Total harmonic distortion plus noise V
O(PP)
= 20 V, R
L
= 2 k Ω, A
VD
= 10, f = 10 kHz 0.01 %
B
1
Unity-gain bandwidth R
L
= 2 k Ω, C
L
= 100 pF 6 MHz
Gain-bandwidth product R
L
= 2 k Ω, C
L
= 100 pF, f = 100 kHz 5.9 MHz
V
O(PP)
= 20 V, A
VD
= 1, R
L
= 2 k Ω, A
VD
= 1,B
OM
Maximum output-swing bandwidth 668 kHzC
L
= 100 pF
φ
m
Phase margin at unity gain R
L
= 2 k Ω, C
L
= 100 pF 58 °
12 Submit Documentation Feedback Copyright © 2008, Texas Instruments Incorporated
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TLE2142-EP
TLE2144-EP
www.ti.com
........................................................................................................................................................................................................ SLOS577 – MAY 2008
V
CC
= 5 V, at specified free-air temperature (unless otherwise noted)
TLE2144PARAMETER TEST CONDITIONS T
A
(1)
UNITMIN TYP MAX
25 °C 0.5 3.8V
IO
Input offset voltage V
O
= 2.5 V, R
S
= 50 Ω, V
IC
= 2.5 V mVFull range 5.2
Temperature coefficient ofα
VIO
V
O
= 2.5 V, R
S
= 50 Ω, V
IC
= 2.5 V Full range 1.7 µV/ °Cinput offset voltage
25 °C 8 100I
IO
Input offset current V
O
= 2.5 V, R
S
= 50 Ω, V
IC
= 2.5 V nAFull range 250
25 °C – 0.8 – 2I
IB
Input bias current V
O
= 2.5 V, R
S
= 50 Ω, V
IC
= 2.5 V µAFull range – 2.3
– 0.3 to25 °C 0 to 3
3.2Common-mode inputV
ICR
R
S
= 50 ΩVvoltage range
– 0.3 toFull range 0 to 2.7
2.9
I
OH
= – 150 µA 3.9 4.1
I
OH
= – 1.5 mA 25 °C 3.8 4
I
OH
= – 15 mA 3.4 3.7V
OH
High-level output voltage VI
OH
= – 100 µA 3.75
I
OH
= – 1 mA Full range 3.65
I
OH
= – 10 mA 3.45
I
OL
= 150 µA 75 125
mVI
OL
= 1.5 mA 25 °C 150 225
I
OL
= 15 mA 1.2 1.6 VV
OL
Low-level output voltage
I
OL
= 100 µA 200
mVI
OL
= 1 mA Full range 250
I
OL
= 10 mA 1.45 V
25 °C 50 95Large-signal differential V
IC
= 2.5 V, R
L
= 2 k Ω,A
VD
V/mVvoltage amplification V
O
= 1 V to – 1.5 V
Full range 5
r
i
Input resistance 25 °C 70 M Ω
c
i
Input capacitance 25 °C 2.5 pF
z
o
Open-loop output impedance f = 1 MHz 25 °C 3. Ω
25 °C 85 118CMRR Common-mode rejection ratio V
IC
= V
ICR
(min), R
S
= 50 ΩdBFull range 80
25 °C 90 106Supply-voltage rejection ratiok
SVR
V
CC ±
= ± 2.5 V to ± 15 V, R
S
= 50 ΩdB(ΔV
CC ±
/ΔV
IO
)
Full range 85
25 °C 13.2 17.6I
CC
Supply current V
O
= 2.5 V, No load, V
IC
= 2.5 V mAFull range 18.4
(1) Full range is – 55 °C to 125 °C.
Copyright © 2008, Texas Instruments Incorporated Submit Documentation Feedback 13
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l TEXAS INSTRUMENTS
TLE2144 OPERATING CHARACTERISTICS
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TLE2142-EP
TLE2144-EP
SLOS577 – MAY 2008 ........................................................................................................................................................................................................
www.ti.com
V
CC
= 5 V, T
A
= 25 °C (unless otherwise noted)
TLE2144PARAMETER TEST CONDITIONS UNITMIN TYP MAX
SR+ Positive slew rate A
VD
= – 1, R
L
= 2 k Ω
(1)
, C
L
= 500 pF 45 V/ µs
SR – Negative slew rate A
VD
= – 1, R
L
= 2 k Ω
(1)
, C
L
= 500 pF 42 V/ µs
To 0.1% 0.16t
s
Settling time A
VD
= – 1, 2.5-V step µsTo 0.01% 0.22
f = 10 Hz 15V
n
Equivalent input noise voltage R
S
= 20 ΩnV/ √Hzf = 1 kHz 10.5
f = 0.1 Hz to 1 Hz 0.48Peak-to-peak equivalent inputV
N(PP)
µVnoise voltage
f = 0.1 Hz to 10 Hz 0.51
f = 10 Hz 1.92I
n
Equivalent input noise current pA/ √Hzf = 1 kHz 0.5
V
O
= 1 V to 3 V, R
L
= 2 k Ω
(1)
, A
VD
= 2,THD+N Total harmonic distortion plus noise 0.0052 %f = 10 kHz
B
1
Unity-gain bandwidth R
L
= 2 k Ω
(1)
, C
L
= 100 pF 5.9 MHz
Gain-bandwidth product R
L
= 2 k Ω
(1)
, C
L
= 100 pF, f = 100 kHz 5.8 MHz
B
OM
Maximum output-swing bandwidth V
O(PP)
= 2 V, R
L
= 2 k Ω
(1)
, A
VD
= 1 660 kHz
φ
m
Phase margin at unity gain R
L
= 2 k Ω
(1)
, C
L
= 100 pF 57 °
(1) R
L
terminated at 2.5 V.
14 Submit Documentation Feedback Copyright © 2008, Texas Instruments Incorporated
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TLE2142-EP
TLE2144-EP
www.ti.com
........................................................................................................................................................................................................ SLOS577 – MAY 2008
V
CC
= ± 15 V, at specified free-air temperature (unless otherwise noted)
TLE2144PARAMETER TEST CONDITIONS T
A
(1)
UNITMIN TYP MAX
25 °C 0.6 2.4V
IO
Input offset voltage V
IC
= 0, R
S
= 50 ΩmVFull range 4
Temperature coefficient ofα
VIO
V
IC
= 0, R
S
= 50 Ω25 °C 1.7 µV/ °Cinput offset voltage
25 °C 7 100I
IO
Input offset current V
IC
= 0, R
S
= 50 ΩnAFull range 250
25 °C – 0.7 – 1.5I
IB
Input bias current V
IC
= 0, R
S
= 50 ΩµAFull range – 1.8
– 15 to – 15.3 to25 °C
13 13.2Common-mode inputV
ICR
R
S
= 50 ΩVvoltage range
– 15 to – 15.3 toFull range
12.7 12.9
I
O
= – 150 µA 13.8 14.1
I
O
= – 1.5 mA 25 °C 13.7 14
I
O
= – 15 mA 13.1 13.7Maximum positive peakV
OM+
Voutput voltage swing
I
O
= – 100 µA 13.7
I
O
= – 1 mA Full range 13.6
I
O
= – 10 mA 13.1
I
O
= 150 µA – 14.7 – 14.9
I
O
= 1.5 mA 25 °C – 14.5 – 14.8
I
O
= 15 mA – 13.4 – 13.8Maximum negative peakV
OM –
Voutput voltage swing
I
O
= 100 µA – 14.6
I
O
= 1 mA Full range – 14.5
I
O
= 10 mA – 13.4
25 °C 100 170Large-signal differentialA
VD
V
O
= ± 10 V, R
L
= 2 k ΩV/mVvoltage amplification
Full range 20
r
i
Input resistance 25 °C 65 M Ω
c
i
Input capacitance 25 °C 2.5 pF
z
o
Open-loop output impedance f = 1 MHz 25 °C 30 Ω
25 °C 85 108CMRR Common-mode rejection ratio V
IC
= V
ICR
(min), R
S
= 50 ΩdBFull range 80
25 °C 90 106Supply-voltage rejection ratiok
SVR
V
CC ±
= ± 2.5 V to ± 15 V, R
S
= 50 ΩdB(ΔV
CC ±
/ΔV
IO
)
Full range 85
V
ID
= 1 V – 25 – 50I
OS
Short-circuit output current V
O
= 0 25 °C mAV
ID
= – 1 V 20 31
25 °C 13.8 18I
CC
Supply current V
O
= 0, No load, V
IC
= 2.5 V mAFull range 18.8
(1) Full range is – 55 °C to 125 °C.
Copyright © 2008, Texas Instruments Incorporated Submit Documentation Feedback 15
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l TEXAS INSTRUMENTS
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TLE2142-EP
TLE2144-EP
SLOS577 – MAY 2008 ........................................................................................................................................................................................................
www.ti.com
V
CC
= ± 15 V, T
A
= 25 °C (unless otherwise noted)
TLE2144PARAMETER TEST CONDITIONS UNITMIN TYP MAX
SR+ Positive slew rate A
VD
= – 1, R
L
= 2 k Ω, C
L
= 100 pF 27 45 V/ µs
SR – Negative slew rate A
VD
= – 1, R
L
= 2 k Ω, C
L
= 100 pF 27 42 V/ µs
To 0.1% 0.34t
s
Settling time A
VD
= – 1, 10-V step µsTo 0.01% 0.4
f = 10 Hz 15V
n
Equivalent input noise voltage R
S
= 20 ΩnV/ √Hzf = 1 kHz 10.5
f = 0.1 Hz to 1 Hz 0.48Peak-to-peak equivalent inputV
n(PP)
µVnoise voltage
f = 0.1 Hz to 10 Hz 0.51
f = 10 Hz 1.89I
n
Equivalent input noise current pA/ √Hzf = 10 kHz 0.47
THD+N Total harmonic distortion plus noise V
O(PP)
= 20 V, R
L
= 2 k Ω, A
VD
= 10, f = 10 kHz 0.01 %
B
1
Unity-gain bandwidth R
L
= 2 k Ω, C
L
= 100 pF 6 MHz
Gain-bandwidth product R
L
= 2 k Ω, C
L
= 100 pF, f = 100 kHz 5.9 MHz
B
OM
Maximum output-swing bandwidth V
O(PP)
= 20 V, A
VD
= 1, R
L
= 2 k Ω, C
L
= 100 pF 668 kHz
φ
m
Phase margin at unity gain R
L
= 2 k Ω, C
L
= 100 pF 58 °
16 Submit Documentation Feedback Copyright © 2008, Texas Instruments Incorporated
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TYPICAL CHARACTERISTICS
TLE2141-EP
TLE2142-EP
TLE2144-EP
www.ti.com
........................................................................................................................................................................................................ SLOS577 – MAY 2008
Table of Graphs
Figure 1 ,V
IO
Input offset voltage Distribution Figure 2 ,Figure 3
I
IO
Input offset current vs Free-air temperature Figure 4
vs Common-mode input voltage Figure 5I
IB
Input bias current
vs Free-air temperature Figure 6
vs Supply voltage Figure 7
vs Free-air temperature Figure 8V
OM+
Maximum positive peak output voltage
vs Output current Figure 9
vs Settling time Figure 11
vs Supply voltage Figure 7
vs Free-air temperature Figure 8V
OM –
Maximum negative peak output voltage
vs Output current Figure 10
vs Settling time Figure 11
V
O(PP)
Maximum peak-to-peak output voltage vs Frequency Figure 12
V
OH
High-level output voltage vs Output current Figure 13
V
OL
Low-level output voltage vs Output current Figure 14
Phase shift vs Frequency Figure 15
vs Frequency Figure 15A
VD
Large-signal differential voltage amplification
vs Free-air temperature Figure 16
z
o
Closed-loop output impedance vs Frequency Figure 17
I
OS
Short-circuit output current vs Free-air temperature Figure 18
vs Frequency Figure 19CMRR Common-mode rejection ratio
vs Free-air temperature Figure 20
vs Frequency Figure 21k
SVR
Supply-voltage rejection ratio
vs Free-air temperature Figure 22
vs Supply voltage Figure 23I
CC
Supply current
vs Free-air temperature Figure 24
V
n
Equivalent input noise voltage vs Frequency Figure 25
V
n
Input noise voltage Over a 10-second period Figure 26
I
n
Noise current vs Frequency Figure 27
THD+N Total harmonic distortion plus noise vs Frequency Figure 28
vs Free-air temperature Figure 29SR Slew rate
vs Load capacitance Figure 30
Noninverting large signal vs Time Figure 31
Pulse response Inverting large signal vs Time Figure 32
Small signal vs Time Figure 33
B
1
Unity-gain bandwidth vs Load capacitance Figure 34
Gain margin vs Load capacitance Figure 35
φ
m
Phase margin vs Load capacitance Figure 36
Copyright © 2008, Texas Instruments Incorporated Submit Documentation Feedback 17
Product Folder Link(s): TLE2141-EP TLE2142-EP TLE2144-EP
l TEXAS INSTRUMENTS \ x x x x x x w x x 236 Unils Tesle 236 Unils Tesla H
−400
12
8
4
00
Percentage of Units − %
16
20
24
400 800
TLE2141
DISTRIBUTION OF
INPUT OFFSET VOLTAGE
VIO − Input Offset Voltage − µV
236 Units Tested From 1 Wafer Lot
VCC± = ±15 V
TA = 25°C
P Package
−800
−400
12
8
4
00
Percentage of Units − %
16
20
24
400 800
TLE2142
DISTRIBUTION OF
INPUT OFFSET VOLTAGE
VIO − Input Offset Voltage − µV
236 Units Tested From 1 Wafer Lot
VCC± = ±15 V
TA = 25°C
P Package
−800 −200 200 600
−600
12
8
4
0−1.6 0
Percentage of Units − %
16
20
24
0.8 1.6
TLE2144
DISTRIBUTION OF
INPUT OFFSET VOLTAGE
VIO − Input Offset Voltage − mV
VCC± = ±15 V
TA = 25°C
N Package
250 Units Tested From 1 Wafer Lot
−0.8
− 2 −1.2 −0.4 0.4 1.2 2
10
8
4
2
0
18
6
IIO − Input Offset Current − nA
14
12
16
20
IIO
INPUT OFFSET CURRENT
vs
FREE-AIR TEMPERATURE
−75 −50 −25 0 25 50 75 100 125
TA − Free-Air Temperature − °C150
VCC± = ±15 V
VCC± = ±2.5 V
VO = 0
VIC = 0
TLE2141-EP
TLE2142-EP
TLE2144-EP
SLOS577 – MAY 2008 ........................................................................................................................................................................................................
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Figure 1. Figure 2.
Figure 3. Figure 4.
18 Submit Documentation Feedback Copyright © 2008, Texas Instruments Incorporated
Product Folder Link(s): TLE2141-EP TLE2142-EP TLE2144-EP
l TEXAS INSTRUMENTS / .= / E vcc :: as v Q / 5 m TA : I25°C / / fi fine / E // “ ’ /, . / / / TA = -55“c / 1 / / // \ \ \ \ Vcc :
−2−2.5
−0.2
−1
−1.2
−1.4 −1.5 −1
IIB − Input Bias Current − uA
0
0 0.5 1
INPUT BIAS CURRENT
vs
COMMON-MODE INPUT VOLTAGE
µAIIB
VIC − Common-Mode Input Voltage − V
VCC± = ±2.5 V
TA = 25°C
TA = 125°C
TA = −55°C
−0.4
−0.6
−0.8
−3 −0.5
IIB − Input Bias Current − nA
−1000
IIB
INPUT BIAS CURRENT
vs
FREE-AIR TEMPERATURE
TA − Free-Air Temperature − °C
−75 −50 −25 0 25 50 75 100 125 150
VO = 0
VIC = 0
VCC± = ±15 V
−900
−800
−700
−600
−500
VCC± = ±2.5 V
0
−12
−18
− 24 0 3 6 9 12 15
− Maximum Peak Output Voltage − V
12
18
24
18 21 24
6
− 6
VOM
VCC± − Supply Voltage − V
MAXIMUM PEAK OUTPUT VOLTAGE
vs
SUPPLY VOLTAGE
RL = 2 kΩ
TA = 25°C
VOM+
VOM−
TLE2141-EP
TLE2142-EP
TLE2144-EP
www.ti.com
........................................................................................................................................................................................................ SLOS577 – MAY 2008
Figure 5. Figure 6.
Figure 7. Figure 8.
Copyright © 2008, Texas Instruments Incorporated Submit Documentation Feedback 19
Product Folder Link(s): TLE2141-EP TLE2142-EP TLE2144-EP
l TEXAS INSTRUMENTS / \ \\ \ \ \\ 0.1% 0.01% .1% TA = -55“c \
−4−0.4 −1
13.8
13.6
− Maximum Positive Peak Output Voltage − V
MAXIMUM POSITIVE PEAK
OUTPUT VOLTAGE
vs
OUTPUT CURRENT
14
−10 −100− 40
14.4
14.2
14.6
IO − Output Current − mA
VOM +
VCC± = ±15 V
TA = 125°C
TA = 25°C
−0.1
TA = −55°C
−14.8
− 15
0.1 10.4
MAXIMUM NEGATIVE PEAK
OUTPUT VOLTAGE
vs
OUTPUT CURRENT
−14.6
104 10040
−14.2
−14.4
−14
IO − Output Current − mA
−13.6
−13.8
−13.4
VCC± = ±15 V
TA = 125°C
TA = −55°C
TA = 25°C
− Maximum Negative Peak Output Voltage − VVOM −
VOM − Maximum Peak Output Voltage − V
0
−7.5
−10
−12.5
10
0 100 200 300 400 500
5
2.5
7.5
12.5
ts − Settling Time − ns
VOM
MAXIMUM PEAK OUTPUT VOLTAGE
vs
SETTLING TIME
AVD = −1
VCC± = ±15 V
TA = 25°C
Rising
Falling
0.1%
0.01%
0.01%
0.1%
−2.5
−5
− Maximum Peak-to-Peak Output Voltage − V
MAXIMUM PEAK-TO-PEAK
OUTPUT VOLTAGE
vs
FREQUENCY
5
0
25
100 k 400 k 1 M
f − Frequency − Hz
20
15
10
30
4 M 10 M
VCC± = ±15 V
RL = 2 kΩ
TA = 125°C
TA = −55°C
TA = 25°C
VO(PP)
TLE2141-EP
TLE2142-EP
TLE2144-EP
SLOS577 – MAY 2008 ........................................................................................................................................................................................................
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Figure 9. Figure 10.
Figure 11. Figure 12.
20 Submit Documentation Feedback Copyright © 2008, Texas Instruments Incorporated
Product Folder Link(s): TLE2141-EP TLE2142-EP TLE2144-EP
l TEXAS INSTRUMENTS \\- Phase shin Phase shin /I
200
0
1000
0.1 1 10
VOL − Low-Level Output Voltage − mV
800
600
400
LOW-LEVEL OUTPUT VOLTAGE
vs
OUTPUT CURRENT
VOL
IO − Output Current − mA
100
1400
1200
TA = −55°C
TA = 125°C
VCC = 5 V
TA = 25°C
10
20
1 10 100 1 M
30
40
50
LARGE-SIGNAL DIFFERENTIAL VOLTAGE
AMPLIFICATION AND PHASE SHIFT
vs
FREQUENCY
f − Frequency − Hz
10 M
− 10
0
Phase Shift
80
90
100
110
120
60
70
0°
20°
40°
60°
80°
100°
120°
140°
160°
180°
200°
220°
240°
260°
1 k 10 k 100 k
VCC± = ±15 V
RL = 2 kΩ
CL = 100 pF
TA = 25°C
AVD
Phase Shift
AVD − Large-Signal Differential
Voltage Amplification − dB
AVD
−75 −50 −25 0 25 50 75 100 125 150
LARGE-SIGNAL DIFFERENTIAL
VOLTAGE AMPLIFICATION
vs
FREE-AIR TEMPERATURE
80
100
120
140
TA − Free-Air Temperature − °C
RL = 2 kΩ
RL = 10 kΩ
VCC± = ±15 V
VO = ±10 V
AVD − Large-Signal Differential
Voltage Amplification − dB
AVD
TLE2141-EP
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........................................................................................................................................................................................................ SLOS577 – MAY 2008
Figure 13. Figure 14.
Figure 15. Figure 16.
Copyright © 2008, Texas Instruments Incorporated Submit Documentation Feedback 21
Product Folder Link(s): TLE2141-EP TLE2142-EP TLE2144-EP
{L} TEXAS INSTRUMENTS ,.__\ /\\\ Vc w A /\/ c ‘ 3:83.... 55.6 mafiimso ‘
1
0.1
0.01
0.0011 k 10 k 100 k 1 M
− Closed-Loop Output Impedance −
10
f − Frequency − Hz
100
10 M
CLOSED-LOOP OUTPUT IMPEDANCE
vs
FREQUENCY
Ωzo
AVD = 100
AVD = 1
30 Ω
AVD = 10
− Short-Circuit Output Current − mA
−75 −50 −25 0 25 50 75 100 125 150
20
30
40
TA − Free-Air Temperature − °C
SHORT-CIRCUIT OUTPUT CURRENT
vs
FREE-AIR TEMPERATURE
50
60
OS
I
VCC± = ±15 V
VO = 0
VID = 1
VID = −1
f − Frequency − Hz
COMMON-MODE REJECTION RATIO
vs
FREQUENCY
60
40
20
0
100 1 k 10 k
CMRR − Common-Mode Rejection Ratio − dB
80
100
120
100 k 1 M
140 VCC± = ±15 V
TA = 25°C
−75 −50 −25 0 25 50 75 100 125 150
100
104
108
112
TA − Free-Air Temperature − °C
COMMON-MODE REJECTION RATIO
vs
FREE-AIR TEMPERATURE
116
120
CMRR − Common-Mode Rejection Ratio − dB
VCC = 5 V
VIC = VICRmin
VCC± = ±15 V
TLE2141-EP
TLE2142-EP
TLE2144-EP
SLOS577 – MAY 2008 ........................................................................................................................................................................................................
www.ti.com
Figure 17. Figure 18.
Figure 19. Figure 20.
22 Submit Documentation Feedback Copyright © 2008, Texas Instruments Incorporated
Product Folder Link(s): TLE2141-EP TLE2142-EP TLE2144-EP
l TEXAS INSTRUMENTS 15V \\ w
100
80
20
010 100 1 k
kSVR − Supply-Voltage Rejection Ratio − dB
120
140
f − Frequency − Hz
160
10 k 100 k 1 M 10 M
SUPPLY-VOLTAGE REJECTION RATIO
vs
FREQUENCY
kSVR
kSVR−
VCC± = ±2.5 V to ±15 V
TA = 25°C
60
40
kSVR+
SUPPLY-VOLTAGE REJECTION RATIO
vs
FREE-AIR TEMPERATURE
TA − Free-Air Temperature − °C
106
104
102
100
108
110
−75 −50 −25 0 25 50 75 100 125 150
VCC± = ±2.5 V to ±15 V
kSVR − Supply-Voltage Rejection Ratio − dB
kSVR
SUPPLY CURRENT
vs
SUPPLY VOLTAGE
IDD − Supply Current − mA
CC
I
2.5
20 4 8 12 16 20
3
3.5
24
|VCC±| − Supply Voltage − V
4
TA = 125°C
TA = −55°C
TA = 25°C
VO = 0
No Load
2.8
3
3.2
3.4
3.6
3.8
IDD − Supply Current − mA
CC
I
SUPPLY CURRENT
vs
FREE-AIR TEMPERATURE
−75 −50 −25 0 25 50 75 100 125 150
TA − Free-Air Temperature − °C
VO = 0
No Load
VCC± = ±15 V
VCC± = ±2.5 V
TLE2141-EP
TLE2142-EP
TLE2144-EP
www.ti.com
........................................................................................................................................................................................................ SLOS577 – MAY 2008
Figure 21. Figure 22.
Figure 23. Figure 24.
Copyright © 2008, Texas Instruments Incorporated Submit Documentation Feedback 23
Product Folder Link(s): TLE2141-EP TLE2142-EP TLE2144-EP
J \\ I )
2 4 6
0
250
8 10
t − Time − s
INPUT NOISE VOLTAGE
OVER A 10-SECOND PERIOD
500
750 VCC± = ±15 V
f = 0.1 to 10 Hz
TA = 25°C
Input Noise Voltage − nV
−250
−500
−7500
250
Vn − Equivalent Input Noise Voltage −
100
50
01 100 1 k
150
f − Frequency − Hz
200
10 k
EQUIVALENT INPUT NOISE VOLTAGE
vs
FREQUENCY
TA = 125°C
TA = −55°C
TA = 25°C
VCC± = ±15 V
RS = 20Ω
10
nV/ Hz
4
2
0
6
8
10 100 1 k 10 k
− Noise Current − pA/
In
f − Frequency − Hz
NOISE CURRENT
vs
FREQUENCY
Hz
TA = −55°C
TA = 25°C
TA = 125°C
1
0.001%10 1 k 10 k 100 k
THD + N − Total Harmonic Distortion + Noise − %
TOTAL HARMONIC DISTORTION
PLUS NOISE
vs
FREQUENCY
0.01%
0.1%
1%
100
f − Frequency − Hz
VO(PP) = 20 V
VCC± = ±15 V
TA = 25°CAV = 100
RL = 600 Ω
AV = 100
RL = 2 kΩ
AV = 10
RL = 2 kΩ
AV = 10
RL = 600 Ω
TLE2141-EP
TLE2142-EP
TLE2144-EP
SLOS577 – MAY 2008 ........................................................................................................................................................................................................
www.ti.com
Figure 25. Figure 26.
Figure 27. Figure 28.
24 Submit Documentation Feedback Copyright © 2008, Texas Instruments Incorporated
Product Folder Link(s): TLE2141-EP TLE2142-EP TLE2144-EP
l TEXAS INSTRUMENTS \ )) CL Vccz= :15 v AVD=1 RL:2kQ
µs
SR − Slew Rate − V/
0
10
20
30
CL − Load Capacitance − nF
SLEW RATE
vs
LOAD CAPACITANCE
101 0.10.01
VCC± = ±15 V
AVD = − 1
TA = 25°C
SR+
SR−
40
50
−75 −50 −25 0 25 50 75 100 125 150
TA − Free-Air Temperature − °C
30
20
10
40
µs
SR − Slew Rate − V/
SLEW RATE
vs
FREE-AIR TEMPERATURE
0
50
60
SR +
SR −
VCC± = ±15 V
AVD = − 1
RL = 2 kΩ
CL = 500 pF
0
−10
−15 0 1
5
10
15
2345
VO − Output Voltage − VVO
t − Time − µs
NONINVERTING
LARGE-SIGNAL
PULSE RESPONSE
TA = −55°C
TA = 25°C
TA = 125°C
TA = 25°C
TA = −55°C
TA = 125°C
VCC± = ±15 V
AVD = 1
RL = 2 kΩ
CL = 300 pF
0
−10
−15
5
10
15
−5
543210
t − Time − µs
INVERTING
LARGE-SIGNAL
PULSE RESPONSE
VO − Output Voltage − VVO
VCC± = ±15 V
AVD = −1
RL = 2 kΩ
CL = 300 pF
TA = 25°C
TA = −55°C
TA = 125°CTA = −55°C
TA = 25°C
TA = 125°C
0
−10
−15
5
10
15
−5
TLE2141-EP
TLE2142-EP
TLE2144-EP
www.ti.com
........................................................................................................................................................................................................ SLOS577 – MAY 2008
Figure 29. Figure 30.
Figure 31. Figure 32.
Copyright © 2008, Texas Instruments Incorporated Submit Documentation Feedback 25
Product Folder Link(s): TLE2141-EP TLE2142-EP TLE2144-EP
l TEXAS INSTRUMENTS ‘ ‘ ‘ H A __.———-"‘ \ v \ \ ,§\ v t—Time—ns CL \HH ‘ \‘WH ‘\\\ TA:—55°C ~\ \ \ \ TA: 25°C \ 5 \~ \~. \\§\\ \:: w w w \
VO − Output Voltage − mV
VO
0
−100
100
50
4000 800 1200 1600
t − Time − ns
SMALL-SIGNAL
PULSE RESPONSE
VCC± = ±15 V
AVD = −1
RL = 2 kΩ
CL = 300 pF
TA = 25°C
−50
10 10000
CL − Load Capacitance − pF
PHASE MARGIN
vs
LOAD CAPACITANCE
1000100
− Phase Margin
TA = −55°C
TA = 125°C
VCC± = ±15 V
RL = 2 kΩ
70°
60°
50°
40°
30°
20°
10°
0°
φm
TA = 25°C
2
010
Gain Margin − dB
4
6
10000
CL − Load Capacitance − pF
8
10
GAIN MARGIN
vs
LOAD CAPACITANCE
1000100
12
14
TA = 125°C
TA = 25°C
TA = −55°C
VCC± = ±15 V
AVD = 1
RL = 2 kΩ to ∞
VO = −10 V to 10 V
TLE2141-EP
TLE2142-EP
TLE2144-EP
SLOS577 – MAY 2008 ........................................................................................................................................................................................................
www.ti.com
Figure 33. Figure 34.
Figure 35. Figure 36.
26 Submit Documentation Feedback Copyright © 2008, Texas Instruments Incorporated
Product Folder Link(s): TLE2141-EP TLE2142-EP TLE2144-EP
l TEXAS INSTRUMENTS
APPLICATION INFORMATION
Input Offset Voltage Nulling
+
–
OUT
IN+
IN-
3
2
6
1
5
OFFSET N1OFFSET N2
5 kW
1 kW
VCC– (split supply)
GND (single supply)
TLE2141-EP
TLE2142-EP
TLE2144-EP
www.ti.com
........................................................................................................................................................................................................ SLOS577 – MAY 2008
The TLE2141 offers external null pins that can be used to further reduce the input offset voltage. If this feature isdesired, connect the circuit of Figure 37 as shown. If external nulling is not needed, the null pins may be leftunconnected.
Figure 37. Input Offset Voltage Null Circuit
Copyright © 2008, Texas Instruments Incorporated Submit Documentation Feedback 27
Product Folder Link(s): TLE2141-EP TLE2142-EP TLE2144-EP
l TEXAS INSTRUMENTS REEL DIMENSIONS TAPE DIMENSIONS ’ I+K0 '«PI» Reel Diame|er AD Dimension deSIgned Io accommodate me componem wIdIh E0 Dimension deSIgned Io eecommodaIe me componenI Iengm KO Dlmenslun desIgned to accommodate me componem Ihlckness 7 w OvereII wmm OHhe earner cape i p1 Pitch between successwe cavIIy cemers f T Reel Width (W1) QUADRANT ASSIGNMENTS FOR PIN 1 ORIENTATION IN TAPE O O O D O O D O SprockeIHoles ,,,,,,,,,,, ‘ User Direcllon 0' Feed Pockel Quadrams
TAPE AND REEL INFORMATION
*All dimensions are nominal
Device Package
Type Package
Drawing Pins SPQ Reel
Diameter
(mm)
Reel
Width
W1 (mm)
A0
(mm) B0
(mm) K0
(mm) P1
(mm) W
(mm) Pin1
Quadrant
TLE2141MDREP SOIC D 8 2500 330.0 12.4 6.4 5.2 2.1 8.0 12.0 Q1
TLE2144MDWREP SOIC DW 16 2000 330.0 16.4 10.75 10.7 2.7 12.0 16.0 Q1
PACKAGE MATERIALS INFORMATION
www.ti.com 23-Jul-2021
Pack Materials-Page 1
l TEXAS INSTRUMENTS TAPE AND REEL BOX DIMENSIONS
*All dimensions are nominal
Device Package Type Package Drawing Pins SPQ Length (mm) Width (mm) Height (mm)
TLE2141MDREP SOIC D 8 2500 340.5 336.1 25.0
TLE2144MDWREP SOIC DW 16 2000 350.0 350.0 43.0
PACKAGE MATERIALS INFORMATION
www.ti.com 23-Jul-2021
Pack Materials-Page 2
www.ti.com
GENERIC PACKAGE VIEW
This image is a representation of the package family, actual package may vary.
Refer to the product data sheet for package details.
SOIC - 2.65 mm max heightDW 16
SMALL OUTLINE INTEGRATED CIRCUIT
7.5 x 10.3, 1.27 mm pitch
4224780/A
www.ti.com
PACKAGE OUTLINE
C
TYP
10.63
9.97
2.65 MAX
14X 1.27
16X 0.51
0.31
2X
8.89
TYP
0.33
0.10
0 - 8 0.3
0.1
(1.4)
0.25
GAGE PLANE
1.27
0.40
A
NOTE 3
10.5
10.1
B
NOTE 4
7.6
7.4
4220721/A 07/2016
SOIC - 2.65 mm max heightDW0016A
SOIC
NOTES:
1. All linear dimensions are in millimeters. Dimensions in parenthesis are for reference only. Dimensioning and tolerancing
per ASME Y14.5M.
2. This drawing is subject to change without notice.
3. This dimension does not include mold flash, protrusions, or gate burrs. Mold flash, protrusions, or gate burrs shall not
exceed 0.15 mm, per side.
4. This dimension does not include interlead flash. Interlead flash shall not exceed 0.25 mm, per side.
5. Reference JEDEC registration MS-013.
116
0.25 C A B
9
8
PIN 1 ID
AREA
SEATING PLANE
0.1 C
SEE DETAIL A
DETAIL A
TYPICAL
SCALE 1.500
£3ng
www.ti.com
EXAMPLE BOARD LAYOUT
0.07 MAX
ALL AROUND 0.07 MIN
ALL AROUND
(9.3)
14X (1.27)
R0.05 TYP
16X (2)
16X (0.6)
4220721/A 07/2016
SOIC - 2.65 mm max heightDW0016A
SOIC
NOTES: (continued)
6. Publication IPC-7351 may have alternate designs.
7. Solder mask tolerances between and around signal pads can vary based on board fabrication site.
METAL SOLDER MASK
OPENING
NON SOLDER MASK
DEFINED
SOLDER MASK DETAILS
OPENING
SOLDER MASK METAL
SOLDER MASK
DEFINED
LAND PATTERN EXAMPLE
SCALE:7X
SYMM
1
89
16
SEE
DETAILS
SYMM
Egg e %
www.ti.com
EXAMPLE STENCIL DESIGN
R0.05 TYP
16X (2)
16X (0.6)
14X (1.27)
(9.3)
4220721/A 07/2016
SOIC - 2.65 mm max heightDW0016A
SOIC
NOTES: (continued)
8. Laser cutting apertures with trapezoidal walls and rounded corners may offer better paste release. IPC-7525 may have alternate
design recommendations.
9. Board assembly site may have different recommendations for stencil design.
SOLDER PASTE EXAMPLE
BASED ON 0.125 mm THICK STENCIL
SCALE:7X
SYMM
SYMM
1
89
16
‘J
www.ti.com
PACKAGE OUTLINE
C
.228-.244 TYP
[5.80-6.19]
.069 MAX
[1.75]
6X .050
[1.27]
8X .012-.020
[0.31-0.51]
2X
.150
[3.81]
.005-.010 TYP
[0.13-0.25]
0 - 8 .004-.010
[0.11-0.25]
.010
[0.25]
.016-.050
[0.41-1.27]
4X (0 -15 )
A
.189-.197
[4.81-5.00]
NOTE 3
B .150-.157
[3.81-3.98]
NOTE 4
4X (0 -15 )
(.041)
[1.04]
SOIC - 1.75 mm max heightD0008A
SMALL OUTLINE INTEGRATED CIRCUIT
4214825/C 02/2019
NOTES:
1. Linear dimensions are in inches [millimeters]. Dimensions in parenthesis are for reference only. Controlling dimensions are in inches.
Dimensioning and tolerancing per ASME Y14.5M.
2. This drawing is subject to change without notice.
3. This dimension does not include mold flash, protrusions, or gate burrs. Mold flash, protrusions, or gate burrs shall not
exceed .006 [0.15] per side.
4. This dimension does not include interlead flash.
5. Reference JEDEC registration MS-012, variation AA.
18
.010 [0.25] C A B
5
4
PIN 1 ID AREA
SEATING PLANE
.004 [0.1] C
SEE DETAIL A
DETAIL A
TYPICAL
SCALE 2.800
Yl“‘+
www.ti.com
EXAMPLE BOARD LAYOUT
.0028 MAX
[0.07]
ALL AROUND
.0028 MIN
[0.07]
ALL AROUND
(.213)
[5.4]
6X (.050 )
[1.27]
8X (.061 )
[1.55]
8X (.024)
[0.6]
(R.002 ) TYP
[0.05]
SOIC - 1.75 mm max heightD0008A
SMALL OUTLINE INTEGRATED CIRCUIT
4214825/C 02/2019
NOTES: (continued)
6. Publication IPC-7351 may have alternate designs.
7. Solder mask tolerances between and around signal pads can vary based on board fabrication site.
METAL SOLDER MASK
OPENING
NON SOLDER MASK
DEFINED
SOLDER MASK DETAILS
EXPOSED
METAL
OPENING
SOLDER MASK METAL UNDER
SOLDER MASK
SOLDER MASK
DEFINED
EXPOSED
METAL
LAND PATTERN EXAMPLE
EXPOSED METAL SHOWN
SCALE:8X
SYMM
1
45
8
SEE
DETAILS
SYMM
www.ti.com
EXAMPLE STENCIL DESIGN
8X (.061 )
[1.55]
8X (.024)
[0.6]
6X (.050 )
[1.27] (.213)
[5.4]
(R.002 ) TYP
[0.05]
SOIC - 1.75 mm max heightD0008A
SMALL OUTLINE INTEGRATED CIRCUIT
4214825/C 02/2019
NOTES: (continued)
8. Laser cutting apertures with trapezoidal walls and rounded corners may offer better paste release. IPC-7525 may have alternate
design recommendations.
9. Board assembly site may have different recommendations for stencil design.
SOLDER PASTE EXAMPLE
BASED ON .005 INCH [0.125 MM] THICK STENCIL
SCALE:8X
SYMM
SYMM
1
45
8
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