Datenblatt für STM32F722xx, STM32F723xx von STMicroelectronics

This is information on a product in full production.
November 2020 DS11853 Rev 7 1/230
STM32F722xx
STM32F723xx
Arm® Cortex®-M7 32b MCU+FPU, 462DMIPS, up to 512KB Flash
/256+16+4KB RAM, USB OTG HS/FS, 18 TIMs, 3 ADCs, 21 com IF
Datasheet - production data
Features
•Core: Arm® 32-bit Cortex®-M7 CPU with FPU,
adaptive real-time accelerator (ART
Accelerator) and L1-cache: 8 Kbytes of data
cache and 8 Kbytes of instruction cache,
allowing 0-wait state execution from embedded
Flash memory and external memories,
frequency up to 216 MHz, MPU,
462 DMIPS/2.14 DMIPS/MHz (Dhrystone 2.1)
and DSP instructions.
•Memories
– Up to 512 Kbytes of Flash memory with
protection mechanisms (read and write
protections, proprietary code readout
protection (PCROP))
– 528 bytes of OTP memory
– SRAM: 256 Kbytes (including 64 Kbytes of
data TCM RAM for critical real-time data) +
16 Kbytes of instruction TCM RAM (for
critical real-time routines) + 4 Kbytes of
backup SRAM (available in the lowest
power modes)
– Flexible external memory controller with up
to 32-bit data bus: SRAM, PSRAM,
SDRAM/LPSDR SDRAM, NOR/NAND
memories
•Dual mode Quad-SPI
•Clock, reset and supply management
– 1.7 V to 3.6 V application supply and I/Os
– POR, PDR, PVD and BOR
– Dedicated USB power
– 4-to-26 MHz crystal oscillator
– Internal 16 MHz factory-trimmed RC (1%
accuracy)
– 32 kHz oscillator for RTC with calibration
– Internal 32 kHz RC with calibration
•Low-power
– Sleep, Stop and Standby modes
–V
BAT supply for RTC, 32×32 bit backup
registers + 4 Kbytes of backup SRAM
•3×12-bit, 2.4 MSPS ADC: up to 24 channels
and 7.2 MSPS in triple interleaved mode
•2×12-bit D/A converters
•Up to 18 timers: up to thirteen 16-bit (1x low-
power 16-bit timer available in Stop mode) and
two 32-bit timers, each with up to 4
IC/OC/PWMs or pulse counter and quadrature
(incremental) encoder inputs. All 15 timers
running up to 216 MHz. 2x watchdogs, SysTick
timer
•General-purpose DMA: 16-stream DMA
controller with FIFOs and burst support
•Debug mode
– SWD and JTAG interfaces
–Cortex
®-M7 Trace Macrocell™
•Up to 140 I/O ports with interrupt capability
– Up to 136 fast I/Os up to 108 MHz
– Up to 138 5 V-tolerant I/Os
•Up to 21 communication interfaces
– Up to 3× I2C interfaces (SMBus/PMBus)
– Up to 4 USARTs/4 UARTs (27 Mbit/s,
ISO7816 interface, LIN, IrDA, modem
control)
– Up to 5 SPIs (up to 54 Mbit/s), 3 with
muxed simplex I2Ss for audio class
accuracy via internal audio PLL or external
clock
– 2 x SAIs (serial audio interface)
LQFP64 (10 × 10 mm) UFBGA144 (7 x 7 mm)
UFBGA176 (10 x 10 mm)
LQFP176 (24 x 24 mm)
WLCSP100
(0.4 mm pitch)
LQFP144 (20 × 20 mm)
LQFP100 (14 × 14 mm)
www.st.com
STM32F722xx STM32F723xx
2/230 DS11853 Rev 7
– 1 x CAN (2.0B active)
– 2 x SDMMCs
•Advanced connectivity
– USB 2.0 full-speed device/host/OTG
controller with on-chip PHY
– USB 2.0 high-speed/full-speed
device/host/OTG controller with
dedicated DMA, on-chip full-speed
PHY and on-chip Hi-speed PHY or
ULPI depending on the part number
•True random number generator
•CRC calculation unit
•RTC: subsecond accuracy, hardware
calendar
•96-bit unique ID
Table 1. Device summary
Reference Part number
STM32F722xx STM32F722IC, STM32F722IE, STM32F722RC, STM32F722RE, STM32F722VC,
STM32F722VE, STM32F722ZC, STM32F722ZE
STM32F723xx STM32F723IC, STM32F723IE, STM32F723VC, STM32F723VE, STM32F723ZC,
STM32F723ZE
DS11853 Rev 7 3/230
STM32F722xx STM32F723xx Contents
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Contents
1 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13
2 Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14
2.1 Full compatibility throughout the family . . . . . . . . . . . . . . . . . . . . . . . . . . 17
2.2 STM32F723xx versus STM32F722xx LQFP100/ LQFP144/
LQFP176 packages . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19
3 Functional overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22
3.1 Arm® Cortex®-M7 with FPU . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22
3.2 Memory protection unit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22
3.3 Embedded Flash memory . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23
3.4 CRC (cyclic redundancy check) calculation unit . . . . . . . . . . . . . . . . . . . 23
3.5 Embedded SRAM . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23
3.6 AXI-AHB bus matrix . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24
3.7 DMA controller (DMA) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25
3.8 Flexible memory controller (FMC) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26
3.9 Quad-SPI memory interface (QUADSPI) . . . . . . . . . . . . . . . . . . . . . . . . . 26
3.10 Nested vectored interrupt controller (NVIC) . . . . . . . . . . . . . . . . . . . . . . . 27
3.11 External interrupt/event controller (EXTI) . . . . . . . . . . . . . . . . . . . . . . . . . 27
3.12 Clocks and startup . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27
3.13 Boot modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28
3.14 Power supply schemes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28
3.15 Power supply supervisor . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30
3.15.1 Internal reset ON . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30
3.15.2 Internal reset OFF . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30
3.16 Voltage regulator . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32
3.16.1 Regulator ON . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32
3.16.2 Regulator OFF . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33
3.16.3 Regulator ON/OFF and internal reset ON/OFF availability . . . . . . . . . . 36
3.17 Real-time clock (RTC), backup SRAM and backup registers . . . . . . . . . . 36
3.18 Low-power modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 37
3.19 VBAT operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 38
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3.20 Timers and watchdogs . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 38
3.20.1 Advanced-control timers (TIM1, TIM8) . . . . . . . . . . . . . . . . . . . . . . . . . 40
3.20.2 General-purpose timers (TIMx) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 40
3.20.3 Basic timers TIM6 and TIM7 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 40
3.20.4 Low-power timer (LPTIM1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 41
3.20.5 Independent watchdog . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 41
3.20.6 Window watchdog . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 41
3.20.7 SysTick timer . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 41
3.21 Inter-integrated circuit interface (I2C) . . . . . . . . . . . . . . . . . . . . . . . . . . . . 42
3.22 Universal synchronous/asynchronous receiver transmitters (USART) . . 43
3.23 Serial peripheral interface (SPI)/inter- integrated sound interfaces (I2S) . 44
3.24 Serial audio interface (SAI) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 44
3.25 Audio PLL (PLLI2S) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 45
3.26 Audio PLL (PLLSAI) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 45
3.27 SD/SDIO/MMC card host interface (SDMMC) . . . . . . . . . . . . . . . . . . . . . 45
3.28 Controller area network (bxCAN) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 45
3.29 Universal serial bus on-the-go full-speed (OTG_FS) . . . . . . . . . . . . . . . . 46
3.30 Universal serial bus on-the-go high-speed (OTG_HS) . . . . . . . . . . . . . . . 46
3.31 Random number generator (RNG) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 47
3.32 General-purpose input/outputs (GPIOs) . . . . . . . . . . . . . . . . . . . . . . . . . . 47
3.33 Analog-to-digital converters (ADCs) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 47
3.34 Temperature sensor . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 48
3.35 Digital-to-analog converter (DAC) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 48
3.36 Serial wire JTAG debug port (SWJ-DP) . . . . . . . . . . . . . . . . . . . . . . . . . . 48
3.37 Embedded Trace Macrocell™ . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 49
4 Pinouts and pin description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 50
5 Memory mapping . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 100
6 Electrical characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 101
6.1 Parameter conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 101
6.1.1 Minimum and maximum values . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 101
6.1.2 Typical values . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 101
6.1.3 Typical curves . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 101
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STM32F722xx STM32F723xx Contents
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6.1.4 Loading capacitor . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 101
6.1.5 Pin input voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 101
6.1.6 Power supply scheme . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 102
6.1.7 Current consumption measurement . . . . . . . . . . . . . . . . . . . . . . . . . . 104
6.2 Absolute maximum ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 104
6.3 Operating conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 106
6.3.1 General operating conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 106
6.3.2 VCAP1/VCAP2 external capacitor . . . . . . . . . . . . . . . . . . . . . . . . . . . . 109
6.3.3 Operating conditions at power-up / power-down (regulator ON) . . . . . 110
6.3.4 Operating conditions at power-up / power-down (regulator OFF) . . . . 110
6.3.5 Reset and power control block characteristics . . . . . . . . . . . . . . . . . . 110
6.3.6 Over-drive switching characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . 112
6.3.7 Supply current characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 112
6.3.8 Wakeup time from low-power modes . . . . . . . . . . . . . . . . . . . . . . . . . . 130
6.3.9 External clock source characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . 131
6.3.10 Internal clock source characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . 136
6.3.11 PLL characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 137
6.3.12 PLL spread spectrum clock generation (SSCG) characteristics . . . . . 140
6.3.13 USB OTG HS PHY PLLs characteristics (on STM32F723xx devices) 142
6.3.14 USB OTG HS PHY regulator characteristics . . . . . . . . . . . . . . . . . . . 142
6.3.15 USB HS PHY external resistor characteristics
(on STM32F723xx devices) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 143
6.3.16 Memory characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 143
6.3.17 EMC characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 145
6.3.18 Absolute maximum ratings (electrical sensitivity) . . . . . . . . . . . . . . . . 146
6.3.19 I/O current injection characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . 147
6.3.20 I/O port characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 148
6.3.21 NRST pin characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 154
6.3.22 TIM timer characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 155
6.3.23 RTC characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 155
6.3.24 12-bit ADC characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 155
6.3.25 Temperature sensor characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . 161
6.3.26 VBAT monitoring characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 161
6.3.27 Reference voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 161
6.3.28 DAC electrical characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 162
6.3.29 Communications interfaces . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 164
6.3.30 FMC characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 177
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6/230 DS11853 Rev 7
6.3.31 Quad-SPI interface characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . 197
6.3.32 SD/SDIO MMC card host interface (SDMMC) characteristics . . . . . . . 199
7 Package information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 202
7.1 LQFP64 – 10 x 10 mm, low-profile quad flat package information . . . . . 202
7.2 LQFP100, 14 x 14 mm low-profile quad flat package information . . . . . 205
7.3 LQFP144, 20 x 20 mm low-profile quad flat package information . . . . . 208
7.4 LQFP176 24 x 24 mm low-profile quad flat package information . . . . . . .211
7.5 UFBGA144 package information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 215
7.6 UFBGA176+25, 10 x 10, 0.65 mm ultra thin-pitch ball grid
array package information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 218
7.7 WLCSP100 - 0.4 mm pitch wafer level chip scale package information 221
7.8 Thermal characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 225
8 Ordering information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 226
Appendix A Recommendations when using internal reset OFF . . . . . . . . . . . 227
A.1 Operating conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 227
Revision history . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 228
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STM32F722xx STM32F723xx List of tables
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List of tables
Table 1. Device summary . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2
Table 2. STM32F722xx and STM32F723xx features and peripheral counts . . . . . . . . . . . . . . . . . . 15
Table 3. Voltage regulator configuration mode versus device operating mode . . . . . . . . . . . . . . . . 33
Table 4. Regulator ON/OFF and internal reset ON/OFF availability. . . . . . . . . . . . . . . . . . . . . . . . . 36
Table 5. Voltage regulator modes in stop mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 37
Table 6. Timer feature comparison . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 39
Table 7. I2C implementation. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 42
Table 8. USART implementation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 43
Table 9. Legend/abbreviations used in the pinout table . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 61
Table 10. STM32F722xx and STM32F723xx pin and ball definition . . . . . . . . . . . . . . . . . . . . . . . . . 62
Table 11. FMC pin definition. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 86
Table 12. STM32F722xx and STM32F723xx alternate function mapping. . . . . . . . . . . . . . . . . . . . . 89
Table 13. Voltage characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 104
Table 14. Current characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 105
Table 15. Thermal characteristics. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 106
Table 16. General operating conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 106
Table 17. Limitations depending on the operating power supply range . . . . . . . . . . . . . . . . . . . . . . 108
Table 18. VCAP1/VCAP2 operating conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 109
Table 19. VCAP1 operating conditions in the LQFP64 package . . . . . . . . . . . . . . . . . . . . . . . . . . . 110
Table 20. Operating conditions at power-up / power-down (regulator ON) . . . . . . . . . . . . . . . . . . . 110
Table 21. Operating conditions at power-up / power-down (regulator OFF). . . . . . . . . . . . . . . . . . . 110
Table 22. reset and power control block characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 111
Table 23. Over-drive switching characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 112
Table 24. Typical and maximum current consumption in Run mode, code with data processing
running from ITCM RAM, regulator ON . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 113
Table 25. Typical and maximum current consumption in Run mode, code with data processing
running from Flash memory (ART ON except prefetch / L1-cache ON)
or SRAM on AXI (L1-cache ON), regulator ON . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 114
Table 26. Typical and maximum current consumption in Run mode, code with data processing
running from Flash memory or SRAM on AXI (L1-cache disabled), regulator ON . . . . . 115
Table 27. Typical and maximum current consumption in Run mode, code with data processing
running from Flash memory on ITCM interface (ART disabled), regulator ON . . . . . . . . 116
Table 28. Typical and maximum current consumption in Run mode, code with data processing
running from Flash memory (ART ON except prefetch / L1-cache ON)
or SRAM on AXI (L1-cache ON), regulator OFF. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 117
Table 29. Typical and maximum current consumption in Sleep mode, regulator ON. . . . . . . . . . . . 118
Table 30. Typical and maximum current consumption in Sleep mode, regulator OFF . . . . . . . . . . . 118
Table 31. Typical and maximum current consumptions in Stop mode . . . . . . . . . . . . . . . . . . . . . . . 119
Table 32. Typical and maximum current consumptions in Standby mode . . . . . . . . . . . . . . . . . . . . 120
Table 33. Typical and maximum current consumptions in VBAT mode. . . . . . . . . . . . . . . . . . . . . . . 121
Table 34. Switching output I/O current consumption . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 125
Table 35. Peripheral current consumption . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 127
Table 36. USB OTG HS and USB OTG PHY HS current consumption . . . . . . . . . . . . . . . . . . . . . . 130
Table 37. Low-power mode wakeup timings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 130
Table 38. High-speed external user clock characteristics. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 131
Table 39. Low-speed external user clock characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 132
Table 40. HSE 4-26 MHz oscillator characteristics. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 133
Table 41. LSE oscillator characteristics (fLSE = 32.768 kHz) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 134
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Table 42. HSI oscillator characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 136
Table 43. LSI oscillator characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 137
Table 44. Main PLL characteristics. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 137
Table 45. PLLI2S characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 138
Table 46. PLLISAI characteristics. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 139
Table 47. SSCG parameters constraint . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 140
Table 48. USB OTG HS PLL1 characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 142
Table 49. USB OTG HS PLL2 characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 142
Table 50. USB OTG HS PHY regulator characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 142
Table 51. USB HS PHY external resistor characteristics (on STM32F723xx devices). . . . . . . . . . . 143
Table 52. Flash memory characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 143
Table 53. Flash memory programming . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 143
Table 54. Flash memory programming with VPP . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 144
Table 55. Flash memory endurance and data retention . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 144
Table 56. EMS characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 145
Table 57. EMI characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 146
Table 58. ESD absolute maximum ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 147
Table 59. Electrical sensitivities . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 147
Table 60. I/O current injection susceptibility . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 148
Table 61. I/O static characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 148
Table 62. Output voltage characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 151
Table 63. I/O AC characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 152
Table 64. NRST pin characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 154
Table 65. TIMx characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 155
Table 66. RTC characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 155
Table 67. ADC characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 155
Table 68. ADC static accuracy at fADC = 18 MHz . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 157
Table 69. ADC static accuracy at fADC = 30 MHz . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 157
Table 70. ADC static accuracy at fADC = 36 MHz . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 158
Table 71. ADC dynamic accuracy at fADC = 18 MHz - limited test conditions . . . . . . . . . . . . . . . . . 158
Table 72. ADC dynamic accuracy at fADC = 36 MHz - limited test conditions . . . . . . . . . . . . . . . . . 158
Table 73. Temperature sensor characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 161
Table 74. Temperature sensor calibration values. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 161
Table 75. VBAT monitoring characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 161
Table 76. internal reference voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 161
Table 77. Internal reference voltage calibration values . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 162
Table 78. DAC characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 162
Table 79. Minimum I2CCLK frequency in all I2C modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 165
Table 80. I2C analog filter characteristics. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 165
Table 81. SPI dynamic characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 166
Table 82. I2S dynamic characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 169
Table 83. SAI characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 171
Table 84. USB OTG full speed startup time . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 173
Table 85. USB OTG full speed DC electrical characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 173
Table 86. USB OTG full speed electrical characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 174
Table 87. USB HS DC electrical characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 174
Table 88. USB HS clock timing parameters . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 175
Table 89. Dynamic characteristics: USB ULPI . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 176
Table 90. USB OTG high speed DC electrical characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 176
Table 91. USB OTG high speed electrical characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 176
Table 92. USB FS PHY BCD electrical characteristics. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 177
Table 93. Asynchronous non-multiplexed SRAM/PSRAM/NOR read timings . . . . . . . . . . . . . . . . . 179
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Table 94. Asynchronous non-multiplexed SRAM/PSRAM/NOR read - NWAIT timings . . . . . . . . . . 179
Table 95. Asynchronous non-multiplexed SRAM/PSRAM/NOR write timings . . . . . . . . . . . . . . . . . 180
Table 96. Asynchronous non-multiplexed SRAM/PSRAM/NOR write - NWAIT timings. . . . . . . . . . 181
Table 97. Asynchronous multiplexed PSRAM/NOR read timings. . . . . . . . . . . . . . . . . . . . . . . . . . . 182
Table 98. Asynchronous multiplexed PSRAM/NOR read-NWAIT timings . . . . . . . . . . . . . . . . . . . . 182
Table 99. Asynchronous multiplexed PSRAM/NOR write timings . . . . . . . . . . . . . . . . . . . . . . . . . . 183
Table 100. Asynchronous multiplexed PSRAM/NOR write-NWAIT timings . . . . . . . . . . . . . . . . . . . . 184
Table 101. Synchronous multiplexed NOR/PSRAM read timings . . . . . . . . . . . . . . . . . . . . . . . . . . . 186
Table 102. Synchronous multiplexed PSRAM write timings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 188
Table 103. Synchronous non-multiplexed NOR/PSRAM read timings . . . . . . . . . . . . . . . . . . . . . . . . 189
Table 104. Synchronous non-multiplexed PSRAM write timings . . . . . . . . . . . . . . . . . . . . . . . . . . . . 191
Table 105. Switching characteristics for NAND Flash read cycles . . . . . . . . . . . . . . . . . . . . . . . . . . . 193
Table 106. Switching characteristics for NAND Flash write cycles. . . . . . . . . . . . . . . . . . . . . . . . . . . 193
Table 107. SDRAM read timings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 195
Table 108. LPSDR SDRAM read timings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 195
Table 109. SDRAM write timings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 196
Table 110. LPSDR SDRAM write timings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 197
Table 111. Quad-SPI characteristics in SDR mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 197
Table 112. Quad-SPI characteristics in DDR mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 198
Table 113. Dynamic characteristics: SD / MMC characteristics, VDD=2.7V to 3.6V . . . . . . . . . . . . . 200
Table 114. Dynamic characteristics: eMMC characteristics, VDD=1.71V to 1.9V . . . . . . . . . . . . . . . 201
Table 115. LQFP64 mechanical data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 202
Table 116. LQPF100 mechanical data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 205
Table 117. LQFP144 mechanical data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 208
Table 118. LQFP176 mechanical data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 211
Table 119. UFBGA144 mechanical data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 215
Table 120. UFBGA144 recommended PCB design rules (0.50 mm pitch BGA) . . . . . . . . . . . . . . . . 216
Table 121. UFBGA176+25 mechanical data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 218
Table 122. UFBGA176+25 recommended PCB design rules (0.65 mm pitch BGA) . . . . . . . . . . . . . 219
Table 123. WLCSP100 mechanical data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 222
Table 124. WLCSP100 recommended PCB design rules (0.4 mm pitch) . . . . . . . . . . . . . . . . . . . . . 223
Table 125. Package thermal characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 225
Table 126. Ordering information scheme . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 226
Table 127. Limitations depending on the operating power supply range . . . . . . . . . . . . . . . . . . . . . . 227
Table 128. Document revision history . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 228
List of figures STM32F722xx STM32F723xx
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List of figures
Figure 1. Compatible board design for LQFP100 package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17
Figure 2. Compatible board design for LQFP64 package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18
Figure 3. Compatible board design for LQFP100 package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19
Figure 4. Compatible board design for LQFP144 package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19
Figure 5. Compatible board design for LQFP176 package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20
Figure 6. STM32F722xx and STM32F723xx block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21
Figure 7. STM32F722xx and STM32F723xx AXI-AHB bus matrix architecture(1) . . . . . . . . . . . . . . 24
Figure 8. VDDUSB connected to VDD power supply . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29
Figure 9. VDDUSB connected to external power supply . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29
Figure 10. Power supply supervisor interconnection with internal reset OFF . . . . . . . . . . . . . . . . . . . 31
Figure 11. PDR_ON control with internal reset OFF . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31
Figure 12. Regulator OFF . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34
Figure 13. Startup in regulator OFF: slow VDD slope
- power-down reset risen after VCAP_1/VCAP_2 stabilization . . . . . . . . . . . . . . . . . . . . . . . . 35
Figure 14. Startup in regulator OFF mode: fast VDD slope
- power-down reset risen before VCAP_1/VCAP_2 stabilization . . . . . . . . . . . . . . . . . . . . . . 35
Figure 15. STM32F722xx LQFP64 pinout . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 50
Figure 16. STM32F722xx LQFP100 pinout . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 51
Figure 17. STM32F723xx LQFP100 pinout . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 52
Figure 18. STM32F723xx WLCSP100 ballout (with OTG PHY HS) . . . . . . . . . . . . . . . . . . . . . . . . . . 53
Figure 19. STM32F722xx LQFP144 pinout . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 54
Figure 20. STM32F723xx LQFP144 pinout . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 55
Figure 21. STM32F723xx UFBGA144 ballout (with OTG PHY HS). . . . . . . . . . . . . . . . . . . . . . . . . . . 56
Figure 22. STM32F722xx LQFP176 pinout . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 57
Figure 23. STM32F723xx LQFP176 pinout . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 58
Figure 24. STM32F723xx UFBGA176 ballout . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 59
Figure 25. STM32F723xx UFBGA176 ballout (with OTG PHY HS). . . . . . . . . . . . . . . . . . . . . . . . . . . 60
Figure 26. Pin loading conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 101
Figure 27. Pin input voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 101
Figure 28. STM32F722xx power supply scheme. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 102
Figure 29. STM32F723xx power supply scheme. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 103
Figure 30. Current consumption measurement scheme . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 104
Figure 31. External capacitor CEXT . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 109
Figure 32. Typical VBAT current consumption (RTC ON/BKP SRAM OFF and
LSE in low drive mode) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 122
Figure 33. Typical VBAT current consumption (RTC ON/BKP SRAM OFF and
LSE in medium low drive mode) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 122
Figure 34. Typical VBAT current consumption (RTC ON/BKP SRAM OFF and
LSE in medium high drive mode) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 123
Figure 35. Typical VBAT current consumption (RTC ON/BKP SRAM OFF and
LSE in high drive mode) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 123
Figure 36. Typical VBAT current consumption (RTC ON/BKP SRAM OFF and
LSE in high medium drive mode) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 124
Figure 37. High-speed external clock source AC timing diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . 132
Figure 38. Low-speed external clock source AC timing diagram. . . . . . . . . . . . . . . . . . . . . . . . . . . . 133
Figure 39. Typical application with an 8 MHz crystal . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 134
Figure 40. Typical application with a 32.768 kHz crystal . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 135
Figure 41. ACCHSI versus temperature . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 136
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Figure 42. LSI deviation versus temperature . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 137
Figure 43. PLL output clock waveforms in center spread mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . 141
Figure 44. PLL output clock waveforms in down spread mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 141
Figure 45. FT I/O input characteristics. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 150
Figure 46. I/O AC characteristics definition . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 153
Figure 47. Recommended NRST pin protection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 154
Figure 48. ADC accuracy characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 159
Figure 49. Typical connection diagram using the ADC . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 159
Figure 50. Power supply and reference decoupling (VREF+ not connected to VDDA). . . . . . . . . . . . . 160
Figure 51. Power supply and reference decoupling (VREF+ connected to VDDA). . . . . . . . . . . . . . . . 160
Figure 52. 12-bit buffered /non-buffered DAC . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 164
Figure 53. SPI timing diagram - slave mode and CPHA = 0 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 167
Figure 54. SPI timing diagram - slave mode and CPHA = 1 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 168
Figure 55. SPI timing diagram - master mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 168
Figure 56. I2S slave timing diagram (Philips protocol)(1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 170
Figure 57. I2S master timing diagram (Philips protocol)(1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 170
Figure 58. SAI master timing waveforms . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 172
Figure 59. SAI slave timing waveforms . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 172
Figure 60. USB OTG full speed timings: definition of data signal rise and fall time. . . . . . . . . . . . . . 174
Figure 61. ULPI timing diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 175
Figure 62. Asynchronous non-multiplexed SRAM/PSRAM/NOR read waveforms . . . . . . . . . . . . . . 178
Figure 63. Asynchronous non-multiplexed SRAM/PSRAM/NOR write waveforms . . . . . . . . . . . . . . 180
Figure 64. Asynchronous multiplexed PSRAM/NOR read waveforms. . . . . . . . . . . . . . . . . . . . . . . . 181
Figure 65. Asynchronous multiplexed PSRAM/NOR write waveforms . . . . . . . . . . . . . . . . . . . . . . . 183
Figure 66. Synchronous multiplexed NOR/PSRAM read timings . . . . . . . . . . . . . . . . . . . . . . . . . . . 185
Figure 67. Synchronous multiplexed PSRAM write timings. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 187
Figure 68. Synchronous non-multiplexed NOR/PSRAM read timings . . . . . . . . . . . . . . . . . . . . . . . . 189
Figure 69. Synchronous non-multiplexed PSRAM write timings . . . . . . . . . . . . . . . . . . . . . . . . . . . . 190
Figure 70. NAND controller waveforms for read access . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 192
Figure 71. NAND controller waveforms for write access . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 192
Figure 72. NAND controller waveforms for common memory read access . . . . . . . . . . . . . . . . . . . . 192
Figure 73. NAND controller waveforms for common memory write access. . . . . . . . . . . . . . . . . . . . 193
Figure 74. SDRAM read access waveforms (CL = 1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 194
Figure 75. SDRAM write access waveforms . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 196
Figure 76. Quad-SPI timing diagram - SDR mode. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 199
Figure 77. Quad-SPI timing diagram - DDR mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 199
Figure 78. SDIO high-speed mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 200
Figure 79. SD default mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 200
Figure 80. LQFP64 outline . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 202
Figure 81. LQFP64 recommended footprint . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 203
Figure 82. LQFP64 top view example . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 204
Figure 83. LQFP100 outline . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 205
Figure 84. LQFP100 recommended footprint . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 206
Figure 85. LQFP100 top view example . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 207
Figure 86. LQFP144 outline . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 208
Figure 87. LQFP144 recommended footprint . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 209
Figure 88. LQFP144 top view example . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 210
Figure 89. LQFP176 outline . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 211
Figure 90. LQFP176 recommended footprint . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 213
Figure 91. LQFP176 top view example . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 214
Figure 92. UFBGA144 outline . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 215
Figure 93. UFBGA144 recommended footprint . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 216
List of figures STM32F722xx STM32F723xx
12/230 DS11853 Rev 7
Figure 94. UFBGA144 top view example . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 217
Figure 95. UFBGA176 outline . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 218
Figure 96. UFBGA176+25 recommended footprint . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 219
Figure 97. UFBGA176 top view example. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 220
Figure 98. WLCSP100 outline . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 221
Figure 99. WLCSP100 recommended footprint . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 222
Figure 100. WLCSP100 top view example . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 224
USB arm
DS11853 Rev 7 13/230
STM32F722xx STM32F723xx Introduction
49
1 Introduction
This datasheet provides the ordering information and mechanical device characteristics of
the STM32F722xx and STM32F723xx microcontrollers.
This document should be ready in conjunction with the STM32F72xxx and STM32F73xxx
advanced Arm®-based 32-bit MCUs reference manual (RM0431). The reference manual is
available from the STMicroelectronics website www.st.com.
For information on the Arm®(a) Cortex®-M7 core, refer to the Cortex®-M7 technical
reference manual available from the http://www.arm.com website.
a. Arm is a registered trademark of Arm Limited (or its subsidiaries) in the US and/or elsewhere.
Description STM32F722xx STM32F723xx
14/230 DS11853 Rev 7
2 Description
The STM32F722xx and STM32F723xx devices are based on the high-performance Arm®
Cortex®-M7 32-bit RISC core operating at up to 216 MHz frequency. The Cortex®-M7 core
features a single floating point unit (SFPU) precision which supports Arm® single-precision
data-processing instructions and data types. It also implements a full set of DSP instructions
and a memory protection unit (MPU) which enhances the application security.
The STM32F722xx and STM32F723xx devices incorporate high-speed embedded
memories with a Flash memory up to 512 Kbytes, 256 Kbytes of SRAM (including
64 Kbytes of data TCM RAM for critical real-time data), 16 Kbytes of instruction TCM RAM
(for critical real-time routines), 4 Kbytes of backup SRAM available in the lowest power
modes, and an extensive range of enhanced I/Os and peripherals connected to two APB
buses, two AHB buses, a 32-bit multi-AHB bus matrix and a multi layer AXI interconnect
supporting internal and external memories access.
All the devices offer three 12-bit ADCs, two DACs, a low-power RTC, thirteen general-
purpose 16-bit timers including two PWM timers for motor control, two general-purpose 32-
bit timers, a true random number generator (RNG). They also feature standard and
advanced communication interfaces.
•Up to three I2Cs
•Five SPIs, three I2Ss in half duplex mode. To achieve the audio class accuracy, the I2S
peripherals can be clocked via a dedicated internal audio PLL or via an external clock
to allow synchronization.
•Four USARTs plus four UARTs
•An USB OTG full-speed and a USB OTG high-speed with full-speed capability (with the
ULPI or with the integrated HS PHY depending on the part number)
•One CAN
•Two SAI serial audio interfaces
•Two SDMMC host interfaces
Advanced peripherals include two SDMMC interfaces, a flexible memory control (FMC)
interface, a Quad-SPI Flash memory interface.
The STM32F722xx and STM32F723xx devices operate in the –40 to +105 °C temperature
range from a 1.7 to 3.6 V power supply. Dedicated supply inputs for the USB (OTG_FS and
OTG_HS) and the SDMMC2 (clock, command and 4-bit data) are available on all the
packages except LQFP100 and LQFP64 for a greater power supply choice.
The supply voltage can drop to 1.7 V with the use of an external power supply supervisor. A
comprehensive set of power-saving mode allows the design of low-power applications.
The STM32F722xx and STM32F723xx devices offer devices in 7 packages ranging from 64
pins to 176 pins. The set of included peripherals changes with the device chosen.
DS11853 Rev 7 15/230
STM32F722xx STM32F723xx Description
49
These features make the STM32F722xx and STM32F723xx microcontrollers suitable for a
wide range of applications:
•Motor drive and application control,
•Medical equipment,
•Industrial applications: PLC, inverters, circuit breakers,
•Printers, and scanners,
•Alarm systems, video intercom, and HVAC,
•Home audio appliances,
•Mobile applications, Internet of Things,
•Wearable devices: smartwatches.
The following table lists the peripherals available on each part number.
Table 2. STM32F722xx and STM32F723xx features and peripheral counts
Peripherals STM32F72xRx STM32F72xVx STM32F72xZx STM32F72xIx
Flash memory in Kbytes 256 512 256 512 256 512 256 512
SRAM in Kbytes
System 256(176+16+64)
Instruction 16
Backup 4
FMC memory controller No Yes(1)
Quad-SPI Yes
Timers
General-purpose 10(2)
Advanced-control 2
Basic 2
Low-power No 1
Random number generator Yes
Communication
interfaces
SPI / I2S 3/3 (simplex)(3) 4/3 (simplex)(3) 5/3 (simplex)(3)
I2C3
USART/UART 4/2 4/4
USB OTG FS Yes
USB OTG HS(4) Yes
USB OTG PHY HS
controller (USBPHYC) No Yes(10)
CAN 1
SAI 2
SDMMC1 Yes
SDMMC2 No Yes(5)(6)
GPIOs 50 82 in STM32F722xx
79 in STM32F723xx
114 in STM32F722xx
112 in STM32F723xx
140 in STM32F722xx
138 in STM32F723xx
12-bit ADC
Number of channels
3
16 24
12-bit DAC
Number of channels
Yes
2
Maximum CPU frequency 216 MHz(7)
Description STM32F722xx STM32F723xx
16/230 DS11853 Rev 7
Operating voltage 1.7 to 3.6 V(8)
Operating temperatures
Ambient temperatures: –40 to +85 °C /–40 to +105 °C
Junction temperature: –40 to + 125 °C
Package LQFP64(9) LQFP100
WLCSP100(10) LQFP144
UFBGA144(10) UFBGA176
LQFP176
1. For the LQFP100 package, only FMC Bank1 is available. Bank1 can only support a multiplexed NOR/PSRAM memory
using the NE1 Chip Select.
2. On the STM32F723xx device packages, except the 176-pin ones, the TIM12 is not available, so there are 9 general-
purpose timers.
3. The SPI1, SPI2 and SPI3 interfaces give the flexibility to work in an exclusive way in either the SPI mode or the I2S audio
mode.
4. USB OTG HS with the ULPI on the STM32F722xx devices and with integrated HS PHY on the STM32F723xx devices.
5. The SDMMC2 supports a dedicated power rail for clock, command and data 0..4 lines, feature available starting from 144
pin package.
6. The SDMMC2 is not available on the STM32F723Vx devices.
7. 216 MHz maximum frequency for - 40°C to + 85°C ambient temperature range (200 MHz maximum frequency for - 40°C to
+ 105°C ambient temperature range).
8. VDD/VDDA minimum value of 1.7 V is obtained when the internal reset is OFF (refer to Section 3.15.2: Internal reset OFF).
9. Available only on the STM32F722xx devices.
10. Available only on the STM32F723xx devices.
Table 2. STM32F722xx and STM32F723xx features and peripheral counts (continued)
Peripherals STM32F72xRx STM32F72xVx STM32F72xZx STM32F72xIx
an; :22, :3 2mm man in $1 «an in emu mm an E E :5 an 81 an E 21 .3 31 an; mm> 2n SYM32F71xxx - Pm: 19 m 49 ave um campalm‘e
DS11853 Rev 7 17/230
STM32F722xx STM32F723xx Description
49
2.1 Full compatibility throughout the family
The STM32F722xx devices are fully pin-to-pin, compatible with the STM32F7x5xx,
STM32F7x6xx, STM32F7x7xx devices.
The STM32F722xx devices are partially pin-to-pin, compatible with the STM32F4xxxx
devices, allowing the user to try different peripherals, and reaching higher performances
(higher frequency) for a greater degree of freedom during the development cycle.
Figure 1 and Figure 2 give compatible board designs between the STM32F722xx, with
LQFP64 and LQFP100 packages, and STM32F4xx families.
Figure 1. Compatible board design for LQFP100 package
MSv41001V2
18
19
20
21
22
23
24
25
PC3
VDD
VSSA
VREF+
VDDA
26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50
PA3
VSS
VDD
PA4
PA5
PA6
PA7
PC5
PB0
PB1
PB2
PE7
PE8
PE9
PE10
PE11
PE12
PE13
PE14
PC4
PB10
PB11
VCAP1
VDD
PE15
STM32F427xx / STM32F437xx
STM32F429xx / STM32F439xx
STM32F415xx / STM32F417xx
STM32F405xx / STM32F407xx
STM32F72xxx
18
19
20
21
22
23
24
25
26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50
VSS
VDD
VSS
PA4
PA5
PA6
PA7
PC5
PB0
PB1
PB2
PE7
PE8
PE9
PE10
PE11
PE12
PE13
PE14
PC4
PB10
PB11
VCAP1
VDD
PE15
PC3
VSSA
VREF+
VDDA
Pins 19 to 49 are not compatible
PA0-WKUP
PA1
PA2
PA3
PA0-WKUP
PA1
PA2
1 I 2x 29 32 w m w 20 2‘ 22 23 2o mg} \DEIDDDEIDDEIDEID
Description STM32F722xx STM32F723xx
18/230 DS11853 Rev 7
Figure 2. Compatible board design for LQFP64 package
The STM32F722xx LQFP144, UFBGA176 and LQFP176 packages are fully pin to pin
compatible with the STM32F4xx devices.
MSv41007V3
PB11 not available anymore
STM32F4x1
Replaced by VCAP_1
53 52 51 50 49
48
47
46
45
44
43
42
41
40
39
38
37
36
35
34
33
29 30 31 32
28
PC12
PC11
PC10
PA15
PA14
VDD
VSS
PA13
PA12
PA11
PA10
PA9
PA8
PC9
PC8
PC7
PC6
PB15
PB14
PB13
PB12
PB2
PB10
VCAP_1
VDD
VSS
STM32F405/
STM32F415 line
PC12
PC11
PC10
PA15
PA14
VSS
VSS
VDD
VDD
53 52 51 50 49
48
47
46
45
44
43
42
41
40
39
38
37
36
35
34
33
29 30 31 3228
VDD
VCAP_2
PA13
PA12
PA11
PA10
PA9
PA8
PC9
PC8
PC7
PC6
PB15
PB14
PB13
PB12
PB2
PB10
VCAP_1
VDD
PB11
V increased to 4.7 μf
ESR 1 ohm or below 1 ohm
CAP
VDD
VSS
VDD
PC12
PC10
PB5
PB4
PB3
A15
A14
PD2
PC5 not available anymore
V increased to 4.7 μf
VDD
STM32F722xx
57 56 55 54 53 52 51 50 49
48
47
46
45
44
43
42
41
40
39
38
37
36
35
34
33
24 29 30 31 3225 26 27 28
PC 11
VDD
VSS
PC8
PC7
PC6
PB12
PC4
PB2
PB10
PB11
VSS
VDD
PA13
PA12
PA11
PA10
PA9
PA8
PC9
PB15
PB14
PB13
PB0
PB1
P
P
VCAP_1
ESR between 0.1 ohm and 0.2 ohm
CAP
VDD
VSS
Replaced by VCAP_1
21 22 2317 18 19 20
VDD
PA4
PA6
PA7
PA3
VSS
PA5
Not compatible STM32F722xx pins with either
STM32F4x1 or STM32F405/F415 or both
VSS
VSS
DS11853 Rev 7 19/230
STM32F722xx STM32F723xx Description
49
2.2 STM32F723xx versus STM32F722xx LQFP100/ LQFP144/
LQFP176 packages
Figure 3. Compatible board design for LQFP100 package
Figure 4. Compatible board design for LQFP144 package
MSv63473V1
STM32F722xx
58
57
56
55
54
53
52
51
50
PD11
PD10
PD9
PD8
PB15
PB14
PB13
PB12
VDD
STM32F723xx
58
57
56
55
54
53
52
51
50
PD11
PB15
PB14
VDD12OTGHS
VDDPHYHS
OTG_HS_REXT
PB13
PB12
VDD
Not compatible pins
MSv41098V1
STM32F722xx
80
79
78
77
76
75
74
73
72
PD11
PD10
PD9
PD8
PB15
PB14
PB13
PB12
VDD
STM32F723xx
PG6, PG7 removed on the STM32F723xx
88
87
86
85
84
83
82
81
PG3
PG2
PD15
PD14
VDD
VSS
PD13
PD12
89 PG4
93
92
91
90
PG8
PG7
PG6
PG5
80
79
78
77
76
75
74
73
72
PD9
PD8
PB15
PB14
VDD12OTGHS
OTG_HS_REXT
PB13
PB12
VDD
88
87
86
85
84
83
82
81
PD15
PD14
VDD
VSS
PD13
PD12
PD11
PD10
89 PG2
93
92
91
90
PG8
PG5
PG4
PG3
Not compatible pins
Description STM32F722xx STM32F723xx
20/230 DS11853 Rev 7
Figure 5. Compatible board design for LQFP176 package
Figure 6 shows the general block diagram of the device family.
MSv41099V1
STM32F722xx
96
95
94
93
92
91
90
89
88
PD8
PB15
PB14
PB13
PB12
VDD
VSS
PH12
PH11
STM32F723xx
PG6, PG7 removed on the STM32F723xx
104
103
102
101
100
99
98
97
PD14
VDD
VSS
PD13
PD12
PD11
PD10
PD9
105 PD15
109
108
107
106
PG5
PG4
PG3
PG2
88
PB14
VDD12OTGHS
OTG_HS_REXT
PB13
PB12
VDD
VSS
PH12
PH11
PD13
PD12
PD11
PD10
PD9
PD8
PB15
VSS
PG2
PD15
PD14
VDD
112
111
110
PG8
PG7
PG6
96
95
94
93
92
91
90
89
104
103
102
101
100
99
98
97
105
109
108
107
106
112
111
110
PG3
PG4
PG8
PG5
Not compatible pins
DS11853 Rev 7 21/230
STM32F722xx STM32F723xx Description
49
Figure 6. STM32F722xx and STM32F723xx block diagram
1. The timers connected to APB2 are clocked from TIMxCLK up to 216 MHz, while the timers connected to APB1 are clocked
from TIMxCLK either up to 108 MHz or 216 MHz depending on TIMPRE bit configuration in the RCC_DCKCFGR register.
2. Available only on the STM32F723xx devices.
3. Available only on the STM32F723xx LQFP100 package.
MSv41012V4
GPIO PORT A
AHB/APB2
EXT IT. WKUP
168 AF
PA[15:0]
TIM1 / PWM
4 compl. chan. (TIM1_CH1[1:4]N),
4 chan. (TIM1_CH1[1:4]ETR, BKIN as AF
USART1
RX, TX, SCK,
CTS, RTS as AF
SPI1/I2S1
APB1 30MHz
8 analog inputs common
to the 3 ADCs
VDDREF_ADC
UART4
MOSI, MISO, SCK
NSS as AF
SPI3/I2S3
DAC1
as AF
ITF
WWDG
4 KB BKPRAM
OSC32_IN
OSC32_OUT
VDDA, VSSA
NRESET
smcard
irDA
16b
SDMMC1
D[7:0]
CMD, CK as AF
VBAT = 1.8 to 3.6 V
GPDMA2
SCL, SDA, SMBAL as AF
I2C3/SMBUS
GP-DMA2
8 Streams
FIFO
ACCEL/
CACHE
SRAM1 176KB
CLK, NE [3:0], A[23:0],
D[31:0], NOEN, NWEN,
NBL[3:0], SDCLKE[1:0]
SDNE[1:0], SDNWE, NL
NWAIT, INTN
DP
DM
SCL, SDA, INT, ID, VBUS
AHB1 216 MHz
FIFO
USAR T 2 M B p s
Temperature sensor
ADC1
ADC2
ADC3
IF
IF
POR/PDR
BOR
SUPPLY
SUPERVISION
PVD
Int
POR
reset
XTAL 32 kHz
MGT
RTC
RC HS
RC LS
Standby
interface
@VDDA
AWU
RCC
Reset & control
PLL1+PLL2+PLL3
AHB1PCLK
VDDUSB33 = 3.0 to 3.6 V
VSS
VCAP1
VOLT. REG
3.3V TO 1.2V
VDD12 BBgen + POWER MNGT
Backup register
AHB bus-matrix 8S7M
APB2 108 MHz (max)
LS
TIM14
TIM9
2 channels as AF
DAC1
TIM6
TIM7
TIM2
TIM3
TIM4
TIM5
TIM12
APB1 54 MHz (max)
SRAM2 16KB
AHB2 216 MHz
GP-DMA1
8 Streams
FIFO
PB[15:0]
PC[15:0]
PD[15:0]
PE[15:0]
PF[15:0]
PG[15:0]
PH[15:0]
PI[11:0]
GPIO PORT B
GPIO PORT C
GPIO PORT D
GPIO PORT E
GPIO PORT F
GPIO PORT G
GPIO PORT H
GPIO PORT I
TIM8 / PWM 16b
16b
TIM10 16b
TIM11 16b
smcard
irDA USART6
4 compl. chan.(TIM8_CH1[1:4]N),
4 chan. (TIM8_CH1[1:4], ETR, BKIN as AF
1 channel as AF
1 channel as AF
RX, TX, SCK,
CTS, RTS as AF
8 analog inputs common
to the ADC1 & 2
8 analog inputs for ADC3
DAC2
as AF
16b
16b
bxCAN1
I2C2/SMBUS
I2C1/SMBUS
SCL, SDA, SMBAL as AF
SCL, SDA, SMBAL as AF
SPI2/I2S2 MOSI, MISO, SCK
NSS as AF
TX, RX
RX, TX as AF
RX, TX as AF
RX, TX, SCK
CTS, RTS as AF
RX, TX, SCK
CTS, RTS as AF
1 channel as AF
UART5
USART3
USART2
smcard
irDA
smcard
irDA
16b
16b
16b
1 channel as AF
TIM13
2 channels as AF
32b
16b
16b
32b
4 channels
4 channels, ETR as AF
4 channels, ETR as AF
4 channels, ETR as AF
GPDMA1
AHB/
APB1
LS
OSC_IN
OSC_OUT
AHB2PCLK
XTAL OSC
4- 16MHz
SPI4
SCK, NSS as AF
SPI5
SCK, NSS as AF
MOSI, MISO,
MOSI, MISO,
RX, TX as AF
UART7
RX, TX as AF
UART8
SAI1
SD, SCK, FS, MCLK as AF
FIFO
NRAS, NCAS, NADV
RTC_TS
RTC_TAMPx
RTC_OUT
Arm CPU
Cortex-M7
AXIM
AHBP
AHBS
DTCM
ICTM
TRACECK
TRACED[3:0]
JTRST, JTDI,
JTCK/SWCLK
JTDO/SWD, JTDO
JTAG & SW
NVIC
ETM
MPU FPU
DTCM RAM 64KB
ITCM RAM 16KB
Quad-SPI CLK, CS,D[7:0]
AHB BUS-MATRIX 11S8M
VDDMMC33 = 3.0 to 3.6V
WKUP[4:0]
LPTIM1 16b
SAI2
SD, SCK, FS, MCLK as AF
FIFO
EXT MEM CTL (FMC)
SRAM, SDRAM, NOR-Flash,
NAND-Flash, SDRAM
216MHz
I-Cache
8KB
D-Cache
8KB
AHB2AXI
@VDDA
@VDD33
@VDD33
@VSW
Digital filter
@VDDA
@VDDA
FLASH 512KB
SDMMC2
D[7:0]
CMD, CK as AF
DAC2
SYSCFG
FIFO
WDG32K
VDD = 1.8 to 3.6 V
PWRCTRL
FCLK
HCLK
APBP2CLK
APBP1CLK
CRC
SCK, NSS as AF
MOSI, MISO,
FIFO
RNG
USB HS
PHY
PLL
LDO
PHY
USB
OTG FS
FIFO
SCL, SDA, INT, ID, VBUS
OTG HS PHY
CONTROLLER
(2)
DP, DM
ULPI:CK, D[7:0], DIR, STP, NXT
SCL/SDA, INT, ID, VBUS
USB OTG HS
FS PHY
PLL1
LDO
DMA/
FIFO
PLL2
(2)
ULPI:CK, D[7:0], DIR, STP, NXT
BGR
VDDPHYHS = 3.0 to 3.6V
(3)
Functional overview STM32F722xx STM32F723xx
22/230 DS11853 Rev 7
3 Functional overview
3.1 Arm® Cortex®-M7 with FPU
The Arm® Cortex®-M7 with FPU processor is the latest generation of Arm processors for
embedded systems. It was developed to provide a low-cost platform that meets the needs of
MCU implementation, with a reduced pin count and low-power consumption, while
delivering outstanding computational performance and low interrupt latency.
The Cortex®-M7 processor is a highly efficient high-performance featuring:
– Six-stage dual-issue pipeline
– Dynamic branch prediction
– Harvard caches (8 Kbytes of I-cache and 8 Kbytes of D-cache)
– 64-bit AXI4 interface
– 64-bit ITCM interface
– 2x32-bit DTCM interfaces
The processor supports the following memory interfaces:
•Tightly Coupled Memory (TCM) interface.
•Harvard instruction and data caches and AXI master (AXIM) interface.
•Dedicated low-latency AHB-Lite peripheral (AHBP) interface.
The processor supports a set of DSP instructions which allow efficient signal processing and
complex algorithm execution.
It supports single precision FPU (floating point unit), speeds up software development by
using metalanguage development tools, while avoiding saturation.
Figure 6 shows the general block diagram of the STM32F722xx and STM32F723xx family.
Note: Cortex®-M7 with FPU core is binary compatible with the Cortex®-M4 core.
3.2 Memory protection unit
The memory protection unit (MPU) is used to manage the CPU accesses to memory to
prevent one task to accidentally corrupt the memory or resources used by any other active
task. This memory area is organized into up to 8 protected areas that can in turn be divided
up into 8 subareas. The protection area sizes are between 32 bytes and the whole 4
gigabytes of addressable memory.
The MPU is especially helpful for applications where some critical or certified code has to be
protected against the misbehavior of other tasks. It is usually managed by an RTOS (real-
time operating system). If a program accesses a memory location that is prohibited by the
MPU, the RTOS can detect it and take action. In an RTOS environment, the kernel can
dynamically update the MPU area setting, based on the process to be executed.
The MPU is optional and can be bypassed for applications that do not need it.
DS11853 Rev 7 23/230
STM32F722xx STM32F723xx Functional overview
49
3.3 Embedded Flash memory
The STM32F722xx and STM32F723xx devices embed a Flash memory of up to 512 Kbytes
available for storing programs and data.
The flexible protections can be configured thanks to option bytes:
•Readout protection (RDP) to protect the whole memory. Three levels are available:
– Level 0: no readout protection
– Level 1: No access (read, erase, program) to the Flash memory or backup SRAM
can be performed while the debug feature is connected or while booting from RAM
or system memory bootloader
– Level 2: debug/chip read protection disabled.
•Write protection (WRP): the protected area is protected against erasing and
programming.
•Proprietary code readout protection (PCROP): Flash memory user sectors (0 to 7) can
be protected against D-bus read accesses by using the proprietary readout protection
(PCROP). The protected area is execute-only.
3.4 CRC (cyclic redundancy check) calculation unit
The CRC (cyclic redundancy check) calculation unit is used to get a CRC code using a
configurable generator polynomial value and size.
Among other applications, CRC-based techniques are used to verify data transmission or
storage integrity. In the scope of the EN/IEC 60335-1 standard, they offer a means of
verifying the Flash memory integrity. The CRC calculation unit helps compute a signature of
the software during runtime, to be compared with a reference signature generated at link-
time and stored at a given memory location.
3.5 Embedded SRAM
All the devices feature:
•System SRAM up to 256 Kbytes:
– SRAM1 on AHB bus Matrix: 176 Kbytes
– SRAM2 on AHB bus Matrix: 16 Kbytes
– DTCM-RAM on TCM interface (Tighly Coupled Memory interface): 64 Kbytes for
critical real-time data.
•Instruction RAM (ITCM-RAM) 16 Kbytes:
– It is mapped on TCM interface and reserved only for CPU Execution/Instruction
useful for critical real-time routines.
The Data TCM RAM is accessible by the GP-DMAs and peripheral DMAs through the
specific AHB slave of the CPU.The instruction TCM RAM is reserved only for CPU. It is
accessed at CPU clock speed with 0 wait states.
•4 Kbytes of backup SRAM
This area is accessible only from the CPU. Its content is protected against possible
unwanted write accesses, and is retained in Standby or VBAT mode.
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Functional overview STM32F722xx STM32F723xx
24/230 DS11853 Rev 7
3.6 AXI-AHB bus matrix
The STM32F722xx and STM32F723xx system architecture is based on 2 sub-systems:
•An AXI to multi AHB bridge converting AXI4 protocol to AHB-Lite protocol:
– 3x AXI to 32-bit AHB bridges connected to AHB bus matrix
– 1x AXI to 64-bit AHB bridge connected to the embedded Flash memory
•A multi-AHB Bus-Matrix
– The 32-bit multi-AHB bus matrix interconnects all the masters (CPU, DMAs, USB
HS) and the slaves (Flash memory, RAM, FMC, Quad-SPI, AHB and APB
peripherals) and ensures a seamless and efficient operation even when several
high-speed peripherals work simultaneously.
Figure 7. STM32F722xx and STM32F723xx AXI-AHB bus matrix architecture(1)
1. The above figure has large wires for 64-bits bus and thin wires for 32-bits bus.
MSv41005V1
Arm Cortex-M7
32-bit Bus Matrix - S
ART
FLASH
512KB
SRAM1
176KB
SRAM2
16KB
AHB
periph2
FMC external
MemCtl
Quad-SPI
AHBP
AXI to
multi-AHB
AHB
Periph1
DTCM RAM
ITCM RAM
DTCM
ITCM
AXIM
16KB
64KB
64-bit AHB
64-bit BuS Matrix
ITCM
APB1
APB2
AHBS
I/D Cache
8KB
GP
DMA1
GP
DMA2
USB OTG
HS
DMA_PI
DMA_MEM1
DMA_MEM2
DMA_P2
USB_HS_M
DS11853 Rev 7 25/230
STM32F722xx STM32F723xx Functional overview
49
3.7 DMA controller (DMA)
The devices feature two general-purpose dual-port DMAs (DMA1 and DMA2) with 8
streams each. They are able to manage memory-to-memory, peripheral-to-memory and
memory-to-peripheral transfers. They feature dedicated FIFOs for APB/AHB peripherals,
support burst transfer and are designed to provide the maximum peripheral bandwidth
(AHB/APB).
The two DMA controllers support a circular buffer management, so that no specific code is
needed when the controller reaches the end of the buffer. The two DMA controllers also
have a double buffering feature, which automates the use and switching of two memory
buffers without requiring any special code.
Each stream is connected to dedicated hardware DMA requests, with support for software
trigger on each stream. The configuration is made by software and transfer sizes between
source and destination are independent.
The DMA can be used with the main peripherals:
•SPI and I2S
•I2C
•USART
•General-purpose, basic and advanced-control timers TIMx
•DAC
•SDMMC
•ADC
•SAI
•Quad-SPI
Functional overview STM32F722xx STM32F723xx
26/230 DS11853 Rev 7
3.8 Flexible memory controller (FMC)
The Flexible memory controller (FMC) includes three memory controllers:
•The NOR/PSRAM memory controller
•The NAND/memory controller
•The Synchronous DRAM (SDRAM/Mobile LPSDR SDRAM) controller
The main features of the FMC controller are the following:
•Interface with static-memory mapped devices including:
– Static random access memory (SRAM)
– NOR Flash memory/OneNAND Flash memory
– PSRAM (4 memory banks)
– NAND Flash memory with ECC hardware to check up to 8 Kbytes of data
•Interface with synchronous DRAM (SDRAM/Mobile LPSDR SDRAM) memories
•8-, 16-, 32-bit data bus width
•Independent Chip Select control for each memory bank
•Independent configuration for each memory bank
•Write FIFO
•Read FIFO for SDRAM controller
•The maximum FMC_CLK/FMC_SDCLK frequency for synchronous accesses is
HCLK/2
LCD parallel interface
The FMC can be configured to interface seamlessly with most graphic LCD controllers. It
supports the Intel 8080 and Motorola 6800 modes, and is flexible enough to adapt to
specific LCD interfaces. This LCD parallel interface capability makes it easy to build cost-
effective graphic applications using LCD modules with embedded controllers or high
performance solutions using external controllers with dedicated acceleration.
3.9 Quad-SPI memory interface (QUADSPI)
All the devices embed a Quad-SPI memory interface, which is a specialized communication
interface targetting Single, Dual or Quad-SPI Flash memories. It can work in:
•Direct mode through registers
•External Flash status register polling mode
•Memory mapped mode.
Up to 256 Mbytes of external Flash are memory mapped, supporting 8, 16 and 32-bit
access. The code execution is supported.
The opcode and the frame format are fully programmable. The communication can be either
in Single Data Rate or Dual Data Rate.
DS11853 Rev 7 27/230
STM32F722xx STM32F723xx Functional overview
49
3.10 Nested vectored interrupt controller (NVIC)
The devices embed a nested vectored interrupt controller able to manage 16 priority levels,
and handle up to 110 maskable interrupt channels plus the 16 interrupt lines of the Cortex®-
M7 with FPU core.
•Closely coupled NVIC gives low-latency interrupt processing
•Interrupt entry vector table address passed directly to the core
•Allows early processing of interrupts
•Processing of late arriving, higher-priority interrupts
•Support tail chaining
•Processor state automatically saved
•Interrupt entry restored on interrupt exit with no instruction overhead
This hardware block provides flexible interrupt management features with a minimum
interrupt latency.
3.11 External interrupt/event controller (EXTI)
The external interrupt/event controller consists of 24 edge-detector lines used to generate
interrupt/event requests. Each line can be independently configured to select the trigger
event (rising edge, falling edge, both) and can be masked independently. A pending register
maintains the status of the interrupt requests. The EXTI can detect an external line with a
pulse width shorter than the Internal APB2 clock period. Up to 140 GPIOs in the
STM32F722xx devices (138 GPIOs in the STM32F723xx devices) can be connected to the
16 external interrupt lines.
3.12 Clocks and startup
On reset the 16 MHz internal HSI RC oscillator is selected as the default CPU clock. The
16 MHz internal RC oscillator is factory-trimmed to offer 1% accuracy. The application can
then select as system clock either the RC oscillator or an external 4-26 MHz clock source.
This clock can be monitored for failure. If a failure is detected, the system automatically
switches back to the internal RC oscillator and a software interrupt is generated (if enabled).
This clock source is input to a PLL thus allowing to increase the frequency up to 216 MHz.
Similarly, a full interrupt management of the PLL clock entry is available when necessary
(for example if an indirectly used external oscillator fails).
Several prescalers allow the configuration of the two AHB buses, the high-speed APB
(APB2) and the low-speed APB (APB1) domains. The maximum frequency of the two AHB
buses is 216 MHz while the maximum frequency of the high-speed APB domains is
108 MHz. The maximum allowed frequency of the low-speed APB domain is 54 MHz.
The devices embed two dedicated PLLs (PLLI2S and PLLSAI) which allow to achieve audio
class performance. In this case, the I2S and SAI master clock can generate all standard
sampling frequencies from 8 kHz to 192 kHz.
The STM32F723xx devices embed two PLLs inside the PHY HS controller: PLL1 and PLL2.
The PLL1 allows to output 60 MHz used as an input for PLL2 which itself allows to generate
the 480 Mbps in the USB OTG High Speed mode.
The PLL1 has as input HSE clock.
Functional overview STM32F722xx STM32F723xx
28/230 DS11853 Rev 7
3.13 Boot modes
At startup, the boot memory space is selected by the BOOT pin and BOOT_ADDx option
bytes, allowing to program any boot memory address from 0x0000 0000 to 0x3FFF FFFF
which includes:
•All Flash address space mapped on ITCM or AXIM interface
•All RAM address space: ITCM, DTCM RAMs and SRAMs mapped on AXIM interface
•The System memory bootloader
The boot loader is located in system memory. It is used to reprogram the Flash memory
through a serial interface.
3.14 Power supply schemes
•VDD = 1.7 to 3.6 V: external power supply for I/Os and the internal regulator (when
enabled), provided externally through VDD pins.
•VSSA, VDDA = 1.7 to 3.6 V: external analog power supplies for ADC, DAC, Reset
blocks, RCs and PLL. VDDA and VSSA must be connected to VDD and VSS, respectively.
•VBAT = 1.65 to 3.6 V: power supply for RTC, external clock 32 kHz oscillator and
backup registers (through power switch) when VDD is not present.
Note: The VDD/VDDA minimum value of 1.7 V is obtained when the internal reset is OFF (refer to
Section 3.15.2: Internal reset OFF). Refer to Table 3: Voltage regulator configuration mode
versus device operating mode to identify the packages supporting this option.
•The VDDSDMMC can be connected either to VDD or an external independent power
supply (1.8 to 3.6V) for the SDMMC2 pins (clock, command, and 4-bit data). For
example, when the device is powered at 1.8V, an independent power supply 2.7V can
be connected to VDDSDMMC.When the VDDSDMMC is connected to a separated power
supply, it is independent from VDD or VDDA but it must be the last supply to be provided
and the first to disappear. The following conditions VDDSDMMC must be respected:
– During the power-on phase (VDD < VDD_MIN), VDDSDMMC should be always lower
than VDD
– During the power-down phase (VDD < VDD_MIN), VDDSDMMC should be always
lower than VDD
–The V
DDSDMMC rising and falling time rate specifications must be respected
– In the operating mode phase, VDDSDMMC could be lower or higher than VDD:
All associated GPIOs powered by VDDSDMMC are operating between
VDDSDMMC_MIN and VDDSDMMC_MAX.
•The VDDUSB can be connected either to VDD or an external independent power supply
(3.0 to 3.6V) for USB transceivers (refer to Figure 8 and Figure 9). For example, when
the device is powered at 1.8V, an independent power supply 3.3V can be connected to
the VDDUSB. When the VDDUSB is connected to a separated power supply, it is
independent from VDD or VDDA but it must be the last supply to be provided and the first
to disappear. The following conditions VDDUSB must be respected:
– During the power-on phase (VDD < VDD_MIN), VDDUSB should be always lower
than VDD
– During the power-down phase (VDD < VDD_MIN), VDDUSB should be always lower
than VDD
VDDUSE DDUSB
DS11853 Rev 7 29/230
STM32F722xx STM32F723xx Functional overview
49
–The V
DDUSB rising and falling time rate specifications must be respected
– In the operating mode phase, VDDUSB could be lower or higher than VDD:
- If the USB (USB OTG_HS/OTG_FS) is used, the associated GPIOs powered by
VDDUSB are operating between VDDUSB_MIN and VDDUSB_MAX.
- The VDDUSB supplies both USB transceiver (USB OTG_HS and USB OTG_FS).
If only one USB transceiver is used in the application, the GPIOs associated to the
other USB transceiver are still supplied by VDDUSB.
- If the USB (USB OTG_HS/OTG_FS) is not used, the associated GPIOs powered
by VDDUSB are operating between VDD_MIN and VDD_MAX.
Figure 8. VDDUSB connected to VDD power supply
Figure 9. VDDUSB connected to external power supply
V
DD_MIN
time
V
DD
= V
DDA
= V
DDUSB
Power-on Power-down
Operating mode
V
DD_MAX
VDD
MS37591V1
MS37590V1
V
DDUSB_MIN
V
DD_MIN
time
V
DDUSB_MAX
USB functional area
V
DD
=V
DDA
USB non
functional
area
V
DDUSB
Power-on Power-down
Operating mode
USB non
functional
area
Functional overview STM32F722xx STM32F723xx
30/230 DS11853 Rev 7
On the STM32F7x3xx devices, the USB OTG HS sub-system uses one or two additional
power supply pins depending on the package:
•The VDD12OTGHS pin is the output of PHY HS regulator (1.2V). An external capacitor
of 2.2 µF must be connected on the VDD12OTGHS pin.
•On the LQFP100 only, a second power pin VDDPHYHS is used to supply the USB
OTG PHY HS and associated GPIOs.The VDDPHYHS follows the same rules provided
for the VDDUSB power pin.
3.15 Power supply supervisor
3.15.1 Internal reset ON
On packages embedding the PDR_ON pin, the power supply supervisor is enabled by
holding PDR_ON high. On the other packages, the power supply supervisor is always
enabled.
The device has an integrated power-on reset (POR)/ power-down reset (PDR) circuitry
coupled with a Brownout reset (BOR) circuitry. At power-on, POR/PDR is always active and
ensures proper operation starting from 1.8 V. After the 1.8 V POR threshold level is
reached, the option byte loading process starts, either to confirm or modify default BOR
thresholds, or to disable BOR permanently. Three BOR thresholds are available through
option bytes. The device remains in reset mode when VDD is below a specified threshold,
VPOR/PDR or VBOR, without the need for an external reset circuit.
The device also features an embedded programmable voltage detector (PVD) that monitors
the VDD/VDDA power supply and compares it to the VPVD threshold. An interrupt can be
generated when VDD/VDDA drops below the VPVD threshold and/or when VDD/VDDA is
higher than the VPVD threshold. The interrupt service routine can then generate a warning
message and/or put the MCU into a safe state. The PVD is enabled by software.
3.15.2 Internal reset OFF
This feature is available only on packages featuring the PDR_ON pin. The internal power-on
reset (POR) / power-down reset (PDR) circuitry is disabled through the PDR_ON pin.
An external power supply supervisor should monitor VDD and NRST and should maintain
the device in reset mode as long as VDD is below a specified threshold. PDR_ON should be
connected to VSS. Refer to Figure 10: Power supply supervisor interconnection with internal
reset OFF.
DS11853 Rev 7 31/230
STM32F722xx STM32F723xx Functional overview
49
Figure 10. Power supply supervisor interconnection with internal reset OFF
The VDD specified threshold, below which the device must be maintained under reset, is
1.7 V (see Figure 11).
A comprehensive set of power-saving mode allows to design low-power applications.
When the internal reset is OFF, the following integrated features are no more supported:
•The integrated power-on reset (POR) / power-down reset (PDR) circuitry is disabled
•The brownout reset (BOR) circuitry must be disabled
•The embedded programmable voltage detector (PVD) is disabled
•VBAT functionality is no more available and VBAT pin should be connected to VDD.
All packages, except for the LQFP100, allow to disable the internal reset through the
PDR_ON signal when connected to VSS.
Figure 11. PDR_ON control with internal reset OFF
MS31383V4
NRST
VDD
PDR_ON
External VDD power supply supervisor
Ext. reset controller active when
VDD < 1.7 V
VDD
Application reset
signal
VSS
Functional overview STM32F722xx STM32F723xx
32/230 DS11853 Rev 7
3.16 Voltage regulator
The regulator has four operating modes:
•Regulator ON
– Main regulator mode (MR)
– Low power regulator (LPR)
– Power-down
•Regulator OFF
3.16.1 Regulator ON
On packages embedding the BYPASS_REG pin, the regulator is enabled by holding
BYPASS_REG low. On all other packages, the regulator is always enabled.
There are three power modes configured by software when the regulator is ON:
•MR mode used in Run/sleep modes or in Stop modes
– In Run/Sleep modes
The MR mode is used either in the normal mode (default mode) or the over-drive
mode (enabled by software). A different voltage scaling is provided to reach the
best compromise between maximum frequency and dynamic power consumption.
The over-drive mode allows operating at a higher frequency than the normal mode
for a given voltage scaling.
– In Stop modes
The MR can be configured in two ways during stop mode:
MR operates in normal mode (default mode of MR in stop mode)
MR operates in under-drive mode (reduced leakage mode).
•LPR is used in the Stop modes:
The LP regulator mode is configured by software when entering Stop mode.
Like the MR mode, the LPR can be configured in two ways during stop mode:
– LPR operates in normal mode (default mode when LPR is ON)
– LPR operates in under-drive mode (reduced leakage mode).
•Power-down is used in Standby mode.
The Power-down mode is activated only when entering in Standby mode. The regulator
output is in high impedance and the kernel circuitry is powered down, inducing zero
consumption. The contents of the registers and SRAM are lost.
Refer to Table 3 for a summary of voltage regulator modes versus device operating modes.
The VCAP_1 and VCAP_2 pins must be connected to 2*2.2 µF, ESR < 2 Ω (or 1*4.7 µF, ESR
between 0.1 Ω and 0.2 Ω if only the VCAP_1 pin is provided (on LQFP64 package)).
All the packages have the regulator ON feature.
DS11853 Rev 7 33/230
STM32F722xx STM32F723xx Functional overview
49
3.16.2 Regulator OFF
This feature is available only on packages featuring the BYPASS_REG pin. The regulator is
disabled by holding BYPASS_REG high. The regulator OFF mode allows to supply
externally a V12 voltage source through VCAP_1 and VCAP_2 pins.
Since the internal voltage scaling is not managed internally, the external voltage value must
be aligned with the targeted maximum frequency.The two 2.2 µF ceramic capacitors should
be replaced by two 100 nF decoupling capacitors.
When the regulator is OFF, there is no more internal monitoring on V12. An external power
supply supervisor should be used to monitor the V12 of the logic power domain. The PA0 pin
should be used for this purpose, and act as power-on reset on V12 power domain.
In regulator OFF mode, the following features are no more supported:
•PA0 cannot be used as a GPIO pin since it allows to reset a part of the V12 logic power
domain which is not reset by the NRST pin.
•As long as PA0 is kept low, the debug mode cannot be used under power-on reset. As
a consequence, PA0 and NRST pins must be managed separately if the debug
connection under reset or pre-reset is required.
•The over-drive and under-drive modes are not available.
•The Standby mode is not available.
Table 3. Voltage regulator configuration mode versus device operating mode(1)
1. ‘-’ means that the corresponding configuration is not available.
Voltage regulator
configuration Run mode Sleep mode Stop mode Standby mode
Normal mode MR MR MR or LPR -
Over-drive
mode(2)
2. The over-drive mode is not available when VDD = 1.7 to 2.1 V.
MR MR - -
Under-drive mode - - MR or LPR -
Power-down
mode ---Yes
Functional overview STM32F722xx STM32F723xx
34/230 DS11853 Rev 7
Figure 12. Regulator OFF
The following conditions must be respected:
•VDD should always be higher than VCAP_1 and VCAP_2 to avoid current injection
between power domains.
•If the time for VCAP_1 and VCAP_2 to reach V12 minimum value is faster than the time for
VDD to reach 1.7 V, then PA0 should be kept low to cover both conditions: until VCAP_1
and VCAP_2 reach V12 minimum value and until VDD reaches 1.7 V (see Figure 13).
•Otherwise, if the time for VCAP_1 and VCAP_2 to reach V12 minimum value is slower
than the time for VDD to reach 1.7 V, then PA0 could be asserted low externally (see
Figure 14).
•If VCAP_1 and VCAP_2 go below V12 minimum value and VDD is higher than 1.7 V, then a
reset must be asserted on PA0 pin.
Note: The minimum value of V12 depends on the maximum frequency targeted in the application.
Note: On the LQFP64 pin package, the VCAP_2 is not available.
ai18498V3
BYPASS_REG
VCAP_1
VCAP_2
PA0
V12
VDD NRST
VDD
Application reset
signal (optional)
External VCAP_1/2 power
supply supervisor
Ext. reset controller active
when VCAP_1/2 < Min V12
V12
CAP 1 CAP 2 CAP 1 CAP 2
DS11853 Rev 7 35/230
STM32F722xx STM32F723xx Functional overview
49
Figure 13. Startup in regulator OFF: slow VDD slope
- power-down reset risen after VCAP_1/VCAP_2 stabilization
1. This figure is valid whatever the internal reset mode (ON or OFF).
Figure 14. Startup in regulator OFF mode: fast VDD slope
- power-down reset risen before VCAP_1/VCAP_2 stabilization
1. This figure is valid whatever the internal reset mode (ON or OFF).
ai18491f
VDD
time
Min V12
PDR = 1.7 V or 1.8 V VCAP_1 / VCAP_2
V12
NRST
time
V
DD
time
Min V
12
V
CAP_1
/ V
CAP_2
V
12
PA0 asserted externally
NRST
time
ai18492e
PDR = 1.7 V or 1.8 V
Functional overview STM32F722xx STM32F723xx
36/230 DS11853 Rev 7
3.16.3 Regulator ON/OFF and internal reset ON/OFF availability
3.17 Real-time clock (RTC), backup SRAM and backup registers
The RTC is an independent BCD timer/counter. It supports the following features:
•Calendar with subsecond, seconds, minutes, hours (12 or 24 format), week day, date,
month, year, in BCD (binary-coded decimal) format.
•Automatic correction for 28, 29 (leap year), 30, and 31 days of the month.
•Two programmable alarms.
•On-the-fly correction from 1 to 32767 RTC clock pulses. This can be used to
synchronize it with a master clock.
•Reference clock detection: a more precise second source clock (50 or 60 Hz) can be
used to enhance the calendar precision.
•Digital calibration circuit with 0.95 ppm resolution, to compensate for quartz crystal
inaccuracy.
•Three anti-tamper detection pins with programmable filter.
•Timestamp feature which can be used to save the calendar content. This function can
be triggered by an event on the timestamp pin, or by a tamper event, or by a switch to
VBAT mode.
•17-bit auto-reload wakeup timer (WUT) for periodic events with programmable
resolution and period.
The RTC and the 32 backup registers are supplied through a switch that takes power either
from the VDD supply when present or from the VBAT pin.
The backup registers are 32-bit registers used to store 128 bytes of user application data
when VDD power is not present. They are not reset by a system or power reset, or when the
device wakes up from Standby mode.
The RTC clock sources can be:
•A 32.768 kHz external crystal (LSE)
•An external resonator or oscillator(LSE)
•The internal low power RC oscillator (LSI, with typical frequency of 32 kHz)
•The high-speed external clock (HSE) divided by 32
The RTC is functional in VBAT mode and in all low-power modes when it is clocked by the
LSE. When clocked by the LSI, the RTC is not functional in VBAT mode, but is functional in
all low-power modes.
Table 4. Regulator ON/OFF and internal reset ON/OFF availability
Package Regulator ON Regulator OFF Internal reset ON Internal reset OFF
LQFP64,
LQFP100 Yes No
Yes No
LQFP144
Yes
PDR_ON set to VDD
Yes
PDR_ON set to VSS
LQFP176,
UFBGA144,
UFBGA176
Yes
BYPASS_REG set
to VSS
Yes
BYPASS_REG set
to VDD
DS11853 Rev 7 37/230
STM32F722xx STM32F723xx Functional overview
49
All the RTC events (Alarm, WakeUp Timer, Timestamp or Tamper) can generate an interrupt
and wakeup the device from the low-power modes.
3.18 Low-power modes
The devices support three low-power modes to achieve the best compromise between low
power consumption, short startup time and available wakeup sources:
•Sleep mode
In Sleep mode, only the CPU is stopped. All peripherals continue to operate and can
wake up the CPU when an interrupt/event occurs.
•Stop mode
The Stop mode achieves the lowest power consumption while retaining the contents of
SRAM and registers. All clocks in the 1.2 V domain are stopped, the PLL, the HSI RC
and the HSE crystal oscillators are disabled.
The voltage regulator can be put either in main regulator mode (MR) or in low-power
mode (LPR). Both modes can be configured as follows (see Table 5: Voltage regulator
modes in stop mode):
– Normal mode (default mode when MR or LPR is enabled)
– Under-drive mode.
The device can be woken up from the Stop mode by any of the EXTI line (the EXTI line
source can be one of the 16 external lines, the PVD output, the RTC alarm / wakeup /
tamper / time stamp events, the USB OTG FS/HS wakeup and the LPTIM1
asynchronous interrupt).
•Standby mode
The Standby mode is used to achieve the lowest power consumption. The internal
voltage regulator is switched off so that the entire 1.2 V domain is powered off. The
PLL, the HSI RC and the HSE crystal oscillators are also switched off. After entering
Standby mode, the SRAM and register contents are lost except for registers in the
backup domain and the backup SRAM when selected.
The device exits the Standby mode when an external reset (NRST pin), an IWDG reset,
a rising or falling edge on one of the 6 WKUP pins (PA0, PA2, PC1, PC13, PI8, PI11),
or an RTC alarm / wakeup / tamper /time stamp event occurs.
The Standby mode is not supported when the embedded voltage regulator is bypassed
and the 1.2 V domain is controlled by an external power.
Table 5. Voltage regulator modes in stop mode
Voltage regulator
configuration Main regulator (MR) Low-power regulator (LPR)
Normal mode MR ON LPR ON
Under-drive mode MR in under-drive mode LPR in under-drive mode
Functional overview STM32F722xx STM32F723xx
38/230 DS11853 Rev 7
3.19 VBAT operation
The VBAT pin allows to power the device VBAT domain from an external battery, an external
supercapacitor, or from VDD when no external battery and an external supercapacitor are
present.
The VBAT operation is activated when VDD is not present.
The VBAT pin supplies the RTC, the backup registers and the backup SRAM.
Note: When the microcontroller is supplied from VBAT, external interrupts and RTC alarm/events
do not exit it from VBAT operation.
When the PDR_ON pin is connected to VSS (Internal Reset OFF), the VBAT functionality is
no more available and the VBAT pin should be connected to VDD.
3.20 Timers and watchdogs
The devices include two advanced-control timers, eight general-purpose timers, two basic
timers and two watchdog timers.
All timer counters can be frozen in debug mode.
Table 6 compares the features of the advanced-control, general-purpose and basic timers.
DS11853 Rev 7 39/230
STM32F722xx STM32F723xx Functional overview
49
Table 6. Timer feature comparison
Timer
type Timer Counter
resolution
Counter
type
Prescaler
factor
DMA
request
generation
Capture/
compare
channels
Complem
entary
output
Max
interface
clock
(MHz)
Max
timer
clock
(MHz)(1)
Advanced
-control
TIM1,
TIM8 16-bit
Up,
Down,
Up/down
Any
integer
between 1
and 65536
Yes 4 Yes 108 216
General
purpose
TIM2,
TIM5 32-bit
Up,
Down,
Up/down
Any
integer
between 1
and 65536
Yes 4 No 54 108/216
TIM3,
TIM4 16-bit
Up,
Down,
Up/down
Any
integer
between 1
and 65536
Yes 4 No 54 108/216
TIM9 16-bit Up
Any
integer
between 1
and 65536
No 2 No 108 216
TIM10,
TIM11 16-bit Up
Any
integer
between 1
and 65536
No 1 No 108 216
TIM12 16-bit Up
Any
integer
between 1
and 65536
No 2 No 54 108/216
TIM13,
TIM14 16-bit Up
Any
integer
between 1
and 65536
No 1 No 54 108/216
Basic TIM6,
TIM7 16-bit Up
Any
integer
between 1
and 65536
Yes 0 No 54 108/216
1. The maximum timer clock is either 108 or 216 MHz depending on TIMPRE bit configuration in the RCC_DCKCFGR
register.
Functional overview STM32F722xx STM32F723xx
40/230 DS11853 Rev 7
3.20.1 Advanced-control timers (TIM1, TIM8)
The advanced-control timers (TIM1, TIM8) can be seen as three-phase PWM generators
multiplexed on 6 channels. They have complementary PWM outputs with programmable
inserted dead times. They can also be considered as complete general-purpose timers.
Their 4 independent channels can be used for:
•Input capture
•Output compare
•PWM generation (edge- or center-aligned modes)
•One-pulse mode output
If configured as standard 16-bit timers, they have the same features as the general-purpose
TIMx timers. If configured as 16-bit PWM generators, they have full modulation capability (0-
100%).
The advanced-control timer can work together with the TIMx timers via the Timer Link
feature for synchronization or event chaining.
The TIM1 and TIM8 support independent DMA request generation.
3.20.2 General-purpose timers (TIMx)
There are ten synchronizable general-purpose timers embedded in the STM32F722xx and
STM32F723xx devices (see Table 6 for differences).
•TIM2, TIM3, TIM4, TIM5
The STM32F722xx and STM32F723xx include 4 full-featured general-purpose timers:
TIM2, TIM5, TIM3, and TIM4.The TIM2 and TIM5 timers are based on a 32-bit auto-
reload up/downcounter and a 16-bit prescaler. The TIM3 and TIM4 timers are based on
a 16-bit auto-reload up/downcounter and a 16-bit prescaler. They all feature 4
independent channels for input capture/output compare, PWM or one-pulse mode
output. This gives up to 16 input capture/output compare/PWMs on the largest
packages.
The TIM2, TIM3, TIM4, TIM5 general-purpose timers can work together, or with the
other general-purpose timers and the advanced-control timers TIM1 and TIM8 via the
Timer Link feature for synchronization or event chaining.
Any of these general-purpose timers can be used to generate PWM outputs.
TIM2, TIM3, TIM4, TIM5 all have independent DMA request generation. They are
capable of handling quadrature (incremental) encoder signals and the digital outputs
from 1 to 4 hall-effect sensors.
•TIM9, TIM10, TIM11, TIM12, TIM13, and TIM14
These timers are based on a 16-bit auto-reload upcounter and a 16-bit prescaler.
TIM10, TIM11, TIM13, and TIM14 feature one independent channel, whereas TIM9
and TIM12 have two independent channels for input capture/output compare, PWM or
one-pulse mode output. They can be synchronized with the TIM2, TIM3, TIM4, TIM5
full-featured general-purpose timers. They can also be used as simple time bases.
3.20.3 Basic timers TIM6 and TIM7
These timers are mainly used for the DAC trigger and waveform generation. They can also
be used as a generic 16-bit time base.
The TIM6 and TIM7 support independent DMA request generation.
DS11853 Rev 7 41/230
STM32F722xx STM32F723xx Functional overview
49
3.20.4 Low-power timer (LPTIM1)
The low-power timer has an independent clock and is running also in Stop mode if it is
clocked by LSE, LSI or an external clock. It is able to wakeup the devices from Stop mode.
This low-power timer supports the following features:
•16-bit up counter with 16-bit autoreload register
•16-bit compare register
•Configurable output: pulse, PWM
•Continuous / one-shot mode
•Selectable software / hardware input trigger
•Selectable clock source:
•Internal clock source: LSE, LSI, HSI or APB clock
•External clock source over LPTIM input (working even with no internal clock source
running, used by the Pulse Counter Application)
•Programmable digital glitch filter
•Encoder mode
3.20.5 Independent watchdog
The independent watchdog is based on a 12-bit downcounter and 8-bit prescaler. It is
clocked from an independent 32 kHz internal RC and as it operates independently from the
main clock, it can operate in Stop and Standby modes. It can be used either as a watchdog
to reset the device when a problem occurs, or as a free-running timer for application timeout
management. It is hardware- or software-configurable through the option bytes.
3.20.6 Window watchdog
The window watchdog is based on a 7-bit downcounter that can be set as free-running. It
can be used as a watchdog to reset the device when a problem occurs. It is clocked from
the main clock. It has an early warning interrupt capability and the counter can be frozen in
debug mode.
3.20.7 SysTick timer
This timer is dedicated to real-time operating systems, but could also be used as a standard
downcounter. It features:
•A 24-bit downcounter
•Autoreload capability
•Maskable system interrupt generation when the counter reaches 0
•Programmable clock source
Functional overview STM32F722xx STM32F723xx
42/230 DS11853 Rev 7
3.21 Inter-integrated circuit interface (I2C)
The devices embed 3 I2Cs. Refer to Table 7: I2C implementation for the features
implementation.
The I2C bus interface handles communications between the microcontroller and the serial
I2C bus. It controls all I2C bus-specific sequencing, protocol, arbitration and timing.
The I2C peripheral supports:
•I2C-bus specification and user manual rev. 5 compatibility:
– Slave and master modes, multimaster capability
– Standard-mode (Sm), with a bitrate up to 100 kbit/s
– Fast-mode (Fm), with a bitrate up to 400 kbit/s
– Fast-mode Plus (Fm+), with a bitrate up to 1 Mbit/s and 20 mA output drive I/Os
– 7-bit and 10-bit addressing mode, multiple 7-bit slave addresses
– Programmable setup and hold times
– Optional clock stretching
•System Management Bus (SMBus) specification rev 2.0 compatibility:
– Hardware PEC (Packet Error Checking) generation and verification with ACK
control
– Address resolution protocol (ARP) support
– SMBus alert
•Power System Management Protocol (PMBusTM) specification rev 1.1 compatibility
•Independent clock: a choice of independent clock sources allowing the I2C
communication speed to be independent from the PCLK reprogramming.
•Programmable analog and digital noise filters
•1-byte buffer with DMA capability
Table 7. I2C implementation
I2C features(1)
1. X: supported.
I2C1 I2C2 I2C3
Standard-mode (up to 100 kbit/s) X X X
Fast-mode (up to 400 kbit/s) X X X
Fast-mode Plus with 20 mA output drive I/Os (up to 1 Mbit/s) X X X
Programmable analog and digital noise filters X X X
SMBus/PMBus hardware support X X X
Independent clock X X X
DS11853 Rev 7 43/230
STM32F722xx STM32F723xx Functional overview
49
3.22 Universal synchronous/asynchronous receiver transmitters
(USART)
The devices embed USARTs. Refer to Table 8: USART implementation for the features
implementation.
The universal synchronous asynchronous receiver transmitter (USART) offers a flexible
means of full-duplex data exchange with external equipment requiring an industry standard
NRZ asynchronous serial data format.
The USART peripheral supports:
•Full-duplex asynchronous communications
•Configurable oversampling method by 16 or 8 to give flexibility between speed and
clock tolerance
•Dual clock domain allowing convenient baud rate programming independent from the
PCLK reprogramming
•A common programmable transmit and receive baud rate of up to 27 Mbit/s when
USART clock source is system clock frequency (max is 216 MHz) and oversampling by
8 is used.
•Auto baud rate detection
•Programmable data word length (7 or 8 or 9 bits) word length
•Programmable data order with MSB-first or LSB-first shifting
•Progarmmable parity (odd, even, no parity)
•Configurable stop bits (1 or 1.5 or 2 stop bits)
•Synchronous mode and clock output for synchronous communications
•Single-wire half-duplex communications
•Separate signal polarity control for transmission and reception
•Swappable Tx/Rx pin configuration
•Hardware flow control for modem and RS-485 transceiver
•Multiprocessor communications
•LIN master synchronous break send capability and LIN slave break detection capability
•IrDA SIR encoder decoder supporting 3/16 bit duration for normal mode
•Smartcard mode ( T=0 and T=1 asynchronous protocols for Smartcards as defined in
the ISO/IEC 7816-3 standard)
•Support for Modbus communication
Table 8 summarizes the implementation of all U(S)ARTs instances
Table 8. USART implementation
features(1) USART1/2/3/6 UART4/5/7/8
Data Length 7, 8 and 9 bits
Hardware flow control for modem X X
Continuous communication using DMA X X
Multiprocessor communication X X
Synchronous mode X -
Functional overview STM32F722xx STM32F723xx
44/230 DS11853 Rev 7
3.23 Serial peripheral interface (SPI)/inter- integrated sound
interfaces (I2S)
The devices feature up to five SPIs in slave and master modes in full-duplex and simplex
communication modes. SPI1, SPI4, and SPI5 can communicate at up to 50 Mbit/s, SPI2
and SPI3 can communicate at up to 25 Mbit/s. The 3-bit prescaler gives 8 master mode
frequencies and the frame is configurable from 4 to 16 bits. The SPI interfaces support the
NSS pulse mode, TI mode and Hardware CRC calculation. All the SPIs can be served by
the DMA controller.
Three standard I2S interfaces (multiplexed with SPI1, SPI2 and SPI3) are available. They
can be operated in master or slave mode, in simplex communication modes, and can be
configured to operate with a 16-/32-bit resolution as an input or output channel. Audio
sampling frequencies from 8 kHz up to 192 kHz are supported. When either or both of the
I2S interfaces is/are configured in master mode, the master clock can be output to the
external DAC/CODEC at 256 times the sampling frequency.
All I2Sx can be served by the DMA controller.
3.24 Serial audio interface (SAI)
The devices embed two serial audio interfaces.
The serial audio interface is based on two independent audio subblocks which can operate
as transmitter or receiver with their FIFO. Many audio protocols are supported by each
block: I2S standards, LSB or MSB-justified, PCM/DSP, TDM, AC’97 and SPDIF output,
supporting audio sampling frequencies from 8 kHz up to 192 kHz. Both subblocks can be
configured in master or in slave mode.
In master mode, the master clock can be output to the external DAC/CODEC at 256 times of
the sampling frequency.
The two sub-blocks can be configured in synchronous mode when full-duplex mode is
required.
Smartcard mode X -
Single-wire half-duplex communication X X
IrDA SIR ENDEC block X X
LIN mode X X
Dual clock domain X X
Receiver timeout interrupt X X
Modbus communication X X
Auto baud rate detection X X
Driver Enable X X
1. X: supported.
Table 8. USART implementation (continued)
features(1) USART1/2/3/6 UART4/5/7/8
DS11853 Rev 7 45/230
STM32F722xx STM32F723xx Functional overview
49
SAI1 and SAI2 can be served by the DMA controller
3.25 Audio PLL (PLLI2S)
The devices feature an additional dedicated PLL for audio I2S and SAI applications. It allows
to achieve an error-free I2S sampling clock accuracy without compromising on the CPU
performance, while using USB peripherals.
The PLLI2S configuration can be modified to manage an I2S/SAI sample rate change
without disabling the main PLL (PLL) used for CPU and USB interfaces.
The audio PLL can be programmed with very low error to obtain sampling rates ranging
from 8 KHz to 192 KHz.
In addition to the audio PLL, a master clock input pin can be used to synchronize the
I2S/SAI flow with an external PLL (or Codec output).
3.26 Audio PLL (PLLSAI)
An additional PLL dedicated to audio is used for the SAI1 peripheral in case the PLLI2S is
programmed to achieve another audio sampling frequency (49.152 MHz or 11.2896 MHz)
and the audio application requires both sampling frequencies simultaneously.
3.27 SD/SDIO/MMC card host interface (SDMMC)
SDMMC host interfaces are available, that support MultiMediaCard System Specification
Version 4.2 in three different databus modes: 1-bit (default), 4-bit and 8-bit.
The interface allows data transfer at up to 50 MHz, and is compliant with the SD Memory
Card Specification Version 2.0.
The SDMMC Card Specification Version 2.0 is also supported with two different databus
modes: 1-bit (default) and 4-bit.
The current version supports only one SD/SDMMC/MMC4.2 card at any one time and a
stack of MMC4.1 or previous.
The SDMMC can be served by the DMA controller
3.28 Controller area network (bxCAN)
The CAN is compliant with the 2.0A and B (active) specifications with a bit rate up to 1
Mbit/s. It can receive and transmit standard frames with 11-bit identifiers as well as
extended frames with 29-bit identifiers. The CAN has three transmit mailboxes, two receive
FIFOs with 3 stages and 28 shared scalable filter banks (all of them can be used even if one
CAN is used). 256 bytes of SRAM are allocated to the CAN.
Functional overview STM32F722xx STM32F723xx
46/230 DS11853 Rev 7
3.29 Universal serial bus on-the-go full-speed (OTG_FS)
The devices embed an USB OTG full-speed device/host/OTG peripheral with integrated
transceivers. The USB OTG FS peripheral is compliant with the USB 2.0 specification and
with the OTG 2.0 specification. It has software-configurable endpoint setting and supports
suspend/resume. The USB OTG controller requires a dedicated 48 MHz clock that is
generated by a PLL connected to the HSE oscillator.
The major features are:
•Combined Rx and Tx FIFO size of 1.28 Kbytes with dynamic FIFO sizing
•Supports the session request protocol (SRP) and host negotiation protocol (HNP)
•1 bidirectional control endpoint + 5 IN endpoints + 5 OUT endpoints
•12 host channels with periodic OUT support
•Software configurable to OTG1.3 and OTG2.0 modes of operation
•USB 2.0 LPM (Link Power Management) support
•Internal FS OTG PHY support
•HNP/SNP/IP inside (no need for any external resistor)
•BCD support
For the OTG/Host modes, a power switch is needed in case bus-powered devices are
connected
3.30 Universal serial bus on-the-go high-speed (OTG_HS)
The devices embed an USB OTG high-speed (up to 480 Mbit/s) device/host/OTG
peripheral. The USB OTG HS supports both full-speed and high-speed operations. It
integrates the transceivers for full-speed operation (12 Mbit/s).
The STM32F722xx devices feature a UTMI low-pin interface (ULPI) for high-speed
operation (480 Mbit/s). When using the USB OTG HS in HS mode, an external PHY device
connected to the ULPI is required.
The STM32F723xx devices feature an integrated PHY HS.
The USB OTG HS peripheral is compliant with the USB 2.0 specification and with the OTG
2.0 specification. It has a software-configurable endpoint setting and supports
suspend/resume. The USB OTG controller requires a dedicated 48 MHz clock that is
generated by a PLL connected to the HSE oscillator.
The major features are:
•Combined Rx and Tx FIFO size of 4 Kbytes with dynamic FIFO sizing
•Supports the session request protocol (SRP) and host negotiation protocol (HNP)
•8 bidirectional endpoints
•16 host channels with periodic OUT support
•Software configurable to OTG1.3 and OTG2.0 modes of operation
•USB 2.0 LPM (Link Power Management) support
•For the STM32F722xx devices: External HS or HS OTG operation supporting ULPI in
SDR mode. The OTG PHY is connected to the microcontroller ULPI port through 12
signals. It can be clocked using the 60 MHz output.
•For the STM32F723xx devices: Internal HS OTG PHY support.
DS11853 Rev 7 47/230
STM32F722xx STM32F723xx Functional overview
49
•Internal USB DMA
•HNP/SNP/IP inside (no need for any external resistor)
•For OTG/Host modes, a power switch is needed in case bus-powered devices are
connected
Universal Serial Bus controller on-the-go High-Speed PHY controller
(USBPHYC) only on STM32F723xx devices.
The USB HS PHY controller:
– Sets the PHYPLL1/2 values for the PHY HS
– Sets the other controls on the PHY HS
– Controls and monitors the USB PHY’s LDO
3.31 Random number generator (RNG)
All the devices embed an RNG that delivers 32-bit random numbers generated by an
integrated analog circuit.
3.32 General-purpose input/outputs (GPIOs)
Each of the GPIO pins can be configured by software as output (push-pull or open-drain,
with or without pull-up or pull-down), as input (floating, with or without pull-up or pull-down)
or as peripheral alternate function. Most of the GPIO pins are shared with digital or analog
alternate functions. All GPIOs are high-current-capable and have speed selection to better
manage internal noise, power consumption and electromagnetic emission.
The I/O configuration can be locked if needed by following a specific sequence in order to
avoid spurious writing to the I/Os registers.
A Fast I/O handling allows a maximum I/O toggling up to 108 MHz.
3.33 Analog-to-digital converters (ADCs)
Three 12-bit analog-to-digital converters are embedded and each ADC shares up to 16
external channels, performing conversions in the single-shot or scan mode. In the scan
mode, an automatic conversion is performed on a selected group of analog inputs.
Additional logic functions embedded in the ADC interface allow:
•Simultaneous sample and hold
•Interleaved sample and hold
The ADC can be served by the DMA controller. An analog watchdog feature allows very
precise monitoring of the converted voltage of one, some or all selected channels. An
interrupt is generated when the converted voltage is outside the programmed thresholds.
To synchronize A/D conversion and timers, the ADCs could be triggered by any of TIM1,
TIM2, TIM3, TIM4, TIM5, or TIM8 timer.
Functional overview STM32F722xx STM32F723xx
48/230 DS11853 Rev 7
3.34 Temperature sensor
The temperature sensor has to generate a voltage that varies linearly with the temperature.
The conversion range is between 1.7 V and 3.6 V. The temperature sensor is internally
connected to the same input channel as VBAT, ADC1_IN18, which is used to convert the
sensor output voltage into a digital value. When the temperature sensor and VBAT
conversion are enabled at the same time, only VBAT conversion is performed.
As the offset of the temperature sensor varies from chip to chip due to process variation, the
internal temperature sensor is mainly suitable for applications that detect temperature
changes instead of absolute temperatures. If an accurate temperature reading is needed,
then an external temperature sensor part should be used.
3.35 Digital-to-analog converter (DAC)
The two 12-bit buffered DAC channels can be used to convert two digital signals into two
analog voltage signal outputs.
This dual digital Interface supports the following features:
•Two DAC converters: one for each output channel
•8-bit or 12-bit monotonic output
•Left or right data alignment in 12-bit mode
•Synchronized update capability
•Noise-wave generation
•Triangular-wave generation
•Dual DAC channel independent or simultaneous conversions
•DMA capability for each channel
•External triggers for conversion
•Input voltage reference VREF+
Eight DAC trigger inputs are used in the device. The DAC channels are triggered through
the timer update outputs that are also connected to different DMA streams.
3.36 Serial wire JTAG debug port (SWJ-DP)
The Arm SWJ-DP interface is embedded, and is a combined JTAG and serial wire debug
port that enables either a serial wire debug or a JTAG probe to be connected to the target.
The debug is performed using 2 pins only instead of 5 required by the JTAG (JTAG pins
could be re-used as GPIO with alternate function): the JTAG TMS and TCK pins are shared
with SWDIO and SWCLK, respectively, and a specific sequence on the TMS pin is used to
switch between JTAG-DP and SW-DP.
DS11853 Rev 7 49/230
STM32F722xx STM32F723xx Functional overview
49
3.37 Embedded Trace Macrocell™
The Arm Embedded Trace Macrocell provides a greater visibility of the instruction and data
flow inside the CPU core by streaming compressed data at a very high rate from the
STM32F722xx and STM32F723xx device through a small number of ETM pins to an
external hardware trace port analyzer (TPA) device. The TPA is connected to a host
computer using the USB or any other high-speed channel. The real-time instruction and
data flow activity can be recorded and then formatted for display on the host computer that
runs the debugger software. The TPA hardware is commercially available from common
development tool vendors.
The Embedded Trace Macrocell operates with third party debugger software tools.
Pinouts and pin description STM32F722xx STM32F723xx
50/230 DS11853 Rev 7
4 Pinouts and pin description
Figure 15. STM32F722xx LQFP64 pinout
1. The above figure shows the package top view.
64 63 62 61 60 59 58 57 56 55 54 53 52 51 50 49
48
47
46
45
44
43
42
41
40
39
38
37
36
35
34
33
17 18 19 20 21 22 23 24 29 30 31 3225 26 27 28
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
VBAT
PC14-OSC32_IN
PC15-OSC32_OUT
NRST
PC0
PC1
PC2
PC3
VSSA
VDDA
PA0-WKUP
PA1
PA2
VDD
PD2
PC12
PC11
PC10
VDD
VSS
PC8
PC7
PC6
PB12
VSS
PA3
VDD
PC4
PB2
PB10
PH1-OSC_OUT
PH0-OSC_IN
PC13
VSS
PB11
VSS
VDD
LQFP64
MS40455V3
PA13
PA12
PA11
PA10
PA9
PA8
PC9
PB15
PB14
PB13
PA4
PA5
PA6
PA7
PB0
PB1
PB9
PB8
BOOT0
PB7
PB6
PB5
PB4
PB3
PA15
PA14
VCAP_1
DS11853 Rev 7 51/230
STM32F722xx STM32F723xx Pinouts and pin description
99
Figure 16. STM32F722xx LQFP100 pinout
1. The above figure shows the package top view.
100
99
98
97
96
95
94
93
92
91
90
89
88
87
86
85
84
83
82
81
80
79
78
77
76
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
75
74
73
72
71
70
69
68
67
66
65
64
63
62
61
60
59
58
57
56
55
54
53
52
51
PE2
PE3
PE4
PE5
PE6
PC14-OSC32_IN
PC15-OSC32_OUT
VSS
VDD
PH0-OSC_IN
PC0
PC1
PC2
PC3
VSSA
VREF+
VDDA
VDD
VSS
VCAP_2
PC9
PC8
PC7
PC6
VSS
VDD
PA4
PB1
PB2
PE7
PE8
PE9
VCAP_1
VDD
VDD
VSS
PD7
PD6
PD5
PD4
PD3
PD2
PD1
PD0
PC12
PC11
PC10
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40
41
42
43
44
45
46
47
48
49
50
MSv40457V1
LQFP100
PC13
PH1-OSC_OUT
PA0-WKUP
PA1
PA2
PA3
PA5
PA6
PA7
PC4
PB0
PC5
PE13
PE14
PE15
PB10
PB11
PE10
PE12
PE11
VSS
PD12
PD11
PD8
PB15
PB14
PB13
PB12
PD9
PD10
PD13
PD14
PD15
PA9
PA8
PA10
PA11
PA12
PA13
PA15
PA14
PE1
PE0
PB9
PB8
BOOT0
PB7
PB6
PB5
PB4
PB3
VBAT
NRST
Pinouts and pin description STM32F722xx STM32F723xx
52/230 DS11853 Rev 7
Figure 17. STM32F723xx LQFP100 pinout
1. The above figure shows the package top view.
100
99
98
97
96
95
94
93
92
91
90
89
88
87
86
85
84
83
82
81
80
79
78
77
76
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
75
74
73
72
71
70
69
68
67
66
65
64
63
62
61
60
59
58
57
56
55
54
53
52
51
PE2
PE3
PE4
PE5
PE6
PC14-OSC32_IN
PC15-OSC32_OUT
VSS
VDD
PH0-OSC_IN
PC0
PC1
PC2
PC3
VSSA
VREF+
VDDA
VDD
VSS
VCAP_2
PC9
PC8
PC7
PC6
VSS
VDD
PA4
PB1
PB2
PE7
PE8
PE9
VCAP_1
VDD
VDD
VSS
PD7
PD6
PD5
PD4
PD3
PD2
PD1
PD0
PC12
PC11
PC10
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40
41
42
43
44
45
46
47
48
49
50
MSv63474V1
LQFP100
PC13
PH1-OSC_OUT
PA0-WKUP
PA1
PA2
PA3
PA5
PA6
PA7
PC4
PB0
PC5
PE13
PE14
PE15
PB10
PB11
PE10
PE12
PE11
VSS
PD12
PD11
VDD12OTGHS
VDDPHYHS
OTG_HS_REXT
PB13
PB12
PB14
PB15
PD13
PD14
PD15
PA9
PA8
PA10
PA11
PA12
PA13
PA15
PA14
PE1
PE0
PB9
PB8
BOOT0
PB7
PB6
PB5
PB4
PB3
VBAT
NRST
0000000000 0000000000 0000000000 0000000000 0000000000 0000000000 0000000000 0000000000 0000000000 000000600@
DS11853 Rev 7 53/230
STM32F722xx STM32F723xx Pinouts and pin description
99
Figure 18. STM32F723xx WLCSP100 ballout (with OTG PHY HS)
1. The above figure shows the package top view.
MSv42002V2
A
B
C
D
E
F
G
H
J
K
PC3
PA4
PA3
VDD
PA7
7
BOOT0
PB4
PB5
PB6
PE0
PB0
PB1
PE8
PE7
PE9
5
PD5
PD0
PC11
PC12
PD2
PA5
PA6
PC4
PC5
PB2
6
PB3
PD4
PD3
PD6
PD7
PE15
PE11
PE12
PE13
PE14
4
PD1
PA15
PA14
PC7
PE10
PC10
PD13
PD11
PB10
PB11
VCAP_1
VSS
3
VCAP_2
PA9
PA8
PD12
OTG_HS
_REXT
PB13
PB12
VDD
2
VSS
PA12
PA10
PC8
PD15
PD14
VDD12
OTGHS
PB15
PB14
VDD
USB
1
VDD
PA13
PA11
PC9
PC6
PA0
PA1
VSS
PC0
8
VSS
PB7
PB8
PB9
PE5
VDD
PH0
PH1
PC2
VSSA
10
PE3
PE6
VBAT
PC13
PC15
PE2
PE4
PC14
NRST
PC1
VREF+
VDDA
VSS
9
VDD
PE1
PA2
Pinouts and pin description STM32F722xx STM32F723xx
54/230 DS11853 Rev 7
Figure 19. STM32F722xx LQFP144 pinout
1. The above figure shows the package top view.
V
DD
PDR_ON
PE1
PE0
PB9
PB8
BOOT0
PB7
PB6
PB5
PB4
PB3
PG15
V
DD
V
SS
PG14
PG13
PG12
PG11
PG10
PG9
PD7
PD6
V
DDSDMMC
V
SS
PD5
PD4
PD3
PD2
PD1
PD0
PC12
PC11
PC10
PA 15
PA 14
PE2 V
DD
PE3 V
SS
PE4
PE5 PA 13
PE6 PA 12
VBAT PA 11
PC13 PA 10
PC14 PA 9
PC15 PA 8
PF0 PC9
PF1 PC8
PF2 PC7
PF3 PC6
PF4 V
DDUSB
PF5 V
SS
V
SS
PG8
V
DD
PG7
PF6 PG6
PF7 PG5
PF8 PG4
PF9 PG3
PF10 PG2
PH0 PD15
PH1 PD14
NRST V
DD
PC0 V
SS
PC1 PD13
PC2 PD12
PC3 PD11
V
SSA
PD10
V
DD
PD9
V
REF+
PD8
V
DDA
PB15
PA 0 PB14
PA 1 PB13
PA 2 PB12
PA 3
V
SS
V
DD
PA 4
PA 5
PA 6
PA 7
PC4
PC5
PB0
PB1
PB2
PF11
PF12
V
DD
PF13
PF14
PF15
PG0
PG1
PE7
PE8
PE9
V
SS
V
DD
PE10
PE11
PE12
PE13
PE14
PE15
PB10
PB11
V
DD
144
143
142
141
140
139
138
137
136
135
134
133
132
131
130
129
128
127
126
125
124
123
122
121
109
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
108
107
106
105
104
103
102
101
100
99
98
97
96
95
94
93
92
91
90
89
88
87
86
85
84
37
38
39
40
41
42
43
44
45
46
47
48
49
50
51
52
53
54
55
56
57
58
59
60
72
LQFP144
120
119
118
117
116
115
114
113
112
111
110
61
62
63
64
65
66
67
68
69
70
71
26
27
28
29
30
31
32
33
34
35
36
83
82
81
80
79
78
77
76
75
74
73
V
CAP_2
V
SS
MS39132V1
V
CAP_1
EE:EEEEEE:EEEEEEEEEEEEEEEEEEEEEEEEEE
DS11853 Rev 7 55/230
STM32F722xx STM32F723xx Pinouts and pin description
99
Figure 20. STM32F723xx LQFP144 pinout
1. The above figure shows the package top view.
V
DD
PDR_ON
PE1
PE0
PB9
PB8
BOOT0
PB7
PB6
PB5
PB4
PB3
PG15
V
DD
V
SS
PG14
PG13
PG12
PG11
PG10
PG9
PD7
PD6
V
DDSDMMC
V
SS
PD5
PD4
PD3
PD2
PD1
PD0
PC12
PC11
PC10
PA 15
PA 14
PE2 V
DD
PE3 V
SS
PE4
PE5 PA13
PE6 PA12
VBAT PA11
PC13 PA10
PC14 PA 9
PC15 PA 8
PF0 PC9
PF1 PC8
PF2 PC7
PF3 PC6
PF4 V
DDUSB
PF5 V
SS
V
SS
PG8
V
DD
PG5
PF6 PG4
PF7 PG3
PF8 PG2
PF9 PD15
PF10 PD14
PH0
PH1
NRST
V
DD
PC0
V
SS
PC1
PD13
PC2
PD12
PC3
PD11
V
SSA
PD10
V
DD
V
REF+
V
DDA
PB15
PA 0
PB14
PA 1 PB13
PA 2 PB12
PA 3
V
SS
V
DD
PA 4
PA 5
PA 6
PA 7
PC4
PC5
PB0
PB1
PB2
PF11
PF12
V
DD
PF13
PF14
PF15
PG0
PG1
PE7
PE8
PE9
V
SS
V
DD
PE10
PE11
PE12
PE13
PE14
PE15
PB10
PB11
V
DD
144
143
142
141
140
139
138
137
136
135
134
133
132
131
130
129
128
127
126
125
124
123
122
121
109
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
108
107
106
105
104
103
102
101
100
99
98
97
96
95
94
93
92
91
90
89
88
87
86
85
84
37
38
39
40
41
42
43
44
45
46
47
48
49
50
51
52
53
54
55
56
57
58
59
60
72
LQFP144
with HS PHY
120
119
118
117
116
115
114
113
112
111
110
61
62
63
64
65
66
67
68
69
70
71
26
27
28
29
30
31
32
33
34
35
36
83
82
81
80
79
78
77
76
75
74
73
V
CAP_2
V
SS
MS41014V1
V
CAP_1
PD9
PD8
VDD12OTGHS
OTG_HS_REXT
Pinouts and pin description STM32F722xx STM32F723xx
56/230 DS11853 Rev 7
Figure 21. STM32F723xx UFBGA144 ballout (with OTG PHY HS)
1. The above figure shows the package top view.
MSv42000V1
PC13 PE3 PE2 PE1 PE0 PB4 PB3 PD6 PD7 PA15 PA14 PA13
123456789101112
A
B
C
D
E
F
G
H
J
K
L
M
PC14-
OSC32_IN PE4 PE5 PE6 PB9 PB5 PG15 PG12 PD5 PC11 PC10 PA12
PC15-
OSC32_OUT VBAT PF0 PF1 PB8 PG11 PD4 PC12 VDDUSB PA11
PH0 -
OSC_IN VSS VDD PD1 PA10 PA9
PH1 -
OSC_OUT PF3 PF4 PD0 PC9 PA8
NRST PF7 PC8 PC7
PF10 PF9 PG8 PC6
PC0 PC1 PC2 VDD12OTG
HS
OTG_HS
_REXT PG5
VSSA PA0 PA4 PG4 PG3 PG2
VREF- PA1 PA5 PC5 PF13 PE13 PD9 PD13 PD14 PD15
VREF+ PA2 PA6 PB0 PF12 PF15 PE8 PE14 PD8 PD12 PB14 PB15
VDDA PA3 PA7 PB1 PF11 PF14 PE7 PE15 PB10 PB11 PB12 PB13
PF2 BOOT0 PB7 PG13
PB6 PG14
PG10 PD3
PG9 PD2VSS VSSPF5 PDR_ON
PF6 VDDVDD VDDVDD VDDVDD VDD
PF8 VSSVSS VCAP_2VDD VDDVSS VDD
PE11 PD11VSS VCAP_1PC3 BYPASS_
REG
PE12 PD10PG1 PE10PC4 PB2
PG0 PE9
nnnnnnnnnnnnnnnnnnnnnnnnnnnnnnnnnnnnnnnnnnnn uuuuuuuuuuuuuuuuuuuuuuuuuuuuuuuuuuuuuuuuuuuu
DS11853 Rev 7 57/230
STM32F722xx STM32F723xx Pinouts and pin description
99
Figure 22. STM32F722xx LQFP176 pinout
1. The above figure shows the package top view.
MS41015V1
PDR_ON
VDD
PE1
PE0
PB9
PB8
BOOT0
PB7
PB6
PB5
PB4
PB3
PG15
V
DD
V
SS
PG14
PG13
PG12
PG11
PG10
PG9
PD7
PD6
V
DDSDMMC
V
SS
PD5
PD4
PD3
PD2
PD1
PD0
PC12
PC11
PC10
PI7
PI6
PE2
V
DD
PE3
V
SS
PE4
PE5
PA13
PE6
PA12
VBAT
PA11
PI8
PA10
PC14
PA9
PC15
PA8
PF0
PC9
PF1
PC8
PF2
PC7
PF3
PC6
PF4
V
DDUSB
PF5
V
SS
PG8
PG7
PF6
PG6
PF7
PG5
PF8
PG4
PF9
PG3
PF10
PG2
PH0
PD15
PH1
PD14
NRST
V
DD
PC0
V
SS
PC1
PD13
PC2
PD12
PC3
PD11
PD10
PD9
VREF+
PD8
PB15
PA0
PB14
PA1
PB13
PA2
PB12
PA3
BYPASS_REG
V
DD
PA4
PA5
PA6
PA7
PC4
PC5
PB0
PB1
PB2
PF11
PF12
VSS
V
DD
PF13
PF14
PF15
PG0
PG1
PE7
PE8
PE9
V
SS
V
DD
PE10
PE11
PE12
PE13
PE14
PE15
PB10
PB11
V
CAP_1
V
DD
176
175
174
173
172
171
170
169
168
167
166
165
164
163
162
161
160
159
158
157
156
155
154
153
141
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
132
131
130
129
128
127
126
125
124
123
122
121
120
119
118
117
116
115
114
113
112
111
110
109
108
45
46
47
48
49
50
51
52
53
54
55
56
57
58
59
60
61
62
63
64
65
66
67
68
80
LQFP176
152
151
150
149
148
147
146
145
144
143
142
69
70
71
72
73
74
75
76
77
78
79
26
27
28
29
30
31
32
33
34
35
36
107
106
105
104
103
102
101
100
99
98
89
V
CAP_2
PI4
PA15
PA14
V
DD
V
SS
PI3
PI2
PI5
140
139
138
137
136
135
134
133
PH4
PH5
PH6
PH7
PH8
PH9
PH10
PH11
88
81
82
83
84
85
86
87
PI1
PI0
PH15
PH14
PH13
V
DD
V
SS
PH12
96
95
94
93
92
91
90
97
37
38
39
40
41
42
43
44
PC13
PI9
PI10
PI11
VSS
PH2
PH3
VDD
VSS
VDD
VDD
VSSA
VDDA
nnnnnnnnnnnnnnnnnnnnnnnnnnnnnnnnnnnnnnnnnnnn uuuuuuuuuuuuuuuuuuuuuuuuuuuuuuuuuuuuuuuuuuuu
Pinouts and pin description STM32F722xx STM32F723xx
58/230 DS11853 Rev 7
Figure 23. STM32F723xx LQFP176 pinout
1. The above figure shows the package top view.
MS41082V1
PDR_ON
VDD
PE1
PE0
PB9
PB8
BOOT0
PB7
PB6
PB5
PB4
PB3
PG15
V
DD
V
SS
PG14
PG13
PG12
PG11
PG10
PG9
PD7
PD6
V
DDSDMMC
V
SS
PD5
PD4
PD3
PD2
PD1
PD0
PC12
PC11
PC10
PI7
PI6
PE2
V
DD
PE3
V
SS
PE4
PE5
PA13
PE6
PA12
VBAT
PA11
PI8
PA10
PC14
PA9
PC15
PA8
PF0
PC9
PF1
PC8
PF2
PC7
PF3
PC6
PF4
V
DDUSB
PF5
V
SS
PG8
PF6
PF7
PG5
PF8
PG4
PF9
PG3
PF10
PG2
PH0
PD15
PH1
PD14
NRST
V
DD
PC0
V
SS
PC1
PD11
PC2
PD10
PC3
PD9
PD8
PB15
VREF+
PB14
VDD12OTGHS
PA0
OTG_HS_REXT
PA1
PB13
PA2
PB12
PA3
BYPASS_REG
V
DD
PA4
PA5
PA6
PA7
PC4
PC5
PB0
PB1
PB2
PF11
PF12
VSS
V
DD
PF13
PF14
PF15
PG0
PG1
PE7
PE8
PE9
V
SS
V
DD
PE10
PE11
PE12
PE13
PE14
PE15
PB10
PB11
V
CAP_1
V
DD
176
175
174
173
172
171
170
169
168
167
166
165
164
163
162
161
160
159
158
157
156
155
154
153
141
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
132
131
130
129
128
127
126
125
124
123
122
121
120
119
118
117
116
115
114
113
112
111
110
109
108
45
46
47
48
49
50
51
52
53
54
55
56
57
58
59
60
61
62
63
64
65
66
67
68
80
LQFP176
with HS PHY
152
151
150
149
148
147
146
145
144
143
142
69
70
71
72
73
74
75
76
77
78
79
26
27
28
29
30
31
32
33
34
35
36
107
106
105
104
103
102
101
100
99
98
89
V
CAP_2
PI4
PA15
PA14
V
DD
V
SS
PI3
PI2
PI5
140
139
138
137
136
135
134
133
PH4
PH5
PH6
PH7
PH8
PH9
PH10
PH11
88
81
82
83
84
85
86
87
PI1
PI0
PH15
PH14
PH13
V
DD
V
SS
PH12
96
95
94
93
92
91
90
97
37
38
39
40
41
42
43
44
PC13
PI9
PI10
PI11
VSS
PH2
PH3
VDD
VSS
VDD
VDD
VSSA
VDDA
PD12
PD13
mwm vmvmvmv @mvmumw Umjmvm/mv OKKQ§© @<©©o r2="" :1="" f5="" \="" :vm="" mumumvrvmvm="" ru®="" @mvmvmw="" boooow="" @®©oo@="" @="" p="" p="" p="" nr5="" m="">
DS11853 Rev 7 59/230
STM32F722xx STM32F723xx Pinouts and pin description
99
Figure 24. STM32F723xx UFBGA176 ballout
1. The above figure shows the package top view.
MS39130V1
1 2 3 9 10 11 12 13 14 15
APE3PE2
PE1 PE0 PB8 PB5 PG14 PG13 PB4 PB3 PD7 PC12 PA15 PA14 PA13
BPE4PE5
PE6 PB9 PB7 PB6 PG15 PG12 PG11 PG10 PD6 PD0 PC11 PC10 PA12
CVBAT PI7 PI6 PI5 PDR_ON
VDD VDD VDD
SDMMC VDD PG9 PD5 PD1 PI3 PI2 PA11
DPC13 PI8 PI9 PI4 BOOT0 VSS VSS VSS PD4 PD3 PD2 PH15 PI1 PA10
EPC14 PF0 PI10 PI11 PH13 PH14 PI0 PA9
FPC15
VSS VDD PH2 VSS VSS VSS VSS VSS VSS VCAP2 PC9 PA8
GPH0 VSS VDD PH3 VSS VSS VSS VSS VSS VSS VDD PC8 PC7
HPH1 PF2 PF1 PH4 VSS VSS VSS VSS VSS VSS VDDUSB PG8 PC6
JNRST PF3 PH5 VSS VSS VSS VSS VSS VDD VDD PG7 PG6
KPF7 PF6
PF4
VDD VSS VSS VSS VSS VSS PH12 PG5 PG4 PG3
LPF10 PF9
PF5
BYPASS_
REG PH11 PH10 PD15 PG2
MVSSAPC0
PF8
PC1 PC2 PC3 PB2 PG1 VSS VSS VCAP_1 PH6 PH8 PH9 PD14 PD13
NVREF- PA0 PA4 PC4 PF13 PG0 VDD VDD VDD PE13 PH7 PD12 PD11 PD10
PVREF+
PA2 PA6 PA5 PC5 PF12 PF15 PE8 PE9 PE11 PE14 PB12 PB13 PD9 PD8
R VDDA PA3 PA7 PB1 PB0 PF11 PF14 PE7 PE10 PE12 PE15 PB10 PB11 PB14 PB15
VSS
45678
PA1
mUVUmUm \mUm PM 3 PM 1 13 F2 mU@ VUVU m :33 52 VUmUm B15 mUVUVUm NKAU \991 66m ®m p p U @mUG Fox I Pm 91 (Q g H @@ .C.(OOCOO®®®® 12 PC Fm mUVV VU@ OD.) VUmUV @U 0).) AU mUnU Fm F951 Ps1: ODOCGCOOOOODOCO VU UVUVV UVUG Mn .\./.\3@ van v D p CKQAJDDQrO @mV/VU fix (UP UUVU UUUU \s/O/Wuqrmvm \/O 1 vs vs; VUVUV/rk @/@.©\-© ©®©© @@@@ AUS mU 5 KS \55 :55 %@ H 51 p p 1 m PF5 PFE PA7 j\j,fl KKK G/Km/ PFZ PF: PFE PF? UnUV UVUV UmU mU@ VU@ PF7 r
Pinouts and pin description STM32F722xx STM32F723xx
60/230 DS11853 Rev 7
Figure 25. STM32F723xx UFBGA176 ballout (with OTG PHY HS)
1. The above figure shows the package top view.
MS42001V1
1 2 3 9 10 11 12 13 14 15
APE3PE2
PE1 PE0 PB8 PB5 PG14 PG13 PB4 PB3 PD7 PC12 PA15 PA14 PA13
BPE4PE5
PE6 PB9 PB7 PB6 PG15 PG12 PG11 PG10 PD6 PD0 PC11 PC10 PA12
CVBAT PI7 PI6 PI5 PDR_ON
VDD VDD VDD
SDMMC VDD PG9 PD5 PD1 PI3 PI2 PA11
DPC13 PI8 PI9 PI4 BOOT0 VSS VSS VSS PD4 PD3 PD2 PH15 PI1 PA10
EPC14 PF0 PI10 PI11 PH13 PH14 PI0 PA9
FPC15
VSS VDD PH2 VSS VSS VSS VSS VSS VSS VCAP2 PC9 PA8
GPH0 VSS VDD PH3 VSS VSS VSS VSS VSS VSS VDD PC8 PC7
HPH1 PF2 PF1 PH4 VSS VSS VSS VSS VSS VSS VDDUSB PG8 PC6
JNRST PF3 PH5 VSS VSS VSS VSS VSS VDD VDD VDD12
OTGHS
OTG_HS
_REXT
KPF7 PF6
PF4
VDD VSS VSS VSS VSS VSS PH12 PG5 PG4 PG3
LPF10 PF9
PF5
BYPASS_
REG PH11 PH10 PD15 PG2
MVSSAPC0
PF8
PC1 PC2 PC3 PB2 PG1 VSS VSS VCAP_1 PH6 PH8 PH9 PD14 PD13
NVREF- PA0 PA4 PC4 PF13 PG0 VDD VDD VDD PE13 PH7 PD12 PD11 PD10
PVREF+
PA2 PA6 PA5 PC5 PF12 PF15 PE8 PE9 PE11 PE14 PB12 PB13 PD9 PD8
R VDDA PA3 PA7 PB1 PB0 PF11 PF14 PE7 PE10 PE12 PE15 PB10 PB11 PB14 PB15
VSS
45678
PA1
DS11853 Rev 7 61/230
STM32F722xx STM32F723xx Pinouts and pin description
99
Table 9. Legend/abbreviations used in the pinout table
Name Abbreviation Definition
Pin name Unless otherwise specified in brackets below the pin name, the pin function during and after
reset is the same as the actual pin name
Pin type
S Supply pin
I Input only pin
I/O Input / output pin
I/O structure
FT 5 V tolerant I/O
FTf 5V tolerant I/O, I2C Fm+ option.
TTa 3.3 V tolerant I/O directly connected to ADC
B Dedicated BOOT pin
RST Bidirectional reset pin with weak pull-up resistor
Notes Unless otherwise specified by a note, all I/Os are set as floating inputs during and after reset
Alternate
functions Functions selected through GPIOx_AFR registers
Additional
functions Functions directly selected/enabled through peripheral registers
Pinouts and pin description STM32F722xx STM32F723xx
62/230 DS11853 Rev 7
Table 10. STM32F722xx and STM32F723xx pin and ball definition
Pin Number
Pin name
(function after
reset)(1)
Pin type
I/O structure
Notes
Alternate functions Additional
functions
STM32F722xx STM32F723xx
LQFP64
LQFP100
LQFP144
UFBGA176
LQFP176
LQFP100
WLCSP100
UFBGA176
UFBGA144
LQFP144
LQFP176
- 1 1 A2 1 1 C9 A2 A3 1 1 PE2 I/O FT -
TRACECLK, SPI4_SCK,
SAI1_MCLK_A,
QUADSPI_BK1_IO2, FMC_A23,
EVENTOUT
-
- 2 2 A1 2 2 A10 A1 A2 2 2 PE3 I/O FT - TRACED0, SAI1_SD_B,
FMC_A19, EVENTOUT -
- 3 3 B1 3 3 D9 B1 B2 3 3 PE4 I/O FT -
TRACED1, SPI4_NSS,
SAI1_FS_A, FMC_A20,
EVENTOUT
-
- 4 4 B2 4 4 E8 B2 B3 4 4 PE5 I/O FT -
TRACED2, TIM9_CH1,
SPI4_MISO, SAI1_SCK_A,
FMC_A21, EVENTOUT
-
- 5 5 B3 5 5 B10 B3 B4 5 5 PE6 I/O FT -
TRACED3, TIM1_BKIN2,
TIM9_CH2, SPI4_MOSI,
SAI1_SD_A, SAI2_MCK_B,
FMC_A22, EVENTOUT
-
1 6 6 C1 6 6 C10 C1 C2 6 6 VBAT S - - - -
STM32F722xx STM32F723xx Pinouts and pin description
DS11853 Rev 7 63/230
- - - D2 7 - - D2 - - 7 PI8 I/O FT
(2)
(3) EVENTOUT
RTC_TAMP2/
RTC_TS,
WKUP5
2 7 7 D1 8 7 D10 D1 A1 7 8 PC13 I/O FT
(2)
(3) EVENTOUT
RTC_TAMP1/
RTC_TS/
RTC_OUT,
WKUP4
388E19 8 E9E1B18 9
PC14-
OSC32_IN(PC1
4)
I/O FT
(2)
(3)
(5)
EVENTOUT OSC32_IN
499F1109E10F1C1910
PC15-
OSC32_OUT(P
C15)
I/O FT
(2)
(3)
(5)
EVENTOUT OSC32_OUT
- - - D3 11 - - D3 - - 11 PI9 I/O FT - UART4_RX, CAN1_RX,
FMC_D30, EVENTOUT -
- - - E3 12 - - E3 - - 12 PI10 I/O FT - FMC_D31, EVENTOUT -
---E413- -E4- -13 PI11 I/OFT
(4) OTG_HS_ULPI_DIR,
EVENTOUT WKUP6
- - - F2 14 - - F2 - - 14 VSS S - - - -
---F315- -F3- -15 VDD S-- - -
Table 10. STM32F722xx and STM32F723xx pin and ball definition (continued)
Pin Number
Pin name
(function after
reset)(1)
Pin type
I/O structure
Notes
Alternate functions Additional
functions
STM32F722xx STM32F723xx
LQFP64
LQFP100
LQFP144
UFBGA176
LQFP176
LQFP100
WLCSP100
UFBGA176
UFBGA144
LQFP144
LQFP176
Pinouts and pin description STM32F722xx STM32F723xx
64/230 DS11853 Rev 7
- - 10 E2 16 - - E2 C3 10 16 PF0 I/O FTf - I2C2_SDA, FMC_A0,
EVENTOUT -
- - 11 H3 17 - - H3 C4 11 17 PF1 I/O FTf - I2C2_SCL, FMC_A1,
EVENTOUT -
- - 12 H2 18 - - H2 D4 12 18 PF2 I/O FT - I2C2_SMBA, FMC_A2,
EVENTOUT -
- - 13 J2 19 - - J2 E2 13 19 PF3 I/O FT - FMC_A3, EVENTOUT ADC3_IN9
- - 14 J3 20 - - J3 E3 14 20 PF4 I/O FT - FMC_A4, EVENTOUT ADC3_IN14
- - 15 K3 21 - - K3 E4 15 21 PF5 I/O FT - FMC_A5, EVENTOUT ADC3_IN15
- 1016G222 10 F9G2D21622 VSS S - - - -
- 11 17 G3 23 11 F10 G3 D3 17 23 VDD S - - - -
- - 18 K2 24 - - K2 F3 18 24 PF6 I/O FT -
TIM10_CH1, SPI5_NSS,
SAI1_SD_B, UART7_RX,
QUADSPI_BK1_IO3,
EVENTOUT
ADC3_IN4
- - 19 K1 25 - - K1 F2 19 25 PF7 I/O FT -
TIM11_CH1, SPI5_SCK,
SAI1_MCLK_B, UART7_TX,
QUADSPI_BK1_IO2,
EVENTOUT
ADC3_IN5
Table 10. STM32F722xx and STM32F723xx pin and ball definition (continued)
Pin Number
Pin name
(function after
reset)(1)
Pin type
I/O structure
Notes
Alternate functions Additional
functions
STM32F722xx STM32F723xx
LQFP64
LQFP100
LQFP144
UFBGA176
LQFP176
LQFP100
WLCSP100
UFBGA176
UFBGA144
LQFP144
LQFP176
STM32F722xx STM32F723xx Pinouts and pin description
DS11853 Rev 7 65/230
- - 20 L3 26 - - L3 G3 20 26 PF8 I/O FT -
SPI5_MISO, SAI1_SCK_B,
UART7_RTS, TIM13_CH1,
QUADSPI_BK1_IO0,
EVENTOUT
ADC3_IN6
- - 21 L2 27 - - L2 G2 21 27 PF9 I/O FT -
SPI5_MOSI, SAI1_FS_B,
UART7_CTS, TIM14_CH1,
QUADSPI_BK1_IO1,
EVENTOUT
ADC3_IN7
- - 22 L1 28 - - L1 G1 22 28 PF10 I/O FT - EVENTOUT ADC3_IN8
5 12 23 G1 29 12 G10 G1 D1 23 29 PH0-OSC_IN I/O FT (5) EVENTOUT OSC_IN
6 13 24 H1 30 13 H10 H1 E1 24 30 PH1-OSC_OUT I/O FT (5) EVENTOUT OSC_OUT
71425J13114 G9J1F12531 NRST I/O
RS
T-- -
8 1526M232 15 F8M2H12632 PC0 I/OFT
(4)
SAI2_FS_B,
OTG_HS_ULPI_STP,
FMC_SDNWE, EVENTOUT
ADC1_IN10,
ADC2_IN10,
ADC3_IN10
9 1627M333 16 H9M3H22733 PC1 I/OFT-
TRACED0,
SPI2_MOSI/I2S2_SD,
SAI1_SD_A, EVENTOUT
ADC1_IN11,
ADC2_IN11,
ADC3_IN11,
RTC_TAMP3,
WKUP3
Table 10. STM32F722xx and STM32F723xx pin and ball definition (continued)
Pin Number
Pin name
(function after
reset)(1)
Pin type
I/O structure
Notes
Alternate functions Additional
functions
STM32F722xx STM32F723xx
LQFP64
LQFP100
LQFP144
UFBGA176
LQFP176
LQFP100
WLCSP100
UFBGA176
UFBGA144
LQFP144
LQFP176
Pinouts and pin description STM32F722xx STM32F723xx
66/230 DS11853 Rev 7
10 17 28 M4 34 17 J10 M4 H3 28 34 PC2 I/O FT (4)
SPI2_MISO,
OTG_HS_ULPI_DIR,
FMC_SDNE0, EVENTOUT
ADC1_IN12,
ADC2_IN12,
ADC3_IN12
11 18 29 M5 35 18 F7 M5 H4 29 35 PC3 I/O FT (4)
SPI2_MOSI/I2S2_SD,
OTG_HS_ULPI_NXT,
FMC_SDCKE0, EVENTOUT
ADC1_IN13,
ADC2_IN13,
ADC3_IN13
- - 30 - 36 - J7 - F10 30 36 VDD S - - - -
12 19 31 M1 37 19 K10 M1 J1 31 37 VSSA S - - - -
- - - N1 - - - N1 K1 - - VREF- S - - - -
13 20 32 P1 38 20 J9 P1 L1 32 38 VREF+ S - - - -
-2133R13921K9R1M13339 VDDA S - - - -
14 22 34 N3 40 22 G8 N3 J2 34 40 PA0-WKUP I/O FT (5)
TIM2_CH1/TIM2_ETR,
TIM5_CH1, TIM8_ETR,
USART2_CTS, UART4_TX,
SAI2_SD_B, EVENTOUT
ADC1_IN0,
ADC2_IN0,
ADC3_IN0,
WKUP1
Table 10. STM32F722xx and STM32F723xx pin and ball definition (continued)
Pin Number
Pin name
(function after
reset)(1)
Pin type
I/O structure
Notes
Alternate functions Additional
functions
STM32F722xx STM32F723xx
LQFP64
LQFP100
LQFP144
UFBGA176
LQFP176
LQFP100
WLCSP100
UFBGA176
UFBGA144
LQFP144
LQFP176
STM32F722xx STM32F723xx Pinouts and pin description
DS11853 Rev 7 67/230
15 23 35 N2 41 23 J8 N2 K2 35 41 PA1 I/O FT -
TIM2_CH2, TIM5_CH2,
USART2_RTS, UART4_RX,
QUADSPI_BK1_IO3,
SAI2_MCK_B, EVENTOUT
ADC1_IN1,
ADC2_IN1,
ADC3_IN1
16 24 36 P2 42 24 H8 P2 L2 36 42 PA2 I/O FT -
TIM2_CH3, TIM5_CH3,
TIM9_CH1, USART2_TX,
SAI2_SCK_B, EVENTOUT
ADC1_IN2,
ADC2_IN2,
ADC3_IN2,
WKUP2
---F443- -F4- -43 PH2 I/OFT-
LPTIM1_IN2,
QUADSPI_BK2_IO0,
SAI2_SCK_B, FMC_SDCKE0,
EVENTOUT
-
---G444- -G4- -44 PH3 I/OFT-
QUADSPI_BK2_IO1,
SAI2_MCK_B, FMC_SDNE0,
EVENTOUT
-
---H445- -H4- -45 PH4 I/OFTf
(4) I2C2_SCL, OTG_HS_ULPI_NXT,
EVENTOUT -
---J446- -J4- -46 PH5 I/OFTf- I2C2_SDA, SPI5_NSS,
FMC_SDNWE, EVENTOUT -
17 25 37 R2 47 25 H7 R2 M2 37 47 PA3 I/O FT (4)
TIM2_CH4, TIM5_CH4,
TIM9_CH2, USART2_RX,
OTG_HS_ULPI_D0, EVENTOUT
ADC1_IN3,
ADC2_IN3,
ADC3_IN3
18 26 38 - - 26 K8 - G4 38 - VSS S - - - -
- - - L4 48 - - L4 H5 - 48 BYPASS_REG I FT - - -
Table 10. STM32F722xx and STM32F723xx pin and ball definition (continued)
Pin Number
Pin name
(function after
reset)(1)
Pin type
I/O structure
Notes
Alternate functions Additional
functions
STM32F722xx STM32F723xx
LQFP64
LQFP100
LQFP144
UFBGA176
LQFP176
LQFP100
WLCSP100
UFBGA176
UFBGA144
LQFP144
LQFP176
Pinouts and pin description STM32F722xx STM32F723xx
68/230 DS11853 Rev 7
19 27 39 K4 49 27 - K4 F4 39 49 VDD S - - - -
20 28 40 N4 50 28 G7 N4 J3 40 50 PA4 I/O TTa -
SPI1_NSS/I2S1_WS,
SPI3_NSS/I2S3_WS,
USART2_CK, OTG_HS_SOF,
EVENTOUT
ADC1_IN4,
ADC2_IN4,
DAC_OUT1
21 29 41 P4 51 29 F6 P4 K3 41 51 PA5 I/O TTa (4)
TIM2_CH1/TIM2_ETR,
TIM8_CH1N,
SPI1_SCK/I2S1_CK,
OTG_HS_ULPI_CK, EVENTOUT
ADC1_IN5,
ADC2_IN5,
DAC_OUT2
22 30 42 P3 52 30 G6 P3 L3 42 52 PA6 I/O FT -
TIM1_BKIN, TIM3_CH1,
TIM8_BKIN, SPI1_MISO,
TIM13_CH1, EVENTOUT
ADC1_IN6,
ADC2_IN6
23 31 43 R3 53 31 K7 R3 M3 43 53 PA7 I/O FT -
TIM1_CH1N, TIM3_CH2,
TIM8_CH1N,
SPI1_MOSI/I2S1_SD,
TIM14_CH1, FMC_SDNWE,
EVENTOUT
ADC1_IN7,
ADC2_IN7
24 32 44 N5 54 32 H6 N5 J4 44 54 PC4 I/O FT - I2S1_MCK, FMC_SDNE0,
EVENTOUT
ADC1_IN14,
ADC2_IN14
- 33 45 P5 55 33 J6 P5 K4 45 55 PC5 I/O FT - FMC_SDCKE0, EVENTOUT ADC1_IN15,
ADC2_IN15
Table 10. STM32F722xx and STM32F723xx pin and ball definition (continued)
Pin Number
Pin name
(function after
reset)(1)
Pin type
I/O structure
Notes
Alternate functions Additional
functions
STM32F722xx STM32F723xx
LQFP64
LQFP100
LQFP144
UFBGA176
LQFP176
LQFP100
WLCSP100
UFBGA176
UFBGA144
LQFP144
LQFP176
STM32F722xx STM32F723xx Pinouts and pin description
DS11853 Rev 7 69/230
25 34 46 R5 56 34 F5 R5 L4 46 56 PB0 I/O FT (4)
TIM1_CH2N, TIM3_CH3,
TIM8_CH2N, UART4_CTS,
OTG_HS_ULPI_D1, EVENTOUT
ADC1_IN8,
ADC2_IN8
26 35 47 R4 57 35 G5 R4 M4 47 57 PB1 I/O FT (4)
TIM1_CH3N, TIM3_CH4,
TIM8_CH3N,
OTG_HS_ULPI_D2, EVENTOUT
ADC1_IN9,
ADC2_IN9
27 36 48 M6 58 36 K6 M6 J5 48 58 PB2 I/O FT -
SAI1_SD_A,
SPI3_MOSI/I2S3_SD,
QUADSPI_CLK, EVENTOUT
-
- - 49 R6 59 - - R6 M5 49 59 PF11 I/O FT - SPI5_MOSI, SAI2_SD_B,
FMC_SDNRAS, EVENTOUT -
- - 50 P6 60 - - P6 L5 50 60 PF12 I/O FT - FMC_A6, EVENTOUT -
- - 51 M8 61 - - M8 - 51 61 VSS S - - - -
- - 52 N8 62 - - N8 G5 52 62 VDD S - - - -
- - 53 N6 63 - - N6 K5 53 63 PF13 I/O FT - FMC_A7, EVENTOUT -
- - 54 R7 64 - - R7 M6 54 64 PF14 I/O FT - FMC_A8, EVENTOUT -
- - 55 P7 65 - - P7 L6 55 65 PF15 I/O FT - FMC_A9, EVENTOUT -
- - 56 N7 66 - - N7 K6 56 66 PG0 I/O FT - FMC_A10, EVENTOUT -
- - 57 M7 67 - - M7 J6 57 67 PG1 I/O FT - FMC_A11, EVENTOUT -
Table 10. STM32F722xx and STM32F723xx pin and ball definition (continued)
Pin Number
Pin name
(function after
reset)(1)
Pin type
I/O structure
Notes
Alternate functions Additional
functions
STM32F722xx STM32F723xx
LQFP64
LQFP100
LQFP144
UFBGA176
LQFP176
LQFP100
WLCSP100
UFBGA176
UFBGA144
LQFP144
LQFP176
Pinouts and pin description STM32F722xx STM32F723xx
70/230 DS11853 Rev 7
- 37 58 R8 68 37 J5 R8 M7 58 68 PE7 I/O FT -
TIM1_ETR, UART7_Rx,
QUADSPI_BK2_IO0, FMC_D4,
EVENTOUT
-
- 3859P869 38 H5P8L75969 PE8 I/OFT-
TIM1_CH1N, UART7_Tx,
QUADSPI_BK2_IO1, FMC_D5,
EVENTOUT
-
- 3960P970 39 K5 P9K76070 PE9 I/OFT-
TIM1_CH1, UART7_RTS,
QUADSPI_BK2_IO2, FMC_D6,
EVENTOUT
-
- - 61 M9 71 - - M9 H6 61 71 VSS S - - - -
- - 62 N9 72 - - N9 G6 62 72 VDD S - - - -
- 40 63 R9 73 40 E4 R9 J7 63 73 PE10 I/O FT -
TIM1_CH2N, UART7_CTS,
QUADSPI_BK2_IO3, FMC_D7,
EVENTOUT
-
- 41 64 P10 74 41 G4 P10 H8 64 74 PE11 I/O FT -
TIM1_CH2, SPI4_NSS,
SAI2_SD_B, FMC_D8,
EVENTOUT
-
- 42 65 R10 75 42 H4 R10 J8 65 75 PE12 I/O FT -
TIM1_CH3N, SPI4_SCK,
SAI2_SCK_B, FMC_D9,
EVENTOUT
-
- 43 66 N11 76 43 J4 N11 K8 66 76 PE13 I/O FT -
TIM1_CH3, SPI4_MISO,
SAI2_FS_B, FMC_D10,
EVENTOUT
-
Table 10. STM32F722xx and STM32F723xx pin and ball definition (continued)
Pin Number
Pin name
(function after
reset)(1)
Pin type
I/O structure
Notes
Alternate functions Additional
functions
STM32F722xx STM32F723xx
LQFP64
LQFP100
LQFP144
UFBGA176
LQFP176
LQFP100
WLCSP100
UFBGA176
UFBGA144
LQFP144
LQFP176
STM32F722xx STM32F723xx Pinouts and pin description
DS11853 Rev 7 71/230
- 44 67 P11 77 44 K4 P11 L8 67 77 PE14 I/O FT -
TIM1_CH4, SPI4_MOSI,
SAI2_MCK_B, FMC_D11,,
EVENTOUT
-
- 45 68 R11 78 45 F4 R11 M8 68 78 PE15 I/O FT - TIM1_BKIN, FMC_D12,
EVENTOUT -
28 46 69 R12 79 46 G3 R12 M9 69 79 PB10 I/O FTf (4)
TIM2_CH3, I2C2_SCL,
SPI2_SCK/I2S2_CK,
USART3_TX,
OTG_HS_ULPI_D3, EVENTOUT
-
29 47 70 R13 80 47 H3 R13 M10 70 80 PB11 I/O FTf (4)
TIM2_CH4, I2C2_SDA,
USART3_RX,
OTG_HS_ULPI_D4, EVENTOUT
-
30 48 71 M10 81 48 J3 M10 H7 71 81 VCAP_1 S - - - -
31 49 - - - 49 K3 - - - - VSS S - - - -
32 50 72 N10 82 50 K2 N10 G7 72 82 VDD S - - - -
---M1183- -M11- -83 PH6 I/OFT-
I2C2_SMBA, SPI5_SCK,
TIM12_CH1, FMC_SDNE1,
EVENTOUT
-
- - - N12 84 - - N12 - - 84 PH7 I/O FTf - I2C3_SCL, SPI5_MISO,
FMC_SDCKE1, EVENTOUT -
- - - M12 85 - - M12 - - 85 PH8 I/O FTf - I2C3_SDA, FMC_D16,
EVENTOUT -
Table 10. STM32F722xx and STM32F723xx pin and ball definition (continued)
Pin Number
Pin name
(function after
reset)(1)
Pin type
I/O structure
Notes
Alternate functions Additional
functions
STM32F722xx STM32F723xx
LQFP64
LQFP100
LQFP144
UFBGA176
LQFP176
LQFP100
WLCSP100
UFBGA176
UFBGA144
LQFP144
LQFP176
Pinouts and pin description STM32F722xx STM32F723xx
72/230 DS11853 Rev 7
- - - M13 86 - - M13 - - 86 PH9 I/O FT - I2C3_SMBA, TIM12_CH2,
FMC_D17, EVENTOUT -
- - - L13 87 - - L13 - - 87 PH10 I/O FT - TIM5_CH1, FMC_D18,
EVENTOUT -
- - - L12 88 - - L12 - - 88 PH11 I/O FT - TIM5_CH2, FMC_D19,
EVENTOUT -
- - - K12 89 - - K12 - - 89 PH12 I/O FT - TIM5_CH3, FMC_D20,
EVENTOUT -
- - - H12 90 - - H12 - - 90 VSS S - - - -
- - - J12 91 - K2 J12 - - 91 VDD S - - - -
33 51 73 P12 92 51 J2 P12 M11 73 92 PB12 I/O FT (4)
TIM1_BKIN, I2C2_SMBA,
SPI2_NSS/I2S2_WS,
USART3_CK,
OTG_HS_ULPI_D5,
OTG_HS_ID, EVENTOUT
-
34 52 74 P13 93 52 H2 P13 M12 74 93 PB13 I/O FT (4)
TIM1_CH1N,
SPI2_SCK/I2S2_CK,
USART3_CTS,
OTG_HS_ULPI_D6, EVENTOUT
OTG_HS_VBUS
- - - - - 53 G2 J15 H11 75 94 OTG_HS_REXT - - - USB HS OTG PHY calibration resistor
- - - - - 54 - - - - - VDDPHYHS - - - - -
- - - - - 55 G1 J14 H10 76 95 VDD12OTGHS - - - - -
Table 10. STM32F722xx and STM32F723xx pin and ball definition (continued)
Pin Number
Pin name
(function after
reset)(1)
Pin type
I/O structure
Notes
Alternate functions Additional
functions
STM32F722xx STM32F723xx
LQFP64
LQFP100
LQFP144
UFBGA176
LQFP176
LQFP100
WLCSP100
UFBGA176
UFBGA144
LQFP144
LQFP176
STM32F722xx STM32F723xx Pinouts and pin description
DS11853 Rev 7 73/230
35 53 75 R14 94 - - - - - - PB14 I/O FT -
TIM1_CH2N, TIM8_CH2N,
SPI2_MISO, USART3_RTS,
TIM12_CH1, SDMMC2_D0,
OTG_HS_DM, EVENTOUT
-
- - - - - 56 J1 R14 L11 77 96 PB14 I/O FT - OTG_HS_DM -
36 54 76 R15 95 - - - - - - PB15 I/O FT -
RTC_REFIN, TIM1_CH3N,
TIM8_CH3N,
SPI2_MOSI/I2S2_SD,
TIM12_CH2, SDMMC2_D1,
OTG_HS_DP, EVENTOUT
-
- - - - - 57 H1 R15 L12 78 97 PB15 I/O FT - OTG_HS_DP -
- 55 77 P15 96 - - P15 L9 79 98 PD8 I/O FT - USART3_TX, FMC_D13,
EVENTOUT -
- 56 78 P14 97 - - P14 K9 80 99 PD9 I/O FT - USART3_RX, FMC_D14,
EVENTOUT -
- 57 79 N15 98 - - N15 J9 81 100 PD10 I/O FT - USART3_CK, FMC_D15,
EVENTOUT -
Table 10. STM32F722xx and STM32F723xx pin and ball definition (continued)
Pin Number
Pin name
(function after
reset)(1)
Pin type
I/O structure
Notes
Alternate functions Additional
functions
STM32F722xx STM32F723xx
LQFP64
LQFP100
LQFP144
UFBGA176
LQFP176
LQFP100
WLCSP100
UFBGA176
UFBGA144
LQFP144
LQFP176
Pinouts and pin description STM32F722xx STM32F723xx
74/230 DS11853 Rev 7
- 58 80 N14 99 58 F3 N14 H9 82 101 PD11 I/O FT -
USART3_CTS,
QUADSPI_BK1_IO0,
SAI2_SD_A,
FMC_A16/FMC_CLE,
EVENTOUT
-
- 59 81 N13 100 59 F2 N13 L10 83 102 PD12 I/O FT -
TIM4_CH1, LPTIM1_IN1,
USART3_RTS,
QUADSPI_BK1_IO1,
SAI2_FS_A,
FMC_A17/FMC_ALE,
EVENTOUT
-
- 60 82 M15 101 60 E3 M15 K10 84 103 PD13 I/O FT -
TIM4_CH2, LPTIM1_OUT,
QUADSPI_BK1_IO3,
SAI2_SCK_A, FMC_A18,
EVENTOUT
-
- - 83 - 102 - - - G8 85 104 VSS S - - - -
- - 84 J13 103 - - J13 F8 86 105 VDD S - - - -
- 61 85 M14 104 61 F1 M14 K11 87 106 PD14 I/O FT - TIM4_CH3, UART8_CTS,
FMC_D0, EVENTOUT -
- 62 86 L14 105 62 E2 L14 K12 88 107 PD15 I/O FT - TIM4_CH4, UART8_RTS,
FMC_D1, EVENTOUT -
- - 87 L15 106 - - L15 J12 89 108 PG2 I/O FT - FMC_A12, EVENTOUT -
- - 88 K15 107 - - K15 J11 90 109 PG3 I/O FT - FMC_A13, EVENTOUT -
Table 10. STM32F722xx and STM32F723xx pin and ball definition (continued)
Pin Number
Pin name
(function after
reset)(1)
Pin type
I/O structure
Notes
Alternate functions Additional
functions
STM32F722xx STM32F723xx
LQFP64
LQFP100
LQFP144
UFBGA176
LQFP176
LQFP100
WLCSP100
UFBGA176
UFBGA144
LQFP144
LQFP176
STM32F722xx STM32F723xx Pinouts and pin description
DS11853 Rev 7 75/230
- - 89 K14 108 - - K14 J10 91 110 PG4 I/O FT - FMC_A14/FMC_BA0,
EVENTOUT -
- - 90 K13 109 - - K13 H12 92 111 PG5 I/O FT - FMC_A15/FMC_BA1,
EVENTOUT -
- - 91 J15 110 - - - - - - PG6 I/O FT - EVENTOUT -
- - 92 J14 111 - - - - - - PG7 I/O FT - USART6_CK, FMC_INT,
EVENTOUT -
- - 93 H14 112 - - H14 G11 93 112 PG8 I/O FT - USART6_RTS, FMC_SDCLK,
EVENTOUT -
- - 94 G12 113 - - G12 - 94 113 VSS S - - - -
--- - - - - -F10- - VDD --- - -
- - 95 H13 114 - K1 H13 C11 95 114 VDDUSB S - - - -
37 63 96 H15 115 63 E1 H15 G12 96 115 PC6 I/O FT -
TIM3_CH1, TIM8_CH1,
I2S2_MCK, USART6_TX,
SDMMC2_D6, SDMMC1_D6,
EVENTOUT
-
38 64 97 G15 116 64 D4 G15 F12 97 116 PC7 I/O FT -
TIM3_CH2, TIM8_CH2,
I2S3_MCK, USART6_RX,
SDMMC2_D7, SDMMC1_D7,
EVENTOUT
-
Table 10. STM32F722xx and STM32F723xx pin and ball definition (continued)
Pin Number
Pin name
(function after
reset)(1)
Pin type
I/O structure
Notes
Alternate functions Additional
functions
STM32F722xx STM32F723xx
LQFP64
LQFP100
LQFP144
UFBGA176
LQFP176
LQFP100
WLCSP100
UFBGA176
UFBGA144
LQFP144
LQFP176
Pinouts and pin description STM32F722xx STM32F723xx
76/230 DS11853 Rev 7
39 65 98 G14 117 65 D2 G14 F11 98 117 PC8 I/O FT -
TRACED1, TIM3_CH3,
TIM8_CH3, UART5_RTS,
USART6_CK, SDMMC1_D0,
EVENTOUT
-
40 66 99 F14 118 66 D1 F14 E11 99 118 PC9 I/O FTf -
MCO2, TIM3_CH4, TIM8_CH4,
I2C3_SDA, I2S_CKIN,
UART5_CTS,
QUADSPI_BK1_IO0,
SDMMC1_D1, EVENTOUT
-
41 67 100 F15 119 67 D3 F15 E12 100 119 PA8 I/O FTf -
MCO1, TIM1_CH1, TIM8_BKIN2,
I2C3_SCL, USART1_CK,
OTG_FS_SOF, EVENTOUT
-
42 68 101 E15 120 68 C3 E15 D12 101 120 PA9 I/O FT -
TIM1_CH2, I2C3_SMBA,
SPI2_SCK/I2S2_CK,
USART1_TX, EVENTOUT
OTG_FS_VBUS
43 69 102 D15 121 69 C2 D15 D11 102 121 PA10 I/O FT - TIM1_CH3, USART1_RX,
OTG_FS_ID, EVENTOUT -
44 70 103 C15 122 70 C1 C15 C12 103 122 PA11 I/O FT -
TIM1_CH4, USART1_CTS,
CAN1_RX, OTG_FS_DM,
EVENTOUT
-
45 71 104 B15 123 71 B2 B15 B12 104 123 PA12 I/O FT -
TIM1_ETR, USART1_RTS,
SAI2_FS_B, CAN1_TX,
OTG_FS_DP, EVENTOUT
-
46 72 105 A15 124 72 B1 A15 A12 105 124 PA13(JTMS-
SWDIO) I/O FT - JTMS-SWDIO, EVENTOUT -
Table 10. STM32F722xx and STM32F723xx pin and ball definition (continued)
Pin Number
Pin name
(function after
reset)(1)
Pin type
I/O structure
Notes
Alternate functions Additional
functions
STM32F722xx STM32F723xx
LQFP64
LQFP100
LQFP144
UFBGA176
LQFP176
LQFP100
WLCSP100
UFBGA176
UFBGA144
LQFP144
LQFP176
STM32F722xx STM32F723xx Pinouts and pin description
DS11853 Rev 7 77/230
- 73 106 F13 125 73 B3 F13 G9 106 125 VCAP_2 S - - - -
47 74 107 F12 126 74 A2 F12 G10 107 126 VSS S - - - -
48 75 108 G13 127 75 A1 G13 F9 108 127 VDD S - - - -
- - - E12 128 - - E12 - - 128 PH13 I/O FT -
TIM8_CH1N, UART4_TX,
CAN1_TX, FMC_D21,
EVENTOUT
-
- - - E13 129 - - E13 - - 129 PH14 I/O FT -
TIM8_CH2N, UART4_RX,
CAN1_RX, FMC_D22,
EVENTOUT
-
- - - D13 130 - - D13 - - 130 PH15 I/O FT - TIM8_CH3N, FMC_D23,
EVENTOUT -
- - - E14 131 - - E14 - - 131 PI0 I/O FT - TIM5_CH4, SPI2_NSS/I2S2_WS,
FMC_D24, EVENTOUT -
- - - D14 132 - - D14 - - 132 PI1 I/O FT -
TIM8_BKIN2,
SPI2_SCK/I2S2_CK, FMC_D25,
EVENTOUT
-
- - - C14 133 - - C14 - - 133 PI2 I/O FT - TIM8_CH4, SPI2_MISO,
FMC_D26, EVENTOUT -
- - - C13 134 - - C13 - - 134 PI3 I/O FT -
TIM8_ETR,
SPI2_MOSI/I2S2_SD, FMC_D27,
EVENTOUT
-
- - - D9 135 - - D9 - - 135 VSS S - - - -
Table 10. STM32F722xx and STM32F723xx pin and ball definition (continued)
Pin Number
Pin name
(function after
reset)(1)
Pin type
I/O structure
Notes
Alternate functions Additional
functions
STM32F722xx STM32F723xx
LQFP64
LQFP100
LQFP144
UFBGA176
LQFP176
LQFP100
WLCSP100
UFBGA176
UFBGA144
LQFP144
LQFP176
Pinouts and pin description STM32F722xx STM32F723xx
78/230 DS11853 Rev 7
- - - C9 136 - - C9 - - 136 VDD S - - - -
49 76 109 A14 137 76 C4 A14 A11 109 137 PA14(JTCK-
SWCLK) I/O FT - JTCK-SWCLK, EVENTOUT -
50 77 110 A13 138 77 B4 A13 A10 110 138 PA15(JTDI) I/O FT -
JTDI, TIM2_CH1/TIM2_ETR,
SPI1_NSS/I2S1_WS,
SPI3_NSS/I2S3_WS,
UART4_RTS, EVENTOUT
-
51 78 111 B14 139 78 A3 B14 B11 111 139 PC10 I/O FT -
SPI3_SCK/I2S3_CK,
USART3_TX, UART4_TX,
QUADSPI_BK1_IO1,
SDMMC1_D2, EVENTOUT
-
52 79 112 B13 140 79 C5 B13 B10 112 140 PC11 I/O FT -
SPI3_MISO, USART3_RX,
UART4_RX,
QUADSPI_BK2_NCS,
SDMMC1_D3, EVENTOUT
-
53 80 113 A12 141 80 D5 A12 C10 113 141 PC12 I/O FT -
TRACED3,
SPI3_MOSI/I2S3_SD,
USART3_CK, UART5_TX,
SDMMC1_CK, EVENTOUT
-
- 81 114 B12 142 81 B5 B12 E10 114 142 PD0 I/O FT - CAN1_RX, FMC_D2,
EVENTOUT -
- 82 115 C12 143 82 A4 C12 D10 115 143 PD1 I/O FT - CAN1_TX, FMC_D3,
EVENTOUT -
Table 10. STM32F722xx and STM32F723xx pin and ball definition (continued)
Pin Number
Pin name
(function after
reset)(1)
Pin type
I/O structure
Notes
Alternate functions Additional
functions
STM32F722xx STM32F723xx
LQFP64
LQFP100
LQFP144
UFBGA176
LQFP176
LQFP100
WLCSP100
UFBGA176
UFBGA144
LQFP144
LQFP176
STM32F722xx STM32F723xx Pinouts and pin description
DS11853 Rev 7 79/230
54 83 116 D12 144 83 E5 D12 E9 116 144 PD2 I/O FT -
TRACED2, TIM3_ETR,
UART5_RX, SDMMC1_CMD,
EVENTOUT
-
- 84 117 D11 145 84 C6 D11 D9 117 145 PD3 I/O FT -
SPI2_SCK/I2S2_CK,
USART2_CTS, FMC_CLK,
EVENTOUT
-
- 85 118 D10 146 85 B6 D10 C9 118 146 PD4 I/O FT - USART2_RTS, FMC_NOE,
EVENTOUT -
- 86 119 C11 147 86 A5 C11 B9 119 147 PD5 I/O FT - USART2_TX, FMC_NWE,
EVENTOUT -
- - 120 D8 148 - - D8 E7 120 148 VSS S - - - -
- - 121 C8 149 - - C8 F7 121 149 VDDSDMMC S - - - -
- 87 122 B11 150 87 D6 B11 A8 122 150 PD6 I/O FT -
SPI3_MOSI/I2S3_SD,
SAI1_SD_A, USART2_RX,
SDMMC2_CK, FMC_NWAIT,
EVENTOUT
-
- 88 123 A11 151 88 E6 A11 A9 123 151 PD7 I/O FT - USART2_CK SDMMC2_CMD,
FMC_NE1, EVENTOUT -
- - 124 C10 152 - - C10 E8 124 152 PG9 I/O FT -
USART6_RX,
QUADSPI_BK2_IO2,
SAI2_FS_B, SDMMC2_D0,
FMC_NE2/FMC_NCE,
EVENTOUT
-
Table 10. STM32F722xx and STM32F723xx pin and ball definition (continued)
Pin Number
Pin name
(function after
reset)(1)
Pin type
I/O structure
Notes
Alternate functions Additional
functions
STM32F722xx STM32F723xx
LQFP64
LQFP100
LQFP144
UFBGA176
LQFP176
LQFP100
WLCSP100
UFBGA176
UFBGA144
LQFP144
LQFP176
Pinouts and pin description STM32F722xx STM32F723xx
80/230 DS11853 Rev 7
- - 125 B10 153 - - B10 D8 125 153 PG10 I/O FT - SAI2_SD_B, SDMMC2_D1,
FMC_NE3, EVENTOUT -
- - 126 B9 154 - - B9 C8 126 154 PG11 I/O FT - SDMMC2_D2, FMC_INT,
EVENTOUT -
- - 127 B8 155 - - B8 B8 127 155 PG12 I/O FT -
LPTIM1_IN1, USART6_RTS,
SDMMC2_D3, FMC_NE4,
EVENTOUT
-
- - 128 A8 156 - - A8 D7 128 156 PG13 I/O FT -
TRACED0, LPTIM1_OUT,
USART6_CTS, FMC_A24,
EVENTOUT
-
- - 129 A7 157 - - A7 C7 129 157 PG14 I/O FT -
TRACED1, LPTIM1_ETR,
USART6_TX,
QUADSPI_BK2_IO3, FMC_A25,
EVENTOUT
-
- - 130 D7 158 - - D7 - 130 158 VSS S - - - -
Table 10. STM32F722xx and STM32F723xx pin and ball definition (continued)
Pin Number
Pin name
(function after
reset)(1)
Pin type
I/O structure
Notes
Alternate functions Additional
functions
STM32F722xx STM32F723xx
LQFP64
LQFP100
LQFP144
UFBGA176
LQFP176
LQFP100
WLCSP100
UFBGA176
UFBGA144
LQFP144
LQFP176
STM32F722xx STM32F723xx Pinouts and pin description
DS11853 Rev 7 81/230
- - 131 C7 159 - - C7 F6 131 159 VDD S - - - -
- - 132 B7 160 - - B7 B7 132 160 PG15 I/O FT - USART6_CTS, FMC_SDNCAS,
EVENTOUT -
55 89 133 A10 161 89 A6 A10 A7 133 161 PB3(JTDO/TRA
CESWO) I/O FT -
JTDO/TRACESWO, TIM2_CH2,
SPI1_SCK/I2S1_CK,
SPI3_SCK/I2S3_CK,
SDMMC2_D2, EVENTOUT
-
56 90 134 A9 162 90 B7 A9 A6 134 162 PB4(NJTRST) I/O FT -
NJTRST, TIM3_CH1,
SPI1_MISO, SPI3_MISO,
SPI2_NSS/I2S2_WS,
SDMMC2_D3, EVENTOUT
-
57 91 135 A6 163 91 C7 A6 B6 135 163 PB5 I/O FT (4)
TIM3_CH2, I2C1_SMBA,
SPI1_MOSI/I2S1_SD,
SPI3_MOSI/I2S3_SD,
OTG_HS_ULPI_D7,
FMC_SDCKE1, EVENTOUT
-
58 92 136 B6 164 92 D7 B6 C6 136 164 PB6 I/O FTf -
TIM4_CH1, I2C1_SCL,
USART1_TX,
QUAD SPI_BK1_NCS,
FMC_SDNE1, EVENTOUT
-
Table 10. STM32F722xx and STM32F723xx pin and ball definition (continued)
Pin Number
Pin name
(function after
reset)(1)
Pin type
I/O structure
Notes
Alternate functions Additional
functions
STM32F722xx STM32F723xx
LQFP64
LQFP100
LQFP144
UFBGA176
LQFP176
LQFP100
WLCSP100
UFBGA176
UFBGA144
LQFP144
LQFP176
Pinouts and pin description STM32F722xx STM32F723xx
82/230 DS11853 Rev 7
59 93 137 B5 165 93 B8 B5 D6 137 165 PB7 I/O FTf -
TIM4_CH2, I2C1_SDA,
USART1_RX, FMC_NL,
EVENTOUT
-
60 94 138 D6 166 94 A7 D6 D5 138 166 BOOT I B - - VPP
61 95 139 A5 167 95 C8 A5 C5 139 167 PB8 I/O FTf -
TIM4_CH3, TIM10_CH1,
I2C1_SCL, CAN1_RX,
SDMMC2_D4, SDMMC1_D4,
EVENTOUT
-
62 96 140 B4 168 96 D8 B4 B5 140 168 PB9 I/O FTf -
TIM4_CH4, TIM11_CH1,
I2C1_SDA, SPI2_NSS/I2S2_WS,
CAN1_TX, SDMMC2_D5,
SDMMC1_D5, EVENTOUT
-
- 97 141 A4 169 97 E7 A4 A5 141 169 PE0 I/O FT -
TIM4_ETR, LPTIM1_ETR,
UART8_Rx, SAI2_MCK_A,
FMC_NBL0, EVENTOUT
-
- 98 142 A3 170 98 B9 A3 A4 142 170 PE1 I/O FT - LPTIM1_IN2, UART8_Tx,
FMC_NBL1, EVENTOUT -
63 99 - D5 - 99 A8 D5 E6 - - VSS S - - - -
Table 10. STM32F722xx and STM32F723xx pin and ball definition (continued)
Pin Number
Pin name
(function after
reset)(1)
Pin type
I/O structure
Notes
Alternate functions Additional
functions
STM32F722xx STM32F723xx
LQFP64
LQFP100
LQFP144
UFBGA176
LQFP176
LQFP100
WLCSP100
UFBGA176
UFBGA144
LQFP144
LQFP176
STM32F722xx STM32F723xx Pinouts and pin description
DS11853 Rev 7 83/230
- - 143 C6 171 - - C6 E5 143 171 PDR_ON S - - - -
64 100 144 C5 172 100 A9 C5 F5 144 172 VDD S - - - -
- - - D4 173 - - D4 - - 173 PI4 I/O FT - TIM8_BKIN, SAI2_MCK_A,
FMC_NBL2, EVENTOUT -
- - - C4 174 - - C4 - - 174 PI5 I/O FT - TIM8_CH1, SAI2_SCK_A,
FMC_NBL3, EVENTOUT -
- - - C3 175 - - C3 - - 175 PI6 I/O FT - TIM8_CH2, SAI2_SD_A,
FMC_D28, EVENTOUT -
- - - C2 176 - - C2 - - 176 PI7 I/O FT - TIM8_CH3, SAI2_FS_A,
FMC_D29, EVENTOUT -
- - - F6 - - - F6 - - - VSS S - - - -
- - - F7 - - - F7 - - - VSS S - - - -
- - - F8 - - - F8 - - - VSS S - - - -
- - - F9 - - - F9 - - - VSS S - - - -
- - - F10 - - - F10 - - - VSS S - - - -
Table 10. STM32F722xx and STM32F723xx pin and ball definition (continued)
Pin Number
Pin name
(function after
reset)(1)
Pin type
I/O structure
Notes
Alternate functions Additional
functions
STM32F722xx STM32F723xx
LQFP64
LQFP100
LQFP144
UFBGA176
LQFP176
LQFP100
WLCSP100
UFBGA176
UFBGA144
LQFP144
LQFP176
Pinouts and pin description STM32F722xx STM32F723xx
84/230 DS11853 Rev 7
- - - G6 - - - G6 - - - VSS S - - - -
- - - G7 - - - G7 - - - VSS S - - - -
- - - G8 - - - G8 - - - VSS S - - - -
- - - G9 - - - G9 - - - VSS S - - - -
- - - G10 - - - G10 - - - VSS S - - - -
- - - H6 - - - H6 - - - VSS S - - - -
- - - H7 - - - H7 - - - VSS S - - - -
- - - H8 - - - H8 - - - VSS S - - - -
- - - H9 - - - H9 - - - VSS S - - - -
- - - H10 - - - H10 - - - VSS S - - - -
- - - J6 - - - J6 - - - VSS S - - - -
- - - J7 - - - J7 - - - VSS S - - - -
- - - J8 - - - J8 - - - VSS S - - - -
- - - J9 - - - J9 - - - VSS S - - - -
- - - J10 - - - J10 - - - VSS S - - - -
- - - K6 - - - K6 - - - VSS S - - - -
- - - K7 - - - K7 - - - VSS S - - - -
- - - K8 - - - K8 - - - VSS S - - - -
Table 10. STM32F722xx and STM32F723xx pin and ball definition (continued)
Pin Number
Pin name
(function after
reset)(1)
Pin type
I/O structure
Notes
Alternate functions Additional
functions
STM32F722xx STM32F723xx
LQFP64
LQFP100
LQFP144
UFBGA176
LQFP176
LQFP100
WLCSP100
UFBGA176
UFBGA144
LQFP144
LQFP176
STM32F722xx STM32F723xx Pinouts and pin description
DS11853 Rev 7 85/230
- - - K9 - - - K9 - - - VSS S - - - -
- - - K10 - - - K10 - - - VSS S - - - -
1. Function availability depends on the chosen device.
2. PC13, PC14, PC15 and PI8 are supplied through the power switch. Since the switch only sinks a limited amount of current (3 mA), the use of GPIOs PC13 to PC15 and
PI8 in output mode is limited:
- The speed should not exceed 2 MHz with a maximum load of 30 pF.
- These I/Os must not be used as a current source (e.g. to drive an LED).
3. Main function after the first backup domain power-up. Later on, it depends on the contents of the RTC registers even after reset (because these registers are not reset by
the main reset).
4. ULPI signals not available on the STM32F723xx devices.
5. If the device is in regulator OFF/internal reset ON mode (BYPASS_REG pin is set to VDD), then PA0 is used as an internal reset (active low).
Table 10. STM32F722xx and STM32F723xx pin and ball definition (continued)
Pin Number
Pin name
(function after
reset)(1)
Pin type
I/O structure
Notes
Alternate functions Additional
functions
STM32F722xx STM32F723xx
LQFP64
LQFP100
LQFP144
UFBGA176
LQFP176
LQFP100
WLCSP100
UFBGA176
UFBGA144
LQFP144
LQFP176
Pinouts and pin description STM32F722xx STM32F723xx
86/230 DS11853 Rev 7
Table 11. FMC pin definition
Pin name NOR/PSRAM/SR
AM
NOR/PSRAM
Mux NAND16 SDRAM
PF0 A0 - - A0
PF1 A1 - - A1
PF2 A2 - - A2
PF3 A3 - - A3
PF4 A4 - - A4
PF5 A5 - - A5
PF12 A6 - - A6
PF13 A7 - - A7
PF14 A8 - - A8
PF15 A9 - - A9
PG0 A10 - - A10
PG1 A11 - - A11
PG2 A12 - - A12
PG3 A13 - - -
PG4 A14 - - BA0
PG5 A15 - - BA1
PD11 A16 A16 CLE -
PD12 A17 A17 ALE -
PD13 A18 A18 - -
PE3 A19 A19 - -
PE4 A20 A20 - -
PE5 A21 A21 - -
PE6 A22 A22 - -
PE2 A23 A23 - -
PG13 A24 A24 - -
PG14 A25 A25 - -
PD14 D0 DA0 D0 D0
PD15 D1 DA1 D1 D1
PD0 D2 DA2 D2 D2
PD1 D3 DA3 D3 D3
PE7 D4 DA4 D4 D4
PE8 D5 DA5 D5 D5
PE9 D6 DA6 D6 D6
PE10 D7 DA7 D7 D7
DS11853 Rev 7 87/230
STM32F722xx STM32F723xx Pinouts and pin description
99
PE11 D8 DA8 D8 D8
PE12 D9 DA9 D9 D9
PE13 D10 DA10 D10 D10
PE14 D11 DA11 D11 D11
PE15 D12 DA12 D12 D12
PD8 D13 DA13 D13 D13
PD9 D14 DA14 D14 D14
PD10 D15 DA15 D15 D15
PH8 D16 - - D16
PH9 D17 - - D17
PH10 D18 - - D18
PH11 D19 - - D19
PH12 D20 - - D20
PH13 D21 - - D21
PH14 D22 - - D22
PH15 D23 - - D23
PI0 D24 - - D24
PI1 D25 - - D25
PI2 D26 - - D26
PI3 D27 - - D27
PI6 D28 - - D28
PI7 D29 - - D29
PI9 D30 - - D30
PI10 D31 - - D31
PD7 NE1 NE1 - -
PG9 NE2 NE2 NCE -
PG10 NE3 NE3 - -
PG11----
PG12 NE4 NE4 - -
PD3 CLK CLK - -
PD4 NOE NOE NOE -
PD5 NWE NWE NWE -
PD6 NWAIT NWAIT NWAIT -
PB7 NADV NADV - -
Table 11. FMC pin definition (continued)
Pin name NOR/PSRAM/SR
AM
NOR/PSRAM
Mux NAND16 SDRAM
Pinouts and pin description STM32F722xx STM32F723xx
88/230 DS11853 Rev 7
PF6 - - - -
PF7 - - - -
PF8 - - - -
PF9 - - - -
PF10----
PG6 - - - -
PG7 - - INT -
PE0 NBL0 NBL0 - NBL0
PE1 NBL1 NBL1 - NBL1
PI4 NBL2 - - NBL2
PI5 NBL3 - - NBL3
PG8 - - - SDCLK
PC0 - - - SDNWE
PF11 - - - SDNRAS
PG15 - - - SDNCAS
PH2 - - - SDCKE0
PH3 - - - SDNE0
PH6 - - - SDNE1
PH7 - - - SDCKE1
PH5 - - - SDNWE
PC2 - - - SDNE0
PC3 - - - SDCKE0
PB5 - - - SDCKE1
PB6 - - - SDNE1
Table 11. FMC pin definition (continued)
Pin name NOR/PSRAM/SR
AM
NOR/PSRAM
Mux NAND16 SDRAM
STM32F722xx STM32F723xx Pinouts and pin description
DS11853 Rev 7 89/230
Table 12. STM32F722xx and STM32F723xx alternate function mapping
Port
AF0 AF1 AF2 AF3 AF4 AF5 AF6 AF7 AF8 AF9 AF10 AF11 AF12 AF15
SYS TIM1/2 TIM3/4/5 TIM8/9/10/1
1/LPTIM1
I2C1/2/3/U
SART1
SPI1/I2S1/
SPI2/I2S2/
SPI3/I2S3/
SPI4/5
SPI2/I2S2/
SPI3/I2S3/
SPI3/I2S3/
SAI1/
UART4
SPI2/I2S2/S
PI3/I2S3/US
ART1/2/3/UA
RT5
SAI2/USART
6/UART4/5/7/
8/OTG1_FS
CAN1/TIM1
2/13/14/QU
ADSPI/
FMC/
OTG2_HS
SAI2/QUAD
SPI/SDMM
C2/OTG2_
HS/OTG1_
FS
SDMMC2
UART7/F
MC/SDM
MC1/
OTG2_FS
SYS
Port A
PA0 -
TIM2_CH1
/TIM2_ET
R
TIM5_CH1 TIM8_ETR - - - USART2_CT
SUART4_ TX - SAI2_SD_B - - EVEN
TOUT
PA1 - TIM2_CH2 TIM5_CH2 - - - - USART2_RT
SUART4_RX QUADSPI_
BK1_IO3
SAI2_MCK
_B --
EVEN
TOUT
PA2 - TIM2_CH3 TIM5_CH3 TIM9_CH1 - - - USART2_TX SAI2_SCK_B - - - - EVEN
TOUT
PA3 - TIM2_CH4 TIM5_CH4 TIM9_CH2 - - - USART2_RX - - OTG_HS_U
LPI_D0 --
EVEN
TOUT
PA4 - - - - - SPI1_NSS
/I2S1_WS
SPI3_NSS
/I2S3_WS USART2_CK - - - - OTG_HS_
SOF
EVEN
TOUT
PA5 -
TIM2_CH1
/TIM2_ET
R
-TIM8_CH1
N-SPI1_SCK
/I2S1_CK -- - -
OTG_HS_U
LPI_CK --
EVEN
TOUT
PA6 - TIM1_BKI
NTIM3_CH1 TIM8_BKIN - SPI1_MIS
O- - - TIM13_CH1 - - - EVEN
TOUT
PA7 - TIM1_CH1
NTIM3_CH2 TIM8_CH1
N-
SPI1_MO
SI/I2S1_S
D
- - - TIM14_CH1 - - FMC_SDN
WE
EVEN
TOUT
PA8 MCO1 TIM1_CH1 - TIM8_BKIN
2I2C3_SCL - - USART1_CK - - OTG_FS_S
OF --
EVEN
TOUT
PA9 - TIM1_CH2 - - I2C3_SMB
A
SPI2_SCK
/I2S2_CK - USART1_TX - - - - - EVEN
TOUT
PA10 - TIM1_CH3 - - - - - USART1_RX - - OTG_FS_I
D--
EVEN
TOUT
PA11 - TIM1_CH4 - - - - - USART1_CT
S- CAN1_RX OTG_FS_D
M--
EVEN
TOUT
Pinouts and pin description STM32F722xx STM32F723xx
90/230 DS11853 Rev 7
Port A
PA12 - TIM1_ETR - - - - - USART1_RT
SSAI2_FS_B CAN1_TX OTG_FS_D
P--
EVEN
TOUT
PA13 JTMS-
SWDIO -- - - -- - - - - --
EVEN
TOUT
PA14 JTCK-
SWCLK -- - - -- - - - - --
EVEN
TOUT
PA15 JTDI
TIM2_CH1
/TIM2_ET
R
-- -
SPI1_NSS
/I2S1_WS
SPI3_NSS
/I2S3_WS - UART4_RTS - - - - EVEN
TOUT
Port B
PB0 - TIM1_CH2
NTIM3_CH3 TIM8_CH2
N- - - - UART4_CTS -OTG_HS_U
LPI_D1 --
EVEN
TOUT
PB1 - TIM1_CH3
NTIM3_CH4 TIM8_CH3
N--- - - -OTG_HS_U
LPI_D2 --
EVEN
TOUT
PB2 - - - - - - SAI1_SD_
A
SPI3_MOSI/I
2S3_SD -QUADSPI_
CLK ---
EVEN
TOUT
PB3 JTDO/TR
ACESWO TIM2_CH2 - - - SPI1_SCK
/I2S1_CK
SPI3_SCK
/I2S3_CK ---
SDMMC2_
D2 --
EVEN
TOUT
PB4 NJTRST - TIM3_CH1 - - SPI1_MIS
O
SPI3_MIS
O
SPI2_NSS/I2
S2_WS --
SDMMC2_
D3 --
EVEN
TOUT
PB5 - - TIM3_CH2 - I2C1_SMB
A
SPI1_MO
SI/I2S1_S
D
SPI3_MO
SI/I2S3_S
D
---
OTG_HS_U
LPI_D7 -FMC_SDC
KE1
EVEN
TOUT
PB6 - - TIM4_CH1 - I2C1_SCL - - USART1_TX - - QUADSPI_
BK1_NCS -FMC_SDN
E1
EVEN
TOUT
PB7 - - TIM4_CH2 - I2C1_SDA - - USART1_RX - - - - FMC_NL EVEN
TOUT
PB8 - - TIM4_CH3 TIM10_CH
1I2C1_SCL - - - - CAN1_RX SDMMC2_
D4 -SDMMC1
_D4
EVEN
TOUT
Table 12. STM32F722xx and STM32F723xx alternate function mapping (continued)
Port
AF0 AF1 AF2 AF3 AF4 AF5 AF6 AF7 AF8 AF9 AF10 AF11 AF12 AF15
SYS TIM1/2 TIM3/4/5 TIM8/9/10/1
1/LPTIM1
I2C1/2/3/U
SART1
SPI1/I2S1/
SPI2/I2S2/
SPI3/I2S3/
SPI4/5
SPI2/I2S2/
SPI3/I2S3/
SPI3/I2S3/
SAI1/
UART4
SPI2/I2S2/S
PI3/I2S3/US
ART1/2/3/UA
RT5
SAI2/USART
6/UART4/5/7/
8/OTG1_FS
CAN1/TIM1
2/13/14/QU
ADSPI/
FMC/
OTG2_HS
SAI2/QUAD
SPI/SDMM
C2/OTG2_
HS/OTG1_
FS
SDMMC2
UART7/F
MC/SDM
MC1/
OTG2_FS
SYS
STM32F722xx STM32F723xx Pinouts and pin description
DS11853 Rev 7 91/230
Port B
PB9 - - TIM4_CH4 TIM11_CH1 I2C1_SDA SPI2_NSS
/I2S2_WS - - - CAN1_TX SDMMC2_
D5 -SDMMC1
_D5
EVEN
TOUT
PB10 - TIM2_CH3 - - I2C2_SCL SPI2_SCK
/I2S2_CK - USART3_TX - - OTG_HS_U
LPI_D3 --
EVEN
TOUT
PB11 - TIM2_CH4 - - I2C2_SDA - - USART3_RX - - OTG_HS_U
LPI_D4 --
EVEN
TOUT
PB12 - TIM1_BKI
N--
I2C2_SMB
A
SPI2_NSS
/I2S2_WS - USART3_CK - - OTG_HS_U
LPI_D5 -OTG_HS_
ID
EVEN
TOUT
PB13 - TIM1_CH1
N-- -
SPI2_SCK
/I2S2_CK -USART3_CT
S--
OTG_HS_U
LPI_D6 --
EVEN
TOUT
PB14 - TIM1_CH2
N-TIM8_CH2
N-SPI2_MIS
O-USART3_RT
S- TIM12_CH1 SDMMC2_
D0 -OTG_HS_
DM
EVEN
TOUT
PB15 RTC_REF
IN
TIM1_CH3
N-TIM8_CH3
N-
SPI2_MO
SI/I2S2_S
D
- - - TIM12_CH2 SDMMC2_
D1 -OTG_HS_
DP
EVEN
TOUT
Port C
PC0--- - - -- -SAI2_FS_B-
OTG_HS_U
LPI_STP -FMC_SDN
WE
EVEN
TOUT
PC1 TRACED0 - - - -
SPI2_MO
SI/I2S2_S
D
SAI1_SD_
A------
EVEN
TOUT
PC2 - - - - - SPI2_MIS
O-- - -
OTG_HS_U
LPI_DIR -FMC_SDN
E0
EVEN
TOUT
PC3 - - - - -
SPI2_MO
SI/I2S2_S
D
-- - -
OTG_HS_U
LPI_NXT -FMC_SDC
KE0
EVEN
TOUT
Table 12. STM32F722xx and STM32F723xx alternate function mapping (continued)
Port
AF0 AF1 AF2 AF3 AF4 AF5 AF6 AF7 AF8 AF9 AF10 AF11 AF12 AF15
SYS TIM1/2 TIM3/4/5 TIM8/9/10/1
1/LPTIM1
I2C1/2/3/U
SART1
SPI1/I2S1/
SPI2/I2S2/
SPI3/I2S3/
SPI4/5
SPI2/I2S2/
SPI3/I2S3/
SPI3/I2S3/
SAI1/
UART4
SPI2/I2S2/S
PI3/I2S3/US
ART1/2/3/UA
RT5
SAI2/USART
6/UART4/5/7/
8/OTG1_FS
CAN1/TIM1
2/13/14/QU
ADSPI/
FMC/
OTG2_HS
SAI2/QUAD
SPI/SDMM
C2/OTG2_
HS/OTG1_
FS
SDMMC2
UART7/F
MC/SDM
MC1/
OTG2_FS
SYS
Pinouts and pin description STM32F722xx STM32F723xx
92/230 DS11853 Rev 7
Port C
PC4 - - - - - I2S1_MCK - - - - - - FMC_SDN
E0
EVEN
TOUT
PC5--- - - -- - - - - -
FMC_SDC
KE0
EVEN
TOUT
PC6 - - TIM3_CH1 TIM8_CH1 - I2S2_MCK - - USART6_TX - SDMMC2_
D6 -SDMMC1
_D6
EVEN
TOUT
PC7 - - TIM3_CH2 TIM8_CH2 - - I2S3_MCK - USART6_RX - SDMMC2_
D7 -SDMMC1
_D7
EVEN
TOUT
PC8 TRACED1 - TIM3_CH3 TIM8_CH3 - - - UART5_RTS USART6_CK - - - SDMMC1
_D0
EVEN
TOUT
PC9 MCO2 - TIM3_CH4 TIM8_CH4 I2C3_SDA I2S_CKIN - UART5_CTS - QUADSPI_
BK1_IO0 --
SDMMC1
_D1
EVEN
TOUT
PC10---- --
SPI3_SCK
/I2S3_CK USART3_TX UART4_TX QUADSPI_
BK1_IO1 --
SDMMC1
_D2
EVEN
TOUT
PC11---- --
SPI3_MIS
OUSART3_RX UART4_RX QUADSPI_
BK2_NCS --
SDMMC1
_D3
EVEN
TOUT
PC12 TRACED3 - - - - -
SPI3_MO
SI/I2S3_S
D
USART3_CK UART5_TX - - - SDMMC1
_CK
EVEN
TOUT
PC13---- --- - - - ---
EVEN
TOUT
PC14---- --- - - - ---
EVEN
TOUT
PC15---- --- - - - ---
EVEN
TOUT
Table 12. STM32F722xx and STM32F723xx alternate function mapping (continued)
Port
AF0 AF1 AF2 AF3 AF4 AF5 AF6 AF7 AF8 AF9 AF10 AF11 AF12 AF15
SYS TIM1/2 TIM3/4/5 TIM8/9/10/1
1/LPTIM1
I2C1/2/3/U
SART1
SPI1/I2S1/
SPI2/I2S2/
SPI3/I2S3/
SPI4/5
SPI2/I2S2/
SPI3/I2S3/
SPI3/I2S3/
SAI1/
UART4
SPI2/I2S2/S
PI3/I2S3/US
ART1/2/3/UA
RT5
SAI2/USART
6/UART4/5/7/
8/OTG1_FS
CAN1/TIM1
2/13/14/QU
ADSPI/
FMC/
OTG2_HS
SAI2/QUAD
SPI/SDMM
C2/OTG2_
HS/OTG1_
FS
SDMMC2
UART7/F
MC/SDM
MC1/
OTG2_FS
SYS
STM32F722xx STM32F723xx Pinouts and pin description
DS11853 Rev 7 93/230
Port D
PD0--- - - -- - -CAN1_RX- -FMC_D2
EVEN
TOUT
PD1--- - - -- - -CAN1_TX- -FMC_D3
EVEN
TOUT
PD2 TRACED2 - TIM3_ETR - - - - - UART5_RX - - - SDMMC1
_CMD
EVEN
TOUT
PD3 - - - - - SPI2_SCK
/I2S2_CK -USART2_CT
S- - - - FMC_CLK EVEN
TOUT
PD4--- - - --
USART2_RT
S----
FMC_NO
E
EVEN
TOUT
PD5--- - - --USART2_TX- - - -
FMC_NW
E
EVEN
TOUT
PD6 - - - - -
SPI3_MO
SI/I2S3_S
D
SAI1_SD_
AUSART2_RX - - - SDMMC2
_CK
FMC_NW
AIT
EVEN
TOUT
PD7--- - - --USART2_CK- - -
SDMMC2
_CMD FMC_NE1 EVEN
TOUT
PD8 - - - - - - - USART3_TX - - - - FMC_D13 EVEN
TOUT
PD9--- - - --USART3_RX- - - -FMC_D14
EVEN
TOUT
PD10 - - - - - - - USART3_CK - - - - FMC_D15 EVEN
TOUT
PD11---- ---
USART3_CT
S-QUADSPI_
BK1_IO0 SAI2_SD_A - FMC_A16/
FMC_CLE
EVEN
TOUT
PD12 - - TIM4_CH1 LPTIM1_IN
1---
USART3_RT
S-QUADSPI_
BK1_IO1 SAI2_FS_A - FMC_A17/
FMC_ALE
EVEN
TOUT
PD13 - - TIM4_CH2 LPTIM1_O
UT --- - -
QUADSPI_
BK1_IO3
SAI2_SCK_
A-FMC_A18
EVEN
TOUT
Port D
PD14 - - TIM4_CH3 - - - - - UART8_CTS - - - FMC_D0 EVEN
TOUT
PD15 - - TIM4_CH4 - - - - - UART8_RTS - - - FMC_D1 EVEN
TOUT
Table 12. STM32F722xx and STM32F723xx alternate function mapping (continued)
Port
AF0 AF1 AF2 AF3 AF4 AF5 AF6 AF7 AF8 AF9 AF10 AF11 AF12 AF15
SYS TIM1/2 TIM3/4/5 TIM8/9/10/1
1/LPTIM1
I2C1/2/3/U
SART1
SPI1/I2S1/
SPI2/I2S2/
SPI3/I2S3/
SPI4/5
SPI2/I2S2/
SPI3/I2S3/
SPI3/I2S3/
SAI1/
UART4
SPI2/I2S2/S
PI3/I2S3/US
ART1/2/3/UA
RT5
SAI2/USART
6/UART4/5/7/
8/OTG1_FS
CAN1/TIM1
2/13/14/QU
ADSPI/
FMC/
OTG2_HS
SAI2/QUAD
SPI/SDMM
C2/OTG2_
HS/OTG1_
FS
SDMMC2
UART7/F
MC/SDM
MC1/
OTG2_FS
SYS
Pinouts and pin description STM32F722xx STM32F723xx
94/230 DS11853 Rev 7
Port E
PE0 - - TIM4_ETR LPTIM1_ET
R- - - - UART8_Rx - SAI2_MCK
_A -FMC_NBL
0
EVEN
TOUT
PE1 - - - LPTIM1_IN
2- - - - UART8_Tx - - - FMC_NBL
1
EVEN
TOUT
PE2 TRACECL
K- - - - SPI4_SCK SAI1_MCL
K_A --
QUADSPI_
BK1_IO2 --FMC_A23
EVEN
TOUT
PE3 TRACED0 - - - - - SAI1_SD_
B-----FMC_A19
EVEN
TOUT
PE4 TRACED1 - - - - SPI4_NSS SAI1_FS_
A-----FMC_A20
EVEN
TOUT
PE5 TRACED2 - - TIM9_CH1 - SPI4_MIS
O
SAI1_SCK
_A -----FMC_A21
EVEN
TOUT
PE6 TRACED3 TIM1_BKI
N2 -TIM9_CH2 - SPI4_MO
SI
SAI1_SD_
A---
SAI2_MCK
_B -FMC_A22
EVEN
TOUT
PE7 - TIM1_ETR - - - - - - UART7_Rx - QUADSPI_
BK2_IO0 -FMC_D4
EVEN
TOUT
PE8 - TIM1_CH1
N-- --- -UART7_Tx-
QUADSPI_
BK2_IO1 -FMC_D5
EVEN
TOUT
PE9-TIM1_CH1-- --- -UART7_RTS-
QUADSPI_
BK2_IO2 -FMC_D6
EVEN
TOUT
PE10 - TIM1_CH2
N-- --- -UART7_CTS-
QUADSPI_
BK2_IO3 -FMC_D7
EVEN
TOUT
PE11 - TIM1_CH2 - - - SPI4_NSS - - - - SAI2_SD_B - FMC_D8 EVEN
TOUT
PE12 - TIM1_CH3
N- - - SPI4_SCK - - - - SAI2_SCK_
B-FMC_D9
EVEN
TOUT
PE13 - TIM1_CH3 - - - SPI4_MIS
O- - - - SAI2_FS_B - FMC_D10 EVEN
TOUT
Port E
PE14 - TIM1_CH4 - - - SPI4_MO
SI -- - -
SAI2_MCK
_B -FMC_D11
EVEN
TOUT
PE15 - TIM1_BKI
N-- --- - - - --FMC_D12
EVEN
TOUT
Table 12. STM32F722xx and STM32F723xx alternate function mapping (continued)
Port
AF0 AF1 AF2 AF3 AF4 AF5 AF6 AF7 AF8 AF9 AF10 AF11 AF12 AF15
SYS TIM1/2 TIM3/4/5 TIM8/9/10/1
1/LPTIM1
I2C1/2/3/U
SART1
SPI1/I2S1/
SPI2/I2S2/
SPI3/I2S3/
SPI4/5
SPI2/I2S2/
SPI3/I2S3/
SPI3/I2S3/
SAI1/
UART4
SPI2/I2S2/S
PI3/I2S3/US
ART1/2/3/UA
RT5
SAI2/USART
6/UART4/5/7/
8/OTG1_FS
CAN1/TIM1
2/13/14/QU
ADSPI/
FMC/
OTG2_HS
SAI2/QUAD
SPI/SDMM
C2/OTG2_
HS/OTG1_
FS
SDMMC2
UART7/F
MC/SDM
MC1/
OTG2_FS
SYS
STM32F722xx STM32F723xx Pinouts and pin description
DS11853 Rev 7 95/230
Port F
PF0 - - - - I2C2_SDA - - - - - - - FMC_A0 EVEN
TOUT
PF1 - - - - I2C2_SCL - - - - - - - FMC_A1 EVEN
TOUT
PF2 - - - - I2C2_SMB
A-- - - - - -FMC_A2
EVEN
TOUT
PF3--- - - -- - - - - -FMC_A3
EVEN
TOUT
PF4--- - - -- - - - - -FMC_A4
EVEN
TOUT
PF5--- - - -- - - - - -FMC_A5
EVEN
TOUT
PF6 - - - TIM10_CH
1- SPI5_NSS SAI1_SD_
B-UART7_Rx
QUADSPI_
BK1_IO3 ---
EVEN
TOUT
PF7 - - - TIM11_CH1 - SPI5_SCK SAI1_MCL
K_B - UART7_Tx QUADSPI_
BK1_IO2 ---
EVEN
TOUT
PF8 - - - - - SPI5_MIS
O
SAI1_SCK
_B - UART7_RTS TIM13_CH1 QUADSPI_
BK1_IO0 --
EVEN
TOUT
PF9 - - - - - SPI5_MO
SI
SAI1_FS_
B- UART7_CTS TIM14_CH1 QUADSPI_
BK1_IO1 --
EVEN
TOUT
PF10---- --- - - - ---
EVEN
TOUT
PF11 - - - - - SPI5_MO
SI -- - -SAI2_SD_B-
FMC_SDN
RAS
EVEN
TOUT
PF12---- --- - - - --FMC_A6
EVEN
TOUT
Port F
PF13---- --- - - - --FMC_A7
EVEN
TOUT
PF14---- --- - - - --FMC_A8
EVEN
TOUT
PF15---- --- - - - --FMC_A9
EVEN
TOUT
Table 12. STM32F722xx and STM32F723xx alternate function mapping (continued)
Port
AF0 AF1 AF2 AF3 AF4 AF5 AF6 AF7 AF8 AF9 AF10 AF11 AF12 AF15
SYS TIM1/2 TIM3/4/5 TIM8/9/10/1
1/LPTIM1
I2C1/2/3/U
SART1
SPI1/I2S1/
SPI2/I2S2/
SPI3/I2S3/
SPI4/5
SPI2/I2S2/
SPI3/I2S3/
SPI3/I2S3/
SAI1/
UART4
SPI2/I2S2/S
PI3/I2S3/US
ART1/2/3/UA
RT5
SAI2/USART
6/UART4/5/7/
8/OTG1_FS
CAN1/TIM1
2/13/14/QU
ADSPI/
FMC/
OTG2_HS
SAI2/QUAD
SPI/SDMM
C2/OTG2_
HS/OTG1_
FS
SDMMC2
UART7/F
MC/SDM
MC1/
OTG2_FS
SYS
Pinouts and pin description STM32F722xx STM32F723xx
96/230 DS11853 Rev 7
Port G
PG0--- - - -- - - - - -FMC_A10
EVEN
TOUT
PG1--- - - -- - - - - -FMC_A11
EVEN
TOUT
PG2--- - - -- - - - - -FMC_A12
EVEN
TOUT
PG3--- - - -- - - - - -FMC_A13
EVEN
TOUT
PG4--- - - -- - - - - -
FMC_A14/
FMC_BA0
EVEN
TOUT
PG5--- - - -- - - - - -
FMC_A15/
FMC_BA1
EVEN
TOUT
PG6--- - - -- - - - - --
EVEN
TOUT
PG7 - - - - - - - - USART6_CK - - - FMC_INT EVEN
TOUT
PG8--- - - -- -
USART6_RT
S---
FMC_SDC
LK
EVEN
TOUT
PG9 - - - - - - - - USART6_RX QUADSPI_
BK2_IO2 SAI2_FS_B SDMMC2
_D0
FMC_NE2
/FMC_NC
E
EVEN
TOUT
PG10---- --- - - -SAI2_SD_B
SDMMC2
_D1 FMC_NE3 EVEN
TOUT
Table 12. STM32F722xx and STM32F723xx alternate function mapping (continued)
Port
AF0 AF1 AF2 AF3 AF4 AF5 AF6 AF7 AF8 AF9 AF10 AF11 AF12 AF15
SYS TIM1/2 TIM3/4/5 TIM8/9/10/1
1/LPTIM1
I2C1/2/3/U
SART1
SPI1/I2S1/
SPI2/I2S2/
SPI3/I2S3/
SPI4/5
SPI2/I2S2/
SPI3/I2S3/
SPI3/I2S3/
SAI1/
UART4
SPI2/I2S2/S
PI3/I2S3/US
ART1/2/3/UA
RT5
SAI2/USART
6/UART4/5/7/
8/OTG1_FS
CAN1/TIM1
2/13/14/QU
ADSPI/
FMC/
OTG2_HS
SAI2/QUAD
SPI/SDMM
C2/OTG2_
HS/OTG1_
FS
SDMMC2
UART7/F
MC/SDM
MC1/
OTG2_FS
SYS
STM32F722xx STM32F723xx Pinouts and pin description
DS11853 Rev 7 97/230
Port G
PG11---- --- - - -
SDMMC2_
D2 --
EVEN
TOUT
PG12 - - - LPTIM1_IN
1--- -
USART6_RT
S--
SDMMC2
_D3 FMC_NE4 EVEN
TOUT
PG13 TRACED0 - - LPTIM1_O
UT --- -
USART6_CT
S---FMC_A24
EVEN
TOUT
PG14 TRACED1 - - LPTIM1_ET
R- - - - USART6_TX QUADSPI_
BK2_IO3 --FMC_A25
EVEN
TOUT
PG15---- --- -
USART6_CT
S---
FMC_SDN
CAS
EVEN
TOUT
Port H
PH0--- - - -- - - - - --
EVEN
TOUT
PH1--- - - -- - - - - --
EVEN
TOUT
PH2 - - - LPTIM1_IN
2--- - -
QUADSPI_
BK2_IO0
SAI2_SCK_
B-FMC_SDC
KE0
EVEN
TOUT
PH3--- - - -- - -
QUADSPI_
BK2_IO1
SAI2_MCK
_B -FMC_SDN
E0
EVEN
TOUT
PH4 - - - - I2C2_SCL - - - - - OTG_HS_U
LPI_NXT --
EVEN
TOUT
PH5 - - - - I2C2_SDA SPI5_NSS - - - - - - FMC_SDN
WE
EVEN
TOUT
PH6 - - - - I2C2_SMB
ASPI5_SCK - - - TIM12_CH1 - - FMC_SDN
E1
EVEN
TOUT
PH7 - - - - I2C3_SCL SPI5_MIS
O-- - ---
FMC_SDC
KE1
EVEN
TOUT
Table 12. STM32F722xx and STM32F723xx alternate function mapping (continued)
Port
AF0 AF1 AF2 AF3 AF4 AF5 AF6 AF7 AF8 AF9 AF10 AF11 AF12 AF15
SYS TIM1/2 TIM3/4/5 TIM8/9/10/1
1/LPTIM1
I2C1/2/3/U
SART1
SPI1/I2S1/
SPI2/I2S2/
SPI3/I2S3/
SPI4/5
SPI2/I2S2/
SPI3/I2S3/
SPI3/I2S3/
SAI1/
UART4
SPI2/I2S2/S
PI3/I2S3/US
ART1/2/3/UA
RT5
SAI2/USART
6/UART4/5/7/
8/OTG1_FS
CAN1/TIM1
2/13/14/QU
ADSPI/
FMC/
OTG2_HS
SAI2/QUAD
SPI/SDMM
C2/OTG2_
HS/OTG1_
FS
SDMMC2
UART7/F
MC/SDM
MC1/
OTG2_FS
SYS
Pinouts and pin description STM32F722xx STM32F723xx
98/230 DS11853 Rev 7
Port H
PH8 - - - - I2C3_SDA - - - - - - - FMC_D16 EVEN
TOUT
PH9 - - - - I2C3_SMB
A- - - - TIM12_CH2 - - FMC_D17 EVEN
TOUT
PH10 - - TIM5_CH1 - - - - - - - - - FMC_D18 EVEN
TOUT
PH11 - - TIM5_CH2 - - - - - - - - - FMC_D19 EVEN
TOUT
PH12 - - TIM5_CH3 - - - - - - - - - FMC_D20 EVEN
TOUT
PH13 - - - TIM8_CH1
N- - - - UART4_TX CAN1_TX - - FMC_D21 EVEN
TOUT
PH14 - - - TIM8_CH2
N- - - - UART4_RX CAN1_RX - - FMC_D22 EVEN
TOUT
PH15 - - - TIM8_CH3
N- - - - - - - - FMC_D23 EVEN
TOUT
Port I
PI0 - - TIM5_CH4 - - SPI2_NSS
/I2S2_WS - - - - - - FMC_D24 EVEN
TOUT
PI1 - - - TIM8_BKIN
2-SPI2_SCK
/I2S2_CK - - - - - - FMC_D25 EVEN
TOUT
PI2 - - - TIM8_CH4 - SPI2_MIS
O- - - - - - FMC_D26 EVEN
TOUT
PI3 - - - TIM8_ETR -
SPI2_MO
SI/I2S2_S
D
- - - - - - FMC_D27 EVEN
TOUT
PI4---TIM8_BKIN- -- - - -
SAI2_MCK
_A -FMC_NBL
2
EVEN
TOUT
PI5 - - - TIM8_CH1 - - - - - - SAI2_SCK_
A-FMC_NBL
3
EVEN
TOUT
PI6 - - - TIM8_CH2 - - - - - - SAI2_SD_A - FMC_D28 EVEN
TOUT
Table 12. STM32F722xx and STM32F723xx alternate function mapping (continued)
Port
AF0 AF1 AF2 AF3 AF4 AF5 AF6 AF7 AF8 AF9 AF10 AF11 AF12 AF15
SYS TIM1/2 TIM3/4/5 TIM8/9/10/1
1/LPTIM1
I2C1/2/3/U
SART1
SPI1/I2S1/
SPI2/I2S2/
SPI3/I2S3/
SPI4/5
SPI2/I2S2/
SPI3/I2S3/
SPI3/I2S3/
SAI1/
UART4
SPI2/I2S2/S
PI3/I2S3/US
ART1/2/3/UA
RT5
SAI2/USART
6/UART4/5/7/
8/OTG1_FS
CAN1/TIM1
2/13/14/QU
ADSPI/
FMC/
OTG2_HS
SAI2/QUAD
SPI/SDMM
C2/OTG2_
HS/OTG1_
FS
SDMMC2
UART7/F
MC/SDM
MC1/
OTG2_FS
SYS
STM32F722xx STM32F723xx Pinouts and pin description
DS11853 Rev 7 99/230
Port I
PI7 - - - TIM8_CH3 - - - - - - SAI2_FS_A - FMC_D29 EVEN
TOUT
PI8--- - - -- - - - - --
EVEN
TOUT
PI9 - - - - - - - - UART4_RX CAN1_RX - - FMC_D30 EVEN
TOUT
PI10---- --- - - - --FMC_D31
EVEN
TOUT
PI11---- --- - - -
OTG_HS_U
LPI_DIR --
EVEN
TOUT
PI12---- --- - - - ---
EVEN
TOUT
PI13---- --- - - - ---
EVEN
TOUT
PI14---- --- - - - ---
EVEN
TOUT
PI15---- --- - - - ---
EVEN
TOUT
Table 12. STM32F722xx and STM32F723xx alternate function mapping (continued)
Port
AF0 AF1 AF2 AF3 AF4 AF5 AF6 AF7 AF8 AF9 AF10 AF11 AF12 AF15
SYS TIM1/2 TIM3/4/5 TIM8/9/10/1
1/LPTIM1
I2C1/2/3/U
SART1
SPI1/I2S1/
SPI2/I2S2/
SPI3/I2S3/
SPI4/5
SPI2/I2S2/
SPI3/I2S3/
SPI3/I2S3/
SAI1/
UART4
SPI2/I2S2/S
PI3/I2S3/US
ART1/2/3/UA
RT5
SAI2/USART
6/UART4/5/7/
8/OTG1_FS
CAN1/TIM1
2/13/14/QU
ADSPI/
FMC/
OTG2_HS
SAI2/QUAD
SPI/SDMM
C2/OTG2_
HS/OTG1_
FS
SDMMC2
UART7/F
MC/SDM
MC1/
OTG2_FS
SYS
Memory mapping STM32F722xx STM32F723xx
100/230 DS11853 Rev 7
5 Memory mapping
Refer to the product line reference manual for details on the memory mapping as well as the
boundary addresses for all peripherals.
Figure 26. Pin loading conditions I Figure 27. Pin input voltage
DS11853 Rev 7 101/230
STM32F722xx STM32F723xx Electrical characteristics
201
6 Electrical characteristics
6.1 Parameter conditions
Unless otherwise specified, all voltages are referenced to VSS.
6.1.1 Minimum and maximum values
Unless otherwise specified the minimum and maximum values are guaranteed in the worst
conditions of ambient temperature, supply voltage and frequencies by tests in production on
100% of the devices with an ambient temperature at TA = 25 °C and TA = TAmax (given by
the selected temperature range).
Data based on characterization results, design simulation and/or technology characteristics
are indicated in the table footnotes. Based on characterization, the minimum and maximum
values refer to sample tests and represent the mean value plus or minus three times the
standard deviation (mean±3σ).
6.1.2 Typical values
Unless otherwise specified, typical data are based on TA = 25 °C, VDD = 3.3 V (for the
1.7 V ≤VDD ≤3.6 V voltage range). They are given only as design guidelines and are not
tested.
Typical ADC accuracy values are determined by characterization of a batch of samples from
a standard diffusion lot over the full temperature range, where 95% of the devices have an
error less than or equal to the value indicated (mean±2σ).
6.1.3 Typical curves
Unless otherwise specified, all typical curves are given only as design guidelines and are
not tested.
6.1.4 Loading capacitor
The loading conditions used for pin parameter measurement are shown in Figure 26.
6.1.5 Pin input voltage
The input voltage measurement on a pin of the device is described in Figure 27.
Figure 26. Pin loading conditions Figure 27. Pin input voltage
MS19011V2
C = 50 pF
MCU pin
MS19010V2
MCU pin
VIN
VBAT fl Leve‘ smller u u Leve‘ smn
Electrical characteristics STM32F722xx STM32F723xx
102/230 DS11853 Rev 7
6.1.6 Power supply scheme
Figure 28. STM32F722xx power supply scheme
1. The two 2.2 µF ceramic capacitors should be replaced by two 100 nF decoupling capacitors when the
voltage regulator is OFF.
2. The 4.7 µF ceramic capacitor must be connected to one of the VDD pin.
3. VDDA=VDD and VSSA=VSS.
VBAT it 3%.. mgfi E2
DS11853 Rev 7 103/230
STM32F722xx STM32F723xx Electrical characteristics
201
Figure 29. STM32F723xx power supply scheme
1. In all the packages (except LQFP100), the VDDUSB allows supplying the PHY FS in PA11/PA12 and the
PHY HS on PB14/PB15. In the LQFP100, the PHY HS on PB14/PB15 is supplied by VDDPHYHS.
MSv42069V1
Analog:
RCs, PLL,
...
VDDA
VREF+
VREF-
VSSA
ADC
+ 1 μF
VREF
100 nF
+ 1 μF
VDD
PDR_ON
Reset
controller
100 nF
2.2 μF
OTG HS PHY
OTG HS PHY
voltage
regulator
VDD12OTGHS
OTG_HS_REXT
VDD
1/2/...11/12
VBAT
Kernel logic
(CPU,
digital
& RAM)
Backup circuitry
(OSC32K,RTC,
Backup registers,
backup RAM)
Wakeup logic
12 × 100 nF
+ 1 × 4.7 μF
VBAT =
1.65 to 3.6V
Voltage
regulator
VSS
1/2/...11/12
Level shifter
VDD
Flash memory
CAP_1
VCAP_2
2 × 2.2 μF
BYPASS_REG
OTG FS
PHY
100 nF
VDDUSB
+ 1 μF
V
DDUSB
OUT
IN
IO
V
DDSDMMC
PG[9..12], PD[6,7]
Logic
GP I/O s
OUT
IN
IO
Logic
Level shifter
V
Level shifter
OUT
IN
IO
PA[11,12], PB[14,15]
Logic
100 nF
VDDSDMMC
+ 1 μF
3 Kohm +/-1%
Power switch
Electrical characteristics STM32F722xx STM32F723xx
104/230 DS11853 Rev 7
2. The two 2.2 µF ceramic capacitors should be replaced by two 100 nF decoupling capacitors when the
voltage regulator is OFF.
3. The 4.7 µF ceramic capacitor must be connected to one of the VDD pin.
4. VDDA=VDD and VSSA=VSS.
Caution: Each power supply pair (VDD/VSS, VDDA/VSSA ...) must be decoupled with filtering ceramic
capacitors as shown above. These capacitors must be placed as close as possible to, or
below, the appropriate pins on the underside of the PCB to ensure good operation of the
device. It is not recommended to remove filtering capacitors to reduce PCB size or cost.
This might cause incorrect operation of the device.
6.1.7 Current consumption measurement
Figure 30. Current consumption measurement scheme
6.2 Absolute maximum ratings
Stresses above the absolute maximum ratings listed in Table 13: Voltage characteristics,
Table 14: Current characteristics, and Table 15: Thermal characteristics may cause
permanent damage to the device. These are stress ratings only and functional operation of
the device at these conditions is not implied. Exposure to maximum rating conditions for
extended periods may affect device reliability. The device mission profile (application
conditions) is compliant with JEDEC JESD47 Qualification Standard. Extended mission
profiles are available on demand.
ai14126
VBAT
VDD
VDDA
IDD_VBAT
IDD
Table 13. Voltage characteristics
Symbol Ratings Min Max Unit
VDD–VSS
External main supply voltage (including VDDA, VDD,
VBAT, VDDUSB, VDDPHYHS and VDDSDMMC) (1) −0.3 4.0
V
VIN
Input voltage on FT pins(2) VSS −0.3 VDD+4.0
Input voltage on TTa pins VSS −0.3 4.0
Input voltage on any other pin VSS −0.3 4.0
Input voltage on BOOT pin VSS 9.0
DS11853 Rev 7 105/230
STM32F722xx STM32F723xx Electrical characteristics
201
|ΔVDDx| Variations between different VDD power pins - 50 mV
|VSSX −VSS| Variations between all the different ground pins(3) -50
VESD(HBM) Electrostatic discharge voltage (human body model)
see Section 6.3.18:
Absolute maximum
ratings (electrical
sensitivity)
-
1. All main power (VDD, VDDA, VDDSDMMC, VDDPHYHS, VDDUSB) and ground (VSS, VSSA) pins must always be
connected to the external power supply, in the permitted range.
2. VIN maximum value must always be respected. Refer to Tab le 14 for the values of the maximum allowed
injected current.
3. Include VREF- pin.
Table 13. Voltage characteristics (continued)
Symbol Ratings Min Max Unit
Table 14. Current characteristics
Symbol Ratings Max. Unit
ΣIVDD Total current into sum of all VDD_x power lines (source)(1) 300
mA
Σ IVSS Total current out of sum of all VSS_x ground lines (sink)(1) −300
Σ IVDDUSB Total current into VDDUSB power line (source) 25
Σ IVDDSDMMC Total current into VDDSDMMC power line (source) 60
IVDD Maximum current into each VDD_x power line (source)(1) 100
IVDDSDMMC Maximum current into VDDSDMMC power line (source): PG[12:9], PD[7:6] 100
IVSS Maximum current out of each VSS_x ground line (sink)(1) −100
IIO
Output current sunk by any I/O and control pin 25
Output current sourced by any I/Os and control pin −25
ΣIIO
Total output current sunk by sum of all I/O and control pins (2) 120
Total output current sunk by sum of all USB I/Os 25
Total output current sourced by sum of all I/Os and control pins(2) −120
IINJ(PIN)
Injected current on FT, FTf, RST and B pins (3) −5/+0
Injected current on TTa pins(4) ±5
ΣIINJ(PIN)(4) Total injected current (sum of all I/O and control pins)(5) ±25
1. All main power (VDD, VDDA) and ground (VSS, VSSA) pins must always be connected to the external power supply, in the
permitted range.
2. This current consumption must be correctly distributed over all I/Os and control pins. The total output current must not be
sunk/sourced between two consecutive power supply pins referring to high pin count LQFP packages.
3. Positive injection is not possible on these I/Os and does not occur for input voltages lower than the specified maximum
value.
4. A positive injection is induced by VIN>VDDA while a negative injection is induced by VIN<VSS. IINJ(PIN) must never be
exceeded. Refer to Table 13: Voltage characteristics for the values of the maximum allowed input voltage.
5. When several inputs are submitted to a current injection, the maximum ΣIINJ(PIN) is the absolute sum of the positive and
negative injected currents (instantaneous values).
Electrical characteristics STM32F722xx STM32F723xx
106/230 DS11853 Rev 7
6.3 Operating conditions
6.3.1 General operating conditions
Table 15. Thermal characteristics
Symbol Ratings Value Unit
TSTG Storage temperature range −65 to +150 °C
TJMaximum junction temperature 125
Table 16. General operating conditions
Symbol Parameter Conditions(1) Min Typ Max Unit
fHCLK Internal AHB clock frequency
Power Scale 3 (VOS[1:0] bits in
PWR_CR register = 0x01), Regulator
ON, over-drive OFF
0 - 144
MH
z
Power Scale 2 (VOS[1:0] bits
in PWR_CR register = 0x10),
Regulator ON
Over-
drive
OFF 0
- 168
Over-
drive
ON
- 180
Power Scale 1 (VOS[1:0] bits
in PWR_CR register= 0x11),
Regulator ON
Over-
drive
OFF 0
- 180
Over-
drive
ON
- 216(2)
fPCLK1 Internal APB1 clock frequency Over-drive OFF 0 - 45
Over-drive ON 0 - 54
fPCLK2 Internal APB2 clock frequency Over-drive OFF 0 - 90
Over-drive ON 0 - 108
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STM32F722xx STM32F723xx Electrical characteristics
201
VDD Standard operating voltage - 1.7(3) -3.6
V
VDDA(4)(5)
Analog operating voltage
(ADC limited to 1.2 M samples) Must be the same potential as VDD(6)
1.7(3) -2.4
Analog operating voltage
(ADC limited to 2.4 M samples) 2.4 - 3.6
VDDUSB
USB supply voltage (supply
voltage for PA11,PA12, PB14 and
PB15 pins)
USB not used 1.7 3.3 3.6
USB used 3.0 - 3.6
VDDSPHYHS
USB PHY HS supply voltage in
the STM32F723 LQFP100 (supply
voltage for PB14 and PB15)
USB PHY HS not used 1.7 3.3 3.6
USB PHY HS used 3.0 - 3.6
VBAT Backup operating voltage - 1.65 - 3.6
VDDSDMMC
SDMMC2 supply voltage (supply
voltage for PG[12:9] and PD6
pins)
It can be different from VDD 1.7 - 3.6
V12
Regulator ON: 1.2 V internal
voltage on VCAP_1/VCAP_2 pins
Power Scale 3 ((VOS[1:0] bits in
PWR_CR register = 0x01), 144 MHz
HCLK max frequency
1.08 1.14 1.20
V
Power Scale 2 ((VOS[1:0] bits in
PWR_CR register = 0x10), 168 MHz
HCLK max frequency with over-drive
OFF or 180 MHz with over-drive ON
1.20 1.26 1.32
Power Scale 1 ((VOS[1:0] bits in
PWR_CR register = 0x11), 180 MHz
HCLK max frequency with over-drive
OFF or 216 MHz with over-drive ON
1.26 1.32 1.40
Regulator OFF: 1.2 V external
voltage must be supplied from
external regulator on
VCAP_1/VCAP_2 pins(7)
Max frequency 144 MHz 1.10 1.14 1.20
Max frequency 168MHz 1.20 1.26 1.32
Max frequency 180 MHz 1.26 1.32 1.38
VIN
Input voltage on RST and FT
pins(8)
2V ≤ VDD ≤ 3.6 V −0.3 - 5.5
VDD ≤ 2V −0.3 - 5.2
Input voltage on TTa pins - −0.3 - VDDA+
0.3
Input voltage on BOOT pin - 0 - 9
Table 16. General operating conditions (continued)
Symbol Parameter Conditions(1) Min Typ Max Unit
Electrical characteristics STM32F722xx STM32F723xx
108/230 DS11853 Rev 7
PD
Power dissipation at TA = 85 °C for
suffix 6 or TA = 105 °C for suffix
7(9)
LQFP64 - - 881
mW
LQFP100 - - 1117
WLCSP100 - - 558
LQFP144 - - 1587
LQFP176 - - 1869
UFBGA144 - - 476
UFBGA176 - - 485
TA
Ambient temperature for 6 suffix
version
Maximum power dissipation −40 - 85 °C
Low power dissipation(10) −40 - 105
Ambient temperature for 7 suffix
version
Maximum power dissipation −40 - 105 °C
Low power dissipation(10) −40 - 125
TJ Junction temperature range 6 suffix version −40 - 105 °C
7 suffix version −40 - 125
1. The over-drive mode is not supported at the voltage ranges from 1.7 to 2.1 V.
2. 216 MHz maximum frequency for 6 suffix version (200 MHz maximum frequency for 7 suffix version).
3. VDD/VDDA minimum value of 1.7 V is obtained with the use of an external power supply supervisor (refer to Section 3.15.2:
Internal reset OFF).
4. When the ADC is used, refer to Table 67: ADC characteristics.
5. If VREF+ pin is present, it must respect the following condition: VDDA-VREF+ < 1.2 V.
6. It is recommended to power VDD and VDDA from the same source. A maximum difference of 300 mV between VDD and VDDA
can be tolerated during power-up and power-down operation.
7. The over-drive mode is not supported when the internal regulator is OFF.
8. To sustain a voltage higher than VDD+0.3, the internal Pull-up and Pull-Down resistors must be disabled
9. If TA is lower, higher PD values are allowed as long as TJ does not exceed TJmax.
10. In low power dissipation state, TA can be extended to this range as long as TJ does not exceed TJmax.
Table 16. General operating conditions (continued)
Symbol Parameter Conditions(1) Min Typ Max Unit
Table 17. Limitations depending on the operating power supply range
Operating
power supply
range
ADC operation
Maximum Flash
memory access
frequency with
no wait states
(fFlashmax)
Maximum HCLK
frequency vs Flash
memory wait states
(1)(2)
I/O operation
Possible Flash
memory
operations
VDD =1.7 to
2.1 V(3)
Conversion time
up to 1.2 Msps 20 MHz
180 MHz with 8 wait
states and over-drive
OFF
No I/O
compensation
8-bit erase and
program
operations only
VDD = 2.1 to
2.4 V
Conversion time
up to 1.2 Msps 22 MHz
216 MHz with 9 wait
states and over-drive
ON
No I/O
compensation
16-bit erase and
program
operations
EXT
DS11853 Rev 7 109/230
STM32F722xx STM32F723xx Electrical characteristics
201
6.3.2 VCAP1/VCAP2 external capacitor
Stabilization for the main regulator is achieved by connecting an external capacitor CEXT to
the VCAP1/VCAP2 pins. CEXT is specified in Table 18.
Note: The VCAP2 pin is not available on the LQFP64 package.
Figure 31. External capacitor CEXT
1. Legend: ESR is the equivalent series resistance.
VDD = 2.4 to
2.7 V
Conversion time
up to 2.4 Msps 24 MHz
216 MHz with 8 wait
states and over-drive
ON
I/O compensation
works
16-bit erase and
program
operations
VDD = 2.7 to
3.6 V(4)
Conversion time
up to 2.4 Msps 30 MHz
216 MHz with 7 wait
states and over-drive
ON
I/O compensation
works
32-bit erase and
program
operations
1. Applicable only when the code is executed from Flash memory. When the code is executed from RAM, no wait state is
required.
2. Thanks to the ART accelerator on ITCM interface and L1-cache on AXI interface, the number of wait states given here
does not impact the execution speed from Flash memory since the ART accelerator or L1-cache allows to achieve a
performance equivalent to 0-wait state program execution.
3. VDD/VDDA minimum value of 1.7 V is obtained with the use of an external power supply supervisor (refer to Section 3.15.2:
Internal reset OFF).
4. The voltage range for USB full speed PHYs can drop down to 2.7 V. However the electrical characteristics of D- and D+
pins will be degraded between 2.7 and 3 V.
Table 17. Limitations depending on the operating power supply range (continued)
Operating
power supply
range
ADC operation
Maximum Flash
memory access
frequency with
no wait states
(fFlashmax)
Maximum HCLK
frequency vs Flash
memory wait states
(1)(2)
I/O operation
Possible Flash
memory
operations
Table 18. VCAP1/VCAP2 operating conditions(1)
1. When bypassing the voltage regulator, the two 2.2 µF VCAP capacitors are not required and should be
replaced by two 100 nF decoupling capacitors.
Symbol Parameter Conditions
CEXT Capacitance of external capacitor 2.2 µF
ESR ESR of external capacitor < 2 Ω
MS19044V2
ESR
R
Leak
C
Electrical characteristics STM32F722xx STM32F723xx
110/230 DS11853 Rev 7
6.3.3 Operating conditions at power-up / power-down (regulator ON)
Subject to general operating conditions for TA.
Table 20. Operating conditions at power-up / power-down (regulator ON)
6.3.4 Operating conditions at power-up / power-down (regulator OFF)
Subject to general operating conditions for TA.
6.3.5 Reset and power control block characteristics
The parameters given in Table 22 are derived from tests performed under ambient
temperature and VDD supply voltage conditions summarized in Table 16.
Table 19. VCAP1 operating conditions in the LQFP64 package(1)
1. When bypassing the voltage regulator, the 4.7 µF VCAP capacitor is not required and should be replaced
by two 100 nF decoupling capacitors.
Symbol Parameter Conditions
CEXT Capacitance of external capacitor 4.7 µF
ESR ESR of external capacitor between 0.1 Ω and 0.2 Ω
Symbol Parameter Min Max Unit
tVDD
VDD rise time rate 20 ∞
µs/V
VDD fall time rate 20 ∞
Table 21. Operating conditions at power-up / power-down (regulator OFF)(1)
1. To reset the internal logic at power-down, a reset must be applied on pin PA0 when VDD reach below
1.08 V.
Symbol Parameter Conditions Min Max Unit
tVDD
VDD rise time rate Power-up 20 ∞
µs/V
VDD fall time rate Power-down 20 ∞
tVCAP
VCAP_1 and VCAP_2 rise time rate Power-up 20 ∞
VCAP_1 and VCAP_2 fall time rate Power-down 20 ∞
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Table 22. reset and power control block characteristics
Symbol Parameter Conditions Min Typ Max Unit
VPVD
Programmable voltage
detector level selection
PLS[2:0]=000 (rising edge) 2.09 2.14 2.19 V
PLS[2:0]=000 (falling edge) 1.98 2.04 2.08 V
PLS[2:0]=001 (rising edge) 2.23 2.30 2.37 V
PLS[2:0]=001 (falling edge) 2.13 2.19 2.25 V
PLS[2:0]=010 (rising edge) 2.39 2.45 2.51 V
PLS[2:0]=010 (falling edge) 2.29 2.35 2.39 V
PLS[2:0]=011 (rising edge) 2.54 2.60 2.65 V
PLS[2:0]=011 (falling edge) 2.44 2.51 2.56 V
PLS[2:0]=100 (rising edge) 2.70 2.76 2.82 V
PLS[2:0]=100 (falling edge) 2.59 2.66 2.71 V
PLS[2:0]=101 (rising edge) 2.86 2.93 2.99 V
PLS[2:0]=101 (falling edge) 2.65 2.84 2.92 V
PLS[2:0]=110 (rising edge) 2.96 3.03 3.10 V
PLS[2:0]=110 (falling edge) 2.85 2.93 2.99 V
PLS[2:0]=111 (rising edge) 3.07 3.14 3.21 V
PLS[2:0]=111 (falling edge) 2.95 3.03 3.09 V
VPVDhyst(1) PVD hysteresis - - 100 - mV
VPOR/PDR
Power-on/power-down
reset threshold
Falling edge 1.60 1.68 1.76 V
Rising edge 1.64 1.72 1.80 V
VPDRhyst(1) PDR hysteresis - - 40 - mV
VBOR1
Brownout level 1
threshold
Falling edge 2.13 2.19 2.24 V
Rising edge 2.23 2.29 2.33 V
VBOR2
Brownout level 2
threshold
Falling edge 2.44 2.50 2.56 V
Rising edge 2.53 2.59 2.63 V
VBOR3
Brownout level 3
threshold
Falling edge 2.75 2.83 2.88 V
Rising edge 2.85 2.92 2.97 V
VBORhyst(1) BOR hysteresis - - 100 - mV
TRSTTEMPO
(1)(2) POR reset temporization - 0.5 1.5 3.0 ms
IRUSH(1)
InRush current on
voltage regulator power-
on (POR or wakeup
from Standby)
- - 160 250 mA
ERUSH(1)
InRush energy on
voltage regulator power-
on (POR or wakeup
from Standby)
VDD = 1.7 V, TA = 105 °C,
IRUSH = 171 mA for 31 µs --5.4µC
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6.3.6 Over-drive switching characteristics
When the over-drive mode switches from enabled to disabled or disabled to enabled, the
system clock is stalled during the internal voltage set-up.
The over-drive switching characteristics are given in Table 23. They are sbject to general
operating conditions for TA.
6.3.7 Supply current characteristics
The current consumption is a function of several parameters and factors such as the
operating voltage, ambient temperature, I/O pin loading, device software configuration,
operating frequencies, I/O pin switching rate, program location in memory and executed
binary code.
The current consumption is measured as described in Figure 30: Current consumption
measurement scheme.
All the run-mode current consumption measurements given in this section are performed
with a reduced code that gives a consumption equivalent to CoreMark code.
1. Guaranteed by design.
2. The reset temporization is measured from the power-on (POR reset or wakeup from VBAT) to the instant
when first instruction is read by the user application code.
Table 23. Over-drive switching characteristics(1)
1. Guaranteed by design.
Symbol Parameter Conditions Min Typ Max Unit
Tod_swen Over_drive switch
enable time
HSI -45 -
µs
HSE max for 4 MHz
and min for 26 MHz 45 -100
External HSE
50 MHz -40 -
Tod_swdis Over_drive switch
disable time
HSI -20 -
HSE max for 4 MHz
and min for 26 MHz. 20 -80
External HSE
50 MHz -15 -
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Typical and maximum current consumption
The MCU is placed under the following conditions:
•All I/O pins are in input mode with a static value at VDD or VSS (no load).
•All peripherals are disabled except if it is explicitly mentioned.
•The Flash memory access time is adjusted both to fHCLK frequency and VDD range
(see Table 17: Limitations depending on the operating power supply range).
•When the regulator is ON, the voltage scaling and over-drive mode are adjusted to
fHCLK frequency as follows:
– Scale 3 for fHCLK ≤ 144 MHz
– Scale 2 for 144 MHz < fHCLK ≤ 168 MHz
– Scale 1 for 168 MHz < fHCLK ≤ 216 MHz. The over-drive is only ON at 216 MHz.
•When the regulator is OFF, the V12 is provided externally as described in Table 16:
General operating conditions:
•The system clock is HCLK, fPCLK1 = fHCLK/4, and fPCLK2 = fHCLK/2.
•External clock frequency is 25 MHz and PLL is ON when fHCLK is higher than 25 MHz.
•The typical current consumption values are obtained for 1.7 V ≤ VDD ≤ 3.6 V voltage
range and for TA= 25 °C unless otherwise specified.
•The maximum values are obtained for 1.7 V ≤ VDD ≤ 3.6 V voltage range and a
maximum ambient temperature (TA) unless otherwise specified.
•For the voltage range 1.7 V ≤ VDD ≤ 3.6 V, the maximum frequency is 180 MHz.
Table 24. Typical and maximum current consumption in Run mode, code with data processing
running from ITCM RAM, regulator ON
Symbol Parameter Conditions fHCLK (MHz) Typ
Max(1)
Unit
TA = 25 °C TA = 85 °C TA = 105 °C
IDD
Supply cur-
rent in RUN
mode
All peripherals
enabled(2)(3)
216 156 170(4) 180(4) 200
mA
200 144 154 164.6 183
180 127 134(4) 143(4) 158(4)
168 113 119 127.4 141
144 86 96 112.6 126
60 41 44 52.8 65
25 22 24 33.5 45
All peripherals
disabled(3)
216 99 110(4) 119.6(4) 138.5
200 92 102 113.1 132
180 81 90(4) 96.7(4) 125(4)
168 72 78 86.5 100.1
144 55 61 77.1 90.8
60 24 25 38.5 50.3
25 12 13 26.3 38.1
1. Guaranteed by characterization results.
Electrical characteristics STM32F722xx STM32F723xx
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2. When analog peripheral blocks such as ADCs, DACs, HSE, LSE, HSI, or LSI are ON, an additional power consumption
should be considered.
3. When the ADC is ON (ADON bit set in the ADC_CR2 register), add an additional power consumption of 1.73 mA per ADC
for the analog part.
4. Guaranteed by test in production.
Table 25. Typical and maximum current consumption in Run mode, code with data processing
running from Flash memory (ART ON except prefetch / L1-cache ON)
or SRAM on AXI (L1-cache ON), regulator ON
Symbol Parameter Conditions fHCLK (MHz) Typ
Max(1)
Unit
TA = 25 °C TA = 85 °C TA = 105 °C
IDD
Supply cur-
rent in RUN
mode
All peripherals
enabled(2)(3)
216 155.3 164 175.8 185
mA
200 144.7 153.6 165.2 176
180 127.3 135 143.5 154
168 113.1 119.1 127.8 138
144 86.9 91.6 99.5 110
60 41.2 43.6 53.1 64
25 21.7 24 33.6 43.8
All peripherals
disabled(3)
216 90 106 120.4 130
200 84 99 113.8 124
180 74 86.6 97.3 107
168 66 76 87 97
144 51 59 68.2 78
60 23 27 38.8 49
25 11 13.6 26.4 36.8
1. Guaranteed by characterization results.
2. When analog peripheral blocks such as ADCs, DACs, HSE, LSE, HSI, or LSI are ON, an additional power consumption
should be considered.
3. When the ADC is ON (ADON bit set in the ADC_CR2 register), add an additional power consumption of 1.73 mA per ADC
for the analog part.
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Table 26. Typical and maximum current consumption in Run mode, code with data processing
running from Flash memory or SRAM on AXI (L1-cache disabled), regulator ON
Symbol Parameter Conditions fHCLK (MHz) Typ
Max(1)
Unit
TA= 25 °C TA=85 °C TA=105 °C
IDD
Supply cur-
rent in RUN
mode
All peripherals
enabled(2)(3)
216 129.3 137.6 162.8 173
mA
200 122 128 153.2 163.3
180 108 117 136.4 146
168 99 104.5 122.3 132
144 80 84.7 99.3 109.2
60 42 45 59.5 70
25 23 23.4 37.8 48
All peripherals
disabled(3)
216 73.3 82.3 107.4 119
200 70 77 101.8 113.5
180 62 71 90.2 101
168 59 63.6 81.4 92.1
144 49 53.3 67.9 79
60 26 31 45.1 56
25 14 16 30.6 41.2
1. Guaranteed by characterization results.
2. When analog peripheral blocks such as ADCs, DACs, HSE, LSE, HSI, or LSI are ON, an additional power consumption
should be considered.
3. When the ADC is ON (ADON bit set in the ADC_CR2 register), add an additional power consumption of 1.73 mA per ADC
for the analog part.
Electrical characteristics STM32F722xx STM32F723xx
116/230 DS11853 Rev 7
Table 27. Typical and maximum current consumption in Run mode, code with data processing
running from Flash memory on ITCM interface (ART disabled), regulator ON
Symbol Parameter Conditions fHCLK (MHz) Typ
Max(1)
Unit
TA= 25 °C TA=85 °C TA=105 °C
IDD
Supply cur-
rent in
RUN mode
All peripherals
enabled(2)(3)
216 138 151 174.7 184
mA
200 133 141 164.3 174
180 110 131 149.2 159
168 99 117 134 144
144 79 98 111.7 121
60 49 53 64 75
25 27 30 38.3 48
All peripherals
disabled(3)
216 82 96 119.5 131
200 81 89 113.1 124
180 65 85 103.1 114
168 58 76 93.2 104
144 48 67 80.4 91
60 33 36 49.7 60
25 18 21 31.1 41
1. Guaranteed by characterization results.
2. When analog peripheral blocks such as ADCs, DACs, HSE, LSE, HSI, or LSI are ON, an additional power consumption
should be considered.
3. When the ADC is ON (ADON bit set in the ADC_CR2 register), add an additional power consumption of 1.73 mA per ADC
for the analog part.
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Table 28. Typical and maximum current consumption in Run mode, code with data processing
running from Flash memory (ART ON except prefetch / L1-cache ON)
or SRAM on AXI (L1-cache ON), regulator OFF
Symbol Parameter Conditions fHCLK
(MHz)
Typ
Max(1)
Unit
TA= 25 °C TA= 85 °C TA= 105 °C
IDD12 IDD IDD12 IDD IDD12 IDD IDD12 IDD
IDD12/
IDD
Supply cur-
rent in RUN
mode from
V12 and
VDD supply
All Peripher-
als
Enabled(2)(3)
180 112 1.4 120 2 132.7 2 142 2
mA
168 110 1.4 106.4 2 118.7 2 130 2
144 78 1.3 82.5 2 93.6 2 103 2
60 37 1.1 37.6 2 49.3 2 60 2
25 19 1.1 18.5 2 30.4 2 40 2
All Peripher-
als Dis-
abled(3)
180 74 1.4 78 2 89.3 2 99 2
168 64 1.4 68 2 80.1 2 90 2
144 51 1.3 54 2 63.5 2 74 2
60 22 1.1 24 2 35.2 2 45 2
25 10 1.2 12 2 23.2 2 35 2
1. Guaranteed by characterization results.
2. When analog peripheral blocks such as ADCs, DACs, HSE, LSE, HSI, or LSI are ON, an additional power consumption
should be considered.
3. When the ADC is ON (ADON bit set in the ADC_CR2 register), add an additional power consumption of 1.73 mA per ADC
for the analog part.
Electrical characteristics STM32F722xx STM32F723xx
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Table 29. Typical and maximum current consumption in Sleep mode, regulator ON
Symbol Parameter Conditions fHCLK (MHz) Typ
Max(1)
Unit
TA= 25 °C TA=85 °C TA=105 °C
IDD
Supply cur-
rent in
SLEEP
mode
All peripherals
enabled(2)
216 82 96(3) 109.3(3) 128.3
mA
200 77 84 103.4 122.6
180 67 72(3) 88.3(3) 120(3)
168 60 64 78.9 92.7
144 46 49 61.8 73.6
60 24 26 37.2 49
25 14 16 27 38.8
All peripherals
disabled
216 24 28(3) 42.9(3) 62.2
200 22 26 41.9 61.2
180 19 21(3) 33.2(3) 48(3)
168 17 19 30.1 43.9
144 13 15 24.6 36.3
60 7 9 20.5 32.3
25 5 7 18.8 30.6
1. Guaranteed by characterization results.
2. When analog peripheral blocks such as ADCs, DACs, HSE, LSE, HSI, or LSI are ON, an additional power consumption
should be considered.
3. Guaranteed by test in production.
Table 30. Typical and maximum current consumption in Sleep mode, regulator OFF
Symbol Parameter Conditions fHCLK
(MHz)
Typ
Max(1)
Unit
TA= 25 °C TA= 85 °C TA= 105 °C
IDD12 IDD IDD12 IDD IDD12 IDD IDD12 IDD
IDD12/
IDD
Supply cur-
rent in RUN
mode from
V12 and VDD
supply
All Periph-
erals
Enabled(2)
180 62 1.3 67.5 2 84.4 2 95 2
mA
168 55 1.3 59.8 2 75.4 2 86 2
144 43 1.3 46.3 2 59.6 2 70 2
60 22 1 24 2 35.8 2 46 2
25 13 1 15 2 25.8 2 36 2
All Periph-
erals Dis-
abled
180 17 1.3 19 2 31.4 2 42 2
168 15 1.3 17 2 28.4 2 40 2
144 12 1.2 14 2 23.2 2 33 2
60 5 1 6 2 19.3 2 29 2
25 3 1 4 2 17.6 2 28 2
DS11853 Rev 7 119/230
STM32F722xx STM32F723xx Electrical characteristics
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1. Guaranteed by characterization results.
2. When analog peripheral blocks such as ADCs, DACs, HSE, LSE, HSI, or LSI are ON, an additional power consumption
should be considered.
Table 31. Typical and maximum current consumptions in Stop mode
Symbol Parameter Conditions
Typ
Max(1)
Unit
VDD = 3.6 V
TA =
25 °C
TA =
25 °C
TA =
85 °C
TA =
105 °C
IDD_STOP_NM
(normal mode)
Supply current in Stop
mode, main regulator in
Run mode
Flash memory in Stop mode,
all oscillators OFF, no IWDG 0.45 2 12 22
mA
Flash memory in Deep power
down mode, all oscillators OFF 0.4 2 12 22
Supply current in Stop
mode, main regulator in
Low-power mode
Flash memory in Stop mode, all
oscillators OFF, no IWDG 0.32 1.5 10 18
Flash memory in Deep power
down mode, all oscillators OFF, no
IWDG
0.27 1.5 10 18
IDD_STOP_UDM
(under-drive
mode)
Supply current in Stop
mode, main regulator in
Low voltage and under-
drive modes
Regulator in Run mode, Flash
memory in Deep power down
mode, all oscillators OFF, no
IWDG
0.15 0.8 5 7
Regulator in Low-power mode,
Flash memory in Deep power
down mode, all oscillators OFF, no
IWDG
0.1 0.7 4 7
1. Data based on characterization, tested in production.
Electrical characteristics STM32F722xx STM32F723xx
120/230 DS11853 Rev 7
Table 32. Typical and maximum current consumptions in Standby mode
Symbol Parameter Conditions
Typ(1) Max(2)
Unit
TA = 25 °C TA =
25 °C
TA =
85 °C
TA =
105 °C
VDD =
1.7 V
VDD=
2.4 V
VDD =
3.3 V VDD = 3.3 V
IDD_STBY
Supply current
in Standby
mode
Backup SRAM OFF, RTC and
LSE OFF 1.09 1.13 1.4 427 55
µA
Backup SRAM ON, RTC and
LSE OFF 1.85 1.88 2.17 530 60
Backup SRAM OFF, RTC ON
and LSE in low drive mode 1.65 1.86 2.43 747 95.5
Backup SRAM OFF, RTC ON
and LSE in medium low drive
mode
1.67 1.88 2.46 747.5 97
Backup SRAM OFF, RTC ON
and LSE in medium high drive
mode
1.8 2.01 2.61 7.5 50.5 102.5
Backup SRAM OFF, RTC ON
and LSE in high drive mode 1.92 2.13 2.73 853 107
Backup SRAM ON, RTC ON
and LSE in low drive mode 2.39 2.6 3.23 962 127
Backup SRAM ON, RTC ON
and LSE in Medium low drive
mode
2.41 2.64 3.25 963 128
Backup SRAM ON, RTC ON
and LSE in Medium high drive
mode
2.67 2.89 2.53 10 68 139
Backup SRAM ON, RTC ON
and LSE in High drive mode 2.68 2.9 3.51 10 68 138
1. PDR is OFF for VDD=1.7V. When the PDR is OFF (internal reset OFF), the typical current consumption is reduced by
additional 1.2 µA.
2. Guaranteed by characterization results.
VBAT
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Table 33. Typical and maximum current consumptions in VBAT mode
Symbol Parameter Conditions(1)
Typ Max(2)
Unit
TA =25 °C TA =85 °C TA =105 °C
VBAT =
1.7 V
VBAT=
2.4 V
VBAT=
3.3 V VBAT = 3.6 V
IDD_VBAT
Supply current
in VBAT mode
Backup SRAM OFF, RTC and
LSE OFF 0.035 0.037 0.043 410
µA
Backup SRAM ON, RTC and
LSE OFF 0.69 0.71 0.73 920
Backup SRAM OFF, RTC ON
and LSE in low drive mode 0.57 0.74 1.05 98 244
Backup SRAM OFF, RTC ON
and LSE in medium low drive
mode
0.59 0.76 1.08 101 251
Backup SRAM OFF, RTC ON
and LSE in medium high drive
mode
0.69 0.86 1.19 111 277
Backup SRAM OFF, RTC ON
and LSE in high drive mode 0.8 0.98 1.31 122 305
Backup SRAM ON, RTC ON and
LSE in low drive mode 1.22 1.41 1.74 162 405
Backup SRAM ON, RTC ON and
LSE in Medium low drive mode 1.25 1.43 1.78 166 414
Backup SRAM ON, RTC ON and
LSE in Medium high drive mode 1.46 1.65 2.01 187 468
Backup SRAM ON, RTC ON and
LSE in High drive mode 1.46 1.65 2.01 187 468
1. Crystal used: Abracon ABS07-120-32.768 kHz-T with a CL of 6 pF for typical values.
2. Guaranteed by characterization results.
222*: 2—2::
Electrical characteristics STM32F722xx STM32F723xx
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Figure 32. Typical VBAT current consumption (RTC ON/BKP SRAM OFF and
LSE in low drive mode)
Figure 33. Typical VBAT current consumption (RTC ON/BKP SRAM OFF and
LSE in medium low drive mode)
0
0.5
1
1.5
2
2.5
3
3.5
4
020406080100120
Temperature °C
1.65 V
1.7 V
1.8 V
2 V
2.4 V
2.7 V
3 V
3.3 V
3.6 V
MS37585V1
IDD_VBAT (uA)
MS37586V1
IDD_VBAT (uA)
0
0.5
1
1.5
2
2.5
3
3.5
4
4.5
020406080100120
Temperature °C
1.65 V
1.7 V
1.8 V
2 V
2.4 V
2.7 V
3 V
3.3 V
3.6 V
*+**_**__ _++***___
DS11853 Rev 7 123/230
STM32F722xx STM32F723xx Electrical characteristics
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Figure 34. Typical VBAT current consumption (RTC ON/BKP SRAM OFF and
LSE in medium high drive mode)
Figure 35. Typical VBAT current consumption (RTC ON/BKP SRAM OFF and
LSE in high drive mode)
0
0.5
1
1.5
2
2.5
3
3.5
4
4.5
020406080100120
Temperature °C
1.65 V
1.7 V
1.8 V
2 V
2.4 V
2.7 V
3 V
3.3 V
3.6 V
IDD_VBAT (uA)
MS37587V1
MS37588V1
0
0.5
1
1.5
2
2.5
3
3.5
4
4.5
020406080100120
Temperature °C
1.65 V
1.7 V
1.8 V
2 V
2.4 V
2.7 V
3 V
3.3 V
3.6 V
IDD_VBAT (uA)
II_:__
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Figure 36. Typical VBAT current consumption (RTC ON/BKP SRAM OFF and
LSE in high medium drive mode)
I/O system current consumption
The current consumption of the I/O system has two components: static and dynamic.
I/O static current consumption
All the I/Os used as inputs with pull-up generate current consumption when the pin is
externally held low. The value of this current consumption can be simply computed by using
the pull-up/pull-down resistors values given in Table 61: I/O static characteristics.
For the output pins, any external pull-down or external load must also be considered to
estimate the current consumption.
Additional I/O current consumption is due to I/Os configured as inputs if an intermediate
voltage level is externally applied. This current consumption is caused by the input Schmitt
trigger circuits used to discriminate the input value. Unless this specific configuration is
required by the application, this supply current consumption can be avoided by configuring
these I/Os in analog mode. This is notably the case of ADC input pins which should be
configured as analog inputs.
Caution: Any floating input pin can also settle to an intermediate voltage level or switch inadvertently,
as a result of external electromagnetic noise. To avoid current consumption related to
floating pins, they must either be configured in analog mode, or forced internally to a definite
digital value. This can be done either by using pull-up/down resistors or by configuring the
pins in output mode.
I/O dynamic current consumption
In addition to the internal peripheral current consumption (see Table 35: Peripheral current
consumption), the I/Os used by an application also contribute to the current consumption.
When an I/O pin switches, it uses the current from the MCU supply voltage to supply the I/O
0
1
2
3
4
5
6
7
8
9
020406080100120
Temperature( °C)
1.65 V
1.7 V
1.8 V
2 V
2.4 V
2.7 V
3 V
3.3 V
3.6 V
IDD_VBAT (uA)
MS37589V1
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STM32F722xx STM32F723xx Electrical characteristics
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pin circuitry and to charge/discharge the capacitive load (internal or external) connected to
the pin:
Where
ISW is the current sunk by a switching I/O to charge/discharge the capacitive load
VDD is the MCU supply voltage
fSW is the I/O switching frequency
C is the total capacitance seen by the I/O pin: C = CINT+ CEXT
The test pin is configured in push-pull output mode and is toggled by software at a fixed
frequency.
ISW VDD fSW C××=
Table 34. Switching output I/O current consumption(1)
Symbol Parameter Conditions
I/O toggling
frequency (fsw)
MHz
Typ
VDD = 3.3 V
Typ
VDD = 1.8 V Unit
IDDIO
I/O switching
Current
CEXT = 0 pF
C = CINT + CS + CEXT
2 0.1 0.1
mA
8 0.4 0.2
25 1.1 0.7
50 2.4 1.3
60 3.1 1.6
84 4.3 2.4
90 4.9 2.6
100 5.4 2.8
108 5.6 -
CEXT = 10 pF
C = CINT + CS + CEXT
20.20.1
80.60.3
25 1.8 1.1
50 3.1 2.3
60 4.6 3.4
84 9.7 3.6
90 10.12 5.2
100 14.92 5.4
108 18.11 -
Electrical characteristics STM32F722xx STM32F723xx
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On-chip peripheral current consumption
The MCU is placed under the following conditions:
•At startup, all I/O pins are in analog input configuration.
•All peripherals are disabled unless otherwise mentioned.
•I/O compensation cell enabled.
•The ART/L1-cache is ON.
•Scale 1 mode selected, internal digital voltage V12 = 1.32 V.
•HCLK is the system clock. fPCLK1 = fHCLK/4, and fPCLK2 = fHCLK/2.
The given value is calculated by measuring the difference of current consumption
– with all peripherals clocked off
– with only one peripheral clocked on
–f
HCLK = 216 MHz (Scale 1 + over-drive ON), fHCLK =168MHz (Scale 2),
fHCLK = 144 MHz (Scale 3)
•Ambient operating temperature is 25 °C and VDD=3.3 V.
IDDIO
I/O switching
Current
CEXT = 22 pF
C = CINT + CS + CEXT
20.30.1
mA
81.00.5
25 3.5 1.6
50 5.9 4.2
60 10.0 4.4
84 19.12 5.8
90 19.6 -
CEXT = 33 pF
C = CINT + CS + CEXT
20.30.2
81.30.7
25 3.5 2.3
50 10.26 5.19
60 16.53 -
1. CINT + CS, PCB board capacitance including the pad pin is estimated to15 pF.
Table 34. Switching output I/O current consumption(1) (continued)
Symbol Parameter Conditions
I/O toggling
frequency (fsw)
MHz
Typ
VDD = 3.3 V
Typ
VDD = 1.8 V Unit
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STM32F722xx STM32F723xx Electrical characteristics
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Table 35. Peripheral current consumption
Peripheral
IDD(Typ)(1)
Unit
Scale 1 Scale 2 Scale 3
AHB1
(up to
216 MHz)
GPIOA 3.6 3.4 2.9
µA/MHz
GPIOB 3.7 3.6 3.1
GPIOC 3.7 3.4 3.0
GPIOD 3.7 3.6 3.0
GPIOE 3.6 3.4 2.9
GPIOF 3.5 3.4 2.9
GPIOG 3.5 3.3 2.8
GPIOH 3.5 3.4 2.9
GPIOI 3.5 3.3 2.9
CRC 1.2 1.1 0.9
BKPSRAM 0.8 0.7 0.6
DMA1 3.07 x N + 8.7 2.98 x N + 8.4 2.52 x N + 7.02
DMA2 3.01 x N + 7.98 2.95 x N + 7.95 2.48 x N + 6.69
OTG_HS+ULPI 54.4 53.2 44.6
AHB2
(up to
216 MHz)
RNG 1.9 1.8 1.6
µA/MHz
USB_OTG_FS 28.7 27.9 23.5
AHB3
(up to
216 MHz)
FMC 16.2 15.8 13.3
µA/MHz
QSPI 16.9 16.3 13.8
Bus matrix(2) 15.8 12.8 8.5 µA/MHz
Electrical characteristics STM32F722xx STM32F723xx
128/230 DS11853 Rev 7
APB1
(up to
54 MHz)
TIM2 19.3 18.2 15.6
µA/MHz
TIM3 15 14 12.2
TIM4 15.7 15.1 12.8
TIM5 18 16.9 14.4
TIM6 3.7 3.1 2.8
TIM7 3.5 2.9 2.5
TIM12 8.1 7.8 6.4
TIM13 6.1 5.1 4.7
TIM14 6.3 5.6 4.7
LPTIM1 9.4 9.8 8.3
WWDG 2.4 1.3 1.4
SPI2/I2S2(3) 6.7 6 5.3
SPI3/I2S3(3) 4.8 3.8 3.3
USART2 13.3 12 10.6
USART3 12.8 12 10.3
UART4 11.7 10.7 9.2
UART5 11.7 10.2 8.9
I2C1 10.6 9.6 8.3
I2C2 10.6 9.6 8.3
I2C3 10.7 9.8 8.3
CAN1 8.9 8 6.9
PWR 11.3 11.3 8.9
DAC(4) 6.1 5.1 4.4
UART7 13.3 12 10.3
UART8 12.6 11.6 9.7
Table 35. Peripheral current consumption (continued)
Peripheral
IDD(Typ)(1)
Unit
Scale 1 Scale 2 Scale 3
DS11853 Rev 7 129/230
STM32F722xx STM32F723xx Electrical characteristics
201
APB2
(up to
108 MHz)
TIM1 24.9 23.8 20
µA/MHz
TIM8 24.5 23.7 20
USART1 12.4 11.6 10
USART6 12.3 11.7 10
ADC1(5) 6.3 5.8 4.9
ADC2(5) 6.3 5.6 4.9
ADC3(5) 6.4 5.8 5
SDMMC1 9.1 8.3 7.1
SDMMC2 7 7.2 6
SPI1/I2S1(3) 3.2 3.2 2.6
SPI4 2.9 2.9 2.2
SYSCFG 1 1 0.7
TIM9 9.9 9.1 7.8
TIM10 7 6.4 5.6
TIM11 7.2 6.8 5.7
SPI5 4.8 4.1 3.6
SAI1 5.6 4.9 4.2
SAI2 5.4 4.7 4
USB PHY HS
Controller 8.3 7.9 6.7
1. When the I/O compensation cell is ON, IDD typical value increases by 0.22 mA.
2. The BusMatrix is automatically active when at least one master is ON.
3. To enable an I2S peripheral, first set the I2SMOD bit and then the I2SE bit in the SPI_I2SCFGR register.
4. When the DAC is ON and EN1/2 bits are set in DAC_CR register, add an additional power consumption of
0.75 mA per DAC channel for the analog part.
5. When the ADC is ON (ADON bit set in the ADC_CR2 register), add an additional power consumption of
1.73 mA per ADC for the analog part.
Table 35. Peripheral current consumption (continued)
Peripheral
IDD(Typ)(1)
Unit
Scale 1 Scale 2 Scale 3
Electrical characteristics STM32F722xx STM32F723xx
130/230 DS11853 Rev 7
USB OTG HS and USB OTG HS PHY current consumption (on STM32F723xx
devices)
The MCU is placed under the following conditions:
•STM32 MCU is enumerated as a HID device.
•fHCLK = 216 MHz (Scale 1 + over-drive ON), fHCLK = 168 MHz (Scale 2),
fHCLK = 144 MHz (Scale 3)
The given value is calculated by measuring the difference of current consumption in
case:
– USB is configured but no transfer is done.
– USB is configured and there is a transmission on going.
•Ambient operating temperature is 25 °C, VDD = VDDUSB = 3.3 V.
6.3.8 Wakeup time from low-power modes
The wakeup times given in Table 37 are measured starting from the wakeup event trigger up
to the first instruction executed by the CPU:
•For Stop or Sleep modes: the wakeup event is WFE.
•WKUP (PA0) pin is used to wakeup from Standby, Stop and Sleep modes.
All timings are derived from tests performed under ambient temperature and VDD=3.3 V.
Table 36. USB OTG HS and USB OTG PHY HS current consumption
-
IDD (Typ)
Unit
Scale 1 Scale 2 Scale 3
USB OTG HS and USB OTG HS PHY
current consumption 50.16 44.92 38.98 mA
Table 37. Low-power mode wakeup timings
Symbol Parameter Conditions Typ(1) Max(1) Unit
tWUSLEEP(2) Wakeup from Sleep - 13 13
CPU
clock
cycles
tWUSTOP(2)
Wakeup from Stop mode
with MR/LP regulator in
normal mode
Main regulator is ON 14 14.9
µs
Main regulator is ON and Flash
memory in Deep power down mode 104.1 107.6
Low power regulator is ON 21.4 24.2
Low power regulator is ON and Flash
memory in Deep power down mode 111.5 116.5
DS11853 Rev 7 131/230
STM32F722xx STM32F723xx Electrical characteristics
201
6.3.9 External clock source characteristics
High-speed external user clock generated from an external source
In bypass mode the HSE oscillator is switched off and the input pin is a standard I/O. The
external clock signal has to respect the Table 61: I/O static characteristics. However, the
recommended clock input waveform is shown in Figure 37.
The characteristics given in Table 38 result from tests performed using an high-speed
external clock source, and under ambient temperature and supply voltage conditions
summarized in Table 16.
tWUSTOP(2)
Wakeup from Stop mode
with MR/LP regulator in
Under-drive mode
Main regulator in under-drive mode
(Flash memory in Deep power-down
mode)
107.4 113.2
µs
Low power regulator in under-drive
mode
(Flash memory in Deep power-down
mode)
112.7 120
tWUSTDBY(2) Wakeup from Standby
mode
Exit Standby mode on rising edge 308 313
µs
Exit Standby mode on falling edge 307 313
1. Guaranteed by characterization results.
2. The wakeup times are measured from the wakeup event to the point in which the application code reads the first
Table 37. Low-power mode wakeup timings (continued)
Symbol Parameter Conditions Typ(1) Max(1) Unit
Table 38. High-speed external user clock characteristics
Symbol Parameter Conditions Min Typ Max Unit
fHSE_ext
External user clock source
frequency(1)
-
1-50MHz
VHSEH OSC_IN input pin high level voltage 0.7VDD -V
DD V
VHSEL OSC_IN input pin low level voltage VSS -0.3V
DD
tw(HSE)
tw(HSE)
OSC_IN high or low time(1)
1. Guaranteed by design.
5--
ns
tr(HSE)
tf(HSE)
OSC_IN rise or fall time(1) --10
Cin(HSE) OSC_IN input capacitance(1) --5-pF
DuCy(HSE) Duty cycle - 45 - 55 %
ILOSC_IN Input leakage current VSS ≤VIN ≤VDD --±1µA
amm
Electrical characteristics STM32F722xx STM32F723xx
132/230 DS11853 Rev 7
Low-speed external user clock generated from an external source
In bypass mode the LSE oscillator is switched off and the input pin is a standard I/O. The
external clock signal has to respect the Table 61: I/O static characteristics. However, the
recommended clock input waveform is shown in Figure 38.
The characteristics given in Table 39 result from tests performed using an low-speed
external clock source, and under ambient temperature and supply voltage conditions
summarized in Table 16.
Figure 37. High-speed external clock source AC timing diagram
Table 39. Low-speed external user clock characteristics
Symbol Parameter Conditions Min Typ Max Unit
fLSE_ext
User External clock source
frequency(1)
-
- 32.768 1000 kHz
VLSEH
OSC32_IN input pin high level
voltage 0.7VDD -V
DD V
VLSEL OSC32_IN input pin low level voltage VSS -0.3V
DD
tw(LSE)
tf(LSE)
OSC32_IN high or low time(1) 450 - -
ns
tr(LSE)
tf(LSE)
OSC32_IN rise or fall time(1) --50
Cin(LSE) OSC32_IN input capacitance(1) --5-pF
DuCy(LSE) Duty cycle - 30 - 70 %
ILOSC32_IN Input leakage current VSS ≤VIN ≤VDD --±1µA
1. Guaranteed by design.
ai17528
OSC _I N
External
STM32F
clock source
VHSEH
tf(HSE) tW(HSE)
IL
90 %
10 %
THSE
t
tr(HSE) tW(HSE)
fHSE_ext
VHSEL
DS11853 Rev 7 133/230
STM32F722xx STM32F723xx Electrical characteristics
201
Figure 38. Low-speed external clock source AC timing diagram
High-speed external clock generated from a crystal/ceramic resonator
The high-speed external (HSE) clock can be supplied with a 4 to 26 MHz crystal/ceramic
resonator oscillator. All the information given in this paragraph are based on
characterization results obtained with typical external components specified in Table 40. In
the application, the resonator and the load capacitors have to be placed as close as
possible to the oscillator pins in order to minimize output distortion and startup stabilization
time. Refer to the crystal resonator manufacturer for more details on the resonator
characteristics (frequency, package, accuracy).
Table 40. HSE 4-26 MHz oscillator characteristics(1)
1. Guaranteed by design.
Symbol Parameter Conditions Min Typ Max Unit
fOSC_IN Oscillator frequency - 4 - 26 MHz
RFFeedback resistor - - 200 - kΩ
IDD HSE current consumption
VDD=3.3 V,
ESR= 30 Ω,
CL=5 pF@25 MHz
- 450 -
µA
VDD=3.3 V,
ESR= 30 Ω,
CL=10 pF@25 MHz
- 530 -
ACCHSE(2)
2. This parameter depends on the crystal used in the application. The minimum and maximum values must
be respected to comply with USB standard specifications.
HSE accuracy - −500 - 500 ppm
Gm_crit_max Maximum critical crystal gmStartup - - 1 mA/V
tSU(HSE(3)
3. tSU(HSE) is the startup time measured from the moment it is enabled (by software) to a stabilized 8 MHz
oscillation is reached. This value is based on characterization results. It is measured for a standard crystal
resonator and it can vary significantly with the crystal manufacturer.
Startup time VDD is stabilized - 2 - ms
ai17529
OSC32_IN
External
STM32F
clock source
VLSEH
tf(LSE) tW(LSE)
IL
90%
10%
TLSE
t
tr(LSE) tW(LSE)
fLSE_ext
VLSEL
Electrical characteristics STM32F722xx STM32F723xx
134/230 DS11853 Rev 7
For CL1 and CL2, it is recommended to use high-quality external ceramic capacitors in the
5 pF to 25 pF range (typ.), designed for high-frequency applications, and selected to match
the requirements of the crystal or resonator (see Figure 39). CL1 and CL2 are usually the
same size. The crystal manufacturer typically specifies a load capacitance which is the
series combination of CL1 and CL2. PCB and MCU pin capacitance must be included (10 pF
can be used as a rough estimate of the combined pin and board capacitance) when sizing
CL1 and CL2.
Note: For information on selecting the crystal, refer to the application note AN2867 “Oscillator
design guide for ST microcontrollers” available from the ST website www.st.com.
Figure 39. Typical application with an 8 MHz crystal
1. REXT value depends on the crystal characteristics.
Low-speed external clock generated from a crystal/ceramic resonator
The low-speed external (LSE) clock can be supplied with a 32.768 kHz crystal/ceramic
resonator oscillator. All the information given in this paragraph are based on
characterization results obtained with typical external components specified in Table 41. In
the application, the resonator and the load capacitors have to be placed as close as
possible to the oscillator pins in order to minimize output distortion and startup stabilization
time. Refer to the crystal resonator manufacturer for more details on the resonator
characteristics (frequency, package, accuracy).
Table 41. LSE oscillator characteristics (fLSE = 32.768 kHz) (1)
Symbol Parameter Conditions Min Typ Max Unit
IDD LSE current consumption
LSEDRV[1:0]=00
Low drive capability -250-
nA
LSEDRV[1:0]=10
Medium low drive capability -300-
LSEDRV[1:0]=01
Medium high drive capability -370-
LSEDRV[1:0]=11
High drive capability -480-
ai17530
OSC_OUT
OSC_IN fHSE
CL1
RF
STM32F
8 MHz
resonator
Resonator with
integrated capacitors
Bias
controlled
gain
REXT(1)
CL2
DS11853 Rev 7 135/230
STM32F722xx STM32F723xx Electrical characteristics
201
Note: For information on selecting the crystal, refer to the application note AN2867 “Oscillator
design guide for ST microcontrollers” available from the ST Microelectronics website
www.st.com.
Figure 40. Typical application with a 32.768 kHz crystal
Gm_crit_max Maximum critical crystal gm
LSEDRV[1:0]=00
Low drive capability - - 0.48
µA/V
LSEDRV[1:0]=10
Medium low drive capability - - 0.75
LSEDRV[1:0]=01
Medium high drive capability --1.7
LSEDRV[1:0]=11
High drive capability --2.7
tSU(2) start-up time VDD is stabilized - 2 - s
1. Guaranteed by design.
2. Guaranteed by characterization results. tSU is the start-up time measured from the moment it is enabled
(by software) to a stabilized 32.768 kHz oscillation is reached. This value is measured for a standard
crystal resonator and it can vary significantly with the crystal manufacturer.
Table 41. LSE oscillator characteristics (fLSE = 32.768 kHz) (1) (continued)
Symbol Parameter Conditions Min Typ Max Unit
ai17531a
OSC32_ OU T
OSC32_ IN fLSE
CL1
RF
STM32F
32.768 kHz
resonator
Resonator with
integrated capacitors
Bias
controlled
gain
CL2
// / // / ———
Electrical characteristics STM32F722xx STM32F723xx
136/230 DS11853 Rev 7
6.3.10 Internal clock source characteristics
The parameters given in Table 42 and Table 43 are derived from tests performed under
ambient temperature and VDD supply voltage conditions summarized in Table 16.
High-speed internal (HSI) RC oscillator
Figure 41. ACCHSI versus temperature
1. Guaranteed by characterization results.
Table 42. HSI oscillator characteristics (1)
1. VDD = 3.3 V, PLL OFF, TA = –40 to 105 °C unless otherwise specified.
Symbol Parameter Conditions Min Typ Max Unit
fHSI Frequency - - 16 - MHz
ACCHSI
HSI user trimming step(2)
2. Guaranteed by design.
---1%
Accuracy of the HSI oscillator
TA = –40 to 105 °C(3)
3. Guaranteed by characterization results.
−8-4.5%
TA = –10 to 85 °C(3) −4- 4 %
TA = 25 °C(4)
4. Factory calibrated, parts not soldered.
−1- 1 %
tsu(HSI)(2) HSI oscillator startup time - - 2.2 4 µs
IDD(HSI)(2) HSI oscillator power consumption - - 60 80 µA
MSv41055V1
-8
-6
-4
-2
0
2
4
6
-40 0 25 55 85 105 125
ACCHSI(%)
TA ( °C)
Min Max Typical
Temperature rc) ill
DS11853 Rev 7 137/230
STM32F722xx STM32F723xx Electrical characteristics
201
Low-speed internal (LSI) RC oscillator
Figure 42. LSI deviation versus temperature
6.3.11 PLL characteristics
The parameters given in Table 44 and Table 45 are derived from tests performed under
temperature and VDD supply voltage conditions summarized in Table 16.
Table 43. LSI oscillator characteristics (1)
1. VDD = 3 V, TA = –40 to 105 °C unless otherwise specified.
Symbol Parameter Min Typ Max Unit
fLSI(2)
2. Guaranteed by characterization results.
Frequency 17 32 47 kHz
tsu(LSI)(3)
3. Guaranteed by design.
LSI oscillator startup time - 15 40 µs
IDD(LSI)(3) LSI oscillator power consumption - 0.4 0.6 µA
MS37554V1
Temperature (°C)
-8.0%
-6.0%
-4.0%
-2.0%
0.0%
2.0%
4.0%
6.0%
8.0%
-40°C 0°C 25°C 85°C 105°C 125°C
Min
Max
Typica
l
Normalized deviation (%)
Table 44. Main PLL characteristics
Symbol Parameter Conditions Min Typ Max Unit
fPLL_IN PLL input clock(1) -0.95
(2) 12.10
MHz
fPLL_OUT PLL multiplier output clock - 24 - 216
fPLL48_OUT
48 MHz PLL multiplier output
clock - - 48 75
fVCO_OUT PLL VCO output - 100 - 432
Electrical characteristics STM32F722xx STM32F723xx
138/230 DS11853 Rev 7
tLOCK PLL lock time VCO freq = 100 MHz 75 - 200 µs
VCO freq = 432 MHz 100 - 300
Jitter(3)
Cycle-to-cycle jitter
System clock
216 MHz
RMS - 25 -
ps
peak
to
peak
-±150 -
Period Jitter
RMS - 15 -
peak
to
peak
-±200 -
Main clock output (MCO) for
RMII Ethernet
Cycle to cycle at 50 MHz
on 1000 samples -32 -
Main clock output (MCO) for MII
Ethernet
Cycle to cycle at 25 MHz
on 1000 samples -40 -
Bit Time CAN jitter Cycle to cycle at 1 MHz
on 1000 samples -330 -
IDD(PLL)(4) PLL power consumption on VDD
VCO freq = 100 MHz
VCO freq = 432 MHz
0.15
0.45 -0.40
0.75 mA
IDDA(PLL)(4) PLL power consumption on VDDA
VCO freq = 100 MHz
VCO freq = 432 MHz
0.30
0.55 -0.40
0.85 mA
1. Take care of using the appropriate division factor M to obtain the specified PLL input clock values. The M factor is shared
between PLL and PLLI2S.
2. Guaranteed by design.
3. The use of 2 PLLs in parallel could degraded the Jitter up to +30%.
4. Guaranteed by characterization results.
Table 44. Main PLL characteristics (continued)
Symbol Parameter Conditions Min Typ Max Unit
Table 45. PLLI2S characteristics
Symbol Parameter Conditions Min Typ Max Unit
fPLLI2S_IN PLLI2S input clock(1) -0.95
(2) 12.10
MHz
fPLLI2SQ_OUT
PLLI2S multiplier output clock for
SAI - - - 216
fPLLI2SR_OUT
PLLI2S multiplier output clock for
I2S - - - 216
fVCO_OUT PLLI2S VCO output - 100 - 432
tLOCK PLLI2S lock time VCO freq = 100 MHz 75 - 200 µs
VCO freq = 432 MHz 100 - 300
DS11853 Rev 7 139/230
STM32F722xx STM32F723xx Electrical characteristics
201
Jitter(3)
Master I2S clock jitter
Cycle to cycle at
12.288 MHz on
48KHz period,
N=432, R=5
RMS - 90 - ps
peak
to
peak
- ±280 - ps
Average frequency of
12.288 MHz
N = 432, R = 5
on 1000 samples
-90 -ps
WS I2S clock jitter Cycle to cycle at 48 KHz
on 1000 samples -400 - ps
IDD(PLLI2S)(4) PLLI2S power consumption on
VDD
VCO freq = 100 MHz
VCO freq = 432 MHz
0.15
0.45 -0.40
0.75 mA
IDDA(PLLI2S)(4) PLLI2S power consumption on
VDDA
VCO freq = 100 MHz
VCO freq = 432 MHz
0.30
0.55 -0.40
0.85 mA
1. Take care of using the appropriate division factor M to have the specified PLL input clock values.
2. Guaranteed by design.
3. Value given with main PLL running.
4. Guaranteed by characterization results.
Table 45. PLLI2S characteristics (continued)
Symbol Parameter Conditions Min Typ Max Unit
Table 46. PLLISAI characteristics
Symbol Parameter Conditions Min Typ Max Unit
fPLLSAI_IN PLLSAI input clock(1) -0.95
(2) 12.10
MHz
fPLLSAIP_OUT
PLLSAI multiplier output clock
for 48 MHz - - 48 75
fPLLSAIQ_OUT
PLLSAI multiplier output clock
for SAI - - - 216
fVCO_OUT PLLSAI VCO output - 100 - 432
tLOCK PLLSAI lock time VCO freq = 100 MHz 75 - 200 µs
VCO freq = 432 MHz 100 - 300
Jitter(3)
Master SAI clock jitter
Cycle to cycle at
12.288 MHz on
48KHz period,
N=432, R=5
RMS - 90 - ps
peak
to
peak
- ±280 - ps
Average frequency of
12.288 MHz
N = 432, R = 5
on 1000 samples
-90 -ps
FS clock jitter Cycle to cycle at 48 KHz
on 1000 samples -400 - ps
Electrical characteristics STM32F722xx STM32F723xx
140/230 DS11853 Rev 7
6.3.12 PLL spread spectrum clock generation (SSCG) characteristics
The spread spectrum clock generation (SSCG) feature allows to reduce electromagnetic
interferences (see Table 57: EMI characteristics). It is available only on the main PLL.
Equation 1
The frequency modulation period (MODEPER) is given by the equation below:
fPLL_IN and fMod must be expressed in Hz.
As an example:
If fPLL_IN = 1 MHz, and fMOD = 1 kHz, the modulation depth (MODEPER) is given by
equation 1:
Equation 2
Equation 2 allows to calculate the increment step (INCSTEP):
fVCO_OUT must be expressed in MHz.
With a modulation depth (md) = ±2 % (4 % peak to peak), and PLLN = 240 (in MHz):
IDD(PLLSAI)(4) PLLSAI power consumption on
VDD
VCO freq = 100 MHz
VCO freq = 432 MHz
0.15
0.45 -0.40
0.75 mA
IDDA(PLLSAI)(4) PLLSAI power consumption on
VDDA
VCO freq = 100 MHz
VCO freq = 432 MHz
0.30
0.55 -0.40
0.85 mA
1. Take care of using the appropriate division factor M to have the specified PLL input clock values.
2. Guaranteed by design.
3. Value given with main PLL running.
4. Guaranteed by characterization results.
Table 46. PLLISAI characteristics (continued)
Symbol Parameter Conditions Min Typ Max Unit
Table 47. SSCG parameters constraint
Symbol Parameter Min Typ Max(1) Unit
fMod Modulation frequency - - 10 KHz
md Peak modulation depth 0.25 - 2 %
MODEPER * INCSTEP - - - 215 −1-
1. Guaranteed by design.
MODEPER round fPLL_IN 4f
Mod
×()⁄[]=
MODEPER round 106410
3
×()⁄[]250==
INCSTEP round 215 1–()md PLLN××()100 5×MODEPER×()⁄[]=
DS11853 Rev 7 141/230
STM32F722xx STM32F723xx Electrical characteristics
201
An amplitude quantization error may be generated because the linear modulation profile is
obtained by taking the quantized values (rounded to the nearest integer) of MODPER and
INCSTEP. As a result, the achieved modulation depth is quantized. The percentage
quantized modulation depth is given by the following formula:
As a result:
Figure 43 and Figure 44 show the main PLL output clock waveforms in center spread and
down spread modes, where:
F0 is fPLL_OUT nominal.
Tmode is the modulation period.
md is the modulation depth.
Figure 43. PLL output clock waveforms in center spread mode
Figure 44. PLL output clock waveforms in down spread mode
mdquantized% MODEPER INCSTEP×100×5×()215 1–()PLLN×()⁄=
mdquantized% 250 126×100×5×()215 1–()240×()⁄2.002%(peak)==
Frequency (PLL_OUT)
Time
F0
tmode 2xtmode
md
ai17291
md
Frequency (PLL_OUT)
Time
F0
tmode 2xtmode
2xmd
ai17292b
Electrical characteristics STM32F722xx STM32F723xx
142/230 DS11853 Rev 7
6.3.13 USB OTG HS PHY PLLs characteristics (on STM32F723xx devices)
The parameters given in Table 48 are derived from tests performed under temperature and
VDD supply voltage conditions summarized in Table 16.
6.3.14 USB OTG HS PHY regulator characteristics
The parameters given in Table 50 are derived from tests performed under temperature and
VDD supply voltage conditions summarized in Table 16.
Table 48. USB OTG HS PLL1 characteristics(1)
1. Guaranteed by design.
Symbol Parameter Conditions Min Typ Max Unit
fPLL1_IN PLL1 input clock - 12, 12.5, 16, 24, 25
MHzfPLL1_OUT PLL1 output clock(2)
2. Based on test during characterization.
--60-
fVCO_OUT PLL1 VCO output - 600 - 720
tLOCK PLL1 lock time(2) ---22µs
IDD(PLL1) PLL1 digital power consumption - - - 1.8 mA
IDDA(PLL1) PLL1 analog power consumption - - - 2.75
Table 49. USB OTG HS PLL2 characteristics(1)
1. Guaranteed by design.
Symbol Parameter Conditions Min Typ Max Unit
fPLL2_IN PLL2 input clock - - 60 -
MHzfPLL2_OUT PLL2 output clock(2)
2. Based on test during characterization.
--480-
fVCO_OUT PLL2 VCO output - - 480 -
tLOCK PLL2 lock time(2) ---91µs
IDD(PLL2) PLL2 digital power consumption - - - 2.1 mA
IDDA(PLL2) PLL2 analog power consumption - - - 1.5
Table 50. USB OTG HS PHY regulator characteristics(1)
1. Based on test during characterization.
Symbol Parameter Conditions Min Typ Max Unit
VDD12OTGHS 1.2 V internal voltage on VDD12OTGHS -1.181.21.24V
CEXT External capacitor on VDD12OTGHS - 1.1 2.2 3.3 µF
IDDPHYHSREG Regulator power consumption - 100 120 125 µA
DS11853 Rev 7 143/230
STM32F722xx STM32F723xx Electrical characteristics
201
6.3.15 USB HS PHY external resistor characteristics
(on STM32F723xx devices)
6.3.16 Memory characteristics
Flash memory
The characteristics are given at TA = –40 to 105 °C unless otherwise specified.
The devices are shipped to customers with the Flash memory erased.
Table 51. USB HS PHY external resistor characteristics (on STM32F723xx devices)
Symbol Parameter Conditions Min Typ Max Unit
REXT External calibration resistor connected
(to GND) from OTG_HS_REXT
Required if using
USB HS PHY 2.97 3.00 3.03 kΩ
Table 52. Flash memory characteristics
Symbol Parameter Conditions Min Typ Max Unit
IDD Supply current
Write / Erase 8-bit mode, VDD = 1.7 V - 6.7 -
mAWrite / Erase 16-bit mode, VDD = 2.1 V - 9.2 -
Write / Erase 32-bit mode, VDD = 3.3 V - 12.6 -
Table 53. Flash memory programming
Symbol Parameter Conditions Min(1) Typ Max(1) Unit
tprog Word programming time Program/erase parallelism
(PSIZE) = x 8/16/32 -16100
(2) µs
tERASE16KB Sector (16 KB) erase time
Program/erase parallelism
(PSIZE) = x 8 - 346 418
ms
Program/erase parallelism
(PSIZE) = x 16 - 252 312
Program/erase parallelism
(PSIZE) = x 32 - 208 265
tERASE128KB Sector (128 KB) erase time
Program/erase parallelism
(PSIZE) = x 8 - 1953 2500
ms
Program/erase parallelism
(PSIZE) = x 16 - 1252 1639
Program/erase parallelism
(PSIZE) = x 32 - 927 1322
tERASE64KB Sector (64 KB) erase time
Program/erase parallelism
(PSIZE) = x 8 - 1027 1298
ms
Program/erase parallelism
(PSIZE) = x 16 - 675 840
Program/erase parallelism
(PSIZE) = x 32 - 505 682
PP
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tME Mass erase time
Program/erase parallelism
(PSIZE) = x 8 - 7718 9883
ms
Program/erase parallelism
(PSIZE) = x 16 - 4869 6379
Program/erase parallelism
(PSIZE) = x 32 - 3503 5180
Vprog Programming voltage
32-bit program operation 2.7 - 3.6 V
16-bit program operation 2.1 - 3.6 V
8-bit program operation 1.7 - 3.6 V
1. Guaranteed by characterization results.
2. The maximum programming time is measured after 10 K erase operations.
Table 54. Flash memory programming with VPP
Symbol Parameter Conditions Min(1) Typ Max(1)
1. Guaranteed by design.
Unit
tprog Double word programming
TA = 0 to +40 °C
VDD = 3.3 V
VPP = 8.5 V
-16100
(2)
2. The maximum programming time is measured after 10 K erase operations.
µs
tERASE16KB Sector (16 KB) erase time - 180 -
mstERASE128KB Sector (128 KB) erase time - 900 -
tERASE64KB Sector (64 KB) erase time - 450 -
tME Mass erase time - 6.9 - s
Vprog Programming voltage - 2.7 - 3.6 V
VPP VPP voltage range - 7 - 9 V
IPP
Minimum current sunk on
the VPP pin -10--mA
tVPP(3)
3. VPP should only be connected during programming/erasing.
Cumulative time during
which VPP is applied - - - 1 hour
Table 55. Flash memory endurance and data retention
Symbol Parameter Conditions(1) Value
Unit
Min(2)
NEND Endurance TA = –40 to +85 °C (6 suffix versions)
TA = –40 to +105 °C (7 suffix versions) 10 kcycles
tRET Data retention
1 kcycle(3) at TA = 85 °C 30
Years1 kcycle(3) at TA = 105 °C 10
10 kcycles(3) at TA = 55 °C 20
Table 53. Flash memory programming (continued)
Symbol Parameter Conditions Min(1) Typ Max(1) Unit
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6.3.17 EMC characteristics
Susceptibility tests are performed on a sample basis during device characterization.
Functional EMS (electromagnetic susceptibility)
While a simple application is executed on the device (toggling 2 LEDs through I/O ports).
the device is stressed by two electromagnetic events until a failure occurs. The failure is
indicated by the LEDs:
•Electrostatic discharge (ESD) (positive and negative) is applied to all device pins until
a functional disturbance occurs. This test is compliant with the IEC 61000-4-2 standard.
•FTB: A burst of fast transient voltage (positive and negative) is applied to VDD and VSS
through a 100 pF capacitor, until a functional disturbance occurs. This test is compliant
with the IEC 61000-4-4 standard.
A device reset allows normal operations to be resumed.
The test results are given in Table 56. They are based on the EMS levels and classes
defined in application note AN1709.
As a consequence, it is recommended to add a serial resistor (1 kΏ) located as close as
possible to the MCU to the pins exposed to noise (connected to tracks longer than 50 mm
on PCB).
Designing hardened software to avoid noise problems
EMC characterization and optimization are performed at component level with a typical
application environment and simplified MCU software. It should be noted that good EMC
performance is highly dependent on the user application and the software in particular.
Therefore it is recommended that the user applies EMC software optimization and
prequalification tests in relation with the EMC level requested for his application.
Software recommendations
1. Tj can not go above 125°C (current consumption limitation).
2. Guaranteed by characterization results.
3. Cycling performed over the whole temperature range.
Table 56. EMS characteristics
Symbol Parameter Conditions Level/
Class
VFESD
Voltage limits to be applied on any I/O
pin to induce a functional disturbance
VDD = 3.3 V, TA = +25 °C,
fHCLK = 216 MHz,
conforms to IEC 61000-4-2
2B
VEFTB
Fast transient voltage burst limits to be
applied through 100 pF on VDD and VSS
pins to induce a functional disturbance
VDD = 3.3 V, TA =+25 °C,
fHCLK = 216 MHz,
conforms to IEC 61000-4-2
5A
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The software flowchart must include the management of runaway conditions such as:
•Corrupted program counter
•Unexpected reset
•Critical Data corruption (control registers...)
Prequalification trials
Most of the common failures (unexpected reset and program counter corruption) can be
reproduced by manually forcing a low state on the NRST pin or the Oscillator pins for 1
second.
To complete these trials, ESD stress can be applied directly on the device, over the range of
specification values. When unexpected behavior is detected, the software can be hardened
to prevent unrecoverable errors occurring (see application note AN1015).
Electromagnetic Interference (EMI)
The electromagnetic field emitted by the device are monitored while a simple application,
executing EEMBC code, is running. This emission test is compliant with SAE IEC61967-2
standard which specifies the test board and the pin loading.
6.3.18 Absolute maximum ratings (electrical sensitivity)
Based on three different tests (ESD, LU) using specific measurement methods, the device is
stressed in order to determine its performance in terms of electrical sensitivity.
Electrostatic discharge (ESD)
Electrostatic discharges (a positive then a negative pulse separated by 1 second) are
applied to the pins of each sample according to each pin combination. The sample size
depends on the number of supply pins in the device (3 parts × (n+1) supply pins). This test
conforms to the ANSI/ESDA/JEDEC JS-001-2012 and ANSI/ESD S5.3.1-2009 standards.
Table 57. EMI characteristics
Symbol Parameter Conditions Monitored
frequency band
Max vs.
[fHSE/fCPU]Unit
25/200 MHz
SEMI Peak level
VDD = 3.6 V, TA = 25 °C, conforming to
IEC61967-2 ART/L1-cache OFF, over-drive ON,
all peripheral clocks enabled, clock dithering
disabled.
0.1 MHz to 30 MHz 23
dBµV
30 MHz to 130 MHz 20
130 MHz to 1 GHz 34
1GHz to 2GHz 24
EMI Level 4 -
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Static latchup
Two complementary static tests are required on six parts to assess the latchup
performance:
•A supply overvoltage is applied to each power supply pin
•A current injection is applied to each input, output and configurable I/O pin
These tests are compliant with EIA/JESD 78A IC latchup standard.
6.3.19 I/O current injection characteristics
As a general rule, current injection to the I/O pins, due to external voltage below VSS or
above VDD (for standard, 3 V-capable I/O pins) should be avoided during normal product
operation. However, in order to give an indication of the robustness of the microcontroller in
cases when abnormal injection accidentally happens, susceptibility tests are performed on a
sample basis during device characterization.
Functional susceptibilty to I/O current injection
While a simple application is executed on the device, the device is stressed by injecting
current into the I/O pins programmed in floating input mode. While current is injected into
the I/O pin, one at a time, the device is checked for functional failures.
The failure is indicated by an out of range parameter: ADC error above a certain limit (>5
LSB TUE), out of conventional limits of induced leakage current on adjacent pins (out of –
5 µA/+0 µA range), or other functional failure (for example reset, oscillator frequency
deviation).
Negative induced leakage current is caused by negative injection and positive induced
leakage current by positive injection.
The test results are given in Table 60.
Table 58. ESD absolute maximum ratings
Symbol Ratings Conditions Class Maximum
value(1) Unit
VESD(HBM)
Electrostatic discharge
voltage (human body model)
TA = +25 °C conforming to
ANSI/ESDA/JEDEC JS-001-2012 2 2000
V
VESD(CDM)
Electrostatic discharge
voltage (charge device model)
TA = +25 °C conforming to ANSI/ESD
STM5.3.1-2009, all the packages
excepted WLCSP100
3250
1. Guaranteed by characterization results.
Table 59. Electrical sensitivities
Symbol Parameter Conditions Class
LU Static latch-up class TA = +105 °C conforming to JESD78A II level A
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Note: It is recommended to add a Schottky diode (pin to ground) to analog pins which may
potentially inject negative currents.
6.3.20 I/O port characteristics
General input/output characteristics
Unless otherwise specified, the parameters given in Table 61: I/O static characteristics are
derived from tests performed under the conditions summarized in Table 16. All I/Os are
CMOS and TTL compliant.
Table 60. I/O current injection susceptibility
Symbol Description
Functional susceptibility
Unit
Negative
injection
Positive
injection
IINJ
Injected current on BOOT0, PDR_ON, BYPASS_REG,
OTG_HS_REXT -0 0
mA
Injected current on NRST -0 NA(1)
Injected current on PF9, PF10, PH0_OSCIN, PH1_OSCOUT, PC0,
PC1, PC2, PC3, PB14(2), PB15(2) -0 NA(1)
Injected current on any other FT or FTf pins -5 NA(1)
Injected current on any other pins -5 +5
1. Injection is not possible.
2. PB14 and PB15 in the STM32F723xx devices.
Table 61. I/O static characteristics
Symbol Parameter Conditions Min Typ Max Unit
VIL
FT, TTa and NRST I/O input
low level voltage 1.7 V≤VDD≤ 3.6 V - - 0.35VDD−0.04(1)
V
0.3VDD(2)
BOOT I/O input low level
voltage
1.75 V≤VDD ≤ 3.6 V,
–40 °C≤TA≤ 105 °C --
0.1VDD+0.1(1)
1.7 V≤VDD ≤ 3.6 V,
0°C
≤TA≤ 105 °C --
VIH
FT, TTa and NRST I/O input
high level voltage(5) 1.7 V≤VDD≤ 3.6 V 0.45VDD+0.3(1)
--
V
0.7VDD(2)
BOOT I/O input high level
voltage
1.75 V≤VDD ≤ 3.6 V,
–40 °C≤TA≤ 105 °C 0.17VDD+0.7(1) --
1.7 V≤VDD ≤ 3.6 V,
0°C≤TA≤ 105 °C
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All I/Os are CMOS and TTL compliant (no software configuration required). Their
characteristics cover more than the strict CMOS-technology or TTL parameters. The
coverage of these requirements for FT I/Os is shown in Figure 45.
VHYS
FT, TTa and NRST I/O input
hysteresis 1.7 V≤VDD≤ 3.6 V 10%VDD(3) --
V
BOOT I/O input hysteresis
1.75 V≤VDD ≤ 3.6 V,
–40 °C≤TA≤ 105 °C 0.1 - -
1.7 V≤VDD ≤ 3.6 V,
0°C≤TA≤ 105 °C
Ilkg
I/O input leakage current (4) VSS ≤VIN ≤ VDD --±1µA
I/O FT input leakage current (5) VIN = 5V - - 3
RPU
Weak pull-up
equivalent
resistor(6)
All pins
except for
PA10/PB12
(OTG_FS_ID
,OTG_HS_ID
)VIN = VSS
30 40 50
kΩ
PA10/PB12
(OTG_FS_ID
,OTG_HS_ID
)
71014
RPD
Weak pull-
down
equivalent
resistor(7)
All pins
except for
PA10/PB12
(OTG_FS_ID
,OTG_HS_ID
)VIN = VDD
30 40 50
PA10/PB12
(OTG_FS_ID
,OTG_HS_ID
)
71014
CIO(8) I/O pin capacitance - - 5 - pF
1. Guaranteed by design.
2. Tested in production.
3. With a minimum of 200 mV.
4. Leakage could be higher than the maximum value, if negative current is injected on adjacent pins, Refer to Table 60: I/O
current injection susceptibility
5. To sustain a voltage higher than VDD +0.3 V, the internal pull-up/pull-down resistors must be disabled. Leakage could be
higher than the maximum value, if negative current is injected on adjacent pins.Refer to Table 60: I/O current injection
susceptibility
6. Pull-up resistors are designed with a true resistance in series with a switchable PMOS. This PMOS contribution to the
series resistance is minimum (~10% order).
7. Pull-down resistors are designed with a true resistance in series with a switchable NMOS. This NMOS contribution to the
series resistance is minimum (~10% order).
8. Hysteresis voltage between Schmitt trigger switching levels. Guaranteed by characterization results.
Table 61. I/O static characteristics (continued)
Symbol Parameter Conditions Min Typ Max Unit
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Figure 45. FT I/O input characteristics
Output driving current
The GPIOs (general purpose input/outputs) can sink or source up to ±8 mA, and sink or
source up to ±20 mA (with a relaxed VOL/VOH) except PC13, PC14, PC15 and PI8 which
can sink or source up to ±3mA. When using the PC13 to PC15 and PI8 GPIOs in output
mode, the speed should not exceed 2 MHz with a maximum load of 30 pF.
In the user application, the number of I/O pins which can drive current must be limited to
respect the absolute maximum rating specified in Section 6.2. In particular:
•The sum of the currents sourced by all the I/Os on VDD, plus the maximum Run
consumption of the MCU sourced on VDD, cannot exceed the absolute maximum rating
ΣIVDD (see Table 14).
•The sum of the currents sunk by all the I/Os on VSS plus the maximum Run
consumption of the MCU sunk on VSS cannot exceed the absolute maximum rating
ΣIVSS (see Table 14).
Output voltage levels
Unless otherwise specified, the parameters given in Table 62 are derived from tests
performed under ambient temperature and VDD supply voltage conditions summarized in
Table 16. All I/Os are CMOS and TTL compliant.
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Input/output AC characteristics
The definition and values of input/output AC characteristics are given in Figure 46 and
Table 63, respectively.
Table 62. Output voltage characteristics
Symbol Parameter Conditions Min Max Unit
VOL(1)
1. The IIO current sunk by the device must always respect the absolute maximum rating specified in Table 14.
and the sum of IIO (I/O ports and control pins) must not exceed IVSS.
Output low level voltage for an I/O pin
CMOS port(2)
IIO = +8 mA
2.7 V ≤ VDD ≤ 3.6 V
2. TTL and CMOS outputs are compatible with JEDEC standards JESD36 and JESD52.
-0.4
V
VOH(3)
3. The IIO current sourced by the device must always respect the absolute maximum rating specified in
Table 1 4 and the sum of IIO (I/O ports and control pins) must not exceed IVDD.
Output high level voltage for an I/O pin
except PC14
CMOS port(2)
IIO = -8 mA
2.7 V ≤ VDD ≤ 3.6 V
VDD −0.4 -
VOH(3) Output high level voltage for PC14
CMOS port(2)
IIO = -2 mA
2.7 V ≤ VDD ≤ 3.6 V
VDD −0.4 -
VOL (1) Output low level voltage for an I/O pin
TTL port(2)
IIO =+8mA
2.7 V ≤ VDD ≤ 3.6 V
-0.4
V
VOH (3) Output high level voltage for an I/O pin
except PC14
TTL port(2)
IIO =-8mA
2.7 V ≤ VDD ≤ 3.6 V
2.4 -
VOL(1) Output low level voltage for an I/O pin IIO = +20 mA
2.7 V ≤ VDD ≤ 3.6 V -1.3
(4)
4. Based on characterization data.
V
VOH(3) Output high level voltage for an I/O pin
except PC14
IIO = -20 mA
2.7 V ≤ VDD ≤ 3.6 V VDD −1.3(4) -
VOL(1) Output low level voltage for an I/O pin IIO = +6 mA
1.8 V ≤ VDD ≤ 3.6 V -0.4
(4)
V
VOH(3) Output high level voltage for an I/O pin
except PC14
IIO = -6 mA
1.8 V ≤ VDD ≤ 3.6 V VDD −0.4(4) -
VOL(1) Output low level voltage for an I/O pin IIO = +4 mA
1.7 V ≤ VDD ≤ 3.6V -0.4
(5)
5. Guaranteed by design.
VVOH(3) Output high level voltage for an I/O pin
except PC14
IIO = -4 mA
1.7 V ≤ VDD ≤ 3.6V VDD −0.4(5) -
VOH(3) Output high level voltage for PC14 IIO = -1 mA
1.7 V ≤ VDD ≤ 3.6V VDD −0.4(5) -
xv
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Unless otherwise specified, the parameters given in Table 63 are derived from tests
performed under the ambient temperature and VDD supply voltage conditions summarized
in Table 16.
Table 63. I/O AC characteristics(1)(2)
OSPEEDRy
[1:0] bit
value(1)
Symbol Parameter Conditions Min Typ Max Unit
00
fmax(IO)out Maximum frequency(3)
CL = 50 pF, VDD ≥ 2.7 V - - 4
MHz
CL = 50 pF, VDD ≥ 1.7 V - - 2
CL = 10 pF, VDD ≥ 2.7 V - - 8
CL = 10 pF, VDD ≥ 1.8 V - - 4
CL = 10 pF, VDD ≥ 1.7 V - - 3
tf(IO)out/
tr(IO)out
Output high to low level fall
time and output low to high
level rise time
CL = 50 pF, VDD = 1.7 V to
3.6 V --100ns
01
fmax(IO)out Maximum frequency(3)
CL = 50 pF, VDD≥ 2.7 V - - 25
MHz
CL = 50 pF, VDD≥ 1.8 V - - 12.5
CL = 50 pF, VDD≥ 1.7 V - - 10
CL = 10 pF, VDD ≥ 2.7 V - - 50
CL = 10 pF, VDD≥ 1.8 V - - 20
CL = 10 pF, VDD≥ 1.7 V - - 12.5
tf(IO)out/
tr(IO)out
Output high to low level fall
time and output low to high
level rise time
CL = 50 pF, VDD ≥ 2.7 V - - 10
ns
CL = 10 pF, VDD ≥ 2.7 V - - 6
CL = 50 pF, VDD ≥ 1.7 V - - 20
CL = 10 pF, VDD ≥ 1.7 V - - 10
10
fmax(IO)out Maximum frequency(3)
CL = 40 pF, VDD ≥ 2.7 V - - 50(4)
MHz
CL = 10 pF, VDD ≥ 2.7 V - - 100(4)
CL = 40 pF, VDD ≥ 1.7 V - - 25
CL = 10 pF, VDD ≥ 1.8 V - - 50
CL = 10 pF, VDD ≥ 1.7 V - - 42.5
tf(IO)out/
tr(IO)out
Output high to low level fall
time and output low to high
level rise time
CL = 40 pF, VDD ≥2.7 V - - 6
ns
CL = 10 pF, VDD ≥ 2.7 V - - 4
CL = 40 pF, VDD ≥ 1.7 V - - 10
CL = 10 pF, VDD ≥ 1.7 V - - 6
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Figure 46. I/O AC characteristics definition
11
fmax(IO)out Maximum frequency(3)
CL = 30 pF, VDD ≥ 2.7 V - - 100(4)
MHz
CL = 30 pF, VDD ≥ 1.8 V - - 50
CL = 30 pF, VDD ≥ 1.7 V - - 42.5
CL = 10 pF, VDD≥ 2.7 V - - 180(4)
CL = 10 pF, VDD ≥ 1.8 V - - 100
CL = 10 pF, VDD ≥ 1.7 V - - 72.5
tf(IO)out/
tr(IO)out
Output high to low level fall
time and output low to high
level rise time
CL = 30 pF, VDD ≥ 2.7 V - - 4
ns
CL = 30 pF, VDD ≥1.8 V - - 6
CL = 30 pF, VDD ≥1.7 V - - 7
CL = 10 pF, VDD ≥ 2.7 V - - 2.5
CL = 10 pF, VDD ≥1.8 V - - 3.5
CL = 10 pF, VDD ≥1.7 V - - 4
- tEXTIpw
Pulse width of external signals
detected by the EXTI
controller
-10--ns
1. Guaranteed by design.
2. The I/O speed is configured using the OSPEEDRy[1:0] bits. Refer to the STM32F72xxx and STM32F73xxx reference
manual for a description of the GPIOx_SPEEDR GPIO port output speed register.
3. The maximum frequency is defined in Figure 46.
4. For maximum frequencies above 50 MHz and VDD > 2.4 V, the compensation cell should be used.
Table 63. I/O AC characteristics(1)(2) (continued)
OSPEEDRy
[1:0] bit
value(1)
Symbol Parameter Conditions Min Typ Max Unit
ai14131d
10%
90%
50%
tr(IO)out
OUTPUT
EXTERNAL
ON CL
Maximum frequency is achieved if (tr + tf) ≤ (2/3)T and if the duty cycle is (45-55%)
when loaded by CL specified in the table “ I/O AC characteristics”.
10%
50%
90%
T
tf(IO)out
DD
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6.3.21 NRST pin characteristics
The NRST pin input driver uses CMOS technology. It is connected to a permanent pull-up
resistor, RPU (see Table 61: I/O static characteristics).
Unless otherwise specified, the parameters given in Table 64 are derived from tests
performed under the ambient temperature and VDD supply voltage conditions summarized
in Table 16.
Figure 47. Recommended NRST pin protection
1. The reset network protects the device against parasitic resets. 0.1 uF capacitor must be placed as close as
possible to the chip.
2. The user must ensure that the level on the NRST pin can go below the VIL(NRST) max level specified in
Table 64. Otherwise the reset is not taken into account by the device.
Table 64. NRST pin characteristics
Symbol Parameter Conditions Min Typ Max Unit
RPU Weak pull-up equivalent resistor(1) VIN = VSS 30 40 50 kΩ
VF(NRST)(2) NRST Input filtered pulse - - - 100 ns
VNF(NRST)(2) NRST Input not filtered pulse VDD > 2.7 V 300 - - ns
TNRST_OUT Generated reset pulse duration Internal Reset source 20 - - µs
1. The pull-up is designed with a true resistance in series with a switchable PMOS. This PMOS contribution to the series
resistance must be minimum (~10% order).
2. Guaranteed by design.
ai14132c
STM32F
RPU
NRST
(2)
VDD
Filter
Internal Reset
0.1 μF
External
reset circuit (1)
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6.3.22 TIM timer characteristics
The parameters given in Table 65 are guaranteed by design.
Refer to Section 6.3.20: I/O port characteristics for details on the input/output alternate
function characteristics (output compare, input capture, external clock, PWM output).
6.3.23 RTC characteristics
6.3.24 12-bit ADC characteristics
Unless otherwise specified, the parameters given in Table 67 are derived from tests
performed under the ambient temperature, fPCLK2 frequency and VDDA supply voltage
conditions summarized in Table 16.
Table 65. TIMx characteristics(1)(2)
1. TIMx is used as a general term to refer to the TIM1 to TIM12 timers.
2. Guaranteed by design.
Symbol Parameter Conditions(3)
3. The maximum timer frequency on APB1 or APB2 is up to 216 MHz, by setting the TIMPRE bit in the
RCC_DCKCFGR register, if APBx prescaler is 1 or 2 or 4, then TIMxCLK = HCLK, otherwise TIMxCLK =
4x PCLKx.
Min Max Unit
tres(TIM) Timer resolution time
AHB/APBx prescaler=1
or 2 or 4, fTIMxCLK =
216 MHz
1-
tTIMxCLK
AHB/APBx
prescaler>4, fTIMxCLK =
108 MHz
1-
tTIMxCLK
fEXT Timer external clock
frequency on CH1 to CH4 fTIMxCLK = 216 MHz 0fTIMxCLK/2 MHz
ResTIM Timer resolution - 16/32 bit
tMAX_COUNT Maximum possible count
with 32-bit counter --
65536 ×
65536 tTIMxCLK
Table 66. RTC characteristics
Symbol Parameter Conditions Min Max
-f
PCLK1/RTCCLK frequency ratio Any read/write operation
from/to an RTC register 4-
Table 67. ADC characteristics
Symbol Parameter Conditions Min Typ Max Unit
VDDA Power supply VDDA − VREF+ < 1.2 V 1.7(1) -3.6V
VREF+ Positive reference voltage 1.7(1) -V
DDA V
VREF- Negative reference voltage - - 0 - V
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fADC ADC clock frequency VDDA = 1.7(1) to 2.4 V 0.6 15 18 MHz
VDDA = 2.4 to 3.6 V 0.6 30 36 MHz
fTRIG(2) External trigger frequency
fADC = 30 MHz,
12-bit resolution - - 1764 kHz
---171/f
ADC
VAIN Conversion voltage range(3) -
0
(VSSA or VREF-
tied to ground)
-V
REF+ V
RAIN(2) External input impedance See Equation 1 for
details --50kΩ
RADC(2)(4) Sampling switch resistance - 1.5 - 6 kΩ
CADC(2) Internal sample and hold
capacitor --47pF
tlat(2) Injection trigger conversion
latency
fADC = 30 MHz - - 0.100 µs
---3
(5) 1/fADC
tlatr(2) Regular trigger conversion
latency
fADC = 30 MHz - - 0.067 µs
---2
(5) 1/fADC
tS(2) Sampling time fADC = 30 MHz 0.100 - 16 µs
- 3 - 480 1/fADC
tSTAB(2) Power-up time - - 2 3 µs
tCONV(2) Total conversion time (including
sampling time)
fADC = 30 MHz
12-bit resolution 0.50 - 16.40 µs
fADC = 30 MHz
10-bit resolution 0.43 - 16.34 µs
fADC = 30 MHz
8-bit resolution 0.37 - 16.27 µs
fADC = 30 MHz
6-bit resolution 0.30 - 16.20 µs
9 to 492 (tS for sampling +n-bit resolution for successive
approximation) 1/fADC
fS(2)
Sampling rate
(fADC = 36 MHz, and
tS = 3 ADC cycles)
12-bit resolution
Single ADC - - 2.4 Msps
12-bit resolution
Interleave Dual ADC
mode
- - 4.5 Msps
12-bit resolution
Interleave Triple ADC
mode
- - 7.2 Msps
Table 67. ADC characteristics (continued)
Symbol Parameter Conditions Min Typ Max Unit
ADC fADC
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Equation 1: RAIN max formula
The formula above (Equation 1) is used to determine the maximum external impedance
allowed for an error below 1/4 of LSB. N = 12 (from 12-bit resolution) and k is the number of
sampling periods defined in the ADC_SMPR1 register.
IVREF+(2)
ADC VREF DC current
consumption in conversion
mode
- - 300 500 µA
IVDDA(2)
ADC VDDA DC current
consumption in conversion
mode
--1.61.8mA
1. VDDA minimum value of 1.7 V is obtained with the use of an external power supply supervisor (refer to Section 3.15.2:
Internal reset OFF).
2. Guaranteed by characterization results.
3. VREF+ is internally connected to VDDA and VREF- is internally connected to VSSA.
4. RADC maximum value is given for VDD=1.7 V, and minimum value for VDD=3.3 V.
5. For external triggers, a delay of 1/fPCLK2 must be added to the latency specified in Table 67.
Table 67. ADC characteristics (continued)
Symbol Parameter Conditions Min Typ Max Unit
Table 68. ADC static accuracy at fADC = 18 MHz
Symbol Parameter Test conditions Typ Max(1)
1. Guaranteed by characterization results.
Unit
ET Total unadjusted error
fADC =18 MHz
VDDA = 1.7 to 3.6 V
VREF = 1.7 to 3.6 V
VDDA − VREF < 1.2 V
±3 ±4
LSB
EO Offset error ±2 ±3
EG Gain error ±1 ±3
ED Differential linearity error ±1 ±2
EL Integral linearity error ±2 ±3
Table 69. ADC static accuracy at fADC = 30 MHz
Symbol Parameter Test conditions Typ Max(1)
1. Guaranteed by characterization results.
Unit
ET Total unadjusted error
fADC = 30 MHz,
RAIN < 10 kΩ,
VDDA = 2.4 to 3.6 V,
VREF = 1.7 to 3.6 V,
VDDA − VREF < 1.2 V
±2 ±5
LSB
EO Offset error ±1.5 ±2.5
EG Gain error ±1.5 ±4
ED Differential linearity error ±1 ±2
EL Integral linearity error ±1.5 ±3
RAIN
k0.5–()
fADC CADC 2N2+
()ln××
-------------------------------------------------------------- RADC
–=
ADC fAm: fAm:
Electrical characteristics STM32F722xx STM32F723xx
158/230 DS11853 Rev 7
Note: ADC accuracy vs. negative injection current: injecting a negative current on any analog
input pins should be avoided as this significantly reduces the accuracy of the conversion
being performed on another analog input. It is recommended to add a Schottky diode (pin to
ground) to analog pins which may potentially inject negative currents.
Any positive injection current within the limits specified for IINJ(PIN) and ΣIINJ(PIN) in
Section 6.3.20 does not affect the ADC accuracy.
Table 70. ADC static accuracy at fADC = 36 MHz
Symbol Parameter Test conditions Typ Max(1)
1. Guaranteed by characterization results.
Unit
ET Total unadjusted error
fADC =36 MHz,
VDDA = 2.4 to 3.6 V,
VREF = 1.7 to 3.6 V
VDDA − VREF < 1.2 V
±4 ±7
LSB
EO Offset error ±2 ±3
EG Gain error ±3 ±6
ED Differential linearity error ±2 ±3
EL Integral linearity error ±3 ±6
Table 71. ADC dynamic accuracy at fADC = 18 MHz - limited test conditions(1)
Symbol Parameter Test conditions Min Typ Max Unit
ENOB Effective number of bits fADC =18 MHz
VDDA = VREF+= 1.7 V
Input Frequency = 20 KHz
Temperature = 25 °C
10.3 10.4 - bits
SINAD Signal-to-noise and distortion ratio 64 64.2 -
dBSNR Signal-to-noise ratio 64 65 -
THD Total harmonic distortion −67 −72 -
1. Guaranteed by characterization results.
Table 72. ADC dynamic accuracy at fADC = 36 MHz - limited test conditions(1)
Symbol Parameter Test conditions Min Typ Max Unit
ENOB Effective number of bits fADC =36 MHz
VDDA = VREF+ = 3.3 V
Input Frequency = 20 KHz
Temperature = 25 °C
10.6 10.8 - bits
SINAD Signal-to noise and distortion ratio 66 67 -
dBSNR Signal-to noise ratio 64 68 -
THD Total harmonic distortion −70 −72 -
1. Guaranteed by characterization results.
DDA REF+ ADC DD
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Figure 48. ADC accuracy characteristics
1. See also Table 69.
2. Example of an actual transfer curve.
3. Ideal transfer curve.
4. End point correlation line.
5. ET = Total Unadjusted Error: maximum deviation between the actual and the ideal transfer curves.
EO = Offset Error: deviation between the first actual transition and the first ideal one.
EG = Gain Error: deviation between the last ideal transition and the last actual one.
ED = Differential Linearity Error: maximum deviation between actual steps and the ideal one.
EL = Integral Linearity Error: maximum deviation between any actual transition and the end point
correlation line.
Figure 49. Typical connection diagram using the ADC
1. Refer to Table 67 for the values of RAIN, RADC and CADC.
2. Cparasitic represents the capacitance of the PCB (dependent on soldering and PCB layout quality) plus the
pad capacitance (roughly 5 pF). A high Cparasitic value downgrades conversion accuracy. To remedy this,
fADC should be reduced.
ai14395c
EO
EG
1L SBIDEAL
4095
4094
4093
5
4
3
2
1
0
7
6
1 2 3 456 7 4093 4094 4095 4096
(1)
(2)
ET
ED
EL
(3)
VDDA
VSSA
VREF+
4096 (or depending on package)]
VDDA
4096
[1LSB IDEAL
=
ai17534
STM32F
VDD
AINx
IL±1 μA
0.6 V
VT
RAIN(1)
Cparasitic
VAIN
0.6 V
VT
RADC(1)
CADC(1)
12-bit
converter
Sample and hold ADC
converter
VREh DDA VREn DDA
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General PCB design guidelines
Power supply decoupling should be performed as shown in Figure 50 or Figure 51,
depending on whether VREF+ is connected to VDDA or not. The 10 nF capacitors should be
ceramic (good quality). They should be placed them as close as possible to the chip.
Figure 50. Power supply and reference decoupling (VREF+ not connected to VDDA)
1. VREF+ input is available on all the packages except LQFP64, whereas the VREF– is available only on
UFBGA176 and UFBGA144. When VREF- is not available, it is internally connected to VSSA.
Figure 51. Power supply and reference decoupling (VREF+ connected to VDDA)
1. VREF+ input is available on all the packages except LQFP64, whereas the VREF– is available only on
UFBGA176 and UFBGA144. When VREF- is not available, it is internally connected to VSSA.
STM32
1 μF // 10 nF
1 μF // 10 nF
V
REF+
(1)
V
DDA
V
SSA
/V
REF+
(1)
ai17535c
STM32F
1 μF // 10 nF
ai17536c
VREF+/VDDA
VREF-/VSSA (1)
(1)
EAT
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6.3.25 Temperature sensor characteristics
6.3.26 VBAT monitoring characteristics
6.3.27 Reference voltage
The parameters given in Table 76 are derived from tests performed under ambient
temperature and VDD supply voltage conditions summarized in Table 16.
Table 73. Temperature sensor characteristics
Symbol Parameter Min Typ Max Unit
TL(1) VSENSE linearity with temperature - ±1±2°C
Avg_Slope(1) Average slope - 2.5 - mV/°C
V25(1) Voltage at 25 °C - 0.76 - V
tSTART(2) Startup time - 6 10 µs
TS_temp(2) ADC sampling time when reading the temperature (1 °C accuracy) 10 - - µs
1. Guaranteed by characterization results.
2. Guaranteed by design.
Table 74. Temperature sensor calibration values
Symbol Parameter Memory address
TS_CAL1 TS ADC raw data acquired at temperature of 30 °C, VDDA= 3.3 V 0x1FF0 7A2C - 0x1FF0 7A2D
TS_CAL2 TS ADC raw data acquired at temperature of 110 °C, VDDA= 3.3 V 0x1FF0 7A2E - 0x1FF0 7A2F
Table 75. VBAT monitoring characteristics
Symbol Parameter Min Typ Max Unit
R Resistor bridge for VBAT -50-KΩ
QRatio on VBAT measurement - 4 - -
Er(1) Error on Q –1 - +1 %
TS_vbat(2)(2) ADC sampling time when reading the VBAT
1 mV accuracy 5--µs
1. Guaranteed by design.
2. Shortest sampling time can be determined in the application by multiple iterations.
Table 76. internal reference voltage
Symbol Parameter Conditions Min Typ Max Unit
VREFINT Internal reference voltage –40 °C < TA < +105 °C 1.18 1.21 1.24 V
TS_vrefint(1) ADC sampling time when reading the
internal reference voltage -10--µs
VRERINT_s(2) Internal reference voltage spread over the
temperature range VDD = 3V ± 10mV - 3 5 mV
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6.3.28 DAC electrical characteristics
TCoeff(2) Temperature coefficient - - 30 50 ppm/°C
tSTART(2) Startup time - - 6 10 µs
1. Shortest sampling time can be determined in the application by multiple iterations.
2. Guaranteed by design.
Table 76. internal reference voltage (continued)
Symbol Parameter Conditions Min Typ Max Unit
Table 77. Internal reference voltage calibration values
Symbol Parameter Memory address
VREFIN_CAL Raw data acquired at temperature of 30 °C VDDA = 3.3 V 0x1FF0 7A2A - 0x1FF0 7A2B
Table 78. DAC characteristics
Symbol Parameter Min Typ Max Unit Comments
VDDA Analog supply voltage 1.7(1) -3.6 V -
VREF+ Reference supply voltage 1.7(1) -3.6VV
REF+ ≤ VDDA
VSSA Ground 0 - 0 V -
RLOAD(2) Resistive load
with buffer ON
Connected to
VSSA
5- -kΩ-
Connected to
VDDA
25 - - kΩ-
RO(2) Impedance output with buffer
OFF --15kΩ
When the buffer is OFF, the Minimum
resistive load between DAC_OUT and
VSS to have a 1% accuracy is 1.5 MΩ
CLOAD(2) Capacitive load - - 50 pF Maximum capacitive load at DAC_OUT
pin (when the buffer is ON).
DAC_OUT
min(2)
Lower DAC_OUT voltage
with buffer ON 0.2 - - V
It gives the maximum output excursion of
the DAC.
It corresponds to 12-bit input code
(0x0E0) to (0xF1C) at VREF+ = 3.6 V and
(0x1C7) to (0xE38) at VREF+ = 1.7 V
DAC_OUT
max(2)
Higher DAC_OUT voltage
with buffer ON --
VDDA −
0.2 V
DAC_OUT
min(2)
Lower DAC_OUT voltage
with buffer OFF -0.5 -mV
It gives the maximum output excursion of
the DAC.
DAC_OUT
max(2)
Higher DAC_OUT voltage
with buffer OFF --
VREF+ −
1LSB V
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IVREF+(4)
DAC DC VREF current
consumption in quiescent
mode (Standby mode)
-170240
µA
With no load, worst code (0x800) at
VREF+ = 3.6 V in terms of DC
consumption on the inputs
-5075
With no load, worst code (0xF1C) at
VREF+ = 3.6 V in terms of DC
consumption on the inputs
IDDA(4)
DAC DC VDDA current
consumption in quiescent
mode(3)
-280380µA
With no load, middle code (0x800) on the
inputs
-475625µA
With no load, worst code (0xF1C) at
VREF+ = 3.6 V in terms of DC
consumption on the inputs
DNL(4)
Differential non linearity
Difference between two
consecutive code-1LSB)
- - ±0.5 LSB Given for the DAC in 10-bit configuration.
- - ±2 LSB Given for the DAC in 12-bit configuration.
INL(4)
Integral non linearity
(difference between
measured value at Code i
and the value at Code i on a
line drawn between Code 0
and last Code 1023)
- - ±1 LSB Given for the DAC in 10-bit configuration.
- - ±4 LSB Given for the DAC in 12-bit configuration.
Offset(4)
Offset error
(difference between
measured value at Code
(0x800) and the ideal value =
VREF+/2)
- - ±10 mV Given for the DAC in 12-bit configuration
--±3LSB
Given for the DAC in 10-bit at VREF+ =
3.6 V
--±12LSB
Given for the DAC in 12-bit at VREF+ =
3.6 V
Gain
error(4) Gain error - - ±0.5 % Given for the DAC in 12-bit configuration
tSETTLING(4)
Settling time (full scale: for a
10-bit input code transition
between the lowest and the
highest input codes when
DAC_OUT reaches final
value ±4LSB
-3 6µs
CLOAD ≤ 50 pF,
RLOAD ≥ 5 kΩ
THD(4) Total Harmonic Distortion
Buffer ON -- -dB
CLOAD ≤ 50 pF,
RLOAD ≥ 5 kΩ
Update
rate(2)
Max frequency for a correct
DAC_OUT change when
small variation in the input
code (from code i to i+1LSB)
-- 1MS/s
CLOAD ≤ 50 pF,
RLOAD ≥ 5 kΩ
Table 78. DAC characteristics (continued)
Symbol Parameter Min Typ Max Unit Comments
,___.
Electrical characteristics STM32F722xx STM32F723xx
164/230 DS11853 Rev 7
Figure 52. 12-bit buffered /non-buffered DAC
1. The DAC integrates an output buffer that can be used to reduce the output impedance and to drive external
loads directly without the use of an external operational amplifier. The buffer can be bypassed by
configuring the BOFFx bit in the DAC_CR register.
6.3.29 Communications interfaces
I2C interface characteristics
The I2C interface meets the timings requirements of the I2C-bus specification and user
manual rev. 03 for:
•Standard-mode (Sm): with a bit rate up to 100 kbit/s
•Fast-mode (Fm): with a bit rate up to 400 kbit/s.
•Fast-mode Plus (Fm+): with a bit rate up to 1Mbit/s.
The I2C timings requirements are guaranteed by design when the I2C peripheral is properly
configured (refer to RM0431 reference manual) and when the I2CCLK frequency is greater
than the minimum shown in the table below:
tWAKEUP(4)
Wakeup time from off state
(Setting the ENx bit in the
DAC Control register)
- 6.5 10 µs
CLOAD ≤ 50 pF, RLOAD ≥ 5 kΩ
input code between lowest and highest
possible ones.
PSRR+ (2)
Power supply rejection ratio
(to VDDA) (static DC
measurement)
- –67 –40 dB No RLOAD, CLOAD = 50 pF
1. VDDA minimum value of 1.7 V is obtained with the use of an external power supply supervisor (refer to Section 3.15.2:
Internal reset OFF).
2. Guaranteed by design.
3. The quiescent mode corresponds to a state where the DAC maintains a stable output level to ensure that no dynamic
consumption occurs.
4. Guaranteed by characterization results.
Table 78. DAC characteristics (continued)
Symbol Parameter Min Typ Max Unit Comments
RL
CL
Buffered/Non-buffered DAC
DAC_OUTx
Buffer(1)
12-bit
digital to
analog
converter
ai17157V3
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STM32F722xx STM32F723xx Electrical characteristics
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The SDA and SCL I/O requirements are met with the following restrictions: the SDA and
SCL I/O pins are not “true” open-drain. When configured as open-drain, the PMOS
connected between the I/O pin and VDD is disabled, but is still present.
The 20mA output drive requirement in Fast-mode Plus is not supported. This limits the
maximum load Cload supported in Fm+, which is given by these formulas:
•Tr(SDA/SCL)=0.8473xRpxCload
•Rp(min)= (VDD-VOL(max))/IOL(max)
Where Rp is the I2C lines pull-up. Refer to
Section 6.3.20: I/O port characteristics
for the
I2C I/Os characteristics.
All I2C SDA and SCL I/Os embed an analog filter. Refer to the table below for the analog
filter characteristics:
Table 79. Minimum I2CCLK frequency in all I2C modes
Symbol Parameter Condition Min Unit
f(I2CCLK) I2CCLK
frequency
Standard-mode - 2
MHz
Fast-mode
Analog Filter ON
DNF=0 10
Analog Filter OFF
DNF=1 9
Fast-mode Plus
Analog Filter ON
DNF=0 22.5
Analog Filter OFF
DNF=1 16
Table 80. I2C analog filter characteristics(1)
1. Guaranteed by characterization results.
Symbol Parameter Min Max Unit
tAF
Maximum pulse width of spikes
that are suppressed by the analog
filter
50(2)
2. Spikes with widths below tAF(min) are filtered.
260(3)
3. Spikes with widths above tAF(max) are not filtered
ns
Electrical characteristics STM32F722xx STM32F723xx
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SPI interface characteristics
Unless otherwise specified, the parameters given in Table 81 for the SPI interface are
derived from tests performed under the ambient temperature, fPCLKx frequency and VDD
supply voltage conditions summarized in Table 16, with the following configuration:
•Output speed is set to OSPEEDRy[1:0] = 11
•Capacitive load C = 30 pF
•Measurement points are done at CMOS levels: 0.5VDD
Refer to Section 6.3.20: I/O port characteristics for more details on the input/output alternate
function characteristics (NSS, SCK, MOSI, MISO for SPI).
Table 81. SPI dynamic characteristics(1)
Symbol Parameter Conditions Min Typ Max Unit
fSCK
1/tc(SCK)
SPI clock frequency
Master mode
SPI1,4,5
2.7≤VDD≤3.6
--54
(2)
MHz
Master mode
SPI1,4,5
1.71≤VDD≤3.6
--27
Master transmitter mode
SPI1,4,5
1.71≤VDD≤3.6
--54
Slave receiver mode
SPI1,4,5
1.71≤VDD≤3.6
--54
Slave mode transmitter/full duplex
SPI1,4,5
2.7≤VDD≤3.6
--50
(3)
Slave mode transmitter/full duplex
SPI1,4,5
1.71≤VDD≤3.6
--37
(3)
Master & Slave mode
SPI2,3
1.71≤VDD≤3.6
--27
tsu(NSS) NSS setup time Slave mode, SPI presc = 2 4xTpclk - -
ns
th(NSS) NSS hold time Slave mode, SPI presc = 2 2xTpclk - -
tw(SCKH)
tw(SCKL) SCK high and low time Master mode Tpclk-1 Tpclk Tpclk+1
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Figure 53. SPI timing diagram - slave mode and CPHA = 0
tsu(MI) Data input setup time Master mode 4 - -
ns
tsu(SI) Slave mode 3.5 - -
th(MI) Data input hold time Master mode 3 - -
th(SI) Slave mode 1 - -
ta(SO) Data output access time Slave mode 7 9 21
tdis(SO) Data output disable time Slave mode 5 7 12
tv(SO) Data output valid time
Slave mode 2.7≤VDD≤3.6V - 6.5 10
Slave mode 1.71≤VDD≤3.6V - 6.5 13.5
tv(MO) Master mode - 2 3
th(SO) Data output hold time
Slave mode
1.71≤VDD≤3.6V 4.5 - -
th(MO) Master mode 0 - -
1. Guaranteed by characterization results.
2. Excepting SPI1 with SCK IO=PA5. In this configuration, the maximum achievable frequency is 40 MHz.
3. Maximum frequency of the slave transmitter is determined by sum of Tv(SO) and Tsu(MI) intervals which has to fit into SCK
level phase preceding the SCK sampling edge.This value can be achieved when it communicates with a Master having
Tsu(MI)=0 while signal Duty(SCK)=50%.
Table 81. SPI dynamic characteristics(1) (continued)
Symbol Parameter Conditions Min Typ Max Unit
MSv41658V1
NSS input
CPHA=0
CPOL=0
SCK input
CPHA=0
CPOL=1
MISO output
MOSI input
tsu(SI)
th(SI)
tw(SCKL)
tw(SCKH)
tc(SCK)
tr(SCK)
th(NSS)
tdis(SO)
tsu(NSS)
ta(SO) tv(SO)
Next bits IN
Last bit OUT
First bit IN
First bit OUT Next bits OUT
th(SO) tf(SCK)
Last bit IN
M—HE )‘:¢—>E .‘ 1 *rv“ x EX: 3 :X x
Electrical characteristics STM32F722xx STM32F723xx
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Figure 54. SPI timing diagram - slave mode and CPHA = 1
Figure 55. SPI timing diagram - master mode
MSv41659V1
NSS input
CPHA=1
CPOL=0
SCK input
CPHA=1
CPOL=1
MISO output
MOSI input
tsu(SI) th(SI)
tw(SCKL)
tw(SCKH)
tsu(NSS)
tc(SCK)
ta(SO) tv(SO)
First bit OUT Next bits OUT
Next bits IN
Last bit OUT
th(SO) tr(SCK)
tf(SCK) th(NSS)
tdis(SO)
First bit IN Last bit IN
ai14136c
SCK Output
CPHA= 0
MOSI
OUTPUT
MISO
INP UT
CPHA= 0
LSB OUT
LSB IN
CPOL=0
CPOL=1
B I T1 OUT
NSS input
tc(SCK)
tw(SCKH)
tw(SCKL)
tr(SCK)
tf(SCK)
th(MI)
High
SCK Output
CPHA=1
CPHA=1
CPOL=0
CPOL=1
tsu(MI)
tv(MO) th(MO)
MSB IN BIT6 IN
MSB OUT
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I2S interface characteristics
Unless otherwise specified, the parameters given in Table 82 for the I2S interface are
derived from tests performed under the ambient temperature, fPCLKx frequency and VDD
supply voltage conditions summarized in Table 16, with the following configuration:
•Output speed is set to OSPEEDRy[1:0] = 10
•Capacitive load C = 30 pF
•Measurement points are done at CMOS levels: 0.5VDD
Refer to Section 6.3.20: I/O port characteristics for more details on the input/output alternate
function characteristics (CK, SD, WS).
Note: Refer to RM0431 reference manual I2S section for more details on the sampling frequency
(FS).
fMCK, fCK, and DCK values reflect only the digital peripheral behavior. The values of these
parameters might be slightly impacted by the source clock precision. DCK depends mainly
on the value of ODD bit. The digital contribution leads to a minimum value of
(I2SDIV/(2*I2SDIV+ODD) and a maximum value of (I2SDIV+ODD)/(2*I2SDIV+ODD). FS
maximum value is supported for each mode/condition.
Table 82. I2S dynamic characteristics(1)
Symbol Parameter Conditions Min Max Unit
fMCK I2S Main clock output - 256 x 8K 256xFs(2) MHz
fCK I2S clock frequency Master data: 32 bits - 64xFs MHz
Slave data: 32 bits - 64xFs
DCK I2S clock frequency duty cycle Slave receiver 30 70 %
tv(WS) WS valid time Master mode - 3
ns
th(WS) WS hold time Master mode 0 -
tsu(WS) WS setup time Slave mode 5 -
th(WS) WS hold time Slave mode 2 -
tsu(SD_MR) Data input setup time Master receiver 2.5 -
tsu(SD_SR) Slave receiver 2.5 -
th(SD_MR) Data input hold time Master receiver 3.5 -
th(SD_SR) Slave receiver 2 -
tv(SD_ST) Data output valid time Slave transmitter (after enable edge) - 12
tv(SD_MT) Master transmitter (after enable edge) - 3
th(SD_ST) Data output hold time Slave transmitter (after enable edge) 5 -
th(SD_MT) Master transmitter (after enable edge) 0 -
1. Guaranteed by characterization results.
2. 256xFs maximum is 49.152 MHz (APB1 Maximum frequency).
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Figure 56. I2S slave timing diagram (Philips protocol)(1)
1. LSB transmit/receive of the previously transmitted byte. No LSB transmit/receive is sent before the first
byte.
Figure 57. I2S master timing diagram (Philips protocol)(1)
1. LSB transmit/receive of the previously transmitted byte. No LSB transmit/receive is sent before the first
byte.
CK Input
CPOL = 0
CPOL = 1
tc(CK)
WS input
SDtransmit
SDreceive
tw(CKH) tw(CKL)
tsu(WS) tv(SD_ST) th(SD_ST)
th(WS)
tsu(SD_SR) th(SD_SR)
MSB receive Bitn receive LSB receive
MSB transmit Bitn transmit LSB transmit
MS46528V1
LSB receive
(1)
LSB transmit
(1)
CK output
CPOL = 0
CPOL = 1
tc(CK)
WS output
SDreceive
SDtransmit
tw(CKH)
tw(CKL)
tsu(SD_MR)
tv(SD_MT) th(SD_MT)
th(WS)
th(SD_MR)
MSB receive Bitn receive LSB receive
MSB transmit Bitn transmit LSB transmit
MS46529V1
tf(CK) tr(CK)
tv(WS)
LSB receive
(1)
LSB transmit
(1)
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SAI characteristics
Unless otherwise specified, the parameters given in Table 8 3 for SAI are derived from tests
performed under the ambient temperature, fPCLKx frequency and VDD supply voltage
conditions summarized in Table 16, with the following configuration:
•Output speed is set to OSPEEDRy[1:0] = 10
•Capacitive load C=30 pF
•Measurement points are performed at CMOS levels: 0.5VDD
Refer to Section 6.3.20: I/O port characteristics for more details on the input/output alternate
function characteristics (SCK,SD,WS).
Table 83. SAI characteristics(1)
Symbol Parameter Conditions Min Max Unit
fMCKL SAI Main clock output - 256x8K 256xFs
MHz
FCK SAI clock frequency(2) Master data: 32 bits - 128xFs(3)
Slave data: 32 bits - 128xFs(3)
tv(FS) FS valid time
Master mode
2.7≤VDD≤3.6V -18
ns
Master mode
1.71≤VDD≤3.6V -20
tsu(FS) FS setup time Slave mode 1 -
th(FS) FS hold time Master mode 7 -
Slave mode 0.5 -
tsu(SD_A_MR) Data input setup time Master receiver 1 -
tsu(SD_B_SR) Slave receiver 2.5 -
th(SD_A_MR) Data input hold time Master receiver 3.5 -
th(SD_B_SR) Slave receiver 0.5 -
tv(SD_B_MT) Data output valid time
Slave transmitter (after enable edge)
2.7≤VDD≤3.6V -11
Slave transmitter (after enable edge)
1.71≤VDD≤3.6V -18
th(SD_B_ST) Data output hold time Slave transmitter (after enable edge) 5 -
tv(SD_A_MT) Data output valid time
Master transmitter (after enable edge)
2.7≤VDD≤3.6V -16
Master transmitter (after enable edge)
1.71≤VDD≤3.6V -18.5
th(SD_A_MT) Data output hold time Master transmitter (after enable edge) 7.5 -
1. Guaranteed by characterization results.
2. APB clock frequency must be at least twice SAI clock frequency.
3. With Fs = 192 KHz.
Electrical characteristics STM32F722xx STM32F723xx
172/230 DS11853 Rev 7
Figure 58. SAI master timing waveforms
Figure 59. SAI slave timing waveforms
MS32771V1
SAI_SCK_X
SAI_FS_X
(output)
1/fSCK
SAI_SD_X
(transmit)
tv(FS)
Slot n
SAI_SD_X
(receive)
th(FS)
Slot n+2
tv(SD_MT) th(SD_MT)
Slot n
tsu(SD_MR) th(SD_MR)
MS32772V1
SAI_SCK_X
SAI_FS_X
(input)
SAI_SD_X
(transmit)
tsu(FS)
Slot n
SAI_SD_X
(receive)
tw(CKH_X) th(FS)
Slot n+2
tv(SD_ST) th(SD_ST)
Slot n
tsu(SD_SR)
tw(CKL_X)
th(SD_SR)
1/fSCK
DS11853 Rev 7 173/230
STM32F722xx STM32F723xx Electrical characteristics
201
USB OTG full speed (FS) characteristics
This interface is present in both the USB OTG HS and USB OTG FS controllers.
Note: When VBUS sensing feature is enabled, PA9 and PB13 should be left at their default state
(floating input), not as alternate function. A typical 200 µA current consumption of the
sensing block (current to voltage conversion to determine the different sessions) can be
observed on PA9 and PB13 when the feature is enabled.
Table 84. USB OTG full speed startup time
Symbol Parameter Max Unit
tSTARTUP(1)
1. Guaranteed by design.
USB OTG full speed transceiver startup time 1 µs
Table 85. USB OTG full speed DC electrical characteristics
Symbol Parameter Conditions Min.
(1)
1. All the voltages are measured from the local ground potential.
Typ. Max.(
1) Unit
Input
levels
VDDUSB
USB OTG full speed
transceiver operating
voltage
-3.0
(2)
2. The USB OTG full speed transceiver functionality is ensured down to 2.7 V but not the full USB full speed
electrical characteristics which are degraded in the 2.7-to-3.0 V VDDUSB voltage range.
-3.6V
VDI(3)
3. Guaranteed by design.
Differential input sensitivity I(USB_FS_DP/DM,
USB_HS_DP/DM) 0.2 - -
VVCM(3) Differential common mode
range Includes VDI range 0.8 - 2.5
VSE(3) Single ended receiver
threshold -1.3-2.0
Output
levels
VOL Static output level low RL of 1.5 kΩ to 3.6 V(4)
4. RL is the load connected on the USB OTG full speed drivers.
--0.3
V
VOH Static output level high RL of 15 kΩ to VSS(4) 2.8 - 3.6
RPD
PA11, PA12
(USB_FS_DP/DM) VIN = VDD 14.25 - 24.8
kΩ
PA9, PB13
(OTG_FS_VBUS,
OTG_HS_VBUS)
VIN = VDD 2.4 5.2 8
RPU
PA12 (USB_FS_DP) VIN = VSS, during idle 0.9 1.25 1.575
PA9, PB13
(OTG_FS_VBUS,
OTG_HS_VBUS)
VIN = VSS, during
reception 0.55 0.95 1.35
2<: 5:="" x="">C
Electrical characteristics STM32F722xx STM32F723xx
174/230 DS11853 Rev 7
Figure 60. USB OTG full speed timings: definition of data signal rise and fall time
USB high speed (HS) characteristics (through ULPI in STM32F722xx devices)
Unless otherwise specified, the parameters given in Table 89 for ULPI are derived from
tests performed under the ambient temperature, fHCLK frequency summarized in Table 88
and VDD supply voltage conditions summarized in Table 87, with the following configuration:
•Output speed is set to OSPEEDRy[1:0] = 11, unless otherwise specified
•Capacitive load C = 20 pF, unless otherwise specified
•Measurement points are done at CMOS levels: 0.5VDD.
Refer to Section 6.3.20: I/O port characteristics for more details on the input/output
characteristics.
Table 86. USB OTG full speed electrical characteristics(1)
1. Guaranteed by design.
Driver characteristics
Symbol Parameter Conditions Min Max Unit
trRise time(2)
2. Measured from 10% to 90% of the data signal. For more detailed informations, please refer to USB
Specification - Chapter 7 (version 2.0).
CL = 50 pF 420ns
tfFall time(2) CL = 50 pF 4 20 ns
trfm Rise/ fall time matching tr/tf90 111 %
VCRS Output signal crossover voltage - 1.3 2.0 V
ZDRV Output driver impedance(3)
3. No external termination series resistors are required on DP (D+) and DM (D-) pins since the matching
impedance is included in the embedded driver.
Driving high or
low 28 44 Ω
Table 87. USB HS DC electrical characteristics
Symbol Parameter Min.(1)
1. All the voltages are measured from the local ground potential.
Max.(1) Unit
Input level VDD USB OTG HS operating voltage 1.7 3.6 V
ai14137b
Cross over
points
Differential
data lines
VCRS
VSS
tftr
XL
DS11853 Rev 7 175/230
STM32F722xx STM32F723xx Electrical characteristics
201
Figure 61. ULPI timing diagram
Table 88. USB HS clock timing parameters(1)
1. Guaranteed by design.
Symbol Parameter Min Typ Max Unit
-fHCLK value to guarantee proper operation of
USB HS interface 30 - - MHz
FSTART_8BIT Frequency (first transition) 8-bit ±10% 54 60 66 MHz
FSTEADY Frequency (steady state) ±500 ppm 59.97 60 60.03 MHz
DSTART_8BIT Duty cycle (first transition) 8-bit ±10% 40 50 60 %
DSTEADY Duty cycle (steady state) ±500 ppm 49.975 50 50.025 %
tSTEADY
Time to reach the steady state frequency and
duty cycle after the first transition --1.4ms
tSTART_DEV Clock startup time after the
de-assertion of SuspendM
Peripheral - - 5.6 ms
tSTART_HOST Host - - -
tPREP
PHY preparation time after the first transition
of the input clock ---µs
Clock
Control In
(ULPI_DIR,
ULPI_NXT)
data In
(8-bit)
Control out
(ULPI_STP)
data out
(8-bit)
tDD
tDC
tHD
tSD
tHC
tSC
ai17361c
tDC
Electrical characteristics STM32F722xx STM32F723xx
176/230 DS11853 Rev 7
USB high speed (HS) characteristics (embedded PHY High speed on
STM32F723xx devices)
Table 89. Dynamic characteristics: USB ULPI(1)
Symbol Parameter Conditions Min. Typ. Max. Unit
tSC Control in (ULPI_DIR, ULPI_NXT) setup time - 1.5 - -
ns
tHC Control in (ULPI_DIR, ULPI_NXT) hold time - 1 - -
tSD Data in setup time - 1.5 - -
tHD Data in hold time - 1 - -
tDC/tDD Data/control output delay
2.7 V < VDD < 3.6 V,
CL = 20 pF and
OSPEEDRy[1:0] = 11
-67.5
--
9.5 11
1.7 V < VDD < 3.6 V,
CL = 15 pF and
OSPEEDRy[1:0] = 11
-
1. Guaranteed by characterization results.
Table 90. USB OTG high speed DC electrical characteristics
Symbol Parameter Conditions Min Typ Max Unit
Vhssq High speed squelch detection threshold - 100 - 150 mV
Vhsdsc High speed disconnect detection threshold - 525 - 625 mV
Vhsdif High speed differential detection threshold - 100 - - mV
Vhscm High speed data signalling common mode voltage
range --50 -500mV
Vhsoi High speed idle level - -10 - 10 mV
Vhsoh High speed data signaling high - 360 - 440 mV
Vhsol High speed data signaling low - -10 - 10 mV
Vchirpj Chirp J level - 700 - 1100 mV
Vchirpk Chirp K level - -900 - -500 mV
Table 91. USB OTG high speed electrical characteristics
Parameter Comments Conditions Min Typ Max Unit
tlr Rise time - 0.5 - - ns
tlf Fall time - 0.5 - - ns
tlrfm Setup time from INHSDRIVERENABLE=1 to the
transition on INHSDATAP/INHSDATAN -10 -- ns
Zdrv Driver output impedance - 40.5 - 49.5 Ω
DS11853 Rev 7 177/230
STM32F722xx STM32F723xx Electrical characteristics
201
CAN (controller area network) interface
Refer to Section 6.3.20: I/O port characteristics for more details on the input/output alternate
function characteristics (CANx_TX and CANx_RX).
6.3.30 FMC characteristics
Unless otherwise specified, the parameters given in Table 93 to Table 106 for the FMC
interface are derived from tests performed under the ambient temperature, fHCLK frequency
and VDD supply voltage conditions summarized in Table 16, with the following configuration:
•Output speed is set to OSPEEDRy[1:0] = 11
•Measurement points are done at CMOS levels: 0.5VDD
Refer to Section 6.3.20: I/O port characteristics for more details on the input/output
characteristics.
Asynchronous waveforms and timings
Figure 62 through Figure 65 represent asynchronous waveforms and Table 93 through
Table 100 provide the corresponding timings. The results shown in these tables are
obtained with the following FMC configuration:
•AddressSetupTime = 0x1
•AddressHoldTime = 0x1
•DataSetupTime = 0x1 (except for asynchronous NWAIT mode , DataSetupTime = 0x5)
•BusTurnAroundDuration = 0x0
•Capcitive load CL = 30 pF
In all timing tables, the THCLK is the HCLK clock period
Table 92. USB FS PHY BCD electrical characteristics
Symbol Parameter Conditions Min Typ Max Unit
IDDUSB
Primary detection mode consumption - - - 300 µA
Secondary detection mode consumption - - - 300
RDAT_LKG Data line leakage resistance - 300 - - kΩ
VDAT_LKG Data line leakage voltage - 0.0 - 3.6 V
RDCP_DAT Dedicated charging port resistance across D+/D- - - - 200 Ω
VLGC_HI Logic high - 2.0 - 3.6
V
VLGC_LOW Logic low - - - 0.8
VLGC Logic threshold - 0.8 - 2.0
VDAT_REF Data detect voltage - 0.25 - 3.6
VDP_SRC D+ source voltage - 0.5 - 3.6
VDM_SRC D- source voltage - 0.5 - 3.6
IDM_SINK D- sink current - 25 - 175
µAIDP_SINK D+ sink current - 25 - 175
IDP_SRC Data contact detect current source - 7 - 30
{ RR T
Electrical characteristics STM32F722xx STM32F723xx
178/230 DS11853 Rev 7
Figure 62. Asynchronous non-multiplexed SRAM/PSRAM/NOR read waveforms
1. Mode 2/B, C and D only. In Mode 1, FMC_NADV is not used.
Data
FMC_NE
FMC_NBL[1:0]
FMC_D[15:0]
t
v(BL_NE)
th(Data_NE)
FMC_NOE
Address
FMC_A[25:0]
t
v(A_NE)
FMC_NWE
tsu(Data_NE)
tw(NE)
MS32753V1
w(NOE)
ttv(NOE_NE) th(NE_NOE)
th(Data_NOE)
th(A_NOE)
th(BL_NOE)
tsu(Data_NOE)
FMC_NADV (1)
tv(NADV_NE)
tw(NADV)
FMC_NWAIT
tsu(NWAIT_NE)
th(NE_NWAIT)
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STM32F722xx STM32F723xx Electrical characteristics
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Table 93. Asynchronous non-multiplexed SRAM/PSRAM/NOR read timings(1)
1. CL = 30 pF.
Symbol Parameter Min Max Unit
tw(NE) FMC_NE low time 2Thclk -1 2Thclk +1
ns
tv(NOE_NE) FMC_NEx low to FMC_NOE low 0 0.5
tw(NOE) FMC_NOE low time 2Thclk -1 2Thclk +1
th(NE_NOE) FMC_NOE high to FMC_NE high hold time 0 -
tv(A_NE) FMC_NEx low to FMC_A valid - 0.5
th(A_NOE) Address hold time after FMC_NOE high 0 -
tv(BL_NE) FMC_NEx low to FMC_BL valid - 0.5
th(BL_NOE) FMC_BL hold time after FMC_NOE high 0 -
tsu(Data_NE) Data to FMC_NEx high setup time Thclk -1.5 -
tsu(Data_NOE) Data to FMC_NOEx high setup time Thclk -1.5 -
th(Data_NOE) Data hold time after FMC_NOE high 0 -
th(Data_NE) Data hold time after FMC_NEx high 0 -
tv(NADV_NE) FMC_NEx low to FMC_NADV low - 0
tw(NADV) FMC_NADV low time - Thclk -0.5
Table 94. Asynchronous non-multiplexed SRAM/PSRAM/NOR read - NWAIT
timings(1)
1. Guaranteed by characterization results.
Symbol Parameter Min Max Unit
tw(NE) FMC_NE low time 7Thclk +1 7Thclk +1
ns
tw(NOE) FMC_NWE low time 5Thclk -1 5Thclk +1
tw(NWAIT) FMC_NWAIT low time Thclk -0.5 -
tsu(NWAIT_NE) FMC_NWAIT valid before FMC_NEx high 5Thclk +1.5 -
th(NE_NWAIT) FMC_NEx hold time after FMC_NWAIT invalid 4Thclk +1 -
Electrical characteristics STM32F722xx STM32F723xx
180/230 DS11853 Rev 7
Figure 63. Asynchronous non-multiplexed SRAM/PSRAM/NOR write waveforms
1. Mode 2/B, C and D only. In Mode 1, FMC_NADV is not used.
Table 95. Asynchronous non-multiplexed SRAM/PSRAM/NOR write timings(1)
1. Guaranteed by characterization results.
Symbol Parameter Min Max Unit
tw(NE) FMC_NE low time 3Thclk +1 3Thclk +1
ns
tv(NWE_NE) FMC_NEx low to FMC_NWE low Thclk - 0.5 Thclk +0.5
tw(NWE) FMC_NWE low time Thclk - 1.5 Thclk +0.5
th(NE_NWE) FMC_NWE high to FMC_NE high hold time Thclk -
tv(A_NE) FMC_NEx low to FMC_A valid - 0
th(A_NWE) Address hold time after FMC_NWE high Thclk - 0.5 -
tv(BL_NE) FMC_NEx low to FMC_BL valid - 0.5
th(BL_NWE) FMC_BL hold time after FMC_NWE high Thclk - 0.5 -
tv(Data_NE) Data to FMC_NEx low to Data valid - Thclk +1.5
th(Data_NWE) Data hold time after FMC_NWE high Thclk +0.5 -
tv(NADV_NE) FMC_NEx low to FMC_NADV low - 0
tw(NADV) FMC_NADV low time - Thclk - 0.5
NBL
Data
FMC_NEx
FMC_NBL[1:0]
FMC_D[15:0]
t
v(BL_NE)
th(Data_NWE)
FMC_NOE
Address
FMC_A[25:0]
t
v(A_NE)
tw(NWE)
FMC_NWE
tv(NWE_NE) th(NE_NWE)
th(A_NWE)
th(BL_NWE)
tv(Data_NE)
tw(NE)
MS32754V1
FMC_NADV (1)
tv(NADV_NE)
tw(NADV)
FMC_NWAIT
tsu(NWAIT_NE)
th(NE_NWAIT)
;—>
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STM32F722xx STM32F723xx Electrical characteristics
201
Figure 64. Asynchronous multiplexed PSRAM/NOR read waveforms
Table 96. Asynchronous non-multiplexed SRAM/PSRAM/NOR write - NWAIT
timings(1)
1. Guaranteed by characterization results.
Symbol Parameter Min Max Unit
tw(NE) FMC_NE low time 8Thclk -1 8Thclk +1
ns
tw(NWE) FMC_NWE low time 6Thclk -1.5 6Thclk +0.5
tsu(NWAIT_NE) FMC_NWAIT valid before FMC_NEx high 6Thclk -1 -
th(NE_NWAIT)
FMC_NEx hold time after FMC_NWAIT
invalid 4Thclk + 2 -
NBL
Data
FMC_ NBL[1:0]
FMC_ AD[15:0]
t
v(BL_NE)
th(Data_NE)
Address
FMC_ A[25:16]
t
v(A_NE)
FMC_NWE
tv(A_NE)
MS32755V1
Address
FMC_NADV
tv(NADV_NE)
tw(NADV)
tsu(Data_NE)
t
h(AD_NADV)
FMC_ NE
FMC_NOE
tw(NE)
tw(NOE)
tv(NOE_NE) th(NE_NOE)
th(A_NOE)
th(BL_NOE)
tsu(Data_NOE) th(Data_NOE)
FMC_NWAIT
tsu(NWAIT_NE)
th(NE_NWAIT)
Electrical characteristics STM32F722xx STM32F723xx
182/230 DS11853 Rev 7
Table 97. Asynchronous multiplexed PSRAM/NOR read timings(1)
1. Guaranteed by characterization results.
Symbol Parameter Min Max Unit
tw(NE) FMC_NE low time 3Thclk -1 3Thclk +1
ns
tv(NOE_NE) FMC_NEx low to FMC_NOE low 2Thclk 2Thclk +0.5
ttw(NOE) FMC_NOE low time Thclk -1 Thclk +1
th(NE_NOE) FMC_NOE high to FMC_NE high hold time 0 -
tv(A_NE) FMC_NEx low to FMC_A valid - 0.5
tv(NADV_NE) FMC_NEx low to FMC_NADV low 0 0.5
tw(NADV) FMC_NADV low time Thclk -0.5 Thclk +1
th(AD_NADV)
FMC_AD(address) valid hold time after
FMC_NADV high) Thclk +0.5 -
th(A_NOE) Address hold time after FMC_NOE high Thclk -0.5 -
th(BL_NOE) FMC_BL time after FMC_NOE high 0 -
tv(BL_NE) FMC_NEx low to FMC_BL valid - 0.5
tsu(Data_NE) Data to FMC_NEx high setup time Thclk -1.5 -
tsu(Data_NOE) Data to FMC_NOE high setup time Thclk -1.5 -
th(Data_NE) Data hold time after FMC_NEx high 0 -
th(Data_NOE) Data hold time after FMC_NOE high 0 -
Table 98. Asynchronous multiplexed PSRAM/NOR read-NWAIT timings(1)
1. Guaranteed by characterization results.
Symbol Parameter Min Max Unit
tw(NE) FMC_NE low time 8Thclk -1 8Thclk +1
ns
tw(NOE) FMC_NWE low time 5Thclk -1.5 8Thclk +0.5
tsu(NWAIT_NE) FMC_NWAIT valid before FMC_NEx high 5Thclk +1.5 -
th(NE_NWAIT)
FMC_NEx hold time after FMC_NWAIT
invalid 4Thclk +1 -
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STM32F722xx STM32F723xx Electrical characteristics
201
Figure 65. Asynchronous multiplexed PSRAM/NOR write waveforms
Table 99. Asynchronous multiplexed PSRAM/NOR write timings(1)
Symbol Parameter Min Max Unit
tw(NE) FMC_NE low time 4Thclk -1 4Thclk +1
ns
tv(NWE_NE) FMC_NEx low to FMC_NWE low Thclk -0.5 Thclk +0.5
tw(NWE) FMC_NWE low time 2Thclk -0.5 2Thclk +0.5
th(NE_NWE) FMC_NWE high to FMC_NE high hold time Thclk -0.5 -
tv(A_NE) FMC_NEx low to FMC_A valid - 0
tv(NADV_NE) FMC_NEx low to FMC_NADV low 0 0.5
tw(NADV) FMC_NADV low time Thclk Thclk +1
th(AD_NADV)
FMC_AD(adress) valid hold time after
FMC_NADV high) Thclk +0.5 -
th(A_NWE) Address hold time after FMC_NWE high Thclk +0.5 -
th(BL_NWE) FMC_BL hold time after FMC_NWE high Thclk -0.5 -
tv(BL_NE) FMC_NEx low to FMC_BL valid - 0.5
tv(Data_NADV) FMC_NADV high to Data valid - Thclk +1.5
th(Data_NWE) Data hold time after FMC_NWE high Thclk +0.5 -
Electrical characteristics STM32F722xx STM32F723xx
184/230 DS11853 Rev 7
Synchronous waveforms and timings
Figure 66 through Figure 69 represent synchronous waveforms and Table 101 through
Table 104 provide the corresponding timings. The results shown in these tables are
obtained with the following FMC configuration:
•BurstAccessMode = FMC_BurstAccessMode_Enable;
•MemoryType = FMC_MemoryType_CRAM;
•WriteBurst = FMC_WriteBurst_Enable;
•CLKDivision = 1;
•DataLatency = 1 for NOR Flash; DataLatency = 0 for PSRAM
•CL = 30 pF on data and address lines. CL = 10 pF on FMC_CLK unless otherwise
specified.
In all timing tables, the THCLK is the HCLK clock period.
–For
2.7 V≤ VDD≤ 3.6 V, maximum FMC_CLK = 108 MHz at CL=20 pF or 90 MHz at
CL=30 pF (on FMC_CLK).
–For 1.71 V≤ VDD<2.7 V, maximum FMC_CLK = 70 MHz at CL=10 pF (on FMC_CLK).
1. Guaranteed by characterization results.
Table 100. Asynchronous multiplexed PSRAM/NOR write-NWAIT timings(1)
1. Guaranteed by characterization results.
Symbol Parameter Min Max Unit
tw(NE) FMC_NE low time 9Thclk - 1 9Thclk + 1
ns
tw(NWE) FMC_NWE low time 7Thclk -0.5 7Thclk + 0.5
tsu(NWAIT_NE) FMC_NWAIT valid before FMC_NEx high 6Thclk + 2 -
th(NE_NWAIT)
FMC_NEx hold time after FMC_NWAIT
invalid 4Thclk - 1 -
M332757w
DS11853 Rev 7 185/230
STM32F722xx STM32F723xx Electrical characteristics
201
Figure 66. Synchronous multiplexed NOR/PSRAM read timings
FMC_CLK
FMC_NEx
FMC_NADV
FMC_A[25:16]
FMC_NOE
FMC_AD[15:0] AD[15:0] D1 D2
FMC_NWAIT
(WAITCFG = 1b,
WAITPOL + 0b)
FMC_NWAIT
(WAITCFG = 0b,
WAITPOL + 0b)
tw(CLK) tw(CLK)
Data latency = 0
BUSTURN = 0
td(CLKL-NExL) td(CLKH-NExH)
td(CLKL-NADVL)
td(CLKL-AV)
td(CLKL-NADVH)
td(CLKH-AIV)
td(CLKL-NOEL) td(CLKH-NOEH)
td(CLKL-ADV)
td(CLKL-ADIV)
tsu(ADV-CLKH)
th(CLKH-ADV)
tsu(ADV-CLKH) th(CLKH-ADV)
tsu(NWAITV-CLKH) th(CLKH-NWAITV)
tsu(NWAITV-CLKH) th(CLKH-NWAITV)
tsu(NWAITV-CLKH) th(CLKH-NWAITV)
MS32757V1
Electrical characteristics STM32F722xx STM32F723xx
186/230 DS11853 Rev 7
Table 101. Synchronous multiplexed NOR/PSRAM read timings(1)
1. Guaranteed by characterization results.
Symbol Parameter Min Max Unit
tw(CLK) FMC_CLK period 2Thclk - 0.5 -
ns
td(CLKL-NExL) FMC_CLK low to FMC_NEx low (x=0..2) - 2
td(CLKH_NExH) FMC_CLK high to FMC_NEx high (x= 0…2) Thclk + 0.5 -
td(CLKL-NADVL) FMC_CLK low to FMC_NADV low - 1
td(CLKL-NADVH) FMC_CLK low to FMC_NADV high 0 -
td(CLKL-AV) FMC_CLK low to FMC_Ax valid (x=16…25) - 3
td(CLKH-AIV) FMC_CLK high to FMC_Ax invalid (x=16…25) Thclk -
td(CLKL-NOEL) FMC_CLK low to FMC_NOE low - 2
td(CLKH-NOEH) FMC_CLK high to FMC_NOE high Thclk - 0.5 -
td(CLKL-ADV) FMC_CLK low to FMC_AD[15:0] valid - 2
td(CLKL-ADIV) FMC_CLK low to FMC_AD[15:0] invalid 0 -
tsu(ADV-CLKH)
FMC_A/D[15:0] valid data before FMC_CLK
high 0.5 -
th(CLKH-ADV) FMC_A/D[15:0] valid data after FMC_CLK high 4 -
tsu(NWAIT-CLKH) FMC_NWAIT valid before FMC_CLK high 2 -
th(CLKH-NWAIT) FMC_NWAIT valid after FMC_CLK high 3 -
DS11853 Rev 7 187/230
STM32F722xx STM32F723xx Electrical characteristics
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Figure 67. Synchronous multiplexed PSRAM write timings
FMC_CLK
FMC_NEx
FMC_NADV
FMC_A[25:16]
FMC_NWE
FMC_AD[15:0] AD[15:0] D1 D2
FMC_NWAIT
(WAITCFG = 0b,
WAITPOL + 0b)
tw(CLK) tw(CLK)
Data latency = 0
BUSTURN = 0
td(CLKL-NExL) td(CLKH-NExH)
td(CLKL-NADVL)
td(CLKL-AV)
td(CLKL-NADVH)
td(CLKH-AIV)
td(CLKH-NWEH)
td(CLKL-NWEL)
td(CLKH-NBLH)
td(CLKL-ADV)
td(CLKL-ADIV) td(CLKL-Data)
tsu(NWAITV-CLKH) th(CLKH-NWAITV)
MS32758V1
td(CLKL-Data)
FMC_NBL
Electrical characteristics STM32F722xx STM32F723xx
188/230 DS11853 Rev 7
Table 102. Synchronous multiplexed PSRAM write timings(1)
1. Guaranteed by characterization results.
Symbol Parameter Min Max Unit
tw(CLK) FMC_CLK period 2Thclk - 0.5 -
ns
td(CLKL-NExL) FMC_CLK low to FMC_NEx low (x=0..2) - 2
td(CLKH-NExH) FMC_CLK high to FMC_NEx high (x= 0…2) Thclk +0.5 -
td(CLKL-NADVL) FMC_CLK low to FMC_NADV low - 1
td(CLKL-NADVH) FMC_CLK low to FMC_NADV high 0 -
td(CLKL-AV) FMC_CLK low to FMC_Ax valid (x=16…25) - 3
td(CLKH-AIV) FMC_CLK high to FMC_Ax invalid (x=16…25) Thclk -
td(CLKL-NWEL) FMC_CLK low to FMC_NWE low - 1.5
t(CLKH-NWEH) FMC_CLK high to FMC_NWE high Thclk +0.5 -
td(CLKL-ADV) FMC_CLK low to FMC_AD[15:0] valid - 3
td(CLKL-ADIV) FMC_CLK low to FMC_AD[15:0] invalid 0 -
td(CLKL-DATA) FMC_A/D[15:0] valid data after FMC_CLK low - 3
td(CLKL-NBLL) FMC_CLK low to FMC_NBL low - 2
td(CLKH-NBLH) FMC_CLK high to FMC_NBL high Thclk +0.5 -
tsu(NWAIT-CLKH) FMC_NWAIT valid before FMC_CLK high 2 -
th(CLKH-NWAIT) FMC_NWAIT valid after FMC_CLK high 3 -
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Figure 68. Synchronous non-multiplexed NOR/PSRAM read timings
Table 103. Synchronous non-multiplexed NOR/PSRAM read timings(1)
Symbol Parameter Min Max Unit
tw(CLK) FMC_CLK period 2Thclk - 0.5 -
ns
t(CLKL-NExL) FMC_CLK low to FMC_NEx low (x=0..2) - 2
td(CLKH-NExH) FMC_CLK high to FMC_NEx high (x= 0…2) Thclk +0.5 -
td(CLKL-NADVL) FMC_CLK low to FMC_NADV low - 0.5
td(CLKL-NADVH) FMC_CLK low to FMC_NADV high 0 -
td(CLKL-AV) FMC_CLK low to FMC_Ax valid (x=16…25) - 3
td(CLKH-AIV) FMC_CLK high to FMC_Ax invalid (x=16…25) Thclk -
td(CLKL-NOEL) FMC_CLK low to FMC_NOE low - 2
td(CLKH-NOEH) FMC_CLK high to FMC_NOE high Thclk -0.5 -
tsu(DV-CLKH) FMC_D[15:0] valid data before FMC_CLK high 0.5 -
th(CLKH-DV) FMC_D[15:0] valid data after FMC_CLK high 4 -
t(NWAIT-CLKH) FMC_NWAIT valid before FMC_CLK high 2 -
th(CLKH-NWAIT) FMC_NWAIT valid after FMC_CLK high 3 -
FMC_CLK
FMC_NEx
FMC_A[25:0]
FMC_NOE
FMC_D[15:0] D1 D2
FMC_NWAIT
(WAITCFG = 1b,
WAITPOL + 0b)
FMC_NWAIT
(WAITCFG = 0b,
WAITPOL + 0b)
tw(CLK) tw(CLK)
Data latency = 0
td(CLKL-NExL) td(CLKH-NExH)
td(CLKL-AV) td(CLKH-AIV)
td(CLKL-NOEL) td(CLKH-NOEH)
tsu(DV-CLKH) th(CLKH-DV)
tsu(DV-CLKH) th(CLKH-DV)
tsu(NWAITV-CLKH) th(CLKH-NWAITV)
tsu(NWAITV-CLKH) th(CLKH-NWAITV)
tsu(NWAITV-CLKH) th(CLKH-NWAITV)
MS32759V1
FMC_NADV
td(CLKL-NADVL) td(CLKL-NADVH)
Electrical characteristics STM32F722xx STM32F723xx
190/230 DS11853 Rev 7
Figure 69. Synchronous non-multiplexed PSRAM write timings
1. Guaranteed by characterization results.
MS32760V1
FMC_CLK
FMC_NEx
FMC_A[25:0]
FMC_NWE
FMC_D[15:0] D1 D2
FMC_NWAIT
(WAITCFG = 0b, WAITPOL + 0b)
tw(CLK) tw(CLK)
Data latency = 0
td(CLKL-NExL) td(CLKH-NExH)
td(CLKL-AV) td(CLKH-AIV)
td(CLKH-NWEH)
td(CLKL-NWEL)
td(CLKL-Data)
tsu(NWAITV-CLKH)
th(CLKH-NWAITV)
FMC_NADV
td(CLKL-NADVL) td(CLKL-NADVH)
td(CLKL-Data)
FMC_NBL
td(CLKH-NBLH)
DS11853 Rev 7 191/230
STM32F722xx STM32F723xx Electrical characteristics
201
NAND controller waveforms and timings
Figure 70 through Figure 73 represent synchronous waveforms, and Table 105 and
Table 106 provide the corresponding timings. The results shown in this table are obtained
with the following FMC configuration:
•COM.FMC_SetupTime = 0x01;
•COM.FMC_WaitSetupTime = 0x03;
•COM.FMC_HoldSetupTime = 0x02;
•COM.FMC_HiZSetupTime = 0x01;
•ATT.FMC_SetupTime = 0x01;
•ATT.FMC_WaitSetupTime = 0x03;
•ATT.FMC_HoldSetupTime = 0x02;
•ATT.FMC_HiZSetupTime = 0x01;
•Bank = FMC_Bank_NAND;
•MemoryDataWidth = FMC_MemoryDataWidth_16b;
•ECC = FMC_ECC_Enable;
•ECCPageSize = FMC_ECCPageSize_512Bytes;
•TCLRSetupTime = 0;
•TARSetupTime = 0.
In all timing tables, the THCLK is the HCLK clock period.
Table 104. Synchronous non-multiplexed PSRAM write timings(1)
1. Guaranteed by characterization results.
Symbol Parameter Min Max Unit
t(CLK) FMC_CLK period 2Thclk - 0.5 -
ns
td(CLKL-NExL) FMC_CLK low to FMC_NEx low (x=0..2) - 2
t(CLKH-NExH) FMC_CLK high to FMC_NEx high (x= 0…2) Thclk +0.5 -
td(CLKL-NADVL) FMC_CLK low to FMC_NADV low - 0.5
td(CLKL-NADVH) FMC_CLK low to FMC_NADV high 0 -
td(CLKL-AV) FMC_CLK low to FMC_Ax valid (x=16…25) - 3
td(CLKH-AIV) FMC_CLK high to FMC_Ax invalid (x=16…25) Thclk -
td(CLKL-NWEL) FMC_CLK low to FMC_NWE low - 1.5
td(CLKH-NWEH) FMC_CLK high to FMC_NWE high Thclk +1 -
td(CLKL-Data) FMC_D[15:0] valid data after FMC_CLK low - 3
td(CLKL-NBLL) FMC_CLK low to FMC_NBL low - 2
td(CLKH-NBLH) FMC_CLK high to FMC_NBL high Thclk +1 -
tsu(NWAIT-CLKH) FMC_NWAIT valid before FMC_CLK high 2 -
th(CLKH-NWAIT) FMC_NWAIT valid after FMC_CLK high 3.5 -
fl
Electrical characteristics STM32F722xx STM32F723xx
192/230 DS11853 Rev 7
Figure 70. NAND controller waveforms for read access
Figure 71. NAND controller waveforms for write access
Figure 72. NAND controller waveforms for common memory read access
FMC_NWE
FMC_NOE (NRE)
FMC_D[15:0]
tsu(D-NOE) th(NOE-D)
MS32767V1
ALE (FMC_A17)
CLE (FMC_A16)
FMC_NCEx
td(ALE-NOE) th(NOE-ALE)
MS32768V1
th(NWE-D)
tv(NWE-D)
FMC_NWE
FMC_NOE (NRE)
FMC_D[15:0]
ALE (FMC_A17)
CLE (FMC_A16)
FMC_NCEx
td(ALE-NWE) th(NWE-ALE)
MS32769V1
FMC_NWE
FMC_NOE
FMC_D[15:0]
tw(NOE)
tsu(D-NOE) th(NOE-D)
ALE (FMC_A17)
CLE (FMC_A16)
FMC_NCEx
td(ALE-NOE) th(NOE-ALE)
DS11853 Rev 7 193/230
STM32F722xx STM32F723xx Electrical characteristics
201
Figure 73. NAND controller waveforms for common memory write access
Table 105. Switching characteristics for NAND Flash read cycles(1)
1. Guaranteed by characterization results.
Symbol Parameter Min Max Unit
tw(N0E) FMC_NOE low width 4Thclk -0.5 4Thclk +0.5
ns
tsu(D-NOE) FMC_D[15-0] valid data before FMC_NOE high 11 -
th(NOE-D) FMC_D[15-0] valid data after FMC_NOE high 0 -
td(ALE-NOE) FMC_ALE valid before FMC_NOE low - 3Thclk +1.5
th(NOE-ALE) FMC_NWE high to FMC_ALE invalid 4Thclk - 2 -
Table 106. Switching characteristics for NAND Flash write cycles(1)
1. Guaranteed by characterization results.
Symbol Parameter Min Max Unit
tw(NWE) FMC_NWE low width 4Thclk -0.5 4Thclk +0.5
ns
tv(NWE-D) FMC_NWE low to FMC_D[15-0] valid 0 -
th(NWE-D) FMC_NWE high to FMC_D[15-0] invalid 2Thclk - 1 -
td(D-NWE) FMC_D[15-0] valid before FMC_NWE high 5Thclk - 1 -
td(ALE-NWE) FMC_ALE valid before FMC_NWE low - 3Thclk +1.5
th(NWE-ALE) FMC_NWE high to FMC_ALE invalid 2Thclk - 2 -
MS32770V1
tw(NWE)
th(NWE-D)
tv(NWE-D)
FMC_NWE
FMC_N
OE
FMC_D[15:0]
td(D-NWE)
ALE (FMC_A17)
CLE (FMC_A16)
FMC_NCEx
td(ALE-NOE) th(NOE-ALE)
Electrical characteristics STM32F722xx STM32F723xx
194/230 DS11853 Rev 7
SDRAM waveforms and timings
•CL = 30 pF on data and address lines. CL = 10 pF on FMC_SDCLK unless otherwise
specified.
In all timing tables, the THCLK is the HCLK clock period.
–For 3.0V≤ VDD≤ 3.6 V, maximum FMC_SDCLK= 100 MHz at CL=20 pF (on
FMC_SDCLK).
–For 2.7V≤ VDD≤ 3.6 V, maximum FMC_SDCLK = 90 MHz at CL=30 pF (on
FMC_SDCLK).
– For 1.71 V≤ VDD<1.9 V, maximum FMC_SDCLK = 70 MHz at CL=10 pF (on
FMC_SDCLK).
Figure 74. SDRAM read access waveforms (CL = 1)
MS32751V2
Row n Col1
FMC_SDCLK
FMC_A[12:0]
FMC_SDNRAS
FMC_SDNCAS
FMC_SDNWE
FMC_D[31:0]
FMC_SDNE[1:0]
td(SDCLKL_AddR) td(SDCLKL_AddC)
th(SDCLKL_AddR)
th(SDCLKL_AddC)
td(SDCLKL_SNDE)
tsu(SDCLKH_Data) th(SDCLKH_Data)
Col2 Coli Coln
Data2 Datai DatanData1
th(SDCLKL_SNDE)
td(SDCLKL_NRAS)
td(SDCLKL_NCAS) th(SDCLKL_NCAS)
th(SDCLKL_NRAS)
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Table 107. SDRAM read timings(1)
1. Guaranteed by characterization results.
Symbol Parameter Min Max Unit
tw(SDCLK) FMC_SDCLK period 2Thclk -0.5 2Thclk +0.5
ns
tsu(SDCLKH _Data) Data input setup time 1.5 -
th(SDCLKH_Data) Data input hold time 2 -
td(SDCLKL_Add) Address valid time - 1.5
td(SDCLKL- SDNE) Chip select valid time - 1.5
th(SDCLKL_SDNE) Chip select hold time 0.5 -
td(SDCLKL_SDNRAS) SDNRAS valid time - 1
th(SDCLKL_SDNRAS) SDNRAS hold time 0.5 -
td(SDCLKL_SDNCAS) SDNCAS valid time - 1.5
th(SDCLKL_SDNCAS) SDNCAS hold time 0 -
Table 108. LPSDR SDRAM read timings(1)
1. Guaranteed by characterization results.
Symbol Parameter Min Max Unit
tW(SDCLK) FMC_SDCLK period 2Thclk -0.5 2Thclk +0.5
ns
tsu(SDCLKH_Data) Data input setup time 0 -
th(SDCLKH_Data) Data input hold time 4.5 -
td(SDCLKL_Add) Address valid time - 1.5
td(SDCLKL_SDNE) Chip select valid time - 1.5
th(SDCLKL_SDNE) Chip select hold time 0 -
td(SDCLKL_SDNRAS SDNRAS valid time - 0.5
th(SDCLKL_SDNRAS) SDNRAS hold time 0 -
td(SDCLKL_SDNCAS) SDNCAS valid time - 1.5
th(SDCLKL_SDNCAS) SDNCAS hold time 0 -
Electrical characteristics STM32F722xx STM32F723xx
196/230 DS11853 Rev 7
Figure 75. SDRAM write access waveforms
Table 109. SDRAM write timings(1)
1. Guaranteed by characterization results.
Symbol Parameter Min Max Unit
tw(SDCLK) FMC_SDCLK period 2Thclk -0.5 2Thclk +0.5
ns
td(SDCLKL _Data) Data output valid time - 1.5
th(SDCLKL _Data) Data output hold time 0 -
td(SDCLKL_Add) Address valid time - 1.5
td(SDCLKL_SDNWE) SDNWE valid time - 1.5
th(SDCLKL_SDNWE) SDNWE hold time 0.5 -
td(SDCLKL_ SDNE) Chip select valid time - 1.5
th(SDCLKL-_SDNE) Chip select hold time 0.5 -
td(SDCLKL_SDNRAS) SDNRAS valid time - 1
th(SDCLKL_SDNRAS) SDNRAS hold time 0.5 -
td(SDCLKL_SDNCAS) SDNCAS valid time - 1.5
td(SDCLKL_SDNCAS) SDNCAS hold time 0.5 -
MS32752V2
Row n Col1
FMC_SDCLK
FMC_A[12:0]
FMC_SDNRAS
FMC_SDNCAS
FMC_SDNWE
FMC_D[31:0]
FMC_SDNE[1:0]
td(SDCLKL_AddR) td(SDCLKL_AddC)
th(SDCLKL_AddR)
th(SDCLKL_AddC)
td(SDCLKL_SNDE)
td(SDCLKL_Data)
th(SDCLKL_Data)
Col2 Coli Coln
Data2 Datai DatanData1
th(SDCLKL_SNDE)
td(SDCLKL_NRAS)
td(SDCLKL_NCAS) th(SDCLKL_NCAS)
th(SDCLKL_NRAS)
td(SDCLKL_NWE) th(SDCLKL_NWE)
FMC_NBL[3:0]
td(SDCLKL_NBL)
DS11853 Rev 7 197/230
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6.3.31 Quad-SPI interface characteristics
Unless otherwise specified, the parameters given in Table 111 and Table 112 for Quad-SPI
are derived from tests performed under the ambient temperature, fAHB frequency and VDD
supply voltage conditions summarized in Table 16: General operating conditions, with the
following configuration:
•Output speed is set to OSPEEDRy[1:0] = 11
•Capacitive load C = 20 pF
•Measurement points are done at CMOS levels: 0.5 ₓVDD
Refer to Section 6.3.20: I/O port characteristics for more details on the input/output alternate
function characteristics.
Table 110. LPSDR SDRAM write timings(1)
1. Guaranteed by characterization results.
Symbol Parameter Min Max Unit
tw(SDCLK) FMC_SDCLK period 2Thclk -0.5 2Thclk +0.5
ns
td(SDCLKL _Data) Data output valid time - 2
th(SDCLKL _Data) Data output hold time 0 -
td(SDCLKL_Add) Address valid time - 1.5
td(SDCLKL-SDNWE) SDNWE valid time - 1.5
th(SDCLKL-SDNWE) SDNWE hold time 0 -
td(SDCLKL- SDNE) Chip select valid time - 0.5
th(SDCLKL- SDNE) Chip select hold time 0. -
td(SDCLKL-SDNRAS) SDNRAS valid time - 2
th(SDCLKL-SDNRAS) SDNRAS hold time 0 -
td(SDCLKL-SDNCAS) SDNCAS valid time - 2
td(SDCLKL-SDNCAS) SDNCAS hold time 0 -
Table 111. Quad-SPI characteristics in SDR mode(1)
Symbol Parameter Conditions Min Typ Max Unit
Fck1/t(CK) Quad-SPI clock
frequency
2.7 V≤ VDD<3.6 V
CL=20 pF --108
MHz
1.71 V<VDD<3.6 V
CL=15 pF --100
Electrical characteristics STM32F722xx STM32F723xx
198/230 DS11853 Rev 7
tw(CKH) Quad-SPI clock high
and low time -t(CK)/2 - 0.5 - t(CK)/2 + 0.5
ns
tw(CKL) t(CK)/2 - 0.5 - t(CK)/2 + 0.5
ts(IN) Data input setup time -3- -
th(IN) Data input hold time 1 - -
tv(OUT) Data output valid time 2.7 V<VDD<3.6 V - 1.5 3
1.71 V<VDD<3.6 V - 1.5 2.5
th(OUT) Data output hold time - 0.5 - -
1. Guaranteed by characterization results.
Table 112. Quad-SPI characteristics in DDR mode(1)
1. Guaranteed by characterization results.
Symbol Parameter Conditions Min Typ Max Unit
Fck1/t(CK) Quad-SPI clock frequency
2.7 V<VDD<3.6 V
CL=20 pF --80
MHz
1.8 V<VDD<3.6 V
CL=15 pF --80
1.71 V<VDD<3.6 V
CL=10 pF --80
tw(CKH) Quad-SPI clock high and
low time -
t(CK)/2 -
0.5 -t(CK)/2 +
0.5
ns
tw(CKL) t(CK)/2 -
0.5 -t(CK)/2 +
0.5
ts(IN),
tsf(IN) Data input setup time 2.7 V<VDD<3.6 V 1 - -
1.71 V<VDD<2 V 0.5 - -
thr(IN),
thf(IN) Data input hold time 2.7 V<VDD<3.6 V 2.25 - -
1.71 V<VDD<2 V 2.75 - -
tvr(OUT),
tvf(OUT) Data output valid time
2.7 V<VDD<3.6 V - 9.5 11.5
1.71 V<VDD<3.6 V
DHHC=0 - 9.5 12.25
DHHC=1
Pres=1, 2... -Thclk/2
+2
Thclk/2
+2.5
thr(OUT),
thf(OUT) Data output hold time
DHHC=0 5.5 - -
DHHC=1
Pres=1, 2...
Thclk/2
+0.75 --
Table 111. Quad-SPI characteristics (continued)in SDR mode(1) (continued)
Symbol Parameter Conditions Min Typ Max Unit
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STM32F722xx STM32F723xx Electrical characteristics
201
Figure 76. Quad-SPI timing diagram - SDR mode
Figure 77. Quad-SPI timing diagram - DDR mode
6.3.32 SD/SDIO MMC card host interface (SDMMC) characteristics
Unless otherwise specified, the parameters given in Table 113 for the SDIO/MMC interface
are derived from tests performed under the ambient temperature, fPCLK2 frequency and VDD
supply voltage conditions summarized in Table 16, with the following configuration:
•Output speed is set to OSPEEDRy[1:0] = 11
•Capacitive load C = 30 pF
•Measurement points are done at CMOS levels: 0.5VDD
Refer to Section 6.3.20: I/O port characteristics for more details on the input/output
characteristics.
MSv36878V1
Data output D0 D1 D2
Clock
Data input D0 D1 D2
t(CK) tw(CKH) tw(CKL)
tr(CK) tf(CK)
ts(IN) th(IN)
tv(OUT) th(OUT)
‘W(CKH’) CK _ D. CMD (output) X Hsug' ‘IH D, CMD (mpul) 5mm
Electrical characteristics STM32F722xx STM32F723xx
200/230 DS11853 Rev 7
Figure 78. SDIO high-speed mode
Figure 79. SD default mode
Table 113. Dynamic characteristics: SD / MMC characteristics, VDD=2.7V to 3.6V(1)
Symbol Parameter Conditions Min Typ Max Unit
fPP Clock frequency in data transfer mode - 0 - 50 MHz
- SDMMC_CK/fPCLK2 frequency ratio - - - 8/3 -
tW(CKL) Clock low time fpp =50 MHz 9 10 - ns
tW(CKH) Clock high time fpp =50 MHz 9 10 -
CMD, D inputs (referenced to CK) in MMC and SD HS mode
tISU Input setup time HS fpp =50 MHz 1 - - ns
tIH Input hold time HS fpp =50 MHz 3 - -
CMD, D outputs (referenced to CK) in MMC and SD HS mode
tOV Output valid time HS fpp =50 MHz - 11 12 ns
tOH Output hold time HS fpp =50 MHz 9 - -
DD
DS11853 Rev 7 201/230
STM32F722xx STM32F723xx Electrical characteristics
201
CMD, D inputs (referenced to CK) in SD default mode
tISUD Input setup time SD fpp =25 MHz 1- -
ns
tIHD Input hold time SD fpp =25 MHz 3- -
CMD, D outputs (referenced to CK) in SD default mode
tOVD Output valid default time SD fpp =25 MHz -22.5
ns
tOHD Output hold default time SD fpp =25 MHz 0.5 - -
1. Guaranteed by characterization results,.
Table 113. Dynamic characteristics: SD / MMC characteristics, VDD=2.7V to 3.6V(1) (continued)
Symbol Parameter Conditions Min Typ Max Unit
Table 114. Dynamic characteristics: eMMC characteristics, VDD=1.71V to 1.9V(1)(2)
Symbol Parameter Conditions Min Typ Max Unit
fPP Clock frequency in data transfer mode - 0 - 50 MHz
- SDMMC_CK/fPCLK2 frequency ratio - - - 8/3 -
tW(CKL) Clock low time fpp =50 MHz 9.5 10.5 - ns
tW(CKH) Clock high time fpp =50 MHz 8.5 9.5 -
CMD, D inputs (referenced to CK) in eMMC mode
tISU Input setup time HS fpp =50 MHz 0 - - ns
tIH Input hold time HS fpp =50 MHz 4.5 - -
CMD, D outputs (referenced to CK) in eMMC mode
tOV Output valid time HS fpp =50 MHz - 12 14 ns
tOH Output hold time HS fpp =50 MHz 10.5 - -
1. Guaranteed by characterization results.
2. Cload = 20 pF.
»uA
Package information STM32F722xx STM32F723xx
202/230 DS11853 Rev 7
7 Package information
In order to meet environmental requirements, ST offers these devices in different grades of
ECOPACK packages, depending on their level of environmental compliance. ECOPACK
specifications, grade definitions and product status are available at: www.st.com.
ECOPACK is an ST trademark.
7.1 LQFP64 – 10 x 10 mm, low-profile quad flat package
information
LQFP64 is a 64-pin, 10 x 10 mm low-profile quad flat package.
Figure 80. LQFP64 outline
1. Drawing is not to scale.
5W_ME_V3
A1
A2
A
SEATING PLANE
ccc C
b
C
c
A1
L
L1
K
IDENTIFICATION
PIN 1
D
D1
D3
e
116
17
32
33
48
49
64
E3
E1
E
GAUGE PLANE
0.25 mm
Table 115. LQFP64 mechanical data
Symbol
millimeters inches(1)
Min Typ Max Min Typ Max
A - - 1.60 - - 0.0630
A1 0.05 - 0.15 0.0020 - 0.0059
A2 1.350 1.40 1.45 0.0531 0.0551 0.0571
Hflflflflflflflflflflflflflflfl 7 ,Aggggggflflflflflflflfl <7 flflflflflflflfl="" ”pgephhh="" 7="" hhhhhhhhhhhhh="" 4,:="" flflflflflflfl="" ‘jfii="" h="" +="">
DS11853 Rev 7 203/230
STM32F722xx STM32F723xx Package information
225
Figure 81. LQFP64 recommended footprint
1. Dimensions are in millimeters.
b 0.17 0.22 0.27 0.0067 0.0087 0.0106
c 0.09 - 0.20 0.0035 - 0.0079
D - 12.00 - - 0.4724 -
D1 - 10.00 - - 0.3937 -
D3 - 7.50 - - 0.2953 -
E - 12.00 - - 0.4724 -
E1 - 10.00 - - 0.3937 -
E3 - 7.50 - - 0.2953 -
e - 0.50 - - 0.0197 -
K 0°3.5°7° 0°3.5°7°
L 0.45 0.60 0.75 0.0177 0.0236 0.0295
L1 - 1.00 - - 0.0394 -
ccc - - 0.08 - - 0.0031
1. Values in inches are converted from mm and rounded to 4 decimal digits.
Table 115. LQFP64 mechanical data (continued)
Symbol
millimeters inches(1)
Min Typ Max Min Typ Max
48
32
49
64 17
116
1.2
0.3
33
10.3
12.7
10.3
0.5
7.8
12.7
ai14909c
\\
Package information STM32F722xx STM32F723xx
204/230 DS11853 Rev 7
LQFP64 device marking
The following figure gives an example of topside marking orientation versus pin 1 identifier
location.
The printed markings may differ depending on the supply chain.
Other optional marking or inset/upset marks, which identify the parts throughout supply
chain operations, are not indicated below.
Figure 82. LQFP64 top view example
1. Parts marked as ES or E or accompanied by an engineering sample notification letter are not yet qualified
and therefore not approved for use in production. ST is not responsible for any consequences resulting
from such use. In no event will ST be liable for the customer using any of these engineering samples in
production. ST’s Quality department must be contacted prior to any decision to use these engineering
samples to run a qualification activity.
MSv42090V1
Revision code
STM32F722
Product identification(1)
Date code
YWW
Pin 1
indentifier
RET6
R
DS11853 Rev 7 205/230
STM32F722xx STM32F723xx Package information
225
7.2 LQFP100, 14 x 14 mm low-profile quad flat package
information
LQFP100 is a 100-pin, 14 x 14 mm low-profile quad flat package.
Figure 83. LQFP100 outline
1. Drawing is not to scale.
Table 116. LQPF100 mechanical data
Symbol
millimeters inches(1)
Min Typ Max Min Typ Max
A - - 1.600 - - 0.0630
A1 0.050 - 0.150 0.0020 - 0.0059
A2 1.350 1.400 1.450 0.0531 0.0551 0.0571
b 0.170 0.220 0.270 0.0067 0.0087 0.0106
c 0.090 - 0.200 0.0035 - 0.0079
D 15.800 16.000 16.200 0.6220 0.6299 0.6378
D1 13.800 14.000 14.200 0.5433 0.5512 0.5591
D3 - 12.000 - - 0.4724 -
E 15.800 16.000 16.200 0.6220 0.6299 0.6378
e
IDENTIFICATION
PIN 1
GAUGE PLANE
0.25 mm
SEATING PLANE
D
D1
D3
E3
E1
E
K
ccc C
C
125
26
100
76
75 51
50
1L_ME_V5
A2
A
A1
L1
L
c
b
A1
EEEEEEE EEEEEE AHV J fl: Hflflflflflflflflflfll] Hflflfll] [|[||]|]|] [|[||]|]|]DD[||]|]|] Dflflflflflflflfll] 7 EEEEEE EEEEEE
Package information STM32F722xx STM32F723xx
206/230 DS11853 Rev 7
Figure 84. LQFP100 recommended footprint
1. Dimensions are expressed in millimeters.
E1 13.800 14.000 14.200 0.5433 0.5512 0.5591
E3 - 12.000 - - 0.4724 -
e - 0.500 - - 0.0197 -
L 0.450 0.600 0.750 0.0177 0.0236 0.0295
L1 - 1.000 - - 0.0394 -
k 0°3.5°7° 0°3.5°7°
ccc - - 0.080 - - 0.0031
1. Values in inches are converted from mm and rounded to 4 decimal digits.
Table 116. LQPF100 mechanical data (continued)
Symbol
millimeters inches(1)
Min Typ Max Min Typ Max
75 51
5076 0.5
0.3
16.7 14.3
100 26
12.3
25
1.2
16.7
1
ai14906c
\‘O
DS11853 Rev 7 207/230
STM32F722xx STM32F723xx Package information
225
LQFP100 device marking
The following figure gives an example of topside marking orientation versus pin 1 identifier
location.
The printed markings may differ depending on the supply chain.
Other optional marking or inset/upset marks, which identify the parts throughout supply
chain operations, are not indicated below.
Figure 85. LQFP100 top view example
1. Parts marked as ES or E or accompanied by an engineering sample notification letter are not yet qualified
and therefore not approved for use in production. ST is not responsible for any consequences resulting
from such use. In no event will ST be liable for the customer using any of these engineering samples in
production. ST’s Quality department must be contacted prior to any decision to use these engineering
samples to run a qualification activity.
MS42091V1
STM32F722
VET6 R
Product identification (1)
Revision code
WWY
Date code
Pin 1 identifier
Package information STM32F722xx STM32F723xx
208/230 DS11853 Rev 7
7.3 LQFP144, 20 x 20 mm low-profile quad flat package
information
LQFP144 is a 144-pin, 20 x 20 mm low-profile quad flat package.
Figure 86. LQFP144 outline
1. Drawing is not to scale.
Table 117. LQFP144 mechanical data
Symbol
millimeters inches(1)
Min Typ Max Min Typ Max
A - - 1.600 - - 0.0630
A1 0.050 - 0.150 0.0020 - 0.0059
A2 1.350 1.400 1.450 0.0531 0.0551 0.0571
b 0.170 0.220 0.270 0.0067 0.0087 0.0106
c 0.090 - 0.200 0.0035 - 0.0079
D 21.800 22.000 22.200 0.8583 0.8661 0.874
e
IDENTIFICATION
PIN 1
GAUGE PLANE
0.25 mm
SEATING
PLANE
D
D1
D3
E3
E1
E
K
ccc C
C
136
37
144
109
108 73
72
1A_ME_V3
A2
A
A1
L1
L
c
b
A1
£ HHHHHHHHHHHHflflflflflflflflflflflflflflflflflflflflflfl
DS11853 Rev 7 209/230
STM32F722xx STM32F723xx Package information
225
Figure 87. LQFP144 recommended footprint
1. Dimensions are expressed in millimeters.
D1 19.800 20.000 20.200 0.7795 0.7874 0.7953
D3 - 17.500 - - 0.689 -
E 21.800 22.000 22.200 0.8583 0.8661 0.8740
E1 19.800 20.000 20.200 0.7795 0.7874 0.7953
E3 - 17.500 - - 0.6890 -
e - 0.500 - - 0.0197 -
L 0.450 0.600 0.750 0.0177 0.0236 0.0295
L1 - 1.000 - - 0.0394 -
k 0°3.5°7° 0°3.5°7°
ccc - - 0.080 - - 0.0031
1. Values in inches are converted from mm and rounded to 4 decimal digits.
Table 117. LQFP144 mechanical data (continued)
Symbol
millimeters inches(1)
Min Typ Max Min Typ Max
0.5
0.35
19.9 17.85
22.6
1.35
22.6
19.9
ai14905e
136
37
72
73108
109
144
Package information STM32F722xx STM32F723xx
210/230 DS11853 Rev 7
LQP144 device marking
The following figure gives an example of topside marking orientation versus pin 1 identifier
location.
The printed markings may differ depending on the supply chain.
Other optional marking or inset/upset marks, which identify the parts throughout supply
chain operations, are not indicated below.
Figure 88. LQFP144 top view example
1. Parts marked as ES or E or accompanied by an engineering sample notification letter are not yet qualified
and therefore not approved for use in production. ST is not responsible for any consequences resulting
from such use. In no event will ST be liable for the customer using any of these engineering samples in
production. ST’s Quality department must be contacted prior to any decision to use these engineering
samples to run a qualification activity.
MS42092V1
Pin 1
identifier
R
Revision code
STM32F722ZET6
Product identification(1)
Date code
YWW
DS11853 Rev 7 211/230
STM32F722xx STM32F723xx Package information
225
7.4 LQFP176 24 x 24 mm low-profile quad flat package
information
LQFP176 is a 176-pin, 24 x 24 mm low-profile quad flat package.
Figure 89. LQFP176 outline
1. Drawing is not to scale.
Table 118. LQFP176 mechanical data
Symbol
millimeters inches(1)
Min Typ Max Min Typ Max
A - - 1.600 - - 0.0630
A1 0.050 - 0.150 0.0020 - 0.0059
A2 1.350 - 1.450 0.0531 - 0.0060
b 0.170 - 0.270 0.0067 - 0.0106
C 0.090 - 0.200 0.0035 - 0.0079
D 23.900 - 24.100 0.9409 - 0.9488
1T_ME_V2
A2
A
e
EHE
D
HD
ZD
ZE
b
0.25 mm
gauge plane
A1 L
L1
k
c
IDENTIFICATION
PIN 1
Seating plane
C
A1
Package information STM32F722xx STM32F723xx
212/230 DS11853 Rev 7
E 23.900 - 24.100 0.9409 - 0.9488
e - 0.500 - - 0.0197 -
HD 25.900 - 26.100 1.0200 - 1.0276
HE 25.900 - 26.100 1.0200 - 1.0276
L 0.450 - 0.750 0.0177 - 0.0295
L1 - 1.000 - - 0.0394 -
ZD - 1.250 - - 0.0492 -
ZE - 1.250 - - 0.0492 -
ccc - - 0.080 - - 0.0031
k0 °-7 °0 °-7 °
1. Values in inches are converted from mm and rounded to 4 decimal digits.
Table 118. LQFP176 mechanical data (continued)
Symbol
millimeters inches(1)
Min Typ Max Min Typ Max
HHHHHHHHHHHHHHHHHHHHH HHHHHHHHHHHHHHHHHHWE: UHHHI]I]UHHHHI]HI]HHHI]HI]UUUHHUUUHHHHUUUUHHHHUUUJ WHHHHI]I]HHHHflflflflflflflflflflflflflflflflflflflflflflfl[UHHHHUUUH WHHHHHHHHHHHHHHHHHHHHH HHHHHHHHHHHHHHHHHHHHH
DS11853 Rev 7 213/230
STM32F722xx STM32F723xx Package information
225
Figure 90. LQFP176 recommended footprint
1. Dimensions are expressed in millimeters.
1T_FP_V1
133
132
1.2
0.3
0.5
89
88 1.2
44
45
21.8
26.7
1176
26.7
21.8
Ewe 4/.
Package information STM32F722xx STM32F723xx
214/230 DS11853 Rev 7
LQFP176 device marking
The following figure gives an example of topside marking orientation versus pin 1 identifier
location.
The printed markings may differ depending on the supply chain.
Other optional marking or inset/upset marks, which identify the parts throughout supply
chain operations, are not indicated below.
Figure 91. LQFP176 top view example
1. Parts marked as ES or E or accompanied by an engineering sample notification letter are not yet qualified
and therefore not approved for use in production. ST is not responsible for any consequences resulting
from such use. In no event will ST be liable for the customer using any of these engineering samples in
production. ST’s Quality department must be contacted prior to any decision to use these engineering
samples to run a qualification activity.
MS44207V1
WWY
Pin 1
identifier
STM32F722IET6
R
Date code
Product identification(1)
Revision code
I I >—C| /// $$000000000$ /n 000000000000 fix 000000000000 000000000000 000000000000 oooooqpooooo 000000000000 000000000000 000000000000 000000000000 000000000009 000000000309 W $ ® \\ ®
DS11853 Rev 7 215/230
STM32F722xx STM32F723xx Package information
225
7.5 UFBGA144 package information
UFBGA144 is a 144-ball, 7 x 7 mm, 0.50 mm pitch, ultra fine pitch ball grid array package.
Figure 92. UFBGA144 outline
1. Drawing is not to scale.
Table 119. UFBGA144 mechanical data
Symbol
millimeters inches(1)
Min. Typ. Max. Min. Typ. Max.
A 0.460 0.530 0.600 0.0181 0.0209 0.0236
A1 0.050 0.080 0.110 0.0020 0.0031 0.0043
A2 0.400 0.450 0.500 0.0157 0.0177 0.0197
A3 - 0.130 - - 0.0051 -
A4 0.270 0.320 0.370 0.0106 0.0126 0.0146
b 0.230 0.280 0.320 0.0091 0.0110 0.0126
D 6.950 7.000 7.050 0.2736 0.2756 0.2776
D1 5.450 5.500 5.550 0.2146 0.2165 0.2185
E 6.950 7.000 7.050 0.2736 0.2756 0.2776
E1 5.450 5.500 5.550 0.2146 0.2165 0.2185
e - 0.500 - - 0.0197 -
F 0.700 0.750 0.800 0.0276 0.0295 0.0315
A0AS_ME_V2
Seating plane
A1
eF
F
D
M
Øb (144 balls)
A
E
TOP VIEWBOTTOM VIEW
112
e
A
A2
Y
X
Z
ddd Z
D1
E1
eee Z Y X
fff
Ø
Ø
M
MZ
A3
A4
A1 ball
identifier
A1 ball
index area
000000000000 000000000000 000000000000 000000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 000000000 000000000 0000000fl0
Package information STM32F722xx STM32F723xx
216/230 DS11853 Rev 7
Figure 93. UFBGA144 recommended footprint
ddd - - 0.100 - - 0.0039
eee - - 0.150 - - 0.0059
fff - - 0.050 - - 0.0020
1. Values in inches are converted from mm and rounded to 4 decimal digits.
Table 120. UFBGA144 recommended PCB design rules (0.50 mm pitch BGA)
Dimension Recommended values
Pitch 0.50 mm
Dpad 0.280 mm
Dsm 0.370 mm typ. (depends on the soldermask
registration tolerance)
Stencil opening 0.280 mm
Stencil thickness Between 0.100 mm and 0.125 mm
Pad trace width 0.120 mm
Table 119. UFBGA144 mechanical data (continued)
Symbol
millimeters inches(1)
Min. Typ. Max. Min. Typ. Max.
A0AS_FP_V1
Dpad
Dsm
DS11853 Rev 7 217/230
STM32F722xx STM32F723xx Package information
225
UFBGA144 device marking
The following figure gives an example of topside marking orientation versus ball A1 identifier
location.
The printed markings may differ depending on the supply chain.
Other optional marking or inset/upset marks, which identify the parts throughout supply
chain operations, are not indicated below.
Figure 94. UFBGA144 top view example
1. Parts marked as ES or E or accompanied by an engineering sample notification letter are not yet qualified
and therefore not approved for use in production. ST is not responsible for any consequences resulting
from such use. In no event will ST be liable for the customer using any of these engineering samples in
production. ST’s Quality department must be contacted prior to any decision to use these engineering
samples to run a qualification activity.
Product
identification
(1)
Ball 1 identifier Revision code
Date code
YWW
R
Standard ST logo
STM32F
723ZEI6
MS44251V1
W ” \ oooooonooooaoo ooooooccooooooo aoocoocoooooooo ooeoooaaooooooo 0000 once coco oaooo oooo oooo ooooo coon coco cacao coco coco ooooo coco 0000 05500 coco coco oooo ooaooooooaaoooo ooooooooooooooo aoooooocooo00007 canoe ocooo‘ooov W ®®
Package information STM32F722xx STM32F723xx
218/230 DS11853 Rev 7
7.6 UFBGA176+25, 10 x 10, 0.65 mm ultra thin-pitch ball grid
array package information
UFBGA176+25 is a 176+25-ball, 10 × 10 × 0.65 mm ultra thin fine-pitch ball grid array
package
Figure 95. UFBGA176 outline
1. Drawing is not to scale.
Table 121. UFBGA176+25 mechanical data
Symbol
millimeters inches(1)
1. Values in inches are converted from mm and rounded to 4 decimal digits.
Min Typ Max Min Typ Max
A 0.460 0.530 0.600 0.0181 0.0209 0.0236
A1 0.050 0.080 0.110 0.002 0.0031 0.0043
A2 0.400 0.450 0.500 0.0157 0.0177 0.0197
b 0.230 0.280 0.330 0.0091 0.0110 0.0130
D 9.950 10.000 10.050 0.3917 0.3937 0.3957
E 9.950 10.000 10.050 0.3917 0.3937 0.3957
e - 0.650 - - 0.0256 -
F 0.400 0.450 0.500 0.0157 0.0177 0.0197
ddd - - 0.080 - - 0.0031
eee - - 0.150 - - 0.0059
fff - - 0.080 - - 0.0031
A0E7_ME_V6
Seating plane
A2 Cddd
A1 A
eF
F
e
R
A
15 1
BOTTOM VIEW
E
D
TOP VIEW
Øb (176 + 25 balls)
B
A
B
eeeØ M
fffØM
C
C
A
C
A1 ball
identifier
A1 ball
index
area
b
A4
DS11853 Rev 7 219/230
STM32F722xx STM32F723xx Package information
225
Figure 96. UFBGA176+25 recommended footprint
Table 122. UFBGA176+25 recommended PCB design rules (0.65 mm pitch BGA)
Dimension Recommended values
Pitch 0.65 mm
Dpad 0.300 mm
Dsm 0.400 mm typ. (depends on the soldermask reg-
istration tolerance)
Stencil opening 0.300 mm
Stencil thickness Between 0.100 mm and 0.125 mm
Pad trace width 0.100 mm
A0E7_FP_V1
Dpad
Dsm
\\
Package information STM32F722xx STM32F723xx
220/230 DS11853 Rev 7
UFBGA176+25 device marking
The following figure gives an example of topside marking orientation versus ball A1 identifier
location.
The printed markings may differ depending on the supply chain.
Other optional marking or inset/upset marks, which identify the parts throughout supply
chain operations, are not indicated below.
Figure 97. UFBGA176 top view example
1. Parts marked as ES or E or accompanied by an engineering sample notification letter are not yet qualified
and therefore not approved for use in production. ST is not responsible for any consequences resulting
from such use. In no event will ST be liable for the customer using any of these engineering samples in
production. ST’s Quality department must be contacted prior to any decision to use these engineering
samples to run a qualification activity.
MS44208V1
Revision code
STM32F722
Product identification(1)
Date code
YWW
Ball A1
indentifier
IEK6
R
61 00000 00000 ooooobooo oooooooooo oooooboooo 00000 00000 777i7i7i4i7i7i777 a 00000 00000 00000 00000 AOOOOOOOOOO [e OOOOODOOOO T, oooboooo :11 ‘ \ x D TOP VIEW aw» A \ El 5mm mu:
DS11853 Rev 7 221/230
STM32F722xx STM32F723xx Package information
225
7.7 WLCSP100 - 0.4 mm pitch wafer level chip scale package
information
WLCSP100 is a 100-ball, 4.166 x 4.628 mm, 0.4 mm pitch wafer level chip scale package.
Figure 98. WLCSP100 outline
1. Drawing is not to scale.
A
K
WLCSP100L_A01Q_ME_V1
A1 ORIENTATION
REFERENCE
FRONT VIEW
BOTTOM VIEW
SIDE VIEW
DETAIL A
A1 BALL LOCATION
(4X)
aaa
TOP VIEW
WAFER BACK SIDE
ROTATED 90°
DETAIL A
3% ©©©© ©©©© ©©© ©©©© ©©© ©©©© ©©©© ©©©© ©©©© ©©©© ©©©©©©©©©© ©©©©©©©©©© ©©©©©©©©©© ©©©©©©©©©© ©©©©©©©©©© ©©©©©©©©©©
Package information STM32F722xx STM32F723xx
222/230 DS11853 Rev 7
Figure 99. WLCSP100 recommended footprint
Table 123. WLCSP100 mechanical data
Symbol
millimeters inches(1)
1. Values in inches are converted from mm and rounded to 4 decimal digits.
Min Typ Max Typ Min Max
A 0.525 0.555 0.585 0.0207 0.0219 0.0230
A1 - 0.17 - - 0.0067 -
A2 - 0.38 - - 0.0150 -
A3(2)
2. Back side coating.
- 0.025 - - 0.0010 -
Ø b(3)
3. Dimension is measured at the maximum bump diameter parallel to primary datum Z.
0.22 0.25 0.28 - 0.0098 0.0110
D 4.166 4.201 4.236 - 0.1654 0.1668
E 4.628 4.663 4.698 - 0.1836 0.1850
e - 0.4 - - 0.0157 -
e1 - 3.6 - - 0.1417 -
e2 - 3.6 - - 0.1417 -
F - 0.3005 - - 0.0118 -
G - 0.5315 - - 0.0209 -
N - 100 - - 3.9370 -
aaa - 0.1 - - 0.0039 -
bbb - 0.1 - - 0.0039 -
ccc - 0.1 - - 0.0039 -
ddd - 0.05 - - 0.0020 -
eee - 0.05 - - 0.0020 -
WLCSP100L_A01Q_FP_V1
Dpad
Dsm
DS11853 Rev 7 223/230
STM32F722xx STM32F723xx Package information
225
Table 124. WLCSP100 recommended PCB design rules (0.4 mm pitch)
Dimension Recommended values
Pitch 0.4 mm
Dpad 0.225 mm
Dsm 0.290 mm
Stencil thickness 0.1 mm
Package information STM32F722xx STM32F723xx
224/230 DS11853 Rev 7
WLCSP100 device marking
The following figure gives an example of topside marking orientation versus ball A1 identifier
location.
The printed markings may differ depending on the supply chain.
Other optional marking or inset/upset marks, which identify the parts throughout supply
chain operations, are not indicated below.
Figure 100. WLCSP100 top view example
1. Parts marked as ES or E or accompanied by an engineering sample notification letter are not yet qualified
and therefore not approved for use in production. ST is not responsible for any consequences resulting
from such use. In no event will ST be liable for the customer using any of these engineering samples in
production. ST’s Quality department must be contacted prior to any decision to use these engineering
samples to run a qualification activity.
MSv44209V1
32F723VEY6
Ball A1 identifier
Product identification(1)
YWWR
Revision code
DS11853 Rev 7 225/230
STM32F722xx STM32F723xx Package information
225
7.8 Thermal characteristics
The maximum chip-junction temperature, TJ max, in degrees Celsius, may be calculated
using the following equation:
TJ max = TA max + (PD max x ΘJA)
Where:
•TA max is the maximum ambient temperature in °C,
•Θ
JA is the package junction-to-ambient thermal resistance, in °C/W,
•PD max is the sum of PINT max and PI/O max (PD max = PINT max + PI/Omax),
•PINT max is the product of IDD and VDD, expressed in Watts. This is the maximum chip
internal power.
PI/O max represents the maximum power dissipation on output pins where:
PI/O max = Σ (VOL × IOL) + Σ((VDD – VOH) × IOH),
taking into account the actual VOL / IOL and VOH / IOH of the I/Os at low and high level in the
application.
Reference document
JESD51-2 Integrated Circuits Thermal Test Method Environment Conditions - Natural
Convection (Still Air). Available from www.jedec.org.
Table 125. Package thermal characteristics
Symbol Parameter Value Unit
ΘJA
Thermal resistance junction-ambient
LQFP64 - 10 × 10 mm / 0.5 mm pitch 48.5
°C/W
Thermal resistance junction-ambient
LQFP100 - 14× 14 mm / 0.5 mm pitch 47.1
Thermal resistance junction-ambient
WLCSP100 - 0.4 mm pitch 35.85
Thermal resistance junction-ambient
LQFP144 - 20 × 20 mm / 0.5 mm pitch 45.6
Thermal resistance junction-ambient
LQFP176 - 24 × 24 mm / 0.5 mm pitch 43.9
Thermal resistance junction-ambient
UFBGA144 - 7 × 7 mm / 0.5 mm pitch 42
Thermal resistance junction-ambient
UFBGA176 - 10× 10 mm / 0.65 mm pitch 41.2
Ordering information STM32F722xx STM32F723xx
226/230 DS11853 Rev 7
8 Ordering information
For a list of available options (speed, package, etc.) or for further information on any aspect
of this device, contact the nearest ST sales office.
Table 126. Ordering information scheme
Example: STM32 F 722 V C T 6 xxx
Device family
STM32 = Arm-based 32-bit microcontroller
Product type
F = general-purpose
Device subfamily
722 = STM32F722xx, no OTG PHY HS
723 = STM32F723xx, with OTG PHY HS
Pin count
R = 64 pins
V = 100 pins
Z = 144 pins
I = 176 pins
Flash memory size
C = 256 Kbytes of Flash memory
E = 512 Kbytes of Flash memory
Package
T = LQFP
K = UFBGA (10 x 10 mm)
I = UFBGA (7 x 7 mm)
Y = WLCSP
Temperature range
6 = Industrial temperature range, –40 to 85 °C.
7 = Industrial temperature range, –40 to 105 °C.
Options
xxx = programmed parts
TR = tape and reel
DS11853 Rev 7 227/230
STM32F722xx STM32F723xx Recommendations when using internal reset OFF
229
Appendix A Recommendations when using internal reset
OFF
When the internal reset is OFF, the following integrated features are no longer supported:
•The integrated power-on reset (POR) / power-down reset (PDR) circuitry is disabled.
•The brownout reset (BOR) circuitry must be disabled.
•The embedded programmable voltage detector (PVD) is disabled.
•VBAT functionality is no more available and VBAT pin should be connected to VDD.
•The over-drive mode is not supported.
A.1 Operating conditions
Table 127. Limitations depending on the operating power supply range
Operating
power
supply
range
ADC
operation
Maximum
Flash
memory
access
frequency
with no wait
states
(fFlashmax)
Maximum Flash
memory access
frequency with
wait states (1)(2)
1. Applicable only when the code is executed from Flash memory. When the code is executed from RAM, no
wait state is required.
2. Thanks to the ART accelerator on ITCM interface and L1-cache on AXI interface, the number of wait states
given here does not impact the execution speed from the Flash memory since the ART accelerator or L1-
cache allows to achieve a performance equivalent to 0-wait state program execution.
I/O operation
Possible Flash
memory
operations
VDD =1.7 to
2.1 V(3)
3. VDD/VDDA minimum value of 1.7 V, with the use of an external power supply supervisor (refer to
Section 3.15.1: Internal reset ON).
Conversion
time up to
1.2 Msps
20 MHz
180 MHz with 8
wait states and
over-drive OFF
– No I/O
compensation
8-bit erase and
program
operations only
Revision history STM32F722xx STM32F723xx
228/230 DS11853 Rev 7
Revision history
Table 128. Document revision history
Date Revision Changes
03-Feb-2017 1 Initial release.
30-Mar-2017 2 Updated cover with the maximum SPI speed at 54 Mbit/s.
Updated Figure 15: STM32F722xx LQFP64 pinout.
01-Jun-2017 3
Updated Figure 18: STM32F723xx WLCSP100 ballout (with OTG PHY
HS).
Updated note 1 below all the package device marking figures.
Updated Section 1: Introduction.
Updated Table 60: I/O current injection susceptibility note by ‘injection
is not possible’.
Updated Table 67: ADC characteristics RADC min at 1.5 Kohm.
Updated Figure 47: Recommended NRST pin protection note about the
0.1uF capacitor.
Updated Table 78: DAC characteristics RLOAD feature.
Updated Figure 41: ACCHSI versus temperature.
10-Apr-2018 4
Added Section 1: Introduction.
Removed memory mapping, transferred in the reference manual
(RM0431).
Updated Table 10: STM32F722xx and STM32F723xx pin and ball
definition footnote 5 only for PC14, PC15, PH0, PH1.
Updated Table 125: Package thermal characteristics thermal values for
LQFP packages.
23-Mar-2020 5
Updated Table 1: Device summary adding STM32F723VC.
Added LQFP100 package for STM32F723xx devices:
– Updated Table 2: STM32F722xx and STM32F723xx features and
peripheral counts.
– Updated Section 2.2: STM32F723xx versus STM32F722xx
LQFP100/ LQFP144/ LQFP176 packages.
– Added Figure 3: Compatible board design for LQFP100 package.
– Added Figure 17: STM32F723xx LQFP100 pinout.
– Updated Table 10: STM32F722xx and STM32F723xx pin and ball
definition
Added VDDPHYS
– Updated Figure 6: STM32F722xx and STM32F723xx block diagram.
– Updated Figure 29: STM32F723xx power supply scheme.
– Updated Table 13: Voltage characteristics
– Updated Table 16: General operating conditions
Updated Section 7: Package information.
DS11853 Rev 7 229/230
STM32F722xx STM32F723xx Revision history
229
04-Apr-2020 6
Updated Table 53: Flash memory programming maximum
programming voltage (Vprog) for 32-bit Flash program operation at 3.6V
(instead of 3V).
05-Nov-2020 7
Updated
–Section 2: Description
–Section 2.1: Full compatibility throughout the family
– Note 1 of Table 42: HSI oscillator characteristics
Table 128. Document revision history (continued)
Date Revision Changes
STM32F722xx STM32F723xx
230/230 DS11853 Rev 7
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