Datenblatt für IX9915N von IXYS Integrated Circuits Division

® (ens.
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IX9915
Low Voltage Error Amplifier with a
350V Darlington Transistor
Features
•Precision reference, error amplifier, and a high
voltage Darlington transistor in a single package
•1.299V±1% reference @25ºC
(±1.5% @-40ºC to 85ºC)
•Error amplifier supply voltage range: 1.3V to 12.5V
over temperature
•Breakdown voltage of Darlington transistor: 350V
Applications
•LED lamps
•Low voltage power supply feedback
•AC-to-DC off-line power supplies
•DC-to-DC converters
Description
The IX9915 integrates an error amplifier with a
precision reference and a 350V Darlington transistor
in a single package. The error amplifier can be
operated from 1.3V to 12.5V over the operational
temperature range. The breakdown voltage of the
Darlington transistor is 350V.
The integrated combination of a 4-terminal 431 type
shunt regulator with a high voltage Darlington
transistor is ideal for use in LED lamp bleeder control
circuits.
Ordering Information
IX9915 Block Diagram
Part Description
IX9915N 8-pin SOIC, Tube (100/Tube)
IX9915NTR 8-pin SOIC, Tape & Reel (2000/Reel)
+
_
+
_
VSS
VCC
FB
OC
C
E
B
VREF
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1. Specifications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3
1.1 Package Pinout . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3
1.2 Pin Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3
1.3 Absolute Maximum Ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3
1.4 Electrical Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4
1.5 Test Diagrams . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4
1.6 Performance Data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6
2. Functional Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7
2.1 Regulation Voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7
2.2 Compensation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8
2.3 Design Example . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8
3. Manufacturing Information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9
3.1 Moisture Sensitivity . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9
3.2 ESD Sensitivity . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9
3.3 Soldering Profile . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9
3.4 Board Wash . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9
3.5 Mechanical Dimensions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10
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1. Specifications
1.1 Package Pinout 1.2 Pin Description
1.3 Absolute Maximum Ratings
1 Derate linearly 2.83 mW/°C.
Unless otherwise specified, Absolute Maximum electrical ratings are at 25°C.
Absolute Maximum Ratings are stress ratings. Stresses in excess of these ratings can cause permanent damage to
the device. Functional operation of the device at these or any other conditions beyond those indicated in the
operational sections of this data sheet is not implied.
Typical values are characteristic of the device at 25°C, and are the result of engineering evaluations. They are
provided for information purposes only, and are not part of the manufacturing testing requirements.
FB
OC
B
N/C
V
SS
V
CC
E
C
1
2
3
4
8
7
6
5
Pin# Name Description
1 FB Input Voltage
2 OC Output Current
3 B Darlington Base
4N/C Not Connected
5 C Darlington Collector
6 E Darlington Emitter
7VCC Supply Input
8VSS Supply Return
Parameter Symbol Ratings Unit
Collector-Emitter Voltage VCEO 350 V
Emitter-Collector Voltage VECO 2V
Collector Current ICE 200 mA
Supply Voltage (Referenced to VSS)V
CC 15 V
Output DC Current IOC 20 mA
Power Dissipation (Shunt Regulator) PA30 mW
Power Dissipation, Darlington Transistor 1PD250 mW
Total Power Dissipation 1PT250 mW
ESD Rating (Human Body Model) - 2 kV
Operating Temperature TOPR -40 to +85 °C
Storage Temperature TSTG -55 to +130 °C
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1.4 Electrical Characteristics
1 Reference voltage measured at Pin FB under the specified conditions.
2 Deviation parameters V
REF(DEV)
and I
IB(DEV)
are defined as the difference between the minimum and maximum values obtained over the rated temperature range.
3 With two external resistors, the total shunt transconductance of the circuit is defined as:
1.5 Test Diagrams Figure 1: VREF, IIB, VREF/VCC, gM Test Circuit
Parameter Symbol Conditions Min Typ Max Unit
Input Characteristics @25°C (Unless Otherwise Specified)
Supply voltage VCC T
A=-40°C to +85°C 1.3 - 12.5 V
Reference voltage 1 VREF VCC=1.6V, IOC=10mA (Fig. 1)
V
T
A=25°C 1.286 1.299 1.312
T
A=-40°C to +85°C 1.280 1.299 1.318
Deviation of VREF over temperature 2VREF(DEV) VCC=1.6V, IOC=10mA, T
A=-40°C to +85°C (Fig. 1) -821mV
Ratio of VREF variation to VCC change VREF/VCC 1.3V < VCC < 12.5V, IOC=10mA (Fig. 1) - -0.37 -2.7 mV/V
FB input bias current IIB VCC=1.6V, IOC=10mA (Fig. 1) 0.1 0.34 0.5 A
Deviation of IIB over temperature 2IIB(DEV) VCC=1.6V, IOC=10mA, (Fig. 1) A
T
A=-40°C to +85°C -0.40.6
Quiescent bias current IQVCC=1.6V, VFB = VREF, IOC=0mA (Fig. 3) - 75 100 A
Error amplifier Off-State current ICC(off) VOC=VCC=12.5V, VFB=0V (Fig. 2) 0.001 0.1 A
Shunt Transconductance 3gm (IOC/VFB)V
CC=1.6V, IOC = 0.2mA to 10mA, f=1kHz -1-S
Darlington Characteristics @25°C (Unless Otherwise Specified)
Collector-emitter voltage breakdown BVCEO ICE=100A350 - - V
Collector current ICE VCE=200V, RB=1M (Fig. 4) - - 100 nA
Base-emitter On voltage VBE(ON)ICE=40mA, VCE=2V --1.8V
Collector-emitter saturation voltage VCE(SAT) IC=100mA, IB=150A--1.2V
Current gain hFE ICE=40mA, VCE=2V 2500 - 40000 -
g
m
gm
1R1
R2
------
+
---------------
=
+
_
+
_
+
OC
FB
VCC
C
E
B
VSS
IOC IQ
IIB
VREF
R2
R1
VCC
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Figure 2: ICC(OFF) Test Circuit
Figure 3: IQ Test Circuit
Figure 4: ICE Test Circuit
+
_
+
_
+
OC
FB
VCC
C
E
B
VSS
VCC
+
_
+
_
+
OC
FB
VCC
C
E
B
VSS
IOC IQ
IIB
VFB
R2
R1
VCC
+
_
+
_
+
OC
FB
VCC
C
E
B
VSS
VCE
RB
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1.6 Performance Data
Temperature (ºC)
-50 -25 0 25 50 75 100 125 150
1.270
1.280
1.290
1.300
1.310
1.320 VREF vs. Temperature
VREF (V)
Temperature (ºC)
-50 -25 0 25 50 75 100 125
IIB (nA)
100
200
300
400
500
600
700
FB Input Bias Current vs. Temperature
(IOC=10mA)
Temperature (ºC)
-50 -25 0 25 50 75 100 125
IOC Off Current (nA)
0.0
0.2
0.4
0.6
0.8
1.0
1.2
Off-State Current vs. Temperature
(VOC=13.2V, VFB=0V)
Temperature (ºC)
-50 -25 0 25 50 75 100 125 150
VOC(sat) (V)
0.00
0.05
0.10
0.15
0.20
0.25
Saturation Voltage vs. Temperature
(IOC=10mA)
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2. Functional Description
IX9915 is the functional equivalent of a 4-terminal 431
type precision shunt regulator and a high voltage
Darlington transistor in the same package.
The typical application for IX9915 is shown in
Figure 5.
Figure 5 IX9915 Application Diagram
This is a simplified application circuit that shows how
the IX9915 can be used in an LED lamp control circuit.
The high voltage Darlington transistor will bleed the
current when VLINE is lower than the predetermined
voltage. The 4-terminal 431 type shunt regulator is
used to monitor VLINE voltage and control the
Darlington transistor bleeding the current (ON) or not
(OFF). When VLINE reaches the predetermined
voltage, the shunt regulator starts to regulate to drive
VOC going low, and turns off the Darlington transistor
to make sure this bleeder circuitry only burns a little
power at the higher VLINE voltage. Maximum bleeding
current IH can be controlled by properly choosing RE
and VREG.
Regulation of VREG is made possible by applying a
scaled sample of its voltage to pin FB, the error
amplifier's non-inverting input. The error amplifier
compares this scaled voltage against an internal high
accuracy reference voltage and generates an output
current which in turn regulate VREG through the
resistor R3.
As VREG increases, the error amplifier's input voltage
VFB will also increase. Ramping of VFB beyond the
internal reference voltage causes the error amplifier to
sink more IOC, which in turn decreases VREG.
Likewise, a reduction of VREG results in a lessoning of
IOC causing VREG to increase.
2.1 Regulation Voltage
When connected as shown in the application circuit
above and properly configured, the IX9915 will
regulate VREG such that VFB is equal to VREF(1.299V).
To achieve this, the values of the voltage divider
resistors, R1 and R2, must be set in the following
manner:
Because VREG regulation occurs when VFB=VREF any
change in bias current through R2 at the desired
regulated voltage level will cause a regulation error. As
shown in the Electrical Characteristics table the error
amplifier input at pin FB has an input bias current (IIB)
specification that reduces the current into R2. (IIB is
+
_
+
_
OC
FB
VCC
C
E
B
VSS
IOC IQ
R2
R1
RE
I1
IH
VREG
R3
I3
R0
VREF
+VLINE
Rectifier
Dimmer Switch
AC Supply -
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always into pin FB). This error causes the regulated
output voltage to increase which increases the current
through R1 by an amount equal to IIB, thereby
restoring the current through R2 to its original value.
Reducing the VREG error created by the input bias
current to less than 1% is accomplished by setting the
value of R1 using the following formula:
Where:
2.2 Compensation
The dominate pole of the error amplifier is around
13kHz. In a typical system with a low-bandwidth
requirement, it doesn't need any external
compensation. Frequency response of the system can
be optimized for the specific application by placing a
compensation network between the OC and FB pins
of the IX9915. For designs with more critical
bandwidth requirements, measurement of the loop
response must be made and compensation adjusted
as necessary.
2.3 Design Example
A design example for the bleeder circuitry in LED lamp
exhibits the detailed steps. In this example, it will target
the predetermined voltage VLINE-TH=25V and
maximum bleeding current IH-MAX=25mA.
In order to flow the maximum bleeding current IH-MAX
through the Darlington transistor:
If taking RE=100:
In fact, the components in the dashed rectangle
function as a comparator, its gain:
If taking R0=40k, the gain of the comparator is
around 82dB. That is to say, once the error amplifier
starts to regulate, the Darlington transistor will be shut
off by this comparator. So, IOC can be ignored for
affecting the predetermined voltage:
Almost full power supply voltage will cross over R3,
taking R3=100k to minimize its power consumption:
Substituting:
•IQ=75A,
•I1=VREF / R2,
•VLINE-TH=25V
into formula (2):
R1
VREG
50A
-------------
50A100 IIB MAX
=
VREG IHMAX–RE
VBE
+= (1)
VREG IHMAX–REVBE
+=
25mA 1001.5V+=
4V=
AR0R2
gm
R1R2
+
------------------------------
=
R2
R1R2
+
------------------ VREF
VREG
------------- 1.299V
4V
----------------- 0.325== =
gm1S(typical)=
VLINE-TH VREG I1IQ
+R3
+(2)
PVrms

2
100k
-------------------
=
R29.6k
R1R2
VREG
VREF
------------- 1–


=
R120k
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3. Manufacturing Information
3.1 Moisture Sensitivity
All plastic encapsulated semiconductor packages are susceptible to moisture ingression. IXYS Integrated
Circuits Division classifies its plastic encapsulated devices for moisture sensitivity according to the latest
version of the joint industry standard, IPC/JEDEC J-STD-020, in force at the time of product evaluation.
We test all of our products to the maximum conditions set forth in the standard, and guarantee proper
operation of our devices when handled according to the limitations and information in that standard as well as to any
limitations set forth in the information or standards referenced below.
Failure to adhere to the warnings or limitations as established by the listed specifications could result in reduced
product performance, reduction of operable life, and/or reduction of overall reliability.
This product carries a Moisture Sensitivity Level (MSL) classification as shown below, and should be handled
according to the requirements of the latest version of the joint industry standard IPC/JEDEC J-STD-033.
3.2 ESD Sensitivity
This product is ESD Sensitive, and should be handled according to the industry standard JESD-625.
3.3 Soldering Profile
Provided in the table below is the Classification Temperature (TC) of this product and the maximum dwell time the
body temperature of this device may be (TC - 5)ºC or greater. The classification temperature sets the Maximum Body
Temperature allowed for this device during lead-free reflow processes. For through-hole devices, and any other
processes, the guidelines of J-STD-020 must be observed.
3.4 Board Wash
IXYS Integrated Circuits Division recommends the use of no-clean flux formulations. Board washing to reduce or
remove flux residue following the solder reflow process is acceptable provided proper precautions are taken to
prevent damage to the device. These precautions include but are not limited to: using a low pressure wash and
providing a follow up bake cycle sufficient to remove any moisture trapped within the device due to the washing
process. Due to the variability of the wash parameters used to clean the board, determination of the bake temperature
and duration necessary to remove the moisture trapped within the package is the responsibility of the user
(assembler). Cleaning or drying methods that employ ultrasonic energy may damage the device and should not be
used. Additionally, the device must not be exposed to flux or solvents that are Chlorine- or Fluorine-based.
Device Moisture Sensitivity Level (MSL) Classification
IX9915N MSL 1
Device Classification Temperature (TC)Dwell Time (tp)Max Reflow Cycles
IX9915N 260°C 30 seconds 3
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3.5 Mechanical Dimensions
3.5.1 IX9915N 8-Pin SOIC Package
3.5.2 IX9915NTR Tape & Reel
Dimensions
MIN / MAX
1.75 MAX
(0.069 MAX)
1.25 MIN
(0.049 MIN)
0.10 / 0.25
(0.004 / 0.010)
0.10
(0.004)
4
4.80 / 5.00
(0.189 / 0.197)
TOP VIEW
PIN #1
5.80 / 6.20
(0.228 / 0.244)
5
3.80 / 4.00
(0.150 / 0.157)
0.31 / 0.51
(0.012 / 0.020)
8x
SEATING PLANE
GAUGE PLANE
8°- 0°
0.10 / 0.25
(0.004 / 0.010)
0.40 / 1.27
(0.016 / 0.050)
A
0.25
(0.010)
PCB Land Pattern
1.55
(0.061)
0.60
(0.024)
3.75
(0.148)
A
Notes:
1. Controlling dimension: millimeters.
2. All dimensions are in mm (inches).
3. This package conforms to JEDEC Standard MS-012, variation AA, Rev. F.
4. Dimension does not include mold flash, protrusions, or gate burrs. Mold flash, protrusions, or gate burrs shall not exceed 0.15mm per end.
5. Dimension does not include interlead flash or protrusion. Interlead flash or protrusion shall not exceed 0.25mm per side.
6. Lead thickness includes plating.
6x
1.27
0.05
Dimensions
mm
(inches)
NOTE: Tape dimensions not shown comply with JEDEC Standard EIA-481-2
Embossment
Embossed Carrier
Top Cover
Tape Thickness
0.102 MAX.
(0.004 MAX.)
330.2 DIA.
(13.00 DIA.)
K
0
= 2.10
(0.083)
W=12.00
(0.472)
B
0
=5.30
(0.209)
User Direction of Feed
A
0
=6.50
(0.256) P1=8.00
(0.315)
For additional information please visit www.ixysic.com
IXYS Integrated Circuits Division makes no representations or warranties with respect to the accuracy or completeness of the contents of this publication and
reserves the right to make changes to specifications and product descriptions at any time without notice. Neither circuit patent licenses or indemnity are expressed
or implied. Except as set forth in IXYS Integrated Circuits Division’s Standard Terms and Conditions of Sale, IXYS Integrated Circuits Division assumes no liability
whatsoever, and disclaims any express or implied warranty relating to its products, including, but not limited to, the implied warranty of merchantability, fitness for a
particular purpose, or infringement of any intellectual property right.
The products described in this document are not designed, intended, authorized, or warranted for use as components in systems intended for surgical implant into
the body, or in other applications intended to support or sustain life, or where malfunction of IXYS Integrated Circuits Division’s product may result in direct physical
harm, injury, or death to a person or severe property or environmental damage. IXYS Integrated Circuits Division reserves the right to discontinue or make changes
to its products at any time without notice.
Specifications: DS-IX9915-R01
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All rights reserved. Printed in USA.
3/23/2018