Datenblatt für MC9S08AC128,96 von NXP USA Inc.

o '0 freescale'“
Freescale Semiconductor
Addendum
Document Number: QFN_Addendum
Rev. 0, 07/2014
© Freescale Semiconductor, Inc., 2014. All rights reserved.
This addendum provides the changes to the 98A case outline numbers for products covered in this book.
Case outlines were changed because of the migration from gold wire to copper wire in some packages. See
the table below for the old (gold wire) package versus the new (copper wire) package.
To view the new drawing, go to Freescale.com and search on the new 98A package number for your
device.
For more information about QFN package use, see EB806: Electrical Connection Recommendations for
the Exposed Pad on QFN and DFN Packages.
Addendum for New QFN
Package Migration
Addendum for New QFN Package Migration, Rev. 0
Freescale Semiconductor2
Part Number Package Description Original (gold wire)
package document number Current (copper wire)
package document number
MC68HC908JW32 48 QFN 98ARH99048A 98ASA00466D
MC9S08AC16
MC9S908AC60
MC9S08AC128
MC9S08AW60
MC9S08GB60A
MC9S08GT16A
MC9S08JM16
MC9S08JM60
MC9S08LL16
MC9S08QE128
MC9S08QE32
MC9S08RG60
MCF51CN128
MC9RS08LA8 48 QFN 98ARL10606D 98ASA00466D
MC9S08GT16A 32 QFN 98ARH99035A 98ASA00473D
MC9S908QE32 32 QFN 98ARE10566D 98ASA00473D
MC9S908QE8 32 QFN 98ASA00071D 98ASA00736D
MC9S08JS16 24 QFN 98ARL10608D 98ASA00734D
MC9S08QB8
MC9S08QG8 24 QFN 98ARL10605D 98ASA00474D
MC9S08SH8 24 QFN 98ARE10714D 98ASA00474D
MC9RS08KB12 24 QFN 98ASA00087D 98ASA00602D
MC9S08QG8 16 QFN 98ARE10614D 98ASA00671D
MC9RS08KB12 8 DFN 98ARL10557D 98ASA00672D
MC9S08QG8
MC9RS08KA2 6 DFN 98ARL10602D 98ASA00735D
‘/ROHS 99m 0" :"free§mggls‘”
824D-02
MC9S08AC128
840B-01
917A-03
Freescale Semiconductor
Data Sheet: Technical Data
Document Number: MC9S08AC128
Rev. 4, 8/2011
© Freescale Semiconductor, Inc., 2007-2011. All rights reserved.
This document contains information on a new product. Specifications and information herein
are subject to change without notice.
MC9S08AC128 8-Bit
Microcontroller Data Sheet
8-Bit HCS08 Central Processor Unit (CPU)
• 40-MHz HCS08 CPU (central processor unit)
• 20-MHz internal bus frequency
• HC08 instruction set with added BGND, CALL and
RTC instructions
• Memory Management Unit to support paged
memory.
• Linear Address Pointer to allow direct page data
accesses of the entire memory map
Development Support
• Background debugging system
• Breakpoint capability to allow single breakpoint
setting during in-circuit debugging (plus two more
breakpoints in on-chip debug module)
• On-chip in-circuit emulator (ICE) Debug module
containing three comparators and nine trigger
modes. Eight deep FIFO for storing change-of-flow
addresses and event-only data. Supports both tag
and force breakpoints.
Memory Options
• Up to 128K FLASH — read/program/erase over full
operating voltage and temperature
• Up to 8K Random-access memory (RAM)
• Security circuitry to prevent unauthorized access to
RAM and FLASH contents
Clock Source Options
• Clock source options include crystal, resonator,
external clock, or internally generated clock with
precision NVM trimming using ICG module
System Protection
• Optional computer operating properly (COP) reset
with option to run from independent internal clock
source or bus clock
• CRC module to support fast cyclic redundancy
checks on system memory
• Low-voltage detection with reset or interrupt
• Illegal opcode detection with reset
• Master reset pin and power-on reset (POR)
Power-Saving Modes
• Wait plus two stops
Peripherals
•ADC — 16-channel, 10-bit resolution, 2.5 s
conversion time, automatic compare function,
temperature sensor, internal bandgap reference
channel
•SCIx — Two serial communications interface
modules supporting LIN 2.0 Protocol and SAE J2602
protocols; Full duplex non-return to zero (NRZ);
Master extended break generation; Slave extended
break detection; Wakeup on active edge
•SPIx — One full and one master-only serial
peripheral interface modules; Full-duplex or
single-wire bidirectional; Double-buffered transmit
and receive; Master or Slave mode; MSB-first or
LSB-first shifting
•IIC — Inter-integrated circuit bus module; Up to 100
kbps with maximum bus loading; Multi-master
operation; Programmable slave address; Interrupt
driven byte-by-byte data transfer; supports broadcast
mode and 10 bit addressing
•TPMx — One 2-channel and two 6-channel 16-bit
timer/pulse-width modulator (TPM) modules:
Selectable input capture, output compare, and
edge-aligned PWM capability on each channel. Each
timer module may be configured for buffered,
centered PWM (CPWM) on all channels
•KBI — 8-pin keyboard interrupt module
Input/Output
• Up to 70 general-purpose input/output pins
• Software selectable pullups on input port pins
• Software selectable drive strength and slew rate
control on ports when used as outputs
Package Options
• 80-pin low-profile quad flat package (LQFP)
• 64-pin quad flat package (QFP)
• 48-pin quad flat no-lead package (QFN)
• 44-pin low-profile quad flat package (LQFP)
MC9S08AC128 MCU Series Data Sheet, Rev. 4
Freescale Semiconductor2
Table of Contents
Related Documentation
MC9S08AC128 Series Reference Manual (MC9S08AC128RM)
contains extensive product information including modes of operartion, memory, resets and interrupts, reg-
ister definitions, port pins, CPU, and all peripheral module information.
For the latest version of the documentation, check our website at:
http://www.freescale.com
Chapter 1
Device Overview. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .3
1.1 MCU Block Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . .3
Chapter 2
Pins and Connections. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .5
2.1 Device Pin Assignment . . . . . . . . . . . . . . . . . . . . . . . . . .5
Chapter 3
Electrical Characteristics and Timing Specifications . . . . . . .11
3.1 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .11
3.2 Parameter Classification . . . . . . . . . . . . . . . . . . . . . . . .11
3.3 Absolute Maximum Ratings . . . . . . . . . . . . . . . . . . . . .11
3.4 Thermal Characteristics . . . . . . . . . . . . . . . . . . . . . . . .13
3.5 ESD Protection and Latch-Up Immunity . . . . . . . . . . . .14
3.6 DC Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . .14
3.7 Supply Current Characteristics . . . . . . . . . . . . . . . . . . .18
3.8 ADC Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . .21
3.9 Internal Clock Generation Module Characteristics . . . 24
3.9.1 ICG Frequency Specifications . . . . . . . . . . . . . 25
3.10 AC Characteristics. . . . . . . . . . . . . . . . . . . . . . . . . . . . 27
3.10.1 Control Timing . . . . . . . . . . . . . . . . . . . . . . . . . 27
3.10.2 Timer/PWM (TPM) Module Timing. . . . . . . . . . 28
3.11 SPI Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . 30
3.12 FLASH Specifications . . . . . . . . . . . . . . . . . . . . . . . . . 33
3.13 EMC Performance . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34
3.13.1 Radiated Emissions . . . . . . . . . . . . . . . . . . . . . 34
Chapter 4
Ordering Information and Mechanical Drawings . . . . . . . . . . 35
4.1 Ordering Information . . . . . . . . . . . . . . . . . . . . . . . . . . 35
4.2 Orderable Part Numbering System . . . . . . . . . . . . . . . 35
4.3 Mechanical Drawings. . . . . . . . . . . . . . . . . . . . . . . . . . 35
Chapter 5
Revision History . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 37
MC9S08AC128 MCU Series Data Sheet, Rev. 4
Freescale Semiconductor 3
Chapter 1
Device Overview
The MC9S08AC128 is a member of the low-cost, high-performance HCS08 Family of 8-bit
microcontroller units (MCUs). The MC9S08AC128 uses the enhanced HCS08 core.
1.1 MCU Block Diagram
The block diagram in Figure 1-1 shows the structure of the MC9S08AC128 Series MCU.
++ Aéééaééé ....... HfiHHHHH
Chapter 1 Device Overview
MC9S08AC128 MCU Series Data Sheet, Rev. 4
4Freescale Semiconductor
Figure 1-1. MC9S08AC128 Series Block Diagram
KBI1P7–KBI1P0
PTD3/KBI1P6/AD1P11
PTD4/TPM2CLK/AD1P12
PTD5/AD1P13
PTD6/TPM1CLK/AD1P14
PTC1/SDA1
PTC0/SCL1
VSS
VDD
PTE3/TPM1CH1
PTE2/TPM1CH0
PTE0/TxD1
PTE1/RxD1
PTD2/KBI1P5/AD1P10
PTD1/AD1P9
PTD0/AD1P8
PTC6
PTC5/RxD2
PTC4
PTC3/TxD2
PTC2/MCLK
PORT C
PORT D
PORT E
8-BIT KEYBOARD
INTERRUPT MODULE (KBI1)
IIC MODULE (IIC1)
SERIAL PERIPHERAL
INTERFACE MODULE (SPI1)
USERMEMORY
DEBUG
MODULE (DBG)
(AW128 = 128K, 8K)
HCS08 CORE
CPU
BDC
PTE5/MISO1
PTE4/SS1
PTE6/MOSI1
PTE7/SPSCK1
HCS08 SYSTEM CONTROL
RESETS AND INTERRUPTS
MODES OF OPERATION
POWER MANAGEMENT
RTI COP
IRQ LVD
LOW-POWER OSC
INTERNAL CLOCK
GENERATOR (ICG)
RESET
VSSAD
VDDAD
VREFH
ANALOG-TO-DIGITAL
CONVERTER (ADC)
6-CHANNEL TIMER/PWM
MODULE (TPM1)
PTD7/KBI1P7/AD1P15
10-BIT
BKGD/MS
PTF3/TPM1CH5
PTF2/TPM1CH4
PTF0/TPM1CH2
PTF1/TPM1CH3
PORT F
PTF5/TPM2CH1
PTF4/TPM2CH0
PTF6
PTF7
INTERFACE MODULE (SCI2)
SERIAL COMMUNICATIONS
(AW96 = 96K, 6K)
VREFL
RQ/TPMCLK
AD1P15–AD1P0
SPSCK1
SS1
MISO1
MOSI1
TPM1CLK or TPMCLK
TPM1CH0–TPM1CH5
SCL
SDA
RXD2
TXD2
INTERFACE MODULE (SCI1)
SERIAL COMMUNICATIONS RXD1
TXD1
SERIAL PERIPHERAL
INTERFACE MODULE (SPI2)
SPSCK2
MISO2
MOSI2
6-CHANNEL TIMER/PWM
MODULE (TPM2)
TPM2CLK or TPMCLK
TPM3CH1
TPM3CH0
2-CHANNEL TIMER/PWM
MODULE (TPM3)
TPMCLK
TPM2CH0–TPM2CH5
FLASH, RAM
(BYTES)
VOLTAGE REGULATOR
EXTAL
XTAL
PTH3/TPM2CH5
PTH2/TPM2CH4
PTH0/TPM2CH2
PTH1/TPM2CH3
PORT H
PTH5/MOSI2
PTH4/SPSCK2
PTH6/MISO2
- Pin not connected in 64-pin and 48-pin packages - Pin not connected in 48-pin and 44-pin package
PTB3/AD1P3
PTB2/AD1P2
PTB0/TPM3CH0/AD1P0
PTB1/TPM3CH1/AD1P1
PORT B
PTB5/AD1P5
PTB4/AD1P4
PTB6/AD1P6
PTB7/AD1P7
PTJ3
PTJ2
PTJ0
PTJ1
PORT J
PTJ5
PTJ4
PTJ6
PTJ7
PTG3/KBI1P3
PTG2/KBI1P2
PTG0/KBIP0
PTG1/KBI1P1
PORT G
PTG5/XTAL
PTG4/KBI1P4
PTG6/EXTAL
PTA3
PTA2
PTA0
PTA1
PORT A
PTA5
PTA4
PTA6
PTA7
CYCLIC REDUNDANCY
CHECK MODULE (CRC)
- Pin not connected in 44-pin package
RESET PTFSNPMZCH‘ S g E 5 Z, Hflflflflflflflfiflflflflflfiflflflflfl flflflflflflflflflflflflflflflflflflflfl O UUUUUUUUUUUUUUUUUUUU UUUUUUUUEUUU UUUUUUU U \% > E a 8 i:
MC9S08AC128 MCU Series Data Sheet, Rev. 4
Freescale Semiconductor 5
Chapter 2
Pins and Connections
This section describes signals that connect to package pins. It includes pinout diagrams, recommended
system connections, and detailed discussions of signals.
2.1 Device Pin Assignment
Figure 2-1 shows the 80-pin LQFP package pin assignments for the MC9S08AC128 Series device.
Figure 2-1. MC9S08AC128 Series in 80-Pin LQFP Package
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
80
79
78
77
76
75
74
73
72
71
70
69
68
67
66
65
64
63
62
61
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40
60
59
58
57
56
55
54
53
52
51
50
49
48
47
46
45
44
43
42
41
80-Pin
LQFP
PTG3/KBI1P3
PTC4
PTC5/RxD2
PTD3/KBI1P6/AD1P11
IRQ/TPMCLK
PTD2/KBI1P5/AD1P10
RESET
VSSADPTF0/TPM1CH2
VDDADPTF1/TPM1CH3
PTD1/AD1P9
PTF2/TPM1CH4
PTD0/AD1P8
PTF5/TPM2CH1
PTB7/AD1P7
PTF6
PTB6/AD1P6
PTJ0
PTB5/AD1P5
PTJ1
PTB4/AD1P4
PTJ2
PTB3/AD1P3
PTJ3
PTB2/AD1P2
PTE0/TxD1
PTB1/TPM3CH1/AD1P1
PTE1/RxD1
PTB0/TPM3CH0/AD1P0
PTF3/TPM1CH5
PTH3/TPM2CH5
PTF4/TPM2CH0
PTC3/TxD2
PTC2/MCLK
PTH6/MISO2
PTH5/MIOSI2
PTH4/SPCK2
VDD (NC)
VSS
PTG6/EXTAL
PTJ6
PTG5/XTAL
PTJ7
VREFH
PTG2/KBI1P2
PTD7/KBI1P7/AD1P15
PTA0
PTD6/TPM1CLK/AD1P14
PTD5/AD1P13
PTD4/TPM2CLK/AD1P12
PTG0/KBI1P0
PTG4/KBI1P4
PTG1/KBI1P1
PTC6
PTF7
PTE2/TPM1CH0
PTE3/TPM1CH1
PTH2/TPM2CH4
PTH1/TPM2CH3
PTH0/TPM2CH2
PTA7
PTC1/SDA1
PTC0/SCL1
BKGD/MS
VREFL
PTA1
PTA2
PTA3
PTA4
PTA5
PTA6
PTE4/SS1
PTE5/MISO1
VSS
VDD
PTE6/MOSI1
PTE7/SPSCK1
PTJ4
PTJ5
Note: Pin names in bold
are lost in lower pin count
packages.
flflflflflflflflflflflflfl fl Dflflflflflflflflflflflflflflfl DDDDDDDDDDDDDDDD UUUUUUUUUUUUUUUU E E
Chapter 2 Pins and Connections
MC9S08AC128 MCU Series Data Sheet, Rev. 4
6Freescale Semiconductor
Figure 2-2 shows the 64-pin package assignments for the MC9S08AC128 Series devices.
Figure 2-2. MC9S08AC128 Series in 64-Pin QFP Package
PTF2/TPM1CH4
1
2
3
4
5
6
7
8
RESET
PTF0/TPM1CH2
PTF3/TPM1CH5
PTF4/TPM2CH0
PTC6
PTF7
PTG2/KBI1P2
PTG1/KBI1P1
PTG0/KBI1P0
VDD
VSS
PTE7/SPSCK1
PTE6/MOSI1
PTB7/AD1P7
PTD0/AD1P8
PTD1/AD1P9
VDDAD
VSSAD
PTB1/TPM3CH1/AD1P1
PTB6/AD1P6
PTD5/AD1P13
VREFH
PTC5/RxD2
PTG5/XTAL
BKGD/MS
VREFL
PTG3/KBI1P3
PTD6//TPM1CLK
PTD7/AD1P15/KBI1P7
43
42
41
40
39
38
18 19 20 21 22 23
505152535455
17 32
33
49
48
64
9
PTF5/TPM2CH1
10
PTF6
11
PTE0/TxD1
16
PTE3/TPM1CH1
PTA0
24
PTA1
25
PTA2
26
PTA3
27
PTB5/AD1P5
37
PTB4/AD1P4
36
PTB3/AD1P3
35
PTB2/AD1P2
34
PTG6/EXTAL
56
VSS
57
PTC0/SCL1
58
PTC1/SDA1
59
PTF1/TPM1CH3
12
PTE1/RxD1
13
14
15
PTE2/TPM1CH0
PTA4
28 29 30 31
PTD2KBI1P5/AD1P10
44
45
46
PTD3/KBI1P6/AD1P11
47
PTC3/TxD2
63 62 61
PTC2/MCLK
60
PTC4
IRQ/TPMCLK
PTE4/SS1
PTE5/MISO1
PTA5
PTA6
PTB0/TPM3CH0/AD1P0
PTA7
PTD4/AD1P12/TPM2CLK
PTG4/KBI1P4
64-Pin QFP
Note: Pin names in bold
are lost in lower pin count
packages.
ODDDDDDDDDDDD DDDDDDDDDDDD DDDDDDDDDDDD DDDDDDDDDDDD E E
Chapter 2 Pins and Connections
MC9S08AC128 MCU Series Data Sheet, Rev. 4
Freescale Semiconductor 7
Figure 2-1 shows the 48-pin package assignments for the MC9S08AC128 Series devices.
Figure 2-1. MC9S08AC128 Series in 48-Pin QFN Package
1
2
3
4
5
6
7
8
RESET
PTF0/TPM1CH2
PTF4/TPM2CH0
PTG2/KBI1P2
PTG1/KBI1P1
PTG0/KBI1P0
VDD
VSS
PTE7/SPSCK1
PTE6/MOSI1
PTD0/AD1P8
PTD1/AD1P9
VDDAD
VSSAD
PTB1/TPM3CH1/AD1P1
VREFH
PTC5/RxD2
PTG5/XTAL
BKGD/MS
VREFL
PTG3/KBI1P3
36
35
34
33
32
31
14 15 16 17 18 19
3839
13
3748
9
PTF5/TPM2CH1
10
PTF6
11
PTE0/TxD1
PTE3/TPM1CH1
PTA0
20
PTA1
21
PTA2
22 23
30
29 PTB3/AD1P3
28 PTB2/AD1P2
27
PTG6/EXTAL
40
VSS
41
PTC0/SCL1
42
PTC1/SDA1
43
PTF1/TPM1CH3
12
PTE1/RxD1
PTE2/TPM1CH0
24
PTD2KBI1P5/AD1P10
25
26
PTD3/KBI1P6/AD1P11
PTC3/TxD2
47 46 45
PTC2/MCLK
44
PTC4
IRQ/TPMCLK
PTE4/SS1
PTE5/MISO1
PTB0/TPM3CH0/AD1P0
PTA7
PTG4/KBI1P4
48-Pin QFN
Note: Pin names in bold
are lost in lower pin count
packages.
flflflflflflflflflflfl flflflflflflflflflflfl O LILILILILILHJLILILILI UUUUUUUUUUU ‘E m
Chapter 2 Pins and Connections
MC9S08AC128 MCU Series Data Sheet, Rev. 4
8Freescale Semiconductor
Figure 2-3 shows the 44-pin LQFP pin assignments for the MC9S08AC128 Series device.
Figure 2-3. MC9S08AC128 Series in 44-Pin LQFP Package
Table 2-4. Pin Availability by Package Pin-Count
Pin Number Lowest <-- Priority --> Highest
80 64 48 44 Port Pin Alt 1 Alt 2
1111 PTC4
2222 IRQ TPMCLK
1
3333RESET
4444 PTF0TPM1CH2
5555 PTF1TPM1CH3
6 6 — — PTF2 TPM1CH4
7 7 — — PTF3 TPM1CH5
8866 PTF4TPM2CH0
99—— PTC6
10 10 — — PTF7
11 11 7 7 PTF5 TPM2CH1
12 12 8 — PTF6
PTF4/TPM2CH0
1
2
3
4
5
6
7
8
RESET
PTF0/TPM1CH2
PTG2/KBI1P2
PTG1/KBI1P1
PTG0/KBI1P0
VDD
VSS
PTE7/SPSCK1
PTE6/MOSI1
PTD0/AD1P8
PTD1/AD1P9
VDDAD
VSSAD
PTB1/TPM3CH1/AD1P1
VREFH
PTC5/RxD2
PTG5/XTAL
BKGD/MS
VREFL
PTG3/KBI1P3
31
30
29
28
27
26
13 14 15 16 17 18
34
35
12 22
23
33
44
9
PTF5/TPM2CH1
10
PTE0/TxD1
11
PTE3/TPM1CH1
PTA0
19
PTA1
20 21
PTB3/AD1P3
PTB2/AD1P2
PTG6/EXTAL
36
VSS
37
PTC0/SCL1
38
PTC1/SDA1
39
PTF1/TPM1CH3
PTE1/RxD1
PTE2/TPM1CH0
PTD2/KBI1P5/AD1P10
32 PTD3/KBI1P6/AD1P11
PTC3/TxD2
43 42 41
PTC2/MCLK
40
PTC4
IRQ/TPMCLK
PTE4/SS1
PTE5/MISO1
PTB0/TPM3CH0/AD1P0
44-Pin LQFP
25
24
Chapter 2 Pins and Connections
MC9S08AC128 MCU Series Data Sheet, Rev. 4
Freescale Semiconductor 9
13——— PTJ0
14——— PTJ1
15——— PTJ2
16——— PTJ3
17 13 9 8 PTE0 TxD1
18 14 10 9 PTE1 RxD1
19 15 11 10 PTE2 TPM1CH0
20 16 12 11 PTE3 TPM1CH1
21 17 13 12 PTE4 SS1
22 18 14 13 PTE5 MISO1
23 19 15 14 PTE6 MOSI1
24 20 16 15 PTE7 SPSCK1
25 21 17 16 VSS
26 22 18 17 VDD
27——— PTJ4
28——— PTJ5
29——— PTJ6
30——— PTJ7
31 23 19 18 PTG0 KBI1P0
32 24 20 19 PTG1 KBI1P1
33 25 21 20 PTG2 KBI1P2
34 26 22 21 PTA0
35 27 23 22 PTA1
36 28 24 — PTA2
37 29 — — PTA3
38 30 — — PTA4
39 31 — — PTA5
40 32 — — PTA6
41 33 25 — PTA7
42 — — — PTH0 TPM2CH2
43 — — — PTH1 TPM2CH3
44 — — — PTH2 TPM2CH4
45 — — — PTH3 TPM2CH5
46 34 26 23 PTB0 TPM3CH0 AD1P0
47 35 27 24 PTB1 TPM3CH1 AD1P1
48 36 28 25 PTB2 AD1P2
49 37 29 26 PTB3 AD1P3
50 38 — — PTB4 AD1P4
51 39 — — PTB5 AD1P5
52 40 — — PTB6 AD1P6
53 41 — — PTB7 AD1P7
Table 2-4. Pin Availability by Package Pin-Count (continued)
Pin Number Lowest <-- Priority --> Highest
80 64 48 44 Port Pin Alt 1 Alt 2
Chapter 2 Pins and Connections
MC9S08AC128 MCU Series Data Sheet, Rev. 4
10 Freescale Semiconductor
54 42 30 27 PTD0 AD1P8
55 43 31 28 PTD1 AD1P9
56 44 32 29 VDDAD
57 45 33 30 VSSAD
58 46 34 31 PTD2 KBI1P5 AD1P10
59 47 35 32 PTD3 KBI1P6 AD1P11
60 48 36 33 PTG3 KBI1P3
61 49 37 — PTG4 KBI1P4
62 50 — — PTD4 TPM2CLK AD1P12
63 51 — — PTD5 AD1P13
64 52 — — PTD6 TPM1CLK AD1P14
65 53 — — PTD7 KBI1P7 AD1P15
66 54 38 34 VREFH
67 55 39 35 VREFL
68 56 40 36 BKGD MS
69 57 41 37 PTG5 XTAL
70 58 42 38 PTG6 EXTAL
71 59 43 39 VSS
72———V
DD(NC)
73 60 44 40 PTC0 SCL1
74 61 45 41 PTC1 SDA1
75 — — — PTH4 SPSCK2
76——— PTH5 MOSI2
77——— PTH6 MISO2
78 62 46 42 PTC2 MCLK
79 63 47 43 PTC3 TxD2
80 64 48 44 PTC5 RxD2
1TPMCLK, TPM1CLK, and TPM2CLK options are configured
via software; out of reset, TPM1CLK, TPM2CLK, and
TPMCLK are available to TPM1, TPM2, and TPM3
respectively.
Table 2-4. Pin Availability by Package Pin-Count (continued)
Pin Number Lowest <-- Priority --> Highest
80 64 48 44 Port Pin Alt 1 Alt 2
MC9S08AC128 Series Data Sheet, Rev. 4
Freescale Semiconductor 11
Chapter 3
Electrical Characteristics and Timing Specifications
3.1 Introduction
This section contains electrical and timing specifications.
3.2 Parameter Classification
The electrical parameters shown in this supplement are guaranteed by various methods. To give the customer a better
understanding the following classification is used and the parameters are tagged accordingly in the tables where appropriate:
NOTE
The classification is shown in the column labeled “C” in the parameter tables where
appropriate.
3.3 Absolute Maximum Ratings
Absolute maximum ratings are stress ratings only, and functional operation at the maxima is not guaranteed. Stress beyond the
limits specified in Table 3-2 may affect device reliability or cause permanent damage to the device. For functional operating
conditions, refer to the remaining tables in this section.
This device contains circuitry protecting against damage due to high static voltage or electrical fields; however, it is advised
that normal precautions be taken to avoid application of any voltages higher than maximum-rated voltages to this
high-impedance circuit. Reliability of operation is enhanced if unused inputs are tied to an appropriate logic voltage level (for
instance, either VSS or VDD).
Table 3-1. Parameter Classifications
PThose parameters are guaranteed during production testing on each individual device.
CThose parameters are achieved by the design characterization by measuring a statistically relevant
sample size across process variations.
TThose parameters are achieved by design characterization on a small sample size from typical devices
under typical conditions unless otherwise noted. All values shown in the typical column are within this
category.
DThose parameters are derived mainly from simulations.
Chapter 3 Electrical Characteristics and Timing Specifications
MC9S08AC128 Series Data Sheet, Rev. 4
12 Freescale Semiconductor
Table 3-2. Absolute Maximum Ratings
Rating Symbol Value Unit
Supply voltage VDD –0.3 to + 5.8 V
Input voltage VIn – 0.3 to VDD + 0.3 V
Instantaneous maximum current
Single pin limit (applies to all port pins)1,2,3
1Input must be current limited to the value specified. To determine the value of the required
current-limiting resistor, calculate resistance values for positive (VDD) and negative (VSS) clamp
voltages, then use the larger of the two resistance values.
2All functional non-supply pins are internally clamped to VSS and VDD.
3Power supply must maintain regulation within operating VDD range during instantaneous and
operating maximum current conditions. If positive injection current (VIn > VDD) is greater than
IDD, the injection current may flow out of VDD and could result in external power supply going
out of regulation. Ensure external VDD load will shunt current greater than maximum injection
current. This will be the greatest risk when the MCU is not consuming power. Examples are: if
no system clock is present, or if the clock rate is very low which would reduce overall power
consumption.
ID 25 mA
Maximum current into VDD IDD 120 mA
Storage temperature Tstg –55 to +150 C
Chapter 3 Electrical Characteristics and Timing Specifications
MC9S08AC128 MCU Series Data Sheet, Rev. 4
Freescale Semiconductor 13
3.4 Thermal Characteristics
This section provides information about operating temperature range, power dissipation, and package thermal resistance. Power
dissipation on I/O pins is usually small compared to the power dissipation in on-chip logic and it is user-determined rather than
being controlled by the MCU design. In order to take PI/O into account in power calculations, determine the difference between
actual pin voltage and VSS or VDD and multiply by the pin current for each I/O pin. Except in cases of unusually high pin current
(heavy loads), the difference between pin voltage and VSS or VDD will be very small.
The average chip-junction temperature (TJ) in C can be obtained from:
TJ = TA + (PD JA)Eqn. 3-1
where:
TA = Ambient temperature, C
JA = Package thermal resistance, junction-to-ambient, C/W
PD = Pint PI/O
Pint = IDD VDD, Watts — chip internal power
PI/O = Power dissipation on input and output pins — user determined
For most applications, PI/O  Pint and can be neglected. An approximate relationship between PD and TJ (if PI/O is neglected)
is:
PD = K (TJ + 273C) Eqn. 3-2
Table 3-3. Thermal Characteristics
Rating Symbol Value Unit
Operating temperature range (packaged) TA
TL to TH
–40 to 125 C
Maximum junction temperature TJ150 C
Thermal resistance 1,2,3,4
80-pin LQFP
1s
2s2p
64-pin QFP
1s
2s2p
48-pin QFN
1s
2s2p
44-pin LQFP
1s
2s2p
1Junction temperature is a function of die size, on-chip power dissipation, package thermal
resistance, mounting site (board) temperature, ambient temperature, air flow, power dissipation
of other components on the board, and board thermal resistance.
2Junction to Ambient Natural Convection
31s - Single Layer Board, one signal layer
42s2p - Four Layer Board, 2 signal and 2 power layers
JA
61
47
57
43
81
28
73
56
C/W
Chapter 3 Electrical Characteristics and Timing Specifications
MC9S08AC128 Series Data Sheet, Rev. 4
14 Freescale Semiconductor
Solving equations 1 and 2 for K gives:
K = PD (TA + 273C) + JA (PD)2Eqn. 3-3
where K is a constant pertaining to the particular part. K can be determined from equation 3 by measuring PD (at equilibrium)
for a known TA. Using this value of K, the values of PD and TJ can be obtained by solving equations 1 and 2 iteratively for any
value of TA.
3.5 ESD Protection and Latch-Up Immunity
Although damage from electrostatic discharge (ESD) is much less common on these devices than on early CMOS circuits,
normal handling precautions should be used to avoid exposure to static discharge. Qualification tests are performed to ensure
that these devices can withstand exposure to reasonable levels of static without suffering any permanent damage.
All ESD testing is in conformity with AEC-Q100 Stress Test Qualification for Automotive Grade Integrated Circuits and
JEDEC Standard for Non-Automotive Grade Integrated Circuits. During the device qualification ESD stresses were performed
for the Human Body Model (HBM), the Machine Model (MM) and the Charge Device Model (CDM).
A device is defined as a failure if after exposure to ESD pulses the device no longer meets the device specification. Complete
DC parametric and functional testing is performed per the applicable device specification at room temperature followed by hot
temperature, unless specified otherwise in the device specification.
3.6 DC Characteristics
This section includes information about power supply requirements, I/O pin characteristics, and power supply current in various
operating modes.
Table 3-4. ESD and Latch-up Test Conditions
Model Description Symbol Value Unit
Human Body
Series Resistance R1 1500
Storage Capacitance C 100 pF
Number of Pulse per pin – 3
Machine
Series Resistance R1 0
Storage Capacitance C 200 pF
Number of Pulse per pin – 3
Latch-up Minimum input voltage limit – 2.5 V
Maximum input voltage limit 7.5 V
Table 3-5. ESD and Latch-Up Protection Characteristics
Num C Rating Symbol Min Max Unit
1 C Human Body Model (HBM) VHBM 2000 – V
2 C Machine Model (MM) VMM 200 – V
3 C Charge Device Model (CDM) VCDM 500 – V
4C
Latch-up Current at TA = 125CI
LAT 100 – mA
m $2 $2 }|
Chapter 3 Electrical Characteristics and Timing Specifications
MC9S08AC128 MCU Series Data Sheet, Rev. 4
Freescale Semiconductor 15
Table 3-6. DC Characteristics
Num C Parameter Symbol Min Typ1Max Unit
1 — Operating Voltage VDD 2.7 — 5.5 V
2 P Output high voltage — Low Drive (PTxDSn = 0)
5 V, ILoad = –2 mA
3 V, ILoad = –0.6 mA
5 V, ILoad = –0.4 mA
3 V, ILoad = –0.24 mA
VOH
VDD – 1.5
VDD – 1.5
VDD – 0.8
VDD – 0.8
—
—
—
—
—
—
—
—
V
P Output high voltage — High Drive (PTxDSn = 1)
5 V, ILoad = –10 mA
3 V, ILoad = –3 mA
5 V, ILoad = –2 mA
3 V, ILoad = –0.4 mA
VDD – 1.5
VDD – 1.5
VDD – 0.8
VDD – 0.8
—
—
—
—
—
—
—
—
3 P Output low voltage — Low Drive (PTxDSn = 0)
5 V, ILoad = 2 mA
3 V, ILoad = 0.6 mA
5 V, ILoad = 0.4 mA
3 V, ILoad = 0.24 mA
VOL
—
—
—
—
—
—
—
—
1.5
1.5
0.8
0.8
V
P Output low voltage — High Drive (PTxDSn = 1)
5 V, ILoad = 10 mA
3 V, ILoad = 3 mA
5 V, ILoad = 2 mA
3 V, ILoad = 0.4 mA
—
—
—
—
—
—
—
—
1.5
1.5
0.8
0.8
4 P Output high current — Max total IOH for all ports
5V
3V
IOHT —
—
—
—
100
60
mA
P Output low current — Max total IOL for all ports
5V
3V
IOLT —
—
—
—
100
60
mA
5
6 P Input high 2.7v VDD 4.5v VIH 0.70xVDD ——
voltage; all
digital inputs 4.5v VDD 5.5v VIH 0.65xVDD ——V
7 P Input low voltage; all digital inputs VIL — — 0.35 x VDD
8 P Input hysteresis; all digital inputs Vhys 0.06 x VDD mV
9 P Input leakage current; input only pins2|IIn|—0.11A
10 P High Impedance (off-state) leakage current2|IOZ|—0.11A
11 P Internal pullup resistors3RPU 20 45 65 k
12 P Internal pulldown resistors4RPD 20 45 65 k
13 C Input Capacitance; all non-supply pins CIn —— 8pF
14 D RAM retention voltage VRAM —0.61.0V
15 P POR rearm voltage VPOR 0.9 1.4 2.0 V
16 D POR rearm time tPOR 10 — — s
17 P Low-voltage detection threshold — high range
VDD falling
VDD rising
VLVDH 4.2
4.3
4.3
4.4
4.4
4.5
V
18 P
Low-voltage detection threshold — low range
VDD falling
VDD rising
VLVDL 2.48
2.54
2.56
2.62
2.64
2.7
V
Chapter 3 Electrical Characteristics and Timing Specifications
MC9S08AC128 Series Data Sheet, Rev. 4
16 Freescale Semiconductor
Figure 3-1. Typical IOH (Low Drive) vs VDD–VOH at VDD = 3 V
19 P
Low-voltage warning threshold — high range
VDD falling
VDD rising
VLVWH 4.2
4.3
4.3
4.4
4.4
4.5
V
20 P Low-voltage warning threshold — low range
VDD falling
VDD rising
VLVW L 2.48
2.54
2.56
2.62
2.64
2.7
V
21
P
Low-voltage inhibit reset/recover hysteresis
5V
3V
Vhys —
—
100
60
—
—
mV
22 P Bandgap Voltage Reference5VBG 1.170 1.200 1.230 V
1Typical values are based on characterization data at 25C unless otherwise stated.
2Measured with VIn = VDD or VSS.
3Measured with VIn = VSS.
4Measured with VIn = VDD.
5Factory trimmed at VDD = 3.0 V, Temperature = 25 C.
Table 3-6. DC Characteristics (continued)
Num C Parameter Symbol Min Typ1Max Unit
–5.0E-3
–4.0E-3
–3.0E-3
–2.0E-3
–1.0E-3
000E+0 0 0.3 0.5 0.8 0.9 1.2 1.5
VDD–VOH (V)
VSupply–VOH
Average of IOH
IOH (A)
–40C
25C
125C
–6.0E-3
Chapter 3 Electrical Characteristics and Timing Specifications
MC9S08AC128 MCU Series Data Sheet, Rev. 4
Freescale Semiconductor 17
Figure 3-2. Typical IOH (High Drive) vs VDD–VOH at VDD = 3 V
Figure 3-3. Typical IOH (Low Drive) vs VDD–VOH at VDD = 5 V
Figure 3-4. Typical IOH (High Drive) vs VDD–VOH at VDD = 5 V
–20.0E-3
–18.0E-3
–16.0E-3
–14.0E-3
–12.0E-3
–10.0E-3
–8.0E-3
–6.0E-3
–4.0E-3
–2.0E-3
000.0E-3 0 0.3 0.5 0.8 0.9 1.2 1.5
VSupply–VOH
VDD–VOH (V)
Average of IOH
–40C
25C
125C
IOH (A)
–5.0E-3
–4.0E-3
–3.0E-3
–2.0E-3
–1.0E-3
000E+0 0.00 0.30
Average of IOH
–40C
25C
125C
–6.0E-3
–7.0E-3
0.50 0.80 1.00 1.30 2.00
VDD–VOH (V)
VSupply–VOH
IOH (A)
–40C
25C
125C
0.00 0.30 0.50 0.80 1.00 1.30 2.00
VSupply–VOH
–30.0E-3
–25.0E-3
–20.0E-3
–15.0E-3
–10.0E-3
–5.0E-3
000.0E+3
VDD–VOH (V)
IOH (A)
Average of IOH
Chapter 3 Electrical Characteristics and Timing Specifications
MC9S08AC128 Series Data Sheet, Rev. 4
18 Freescale Semiconductor
3.7 Supply Current Characteristics
Table 3-7. Supply Current Characteristics
Num C Parameter Symbol VDD
(V) Typ1
1Typical values are based on characterization data at 25C unless otherwise stated. See Figure 3-5 through Figure 3-7 for
typical curves across voltage/temperature.
Max Unit Temp
(C)
1C
Run supply current2 measured at
(CPU clock = 2 MHz, fBus = 1 MHz)
2All modules except ADC active, ICG configured for FBE, and does not include any dc loads on port pins
RIDD
51.11.4
3
3Every unit tested to this parameter. All other values in the Max column are guaranteed by characterization.
mA –40 to 125C
31.01.2
2C
Run supply current4 measured at
(CPU clock = 16 MHz, fBus = 8 MHz)
4All modules except ADC active, ICG configured for FBE, and does not include any dc loads on port pins
RIDD
56.78.0
5
5Every unit tested to this parameter. All other values in the Max column are guaranteed by characterization.
mA –40 to 125C
367.5
3C
Stop2 mode supply current
S2IDD
51.0
25
160 A–40 to 85C
–40 to 125C
30.8
23
150 A–40 to 85C
–40 to 125C
4C
Stop3 mode supply current
S3IDD
51.2
27
1803 A–40 to 85C
–40 to 125C
31.0
25
170 A–40 to 85C
–40 to 125C
5C
RTI adder to stop2 or stop36
6Most customers are expected to find that auto-wakeup from stop2 or stop3 can be used instead of the higher current wait
mode. Wait mode typical is 560 A at 3 V with fBus = 1 MHz.
S23IDDRTI
5300500
500 nA –40 to 85C
–40 to 125C
3300500
500 nA –40 to 85C
–40 to 125C
6 C LVD adder to stop3 (LVDE = LVDSE = 1) S3IDDLVD
5110180
180 A–40 to 85C
–40 to 125C
390160
160 A–40 to 85C
–40 to 125C
7C
Adder to stop3 for oscillator enabled7
(OSCSTEN =1)
7Values given under the following conditions: low range operation (RANGE = 0) with a 32.768kHz crystal, low power mode
(HGO = 0), clock monitor disabled (LOCD = 1).
S3IDDOSC
5,3 5 8
8
A
A
–40 to 85C
–40 to 125C
Chapter 3 Electrical Characteristics and Timing Specifications
MC9S08AC128 MCU Series Data Sheet, Rev. 4
Freescale Semiconductor 19
Figure 3-5. Typical Run IDD for FBE and FEE Modes, IDD vs. VDD
5.45.0
4.64.2
3.83.4
3.02.62.2
0
2
4
6
8
10
12
14
16
18
IDD
VDD
20 MHz, ADC off, FEE, 25C
20 MHz, ADC off, FBE, 25C
8 MHz, ADC off, FEE, 25C
8 MHz, ADC off, FBE, 25C
1 MHz, ADC off, FEE, 25C
1 MHz, ADC off, FBE, 25C
Note: External clock is square wave supplied by function generator. For FEE mode, external reference frequency is 4 MHz
:1
Chapter 3 Electrical Characteristics and Timing Specifications
MC9S08AC128 Series Data Sheet, Rev. 4
20 Freescale Semiconductor
Figure 3-6. Typical Stop 2 IDD
Figure 3-7. Typical Stop3 IDD
–5.0E-3
–4.0E-3
–3.0E-3
–2.0E-3
–1.0E-3
000E+0
–6.0E-3
–7.0E-3
–8.0E-3
1.8 2 2.5 3 3.5 4 4.5 5
Stop2 IDD (A)
Average of Measurement IDD
IDD (A)
VDD (V)
–40C
25C
55C
85C
–5.0E-3
–4.0E-3
–3.0E-3
–2.0E-3
–1.0E-3
000E+0
–6.0E-3
–7.0E-3
–8.0E-3
1.8 2 2.5 3 3.5 4 4.5 5
Stop3 IDD (A)
Average of Measurement IDD
IDD (A)
VDD (V)
25C
55C
85C
–40C
Chapter 3 Electrical Characteristics and Timing Specifications
MC9S08AC128 MCU Series Data Sheet, Rev. 4
Freescale Semiconductor 21
3.8 ADC Characteristics
Table 3-8. 5 Volt 10-bit ADC Operating Conditions
Characteristic Conditions Symb Min Typ1
1Typical values assume VDDAD = 5.0 V, Temp = 25C, fADCK = 1.0 MHz unless otherwise stated. Typical values are for reference
only and are not tested in production.
Max Unit
Supply voltage
Absolute VDDAD 2.7 — 5.5 V
Delta to VDD (VDD–VDDAD)2
2dc potential difference.
VDDAD –100 0 +100 mV
Ground voltage Delta to VSS (VSS–VSSAD)2VSSAD –100 0 +100 mV
Ref voltage high VREFH 2.7 VDDAD VDDAD V
Ref voltage low VREFL VSSAD VSSAD VSSAD V
Supply current Stop, reset, module off IDDAD — 0.011 1 A
Input voltage VADIN VREFL —V
REFH V
Input capacitance CADIN —4.55.5pF
Input resistance RADIN —3 5k
Analog source resistance
External to MCU
10-bit mode
fADCK > 4MHz
fADCK < 4MHz RAS
—
—
—
—
5
10 k
8-bit mode (all valid fADCK)——10
ADC conversion clock frequency
High speed (ADLPC = 0)
fADCK
0.4 — 8.0
MHz
Low power (ADLPC = 1) 0.4 — 4.0
Temp Sensor
Slope
–40C to 25C
m—
3.266 — mV/
C
25C to 125C 3.638 —
Temp Sensor
Voltage 25CV
TEMP25 — 1.396 — V
SIMPUFIED \\\\\\ \\\\\\ \\\\\\\
Chapter 3 Electrical Characteristics and Timing Specifications
MC9S08AC128 Series Data Sheet, Rev. 4
22 Freescale Semiconductor
Figure 3-8. ADC Input Impedance Equivalency Diagram
+
–
+
–
V
AS
R
AS
C
AS
V
ADIN
Z
AS
Pad
leakage
due to
input
protection
Z
ADIN
SIMPLIFIED
INPUT PIN EQUIVALENT
CIRCUIT
R
ADIN
ADC SAR
ENGINE
SIMPLIFIED
CHANNEL SELECT
CIRCUIT
INPUT PIN
R
ADIN
C
ADIN
INPUT PIN
R
ADIN
INPUT PIN
R
ADIN
Chapter 3 Electrical Characteristics and Timing Specifications
MC9S08AC128 MCU Series Data Sheet, Rev. 4
Freescale Semiconductor 23
Table 3-9. 5 Volt 10-bit ADC Characteristics (VREFH = VDDAD, VREFL = VSSAD)
Characteristic Conditions C Symb Min Typ1Max Unit
Supply current
ADLPC = 1
ADLSMP = 1
ADCO = 1
TI
DDAD — 133 — A
Supply current
ADLPC = 1
ADLSMP = 0
ADCO = 1
TI
DDAD — 218 — A
Supply current
ADLPC = 0
ADLSMP = 1
ADCO = 1
TI
DDAD — 327 — A
Supply current
ADLPC = 0
ADLSMP = 0
ADCO = 1
TI
DDAD — 582 — A
VDDAD < 5.5 V P——1mA
ADC asynchronous clock source
tADACK = 1/fADACK
High speed (ADLPC = 0) PfADACK 23.35MHz
Low power (ADLPC = 1) 1.25 2 3.3
Conversion time
(Including sample time)
Short sample (ADLSMP = 0) P tADC —20—ADCK
cycles
Long sample (ADLSMP = 1) —40—
Sample time Short sample (ADLSMP = 0) P tADS —3.5—ADCK
cycles
Long sample (ADLSMP = 1) — 23.5 —
Total unadjusted error
Includes quantization
10-bit mode P ETUE —12.5 LSB2
8-bit mode — 0.5 1.0
Differential non-linearity
10-bit mode P DNL — 0.5 1.0 LSB2
8-bit mode — 0.3 0.5
Monotonicity and no-missing-codes guaranteed
Integral non-linearity
10-bit mode C INL — 0.5 1.0 LSB2
8-bit mode — 0.3 0.5
Zero-scale error
VADIN = VSSA
10-bit mode PEZS —0.5 1.5 LSB2
8-bit mode — 0.5 0.5
Full-scale error
VADIN = VDDA
10-bit mode PEFS —0.5 1.5 LSB2
8-bit mode — 0.5 0.5
Quantization error
10-bit mode D EQ——0.5 LSB2
8-bit mode — — 0.5
Chapter 3 Electrical Characteristics and Timing Specifications
MC9S08AC128 Series Data Sheet, Rev. 4
24 Freescale Semiconductor
3.9 Internal Clock Generation Module Characteristics
Input leakage error
Pad leakage3 * RAS
10-bit mode D EIL —0.2 2.5 LSB2
8-bit mode — 0.1 1
1Typical values assume VDDAD = 5.0V, Temp = 25C, fADCK=1.0 MHz unless otherwise stated. Typical values are for reference
only and are not tested in production.
21 LSB = (VREFH – VREFL)/2N
3Based on input pad leakage current. Refer to pad electricals.
Table 3-10. ICG DC Electrical Specifications (Temperature Range = –40 to 125C Ambient)
Characteristic Symbol Min Typ1
1Typical values are based on characterization data at VDD = 5.0V, 25C or is typical recommended value.
Max Unit
Load capacitors C1
C2
See Note 2
2See crystal or resonator manufacturer’s recommendation.
Feedback resistor
Low range (32k to 100 kHz)
High range (1M – 16 MHz)
RF10
1
M
M
Series resistor
Low range
Low Gain (HGO = 0)
High Gain (HGO = 1)
High range
Low Gain (HGO = 0)
High Gain (HGO = 1)
8 MHz
4 MHz
MHz
RS
—
—
—
—
—
—
0
100
0
0
10
20
—
—
—
—
—
—
k
Table 3-9. 5 Volt 10-bit ADC Characteristics (VREFH = VDDAD, VREFL = VSSAD)
Characteristic Conditions C Symb Min Typ1Max Unit
ICG
EXTAL XTAL
Crystal or Resonator
R
S
C2
RF
C1
Chapter 3 Electrical Characteristics and Timing Specifications
MC9S08AC128 MCU Series Data Sheet, Rev. 4
Freescale Semiconductor 25
3.9.1 ICG Frequency Specifications
Table 3-11. ICG Frequency Specifications
(VDDA = VDDA (min) to VDDA (max), Temperature Range = –40 to 125C Ambient)
Num C Characteristic Symbol Min Typ1
1Typical values are based on characterization data at VDD = 5.0V, 25C unless otherwise stated.
Max Unit
1
Oscillator crystal or resonator (REFS = 1)
(Fundamental mode crystal or ceramic resonator)
Low range
High range
High Gain, FBE (HGO = 1,CLKS = 10)
High Gain, FEE (HGO = 1,CLKS = 11)
Low Power, FBE (HGO = 0, CLKS = 10)
Low Power, FEE (HGO = 0, CLKS = 11)
flo
fhi_byp
fhi_eng
flp_byp
flp_eng
32
1
2
1
2
—
—
—
100
16
10
8
8
kHz
MHz
MHz
MHz
MHz
2
Input clock frequency (CLKS = 11, REFS = 0)
Low range
High range
flo
fhi_eng
32
2
—
—
100
10
kHz
MHz
3Input clock frequency (CLKS = 10, REFS = 0) fExtal 0—40MHz
4Internal reference frequency (untrimmed) fICGIRCLK 182.25 243 303.75 kHz
5Duty cycle of input clock (REFS = 0) tdc 40 — 60 %
6
Output clock ICGOUT frequency
CLKS = 10, REFS = 0
All other cases
fICGOUT fExtal (min)
flo (min)
—
—
fExtal (max)
fICGDCLKmax(
max)
MHz
7 Minimum DCO clock (ICGDCLK) frequency fICGDCLKmin 3— MHz
8 Maximum DCO clock (ICGDCLK) frequency fICGDCLKmax —40MHz
9 Self-clock mode (ICGOUT) frequency 2
2Self-clocked mode frequency is the frequency that the DCO generates when the FLL is open-loop.
fSelf fICGDCLKmin fICGDCLKmax MHz
10 Self-clock mode reset (ICGOUT) frequency fSelf_reset 5.5 8 10.5 MHz
11
Loss of reference frequency 3
Low range
High range
fLOR 5
50
25
500 kHz
12 Loss of DCO frequency 4fLOD 0.5 1.5 MHz
13
Crystal start-up time 5, 6
Low range
High range
tCSTL
tCSTH
—
—
430
4
—
—ms
14
FLL lock time , 7
Low range
High range
tLockl
tLockh
—
—
2
2
ms
15 FLL frequency unlock range nUnlock –4*N 4*N counts
16 FLL frequency lock range nLock –2*N 2*N counts
17 ICGOUT period jitter, , 8 measured at fICGOUT Max
Long term jitter (averaged over 2 ms interval) CJitter —0.2
% fICG
18
Internal oscillator deviation from trimmed
frequency9
VDD = 2.7 – 5.5 V, (constant temperature)
VDD = 5.0 V 10%, –40 C to 125C
ACCint —
—
0.5
0.5 2
2%
2 E35. Tnmp
Chapter 3 Electrical Characteristics and Timing Specifications
MC9S08AC128 Series Data Sheet, Rev. 4
26 Freescale Semiconductor
Figure 3-9. Internal Oscillator Deviation from Trimmed Frequency
3Loss of reference frequency is the reference frequency detected internally, which transitions the ICG into self-clocked mode if it
is not in the desired range.
4Loss of DCO frequency is the DCO frequency detected internally, which transitions the ICG into FLL bypassed external mode (if
an external reference exists) if it is not in the desired range.
5This parameter is characterized before qualification rather than 100% tested.
6Proper PC board layout procedures must be followed to achieve specifications.
7This specification applies to the period of time required for the FLL to lock after entering FLL engaged internal or external modes.
If a crystal/resonator is being used as the reference, this specification assumes it is already running.
8Jitter is the average deviation from the programmed frequency measured over the specified interval at maximum fICGOUT
.
Measurements are made with the device powered by filtered supplies and clocked by a stable external clock signal. Noise
injected into the FLL circuitry via VDDA and VSSA and variation in crystal oscillator frequency increase the CJitter percentage for
a given interval.
9See Figure 3-9
Average of Percentage Error
3 V
5 V
Variable
Chapter 3 Electrical Characteristics and Timing Specifications
MC9S08AC128 MCU Series Data Sheet, Rev. 4
Freescale Semiconductor 27
3.10 AC Characteristics
This section describes ac timing characteristics for each peripheral system.
3.10.1 Control Timing
Figure 3-10. Reset Timing
Table 3-12. Control Timing
Num C Parameter Symbol Min Typ1
1Typical values are based on characterization data at VDD = 5.0V, 25C unless otherwise stated.
Max Unit
1 Bus frequency (tcyc = 1/fBus)f
Bus dc — 20 MHz
2Real-time interrupt internal oscillator period tRTI 600 1500 s
External reset pulse width2
(tcyc = 1/fSelf_reset)
2This is the shortest pulse that is guaranteed to be recognized as a reset pin request. Shorter pulses are not guaranteed to
override reset requests from internal sources.
textrst
1.5 x
tSelf_reset —ns
4Reset low drive3
3When any reset is initiated, internal circuitry drives the reset pin low for about 34 bus cycles and then samples the level on
the reset pin about 38 bus cycles later to distinguish external reset requests from internal requests.
trstdrv 34 x tcyc —ns
5Active background debug mode latch setup time tMSSU 25 — ns
6Active background debug mode latch hold time tMSH 25 — ns
7
IRQ pulse width
Asynchronous path2
Synchronous path4
4This is the minimum pulse width that is guaranteed to pass through the pin synchronization circuitry. Shorter pulses may or
may not be recognized. In stop mode, the synchronizer is bypassed so shorter pulses can be recognized in that case.
tILIH, tIHIL 100
1.5 x tcyc
——ns
8 KBIPx pulse width
Asynchronous path2
Synchronous path3
tILIH, tIHIL 100
1.5 x tcyc
——ns
9
Port rise and fall time (load = 50 pF)5
Slew rate control disabled (PTxSE = 0)
Slew rate control enabled (PTxSE = 1)
5Timing is shown with respect to 20% VDD and 80% VDD levels. Temperature range –40C to 125C.
tRise, tFall —
—
3
30
ns
textrst
RESET PIN
Chapter 3 Electrical Characteristics and Timing Specifications
MC9S08AC128 Series Data Sheet, Rev. 4
28 Freescale Semiconductor
Figure 3-11. Active Background Debug Mode Latch Timing
Figure 3-12. IRQ/KBIPx Timing
3.10.2 Timer/PWM (TPM) Module Timing
Synchronizer circuits determine the shortest input pulses that can be recognized or the fastest clock that can be used as the
optional external source to the timer counter. These synchronizers operate from the current bus rate clock.
Table 3-13. TPM Input Timing
Function Symbol Min Max Unit
External clock frequency fTPMext dc fBus/4 MHz
External clock period tTPMext 4—
tcyc
External clock high time tclkh 1.5 — tcyc
External clock low time tclkl 1.5 — tcyc
Input capture pulse width tICPW 1.5 — tcyc
BKGD/MS
RESET
tMSSU
tMSH
tIHIL
IRQ/KBIP7-KBIP4
tILIH
IRQ/KBIPx
Chapter 3 Electrical Characteristics and Timing Specifications
MC9S08AC128 MCU Series Data Sheet, Rev. 4
Freescale Semiconductor 29
Figure 3-13. Timer External Clock
Figure 3-14. Timer Input Capture Pulse
tTPMext
tclkh
tclkl
TPMxCLK
tICPW
TPMxCHn
tICPW
TPMxCHn
Chapter 3 Electrical Characteristics and Timing Specifications
MC9S08AC128 Series Data Sheet, Rev. 4
30 Freescale Semiconductor
3.11 SPI Characteristics
Table 3-14 and Figure 3-15 through Figure 3-18 describe the timing requirements for the SPI system.
Table 3-14. SPI Electrical Characteristic
Num1
1Refer to Figure 3-15 through Figure 3-18.
C Characteristic2
2All timing is shown with respect to 20% VDD and 70% VDD, unless noted; 100 pF load on all SPI
pins. All timing assumes slew rate control disabled and high drive strength enabled for SPI output
pins.
Symbol Min Max Unit
Operating frequency3
Master
Slave
3Maximum baud rate must be limited to 5 MHz due to pad input characteristics.
fop
fop
fBus/2048
dc
fBus/2
fBus/4
Hz
1Cycle time
Master
Slave
tSCK
tSCK
2
4
2048
—
tcyc
tcyc
2Enable lead time
Master
Slave
tLead
tLead
—
1/2
1/2
—
tSCK
tSCK
3Enable lag time
Master
Slave
tLag
tLag
—
1/2
1/2
—
tSCK
tSCK
4Clock (SPSCK) high time
Master and Slave tSCKH 1/2 tSCK – 25 — ns
5Clock (SPSCK) low time Master
and Slave tSCKL 1/2 tSCK – 25 — ns
6Data setup time (inputs)
Master
Slave
tSI(M)
tSI(S)
30
30
—
—
ns
ns
7Data hold time (inputs)
Master
Slave
tHI(M)
tHI(S)
30
30
—
—
ns
ns
8Access time, slave4
4Time to data active from high-impedance state.
tA040ns
9Disable time, slave5
5Hold time to high-impedance state.
tdis —40ns
10 Data setup time (outputs)
Master
Slave
tSO
tSO
25
25
—
—
ns
ns
11 Data hold time (outputs)
Master
Slave
tHO
tHO
–10
–10
—
—
ns
ns
g J?) X ; + r )J \ u V0 0 E? *O* E
Chapter 3 Electrical Characteristics and Timing Specifications
MC9S08AC128 MCU Series Data Sheet, Rev. 4
Freescale Semiconductor 31
Figure 3-15. SPI Master Timing (CPHA = 0)
Figure 3-16. SPI Master Timing (CPHA = 1)
SCK
(OUTPUT)
SCK
(OUTPUT)
MISO
(INPUT)
MOSI
(OUTPUT)
SS1
(OUTPUT)
MSB IN2
BIT 6 . . . 1
LSB IN
MSB OUT2LSB OUT
BIT 6 . . . 1
(CPOL = 0)
(CPOL = 1)
NOTES:
2. LSBF = 0. For LSBF = 1, bit order is LSB, bit 1, ..., bit 6, MSB.
1. SS output mode (MODFEN = 1, SSOE = 1).
1
23
5
67
10 11
5
10
4
4
SCK
(OUTPUT)
SCK
(OUTPUT)
MISO
(INPUT)
MOSI
(OUTPUT)
MSB IN(2)
BIT 6 . . . 1
LSB IN
MSB OUT(2) LSB OUT
BIT 6 . . . 1
(CPOL = 0)
(CPOL = 1)
SS(1)
(OUTPUT)
1. SS output mode (MODFEN = 1, SSOE = 1).
2. LSBF = 0. For LSBF = 1, bit order is LSB, bit 1, ..., bit 6, MSB.
NOTES:
2
1
3
4
5
67
10 11
5
4
Chapter 3 Electrical Characteristics and Timing Specifications
MC9S08AC128 Series Data Sheet, Rev. 4
32 Freescale Semiconductor
Figure 3-17. SPI Slave Timing (CPHA = 0)
Figure 3-18. SPI Slave Timing (CPHA = 1)
SCK
(INPUT)
SCK
(INPUT)
MOSI
(INPUT)
MISO
(OUTPUT)
SS
(INPUT)
MSB IN
BIT 6 . . . 1
LSB IN
MSB OUT SLAVE LSB OUT
BIT 6 . . . 1
(CPOL = 0)
(CPOL = 1)
NOTE:
SLAVE SEE
NOTE
1. Not defined but normally MSB of character just received
1
2
3
4
67
8
9
10 11
5
5
4
SCK
(INPUT)
SCK
(INPUT)
MOSI
(INPUT)
MISO
(OUTPUT)
MSB IN
BIT 6 . . . 1
LSB IN
MSB OUT SLAVE LSB OUT
BIT 6 . . . 1
SEE
(CPOL = 0)
(CPOL = 1)
SS
(INPUT)
NOTE:
SLAVE
NOTE
1. Not defined but normally LSB of character just received
1
2
3
4
67
8
9
10 11
4
5
5
Chapter 3 Electrical Characteristics and Timing Specifications
MC9S08AC128 MCU Series Data Sheet, Rev. 4
Freescale Semiconductor 33
3.12 FLASH Specifications
This section provides details about program/erase times and program-erase endurance for the Flash memory.
Program and erase operations do not require any special power sources other than the normal VDD supply.
Table 3-15. Flash Characteristics
Num C Characteristic Symbol Min Typ1
1Typical values are based on characterization data at VDD = 5.0 V, 25C unless otherwise stated.
Max Unit
1P
Supply voltage for program/erase Vprog/erase 2.7 5.5 V
2P
Supply voltage for read operation VRead 2.7 5.5 V
PInternal FCLK frequency2
2The frequency of this clock is controlled by a software setting.
fFCLK 150 200 kHz
4P
Internal FCLK period (1/FCLK) tFcyc 56.67s
5P
Byte program time (random location)(2) tprog 9tFcyc
6C
Byte program time (burst mode)(2) tBurst 4tFcyc
7P
Page erase time3
3These values are hardware state machine controlled. User code does not need to count cycles. This information
supplied for calculating approximate time to program and erase.
tPage 4000 tFcyc
8P
Mass erase time(2) tMass 20,000 tFcyc
9C
Program/erase endurance4
TL to TH = –40C to + 125C
T = 25C
4Typical endurance for Flash was evaluated for this product family on the 9S12Dx64. For additional information on
how Freescale Semiconductor defines typical endurance, please refer to Engineering Bulletin EB619/D, Ty p i c a l
Endurance for Nonvolatile Memory.
10,000
—
—
100,000
—
—
cycles
10 C Data retention5
5Typical data retention values are based on intrinsic capability of the technology measured at high temperature and
de-rated to 25C using the Arrhenius equation. For additional information on how Freescale Semiconductor defines
typical data retention, please refer to Engineering Bulletin EB618/D, Typical Data Retention for Nonvolatile Memory.
tD_ret 15 100 — years
Chapter 3 Electrical Characteristics and Timing Specifications
MC9S08AC128 Series Data Sheet, Rev. 4
34 Freescale Semiconductor
3.13 EMC Performance
Electromagnetic compatibility (EMC) performance is highly dependant on the environment in which the MCU resides. Board
design and layout, circuit topology choices, location and characteristics of external components as well as MCU software
operation all play a significant role in EMC performance. The system designer should consult Freescale applications notes such
as AN2321, AN1050, AN1263, AN2764, and AN1259 for advice and guidance specifically targeted at optimizing EMC
performance.
3.13.1 Radiated Emissions
Microcontroller radiated RF emissions are measured from 150 kHz to 1 GHz using the TEM/GTEM Cell method in accordance
with the IEC 61967-2 and SAE J1752/3 standards. The measurement is performed with the microcontroller installed on a
custom EMC evaluation board while running specialized EMC test software. The radiated emissions from the microcontroller
are measured in a TEM cell in two package orientations (North and East). For more detailed information concerning the
evaluation results, conditions and setup, please refer to the EMC Evaluation Report for this device.
The maximum radiated RF emissions of the tested configuration in all orientations are less than or equal to the reported
emissions levels.
Table 3-16. Radiated Emissions
Parameter Symbol Conditions Frequency fOSC/fBUS
Level1
(Max)
1Data based on laboratory test results.
Unit
Radiated emissions,
electric field and magnetic field
VRE_TEM VDD = 5.0 V
TA = +25oC
package type
80 LQFP
0.15 – 50 MHz 32kHz crystal
20MHz Bus
30 dBV
50 – 150 MHz 32
150 – 500 MHz 19
500 – 1000 MHz 7
IEC Level I2
2IEC and SAE Level Maximums: I=36 dBuV.
—
SAE Level I2—
£E
MC9S08AC128 Series Data Sheet, Rev. 4
Freescale Semiconductor 35
Chapter 4
Ordering Information and Mechanical Drawings
4.1 Ordering Information
This section contains ordering numbers for MC9S08AC128 Series devices. See below for an example of the device numbering
system.
4.2 Orderable Part Numbering System
4.3 Mechanical Drawings
Table 4-2 provides the available package types and their document numbers. The latest package outline/mechanical drawings
are available on the MC9S08AC128 Series Product Summary pages at http://www.freescale.com.
To view the latest drawing, either:
• Click on the appropriate link in Table 4-2, or
• Open a browser to the Freescale® website (http://www.freescale.com), and enter the appropriate document number (from
Table 4-2) in the “Enter Keyword” search box at the top of the page.
Table 4-1. Device Numbering System
Device Number
Memory Available Packages1
1See Ta b l e 4 - 2 for package information.
FLASH RAM Type
MC9S08AC128 128K 8K 80 LQFP, 64 QFP, 48-QFN, 44-LQFP
MC9S08AC96 96K 6K 80 LQFP, 64 QFP, 48-QFN, 44-LQFP
Table 4-2. Package Information
Pin Count Type Designator Document No.
80 LQFP LK 98ASS23237W
64 QFP FU 98ASB42844B
48 QFN FT 98ARH99048A
44 LQFP FG 98ASS23225W
Package designator
Temperature range
Family
Memory
Status
Core
Pb free indicator
(C = –40C to 85C)
(M = –40C to 125C)
(MC = Fully Qualified)
(9 = FLASH-based)
MC 9 S08 AC C XX E
Approximate memory size (in KB)
(See Ta bl e 4 - 2 )
128
Chapter 4 Ordering Information and Mechanical Drawings
MC9S08AC128 Series Data Sheet, Rev. 4
36 Freescale Semiconductor
MC9S08AC128 MCU Series Data Sheet, Rev. 4
Freescale Semiconductor 37
Chapter 5
Revision History
To provide the most up-to-date information, the version of our documents on the World Wide Web will be
the most current. Your printed copy may be an earlier revision. To verify you have the latest information
available, refer to:
http://freescale.com/
The following revision history table summarizes changes contained in this document.
Revision
Number
Revision
Date Description of Changes
19/2008
Initial release of a separate data sheet and reference manual. Removed PTH7,
clarified SPI as one full and one master-only, added missing RoHS logo, updated
back cover addresses, and incorporated general release edits and updates.
Added some finalized electrical characteristics.
26/2009
Added the parameter “Bandgap Voltage Reference” in Ta b le 3 -6
Updated Section 3.13, “EMC Performance” and corrected Ta b le 3 - 1 6 .
Updated disclaimer page.
3 9/2010 Added 48-pin QFN package information.
48/2011
Updated the tRTI in the Ta b l e 3 - 1 2 .
Updated the RIDD in the Ta bl e 3 - 7 .
MC9S08AC128 MCU Series Data Sheet, Rev. 4
Freescale Semiconductor 38
0" :9 freescale" samfconductol
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MC9S08AC128, Rev. 4
08/2011