Datenblatt für TS321 von Texas Instruments

V'.‘ I TEXAS INSTRUMENTS !_H_H_H_\ \_H_H_H_l
1
2
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OUT VCC+
34
IN+ IN–
VCC–
1
2
36
7
8
45
OUT
VCC+
IN–
IN+
VCC– NC
NCNC
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An IMPORTANT NOTICE at the end of this data sheet addresses availability, warranty, changes, use in safety-critical applications,
intellectual property matters and other important disclaimers. PRODUCTION DATA.
TS321
SLOS489D –DECEMBER 2005–REVISED MAY 2018
TS321 Low-Power Single Operational Amplifier
1
1 Features
1• Wide Power-Supply Range
– Single Supply from 3 V to 30 V
– Dual Supply from ±1.5 V to ±15 V
• Large Output Voltage Swing from
0 V to 3.5 V (Minimum) (VCC = 5 V)
• Low Supply Current at 500 μA (Typical)
• Low Input Bias Current at 20 nA (Typical)
• Stable With High Capacitive Loads
2 Applications
• Desktop PCs
• HVAC: Heating, Ventilating, and Air Conditioning
• Portable Media Players
• Refrigerators
• Washing Machines: High-End and Low-End
3 Description
The TS321 is a bipolar operational amplifier for cost-
sensitive applications in which space savings are
important.
Device Information(1)
PART NUMBER PACKAGE BODY SIZE (NOM)
TS321 SOIC (8) 4.90 mm × 3.90 mm
SOT-23 (5) 2.90 mm × 1.60 mm
(1) For all available packages, see the orderable addendum at
the end of the data sheet.
l TEXAS INSTRUMENTS
2
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Table of Contents
1 Features.................................................................. 1
2 Applications ........................................................... 1
3 Description ............................................................. 1
4 Revision History..................................................... 2
5 Pin Configuration and Functions......................... 3
6 Specifications......................................................... 4
6.1 Absolute Maximum Ratings ..................................... 4
6.2 ESD Ratings.............................................................. 4
6.3 Recommended Operating Conditions....................... 4
6.4 Thermal Information: TS321 ..................................... 4
6.5 Electrical Characteristics........................................... 5
6.6 Typical Characteristics.............................................. 7
7 Detailed Description.............................................. 8
7.1 Overview ................................................................... 8
7.2 Functional Block Diagram......................................... 8
7.3 Feature Description................................................... 8
7.4 Device Functional Modes.......................................... 9
8 Application and Implementation ........................ 10
8.1 Application Information............................................ 10
8.2 Typical Application ................................................. 10
9 Power Supply Recommendations...................... 12
10 Layout................................................................... 12
10.1 Layout Guidelines ................................................. 12
10.2 Layout Example .................................................... 12
11 Device and Documentation Support ................. 14
11.1 Documentation Support ....................................... 14
11.2 Trademarks........................................................... 14
11.3 Electrostatic Discharge Caution............................ 14
11.4 Glossary................................................................ 14
4 Revision History
Changes from Revision C (April 2015) to Revision D Page
• Corrected SOIC package pinout quantity from "SOIC (14)" to "SOIC (8)" in Device Information table................................. 1
Changes from Revision B (December 2013) to Revision C Page
• Added Pin Configuration and Functions section, ESD Ratings table, Feature Description section, Device Functional
Modes,Application and Implementation section, Power Supply Recommendations section, Layout section, Device
and Documentation Support section, and Mechanical, Packaging, and Orderable Information section .............................. 1
l TEXAS INSTRUMENTS flyfl \_H_H_H_l
1
2
5
OUT VCC+
34
IN+ IN–
VCC–
1
2
36
7
8
45
OUT
VCC+
IN–
IN+
VCC– NC
NCNC
3
TS321
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5 Pin Configuration and Functions
D Package
8-Pin SOIC
(Top View)
NC - no internal connection
DBV Package
5-Pin SOT-23
(Top View)
Pin Functions
PIN I/O DESCRIPTION
NAME SOIC SOT-23
IN– 2 4 I Negative input
IN+ 3 3 I Positive input
NC
1
— — Do not connect5
8
OUT 6 1 O Output
VCC– 4 2 — Negative supply
VCC+ 7 5 — Positive supply
l TEXAS INSTRUMENTS
4
TS321
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(1) Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. These are stress ratings
only, and functional operation of the device at these or any other conditions beyond those indicated under Recommended Operating
Conditions is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
(2) Differential voltages are at IN+ with respect to IN–.
(3) Input voltages are at IN with respect to VCC–.
6 Specifications
6.1 Absolute Maximum Ratings
over operating free-air temperature range (unless otherwise noted)(1)
MIN MAX UNIT
Supply voltage, VCC Single supply 32 V
Dual supplies ±16
Differential input voltage(2),VID ±32 V
Input voltage range (3), VI–0.3 32 V
Input current, IIK 50 mA
Duration of output short circuit to ground, tshort Unlimited
Operating virtual junction temperature, TJ150 °C
Storage temperature, Tstg –65 150 °C
(1) JEDEC document JEP155 states that 500-V HBM allows safe manufacturing with a standard ESD control process.
(2) JEDEC document JEP157 states that 250-V CDM allows safe manufacturing with a standard ESD control process.
6.2 ESD Ratings
VALUE UNIT
V(ESD) Electrostatic discharge
Human-body model (HBM), per ANSI/ESDA/JEDEC JS-001(1) ±2500
V
Charged-device model (CDM), per JEDEC specification JESD22-
C101(2) ±1500
6.3 Recommended Operating Conditions
MIN MAX UNIT
VCC Supply voltage Single supply 3 30 V
Dual supply ±1.5 ±15
TAOperating free-air temperature –40 125 °C
(1) For more information about traditional and new thermal metrics, see the Semiconductor and IC Package Thermal Metrics application
report.
(2) Maximum power dissipation is a function of TJ(max), qJA, and TA. The maximum allowable power dissipation at any allowable ambient
temperature is PD = [TJ(max) – TA] / qJA. Selecting the maximum of 150°C can effect reliability.
(3) The package thermal impedance is calculated in accordance with JESD 51-7.
6.4 Thermal Information: TS321
THERMAL METRIC(1) (2)(3)
TS321
UNITD (SOIC) DBV (SOT-23)
5 PINS 5 PINS
RθJA Junction-to-ambient thermal resistance 97 206 °C/W
l TEXAS INSTRUMENTS
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(1) The direction of the input current is out of the device. This current essentially is constant, independent of the state of the output, so no
loading change exists on the input lines.
(2) The input common-mode voltage of either input signal should not be allowed to go negative by more than 0.3 V. The upper end of the
common-mode voltage range is VCC+ – 1.5 V, but either or both inputs can go to 32 V without damage.
6.5 Electrical Characteristics
VCC+ = 5 V, VCC– = GND, VO= 1.4 V (unless otherwise noted)
PARAMETER TEST CONDITIONS MIN TYP MAX UNIT
VIO Input offset voltage RS= 0, 5 V < VCC+ < 30 V
0 < VIC < (VCC+ – 1.5 V)
TA= 25°C 0.5 4 mV
TA= Full range 5
IIO Input offset current TA= 25°C 2 30 nA
TA= Full range 50
IIB Input bias current(1) TA= 25°C 20 150 nA
TA= Full range 200
AVD Large-signal differential
voltage amplification VCC = 15 V, RL= 2 kΩ
VO= 1.4 V to 11.4 V
TA= 25°C 50 100 V/mV
TA= Full range 25
VICR Common-mode input
voltage(2) VCC = 30 V TA= 25°C 0 VCC+ – 1.5 V
TA= Full range 0 VCC+ – 2
VOH High-level output voltage
VCC = 30 V
RL= 2 kΩ
TA= 25°C 26 27
V
TA= Full range 25.5
VCC = 30 V
RL= 10 kΩ
TA= 25°C 27 28
TA= Full range 26.5
VCC = 5 V
RL= 2 kΩ
TA= 25°C 3.5
TA= Full range 3
VOL Low-level output voltage RL= 10 kΩTA= 25°C 5 15 mV
TA= Full range 20
GBP Gain bandwidth product VCC = 30 V, VI= 10 mV, RL= 2 kΩ
f = 100 kHz, CL= 100 pF
TA= 25°C 0.8 MHz
SR Slew rate VCC = 15 V, VI= 0.5 V to 3 V, RL= 2 kΩ,
CL= 100 pF, unity gain,
TA= 25°C 0.4 V/µs
φmPhase margin TA= 25°C 60 °
CMRR Common-mode rejection ratio RS≤10 kΩ
TA= 25°C 65 85 dB
ISOURCE Output source current VCC = 15 V, VO= 2 V, VID = 1 V
TA= 25°C 20 40 mA
ISINK Output sink current
VCC = 15 V, VID = 1 V
VO= 2 V
TA= 25°C 10 20 mA
VCC = 15 V, VID = 1 V
VO= 0.2 V
TA= 25°C 12 50 µA
IOShort-circuit to GND VCC = 15 V, TA= 25°C 40 60 mA
SVR Supply-voltage rejection ratio VCC = 5 V to 30 V, TA= 25°C 65 110 dB
ICC Total supply current
VCC = 5 V
TA= 25°C, no load 500 800
µA
VCC = 30 V
TA= 25°C, no load 600 900
VCC = 5 V
TA= full range, no load 600 900
VCC = 30 V
TA= full range, no load 1000
THD Total harmonic distortion VCC = 30 V, VO= 2 Vpp, AV= 20 dB
RL= 2 k, f = 1 kHz, CL= 100 pF, TA= 25°C 0.015%
l TEXAS INSTRUMENTS
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Electrical Characteristics (continued)
VCC+ = 5 V, VCC– = GND, VO= 1.4 V (unless otherwise noted)
PARAMETER TEST CONDITIONS MIN TYP MAX UNIT
eNEquivalent input noise voltage VCC = 30 V, f = 1 kHz, RS= 100 Ω
TA= 25°C 50
l TEXAS INSTRUMENTS
0
5
10
15
20
25
±50 ±25 0 25 50 75 100 125
Output (mA)
Temperature (C)
Vcc = 15V
C001
±45
±40
±35
±30
±25
±20
±15
±10
±5
0
±50 ±25 0 25 50 75 100 125
Output (mA)
Temperature (C)
Vcc = 15V
C001
C001
0.0
0.5
1.0
1.5
2.0
2.5
±50 ±25 0 25 50 75 100 125
Voltage from Vcc+ (V)
Temperature (C)
Iout = 3mA
Iout = 15mA
C001
0
5
10
15
20
25
30
35
40
45
±50 ±25 0 25 50 75 100 125
Input Bias (nA)
Temperature (C)
Vcc = 5V
C001
0.0
0.1
0.2
0.3
0.4
0.5
0.6
0.7
0.8
±50 ±25 0 25 50 75 100 125
ICC (mA)
Temperature (C)
Vcc = 5V
Vcc = 30V
C001
7
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(1) Short circuits from outputs to VCC can cause excessive heating and eventual destruction.
6.6 Typical Characteristics
Figure 1. Input Current vs Temperature Figure 2. Supply Current vs Temperature
Figure 3. Output Sinking Characteristics Figure 4. Output Sourcing Characteristics
Figure 5. Short-Circuit Current to Supply (1) Figure 6. Short-Circuit Current to Ground
l TEXAS INSTRUMENTS
VCC
IN–
IN+
OUT
8
TS321
SLOS489D –DECEMBER 2005–REVISED MAY 2018
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7 Detailed Description
7.1 Overview
The TS321 is a single-channel operational amplifier. The device can handle a single supply between 3 V and 30
V or a dual-supply between ±1.5 V and ±15 V. Available in the small SOT-23 package, the TS321 is great for
saving space in any application.
7.2 Functional Block Diagram
7.3 Feature Description
7.3.1 Operating Voltage
The TS321 can be powered from a single supply between 3 V and 30 V or a dual-supply between ±1.5 V and
±15 V.
7.3.2 Gain Bandwidth Product
Gain bandwidth product is found by multiplying a measured bandwidth of the amplifier by the gain at which that
bandwidth was measured. The TS321 has a gain bandwidth of 0.8 MHz.
7.3.3 Slew Rate
The slew rate is the rate at which an operational amplifier can change the output when there is a change on the
input. The TS321 has a 0.4-V/μs slew rate.
l TEXAS INSTRUMENTS
100 pF 100 nF
1 nF
1 µF
10 µF
10 nF
9
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Feature Description (continued)
7.3.4 Input Common-Mode Range
The valid common-mode range is from device ground pin to VCC – 1.5 V (VCC – 2 V across temperature).
Inputs may exceed VCC up to the maximum VCC without device damage. At least one input must be in the valid
input common-mode range for output to be correct phase. If both inputs exceed valid range then output phase is
undefined. If either input is less than –0.3 V then input current must be limited to 1 mA and output phase is
undefined.
7.3.5 Stability With High Capacitive Loads
Operational amplifiers have reduced phase margin when there is a direct capacitance on the output. The stability
is affected most when the amplifier is set to unity gain. Small signal response to a step input of 100 mV reveals
the loop stability with a range of capacitors. See SLVA381 to correlate response waveform to phase margin. The
responses at 1 nF or less indicate acceptable phase margin. The responses at 1 uF and above indicate good
phase margin.
Figure 7. Small-Signal Response
7.4 Device Functional Modes
The TS321 is powered on when the supply is connected. This device can operate as a single-supply operational
amplifier or dual-supply amplifier depending on the application.
l TEXAS INSTRUMENTS
VRF
ARI
V1.8
A 3.6
0.5
VVOUT
AVIN
Vsup+
+VOUT
RF
VIN
RI
Vsup-
10
TS321
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8 Application and Implementation
NOTE
Information in the following applications sections is not part of the TI component
specification, and TI does not warrant its accuracy or completeness. TI’s customers are
responsible for determining suitability of components for their purposes. Customers should
validate and test their design implementation to confirm system functionality.
8.1 Application Information
The TS321 operational amplifier is useful in a wide range of signal conditioning applications. Inputs can be
powered before VCC for flexibility in multiple supply circuits.
8.2 Typical Application
A typical application for an operational amplifier in an inverting amplifier. This amplifier takes a positive voltage
on the input, and makes the voltage a negative voltage of the same magnitude. In the same manner, the
amplifier makes negative voltages positive.
Figure 8. Typical Application Schematic
8.2.1 Design Requirements
The supply voltage must be selected such that the supply voltage is larger than the input voltage range and
output range. For instance, this application scales a signal of ±0.5 V to ±1.8 V. Setting the supply at ±12 V is
sufficient to accommodate this application.
8.2.2 Detailed Design Procedure
Determine the gain required by the inverting amplifier:
(1)
(2)
Once the desired gain is determined, select a value for RI or RF. Selecting a value in the kilohm range is
desirable because the amplifier circuit uses currents in the milliamp range. This ensures the part does not draw
too much current. This example selects 10 kΩfor RI which means 36 kΩis be used for RF. This is determined
by Equation 3.
(3)
l TEXAS INSTRUMENTS Volts
-2
-1.5
-1
-0.5
0
0.5
1
1.5
2
0 0.5 1 1.5 2
Volts
Time (ms)
VIN
VOUT
11
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Typical Application (continued)
8.2.3 Application Curve
Figure 9. Input and Output Voltages of the Inverting Amplifier
l TEXAS INSTRUMENTS V
+
RIN
RG RF
VOUT
VIN
12
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9 Power Supply Recommendations
The TS321 is specified to operate between 3 V and 30 V or a dual supply between ±1.5 V and ±15 V.
CAUTION
Supply voltages larger than 32 V for a single supply, or outside the range of ±16 V for
a dual supply can permanently damage the device (see the Absolute Maximum
Ratings ).
Place 0.1-μF bypass capacitors close to the power-supply pins to reduce errors coupling in from noisy or high
impedance power supplies. For more detailed information on bypass capacitor placement, see the Layout
section.
10 Layout
10.1 Layout Guidelines
For best operational performance of the device, use good PCB layout practices, including:
• Noise can propagate into analog circuitry through the power pins of the circuit as a whole, as well as the
operational amplifier. Bypass capacitors are used to reduce the coupled noise by providing low impedance
power sources local to the analog circuitry.
– Connect low-ESR, 0.1-μF ceramic bypass capacitors between each supply pin and ground, placed as
close to the device as possible. A single bypass capacitor from V+ to ground is applicable for single
supply applications.
• Separate grounding for analog and digital portions of circuitry is one of the simplest and most-effective
methods of noise suppression. One or more layers on multilayer PCBs are usually devoted to ground planes.
A ground plane helps distribute heat and reduces EMI noise pickup. Make sure to physically separate digital
and analog grounds, paying attention to the flow of the ground current. For more detailed information, see
SLOA089.
• To reduce parasitic coupling, run the input traces as far away from the supply or output traces as possible. If
it is not possible to keep them separate, it is much better to cross the sensitive trace perpendicular as
opposed to in parallel with the noisy trace.
• Place the external components as close to the device as possible. Keeping RF and RG close to the inverting
input minimizes parasitic capacitance, as shown in Layout Example.
• Keep the length of input traces as short as possible. Always remember that the input traces are the most
sensitive part of the circuit.
• Consider a driven, low-impedance guard ring around the critical traces. A guard ring can significantly reduce
leakage currents from nearby traces that are at different potentials.
10.2 Layout Example
Figure 10. Operational Amplifier Schematic for Noninverting Configuration
‘5‘ TEXAS INSTRUMENTS
NC
VCC+
IN1í
IN1+
VCCí
NC
OUT
NC
RG
RIN
RF
GND
VIN
VS-GND
VS+
GND
Run the input traces as far
away from the supply lines
as possible
Only needed for
dual-supply
operation
Place components close to
device and to each other to
reduce parasitic errors
Use low-ESR, ceramic
bypass capacitor
(or GND for single supply) Ground (GND) plane on another layerVOUT
13
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Layout Example (continued)
Figure 11. Operational Amplifier Board Layout for Noninverting Configuration
l TEXAS INSTRUMENTS
14
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11 Device and Documentation Support
11.1 Documentation Support
11.1.1 Related Documentation
For more information, see the following:
•Simplifying Stability Checks
•Circuit Board Layout Techniques
11.2 Trademarks
All trademarks are the property of their respective owners.
11.3 Electrostatic Discharge Caution
These devices have limited built-in ESD protection. The leads should be shorted together or the device placed in conductive foam
during storage or handling to prevent electrostatic damage to the MOS gates.
11.4 Glossary
SLYZ022 —TI Glossary.
This glossary lists and explains terms, acronyms, and definitions.
I TEXAS INSTRUMENTS Samples Samples Sample: Sample: Samples Samples
PACKAGE OPTION ADDENDUM
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Addendum-Page 1
PACKAGING INFORMATION
Orderable Device Status
(1)
Package Type Package
Drawing Pins Package
Qty Eco Plan
(2)
Lead finish/
Ball material
(6)
MSL Peak Temp
(3)
Op Temp (°C) Device Marking
(4/5)
Samples
TS321ID ACTIVE SOIC D 8 75 RoHS & Green NIPDAU Level-1-260C-UNLIM -40 to 125 SR321I
TS321IDBVR ACTIVE SOT-23 DBV 5 3000 RoHS & Green NIPDAU | SN Level-1-260C-UNLIM -40 to 125 (9C1G, 9C1S)
TS321IDBVRE4 ACTIVE SOT-23 DBV 5 3000 RoHS & Green NIPDAU Level-1-260C-UNLIM -40 to 125 9C1G
TS321IDBVRG4 ACTIVE SOT-23 DBV 5 3000 RoHS & Green NIPDAU Level-1-260C-UNLIM -40 to 125 9C1G
TS321IDBVT ACTIVE SOT-23 DBV 5 250 RoHS & Green NIPDAU | SN Level-1-260C-UNLIM -40 to 125 (9C1G, 9C1S)
TS321IDR ACTIVE SOIC D 8 2500 RoHS & Green NIPDAU Level-1-260C-UNLIM -40 to 125 SR321I
(1) The marketing status values are defined as follows:
ACTIVE: Product device recommended for new designs.
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design.
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.
OBSOLETE: TI has discontinued the production of the device.
(2) RoHS: TI defines "RoHS" to mean semiconductor products that are compliant with the current EU RoHS requirements for all 10 RoHS substances, including the requirement that RoHS substance
do not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, "RoHS" products are suitable for use in specified lead-free processes. TI may
reference these types of products as "Pb-Free".
RoHS Exempt: TI defines "RoHS Exempt" to mean products that contain lead but are compliant with EU RoHS pursuant to a specific EU RoHS exemption.
Green: TI defines "Green" to mean the content of Chlorine (Cl) and Bromine (Br) based flame retardants meet JS709B low halogen requirements of <=1000ppm threshold. Antimony trioxide based
flame retardants must also meet the <=1000ppm threshold requirement.
(3) MSL, Peak Temp. - The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature.
(4) There may be additional marking, which relates to the logo, the lot trace code information, or the environmental category on the device.
(5) Multiple Device Markings will be inside parentheses. Only one Device Marking contained in parentheses and separated by a "~" will appear on a device. If a line is indented then it is a continuation
of the previous line and the two combined represent the entire Device Marking for that device.
(6) Lead finish/Ball material - Orderable Devices may have multiple material finish options. Finish options are separated by a vertical ruled line. Lead finish/Ball material values may wrap to two
lines if the finish value exceeds the maximum column width.
I TEXAS INSTRUMENTS
PACKAGE OPTION ADDENDUM
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Addendum-Page 2
Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information
provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and
continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals.
TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited information may not be available for release.
In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI to Customer on an annual basis.
OTHER QUALIFIED VERSIONS OF TS321 :
•Automotive: TS321-Q1
NOTE: Qualified Version Definitions:
•Automotive - Q100 devices qualified for high-reliability automotive applications targeting zero defects
l TEXAS INSTRUMENTS REEL DIMENSIONS TAPE DIMENSIONS 7 “K0 '«Pt» Reel Dlameter AD Dimension designed to accommodate the component Width ED Dimension designed to accommodate the component iengtn K0 Dimension designed to accommodate the component Ihlckness 7 W OveraH wtdlh loe Gamer tape i P1 Pitch between successive cavtty centers f T Reel Width (W1) QUADRANT ASSIGNMENTS FOR PIN 1 ORIENTATION IN TAPE O O O D O O D D SprocketHotes ,,,,,,,,,,, ‘ User Direcllon 0' Feed Pockel Quadrants
TAPE AND REEL INFORMATION
*All dimensions are nominal
Device Package
Type Package
Drawing Pins SPQ Reel
Diameter
(mm)
Reel
Width
W1 (mm)
A0
(mm) B0
(mm) K0
(mm) P1
(mm) W
(mm) Pin1
Quadrant
TS321IDBVR SOT-23 DBV 5 3000 178.0 9.0 3.23 3.17 1.37 4.0 8.0 Q3
TS321IDBVR SOT-23 DBV 5 3000 180.0 8.4 3.23 3.17 1.37 4.0 8.0 Q3
TS321IDBVRG4 SOT-23 DBV 5 3000 178.0 9.0 3.23 3.17 1.37 4.0 8.0 Q3
TS321IDBVT SOT-23 DBV 5 250 180.0 8.4 3.23 3.17 1.37 4.0 8.0 Q3
TS321IDBVT SOT-23 DBV 5 250 178.0 9.0 3.23 3.17 1.37 4.0 8.0 Q3
TS321IDR SOIC D 8 2500 330.0 12.4 6.4 5.2 2.1 8.0 12.0 Q1
PACKAGE MATERIALS INFORMATION
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Pack Materials-Page 1
l TEXAS INSTRUMENTS TAPE AND REEL BOX DIMENSIONS
*All dimensions are nominal
Device Package Type Package Drawing Pins SPQ Length (mm) Width (mm) Height (mm)
TS321IDBVR SOT-23 DBV 5 3000 180.0 180.0 18.0
TS321IDBVR SOT-23 DBV 5 3000 202.0 201.0 28.0
TS321IDBVRG4 SOT-23 DBV 5 3000 180.0 180.0 18.0
TS321IDBVT SOT-23 DBV 5 250 202.0 201.0 28.0
TS321IDBVT SOT-23 DBV 5 250 180.0 180.0 18.0
TS321IDR SOIC D 8 2500 340.5 336.1 25.0
PACKAGE MATERIALS INFORMATION
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Pack Materials-Page 2
l TEXAS INSTRUMENTS T - Tube height| L - Tube length l ,g + w-Tuhe _______________ _ ______________ width 47 — B - Alignment groove width
TUBE
*All dimensions are nominal
Device Package Name Package Type Pins SPQ L (mm) W (mm) T (µm) B (mm)
TS321ID D SOIC 8 75 507 8 3940 4.32
PACKAGE MATERIALS INFORMATION
www.ti.com 5-Jan-2022
Pack Materials-Page 3
www.ti.com
PACKAGE OUTLINE
C
0.22
0.08 TYP
0.25
3.0
2.6
2X 0.95
1.9
1.45
0.90
0.15
0.00 TYP
5X 0.5
0.3
0.6
0.3 TYP
8
0 TYP
1.9
A
3.05
2.75
B
1.75
1.45
(1.1)
SOT-23 - 1.45 mm max heightDBV0005A
SMALL OUTLINE TRANSISTOR
4214839/F 06/2021
NOTES:
1. All linear dimensions are in millimeters. Any dimensions in parenthesis are for reference only. Dimensioning and tolerancing
per ASME Y14.5M.
2. This drawing is subject to change without notice.
3. Refernce JEDEC MO-178.
4. Body dimensions do not include mold flash, protrusions, or gate burrs. Mold flash, protrusions, or gate burrs shall not
exceed 0.25 mm per side.
0.2 C A B
1
34
5
2
INDEX AREA
PIN 1
GAGE PLANE
SEATING PLANE
0.1 C
SCALE 4.000
www.ti.com
EXAMPLE BOARD LAYOUT
0.07 MAX
ARROUND 0.07 MIN
ARROUND
5X (1.1)
5X (0.6)
(2.6)
(1.9)
2X (0.95)
(R0.05) TYP
4214839/F 06/2021
SOT-23 - 1.45 mm max heightDBV0005A
SMALL OUTLINE TRANSISTOR
NOTES: (continued)
5. Publication IPC-7351 may have alternate designs.
6. Solder mask tolerances between and around signal pads can vary based on board fabrication site.
SYMM
LAND PATTERN EXAMPLE
EXPOSED METAL SHOWN
SCALE:15X
PKG
1
34
5
2
SOLDER MASK
OPENING
METAL UNDER
SOLDER MASK
SOLDER MASK
DEFINED
EXPOSED METAL
METAL
SOLDER MASK
OPENING
NON SOLDER MASK
DEFINED
(PREFERRED)
SOLDER MASK DETAILS
EXPOSED METAL
www.ti.com
EXAMPLE STENCIL DESIGN
(2.6)
(1.9)
2X(0.95)
5X (1.1)
5X (0.6)
(R0.05) TYP
SOT-23 - 1.45 mm max heightDBV0005A
SMALL OUTLINE TRANSISTOR
4214839/F 06/2021
NOTES: (continued)
7. Laser cutting apertures with trapezoidal walls and rounded corners may offer better paste release. IPC-7525 may have alternate
design recommendations.
8. Board assembly site may have different recommendations for stencil design.
SOLDER PASTE EXAMPLE
BASED ON 0.125 mm THICK STENCIL
SCALE:15X
SYMM
PKG
1
34
5
2
‘J
www.ti.com
PACKAGE OUTLINE
C
.228-.244 TYP
[5.80-6.19]
.069 MAX
[1.75]
6X .050
[1.27]
8X .012-.020
[0.31-0.51]
2X
.150
[3.81]
.005-.010 TYP
[0.13-0.25]
0 - 8 .004-.010
[0.11-0.25]
.010
[0.25]
.016-.050
[0.41-1.27]
4X (0 -15 )
A
.189-.197
[4.81-5.00]
NOTE 3
B .150-.157
[3.81-3.98]
NOTE 4
4X (0 -15 )
(.041)
[1.04]
SOIC - 1.75 mm max heightD0008A
SMALL OUTLINE INTEGRATED CIRCUIT
4214825/C 02/2019
NOTES:
1. Linear dimensions are in inches [millimeters]. Dimensions in parenthesis are for reference only. Controlling dimensions are in inches.
Dimensioning and tolerancing per ASME Y14.5M.
2. This drawing is subject to change without notice.
3. This dimension does not include mold flash, protrusions, or gate burrs. Mold flash, protrusions, or gate burrs shall not
exceed .006 [0.15] per side.
4. This dimension does not include interlead flash.
5. Reference JEDEC registration MS-012, variation AA.
18
.010 [0.25] C A B
5
4
PIN 1 ID AREA
SEATING PLANE
.004 [0.1] C
SEE DETAIL A
DETAIL A
TYPICAL
SCALE 2.800
Yl“‘+
www.ti.com
EXAMPLE BOARD LAYOUT
.0028 MAX
[0.07]
ALL AROUND
.0028 MIN
[0.07]
ALL AROUND
(.213)
[5.4]
6X (.050 )
[1.27]
8X (.061 )
[1.55]
8X (.024)
[0.6]
(R.002 ) TYP
[0.05]
SOIC - 1.75 mm max heightD0008A
SMALL OUTLINE INTEGRATED CIRCUIT
4214825/C 02/2019
NOTES: (continued)
6. Publication IPC-7351 may have alternate designs.
7. Solder mask tolerances between and around signal pads can vary based on board fabrication site.
METAL SOLDER MASK
OPENING
NON SOLDER MASK
DEFINED
SOLDER MASK DETAILS
EXPOSED
METAL
OPENING
SOLDER MASK METAL UNDER
SOLDER MASK
SOLDER MASK
DEFINED
EXPOSED
METAL
LAND PATTERN EXAMPLE
EXPOSED METAL SHOWN
SCALE:8X
SYMM
1
45
8
SEE
DETAILS
SYMM
www.ti.com
EXAMPLE STENCIL DESIGN
8X (.061 )
[1.55]
8X (.024)
[0.6]
6X (.050 )
[1.27] (.213)
[5.4]
(R.002 ) TYP
[0.05]
SOIC - 1.75 mm max heightD0008A
SMALL OUTLINE INTEGRATED CIRCUIT
4214825/C 02/2019
NOTES: (continued)
8. Laser cutting apertures with trapezoidal walls and rounded corners may offer better paste release. IPC-7525 may have alternate
design recommendations.
9. Board assembly site may have different recommendations for stencil design.
SOLDER PASTE EXAMPLE
BASED ON .005 INCH [0.125 MM] THICK STENCIL
SCALE:8X
SYMM
SYMM
1
45
8
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