Datenblatt für TPS65903x-Q1 Datsheet von Texas Instruments

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An IMPORTANT NOTICE at the end of this data sheet addresses availability, warranty, changes, use in safety-critical applications,
intellectual property matters and other important disclaimers. PRODUCTION DATA.
TPS659038-Q1, TPS659039-Q1
SWCS095L –AUGUST 2013–REVISED FEBRUARY 2019
TPS65903x-Q1 Automotive Power Management Unit (PMU) for Processor
1 Device Summary
1
1.1 Features
1
• Qualified for Automotive Applications
– AEC-Q100 Qualified With the Following Results:
– Temperature Grade 3: –40°C to 85°C
– ESD Classification:
– HBM Level 2
– CDM Level C3
– Latch-Up Classification:
– Level IIB for I2C and SPI Terminals
– Level IIA for all other Terminals
• Seven Step-Down Switched-Mode Power Supply
(SMPS) Regulators:
– One 0.7 to 1.65 V at 6 A (10-mV Steps)
– Dual-Phase Configuration With Digital
Voltage Scaling (DVS) Control
– One 0.7 to 1.65 V at 4 A (10-mV Steps)
– Dual-Phase Configuration With DVS Control
– One 0.7 to 3.3 V at 3 A (10 or 20-mV Steps)
– Single-Phase Configuration
– This Regulator can be Combined With the 6
A Resulting in a 9 A Triple-Phase Regulator
(DVS Controlled)
– Two 0.7 to 3.3 V at 2 A (10 or 20-mV Steps)
– Single-Phase Configuration
– One Regulator With DVS Control, Which can
also be Configured as a 3-A Regulator
– Two 0.7 to 3.3 V at 1 A (10 or 20-mV Steps)
– Single-Phase Configuration
– One Regulator With DVS Control
– Output Current Measurement in All Except 1-A
SMPS Regulators
– Differential Remote Sensing (Output and
Ground) in Dual-Phase and Triple-Phase
Regulators
– Hardware and Software-Controlled ECO-
mode™ up to 5 mA with 15-µA Quiescent
Current
– Short-Circuit Protection
– Powergood Indication (Voltage and Overcurrent
Indication)
– Internal Soft-Start for In-Rush Current Limitation
– Ability to synchronize SMPS to External Clock
or Internal Fallback Clock With Phase
Synchronization
• Eleven General-Purpose Low Dropout (LDO)
Regulators (50-mV Steps):
– Four 0.9 to 3.3 V at 300 mA With Preregulated
Supply
– Four 0.9 to 3.3 V at 200 mA With Preregulated
Supply
– One 0.9 to 3.3 V at 50 mA With Preregulated
Supply
– One 100-mA USB LDO
– One Low-Noise LDO 0.9 to 3.3 V up to 100 mA
(Low Noise Performance up to 50 mA)
– Two Additional LDOs for PMU Internal Use
– Short-Circuit Protection
• Clock Management 16-MHz Crystal Oscillator and
32-kHz RC Oscillator
– One Buffered 32-kHz Output
• Real-Time Clock (RTC) With Alarm Wake-Up
Mechanism
• 12-bit Sigma-Delta General-Purpose Analog-to-
Digital-Converter (GPADC) With Three External
Input Channels and Six Internal Channels for Self
Monitoring
• Thermal Monitoring
– High Temperature Warning
– Thermal Shutdown
• Control
– Configurable Power-Up and Power-Down
Sequences (One-Time Programmable [OTP])
– Configurable Sequences Between the SLEEP
and ACTIVE States (OTP Programmable)
– One Dedicated Digital Output Signal (REGEN)
that can be Included in the Start-up Sequence
– Three Digital Output Signals MUXed With GPIO
that can be Included in the Start-up Sequence
– Selectable Control Interface
– One Serial Peripheral Interface (SPI) for
Resource Configurations and DVS Control
– Two I2C Interfaces. One Dedicated for DVS
Control, and a General Purpose I2C Interface
for Resource Configuration and DVS Control
• Undervoltage Lockout
• System Voltage Range from 3.135 to 5.25 V
• Package Options
– 12-mm × 12-mm 169-pin nFBGA with 0,8-mm
Ball Pitch
l TEXAS INSTRUMENTS
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TPS659038-Q1, TPS659039-Q1
SWCS095L –AUGUST 2013–REVISED FEBRUARY 2019
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Device Summary Copyright © 2013–2019, Texas Instruments Incorporated
1.2 Applications
• Automotive Infotainment
• Automotive Digital Cluster
• Automotive Sensor Fusion
• Programmable Logic Controller
(1) For all available packages, see the orderable addendum at the end of the datasheet.
1.3 Description
The TPS659038-Q1 and TPS659039-Q1 devices are integrated power-management integrated circuits
(PMICs) for automotive applications. The device provides seven configurable step-down converters with
up to 6 A of output current for memory, processor core, input-output (I/O), or preregulation of LDOs. One
of these configurable step-down converters can be combined with another 3-A regulator to allow up to 9 A
of output current. All of the step-down converters can synchronize to an external clock source between 1.7
Mhz and 2.7 MHz, or an internal fall back clock at 2.2 MHz. The TPS659038-Q1 device contains 11 LDO
regulators while the TPS659039-Q1 device contains six LDO regulators for external use. These LDO
regulators can be supplied from either a system supply or a preregulated supply. The power-up and
power-down controller is configurable and supports any power-up and power-down sequences (OTP
based). The TPS659038-Q1 and TPS659039-Q1 devices include a 32-kHz RC oscillator to sequence all
resources during power up and power down. In cases where a fast start up is needed, a 16-MHz crystal
oscillator is also included to quickly generate a stable 32-kHz for the system. All LDOs and SMPS
converters can be controlled by the SPI or I2C interface, or by power request signals. In addition, voltage
scaling registers allow transitioning the SMPS to different voltages by SPI, I2C, or roof and floor control.
One dedicated pin in each package can be configured as part of the power-up sequence to control
external resources. General-purpose input-output (GPIO) functionality is available and two GPIOs can be
configured as part of the power-up sequence to control external resources. Power request signals enable
power mode control for power optimization. The device includes a general-purpose (GP) sigma-delta
analog-to-digital converter (ADC) with three external input channels. The TPS659038-Q1 and TPS659039-
Q1 device is available in a 13-ball × 13-ball nFBGA package with a 0,8-mm pitch.
Device Information(1)
PART NUMBER PACKAGE BODY SIZE (NOM)
TPS659038-Q1 ZWS (169) 12.00 mm × 12.00 mm
TPS659039-Q1
l TEXAS INSTRUMENTS
16-MHz XTAL
Reference and Bias
8x GPIO
Programmable Power
Sequencer Controller
ECO
PWM
DVS
Switch On or OFF
Watchdog
Thermal Monitoring
and Shutdown
2x I2C or 1x SPI
PLL for external
SyncClk
SMPS12
0.7 to 1.6 V,
10-mV step, 6 A
SMPS3
0.7 to 1.6 V,
10-mV step
1 to 3.3 V,
20-mV step, 3 A
Dual Phase or
Triple Phase
SMPS6
0.7 to 1.6 V,
10-mV step
1 to 3.3 V,
20-mV step, 2 or 3 A
SMPS8
0.7 to 1.6 V,
10-mV step
1 to 3.3-V,
20-mV step, 1 A
SMPS9
0.7 to 1.6 V,
10-mV step
1 to 3.3 V,
20-mV step, 1 A
SMPS45
0.7 to 1.6 V,
10-mV step, 4 A
SMPS7
0.7 to 1.6 V,
10-mV step
1 to 3.3 V,
20-mV step, 2 A
Dual Phase or
Triple Phase
LDO1
300 mA
LDO2
300 mA
LDO3
300 mA
LDO9
50 mA
LDOLN
50 mA
LDOUSB
100 mA
LDOVRTC
25 mA
OTP Controller
OTP Registers
Registers
Power Good Monitor
LDO5
200 mA
LDO6
200 mA
LDO7
200 mA
LDO8
170 mA
LDO4
300 mA
TPS659038-Q1 Only
RTC
12-Bit GPADC
with 3 External
Channels
VSYS Monitor
TPS659038-Q1
TPS659039-Q1
Copyright © 2017, Texas Instruments Incorporated
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Device SummaryCopyright © 2013–2019, Texas Instruments Incorporated
1.4 Simplified Block Diagram
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Revision History Copyright © 2013–2019, Texas Instruments Incorporated
Table of Contents
1 Device Summary......................................... 1
1.1 Features .............................................. 1
1.2 Applications........................................... 2
1.3 Description............................................ 2
1.4 Simplified Block Diagram............................. 3
2 Revision History ......................................... 4
3 Device Comparison ..................................... 8
4 Pin Configuration and Functions..................... 9
4.1 Pin Functions ......................................... 9
4.2 Device Ball Mapping – 13 × 13 nFBGA, 169 Balls,
0,8-mm Pitch ........................................ 14
4.3 Signal Descriptions.................................. 16
5 Specifications........................................... 18
5.1 Absolute Maximum Ratings......................... 18
5.2 ESD Ratings ........................................ 18
5.3 Recommended Operating Conditions............... 19
5.4 Thermal Information................................. 19
5.5 Electrical Characteristics: Latch Up Rating ......... 19
5.6 Electrical Characteristics: LDO Regulator .......... 20
5.7 Electrical Characteristics: Dual-Phase (SMPS12
and SMPS45) and Triple-Phase (SMPS123 and
SMPS457) Regulators .............................. 22
5.8 Electrical Characteristics: Stand-Alone Regulators
(SMPS3, SMPS6, SMPS7, SMPS8, and SMPS9).. 23
5.9 Electrical Characteristics: Reference Generator
(Bandgap) ........................................... 25
5.10 Electrical Characteristics: 16-MHz Crystal Oscillator,
32-kHz RC Oscillator, and Output Buffers .......... 25
5.11 Electrical Characteristics: DC-DC Clock Sync ...... 26
5.12 Electrical Characteristics: 12-Bit Sigma-Delta ADC.26
5.13 Electrical Characteristics: Thermal Monitoring and
Shutdown............................................ 28
5.14 Electrical Characteristics: System Control
Thresholds .......................................... 28
5.15 Electrical Characteristics: Current Consumption.... 28
5.16 Electrical Characteristics: Digital Input Signal
Parameters .......................................... 29
5.17 Electrical Characteristics: Digital Output Signal
Parameters .......................................... 29
5.18 Electrical Characteristics: I/O Pullup and Pulldown
Resistance .......................................... 31
5.19 I2C Interface Timing Requirements ................. 32
5.20 SPI Timing Requirements........................... 33
5.21 Typical Characteristics .............................. 35
6 Detailed Description ................................... 37
6.1 Overview ............................................ 37
6.2 Functional Block Diagrams.......................... 38
6.3 Feature Description ................................. 39
6.4 Device Functional Modes ........................... 66
7 Application and Implementation .................... 83
7.1 Application Information.............................. 83
7.2 Typical Application .................................. 83
8 Power Supply Recommendations .................. 94
9 Layout .................................................... 94
9.1 Layout Guidelines ................................... 94
9.2 Layout Example ..................................... 98
10 Device and Documentation Support.............. 101
10.1 Device Support..................................... 101
10.2 Documentation Support............................ 101
10.3 Related Links ...................................... 101
10.4 Receiving Notification of Documentation Updates.102
10.5 Community Resources............................. 102
10.6 Trademarks ........................................ 102
10.7 Electrostatic Discharge Caution ................... 102
10.8 Glossary............................................ 102
11 Mechanical, Packaging, and Orderable
Information............................................. 102
11.1 Package Materials Information..................... 102
2 Revision History
NOTE: Page numbers for previous revisions may differ from page numbers in the current version.
Changes from Revision K (January 2018) to Revision L Page
• Changed ESD classification from C4B to C3 .................................................................................... 1
• Updated the LDOVRTC_OUT pulldown resistor recommendation to only include applicable silicon revisions. ....... 11
• Changed ESD Ratings for charge device model on 6 pins ................................................................... 18
• Clarified that LDO1 and LDO2 input pins are not included in this minimum recommended operating voltage. See
Electrical Characteristics: LDO Regulators for more information. ............................................................ 19
• Changed minimum recommended operating condition of OSC16MIN from 0V to -0.7V ................................. 19
• Added LDO and SMPS output capacitance footnote .......................................................................... 20
• Changed VSYS_LO hysteresis from 95mV to 75mV........................................................................... 28
• Updated Caution statement to only include applicable silicon revisions. ................................................... 37
• Changed discharge resistance to match electrical characteristics table .................................................... 40
• Added information about shutdown timing during short circuit detection ................................................... 43
• Updated POWERGOOD description to clarify multi-phase operation. ...................................................... 43
• Updated LDOVRTC note to only include applicable silicon revisions. ....................................................... 48
• Added details on identifying device version...................................................................................... 66
l TEXAS INSTRUMENTS a: a? :5 E5 ‘ m .5 .5 3 m b M 2 u u M 9 1 on \I-‘w W“ _. \.
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Revision HistoryCopyright © 2013–2019, Texas Instruments Incorporated
• Added typical debounce time from POWERHOLD to the enable of the first rail in the power sequence. .............. 69
• Added VSYS_LO note for applicable silicon revisions. ........................................................................ 79
• Updated POR requirements to only include applicable silicon revisions. ................................................... 81
• SMPS and LDO output capacitance specification further explained ......................................................... 88
• Added design considerations for VCC1 capacitance to support loss of power ............................................. 88
• Corrected 9-Vpp with 7V absolute maximum specification in the Layout Guidelines section............................. 94
• Updated requirements relating to measurement of high-side and low-side FETs in the Layout Guidelines section... 96
• Updated images and description on differential measurements across high-side and low-side FETs .................. 97
Changes from Revision J (March 2017) to Revision K Page
• Removed pullup and pulldown from BOOT0 pin description .................................................................. 16
• Deleted the nominal Tstg value (27°C) from the Absolute Maximum Ratings table......................................... 18
• Deleted the voltage mode to the I/O digital supply voltage, VIO_IN parameter from the Recommended
Operating Conditions table......................................................................................................... 19
• Deleted the voltage on the VCC1 GPADC pins (TBC) parameter from the Recommended Operating Conditions
table................................................................................................................................... 19
• Added 2-A mode for SMPS6 in the test conditions for high-side and low-side MOSFET forward current limit and
low-side MOSFET negative current limit in the Electrical Characteristics: Stand-Alone Regulators (SMPS3,
SMPS6, SMPS7, SMPS8, and SMPS9) table................................................................................... 24
• Added the number of active SMPS phases (K) to the equation for the temperature compensated result in the
Current Monitoring and Short Circuit Detection section........................................................................ 43
• Added additional description of SMPS short detection and recovery behavior ............................................. 43
• Added equation to convert GPADC code to internal die temperature........................................................ 52
• Added description of VIO power-up timing, and updated start up timing diagram ......................................... 73
• Added additional description of VSYS_LO functionality........................................................................ 79
• Added link to application note about POR generation.......................................................................... 81
Changes from Revision I (June 2016) to Revision J Page
• First public release of data sheet .................................................................................................. 2
• Added recommendation for external pulldown resistor on the LDOVRTC_OUT pin in the Pin Functions table........ 11
• Changed the description of the LDOVRTC when in the BACKUP and OFF states and added a note in the
LDOVRTC section .................................................................................................................. 47
• Added the note and pulldown equations to the System Voltage Monitoring section....................................... 81
Changes from Revision H (October 2015) to Revision I Page
• Changed the typical value for the Channel 11 SMPS output current measurement gain factor parameter in the
12-Bit Sigma-Delta ADC table..................................................................................................... 27
• Changed the typical value for the channel 11 SMPS output current measurement current offset parameter in the
12-Bit Sigma-Delta ADC table..................................................................................................... 27
• Updated part numbers and settings for released devices in the Design Parameters table ............................... 86
Changes from Revision G (October 2015) to Revision H Page
• Added DC accuracy spec for LDO3 and LDO4 when IO= 300 mA, which is the new IOmax from the previous
revision ............................................................................................................................... 20
• Added VDROPOUT spec for LDO3 and LDO4 when IO= 300 mA, which is the new IOmax from the previous revision.. 20
• Added DC Load Regulation spec for LDO3 and LDO4 when IO= 300 mA, which is the new IOmax from the
previous revision .................................................................................................................... 21
• Updated PSRR spec for LDO3 and LDO4 when IO= 300 mA, which is the new IOmax from the previous revision .. 21
• Added DC Load Transient spec for LDO3 and LDO4 when IO= 300 mA, which is the new IOmax from the
previous revision .................................................................................................................... 21
• Updated the current capability of LDO3 and LDO4 from 200 mA to 300 mA throughout the specification ............ 39
l TEXAS INSTRUMENTS u m M" Kim; 5-? Ma W“ a N
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Revision History Copyright © 2013–2019, Texas Instruments Incorporated
Changes from Revision F (February 2015) to Revision G Page
• Updated the functional block diagram by removing the external connections and combining both 38/39 devices
in one diagram. ...................................................................................................................... 38
• Added caution statement for operating the GPADC in SW mode. ........................................................... 53
• Updated the component numbering in the Typical Applications Diagrams to align with EVM schematics and
Table 7-2 ............................................................................................................................ 85
• Added description of OSC16M_CFG OTP bit, and the required setting of this bit in relation to the presence of a
16-MHz crystal for proper device function........................................................................................ 91
Changes from Revision E (December 2014) to Revision F Page
• Changed the DVS-Capable Regulators section; the slew rate of the output voltage is fixed at 2.5 mV/µs............. 45
• Updated the Design Requirements section ..................................................................................... 86
• Changed the REFERENCE COMPONENT numbers in the Recommended External Components for Automotive
Usage table ......................................................................................................................... 87
• Deleted the Recommended External Components for Commercial Usage table from the Typical Application
section ............................................................................................................................... 87
• Changed the body size for CX8045GB16384H0HEQZ1 in the Recommended External Components for
Automotive Usage table ............................................................................................................ 87
• Deleted the GPADC EXTERNAL COMPONENTS from the Recommended External Components for Automotive
Usage table .......................................................................................................................... 87
Changes from Revision D (October 2014) to Revision E Page
• Added caution statement to the Specifications section ........................................................................ 18
• Added caution statement to the Specifications section ........................................................................ 37
Changes from Revision C (June 2014) to Revision D Page
• Deleted the export control notice from the data sheet .......................................................................... 2
• Removed all notions of (3.6V tolerance) from VRTC digital pins without fail-safe feature ................................ 17
• Changed Replaced LDOVRTCmax + 0.3 notion with actual value of 2.15 under the ABS Max Rating table for
VRTC digital input pins ............................................................................................................. 18
• Changed Replaced LDOVRTCmax notion with actual value of 1.85 under the ROC table for OSC16MIN and
VRTC digital input pins ............................................................................................................. 19
• Updated typical IQ(on) value of LDOUSB-IN1 from 30µA to 45µA in accordance with characterization data ......... 21
• Added Caution clause to describe the scenario which may cause unexpected shutdown of the PLL, and the
actions to recover from such fault condition. .................................................................................... 72
• Added comments for the ideal SMPS voltage-spike measurement condition under Layout Guidance section. ....... 96
Changes from Revision B (June 2014) to Revision C Page
• Updated Latch Up Current Class specification format and separated LDOVANA_OUT pin specification from all
other pins............................................................................................................................. 19
• Updated typical value of high-side FET rDS(on) from 50mΩto 115mΩfor all multi-phase SMPSs ....................... 22
• Updated typical value of low-side FET rDS(on) from 39mΩto 30mΩfor all multi-phase SMPSs .......................... 22
• Updated typical value of High-side FET rDS(on) from 50mΩto 115mΩfor all single-phase SMPSs except SMPS 8
& 9 .................................................................................................................................... 24
• Updated typical value of high-side FET rDS(on) from 110mΩto 180mΩfor SMPS8 & 9 ................................... 24
• Updated typical value of low-side FET rDS(on) from 39mΩto 30mΩfor all single-phase SMPSs except SMPS 8 &
9...................................................................................................................................... 24
• Updated the typical value of CLK32KGO output buffer rise and fall time based on characterization data. ............ 25
• Updated the min and max value of CLK32KGO1V8 output buffer rise and fall time based on simulation data. ...... 25
• Added comments on limitation of Vout/Vin ratio and Vin monitor and shut down mechanism when a SMPS
converter is in ECO mode.......................................................................................................... 40
l TEXAS INSTRUMENTS \ S :5 ‘ m m mbwmm Mu: (D‘On‘w ‘ on w KS \ :7 :5 on m 25 WW \ ‘ m on Wm \. g.
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Revision HistoryCopyright © 2013–2019, Texas Instruments Incorporated
Changes from Revision A (May 2014) to Revision B Page
• Corrected the default state of the NSLEEP pin to PPU under Pin Function table.......................................... 12
• Corrected the voltage range for the GPADC_IN0 and GPADC_IN1 pins under the Recommended Operating
Conditions table ..................................................................................................................... 19
• Reduced minimum output inductance to -30% of the recommended value of 1µH for SMPSs in multi-phase
configuration ......................................................................................................................... 22
• Reduced minimum output inductance to -30% of the recommended value of 1µH for SMPSs in single-phase
configuration ......................................................................................................................... 23
• Added device Current Consumption specification for Sleep Mode when VSYS = 5.25V ................................. 28
• Added paragraph with regards to the importance of VSYS being the first supply available to the device. ............ 39
• Added approximate power rail shut down time from a short detection....................................................... 43
• Added approximate wait time for the device to reach OFF state from No Supply state. .................................. 67
• Added a paragraph under the Application Information section to emphasize the importance of operating the
device under ROC, and encourage customers to consider thermal management, power sequencing and layout
strategy to maximize device performance........................................................................................ 83
Changes from Original (April 2014) to Revision A Page
• Added option to float the VPROG pin when it is configured as an input pin ............................................... 12
• Updated Output Type of I2C2_SDA_SDO pin to specify Push-pull type when the pin is configured in SPI mode .... 17
• Corrected the minimum voltage level for all SMPS-related input pins to match VSYS minimum input level in
Recommended Operating Conditions ........................................................................................... 19
• Moved Latch Up Current Classification table out of the Handling Ratings table............................................ 19
• Corrected editing error which added an invalid Ripple spec for LDO1 & LDO2 ............................................ 22
• Updated the maximum specification of device Current Consumption in OFF Mode from 30 µA to 45 µA ............. 28
• Updated the definition and test condition of the device Current Consumption in SLEEP mode from having only
SMPS6 and SMPS8 enabled to having only LDO2 and LDO9 enabled. Also updated the typical and maximum
specifications to associate with the new definition. ............................................................................. 28
• Added the specific description that SDO line defaults to high impedance when the pin is configured as SPI
mode. ................................................................................................................................ 64
• Corrected the recommended part number for the Crystal decoupling caps in automotive use case .................... 87
l TEXAS INSTRUMENTS
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Device Comparison Copyright © 2013–2019, Texas Instruments Incorporated
3 Device Comparison
POWER BREAKDOWN TPS659038-Q1 TPS659039-Q1
Total DC-DC converters 9 9
Total DC-DC converter rails 7 7
LDOs 11 6
Package 0,8-mm pitch 169ZWS
(12 × 12 mm) nFBGA 0,8-mm 169ZWS
(12 × 12 mm) nFBGA
i TEXAS INSTRUMENTS 0000000000000 0000000000000 0000000000000 0000000000000 0000000000000 0000000000 000000000 00000000 0000000 0000000 000000 000000 00000000 00000000 00000000 0000000 000000 00000 000 ) 0 0 0 0 0 0 1 2 A H 12
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Pin Configuration and FunctionsCopyright © 2013–2019, Texas Instruments Incorporated
4 Pin Configuration and Functions
Figure 4-1. 169-Pin ZWS Plastic Ball Grid Array (PBGA)
Bottom View
(1) The PU/PD column shows the pullup and pulldown resistors on the digital input lines. Pullup and pulldown resistors:
PU pullup
PD pulldown
PPU software-programmable pullup
PPD software-programmable pulldown
(2) '38 designates the TPS659038-Q1 and '39 designates TPS659039-Q1
4.1 Pin Functions
Pin Functions
PIN
I/O
FUNCTION
AVAILABILITY DESCRIPTION CONNECTION
IF NOT USED OR
NOT AVAILABLE PU/PD(1)
NAME NO. '38(2) '39(2)
REFERENCE
REFGND1 A4 — √ √ System reference ground Ground —
VBG B7 O √ √ Bandgap reference voltage N/A —
STEP-DOWN CONVERTERS (SMPSs)
SMPS1_GND
D10
—√ √ Power ground connection for SMPS1 Ground —E9
E10
SMPS1_IN
D11
I√ √ Power input for SMPS1 System supply —D12
D13
SMPS1_SW
E11
O√ √ Switch node of SMPS1; connect output inductor Floating —E12
E13
SMPS2_GND
F9
—√ √ Power ground connection for SMPS2 Ground —F10
G10
SMPS2_IN
G11
I√ √ Power input for SMPS2 System supply —G12
G13
SMPS2_SW
F11
O√ √ Switch node of SMPS2; connect output inductor Floating —F12
F13
SMPS1_2_FDBK B13 I √ √ Output voltage-sense (feedback) input for SMPS1 and SMPS2 Ground —
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Pin Configuration and Functions Copyright © 2013–2019, Texas Instruments Incorporated
Pin Functions (continued)
PIN
I/O
FUNCTION
AVAILABILITY DESCRIPTION CONNECTION
IF NOT USED OR
NOT AVAILABLE PU/PD(1)
NAME NO. '38(2) '39(2)
SMPS1_2_FDBK_GND C12 I √ √ Ground-sense (feedback) input for SMPS1 and SMPS2 Ground —
SMPS3_GND
H10
—√ √ Power ground connection for SMPS3 Ground —J9
J10
SMPS3_IN
H11
I√ √ Power input for SMPS3 System supply —H12
H13
SMPS3_SW
J11
O√ √ Switch node of SMPS3; connect output inductor Floating —J12
J13
SMPS3_FDBK K13 I √ √ Output voltage-sense (feedback) input for SMPS3 Floating —
SMPS4_GND
F4
—√ √ Power ground connection for SMPS4 Ground —G4
G5
SMPS4_IN
F1
I√ √ Power input for SMPS4 System supply —F2
F3
SMPS4_SW
G1
O√ √ Switch node of SMPS4; connect output inductor Floating —G2
G3
SMPS4_5_FDBK K2 I √ √ Output voltage-sense (feedback) input for SMPS4 and SMPS5 Ground —
SMPS4_5_FDBK_GND K3 I √ √ Ground-sense (feedback) input for SMPS4 and SMPS5 Ground —
SMPS5_GND
H4
—√ √ Power ground connection for SMPS5 Ground —H5
J4
SMPS5_IN
J1
I√ √ Power input for SMPS5 System supply —J2
J3
SMPS5_SW
H1
O√ √ Switch node of SMPS5; connect output inductor Floating —H2
H3
SMPS6_GND L5 —√ √ Power ground connection for SMPS6 Ground —
L6
SMPS6_IN M6 I√ √ Power input for SMPS6 System supply —
N6
SMPS6_SW M5 O√ √ Switch node of SMPS6 connect output inductor Floating —
N5
SMPS6_FDBK K6 I √ √ Output voltage sense (feedback) input for SMPS6 Ground —
SMPS7_GND
D4
—√ √ Power ground connection for SMPS7 Ground —D5
E4
SMPS7_IN
E1
I√ √ Power input for SMPS7 System supply —E2
E3
SMPS7_SW
D1
O√ √ Switch node of SMPS7; connect output inductor Floating —D2
D3
SMPS7_FDBK B1 I √ √ Output voltage-sense (feedback) input for SMPS7 Floating —
SMPS8_GND L9 —√ √ Power ground connection for SMPS8 Ground —
L10
SMPS8_IN M9 I√ √ Power input for SMPS8 System supply —
N9
SMPS8_SW M10 O√ √ Switch node of SMPS8 connect output inductor Floating —
N10
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Pin Functions (continued)
PIN
I/O
FUNCTION
AVAILABILITY DESCRIPTION CONNECTION
IF NOT USED OR
NOT AVAILABLE PU/PD(1)
NAME NO. '38(2) '39(2)
(3) Default option
SMPS8_FDBK L11 I √ √ Output voltage-sense (feedback) input for SMPS8 Ground —
SMPS9_GND L7 —√ √ Power ground connection for SMPS9 Ground —
L8
SMPS9_IN M8 I√ √ Power input for SMPS9 System supply —
N8
SMPS9_SW M7 O√ √ Switch node of SMPS9 connect output inductor Floating —
N7
SMPS9_FDBK J8 I √ √ Output voltage-sense (feedback) input for SMPS9 Ground —
LOW DROPOUT REGULATORS
LDO1_OUT C6 O √ √ LDO1 output voltage Floating —
LDO12_IN A6 I √ √ Power input voltage for LDO1 and LDO2 regulators System supply —
LDO2_OUT B6 O √ √ LDO2 output voltage Floating —
LDO3_OUT K11 O √ √ LDO3 output voltage Floating —
LDO34_IN L12 I√ √ Power input voltage for LDO3 and LDO4 regulators System supply —
L13
LDO4_OUT K12 O √LDO4 output voltage Floating —
LDO5_OUT K4 O √LDO5 output voltage Floating —
LDO58_IN M4 I√Power input voltage for LDO5 and LDO8 regulators System supply —
N4
LDO6_IN N3 I √Power input voltage for LDO6 regulator System supply —
LDO6_OUT L4 O √LDO6 output voltage Floating —
LDO7_LDOUSB_IN A10 I √ √ Power input voltage for LDO7 and LDOUSB (LDOUSB_IN1) regulators System supply —
LDO7_OUT C9 O √LDO7 output voltage Floating —
LDO8_OUT K5 O √LDO8 output voltage Floating —
LDO9_IN C4 I √ √ Power input voltage for LDO9 regulator System supply —
LDO9_OUT A5 O √ √ LDO9 output voltage Floating —
LDOUSB_IN2 A9 I √ √ Power input voltage 2 for LDOUSB regulator System supply —
LDOUSB_OUT B9 O √ √ LDOUSB output voltage Floating —
LOW NOISE DROPOUT REGULATORS
LDOLN_IN C5 I √ √ Power input voltage for LDOLN regulator System supply —
LDOLN_OUT B5 O √ √ LDOLN output voltage Floating —
LOW-DROPOUT REGULATORS (INTERNAL)
LDOVANA_OUT C8 O √ √ LDOVANA output voltage N/A —
LDOVRTC_OUT A8 O √ √ LDOVRTC output voltage. For silicon revisions 1.3 or earlier, rapid power off and on
requires a pulldown resistor on the LDOVRTC_OUT pin. See Section 6.4.11 for
more details. N/A —
SIGMA-DELTA GPADC
GPADC_IN0 B2 I √ √ GPADC input 0 Ground —
GPADC_IN1 C2 I √ √ GPADC input 1 Ground —
GPADC_IN2 C3 I √ √ GPADC input 2 Ground —
GPADC_VREF B4 O √ √ GPADC output reference voltage Floating —
CLOCKING
CLK32KGO M11 O √ √ 32-kHz digital-gated output clock available when VIO_IN input supply is present Floating —
OSC16MCAP C1 O √ √ Filtering capacitor for the 16-MHz crystal oscillator Floating —
OSC16MIN A3 I √ √ 16-MHz crystal oscillator input or digital clock input Floating or Ground in
Bypass Mode —
OSC16MOUT A2 O √ √ 16-MHz crystal oscillator output or floating in case of digital clock Floating —
SYNCDCDC B8 I √ √ Sync pin to sync DC-DCs with external clock Ground -
SYSTEM CONTROL
BOOT0 L3 I √ √ Boot ball 0 for power-up sequence selection Ground or VRTC —
BOOT1 K7 I √ √ Boot ball 1 for power-up sequence selection Ground or VRTC —
ENABLE1 J5 I √ √ Peripheral power request input 1 Floating PPU
PPD(3)
GPIO_0 B12 I/O √ √ General-purpose input(3) or output Ground or VSYS
(VCC1) PPD
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Pin Functions (continued)
PIN
I/O
FUNCTION
AVAILABILITY DESCRIPTION CONNECTION
IF NOT USED OR
NOT AVAILABLE PU/PD(1)
NAME NO. '38(2) '39(2)
GPIO_1 C13 I/O √ √ Primary function: General-purpose input(3) or output Floating PPU
PPD
O√ √ Secondary function: VBUSDET - VBUS detection Floating —
GPIO_2 A12 I/O √ √ General-purpose input(3) or output Floating PPU
PPD
O√ √ Secondary function: REGEN2 — External regulator enable output 2 Floating —
GPIO_3 H9 I √ √ General-purpose input(3) or output Ground PPD
GPIO_4 K10 I/O √ √ Primary function: General-purpose input(3) or output Floating PPU
PPD(3)
O√ √ Secondary function: SYSEN1 — External system enable Floating —
GPIO_5 C10
I/O √ √ Primary function: General-purpose input(3) or output Ground PPU
PPD(3)
O√ √ Secondary function: CLK32KGO1V8 — 32-kHz digital-gated output clock available
when VRTC is present Floating —
GPIO_6 N11 I/O √ √ Primary function: General-purpose input(3) or output Floating PPU
PPD(3)
O√ √ Secondary function: SYSEN2 — External system enable Floating —
GPIO_7 G9 I/O √ √ Primary function: General-purpose input(3) or output Ground or VRTC PPD
I√ √ Secondary function: POWERHOLD input Ground or VRTC PPD(3)
I2C1_SCL_SCK L1 I/O √ √ Control I2C serial clock (external pullup) and SPI clock signal Floating —
I2C1_SDA_SDI L2 I/O √ √ Control I2C serial bidirectional data (external pullup) and SPI data signal Floating —
I2C2_SDA_SDO H8 I/O √ √ DVS I2C serial bidirectional data (external pullup) and SPI data read signal or I2C
serial bidirectional data (external pullup) Floating —
I2C2_SCL_SCE M3 I/O √ √ DVS I2C serial clock (external pullup) and SPI enable signal or I2C serial clock
(external pullup) Floating —
INT K1 O √ √ Maskable interrupt output request to the host processor N/A —
NRESWARM E6 I √ √ Warm reset input Floating PPU(3)
NSLEEP E5 I √ √ NSLEEP request signal Floating PPU(3)
PPD
RPWRON C11 I √ √ External remote switch-on event Floating PU
PWRDOWN K8 I √ √ Power-down signal Floating PPD
PWRON G8 I √ √ External power-on event (on-button switch-on event) Floating PU
REGEN1 F8 O √ √ External regulator enable output 1 Floating —
RESET_IN K9 I √ √ Reset input Floating PPD
RESET_OUT G6 O √ √ System reset/power on output (Low—Reset, High—Active or Sleep) Floating —
POWER DETECTION
POWERGOOD J7 O √ √ Indication signal for valid regulator output voltages Floating —
VBUS D8 I √ √ VBUS Detection Voltage Ground —
VCC_SENSE B3 I √ √ System supply sense line System supply —
VCC_SENSE2 A11 I √ √ System supply sense line System supply —
PROGRAMMING, TESTING
VPROG N12 I√ √ Primary function: OTP programming voltage Ground or Floating —
O√ √ Secondary function: TESTV Floating —
POWER SUPPLIES
GND_ANA
A7
—√ √ Analog power ground Ground —
E7
F5
M13
GND_DIG M12 — √ √ Digital power ground Ground —
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Pin Functions (continued)
PIN
I/O
FUNCTION
AVAILABILITY DESCRIPTION CONNECTION
IF NOT USED OR
NOT AVAILABLE PU/PD(1)
NAME NO. '38(2) '39(2)
PBKG
A1
—√ √ Substrate ground Ground —
A13
B10
B11
D6
D7
E8
F6
F7
G7
H6
H7
J6
M1
M2
N1
N13
VCC1 C7 I √ √ Analog input voltage supply System supply —
VIO_GND N2 — √ √ Digital ground connection Ground —
VIO_IN D9 I √ √ Digital supply input for GPIOs and I/O supply voltage System supply —
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4.2 Device Ball Mapping – 13 × 13 nFBGA, 169 Balls, 0,8-mm Pitch
Figure 4-2 shows the nFBGA package ball mapping of the TPS659038-Q1 device and Figure 4-3 shows
the nFBGA package ball mapping of the TPS659039-Q1 device.
Figure 4-2. Top-View Ball Mapping for TPS659038-Q1 – nFBGA 13 × 13, 169 Balls, 0,8-mm Pitch
I TEXAS INSTRUMENTS
A B C D E F G H J K L M N
13
PBKG SMPS1_2_FDBK GPIO_1 SMPS1_IN SMPS1_SW SMPS2_SW SMPS2_IN SMPS3_IN SMPS3_SW SMPS3_FDBK LDO34_IN GND_ANA PBKG 13
12
GPIO_2 GPIO_0
SMPS1_2_FDBK_
GND
SMPS1_IN SMPS1_SW SMPS2_SW SMPS2_IN SMPS3_IN SMPS3_SW NC LDO34_IN GND_DIG VPROG 12
11
VCC_SENSE2 PBKG RPWRON SMPS1_IN SMPS1_SW SMPS2_SW SMPS2_IN SMPS3_IN SMPS3_SW LDO3_OUT SMPS8_FDBK CLK32KGO GPIO_6 11
10
LDOUSB_IN1 PBKG GPIO_5 SMPS1_GND SMPS1_GND SMPS2_GND SMPS2_GND SMPS3_GND SMPS3_GND GPIO_4 SMPS8_GND SMPS8_SW SMPS8_SW 10
9
LDOUSB_IN2 LDOUSB_OUT NC VIO_IN SMPS1_GND SMPS2_GND GPIO_7 GPIO_3 SMPS3_GND RSET_IN SMPS8_GND SMPS8_IN SMPS8_IN 9
8
LDOVRTC_OUT SYNCDCDC LDOVANA_OUT VBUS PBKG REGEN1 PWRON I2C2_SDA_SDO SMPS9_FDBK PWRDOWN SMPS9_GND SMPS9_IN SMPS9_IN 8
7
GND_ANA VBG VCC1 PBKG GND_ANA PBKG PBKG PBKG PWRGOOD BOOT1 SMPS9_GND SMPS9_SW SMPS9_SW 7
6
LDO12_IN LDO2_OUT LDO1_OUT PBKG NRESWARM PBKG RESET_OUT PBKG PBKG SMPS6_FDBK SMPS6_GND SMPS6_IN SMPS6_IN 6
5
LDO9_OUT LDOLN_OUT LDOLN_IN SMPS7_GND NSLEEP GND_ANA SMPS4_GND SMPS5_GND ENABLE1 NC SMPS6_GND SMPS6_SW SMPS6_SW 5
4
REFGND1 GPADC_VREF LDO9_IN SMPS7_GND SMPS7_GND SMPS4_GND SMPS4_GND SMPS5_GND SMPS5_GND NC NC LDO58_IN LDO58_IN 4
3
OSC16MIN VCC_SENSE GPADC_IN2 SMPS7_SW SMPS7_IN SMPS4_IN SMPS4_SW SMPS5_SW SMPS5_IN
SMPS4_5_FDBK_
GND
BOOT0 I2C2_SCL_SCE LDO6_IN 3
2
OSC16MOUT GPADC_IN0 GPADC_IN1 SMPS7_SW SMPS7_IN SMPS4_IN SMPS4_SW SMPS5_SW SMPS5_IN SMPS4_5_FDBK I2C1_SDA_SDI PBKG VIO_GND 2
1
PBKG SMPS7_FDBK OSC16MCAP SMPS7_SW SMPS7_IN SMPS4_IN SMPS4_SW SMPS5_SW SMPS5_IN INT I2C1_SCL_SCK PBKG PBKG 1
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Figure 4-3. Top-View Ball Mapping for TPS659039-Q1 – nFBGA 13 × 13, 169 Balls, 0,8-mm Pitch
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(1) Pullup and pulldown resistors: PU = Pullup, PD = Pulldown, PPU = Software-programmable pullup, PPD = Software-programmable pulldown.
(2) Default option.
4.3 Signal Descriptions
Table 4-1. Summary of Digital Signals and Some Dedicated Analog Signals
SIGNAL NAME POWER DOMAIN /
TOLERANCE LEVEL I/O INPUT PU/PD (1) OTP PU/PD SELECTION OUTPUT TYPE
SELECTION ACTIVE HI/LO OTP POLARITY
SELECTION
PWRON VSYS (VCC1) Input PU fixed N/A (fixed) N/A (input) Low No
RPWRON VSYS (VCC1) Input PU fixed N/A (fixed) N/A (input) Low No
PWRDOWN VRTC, fail-safe
(5.25-V tolerance) Input PPD(2) (Optional Ext.PU) Yes N/A (input) Low or high(2) Yes
POWERGOOD VRTC Output N/A (output) N/A (output) Open-drain Low or high(2) Yes
BOOT0 VRTC Input No No N/A (input) Boot conf. No
BOOT1 VRTC Tri-level input PPU/PPD(2) No N/A (input) Boot conf. No
GPIO_0 VRTC, fail-safe
(5.25-V tolerance) Input(2)/output PPD(2) Yes Open-drain Low or high No
GPIO_1
(primary function)
VSYS
Input(2)/output PPU/PPD(2) Yes Push-pull(2) or open- drain Low or high
No
GPIO_1
secondary function:
VBUSDET Output N/A (output) N/A (output) Push-pull(2) or open- drain High
GPIO_2
(primary function)
VSYS
Input(2)/output PPU/PPD(2) Yes Push-pull(2) or open- drain Low or high
No
GPIO_2
secondary function:
REGEN2 Output N/A (output) N/A (output) Push-pull(2) or open- drain High
GPIO_3 VRTC, fail-safe
(5.25-V tolerance) Input(2)/output PPD(2) Yes Open-drain Low or high(2) Yes
GPIO_4
(primary function)
VIO (VIO_IN)
Input(2)/output PPU/PPD(2) No
Push-pull
Low or high
No
GPIO_4
secondary function:
SYSEN1 Output N/A (output) N/A (output) High
GPIO_5
(primary function)
VRTC
Input(2)/output PPU/PPD(2) No Push-pull(2) or open- drain Low or high No
GPIO_5
secondary function:
CLK32KGO1V8 or
SYNCCLKOUT
Output N/A (output) N/A (output) Push-pull Toggling No
GPIO_6
(primary function)
VIO (VIO_IN)
Input(2)/output PPU/PPD(2) No
Push-pull
Low or high
No
GPIO_6
secondary function:
SYSEN2 Output N/A (output) N/A (output) High
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Table 4-1. Summary of Digital Signals and Some Dedicated Analog Signals (continued)
SIGNAL NAME POWER DOMAIN /
TOLERANCE LEVEL I/O INPUT PU/PD (1) OTP PU/PD SELECTION OUTPUT TYPE
SELECTION ACTIVE HI/LO OTP POLARITY
SELECTION
GPIO_7
(primary function) VRTC, fail-safe
(5.25-V tolerance)
Input(2)/output PPD(2) Yes Open-drain Low or high
No
GPIO_7
secondary function:
POWERHOLD Input PD fixed No N/A (input) High
NSLEEP VRTC Input PPU(2)/PPD No N/A (input) Low(2) or high No but software possible
ENABLE1 VIO (VIO_IN) Input PPU/PPD(2) No N/A (input) Low or high(2) No but software possible
REGEN1 VSYS (VCC1) Output N/A (output) N/A (output) Push-pull or open- drain
(OTP selection) High No
RESET_IN VRTC, fail-safe
(5.25-V tolerance) Input PPD(2) Yes N/A (input) Low(2) or high Yes
RESET_OUT VIO (VIO_IN) Output N/A (output) N/A (output) Push-pull Low No
NRESWARM VRTC Input PPU(2) No N/A (input) Low No
INT VIO (VIO_IN) Output N/A (output) N/A (output) Push-pull(2) or open- drain Low(2) or high No but software possible
CLK32KGO VIO (VIO_IN) Output N/A (output) N/A (output) Push-pull Toggling No
I2C1_SDA_SDI VIO (VIO_IN) Input/output No No Open-drain High (I2C) Yes (I2C/SPI)
I2C1_SCL_SCK VIO (VIO_IN) Input No No N/A (input) High (I2C) Yes (I2C/SPI)
I2C2_SCL_SCE VIO (VIO_IN) Input No No N/A (input) High (I2C) Yes (I2C/SPI)
I2C2_SDA_SD0 VIO (VIO_IN) Input/output No No Open-drain (I2C) or Push-
pull (SPI) High (I2C) Yes (I2C/SPI)
GPADC_IN0 VRTC Input No No N/A (analog) Analog No
GPADC_IN1 VANA Input No No N/A (analog) Analog No
GPADC_IN2 VANA Input No No N/A (analog) Analog No
GPADC_VREF VANA Output No No N/A (analog) Analog No
OSC16MIN VRTC Input No No N/A (analog) Analog No
OSC16MOUT VRTC Output No No N/A (analog) Analog No
VCC_SENSE2 VSYS (VCC1) Input No No N/A (analog) Analog No
VCC_SENSE VSYS (VCC1) Input No No N/A (analog) Analog No
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Specifications Copyright © 2013–2019, Texas Instruments Incorporated
(1) Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. These are stress ratings
only and functional operation of the device at these or any other conditions beyond those indicated under Recommended Operating
Conditions is not implied. Exposure to absolute-maximum conditions for extended periods may affect device reliability.
(2) When operating the TPS659038-Q1 andTPS659039-Q1 devices without an external crystal, each SMPS regulating an output voltage
greater than 1.8 V must be disabled before VCC is removed. Lowering VCC below the programmed VSYS_LO level while any SMPS is
regulating an output voltage above 1.8 V may cause damage to the device.
5 Specifications
5.1 Absolute Maximum Ratings
See(1) (2).
MIN MAX UNIT
Voltage
Voltage on VCC1 pins –0.3 6 V
Voltage on VCC_SENSE, VCC_SENSE2 pins –0.3 7 V
All LDOs and SMPS supply voltage input pins (except LDOUSB_IN2) –0.3 6 V
Voltage on SMPSx_SW pins, 10 ns transient –2 7 V
All SMPS-related input pins _FDBK –0.3 3.6 V
LDOUSB regulator LDOUSB_IN2 input voltage –0.3 20 V
I/O digital supply voltage (VIO_IN with respect to VIO_GND) –0.3
VIOmax +
0.3
VIOmax +
0.3 V
VBUS –2 20 V
Voltage on the GPADC pins: GPADC_IN0, GPADC_IN1 –0.3 5.25 V
Voltage on the GPADC pins: GPADC_IN2 –0.3 2.5 V
OTP supply voltage VPROG –0.3 20 V
Voltage on VRTC digital input pins Without fail-safe –0.3 2.15 V
With fail-safe –0.3 5.25
Voltage on VIO digital input pins (VIO_IN pin reference) –0.3 VIOmax +
0.3 V
Voltage on VSYS digital input pins (VCC1 pin reference) –0.3 6 V
Current
Peak output current on all pins other than power resources –5 5 mA
Power pins, nFBGA 1 A
Buck SMPS, SMPSx_IN, SMPSx_SW, and SMPSx_OUT total per phase 4 A
LDOs 1 A
Junction temperature range, TJ–45 150 °C
Storage temperature, Tstg –65 150 °C
(1) AEC Q100-002 indicates HBM stressing is done in accordance with the ANSI/ESDA/JEDEC JS-001 specification.
5.2 ESD Ratings
VALUE UNIT
V(ESD) Electrostatic
discharge
Human body model (HBM), per AEC Q100-002(1) ±2000 V
Charge device model (CDM), per AEC Q100-011
Corner pins (A1, A13, N1, and N13) ±750
VPins B4, B7, H8, L1, L2, M3 ±450
All other pins ±500
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SpecificationsCopyright © 2013–2019, Texas Instruments Incorporated
(1) Does not include LDO1 and LDO2 minimum input voltages.
(2) Additional cooling strategies may be necessary to maintain junction temperature at recommended limits.
5.3 Recommended Operating Conditions
Over operating free-air temperature range (unless otherwise noted)
MIN NOM MAX UNIT
All system voltage input pins, VCC1 (named VSYS in the specification) 3.135 3.8 5.25 V
VCC_SENSE and VCC_SENSE2, HIGH_VCC_SENSE = 0 (if measured with GPADC,
see also Table 6-1)3.135 VCC1 V
VCC_SENSE and VCC_SENSE2, HIGH_VCC_SENSE = 1 (if measured with GPADC,
see also Table 6-1)3.135 VCC1 – 1 V
All LDO-related input pins, _IN (except LDOUSB)(1) 1.75 3.8 5.25 V
LDOUSB_IN1 3.6 5.25 V
LDOUSB_IN2 4.3 5.25 V
All SMPS-related input pins, _IN 3.135 3.8 5.25 V
All SMPS-related input pins, _FDBK 0 VOmax + 0.3 V
All SMPS-related input pins, _FDBK_GND –0.3 0.3 V
I/O digital supply voltage, VIO_IN, for 1.8-V Mode 1.71 1.8 1.89 V
I/O digital supply voltage, VIO_IN, for 3.3-V Mode 3.135 3.3 3.465 V
Voltage on the GPADC pins, GPADC_IN0, GPADC_IN1 0 1.25 V
Voltage on the GPADC pins GPADC_IN2 pin 0 2.5 V
Voltage on the crystal oscillator pin, OSC16MIN -0.7 LDOVRT
C1.85 V
OTP supply voltage, VPROG 0 8 10 V
Voltage on VRTC digital input pins 0 LDOVRT
C1.85 V
Voltage on VIO digital input pins (VIO_IN pin reference) 0 VIO VIOmax V
Voltage on VSYS digital input pins (VCC1 pin reference) 0 3.8 5.25 V
Lead temperature (soldering, 10 seconds) 260 °C
Operating free-air temperature(2) –40 27 85 °C
Operating junction temperature, TJ–40 27 125 °C
(1) For more information about traditional and new thermal metrics, see the Semiconductor and IC Package Thermal Metrics application
report.
5.4 Thermal Information
THERMAL METRIC(1)
TPS659038-Q1
TPS659039-Q1 UNIT
ZWS (NFBGA)
169 PINS
RθJA Junction-to-ambient thermal resistance 36.4 °C/W
RθJC(top) Junction-to-case (top) thermal resistance 6.6 °C/W
RθJB Junction-to-board thermal resistance 18.6 °C/W
ψJT Junction-to-top characterization parameter 0.2 °C/W
ψJB Junction-to-board characterization parameter 18.2 °C/W
RθJC(bot) Junction-to-case (bottom) thermal resistance — °C/W
5.5 Electrical Characteristics: Latch Up Rating
Over operating free-air temperature range (unless otherwise noted)
PARAMETER TEST CONDITIONS MIN TYP MAX UNIT
ILU Latch up current Class 2
I2C / SPI pins 90
mALDOVANA_OUT pin –60
All other pins 100
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(1) Additional information about how this parameter is specified is located in the Section 7.2.2 section.
(2) LDO output voltages are programmed separately.
(3) DV(LDOx) = VI–VO, where VO= VOnom – 2%
5.6 Electrical Characteristics: LDO Regulator
Over operating free-air temperature range, typical values are at TA= 27°C (unless otherwise noted)
PARAMETER TEST CONDITIONS MIN TYP MAX UNIT
Input filtering capacitance (C29, C30,
C31, C32, C33, C34) Connected from LDOx_IN to GND. Shared input tank capacitance
(depending on platform requirements) 0.6 2.2 µF
Output filtering capacitance (C35,
C36, C37, C38, C39, C40, C41, C42,
C43, C45, C46, C47)(1) Connected from LDOx_OUT to GND (Except LDO9) 0.6 2.2 2.7 µF
LDO9 Output filtering capacitance
(C44)(1)
Connected from LDO9_OUT to GND 0.6 2.2 2.7
µF
Connected from LDO9_OUT to GND. LDO9 configured in BYPASS MODE
(LDO9_CTRL.LDO_PYPASS_EN = 1) 0.6 1 1.2
LDO6 inductive load (LDO6) Connected between LDO6 output (LDO6_OUT) and GND 70 350 700 µH
LDO6 load resistance (LDO6) 15 40 50 Ω
CESR Filtering capacitor ESR < 100 kHz 20 100 600 mΩ
1≤MHz f ≤10 MHz 1 10 20 mΩ
VI(LDOx) Input voltage
LDO1, LDO2 0.9V ≤VO≤2.15V 1.2 VCC1
V
2.2V ≤VO≤3.3V 1.2 5.25
LDOLN, LDO3, LDO4, LDO5, LDO6, LDO7,
LDO8
0.9V ≤VO≤2.15V 1.75 VCC1
2.2V ≤VO≤3.3V 1.75 5.25
LDO9
0.9V ≤VO≤1.75V 1.75 VCC1
1.8V ≤VO≤3.3V 1.75 5.25
Bypass Mode 1.75 3.6
VI(LDOUSB1) Input voltage LDOUSB from LDOUSB_IN1 0.9V ≤VO≤2.15V 3.6 VCC1
2.2V ≤VO≤3.3V 3.6 5.25
VI(LDOUSB2) Input voltage LDOUSB from LDOUSB_IN2 0.9V ≤VO≤2.15V 4.3 VCC1
2.2V ≤VO≤3.3V 4.3 5.25
VCC(1) Input voltage VCC1 used for internal power supply 3.135 3.8 5.25
VO(LDOx) LDO output voltage programmable(2)
(except LDOVRTC and LDOVANA)
VO(LDOx) < VI(LDOx) - DV(LDOx) 0.9 3.3 V
Step size 50 mV
TDCOV(LDOx)
Total DC output voltage accuracy,
including voltage references, DC load
and line regulations, process and
temperature
All LDOs except LDO3, LDO4, LDOVANA, and LDOVRTC 0.99 ×
VO(LDOx)
–0.014
1.006 ×
VO(LDOx)
+0.014
V
LDO3, LDO4: IO≤200 mA 0.99 ×
VO(LDOx)
–0.014
1.006 ×
VO(LDOx)
+0.014
LDO3, LDO4: 200 mA < IO≤300 mA 0.99 ×
VO(LDOx)
–0.018
1.006 ×
VO(LDOx)
+0.018
LDOVRTC_OUT 1.726 1.8 1.850
LDOVANA_OUT 2.002 2.093 2.119
VDROPOUT(LDOx) Dropout voltage(3)
LDO1, LDO2: IO= IOmax 150
mV
LDO3, LDO4: IO= 200 mA 290
LDO3, LDO4: IO= IOmax 550
LDO5, LDO6, LDO7, LDO8: IO= IOmax 290
LDO9: IO= IOmax 230
LDOLN: IO= IOmax 150
LDOLN: IO= 100 mA (Functional, not low-noise performance) 290
LDOUSB – From LDOUSB_IN1: IO= IOmax 200
LDOUSB – From LDOUSB_IN2: IO= IOmax 900
VDROPOUT(LDOx) Dropout voltage (internal LDOs) LDOVRTC, LDOVANA: IO= IOmax 150
IO(LDOx) Output current
LDO1, LDO2, LDO3, LDO4 300
mA
LDO5, LDO6, LDO7 200
LDO8 170
LDO9, LDOLN 50
LDOUSB 100
IO(LDOx) Output current, internal LDOs LDOVANA 10
LDOVRTC 25
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Electrical Characteristics: LDO Regulator (continued)
Over operating free-air temperature range, typical values are at TA= 27°C (unless otherwise noted)
PARAMETER TEST CONDITIONS MIN TYP MAX UNIT
ISHORT(LDOx) LDO current limitation
LDO1, LDO2 380 600 1800
mA
LDO3, LDO4, LDO5, LDO6, LDO7, LDO8 400 650 1300
LDO9 120 200 400
LDOUSB 120 250 600
LDOLN 150 325 740
LDOVANA 100 250 400
LDOVRTC 55 250 400
LDO inrush current LDO1, LDO2 500 mA
ΔVO(ΔVI)(DC) DC load regulation ΔVO
IO= 0 to IOmax at pin, LDO1, LDO2 4 16
mV
IO= 0 to 200 mA at pin, LDO3, LDO4 4 14
IO= 0 to IOmax at pin, LDO3, LDO4 4 18
IO= 0 to IOmax at pin, all other LDOs 4 14
ΔVO(ΔVI)(DC) DC line regulation, except VRTC,
ΔVO/ VO
VI= VImin to VImax, IO= IOmax 0.1% 0.2%
VSYS = VSYSmin to VSYSmax, IO = IOUTmax. VIN constant (LDO
preregulated), VO≤2.2 V 0.3% 0.75%
DCLNR(LDOVRTC) DC line regulation on LDOVRTC,
ΔVO/VOVSYS = VSYSmin to VSYSmax, IO= IOmax 1%
Bypass resistance of LDO9 VI≥2.7 V, programmed to BYPASS 4.2 Ω
ton Turnon time IO= 0, VO= 0.1 V up to VOmin 100 500 µs
toff Turnoff time
(except VRTC ) IO= 0, VOdown to 10% × VO250 500 µs
RDIS Pulldown discharge resistance at LDO
output, except LDOVRTC OFF mode, pulldown enabled and LDO disabled. Also applies to bypass
mode 30 125 Ω
PSRR
Power supply ripple rejection, LDO1,
LDO2
ƒ= 217 Hz, IO= IOmax 55 90
dBƒ = 50 kHz, IO= IOmax 28 45
ƒ = 1 MHz, IO= IOmax 25 35
Power supply ripple rejection, LDO3,
LDO4
ƒ = 217 Hz, IO= 200 mA 55 90
dB
ƒ = 217 Hz, IO= IOmax 50 60
ƒ = 50 kHz, IO= IOmax 20 45
ƒ = 1 MHz, IO= IOmax 20 35
Power supply ripple rejection, LDO5,
LDO6, LDO7, LDO8, LDO9, LDOUSB
ƒ = 217 Hz, IO= IOmax 55 90
dBƒ = 50 kHz, IO= IOmax 20 45
ƒ = 1 MHz, IO= IOmax 20 35
Power supply ripple rejection, LDOLN
ƒ = 217 Hz, IO= IOmax 55 90
dBƒ = 50 kHz, IO= IOmax 25 45
ƒ = 1 MHz, IO= IOmax 25 35
IQ(off) Quiescent current OFF mode For all LDOs, T = 27°C 0.1 µA
For all LDOs, T ≥85°C 0.2
IQ(on) Quiescent current LDO ON mode
IL= 0 mA (LDO1, LDO2), 0.9 V ≤VO≤3.3 V, VO(LDOx) < VI(LDOx) – DV(LDOx) 39 70
µA
IL= 0 mA (LDO3, LDO4, LDO5, LDO6, LDO7, LDO8, LDO9), VO(LDOx) <
VI(LDOx) – DV(LDOx) 36 47
IL= 0 mA (LDOLN) , VO≤1.8 V, VO(LDOx) < VI(LDOx) – DV(LDOx) 140 190
IL= 0 mA (LDOLN) , VO> 1.8 V, VO(LDOx) < VI(LDOx) – DV(LDOx) 180 210
IL= 0 mA (LDOUSB) – IN1, VO(LDOx) < VI(LDOx) – DV(LDOx) 45 65
IL= 0 mA (LDOUSB) – IN2, VO(LDOx) < VI(LDOx) – DV(LDOx) 18 25
αQQuiescent current coefficient LDO ON
mode, IQO = IQ(on) +αQ × IO
IO< 100 µA 4%
100 µA ≤IO< 1 mA 2%
IO≥1 mA 1%
TLDR Transient load regulation ΔVO
ON mode, IO= 10 mA to IOmax / 2, tr= tf= 1 µs. All LDOs except LDO3,
LDO4, LDO9, LDOLN –25 25
mV
ON mode, IO= 10 mA to 100 mA, tr= tf= 1 µs. LDO3, LDO4 –25 25
ON mode, IO= 10 mA to IOmax / 2, tr= tf= 1 µs. LDO3, LDO4 –40 25
ON mode, IO= 1 mA to IOmax /2, tr= tf= 1 µs. LDO9, LDOLN –25 25
ON mode, IO= 100 µA to IOmax / 2, tr= tf= 1 µs. –50 33
TLNR Transient line regulation, ΔVO/ VO
VIstep = 600 mVpp, tr= tf= 10 µs 0.25% 0.5%
VSYS step = 600 mVpp, tr= tf= 10 µs. VIconstant (LDO preregulated), VO≤
2.2 V 0.8% 1.6%
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Electrical Characteristics: LDO Regulator (continued)
Over operating free-air temperature range, typical values are at TA= 27°C (unless otherwise noted)
PARAMETER TEST CONDITIONS MIN TYP MAX UNIT
Noise (except LDOLN)
100 Hz < ƒ ≤10 kHz 5000 8000
nV/√Hz
10 kHz < ƒ ≤100 kHz 1250 2500
100 kHz < IJ1 MHz 150 300
ƒ > 1 MHz 250 500
Noise (LDOLN)
100 Hz < ƒ ≤5 kHz, IO= 50 mA, VO≤1.8 V 400 500
nV/√Hz5 kHz < ƒ ≤400 kHz, IO= 50 mA, VO≤1.8 V 62 125
400 kHz < ƒ ≤10 MHz, IO= 50 mA, VO≤1.8 V 25 50
Ripple LDO1, LDO2, ripple (from internal charge pump) 5 mVpp
(1) Additional information about how this parameter is specified is located in the Section 7.2.2 section.
5.7 Electrical Characteristics: Dual-Phase (SMPS12 and SMPS45) and Triple-Phase
(SMPS123 and SMPS457) Regulators
Over operating free-air temperature range, typical values are at TA= 27°C (unless otherwise noted)
PARAMETER TEST CONDITIONS MIN TYP MAX UNIT
Input capacitance (C9, C10, C11, C12,
C13) 4.7 µF
Output capacitance (C18, C19, C21,
C22)(1) SMPS12 or SMPS45 dual phase operation, per phase 33 47 57 µF
Output capacitance (C20, C24)(1) SMPS3 and SMPS7 (triple phase operation) 33 47 57
CESR Filtering capacitor ESR 1 ≤MHz f ≤10 MHz 2 10 mΩ
Output filter inductance (L1, L2, L3, L4,
L5) SMPSx_SW 0.7 1 1.3 µH
DCRLFilter inductor DC resistance 50 100 mΩ
VI(SMPSx) Input voltage range, SMPSx_IN VSYS (VCC1) 3.135 5.25 V
VOSMPSx Output voltage, programmable, SMPSx
RANGE = 0 (value for RANGE must not be changed when SMPS is
active). In Eco-mode the output voltage values are fixed (defined
before Eco-mode is enabled). RANGE = 1 is not supported for Multi-
phase regulators.
0.7 1.65 V
Step size, 0.7 V ≤VO≤1.65 V (RANGE = 0) 10 mV
DC output voltage accuracy, includes
voltage references, DC load/line
regulation, process and temperature
Eco-mode –3% 4%
Forced PWM mode –1% 2%
Ripple, dual phase Max load, VI= 3.8 V, VO= 1.2 V, ESRCO = 2 mΩ, measure with 20-
MHz LPF 4 mVPP
Ripple, triple phase Max load, VI= 3.8 V, VO= 1.2 V, ESRCO = 2 mΩ, measure with 20-
MHz LPF 1 mVPP
DCLNR DC line regulation 0.1 %/V
DCLDR DC load regulation 0.1 %/A
TLDSR
Transient load step response, dual
phase IO= 0.8 to 2 A, tr= tf= 400 ns, CO= 47 µF , L= 1 µH 3%
Transient load step response, triple
phase IO= 0.8 to 2 A, tr= tf= 400 ns, CO= 47 µF , L= 1 µH 3%
Transient load step response, dual or
triple phase IO= 0.5 to 500 mA, tr= tf= 100 ns, CO= 47 µF , L= 1 µH 3%
IOmax
Rated output current, SMPS12 Advance thermal design is required to avoid thermal shutdown 6
ARated output current, SMPS123 Advance thermal design is required to avoid thermal shutdown 9
Rated output current, SMPS45 Advance thermal design is required to avoid thermal shutdown 4
Maximum output current, Eco-mode 5 mA
ILIM HS FET High-side MOSFET forward current limit SMPS123, each phase 3.7 4 A
SMPS45, each phase 2.7 3
ILIM LS FET Low-side MOSFET forward current limit SMPS123, each phase 3.7 A
SMPS45, each phase 2.7
Low-side MOSFET negative current limit SMPS123, phase 1 0.6 A
SMPS45, phase 4 0.6
rDS(on) HS FET N-channel MOSFET on-resistance,
high-side FET
SMPS123, each phase 115 mΩ
SMPS45, each phase 115
rDS(on) LS FET N-channel MOSFET on-resistance, low-
side FET
SMPS123, each phase 30 mΩ
SMPS45, each phase 30
tstart Time from enable to start of the ramp 150 µs
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Electrical Characteristics: Dual-Phase (SMPS12 and SMPS45) and Triple-Phase (SMPS123 and
SMPS457) Regulators (continued)
Over operating free-air temperature range, typical values are at TA= 27°C (unless otherwise noted)
PARAMETER TEST CONDITIONS MIN TYP MAX UNIT
tramp Time from enable to 80% of VOCO< 57 µF per phase, no load 400 1000 µs
Overshoot during turn-on 5%
Output voltage slew rate Fixed TSTEP 2.5 mV/µs
RDIS Pulldown discharge resistance at
SMPS2, SMPS4 output
SMSP turned off 300
Ω
SMPSx_SW, SMPS turned off. Pulldown is at the master phase
output. 9 22
RSENSE Input resistance for remote sense/sense
line
Between SMPS1_2_FDBK, SMPS1_2_FDBK_GND 380 1300
kΩBetween SMPS4_5_FDBK, SMPS4_5_FDBK_GND 380 1300
SMPS3_FDBK input resistance 380 1300
IQ(off) Quiescent current – OFF mode IL= 0 mA 0.1 1 µA
IQ(on) Quiescent current - ON mode, dual or
triple phase
Eco-mode, device not switching, VO< 1.8 V 13.5 19 µA
Eco-mode, device not switching, VO≥1.8 V 15 21
FORCED_PWM mode, IL= 0 mA, VI= 3.8 V, device switching, 1-
phase operation 11 mA
VSMPSPG Powergood threshold SMPS output voltage rising, referenced to programmed output voltage –7.5%
SMPS output voltage falling, referenced to programmed output voltage –12.5%
IL_AVG_COMP Powergood: GPADC monitoring SMPS
IL_AVG_COMP_rising IOmax– 20% IOmax IOmax + 20%
IL_AVG_COMP_falling, 3A-phase IL_AVG_COMP_rising – 5%
IL_AVG_COMP_falling, 2A-phase IL_AVG_COMP_rising – 8%
(1) Additional information about how this parameter is specified is located in the Section 7.2.2 section.
5.8 Electrical Characteristics: Stand-Alone Regulators (SMPS3, SMPS6, SMPS7, SMPS8,
and SMPS9)
Over operating free-air temperature range, typical values are at TA= 27°C (unless otherwise noted)
PARAMETER TEST CONDITIONS MIN TYP MAX UNIT
Input capacitance (C11, C14, C15, C16,
C17) 4.7 µF
Output capacitance (C20, C23, C24,
C25, C26)(1) SMPSx operation 33 47 57 µF
CESR Filtering capacitor DC ESR 1 ≤MHz f ≤10 MHz 2 10 mΩ
Output filter inductance (L3, L6, L7, L8,
L9) SMPSx_SW 0.7 1 1.3 µH
DCRLFilter inductor DC resistance 50 100 mΩ
VI(SMPSx) Input voltage range, SMPSx_IN VSYS (VCC1) 3.135 5.25 V
VOSMPSx Output voltage, programmable, SMPSx
RANGE = 0 (value for RANGE must not be changed when SMPS is
active). In Eco-mode the output voltage value is fixed (defined before
Eco-mode is enabled). 0.7 1.65
V
RANGE = 1 (value for RANGE must not be changed when SMPS is
active). In Eco-mode the output voltage value is fixed (defined before
Eco-mode is enabled). 1 3.3
Step size, 0.7 V ≤VO≤1.65 V 10 mV
Step size, 1 V ≤VO≤3.3 V 20
DC output voltage accuracy, includes
voltage references, DC load/line
regulation, process and temperature
Eco-mode –3% 4%
PWM mode –1% 2%
Ripple Max load, VI= 3.8 V, VO= 1.2 V,
ESRCO = 2 mΩ, measure with 20-MHz LPF 8 mVPP
DCLNR DC line regulation TA= –40°C to 85°C 0.1 %/V
DCLDR DC load regulation TA= –40°C to 85°C 0.1 %/A
TLDSR Transient load step response
SMPS3, SMPS6, SMPS7 , IOUT = 0.5 to 500 mA,
tr= tf= 100 ns, CO= 47 µF , L = 1 µH 3%
SMPS8, SMPS9, IO= 0.5 to 500 mA,
tr= tf= 1 µs, CO= 47 µF , L = 1 µH 3%
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Electrical Characteristics: Stand-Alone Regulators (SMPS3, SMPS6, SMPS7, SMPS8, and
SMPS9) (continued)
Over operating free-air temperature range, typical values are at TA= 27°C (unless otherwise noted)
PARAMETER TEST CONDITIONS MIN TYP MAX UNIT
IOmax
Rated output current, SMPS3
VI≥3 V
Advance thermal design is required to avoid thermal shutdown 3
A
VI< 3 V
Advance thermal design is required to avoid thermal shutdown 2
Rated output current, SMPS6
When OTP programmed with BOOST_CURRENT = 0
Advance thermal design is required to avoid thermal shutdown 2
When OTP programmed with BOOST_CURRENT = 1
Advance thermal design is required to avoid thermal shutdown 3
Rated output current, SMPS7 Advance thermal design is required to avoid thermal shutdown 2
Rated output current, SMPS8, SMPS9 Advance thermal design is required to avoid thermal shutdown 1
Maximum output current, Eco-mode 5 mA
ILIM HS FET High-side MOSFET forward current limit
SMPS3 and SMPS6 in 3-A mode 3.7 4
ASMPS6 in 2-A mode, SMPS7 2.7 3
SMPS8, SMPS9 1.7 2
ILIM LS FET Low-side MOSFET forward current limit
SMPS3 and SMPS6 in 3-A mode 3.7
ASMPS6 in 2-A mode, SMPS7 2.7
SMPS8, SMPS9 1.7
Low-side MOSFET negative current limit
SMPS3 and SMPS6 in 3-A mode 0.6
ASMPS6 in 2-A mode, SMPS7 0.6
SMPS8, SMPS9 0.6
rDS(on) HS FET N-channel MOSFET on-resistance
(high-side FET)
SMPS3 115
mΩSMPS6, SMPS7 115
SMPS8, SMPS9 180
rDS(on) LS FET N-channel MOSFET on-resistance (low-
side FET)
SMPS3 30
mΩSMPS6, SMPS7 30
SMPS8, SMPS9 79
tstart Time from enable to start of the ramp 150 µs
tramp Time from enable to 80% of VOCO< 57 µF, no load 400 1000 µs
Overshoot during turn-on 5%
Output voltage slew rate Fixed TSTEP, only available on SMPS6, SMPS8 2.5 mV/µs
RDIS Pulldown discharge resistance at
SMPSx output
SMPSx_FDBK, SMPS turned off 300 Ω
SMPSx_SW, SMPS turned off 9 22
IQ(off) Quiescent current – OFF mode IL= 0 mA 0.1 1 µA
IQ(on) Quiescent current – ON mode - SMPS3,
SMPS6, SMPS7
Eco-mode, device not switching, VO< 1.8 V 12 15 µA
Eco-mode, device not switching, VO≥1.8 V 13.5 23
FORCED_PWM mode, IL= 0 mA,
VI= 3.8 V, device switching 11 mA
IQ(on) Quiescent current – ON mode - SMPS8,
SMPS9
Eco-mode, device not switching, VO< 1.8 V 10.5 15 µA
Eco-mode, device not switching, VO≥1.8 V 12 23
FORCED_PWM mode, IL= 0 mA,
VI= 3.8 V, device switching 7 mA
VSMPSPG Powergood threshold SMPS output voltage rising, referenced to programmed output voltage –7.5%
SMPS output voltage falling, referenced to programmed output voltage –12.5%
IL_AVG_COMP Powergood: GPADC monitoring SMPS
IL_AVG_COMP_rising IOmax – 20% IOmax IOmax + 20%
IL_AVG_COMP_falling, 3-A phase IL_AVG_COMP_rising – 5%
IL_AVG_COMP_falling, 2-A phase IL_AVG_COMP_rising – 8%
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5.9 Electrical Characteristics: Reference Generator (Bandgap)
Over operating free-air temperature range, typical values are at TA= 27°C (unless otherwise noted)
PARAMETER TEST CONDITIONS MIN TYP MAX UNIT
Filtering capacitor Connected from VBG to REFGND 30 100 150 nF
Input voltage (VI) 2.1 3.8 5.25 V
Output voltage 0.85 V
Ground current 20 40 µA
Start-up time 1 3 ms
5.10 Electrical Characteristics: 16-MHz Crystal Oscillator, 32-kHz RC Oscillator, and
Output Buffers
Over operating free-air temperature range, typical values are at TA= 27°C (unless otherwise noted)
PARAMETER TEST CONDITIONS MIN TYP MAX UNIT
CRYSTAL CHARACTERISTICS
Crystal frequency Typical with specified load capacitors 16.384 MHz
Crystal frequency tolerance Parameter of crystal; TA= 27°C –20 20 ppm
Crystal motional inductance Parameter of crystal 23 33 43 mH
Crystal series resistance At fundamental frequency 90 Ω
Oscillator drive power The power dissipated in the crystal during oscillator
operation 15 120 µW
Load capacitance Corresponding to crystal frequency, including
parasitic capacitances 9 10 11 pF
Crystal shunt capacitance Parameter of crystal 0.5 4 pF
Oscillator frequency drift TJfrom –40°C to 125°C, VCC1 from 3.15 V to 5.25
V
Excluding crystal tolerance –50 50 ppm
Oscillator startup time Time from VCC1 > 3.15 V until 32-kHz clock output
is available from crystal oscillator 10 ms
32-kHz RC OSCILLATOR
Output frequency low-level output voltage 32768 Hz
Output frequency accuracy After trimming, TA= 27°C –10% 0 10%
Cycle jitter (RMS) 10%
Output duty cycle 40% 50% 60%
Settling time 150 µs
Active current consumption 4 8 µA
Power-down current 30 nA
CLK32KGO OUTPUT BUFFER
Logic output external load 5 35 50 pF
Rise and fall time CL= 35 pF, 10% to 90% 5 50 100 ns
Duty cycle Logic output signal 40% 50% 60%
CLK32KGO1V8 OUTPUT BUFFER
Settling time 25 50 µs
Active current consumption 5 7 10 µA
Power-down current 30 nA
Duty cycle degradation contribution –2% 2%
External output load 5 10 50 pF
Output delay time Output load = 10 pF 15 30 ns
Output rise/fall time Output load = 10 pF 7.5 20 ns
SYNCCLKOUT OUTPUT BUFFER
Logic output external load 5 35 50 pF
Rise and fall time CL= 35 pF, 10% to 90% 5 50 100 ns
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Electrical Characteristics: 16-MHz Crystal Oscillator, 32-kHz RC Oscillator, and Output
Buffers (continued)
Over operating free-air temperature range, typical values are at TA= 27°C (unless otherwise noted)
PARAMETER TEST CONDITIONS MIN TYP MAX UNIT
Duty cycle Logic output signal 40% 50% 60%
5.11 Electrical Characteristics: DC-DC Clock Sync
Over operating free-air temperature range, typical values are at TA= 27°C (unless otherwise noted)
PARAMETER TEST CONDITIONS MIN TYP MAX UNIT
SYNC CLOCK SPECIFICATION AND DITHER PARAMETERS
ƒSYNC The allowed range of the
external sync clock input 1.7 2.2 2.7 MHz
ADITHER Dither amplitude 128 kHz
MDITHER Dither slope 1.35 kHz/
µs
SYNC DC-DC DIGITAL CLOCK INPUT
VIL Low-level input on
SYNCDCDC pin –0.3 0 0.3 ×
VRTC V
VIH High-level input on
SYNCDCDC pin 0.7 ×
VRTC VRTC 5.25 V
Duty cycle of SYNCDCDC
input signal 20% 80%
Hysteresis of input buffer 0.1 ×
VRTC V
SYNC CLOCK AND FREQUENCY FALLBACK
ƒFALLBACK Fall-back frequency 1.98 2.2 2.42 MHz
ƒSAT,LO The low saturation frequency
output of the PLL 1.65 MHz
ƒSAT,HI The high saturation
frequency output of the PLL 2.8 MHz
ƒSETTLE
Time from initial application
or removal of sync clock until
PLL output has settled to 1%
of its final value
100 µs
ƒERROR
The steady-state percent
difference between fSYNC and
the switching frequency –1% 1%
td
Time delay between
corresponding staggered
phases 15 30 45 ns
5.12 Electrical Characteristics: 12-Bit Sigma-Delta ADC
Over operating free-air temperature range, typical values are at TA= 27°C (unless otherwise noted)
PARAMETER TEST CONDITIONS MIN TYP MAX UNIT
IQ(on) Current consumption During conversion 1500 1600 µA
IQ(off) OFF mode current GPADC is not enabled (no conversion) 1 µA
ƒ Running frequency 2.5 MHz
Resolution 12 Bit
Number of available external
inputs 3
Number of available internal
inputs 5
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Electrical Characteristics: 12-Bit Sigma-Delta ADC (continued)
Over operating free-air temperature range, typical values are at TA= 27°C (unless otherwise noted)
PARAMETER TEST CONDITIONS MIN TYP MAX UNIT
Turnon time
Active or sleep with VANA ON and
RC15MHZ_ON_IN_SLEEP = 1 or sleep with
GPADC_FORCE = 1 0 µs
Sleep or OFF 794 µs
Sleep with VANA enabled 282 µs
Gain error (without scaler) –3.5% 3.5%
Gain error of the scaler –1% 1%
Offset before trimming –50 50 LSB
Offset drift after trimming Temperature and supply –2 2 LSB
Gain error drift (after
trimming, including reference
voltage) Temperature and supply –0.6% 0.2%
INL Integral nonlinearity Best fitting –3.5 3.5 LSB
DNL Differential nonlinearity –1 3.5 LSB
Input capacitance GPADC_IN0–GPADC_IN2 0.5 pF
Source input impedance Source resistance without capacitance 20 kΩ
Source capacitance with > 20-kΩsource resistance 100 nF
GPADC_VREF voltage
reference 1.237 1.25 1.263 V
Load current for
GPADC_VREF 200 µA
Input range (sigma-delta
ADC)
Typical range 0 1.250 V
Assured range without saturation 0.01 1.215
Conversion time
1 channel, EXTEND_DELAY = 0 113
µs1 channel, EXTEND_DELAY = 1 563
2 channels 223
GPADC_IN0 current source
CURRENT_SRC_CH0[1:0] = 00 (default) 0
µA
CURRENT_SRC_CH0[1:0] = 01 4.5 5.13 5.75
CURRENT_SRC_CH0[1:0] = 10 14.45 15.55 16.65
CURRENT_SRC_CH0[1:0] = 11 19.2 20.7 22.1
SMPS current monitoring
(GPADC Channel 11) See Equation 1 and Equation 2
IFS0
Channel 11 SMPS output
current measurement gain
factor 3.958 A
IOS0
Channel 11 SMPS output
current measurement current
offset 0.652 A
TC_R0 Channel 11 SMPS output
current measurement
temperature coefficient –1090 ppm/
C
SMPS output current
measurement Accuracy, IERR
(%), GPADC trimmed
SMPS3, SMPS6, SMPS7 IL_error (%) = IL_meas / IL×
100 at 1 A, 25°C –13% 13%
SMPS6, SMPS7 IL_error (%) = ILOAD_meas / IL× 100
at 2 A, 25°C –9% 9%
SMPS3 IL_error (%) = IL_meas / IL× 100 at 3 A, 25°C –8% 8%
SMPS45 IL_error (%) = IL_meas / IL× 100 at 4 A, 25°C –7% 7%
SMPS12 IL_error (%) = IL_meas / IL× 100 at 6 A,
25°C, –7% 7%
SMPS123 IL_error (%) = IL_meas / IL× 100 at 9 A,
25°C –7% 7%
l TEXAS INSTRUMENTS
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5.13 Electrical Characteristics: Thermal Monitoring and Shutdown
Over operating free-air temperature range, typical values are at TA= 27°C (unless otherwise noted)
PARAMETER TEST CONDITIONS MIN TYP MAX UNIT
Hot-die temperature
threshold
Rising threshold, THERM_HD_SEL[1:0] = 00 104 117 129
°C
Falling threshold, THERM_HD_SEL[1:0] = 00 95 108 119
Rising threshold, THERM_HD_SEL[1:0] = 01 109 121 133
Falling threshold, THERM_HD_SEL[1:0] = 01 99 112 124
Rising threshold, THERM_HD_SEL[1:0] = 10 113 125 136
Falling threshold, THERM_HD_SEL[1:0] = 10 104 116 128
Rising threshold, THERM_HD_SEL[1:0] = 11 117 130 143
Falling threshold, THERM_HD_SEL[1:0] = 11 108 120 132
Thermal shutdown threshold Rising threshold 133 148 163 °C
Falling threshold 111 123 135
IQ(off)
Off ground current (two
sensors on the die,
specification for one sensor)
Device in OFF state, VCC1 = 3.8 V, T = 25°C 0.1 µA
Device in OFF state 0.5
IQ(on)
On ground current (two
sensors on the die,
specification for one sensor)
Device in ACTIVE state, VCC1 = 3.8 V, T = 25°C 7 15 µA
Device in ACTIVE state, GPADC measurement 25 40
5.14 Electrical Characteristics: System Control Thresholds
Over operating free-air temperature range, typical values are at TA= 27°C (unless otherwise noted)
PARAMETER TEST CONDITIONS MIN TYP MAX UNIT
POR (power-on reset) rising-edge threshold Measured on VCC1 pin 2 2.15 2.5 V
POR falling-edge threshold Measured on VCC1 pin 1.9 2 2.1 V
POR hysteresis Rising edge to falling edge 40 300 mV
VSYS_LO, measured on VCC1 pin Voltage range, 50-mV steps 2.75 3.10 V
Voltage accuracy –50 95 mV
VSYS_LO hysteresis Falling edge to rising edge 75 460 mV
VSYS_HI, measured on VCC_SENSE pin Voltage range, 50-mV steps 2.9 3.85 V
Voltage accuracy –55 105 mV
VSYS_MON, measured on VCC_SENSE
pin
Voltage range, 50-mV steps 2.75 4.6 V
Voltage accuracy –70 140 mV
VBUS Detection (VBUS wake-up
comparator threshold)
Rising Threshold 2.9 3.6 V
Falling Threshold 2.8 3.3 V
5.15 Electrical Characteristics: Current Consumption
Over operating free-air temperature range, typical values are at TA= 27°C (unless otherwise noted)
PARAMETER TEST CONDITIONS MIN TYP MAX UNIT
OFF MODE
Current consumption in
OFF mode VSYS (VCC1) = 3.8 V 20 45 µA
SLEEP MODE
Current consumption in
SLEEP mode
LDO2 and LDO9 enabled without load,
16-MHz oscillator completely disabled
with system clock coming solely on
internal 32KHz RC oscillator
VSYS (VCC1) = 3.8 V 120 180
µA
VSYS (VCC1) = 5.25 V 150 225
LDO2 and LDO9 enabled without load,
16-MHz oscillator enabled
VSYS (VCC1) = 3.8 V 2.64 2.81 mA
VSYS (VCC1) = 5.25 V 3.3 3.5
l TEXAS INSTRUMENTS
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5.16 Electrical Characteristics: Digital Input Signal Parameters
Over operating free-air temperature range, typical values are at TA= 27°C, VIO refers to the VIO_IN pin, VSYS to the VCC1
pin (unless otherwise noted)
PARAMETER TEST CONDITIONS MIN TYP MAX UNIT
PWRON, RPWRON
VIL
Low-level input voltage
related to VSYS (VCC1 pin
reference) –0.3 0 0.35 ×
VSYS V
VIH
High-level input voltage
related to VSYS (VCC1 pin
reference)
0.65 ×
VSYS VSYS VSYS +
0.3 ≤
5.25 V
Hysteresis 0.05 ×
VSYS V
ENABLE1, GPIO_4, GPIO_6, I2C1_SCL_SCK, I2C1_SDA_SDI, I2C2_SCL_SCE, I2C2_SDA_SDO
VIL
Low-level input voltage
related to VIO (VIO_IN pin
reference) –0.3 0 0.3 ×
VIO V
VIH
High-level input voltage
related to VIO (VIO_IN pin
reference)
0.7 ×
VIO VIO VIO +
0.3 V
Hysteresis 0.05 ×
VIO V
CBCapacitive load for SDA and
SCL in I2C mode 400 pF
BOOT0, PWRDOWN, RESET_IN, NSLEEP, NRESWARM, GPIO_0, GPIO_1, GPIO_2, GPIO_3, GPIO_5, GPIO_7 OR POWERHOLD
VIL Low-level input voltage
related to VRTC –0.3 0 0.3 ×
VRTC V
VIH High-level input voltage
related to VRTC 0.7 ×
VRTC VRTC VRTC +
0.3 V
Hysteresis 0.05 ×
VRTC V
Input voltage maximum for
RESET_IN and GPIO_7 5.25 V
BOOT1
VIL Low-level input voltage
related to VRTC –0.3 0 0.3 ×
VRTC V
VIH High-level input voltage
related to VRTC 0.95 ×
VRTC VRTC VRTC +
0.3 V
5.17 Electrical Characteristics: Digital Output Signal Parameters
Over operating free-air temperature range, typical values are at TA= 27°C, VIO refers to the VIO_IN pin, VSYS to the VCC1
pin (unless otherwise noted)
PARAMETER TEST CONDITIONS MIN TYP MAX UNIT
REGEN1, REGEN2
VOL Low-level output voltage,
push-pull and open-drain
IOL = 2 mA 0 0.45 V
IOL = 100 µA 0 0.2 V
VOH High-level output voltage ,
push-pull
IOH = 2 mA VSYS –
0.45 VSYS V
IOH = 100 µA VSYS –
0.2 VSYS V
Supply for external pullup
resistor, open-drain VSYS V
GPIO_1 or VBUSDET, GPIO_2
VOL Low-level output voltage,
push-pull and open-drain IOL = 10 mA 0 0.4 V
l TEXAS INSTRUMENTS
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Electrical Characteristics: Digital Output Signal Parameters (continued)
Over operating free-air temperature range, typical values are at TA= 27°C, VIO refers to the VIO_IN pin, VSYS to the VCC1
pin (unless otherwise noted)
PARAMETER TEST CONDITIONS MIN TYP MAX UNIT
VOH High-level output voltage,
push-pull
IOH = 2 mA VSYS –
0.45 VSYS V
IOH = 100 µA VSYS –
0.2 VSYS V
Supply for external pullup
resistor, open-drain VSYS V
INT
VOL Low-level output voltage,
push-pull and open-drain
IOL = 2 mA 0 0.45 V
IOL = 100 µA 0 0.2 V
VOH
High-level output voltage,
push-pull (VIO_IN pin
reference)
IOH = 2 mA VIO –
0.45 VIO V
IOH = 100 µA VIO – 0.2 VIO V
Supply for external pullup
resistor, open-drain VIO V
GPIO_4 or SYSEN1, GPIO_6 or SYSEN2, RESET_OUT
VOL Low-level output voltage,
push-pull
IOL = 2 mA 0 0.45 V
IOL = 100 µA 0 0.2 V
VOH
High-level output voltage,
push-pull (VIO_IN pin
reference)
IOH = 2 mA VIO –
0.45 VIO V
IOH = 100 µA VIO – 0.2 VIO V
POWERGOOD
VOL Low-level output voltage,
open-drain
IOL = 2 mA 0 0.45 V
IOL = 100 µA 0 0.2 V
Supply for external pullup
resistor, open-drain VRTC V
GPIO5
VOL Low-level output voltage,
open-drain
IOL = 2 mA 0 0.45 V
IOL = 100 µA 0 0.2 V
VOL Low-level output voltage,
push-pull
IOL = 2 mA 0 0.45 V
IOL = 100 µA 0 0.2 V
VOH High-level output voltage,
push-pull
IOH = 2 mA VRTC –
0.45 VRTC V
IOH = 100 µA VRTC –
0.2 VRTC V
Supply for external pullup
resistor, open-drain VRTC V
CLK32KGO1V8, SYNCCLKOUT
VOL Low-level output voltage,
push-pull
IOL = 1 mA 0 0.45 V
IOL = 100 µA 0 0.2 V
VOH High-level output voltage,
push-pull
IOH = 1 mA VRTC –
0.45 VRTC V
IOH = 100 µA VRTC –
0.2 VRTC V
CLK32KGO
VOL Low-level output voltage,
push-pull
IOL = 1 mA 0 0.45 V
IOL = 100 µA 0 0.2 V
VOH
High-level output voltage,
push-pull
(VIO_IN pin reference)
IOH = 1 mA VIO –
0.45 VIO V
IOH = 100 µA VIO – 0.2 VIO V
l TEXAS INSTRUMENTS
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Electrical Characteristics: Digital Output Signal Parameters (continued)
Over operating free-air temperature range, typical values are at TA= 27°C, VIO refers to the VIO_IN pin, VSYS to the VCC1
pin (unless otherwise noted)
PARAMETER TEST CONDITIONS MIN TYP MAX UNIT
GPIO_0, GPIO_3, GPIO_7
VOL Low-level output voltage,
open-drain
External pullup to VRTC, IOL = 2 mA 0 0.45 V
External pullup to VRTCIOL = 100 µA 0 0.2 V
Maximum supply for external
pullup resistor, open-drain 5.25 V
I2C1_SDA_SDI, I2C2_SDA_SDO
Low-level output voltage VOL
related to VIO (VIO_IN pin
reference) 3-mA sink current 0 0.1 ×
VIO 0.2 ×
VIO V
CB
Capacitive load for
I2C2_SDA_SDO
in SPI mode 20 pF
5.18 Electrical Characteristics: I/O Pullup and Pulldown Resistance
Over operating free-air temperature range, VIO refers to the VIO_IN pin, VSYS to refers to the VCC1 pin (unless otherwise
noted)
PARAMETER TEST CONDITIONS PULLUP
SUPPLY MIN TYP MAX UNIT
PWRON, RPWRON pullup resistance, fixed
pullup VSYS 55 120 370 kΩ
PWRDOWN pulldown resistance — 180 400 900 kΩ
BOOT1 pullup resistance VRTC 13.5 kΩ
GPIO_0 pulldown resistance — 180 400 900 kΩ
GPIO_1, GPIO_2 pullup resistance VSYS 170 400 950 kΩ
GPIO_1, GPIO_2 pulldown resistance — 170 400 950 kΩ
GPIO_3, RESET_IN pulldown resistance — 180 400 900 kΩ
GPIO_4, GPIO_6 pullup resistance VIO 170 400 950 kΩ
GPIO_4, GPIO_6 pulldown resistance — 170 400 950 kΩ
GPIO_5 pullup resistance VRTC 170 400 950 kΩ
GPIO_5 pulldown resistance — 170 400 950 kΩ
GPIO_7 or POWERHOLD pulldown
resistance — 180 400 900 kΩ
NSLEEP, ENABLE1 pullup resistance VRTC 170 400 950 kΩ
NSLEEP, ENABLE1 pulldown resistance — 170 400 950 kΩ
NRESWARM pullup resistance VRTC 78 120 225 kΩ
l TEXAS INSTRUMENTS
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(1) Specified by design. Not tested in production.
(2) All values referred to VIH(min) and VIH(max) levels.
(3) For bus line loads CBbetween 100 and 400pF, the timing parameters must be linearly interpolated.
(4) A device must internally provide a data hold time to bridge the undefined part between VIH and VIL of the falling edge of the SCLH
signal. An input circuit with a threshold as low as possible for the falling edge of the SCLH signal minimizes this hold time.
5.19 I2C Interface Timing Requirements
Over operating free-air temperature range(1)(2)(3)(4). For the timing diagram for fast and standard (F/S) modes, see Figure 5-1.
For the timing diagram for high-speed (HS) mode, see Figure 5-2.
MIN MAX UNIT
ƒ(SCL) SCL clock frequency
Standard mode 100 kHz
Fast mode 400 kHz
High-speed mode (write operation), CB– 100 pF max 3.4 MHz
High-speed mode (read operation), CB– 100 pF max 3.4 MHz
High-speed mode (write operation), CB– 400 pF max 1.7 MHz
High-speed mode (read operation), CB– 400 pF max 1.7 MHz
tBUF Bus free time between a STOP
and START condition
Standard mode 4.7 µs
Fast mode 1.3 µs
tHD, tSTA Hold time (REPEATED) START
condition
Standard mode 4 µs
Fast mode 600 ns
High-speed mode 160 ns
tLOW Low period of the SCL clock
Standard mode 4.7 µs
Fast mode 1.3 µs
High-speed mode, CB– 100 pF max 160 ns
High-speed mode, CB– 400 pF max 320 ns
tHIGH High period of the SCL clock
Standard mode 4 µs
Fast mode 600 ns
High-speed mode, CB– 100 pF max 60 ns
High-speed mode, CB– 400 pF max 120 ns
tSU, tSTA Setup time for a REPEATED
START condition
Standard mode 4.7 µs
Fast mode 600 ns
High-speed mode 160 ns
tSU, tDAT Data setup time
Standard mode 250 ns
Fast mode 100 ns
High-speed mode 10 ns
tHD, tDAT Data hold time
Standard mode 0 3.45 µs
Fast mode 0 0.9 µs
High-speed mode, CB– 100 pF max 0 70 ns
High-speed mode, CB– 400 pF max 0 150 ns
tRCL Rise time of the SCL signal
Standard mode 20 + 0.1
CB1000 ns
Fast mode 20 + 0.1
CB300 ns
High-speed mode, CB– 100 pF max 10 40 ns
High-speed mode, CB– 400 pF max 20 80 ns
tRCL1
Rise time of the SCL signal
after a REPEATED START
condition and after an
acknowledge bit
Standard mode 20 + 0.1
CB1000 ns
Fast mode 20 + 0.1
CB300 ns
High-speed mode, CB– 100 pF max 10 80 ns
High-speed mode, CB– 400 pF max 20 160 ns
l TEXAS INSTRUMENTS
SDA
SCL
tftftLOW tr
tsu;DAT
HIGH
SSr SP
thd;STA
thd;DAT
tsu;STA
thd;STA
tsu;STO
tr
tBUF
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I2C Interface Timing Requirements (continued)
Over operating free-air temperature range(1)(2)(3)(4). For the timing diagram for fast and standard (F/S) modes, see Figure 5-1.
For the timing diagram for high-speed (HS) mode, see Figure 5-2.
MIN MAX UNIT
tFCL Fall time of the SCL signal
Standard mode 20 + 0.1
CB300 ns
Fast mode 20 + 0.1
CB300 ns
High-speed mode, CB– 100 pF max 10 40 ns
High-speed mode, CB– 400 pF max 20 80 ns
tRDA Rise time of the SDA signal
Standard mode 20 + 0.1
CB1000 ns
Fast mode 20 + 0.1
CB300 ns
High-speed mode, CB– 100 pF max 10 80 ns
High-speed mode, CB– 400 pF max 20 160 ns
tFDA Fall time of the SDA signal
Standard mode 20 + 0.1
CB300 ns
Fast mode 20 + 0.1
CB300 ns
High-speed mode, CB– 100 pF max 10 80 ns
High-speed mode, CB– 400 pF max 20 160 ns
tSU, tSTO Setup time for a STOP
condition
Standard mode 4 µs
Fast mode 600 ns
High-speed mode 160 ns
5.20 SPI Timing Requirements
For the SPI timing diagram, see Figure 5-3.
MIN MAX UNIT
tcesu Chip-select setup time 30 ns
tcehld Chip-select hold time 30 ns
tckper Clock cycle time 67 100 ns
tckhigh Clock high typical pulse duration 20 ns
tcklow Clock low typical pulse duration 20 ns
tsisu Input data setup time, before clock active edge 5 ns
tsihld Input data hold time, after clock active edge 5 ns
tdr Data retention time 15 ns
tCE Time from CE going low to CE going high 67 ns
Figure 5-1. Serial Interface Timing Diagram for F/S Mode
XAS INSTRUMENTS TE *9 ff
SPI clock enable
SPI chip select
SPI data input
SPI data output
R/W Address Unused Data
Don’t care
tckhigh
tcklow
tcesu
tckper
tsisu tsihld
tcehld
tdr
SPI_Timing
SDA (HS)
SCL (HS)
tsu;STA thd;STA
thd;DAT
tsu;DAT
tsu;STO
trCL1
trCL
tLOW tHIGH See Note A
tfCL1
trCL1
See Note A tHIGH tLOW
trDA
tfDA
Sr Sr P
= MCS Current Source Pullup
= R(P) Resistor Pullup
Note A: First rising edge of the SCL (HS) signal after Sr and after each acknowledge bit.
34
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Figure 5-2. Serial Interface Timing Diagram For HS Mode
Figure 5-3. SPI Interface Timing Diagram
l TEXAS INSTRUMENTS mu mu mu mu 100 100
Load Current (mA)
Efficiency (%)
0 0.4 0.8 1.2 1.6 2 2.4 2.8 3.2 3.6 4 4.4 4.8
0
10
20
30
40
50
60
70
80
90
100
D006
VO = 0.7 V
VO = 1.2 V
VO = 1.8 V
VO = 2.5 V
VO = 3.3 V
Load Current (A)
Efficiency (%)
0 0.2 0.4 0.6 0.8 1
0
10
20
30
40
50
60
70
80
90
100
D005
VO = 1.05 V
VO = 1.2 V
VO = 1.8 V
VO = 2.5 V
VO = 3.3 V
Load Current (A)
Efficiency (%)
0 0.6 1.2 1.8 2.4 3 3.6 4.2 4.8 5.4 6
0
10
20
30
40
50
60
70
80
90
100
D008
VO = 1.05 V
VO = 1.2 V
Load Current (A)
Efficiency (%)
0 0.8 1.6 2.4 3.2 4 4.8 5.6 6.4 7.2 8 8.8
0
10
20
30
40
50
60
70
80
90
100
D007
VO = 1.05 V
VO = 1.2 V
Load Current (mA)
Efficiency (%)
0 0.4 0.8 1.2 1.6 2 2.4 2.8 3.2 3.6 4 4.4 4.8
0
10
20
30
40
50
60
70
80
90
100
D010
VO = 0.7 V
VO = 1.2 V
Load Current (A)
Efficiency (%)
0 0.4 0.8 1.2 1.6 2 2.4 2.8 3.2 3.6 4
0
10
20
30
40
50
60
70
80
90
100
D009
VO = 1.05 V
VO = 1.2 V
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5.21 Typical Characteristics
VI= 3.8 V ƒS= 2.2 MHz
Figure 5-4. SMPS Efficiency for Multi-Phase
ECO-mode
VI= 3.8 V ƒS= 2.2 MHz
Figure 5-5. SMPS Efficiency for 4-A Multi-Phase
PWM Mode
VI= 3.8 V ƒS= 2.2 MHz
Figure 5-6. SMPS Efficiency for 6-A Multi-Phase
PWM Mode
VI= 3.8 V ƒS= 2.2 MHz
Figure 5-7. SMPS Efficiency for 9-A Multi-Phase
PWM Mode
VI= 3.8 V ƒS= 2.2 MHz
Figure 5-8. SMPS Efficiency for 1-A Single-Phase
ECO-mode
VI= 3.8 V ƒS= 2.2 MHz
Figure 5-9. SMPS Efficiency for 1-A Single-Phase
PWM Mode
l TEXAS INSTRUMENTS mu mu mu mu
Load Current (mA)
Efficiency (%)
0 0.4 0.8 1.2 1.6 2 2.4 2.8 3.2 3.6 4 4.4 4.8
0
10
20
30
40
50
60
70
80
90
100
D002
VO = 0.7 V
VO = 1.2 V
VO = 1.8 V
VO = 2.5 V
VO = 3.3 V
Load Set (A)
Efficiency (%)
0 0.4 0.8 1.2 1.6 2 2.4 2.8
0
10
20
30
40
50
60
70
80
90
100
D001
VO = 1.05 V
VO = 1.2 V
VO = 1.8 V
VO = 2.5 V
VO = 3.3 V
Load Current (mA)
Efficiency (%)
0 0.4 0.8 1.2 1.6 2 2.4 2.8 3.2 3.6 4 4.4 4.8
0
10
20
30
40
50
60
70
80
90
100
D004
VO = 0.7 V
VO = 1.2 V
VO = 1.8 V
VO = 2.5 V
VO = 3.3 V
Load Current (A)
Efficiency (%)
0 0.2 0.4 0.6 0.8 1 1.2 1.4 1.6 1.8 2
0
10
20
30
40
50
60
70
80
90
100
D003
VO = 1.05 V
VO = 1.2 V
VO = 1.8 V
VO = 2.5 V
VO = 3.3 V
36
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Typical Characteristics (continued)
VI= 3.8 V ƒS= 2.2 MHz
Figure 5-10. SMPS Efficiency for 2-A Single-Phase
ECO-ode
VI= 3.8 V ƒS= 2.2 MHz
Figure 5-11. SMPS Efficiency for 2-A Single-Phase
PWM Mode
VI= 3.8 V ƒS= 2.2 MHz
Figure 5-12. SMPS Efficiency for 3-A Single-Phase
ECO-mode
VI= 3.8 V ƒS= 2.2 MHz
Figure 5-13. SMPS Efficiency for 3-A Single-Phase
PWM Mode
l TEXAS INSTRUMENTS
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Detailed DescriptionCopyright © 2013–2019, Texas Instruments Incorporated
6 Detailed Description
6.1 Overview
The TPS659038-Q1 and TPS659039-Q1 device are integrated power management integrated circuits
(PMIC), both available in a 169-pin, 0.8-mm pitch, 12-mm x 12-mm nFBGA package. They are designed
specifically for automotive applications. Both devices provide seven configurable step-down converter
rails, with the ability to combine power rails and supply up to 9 A of output current in multi-phase mode.
The TPS659038-Q1 device also provides eleven external LDOs, while the TPS659039-Q1 device provides
six external LDOs. Both devices also come with a 12-bit GPADC with three external channels, eight
configurable GPIOs, two I2C interface channels or one SPI interface channel, real-time clock module with
calendar function, PLL for external clock sync and phase delay capability, and programmable power
sequencer and control for supporting different processors and applications.
The seven step-down converter rails are consisting of nine high frequency switch mode converters with
integrated FETs. They are capable of synchronizing to an external clock input and supports switching
frequency between 1.7 MHz and 2.7 MHz. The SMPS12 and SMPS45 devices are dual-phase step-down
converters, which can combine with the SMPS3 or SMPS7 device respectively and become triple-phase
converters. In addition, the SMPS12, SMPS45, SMPS6, and SMPS8 device support dynamic voltage
scaling by a dedicated I2C interface for optimum power savings.
The TPS659038-Q1 device contains 11 LDO regulators while the TPS659039-Q1 device contains six LDO
regulators for external use. All of the LDOs support 0.9 V to 3.3 V output with 50-mV step. The devices
are fully controllable by the I2C interface and can be supplied from either a system supply or a
preregulated supply.
All LDOs and step-down converters can be controlled by the SPI or I2C interface, or by power request
signals. In addition, voltage scaling registers allow transitioning the SMPS to different voltages by SPI, I2C,
or roof and floor control.
The power-up and power-down controller is configurable and programmable through OTP. The
TPS65903x-Q1 devices include a 32-kHz RC oscillator to sequence all resources during power up and
power down. In cases where a fast start up is required, a 16-MHz crystal oscillator is also included to
quickly generate a stable 32-kHz for the system. The device also includes an RTC module which provides
date, time, calendar, and alarm capability, which is best utilized when a 16-MHz crystal or an external and
high accuracy 32-kHz clock is present.
Eight Configurable GPIOs with multiplexed feature are available on the TPS659038-Q1 and TPS659039-
Q1 devices. Three of the GPIOs, together with the REGEN1 pin can be configured and used as enable
signals for external resources, which can be included into the power-up and power-down sequence. Both
devices also include a general-purpose (GP) sigma-delta analog-to-digital converter (ADC) with three
external input channels, which can be used as thermal or voltage and current monitors.
CAUTION
When operating the TPS659038-Q1 and TPS659039-Q1 devices using silicon
revision 1.3 or earlier, without an external crystal, each SMPS regulating an
output voltage greater than 1.8 V must be disabled before VCC is removed.
Lowering VCC below the programmed VSYS_LO level while any SMPS is
regulating an output voltage above 1.8 V may cause damage to the device.
See Section 6.3.10 to identify the silicon version in the device.
l TEXAS INSTRUMENTS
SMPS1_IN
SMPS1_SW
SMPS1_GND
SMPS2_IN
SMPS2_SW
SMPS2_GND
SMPS3_IN
SMPS3_SW
SMPS3_FDBK
SMPS3_GND
SMPS4_IN
SMPS4_SW
SMPS4_5_FDBK
SMPS4_GND
SMPS5_IN
SMPS5_SW
SMPS5_GND
INT
BOOT0
BOOT1
PWRON
RPWRON
GPIO_1
GPIO_2
RESET_IN
OSC16MIN
OSC16MOUT
CLK32KGO
GPADC_IN0
GPADC_IN1
GPADC_IN2
GPADC_VREF
RC
32 kHz
Internal
RC
oscillator
Output
buffers
16-MHz
oscillator
12-bit
SD-ADC
Multiplexer
LDOVANA_OUT
LDOVANA
LDOVRTC_OUT
LDOVRTC
Registers
Programmable power
sequencer controller
ECO
PWM
DVS
Switch ON or OFF
RTC
Interrupt handler (24 channels)
Thermal
monitoring
SMPS6_IN
SMPS6_SW
SMPS6_FDBK
SMPS6_GND
SMPS3
3 A
[Multi or
Stand-
alone]
SMPS4
2 A
(DVS)
[Master]
SMPS5
2 A
(DVS)
[Slave]
SMPS6
2 A
SMPS7_IN
SMPS7_SW
SMPS7_FDBK
SMPS7_GND
SMPS7
2 A
SMPS8_IN
SMPS8_SW
SMPS8_FDBK
SMPS8_GND
SMPS8
1 A
SMPS9_IN
SMPS9_SW
SMPS9_FDBK
SMPS9_GND
SMPS9
1 A
SMPS4_5_FDBK_GND
I2C1_SDA_SDI
PWRDOWN
NRESWARM
I2C1_SCL_CLK
I2C2_SDA_SDO
I2C2_SCL_SCE
RESET_OUT
Thermal shutdown
Hot die detection
(DVS)
(DVS)
OTP controller
OTP memory
DFT
WDT
JTAG
I2C CNTL,
I2C DVS
or SPI
POWERGOOD
OSC16MCAP
VCC1
VSYS_LO
VSYS_MON
POR
SMPS1
3 A
(DVS)
[Slave]
SMPS2
3 A
(DVS)
[Master] SMPS1_2_FDBK_GND
EN
VSEL
RAMP
EN
VSEL
ENABLE1
NSLEEP SMPS1_2_FDBK
GPIO_0
GPIO_3
GPIO_4
GPIO_5
GPIO_6
GPIO_7
REGEN1
POWERHOLD
SYSEN2
SYSEN1
TPS659038-Q1
GPIO
VCC1
REGEN2
VBUSDET
VCC_SENSE
Dual-
phases
Triple-
phases
Dual-
phases
Control
inputs
Internal
interrupt
events
Control
outputs
SYNCDCDC
VBUS_SENSE
VBUS_WKUP
TESTV
VIO_IN
VPROG
Test and program
VCC_SENSE2
PwrMgmt
VIO_GND
VCC_SENSE
VCC1
VPROG
VCC internal supply
VBUS
CLK32KGO1V8
Triple-
phases
[Multi or
Stand-
alone]
TPS659039-Q1
VBG
REFGND1 Reference
and
bias
Grounds
PBKG
GND_ANA
GND_DIG
GND_ANA
GND_ANA
GND_ANA
GND_ANA
LDO2_OUT
LDO3_OUT
LDO4_OUT
LDO5_OUT
LDO6_IN
LDO6_OUT
LDO7_OUT
LDO1
300 mA
LDO1_OUT
LDOLN_IN
LDOLN_OUT
LDO8_OUT
LDO9_IN
LDO9_OUT
LDO2
300 mA LDO3
300 mA LDO4(1)
300 mA LDO5(1)
200 mA LDO6(1)
200 mA LDO7(1)
2
LDO8(1)
170 mA
LDO9
50 mA
SDIO
LDOUSB
1
LDOUSB_IN2
LDOLN
50 mA
LDOUSB_OUT
VSEL
EN
VSEL
EN
VSEL
EN
VSEL
EN
VSEL
EN
VSEL
EN
VSEL
EN
VSEL
EN
VSEL
EN
VSEL
EN
VSEL
EN
Bypass
LDO12_IN
LDO34_IN
LDO58_IN
LDO7_LDO
USB_IN
00 mA
00 mA
VCC1
EN
VSEL
RAMP
EN
VSEL
RAMP
EN
VSEL
RAMP
EN
VSEL
EN
VSEL
38
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Detailed Description Copyright © 2013–2019, Texas Instruments Incorporated
6.2 Functional Block Diagrams
(1) Only available on the TPS659038-Q1 device.
Figure 6-1. Functional Block Diagram of TPS659038-Q1 and TPS659039-Q1
l TEXAS INSTRUMENTS
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Detailed DescriptionCopyright © 2013–2019, Texas Instruments Incorporated
6.3 Feature Description
6.3.1 Power Management
The TPS65903x-Q1 device series integrates an embedded power controller (EPC) that fully manages the
state of the device during power transitions. According to four defined types of requests (ON, OFF, WAKE,
and SLEEP), the EPC executes one of the five predefined power sequences (OFF2ACT, ACT2OFF,
SLP2OFF, ACT2SLP, and SLP2ACT) to control the state of the device resources. Any resource can be
included in any power sequence. When a resource is not controlled or configured through a power
sequence, the resource remains in the default state of the resource (from OTP).
Each resource is configured only through register bits. Therefore, a resource can be controlled statically
by the user through the control interfaces (I2C or SPI) or controlled automatically by the EPC during power
transitions (predefined sequences of registers accesses).
The EPC is powered by an internal LDO which is automatically enabled when VSYS is available to the
device. It is important to ensure that VSYS (which is connected to VCC1, VCC_SENSE, and may also be
connected to SMPSx_In and LODx_IN as suggested in the device block diagram) is the first supply
available to the device to guarantee proper operation of all the power resources provided by the device. It
is also important that VSYS is stable prior to VIO supply is available to ensure proper operation of the
control interface and device IOs.
6.3.2 Power Resources (Step-Down and Step-Up SMPS Regulators, LDOs)
The power resources provided by the TPS659038-Q1 and TPS659039-Q1 devices include inductor-based
SMPSs and linear low-dropout voltage regulators (LDOs). These supply resources provide the required
power to the external processor cores, external components, and to modules embedded in the devices.
Table 6-1 lists the power sources provided by the TPS65903x-Q1 devices.
Table 6-1. Power Sources
RESOURCE TYPE VOLTAGE CURRENT COMMENTS
SMPS1, SMPS2,
and SMPS3 SMPS 0.5 to 1.65 V, 10-mV steps
1 to 3.3 V, 20-mV steps 9 A Can be used as one triple-phase regulator (9 A)
or one dual-phase (6 A) and single-phase (3 A)
regulators
SMPS4, SMPS5,
and SMPS7 SMPS 0.5 to 1.65 V, 10-mV steps
1 to 3.3 V, 20-mV steps 6 A Can be used as one triple-phase regulator (6 A)
or one dual-phase (4 A) and single-phase (2 A)
regulators
SMPS6 SMPS 0.5 to 1.65 V, 10-mV steps
1 to 3.3 V, 20-mV steps 2 A or 3 A Can be configured as 2-A or 3-A SMPS through
OTP programming
SMPS8 SMPS 0.5 to 1.65 V, 10-mV steps
1 to 3.3 V, 20-mV steps 1 A
SMPS9 SMPS 0.5 to 1.65 V, 10-mV steps
1 to 3.3 V, 20-mV steps 1 A
LDO1 LDO 0.9 to 3.3 V, 50-mV steps 300 mA
LDO2 LDO 0.9 to 3.3 V, 50-mV steps 300 mA
LDO3 LDO 0.9 to 3.3 V, 50-mV steps 300 mA
LDO4 LDO 0.9 to 3.3 V, 50-mV steps 300 mA
LDO5 LDO 0.9 to 3.3 V, 50-mV steps 200 mA
LDO6 LDO 0.9 to 3.3 V, 50-mV steps 200 mA
LDO7 LDO 0.9 to 3.3 V, 50-mV steps 200 mA
LDO8 LDO 0.9 to 3.3 V, 50-mV steps 200 mA
LDO9 LDO 0.9 to 3.3 V, 50-mV steps 50 mA
LDOLN LDO 0.9 to 3.3 V, 50-mV steps 50 mA
LDOUSB LDO 0.9 to 3.3 V, 50-mV steps 100 mA
l TEXAS INSTRUMENTS
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6.3.2.1 Step-Down Regulators
The synchronous step-down converter used in the power-management core has high efficiency while
enabling operation with small and cost-competitive external components. The SMPSx_IN supply terminals
of all the converters can be individually connected to the VSYS supply (VCC1 terminal). Four of these
configurable step-down converters are multi-phased to create up to 4-A and 6-A rails, while another
converter can be combined to these 2 rails to create 2 rails up to 9 A and 6A of output current. All of the
step-down converters can synchronize to an external clock source between 1.7 Mhz and 2.7 MHz, or an
internal fall back clock at 2.2 MHz.
The step-down converter supports two operating modes, which can be selected independently:
Forced PWM mode: In forced PWM mode, the device avoids pulse skipping and allows easy filtering of
the switch noise by external filter components. The drawback is the higher IDDQ at low
output current levels.
ECO-mode (lowest quiescent current mode): Each step-down converter can be individually controlled
to enter a low quiescent current mode. In ECO-mode, the quiescent current is reduced and
the output voltage is supervised by a comparator while most parts of the control are disabled
to save power. The regulators should not be enabled under ECO-mode in order to ensure
the stability of the output. ECO-mode should be enabled only when a converter has less
than 5 mA of load current and VOcan remain constant. In addition, ECO-mode should be
disabled before a load transient step to let the converter respond in a timely manner to the
excess current draw. To ensure proper operation of the converter while it is in ECO-mode,
the output voltage level must be less then 70% of the input supply voltage level. If the VOof
the converter is greater than 2.8V, a safety feature of the device will monitor the supply
voltage of the converter, and automatically shut down the converter if the input voltage falls
below 4V. The purpose of this safety mechanism is to prevent damage to the converter due
to design limitation while the converter is in ECO mode.
In addition to the operating modes, the following parameters can be selected for the regulators:
Powergood: The POWERGOOD signal high indicates that all SMPS outputs are within 10% (typical
case) of the programmed value. The individual power good signal of a switching regulator is
blanked when the regulator is disabled or when the regulator voltage transitions from one set
point to another.
Output discharge: Each switching regulator is equipped with an output discharge enable bit. When this
bit is set to 1, the output of the regulator is discharged to ground with the equivalent of a 9-Ω
resistor when the regulator is disabled. If the regulator enable bit is set, the discharge bit of
the regulator is ignored.
Output current monitoring: GPADC can monitor the SMPS output current. One SMPS at a time can be
selected for measurement from the following: SMPS12, SMPS3, SMPS123, SMPS45,
SMPS457, SMPS6 and SMPS7. Selection is controlled through the GPADC_SMPS
_ILMONITOR_EN register.
Step-down converter ENABLE: The step-down converter enable and disable is part of the flexible
power-up and power-down state-machine. Each converter can be programmed so that it is
powered up automatically to a preselected voltage in one of the time slots after a power-on
condition occurs. Alternatively, each SMPS can be controlled by a dedicated terminal.
Terminals NSLEEP and ENABLE1 can be mapped to any resource (LDOs, SMPS converter,
32-kHz clock output or GPIO) to enable or disable it. Each SMPS can also be enabled and
disabled through I2C register access.
b TEXAS INSTRUMENTS
fSYNC, MIN
fSYNC, MAX
MDITHER
fSYNC
t
ADITHER
TDITHER
41
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6.3.2.1.1 Sync Clock Functionality
The TPS65903x-Q1 device contains a SYNCDCDC input to sync DC-DCs with the external clock.
In forced PWM mode, SMPSs are synchronized on an external input clock (SYNCDCDC) whereas in
ECO-mode, or if the SYNCDCDC pin is grounded, the switching frequency is based on an internal RC
oscillator. The clock generated from the internal RC oscillator can be output through GPIO5 to provide
synchronization clock to external SMPSs. For PWM mode, a PLL is present to buffer the external input
clock to create nine clock signals for the nine SMPSs with different phases.
The sync clock dither specification parameters are based on a triangular dither pattern, but other patterns
that comply with the minimum and maximum sync frequency range and the maximum dither slope can
also be used.
Figure 6-2. Sync Clock Range and Dither
The ollowing figure shows ƒSYNC, the frequency of SYNCDCDC input clock and ƒS, the frequency of PLL
output signal.
When there is no clock present on SYNCDCDC ball, the PLL generates a clock with a frequency equal to
ƒFALLBACK.
If a clock is present on SYNCDCDC ball with a frequency between ƒSAT,LO and ƒSAT,HI, then the PLL is
synchronised on SYNCDCDC clock and generates a clock with frequency equal to fSYNC.
If ƒSYNC is higher than ƒSAT,HI, then the PLL generates a clock with a frequency equal to ƒSAT,HI.
If fSYNC is smaller than ƒSAT,LO, then the PLL generates a clock with a frequency equal to ƒSAT,LO.
{L} TEXAS INSTRUMENTS N0 Clock 05
FS
L OS
12
I GPADC code
I I
2 1
u
No Clock
fSAT, LO
fSAT, LO
fSYNC
fSW
fA
fA
fSAT, HI
fFALLBACK
fSAT, HI
tSETTLE
tSETTLE
42
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Figure 6-3. Sync Clock Saturation and Frequency Fallback
6.3.2.1.2 Output Voltage and Mode Selection
The default output voltage and enabling of the regulator during startup sequence is defined by OTP bits.
After start-up the software can change the output voltage with the RANGE and VSEL bits in the
SMPSx_VOLTAGE register. The value 0x0 disables the SMPS (OFF).
The operating mode of an SMPSx when the TPS65903x-Q1 device is in ACTIVE mode can be selected in
SMPSx_CTRL register with MODE_ACTIVE[1:0].
The operating mode of an SMPSx when the TPS65903x-Q1 device is in SLEEP mode is controlled by
MODE_SLEEP[1:0] bit depending on SMPS assignment to NSLEEP and ENABLE1, see Table 6-13.
Soft-start slew rate is fixed (Tramp).
The pulldown discharge resistance for OFF mode is enabled and disabled in the SMPS_PD_CTRL
register. By default, discharge is enabled.
SMPS behavior for warm reset (reload default values or keep current values) is defined by the
SMPSx_CTRL.WR_S bit.
6.3.2.1.3 Current Monitoring and Short Circuit Detection
The step-down converters include several other features.
The SMPS sink current limitation is controlled with the SMPS_NEGATIVE_CURRENT_LIMIT_EN register.
The limitation is enabled by default.
Channel 11 of the GPADC can be used to monitor the output current of SMPS12, SMPS3, SMPS123,
SMPS45, SMPS457, SMPS6, or SMPS7. Load current monitoring is enabled for a given SMPS in the
SMPS_ILMONITOR_EN register. SMPS output power monitoring is intended to be used during the steady
state of the output voltage, and is supported in PWM mode only.
Use Equation 1 as the basic equation for the SMPS output current result.
where
• IFS = IFS0 × K (K is the number of active SMPS phases)
• IOS = IOS0 × K (K is the number of active SMPS phases) (1)
l TEXAS INSTRUMENTS 'L a 1]
 
FS
L OS
12
I GPADC code
I I
2 1 1 TC_R0 Temperature 25
u
ª º ª º
 u  u
¬ ¼
¬ ¼
43
TPS659038-Q1, TPS659039-Q1
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Use Equation 2 to calculate the temperature compensated result.
(2)
For values of IFS0 and IOS0, see Section 5.12.
The SMPS thermal monitoring is enabled (default) and disabled with the SMPS_THERMAL_EN register.
When enabled, the SMPS thermal status is available in the SMPS_THERMAL_STATUS register. SMPS12
and SMPS3 have shared thermal protection, in effect, if SMSP12 triggers the thermal protection, then
SMPS3 operating in stand-alone mode is disabled. There is no dedicated thermal protection in SMPS8 or
SMPS9.
Each SMPS has a detection for load current above ILIM, indicating overcurrent or shorted SMPS output. A
register SMPS_SHORT_STATUS indicates any SMPS short condition. Depending on the interrupt short
line mask bit register (INT2_MASK.SHORT), an interrupt is generated upon any shorted SMPS. If a short
situation occurs on any enabled SMPSs, the corresponding short status bit is set in the
SMPS_SHORT_STATUS register. A switch-off signal is then sent to the corresponding SMPS, and the
SMPS remains off until the corresponding bit in the SMPS_SHORT_STATUS register is cleared. The
SMPS_SHORT_STATUS register is cleared when read, or by issuing a POR. The same behavior applies
to LDO shorts using the LDO_SHORT_STATUS registers.
A short must occur on any enabled SMPS or LDO for at least 155 us to 185 us for the short detection to
shut off the rail. During startup of the device, there is a 2 ms counter that masks any short-circuit
shutdown. This counter starts when the device is enabled and the counter is reset when any SMPSx or
LDOx rail becomes ACTIVE. When no rail has been enabled for 2 ms, the counter reaches its threshold
and the short-circuit shutdown is no longer masked for the enabled SMPSs and LDOs.
6.3.2.1.4 POWERGOOD
The external POWERGOOD terminal indicates if the outputs of the SMPS are correct or not (Figure 6-4).
Either voltage and current monitoring or a current monitoring only can be selected for POWERGOOD
indication. This selection is common for all SMPSs in the SMPS_POWERGOOD_MASK2
.POWERGOOD_TYPE_SELECT bit register. When both voltage and current are monitored,
POWERGOOD signal active (polarity is programmable) indicates that all SMPS outputs are within certain
percentage, VSMPSPG, of the programmed value and that load current is below ILIM.
All POWERGOOD sources can be masked in the SMPS_POWERGOOD_MASK1 and
SMPS_POWERGOOD_MASK2 registers. By default, only the SMPS12 rail (or SMPS123 rail if in triple
phase) is monitored. When an SMPS is disabled, it should be masked to prevent it forcing POWERGOOD
inactive. When SMPS voltage is transitioning from one target voltage to another due to DVS command,
voltage monitoring is internally masked and POWERGOOD is not impacted.
It is also possible to include in POWERGOOD the GPADC result for SMPS output current monitoring by
setting SMPS_COMPMODE = 1. Only one SMPS can be monitored by the GPADC channel at the time.
The POWERGOOD function can also be used for monitoring an external SMPS is at the correct output
level and the load is lower than the current limit; indication is through the GPIO_7 terminal.
All POWERGOOD sources can be masked in SMPS_POWERGOOD_MASK1 and
SMPS_POWERGOOD_MASK2 registers.
l TEXAS INSTRUMENTS sws powzmoop MAsKmI
OVER_TEMP
SMPS_SHORT_STATUS
SMPS_THERMAL_STATUS
INT2_MASK[6]
INT
ILIM
OVER_TEMP
SMPS12
SMPS3
SMPS_POWERGOOD_MASK1[0]
SMPS3
SMPS_POWERGOOD_MASK1[1]
SMPS_POWERGOOD_MASK1[7]
SMPS_POWERGOOD_MASK2[2]
POWERGOOD
External SMPS (trrough GPIO7)
POWERGOOD
44
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CAUTION
The current monitor on multi-phase rails (such as SMPS12, SMPS123, or
SMPS45) may cause POWERGOOD to change to a low level (with default
polarity) when transitioning from multi-phase operation to single phase
operation. TI recommends masking the multi-phase rails as a POWERGOOD
source, using SMPS_POWERGOOD_MASK1, or debouncing the
POWERGOOD signal if this POWERGOOD toggle is not desired in the
application design.
Figure 6-4. POWERGOOD Block Diagram
6.3.2.1.5 DVS-Capable Regulators
The step-down converters SMPS12 or SMPS123, SMPS45 or SMPS457, SMPS6, and SMPS8 are DVS-
capable and have some additional parameters for control. The slew rate of the output voltage during
voltage level change is fixed at 2.5 mV/µs. The control for two different voltage levels (ROOF and FLOOR)
with the NSLEEP and ENABLE1 signals is available. When the ROOF_FLOOR control is not used, two
different voltage levels can be selected with the CMD bit in the SMPSx_FORCE register.
• The output voltage slew rate for achieving new output voltage value is fixed at 2.5 mV/μs.
• The NSLEEP and ENABLE1 terminals can be used for roof-floor control of SMPS. For roof-floor
operation sets the SMPSx_CTRL.ROOF_FLOOR_EN register, and assign SMPS to NSLEEP and
ENABLE1 in the NSLEEP_SMPS_ASSIGN and ENABLE1_SMPS_ASSIGN registers. When the
controlling terminal is active, the SMPS output value is defined by the SMPSx_VOLTAGE register.
When the controlling terminal is not active, the SMPS output value is defined by the SMPSx_FORCE
register.
l TEXAS INSTRUMENTS Voltage controlmlaugh \‘C SMPS' CTRL ROOF FLOOR EN: \, ___________________ down) X X Voltage control through extema‘ gm SMPS' CTRL ROOF FLOOR EN= down)
Voltage control through I C (SMPS*_CTRL.ROOF_FLOOR_EN=0)
2
SMPS*_VOLTAGE.VSEL, when SMPS*_FORCE.CMD=1 SMPS*_FORCE.VSEL, when SMPS*_FORCE.CMD=0
SMPS*_OUT
SMPS*_VOLTAGE.VSEL
Tstart
Discharge control (pull-down)
SMPS_PD_CTRL.SMPS*
(disabled or enabled)
I2C
Voltage control through external pin (SMPS*_CTRL.ROOF_FLOOR_EN=1)
SMPS*_OUT
SMPS*_VOLTAGE.VSEL (ACTIVE mode)
SMPS*_VOLTAGE.VSEL
SMPS*_FORCE.VSEL (SLEEP mode)
Discharge control (pull-down)
SMPS_PD_CTRL.SMPS*
(disabled or enabled)
EN
EN: Control through NSLEEP or ENABLE1 (see Resources SLEEP or ACTIVE assignments table)
VSEL[6:0] (voltage selection): OFF, 0.5 V - 1.65 V in 10-mV steps if SMPS*_VOLTAGE.RANGE = 0; 1 - 3.3 V in 20-mV steps
if SMPS*_VOLTAGE.RANGE = 1
I C: Control through access to SMPS*_VOLTAGE, SMPS*_FORCE registers
2
Tstart
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• Set the second value for the output voltage with the SMPSx_FORCE.VSEL register. A value of 0x0
disables the SMPS (OFF).
• Select which register, SMPSx_VOLTAGE or SMPSx_FORCE, to use with the SMPSx_FORCE.CMD
bit. The default is the voltage setting of SMPSx_VOLTAGE. For the CMD bit to work, ensure that
SMPSx_CTRL.ROOF_FLOOR_EN = 0.
Figure 6-5 shows the SMPS controls for DVS.
Figure 6-5. DVS – SMPS Controls
6.3.2.1.6 Non DVS-Capable Regulators
SMPS3 and SMPS7, when they are not part of the multi-phase configuration, will work as single phase
step down converters. Together with SMPS9, these are non-DVS-Capable regulators. The output voltage
slew rate is not controlled internally, and the converter will achieve the new output voltage in JUMP mode.
It is recommended that when changes to output voltage is necessary while SMPS3, SMPS7, or SMPS9
are configured as single phase converters, that the changes to their output voltages are programmed at a
rate which is slower than 2.5 mV/μs to avoid voltage overshoot or undershoot.
6.3.2.1.7 Step-Down Converters SMPS12 and SMPS123
The step-down converters SMPS1, SMPS2, and SMPS3 can be used in two different configurations:
• SMPS12 in dual-phase configuration supporting 6-A load current and SMPS3 in single-phase
configuration supporting 3-A load current
• SMPS123 in triple-phase configuration supporting 9-A load current
l TEXAS INSTRUMENTS
VSYS
SMPS1_SW
SMPS1_IN (SMPS5_IN)
SMPS1_GND
L2 (L7)
C11, C13
(C20, C24)
C10 (C23)
SMPS1
(SMPS5)
[Slave]
VSYS
SMPS2_SW
SMPS2_IN (SMPS4_IN)
SMPS2_GND (SMPS4_GND)
SMPS1_2_FDBK (SMPS4_5_FDBK)
SMPS1_2_FDBK_GND (SMPS4_5_FDBK_GND)
SMPS2
(SMPS4)
[Master]
VSYS
SMPS3_SW
SMPS3_IN (SMPS7_IN)
SMPS3_GND (SMPS7_GND)
SMPS3_FDBK (SMPS7_FDBK)
SMPS3
(SMPS7)
[Stand-
alone]
Vapps1
Vapps2
(SMPS5_SW)
(SMPS5_GND)
(SMPS4_SW)
(SMPS7_SW)
L3 (L6)
L4 (L9)
C12 (C19)
C14 (C27)
C16 (C28)
VSYS
SMPS1
(SMPS5)
[Slave]
VSYS
SMPS2
(SMPS4)
[Master]
VSYS
SMPS3
(SMPS7)
[Multi]
Vapps1
SMPS1_SW
SMPS1_IN (SMPS5_IN)
SMPS1_GND
(SMPS5_SW)
(SMPS5_GND)
SMPS2_SW
SMPS2_IN (SMPS4_IN)
SMPS2_GND (SMPS4_GND)
SMPS1_2_FDBK (SMPS4_5_FDBK)
SMPS1_2_FDBK_GND (SMPS4_5_FDBK_GND)
(SMPS4_SW)
SMPS3_SW
SMPS3_IN (SMPS7_IN)
SMPS3_GND (SMPS7_GND)
SMPS3_FDBK (SMPS7_FDBK)
(floating)
(SMPS7_SW)
C10 (C23)
L2 (L7)
C12 (C19)
L3 (L6)
C14 (C27)
L4 (L9)
C11, C13, C16
(C20, C24, C28)
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SMPS1 and SMPS2 cannot be used as separate converters. In dual-phase configuration the two
interleaved synchronous buck regulator phases with built-in current sharing operate in opposite phase. In
triple-phase configuration the three interleaved synchronous buck regulator phases with built-in current
sharing operate 120° out of phase. For light loads, the converter automatically changes to 1-phase
operation.
Figure 6-6 shows the connections for dual-phase and triple-phase configurations.
a. Dual-Phase SMPS and Stand-Alone SMPS b. Triple Phase SMPS
Figure 6-6. Multi-Phase SMPS Connectivity
To use the SMPS123 or SMPS12 and SMPS3 in the system:
• OTP defines dual-phase (SMPS12) operation, single-phase (SMPS3) operation, or triple-phase
(SMPS123) operation. If SMPS123 mode is selected, the SMPS12 registers control SMPS123.
• By default SMPS123 and SMPS12 operate in multiphase mode for higher load currents and switch
automatically to single-phase mode for low load currents. Forcing multiphase operation or single-phase
operation by setting the SMPS_CTRL.SMPS123_PHASE_CTRL[1:0] bits when the SMPS123 or
SMPS12 are loaded is also possible. Under no-load condition, do not force the multiphase operation,
as this causes the SMPS to exhibit instability.
6.3.2.1.8 Step-Down Converter SMPS45 and SMPS457
The step-down converters SMPS4, SMPS5 and SMPS7 can be used in two different configurations:
• SMPS45 in dual-phase configuration supporting 4-A load current and SMPS7 in single-phase
configuration supporting 2-A load current
• SMPS457 in triple-phase configuration supporting 6-A load current
SMPS4 and SMPS5 cannot be used as separate converters. In dual-phase configuration the two
interleaved synchronous buck regulator phases with built-in current sharing operate in opposite phase. In
triple-phase configuration the three interleaved synchronous buck regulator phases with built-in current
sharing operate 120° out of phase. For light loads, the converter automatically changes to 1-phase
operation.
To use SMPS457 or SMPS45 and SMPS7 in the system:
l TEXAS INSTRUMENTS
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Detailed DescriptionCopyright © 2013–2019, Texas Instruments Incorporated
• OTP defines dual-phase (SMPS45) operation, single-phase (SMPS7) operation, or triple-phase
(SMPS457) operation. If SMPS457 mode is selected, the SMPS45 registers control SMPS457.
• By default SMPS457 and SMPS45 operate in multiphase mode for higher load currents and switch
automatically to single-phase mode for low load currents. Forcing multiphase operation or single-phase
operation by setting the SMPS_CTRL.SMPS457_PHASE_CTRL[1:0] bits when the SMPS457 or
SMPS45 are loaded is also possible. Under no-load condition, do not force the multiphase operation,
as this causes the SMPS to exhibit instability.
6.3.2.1.9 Step-Down Converters SMPS3, SMPS6, SMPS7, SMPS8, and SMPS9
The SMPS3 is a buck converter supporting up to a 3-A load current, SMPS6 and SMPS7 are buck
converters supporting up to a 2-A load current. The SMPS6 can support up to 3 A if programmed in OTP
for boosted current mode. Using extended current mode increases SMPS6 current limits so to protect
external coil from damage, coil should be selected according to the higher current rating.
SMPS8 and SMPS9 are buck converters supporting up to a 1-A load current. SMPS6 and SMPS8 are
DVS-capable.
6.3.2.2 LDOs – Low Dropout Regulators
All LDOs are integrated so that they can be connected to a system supply, to an external buck boost
SMPS, or to another preregulated voltage source. The output voltages of all LDOs can be selected,
regardless of the LDO input voltage level VI. There is no hardware protection to prevent software from
selecting an improper output voltage if the VIminimum level is lower than TDCOV (total DC output voltage)
+ DV (dropout voltage). In such conditions, the output voltage would be lower and nearly equal to the input
supply. The regulator output voltage cannot be modified on the fly from one (0.9–2.1 V) voltage range to
the other (2.2–3.3 V) voltage range and vice versa. The regulator must be restarted in these cases. If an
LDO is not needed, the external components can be unplaced. The TPS65903x-Q1 devices are not
damaged by such configuration, and the other functions do not depend on the unused LDOs and work
properly.
6.3.2.2.1 LDOVANA
The VANA voltage regulator is dedicated to supply the analog functions of the TPS65903x-Q1 devices,
such as the GPADC and other analog circuits. VANA is automatically enabled and disabled when it is
needed. The automatic control optimizes the overall SLEEP state current consumption.
6.3.2.2.2 LDOVRTC
The VRTC regulator supplies always-on functions, such as real-time clock (RTC) and wake-up functions.
This power resource is active as soon as a valid energy source is present.
This resource has two modes:
• Normal mode is able to supply all digital parts of the TPS65903x-Q1 devices
• Backup mode is able to supply only always-on parts
VRTC supplies the digital part of TPS65903x-Q1 devices. In the BACKUP state, the VRTC regulator is in
low-power mode and the digital activity is reduced to the RTC parts only and maintained in retention
registers of the backup domain. The rest of the digital is under reset and the clocks are gated. In the OFF
state, the turn-on events and detection mechanism are also added to the previous RTC current load. In
the BACKUP and OFF states, the external load on VRTC should not exceed 0.5 mA. In the ACTIVE state,
VRTC switches automatically into ACTIVE mode. The reset is released and the clocks are available. In
SLEEP state, VRTC is kept active. The reset is released and only the 32-kHz clock is available. To reduce
power consumption, low-power mode can be selected by software.
l TEXAS INSTRUMENTS
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Detailed Description Copyright © 2013–2019, Texas Instruments Incorporated
NOTE
For silicon revision 1.3 or earlier, if VCC is discharged rapidly and then resupplied, a POR
may not be reliably generated. In this case a pulldown resistor can be added on the
LDOVRTC output. See Section 6.4.11 for details. See Section 6.3.10 to identify the silicon
version in the device.
6.3.2.2.3 LDO Bypass (LDO9)
LDO9 has a bypass capability to connect the input voltage to the output. It allows switching between 1.8 V
and the preregulated supply.
6.3.2.2.4 LDOUSB
This LDOUSB has two inputs, LDOUSB_IN1 and LDOUSB_IN2. LDOUSB_IN1 is shared with LDO7_IN.
The input selection occurs by the LDOUSB_ON_VBUS_VSYS bit in the LDO_CTRL register.
6.3.2.2.5 Other LDOs
All the other LDOs have the same output voltage capability, from 0.9 to 3.3 V in 50-mV steps. All the LDO
inputs can be independently connected into system voltage or into preregulated supply. The preregulated
supply can be higher or lower than the system supply.
6.3.3 Long-Press Key Detection
The TPS65903x-Q1 device can detect a long press on the PWRON terminal. Upon detection, the device
generates a LONG_PRESS_KEY interrupt and then switches the system off. The key-press duration is
configured through the LONG_PRESS_KEY.LPK_TIME bits.
The interrupt clear has two behaviors based on the configuration of the LONG_PRESS_KEY
.LPK_INT_CLR bit:
• LONG_PRESS_KEY.LPK_INT_CLR = 0: If PWRON remains low and the interrupt is cleared, the
switch-off sequence is cancelled. If PWRON remains low and the interrupt is not cleared, the switch-off
sequence is executed.
• LONG_PRESS_KEY.LPK_INT_CLR = 1: Switch off cannot be cancelled as long as PWRON remains
low (default).
6.3.4 RTC
6.3.4.1 General Description
The RTC is driven by the 32-kHz oscillator and it provides the alarm and time-keeping functions.
The main functions of the RTC block are:
• Time information (seconds, minutes, hours) in binary-coded decimal (BCD) code
• Calendar information (day, month, year, day of the week) in BCD code up to year 2099
• Programmable interrupts generation; the RTC can generate two interrupts:
– Timer interrupts periodically (1-second, 1-minute, 1-hour, or 1-day periods), which can be masked
during the SLEEP state to prevent the host processor from waking up
– Alarm interrupt at a precise time of the day (alarm function)
• Oscillator frequency calibration and time correction with 1/32768 resolution
Figure 6-7 shows the RTC block diagram.
l TEXAS INSTRUMENTS \—> \NT ‘HMEH
32-kHz
counter Frequency
compensation ControlWeek days
32-kHz
clock input
Months YearsDaysMinutes HoursSeconds
Interrupt Alarm INT_ALARM
INT_TIMER
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Figure 6-7. RTC Block Diagram
6.3.4.2 Time Calendar Registers
All the time and calendar information is available in the time calendar (TC) dedicated registers:
SECONDS_REG, MINUTES_REG, HOURS_REG, DAYS_REG, WEEKS_REG, MONTHS_REG, and
YEARS_REG. The TC register values are written in BCD code.
• Year data ranges from 00 to 99.
– Leap Year = Year divisible by four (2000, 2004, 2008, 2012, and so on)
– Common Year = Other years
• Month data ranges from 01 to 12.
• Day value ranges:
– 1 to 31 when months are 1, 3, 5, 7, 8, 10, 12
– 1 to 30 when months are 4, 6, 9, 11
– 1 to 29 when month is 2 and year is a leap year
– 1 to 28 when month is 2 and year is a common year
• Week value ranges from 0 to 6.
• Hour value ranges from 0 to 23 in 24-hour mode and ranges from 1 to 12 in AM or PM mode.
• Minutes value ranges from 0 to 59.
• Seconds value ranges from 0 to 59.
Example: Time is 10H54M36S PM (PM_AM mode set), 2008 September 5; previous registers values are
listed in Table 6-2:
Table 6-2. RTC Time Calendar Registers Example
REGISTER CONTENT
SECONDS_REG 0x36
MINTURES_REG 0x54
HOURS_REG 0x10
DAYS_REG 0x05
MONTHS_REG 0x09
YEARS_REG 0x08
l TEXAS INSTRUMENTS
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The user can round to the closest minute, by setting the ROUND_30S register bit in the RTC_CTRL_REG
register. TC values are set to the closest minute value at the next second. The ROUND_30S bit is
automatically cleared when the rounding time is performed.
Example:
• If current time is 10H59M45S, round operation changes time to 11H00M00S
• If current time is 10H59M29S, round operation changes time to 10H59M00S
6.3.4.2.1 TC Registers Read Access
TC registers read accesses can be done in two ways:
• A direct read to the TC registers. In this case, there can be a discrepancy between the final time read
and the real time because the RTC keeps running because some of the registers can toggle in
between register accesses. Software must manage the register change during the reading.
• Read access to shadowed TC registers. These registers are at the same addresses as the normal TC
registers. They are selected by setting the GET_TIME bit in the RTC_CTRL_REG register. When this
bit is set, the content of all TC registers is transferred into shadow registers so they represent a
coherent timestamp, avoiding any possible discrepancy between them. When processing the read
accesses to the TC registers, the value of the shadowed TC registers is returned so it is completely
transparent in terms of register access.
6.3.4.2.2 TC Registers Write Access
TC registers write accesses can be done in two ways:
• Direct write into the TC registers. In this case, because the RTC keeps running, there can be a
discrepancy between the final time written and the target time to be written because some of the
registers can toggle in between register accesses. Software must manage the register change during
the writing.
• Write access while RTC is stopped. Software can stop the RTC by the clearing STOP_RTC bit of the
control register and checking the RUN bit of the status to be sure that RTC is frozen. It then updates
the TC values and restarts the RTC by setting the STOP_RTC bit, which ensures that the final written
values are aligned with the targeted values.
6.3.4.3 RTC Alarm
RTC alarm registers (ALARM_SECONDS_REG, ALARM_MINUTES_REG, ALARM_HOURS_REG,
ALARM_DAYS_REG, ALARM_MONTHS_REG, and ALARM_YEARS_REG) are used to set the alarm
time or date to the corresponding generated IT_ALARM interrupts. This interrupt is enabled through the
IT_ALARM bit in the RTC_INTERRUPTS_REG register. These register values are written in BCD code,
with the same data range as described for the TC registers (see Section 6.3.4.2).
6.3.4.4 RTC Interrupts
The RTC supports two types of interrupts:
• IT_ALARM interrupt. This interrupt is generated when the configured date or time in the corresponding
ALARM registers is reached. This interrupt is enable by the IT_ALARM bit in the
RTC_INTERRUPT_REG register.
• IT_TIMER interrupt. This interrupt is generated when the periodic time set in the EVERY bits of the
RTC_INTERRUPT_REG register is reached. This interrupt is enabled by the IT_TIMER bit in the
RTC_INTERRUPT_REG register. During the SLEEP state, the IT_TIMER interrupt can either be
masked (stored and generated once out of SLEEP state) or unmasked using the
IT_SLEEP_MASK_EN bit of the RTC_INTERRUPT_REG register.
l TEXAS INSTRUMENTS
Compensation Value Frozen
3 4 5 6HOURS_REG
1 58 59 0 1 58 59 0 1 58 59 0 1 58
0 59
... ... ... ...
New Compensation Value
02 3
43
59
58
SECONDS_REG
HOURS_REG
SECONDS_REG
RTC_COMP_xxx_REG
Register
Update Compensation
Event
32768 COMP_REG
32768
-
æ ö
ç ÷
è ø
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6.3.4.5 RTC 32-kHz Oscillator Drift Compensation
The RTC_COMP_MSB_REG and RTC_COMP_LSB_REG registers are used to compensate for any
inaccuracy of the 32-kHz clock output from the 16.384MHz crystal oscillator. To compensate for any
inaccuracy, software must perform an external calibration of the oscillator frequency, calculate the drift
compensation needed versus one time hour period, and load the compensation registers with the drift
compensation value.
The compensation mechanism is enabled by the AUTO_COMP_EN bit in the RTC_CTRL_REG register.
The process happens after the first second of each hour. The time between second 1 to second 2
(T_ADJ) is adjusted based on the settings of the two RTC_COMP_MSB_REG and
RTC_COMP_LSB_REG registers. These two registers form a 16-bit, 2s complement value COMP_REG
(from –32767 to 32767) that is subtracted from the 32-kHz counter as per the following formula to adjust
the length of T_ADJ: . It is therefore possible to adjust the compensation with a
1/32768-second time unit accuracy per hour and up to 1 second per hour.
Software must ensure that these registers are updated before each compensation process (there is no
hardware protection). For example, software can load the compensation value into these registers after
each hour event, during second 0 to second 1, just before the compensation period, happening from
second 1 to second 2.
It is also possible to preload the internal 32-kHz counter with the content of the RTC_COMP_MSB_REG
and RTC_COMP_LSB_REG registers when setting the SET_32_COUNTER bit in the RTC_CTRL_REG
register. This must be done when the RTC is stopped.
Figure 6-8 shows the RTC compensation scheduling.
Figure 6-8. RTC Compensation Scheduling
6.3.5 GPADC – 12-Bit Sigma-Delta ADC
The GPADC consists of a 12-bit sigma-delta ADC combined with an analog input multiplexer. The GPADC
allows the host processor to monitor a variety of analog signals using analog-to-digital conversion on the
input source. After the conversion completes, an interrupt is generated for the host processor and it can
read the result of the conversion through the I2C interface.
The GPADC on this PMIC supports 16 analog inputs. However only a total of 9 inputs are available for the
application use. Three of these inputs are available on external balls, and the remaining six are dedicated
to internal resource monitoring. One of the three external inputs is associated with a current source
allowing measurements of resistive elements (thermal sensor). To improve the measurement accuracy,
the reference voltages GPADC_VREF can be used with an external resistor for the NTC resistor
measurement. The reference voltage GPADC_VREF is always present when the GPADC is enabled.
l TEXAS INSTRUMENTS
12-bit sigma
delta ADC
Software
conversion result
ADC control
ADC voltage reference
GPADC_IN0
GPADC_IN1
AUTO conversion request
AUTO conversion result
AUTO conversion result
Software conversion request
Interrupt
GPADC_IN2
Internal Channels
(Supply Voltage, DCDC
Current, and Die Temperature
Monitoring)
GPADC_VREF
Input
Scalar
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GPADC_IN0 is associated with three selectable current sources. The selectable current levels are 5, 15,
and 20 μA.
GPADC_IN1 is intended to measure temperature with an NTC sensor connected to ground. Two resistors,
one in parallel with the NTC resistor and the other one between GPADC_IN1 and GPADC_VREF, can be
used to modify the exponential function of the NTC resistor.
Figure 6-9 shows the block diagram of the GPADC.
Figure 6-9. Block Diagram of the GPADC
For all the measurements performed by the monitoring GPADC, voltage dividers, current to voltage
converters, and current source are integrated in the TPS65903x-Q1 devices to scale the signal to be
measured to the GPADC input range.
The conversion requests are initiated by the host processor either by software through the I2C. This mode
is useful when real-time conversion is required.
There are two kinds of conversion requests with the following priority:
• Asynchronous conversion request (SW)
• Periodic conversion (AUTO)
The EXTEND_DELAY bit in the GPADC_RT_CTRL register can extend by 400 μs the delay from the
channel selection or triggering to the sampling.
Use Equation 3 to convert from the GPADC code to the internal die temperature using GPADC channels
12 and 13.
l TEXAS INSTRUMENTS 2.64 mV
12
GPADC Code 1.25 0.753 V
Die Temperature ( C) 2.6 m
24 V
§ ·
ª º u 
¨ ¸
« »
¬ ¼
© ¹
q
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(1) The minimum and maximum voltage full range corresponds to typical minimum and maximum output codes (0 and 4095).
(2) The performance voltage is a range where gain error drift, offset drift, INL and DNL parameters are specified.
(3) If VANA LDO is OFF, maximum current to draw from GPADC_INx is 1 mA for reliability. For current higher than 1-mA VANA must be
set to SLEEP or ACTIVE mode.
(3)
Table 6-3. GPADC Channel Assignments
CHANNEL TYPE INPUT VOLTAGE
FULL RANGE(1) INPUT VOLTAGE
PERFORMANCE RANGE(2) SCALER OPERATION
0 (GPADC_IN0) External(3) 0 to 1.25 V 0.01 to 1.215 V No Resistor value or general purpose. Select
source current 0, 5, 15, or 20 μA
1 (GPADC_IN1) External(3) 0 to 1.25 V 0.01 to 1.215 V No Platform temperature, NTC resistor value
and general purpose
2 (GPADC_IN2) External(3) 0 to 2.5 V 0.02 to 2.43 V 2 Audio accessory or general purpose
7
(VCC_SENSE) Internal
2.5 to 5 V when
HIGH_VCC_SENSE
= 0
2.3 V to (VCC1–1 V)
when
HIGH_VCC_SENSE
= 1
2.5 to 4.86 V when
HIGH_VCC_SENSE = 0
2.3 V to (VCC1–1 V) when
HIGH_VCC_SENSE = 1
4 System supply voltage (VCC_SENSE)
10 (VBUS) Internal 0 to 6.875V 0.055 to 5.25V 5,5 VBUS Voltage
11 Internal 0 to 1.25 V No DC-DC current probe
12 Internal 0 to 1.25 V 0 to 1.215 V No PMIC internal die temperature
13 Internal 0 to 1.25 V 0 to 1.215 V No PMIC internal die temperature
15 Internal 0 to VCC1 V 0.055 to VCC1 V 5 Test network
6.3.5.1 Asynchronous Conversion Request (SW)
Software can also request conversion asynchronously. This conversion is not critical in terms of start-of-
conversion positioning. Software must select the channel to be converted, and then requests the
conversion with the GPADC_SW_SELECT register. An INT interrupt is generated when the conversion
result is ready, and the result is stored in the GPADC_SW_CONV0_LSB and GPADC_SW_CONV0_MSB
registers.
CAUTION
A defect in the digital controller of TPS65903x-Q1 devices may cause an
unreliable result from the first asynchronous conversion request after the device
exit from a warm reset. Texas Instruments recommends that user rely on
subsequent requests to obtain accurate result from the asynchronous
conversion after a device warm reset.
In addition, a cold reset event which happens during a GPADC conversion will
cause the GPADC controller to lock up. A software workaround for these issues
are described in detail in the Guide to Using the GPADC in TPS65903x and
TPS6591x Devices.
6.3.5.2 Periodic Conversion Request (AUTO)
Software can enable periodic conversions to compare one or two channels with a predefined threshold
level. Software must select one or two channels with the GPADC_AUTO_SELECT register and thresholds
and polarity with the GPADC_THRES_CONV0_LSB, GPADC_THRES_CONV0_MSB,
GPADC_THRES_CONV1_LSB, and GPADC_THRES_CONV1_MSB registers. In addition, software must
select the conversion interval with the GPADC_AUTO_CTRL register and enable the periodic conversion
l TEXAS INSTRUMENTS Measured de O 3 Measured poms
Measured
code
Y2
Ideal
curve
D2 = Y2 – X2
Measured
curve
Y1
Offset
D1 = Y1 – X1
X1 X2
Ideal code
Calibration
points
Measured
points
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with the AUTO_CONV0_EN and AUTO_CONV1_EN bits. There is no need to enable the GPADC
separately. The control logic enables and disables the GPADC automatically to save power. When AUTO
mode is the only conversion enabled, do not use the AUTO_CONV0_EN and AUTO_CONV1_EN bits to
disabled the conversion. Instead, force the state machine of the GPADC on by setting the
GPADC_CTRL1. GPADC_FORCE bit = 1, then shutdown the GPADC AUTO conversion using
GPADC_AUTO_CTRL.SHUTDOWN_CONV[01] = 0. Wait 100µS before disabling the GPADC state
machine by setting GPADC_CTRL1. GPADC_FORCE bit = 0. The latest conversion result is always
stored in the GPADC_AUTO_CONV0_LSB, GPADC_AUTO_CONV0_MSB,
GPADC_AUTO_CONV1_LSB, and GPADC_AUTO_CONV1_MSB registers. All selected channels are
queued and converted from channel 0 to 7. The first (lower) converted channel results is placed in the
GPADC_AUTO_CONV0 register and the second one is placed in the GPADC_AUTO_CONV1 register.
Therefore, TI recommends putting the lower channel to convert in AUTO_CONV0_SEL and the higher
channel to convert in AUTO_CONV1_SEL.
If the conversion result triggers the threshold level, an INT interrupt is generated and the conversion result
is stored. If the interrupt is not cleared or the results are not read before another auto-conversion is
completed, then the registers store only the latest results, discarding the previous ones. The
autoconversion is never stopped by an uncleared interrupt or unread registers.
Programming the triggering of the threshold level can also generate shutdown. This is available for
CONV0 and CONV1 channels independently and is enabled with the SHUTDOWN bits in the
GPADC_AUTO_CTRL register. During SLEEP and OFF modes, only channels from 0 to 10 can be
converted. For channels 12 and 13, conversion is possible in sleep if thermal sensor is not disabled.
6.3.5.3 Calibration
The GPADC channels are calibrated in the production line using a two-point calibration method. The
channels are measured with two known values (X1 and X2) and the difference (D1 and D2) to the ideal
values (Y1 and Y2) are stored in OTP memory. The principle of the calibration is shown in Figure 6-10.
Figure 6-10. ADC Calibration Scheme
Some of the GPADC channels can use the same calibration data and the corrected result can be
calculated using the equations:
l TEXAS INSTRUMENTS
( )
a b
a '
k
-
=
( )
b D1 k 1 X1= - - ´
(D2 D1)
k 1 (X2 X1)
æ ö
-
= + ç ÷
-
è ø
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Gain:
(4)
Offset:
(5)
If the measured code is a, the corrected code a' is:
(6)
Table 6-4 summarizes the parameters X1 and X2, and the register of D1 and D2 needed in the calculation
for all the channels.
Table 6-4. GPADC Calibration Parameters
CHANNEL X1 X2 D1 D2 COMMENTS
0,1 2064 (0.63 V) 3112 (0.95 V) GPADC_TRIM1 GPADC_TRIM2 Channel 1 trimming is used
2 2064 (1.26 V) 3112 (1.9 V) GPADC_TRIM3 GPADC_TRIM4
7 2064 (2.52 V) 3112 (3.8 V) GPADC_TRIM7 GPADC_TRIM8
6.3.6 General-Purpose I/Os (GPIO Terminals)
The TPS65903x-Q1 device integrates eight configurable general-purpose I/Os that are multiplexed with
alternative features as described in Table 6-5.
Table 6-5. General Purpose I/Os Multiplexed Functions
TERMINAL PRIMARY FUNCTION SECONDARY FUNCTION
GPIO_1 General-purpose I/O Output: VBUSDET (VBUS detection)
GPIO_2 General-purpose I/O Output: REGEN2
GPIO_4 General-purpose I/O Output: SYSEN1 (external system enable)
GPIO_5 General-purpose I/O Output: CLK32KGO1V8 (32-kHz digital-fated output clock in VRTC domain) or
SYNCCLKOUT (Fallback synchronization clock for SMPS, 2.2MHz)
GPIO_6 General-purpose I/O Output: SYSEN2 (external system enable)
GPIO_7 General-purpose I/O Input: POWERHOLD
For GPIO characteristics, refer to:
• Ball description (see Section 4)
• Electrical characteristics (see Section 5.16, and Section 5.17 )
• Pullup and pulldown characteristics (see Section 5.18)
Each GPIO event can generate an interrupt on either rising and/or falling edge and each line is individually
maskable (as described in Section 6.3.8)
All GPIOs can be used as wake-up events.
NOTE
GPIO_4 and GPIO_6 are in the VIO domain and need the I/O supply to be available.
When configured in OTP as SYSEN1 and SYSEN2, GPIO_4 and GPIO_6 can be programmed to be part
of power-up sequence.
Selection between primary and secondary functions is controlled through the registers
PRIMARY_SECONDARY_PAD1 and PRIMARY_SECONDARY_PAD2.
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When configured as primary functions, all GPIOs are controlled through the following set of registers:
• GPIO_DAT_DIR: Configure each GPIO direction individually (Read or Write)
• GPIO_DATA_IN: Data line-in when configured as an input (Read Only)
• GPIO_DATA_OUT: Data line-out when configured as an output (Read or Write)
• GPIO_DEBOUNCE_EN: Enable each GPIO debouncing individually (Read or Write)
• GPIO_CTRL: Global GPIO control to enable or disable all GPIOs (Read or Write)
• GPIO_CLEAR_DATA_OUT: Clear each GPIO data out individually (Write Only)
• GPIO_SET_DATA_OUT: Set each GPIO data out individually (Write Only)
• PU_PD_GPIO_CTRL1, PU_PD_GPIO_CTRL2: Configure each line pull up and pull down (Read or
Write)
• OD_OUTPUT_GPIO_CTRL: Enable individual open-drain output (Read or Write)
When configured as secondary functions, none of the GPIO control registers (see Table 6-5) affect GPIO
lines. Line configuration (pullup, pulldown, open-drain) for secondary functions is held in a separate
register set, as well as specific function settings.
6.3.6.1 REGEN Output
Dedicated REGEN signal REGEN1 can be programmed to be part of power sequences to enable external
devices like external SMPS. The REGEN2 signal is MUXed in GPIO_2, and when REGEN2 mode is
selected it can also be programmed to be part of power sequences. All REGEN signals are at VSYS level.
6.3.7 Thermal Monitoring
The TPS65903x-Q1 devices include several thermal monitoring functions:
• Thermal protection module internal to the TPS65903x-Q1 devices, placed close to the SMPS and LDO
modules
• Platform temperature monitoring with an external NTC resistor
• Platform temperature monitoring with an external diode
The TPS65903x-Q1 devices integrate two thermal detection modules to monitor the temperature of the
die. These modules are placed on opposite sides of the chip and close to the LDO and SMPS modules.
Overtemperature at either module generates a warning to the system; if the temperature continues to rise,
the TPS65903x-Q1 devices shut down before damage to the die can occur.
Thus, there are two protection levels:
• A hot-die (HD) function sends an interrupt to software. Software is expected to close any noncritical
running tasks to reduce power.
• A thermal shutdown (TS) function immediately starts the TPS65903x-Q1 device switch-off.
By default, thermal protection is always enabled except in the BACKUP or OFF state. Disabling thermal
protection in SLEEP mode for minimum power consumption is possible.
To use thermal monitoring in the system:
• Set the value for the HD temperature threshold with the OSC_THERM_CTRL.THERM_HD_SEL[1:0]
register.
• TS can be disabled in SLEEP mode by setting the THERM_OFF_IN_SLEEP bit to 1 in the
OSC_THERM_CTRL register.
• During operation, if the die temperature increases above HD_THR_SEL, an interrupt (INT1.HOTDIE) is
sent to the host processor. Immediate action to reduce TPS65903x-Q1 power dissipation must be
taken by shutting down some function.
• If the die temperature of the TPS65903x-Q1 devices rise further (above 148°C) an immediate
shutdown occurs. A TS event indication is written to the status register, INT1_STATUS_HOTDIE. The
system cannot restart until the temperature falls below HD_THR_SEL.
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6.3.7.1 Hot-Die Function (HD)
The HD detector monitors the temperature of the die and provides a warning to the host processor
through the interrupt system when temperature reaches a critical value. The threshold value must be set
below the thermal shutdown threshold. Hysteresis is added to the HD detection to avoid the generation of
multiple interrupts.
The integrated HD function provides the host PM software with an early warning overtemperature
condition. This monitoring system is connected to the interrupt controller and can send an interrupt when
the temperature is higher than the programmed threshold. The TPS65903x-Q1 devices allow the
programming of four junction-temperature thresholds to increase the flexibility of the system: in nominal
conditions, the threshold triggering of the interrupt can be set from 117°C to 130°C. The HD hysteresis is
10°C in typical conditions.
When an interrupt is triggered by the power-management software, immediate action must be taken to
reduce the amount of power drawn from the TPS65903x-Q1 devices (for example, noncritical applications
must be closed).
6.3.7.2 Thermal Shutdown (TS)
The TS detector monitors the temperature on the die. If the junction reaches a temperature at which
damage can occur, a switch-off transition is initiated and a thermal shutdown event is written into a status
register.
The system cannot be restarted until the die temperature falls below the HD threshold.
6.3.7.3 Temperature Monitoring With External NTC Resistor or Diode
The GPADC_IN1 channel can be used to measure a temperature with an external NTC resistor. External
pullup and pulldown resistors can be connected to the input to linearize the characteristics of the NTC
resistor. The temperature limits are set by external resistors.
6.3.8 Interrupts
Table 6-6 lists the TPS65903x-Q1 interrupts.
These interrupts are split into four register groups (INT1, INT2, INT3, INT4) and each group has three
associated control registers:
• INTx_STATUS: Reflects which interrupt source has triggered an interrupt event
• INTx_MASK: Used to mask any source of interrupt, to avoid generating an interrupt on a specified
source
• INTx_LINE_STATE: Reflects the real-time state of each line associated to each source of interrupt
The INT4 register group has two additional registers, INT4_EDGE_DETECT1 and
INT4_EDGE_DETECT2, to independently configure rising and falling edge detection.
All interrupts are logically combined on a single output line INT (default active low). This line is used as an
external interrupt line to warn the host processor of any interrupt event that has occurred within the device.
The host processor has to read the interrupt status registers (INTx_STATUS) through the control interface
(I2C or SPI) to identify the interrupt source(s). Any interrupt source can be masked by programming the
corresponding mask register (INTx_MASK). When an interrupt is masked, its associated event detection
mechanism is disabled. Therefore the corresponding STATUS bit is not updated and the INT line is not
triggered if the masked event occurs. Any event happening while its corresponding interrupt is masked is
lost. If an interrupt is masked after it has been triggered (event has occurred and has not yet been
cleared), then the STATUS bit reflects the event until it is cleared and it does not trigger again if a new
event occurs (because it is now masked).
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Because some interrupts are sources of ON requests (see Table 6-6), source masking can be used to
mask a specific device switch-on event. Because an active interrupt line INT is treated as an ON request,
any interrupt not masked must be cleared to allow the execution of a SLEEP sequence of the device when
requested.
The INT line polarity and interrupts clearing method can be configured using the INT_CTRL register.
An INT line event can be provided to the host in either SLEEP or ACTIVE mode, depending on the setting
of the OSC_THERM_CTRL.INT_MASK_IN_SLEEP bit.
When a new interrupt occurs while the interrupt line INT is still active (not all interrupts have been
cleared), then:
• If the new interrupt source is the same as the one that has already triggered the INT line, it can be
discarded or stored as a pending interrupt depending on the setting of the INT_CTRL.INT_PENDING
bit.
– When the INT_CTRL.INT_PENDING bit is active (default), then any new interrupt event occurring
on the same source (while the INT line is still active) is stored as a pending interrupt. Because only
one level of pending interrupt can be stored for a given source, when several events (more than
two) occur on the same source, only the last one is stored. While an interrupt is pending, two
accesses are needed (either read or write) to clear the STATUS bit: one access for the actual
interrupt and another for the pending interrupt. Note: two consecutive read or write operations to
the same register clear only one interrupt. Another register must be accessed between the two read
or write clear operations. Example for clear-on-read: when INT signal is active, read all four
INTx_STATUS registers in sequence to collect status of all potential interrupt sources. Read access
clears the full register for an active or actual interrupt. If the INT line is still active, repeat read
sequence to check and clear pending interrupts.
– When the INT_CTRL.INT_PENDING bit is inactive, then any new interrupt event occurring on the
same source (while the INT line is still active) is discarded. Note: two consecutive read or write
operations to the same register clear only one interrupt. Another register must be accessed
between the two read or write clear operations.
• If the new interrupt source is different from the one that already triggered the INT line, then it is stored
immediately into its corresponding STATUS bit.
To clear the interrupt line, all status registers must be cleared. The clearing of all status registers is
achieved by using a clear-on-read or a clear-on-write method. The clearing method is selectable though
the INT_CTRL.INT_CLEAR bit. Once set, the clearing method applies to all bits for all interrupts.
• Clear-on-read
– Read access to a single status register clears all the bits for only this specific register (8 bits).
Therefore, clearing all interrupts requests to read the four status registers. If the INT line is still
active when the four read accesses complete, then another interrupt event has occurred during the
read process; therefore the read sequence must be repeated.
• Clear-on-write
– This method is bit-based; setting a specific bit to 1 clears only the written bit. Therefore, to clear a
complete status register, 0xFF must be written. Clearing all interrupts requests to write 0xFF into
the four status registers. If the INT line is still active when the four write accesses are complete,
then another interrupt event has occurred during the write process; therefore the write sequence
must be repeated.
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Table 6-6. Interrupt Sources
INTERRUPT ASSOCIATED
EVENT EDGES
DETECTION ON REQUEST REG.
GROUP REG. BIT DESCRIPTION
VSYS_MON Internal event Rising and falling Never
INT1
6System voltage monitoring interrupt: Triggered when
system voltage has crossed the configured threshold
in VSYS_MON register.
HOTDIE Internal event Rising and falling Never 5
Hot-die temperature interrupt: The embedded thermal
monitoring module has detected a die temperature
above the hot-die detection threshold. Interrupt is
generated in ACTIVE and SLEEP state, not in OFF
state.
PWRDOWN PWRDOWN
(terminal) Rising and falling Never 4 Power-down interrupt: Triggered when the event is
detected on the PWRDOWN terminal.
RPWRON RPWRON
(terminal) Falling Always
(INT mask don't
care) 3Remote power-on interrupt: Triggered when a signal
change is detected. Interrupt is generated in ACTIVE
and SLEEP state, not in OFF state.
LONG_PRESS_KE
YPWRON
(terminal) Falling Never 2 Power-on long key-press interrupt. Triggered when
PWRON is low during more than the long-press delay
LONG_PRESS_KEY.LPK_TIME.
PWRON PWRON
(terminal) Falling Always
(INT mask don't
care) 1
Power-on interrupt: Triggered when PWRON button is
pressed (low) while the device is on. Interrupt is
generated in ACTIVE and SLEEP state, not in OFF
state.
SHORT Internal event Rising Yes
(if INT not
masked)
INT2
6Short interrupt: Triggered when at least one of the
power resources (SMPS or LDO) has its output
shorted.
RESET_IN RESET_IN
(terminal) Rising Never 4 RESET_IN interrupt: Triggered when event is detected
on RESET_IN terminal.
WDT Internal event Rising Never 2 Watchdog time-out interrupt: Triggered when
watchdog time-out has expired.
RTC_TIMER Internal event Rising Yes
(if INT not
masked) 1
Real-time clock timer interrupt: Triggered at
programmed regular period of time (every second or
minute). Running in ACTIVE, OFF, and SLEEP state,
default inactive.
RTC_ALARM Internal event Rising Yes
(if INT not
masked) 0Real-time clock alarm interrupt: Triggered at
programmed determinate date and time.
VBUS VBUS
(terminal) Rising and falling Yes
(if INT not
masked)
INT3
7VBUS wake-up comparator interrupt. Active in OFF
state. Triggered when VBUS present.
GPADC_EOC_SW Internal event N/A Yes
(if INT not
masked) 2GPADC software end of conversion interrupt:
Triggered when conversion result is available.
GPADC_AUTO_1 Internal event N/A Yes
(if INT not
masked) 1
GPADC automatic periodic conversion 1: Triggered
when result of conversion is either above or below
(depending on configuration) reference threshold
GPADC_AUTO_CONV1_LSB and
GPADC_AUTO_CONV1_MSB.
GPADC_AUTO_0 Internal event N/A Yes
(if INT not
masked) 0
GPADC automatic periodic conversion 0: Triggered
when result of conversion is either above or below
(depending on configuration) reference threshold
GPADC_AUTO_CONV0_LSB and
GPADC_AUTO_CONV0_MSB.
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Table 6-6. Interrupt Sources (continued)
INTERRUPT ASSOCIATED
EVENT EDGES
DETECTION ON REQUEST REG.
GROUP REG. BIT DESCRIPTION
GPIO_7 GPIO_7
(terminal) Rising and/or
falling
Yes
(if INT not
masked)
INT4
7 GPIO_7 rising- or falling-edge detection interrupt
GPIO_6 GPIO_6
(terminal) Rising and/or
falling
Yes
(if INT not
masked) 6 GPIO_6 rising- or falling-edge detection interrupt
GPIO_5 GPIO_5
(terminal) Rising and/or
falling
Yes
(if INT not
masked) 5 GPIO_5 rising- or falling-edge detection interrupt
GPIO_4 GPIO_4
(terminal) Rising and/or
falling
Yes
(if INT not
masked) 4 GPIO_4 rising- or falling-edge detection interrupt
GPIO_3 GPIO_3
(terminal) Rising and/or
falling
Yes
(if INT not
masked) 3 GPIO_3 rising- or falling-edge detection interrupt
GPIO_2 GPIO_2
(terminal) Rising and/or
falling
Yes
(if INT not
masked) 2 GPIO_2 rising- or falling-edge detection interrupt
GPIO_1 GPIO_1
(terminal) Rising and/or
falling
Yes
(if INT not
masked) 1 GPIO_1 rising- or falling-edge detection interrupt
GPIO_0 GPIO_0
(terminal) Rising and/or
falling
Yes
(if INT not
masked) 0 GPIO_0 rising- or falling-edge detection interrupt
6.3.9 Control Interfaces
The TPS65903x-Q1 devices have two exclusive selectable (from factory settings) interfaces; two high-
speed I2C interfaces (I2C1_SCL_SCK or I2C1_SDA_SDI and I2C2_SCL_SCE or I2C2_SDA_SDO) or one
SPI interface (I2C1_SCL_SCK, I2C1_SDA_SDI, I2C2_SDA_SDO, or I2C2_SCL_SCE). Both are used to
fully control and configure the device and have access to all the registers. When the I2C configuration is
selected the I2C1_SCL_SCK or I2C1_SDA_SDI, a general purpose control (GPC) interface is dedicated
to configure the device and the I2C2_SCL_SCE or I2C2_SDA_SDO interface dynamic voltage scaling
(DVS) is dedicated to dynamically change the output voltage of the SMPS converters. The DVS I2C
interface has access only to the voltage scaling registers of the SMPS converters (read and write mode).
6.3.9.1 I2C Interfaces
The GPC I2C interface (I2C1_SCL_SCK and I2C1_SDA_SDI) is dedicated to access the configuration
registers of all the resources of the system.
The DVS I2C interface (I2C2_SCL_SCE and I2C2_SDA_SDO) is dedicated to access the DVS registers
independently from the GPC I2C.
The control interfaces comply with the HS-I2C specification and support the following features:
• Mode: Slave only (receiver and transmitter)
• Speed:
– Standard mode (100 kbps)
– Fast mode (400 kbps)
– High-speed mode (3.4 Mbps)
• Addressing: 7-bit mode addressing device
The following features are not supported:
• 10-bit addressing
• General call
• Master mode (bus arbitration and clock generation)
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I2C is a 2-wire serial interface developed by NXP (formerly Philips Semiconductor) (see I2C-Bus
Specification and user manual, Rev 03, June 2007). The bus consists of a data line (SDA) and a clock line
(SCL) with pullup structures. When the bus is idle, the SDA and SCL lines are pulled high. All the I2C-
compatible devices connect to the I2C bus through open-drain I/O terminals, SDA and SCL. A master
device, usually a microcontroller or a digital signal processor, controls the bus. The master is responsible
for generating the SCL signal and device addresses. The master also generates specific conditions that
indicate the start and stop of data transfers. A slave device receives and/or transmits data on the bus
under control of the master device. The data transfer protocol for standard and fast modes is exactly the
same, and they are referred to as F/S mode in this document. The protocol for high-speed mode is
different from F/S mode, and it is referred to as HS mode.
6.3.9.1.1 I2C Implementation
The TPS65903x-Q1 standard I2C 7-bit slave device address is set to 010010xx (binary) where the two
least-significant bits are used for page selection.
The device is organized in five internal pages of 256 bytes (registers) as follows:
• Slave device address 0x48: Power registers
• Slave device address 0x49: Interfaces and auxiliaries
• Slave device address 0x4A: Trimming and test
• Slave device address 0x4B: OTP
• Slave device address 0x12: DVS
The device address for the DVS I2C interface is set to 0x12.
If one of the addresses conflicts with another device I2C address, it is possible to remap each address to a
fixed alternative one as described in Table 6-7. I2C for DVS is fixed because it is dedicated interface.
Table 6-7. I2C Address Configuration
REGISTER BIT PAGE ADDRESSES
I2C_SPI
ID_I2C1[0] Power registers ID_I2C1[0] = 0: 0x48
ID_I2C1[0] = 1: 0x58
ID_I2C1[1] Interfaces and auxiliaries ID_I2C1[1] = 0: 0x49
ID_I2C1[1] = 1: 0x59
ID_I2C1[2] Trimming and test ID_I2C1[2] = 0: 0x4A
ID_I2C1[2] = 1: 0x5A
ID_I2C1[3] OTP ID_I2C1[3] = 0: 0x4B
ID_I2C1[3] = 1: 0x5B
ID_I2C2 DVS ID_I2C2 = 0: 0x12
6.3.9.1.2 F/S Mode Protocol
The master initiates data transfer by generating a START condition. The START condition is when a high-
to-low transition occurs on the SDA line while SCL is high (see Figure 6-11). All I2C-compatible devices
should recognize a START condition.
The master then generates the SCL pulses and transmits the 7-bit address and the read or write direction
bit (R/W) on the SDA line. During all transmissions, the master ensures that data is valid. A valid data
condition requires the SDA line to be stable during the entire high period of the clock pulse (see Figure 6-
12). All devices recognize the address sent by the master and compare it to their internal fixed addresses.
Only the slave device with a matching address generates an acknowledge (see Figure 6-13) by pulling the
SDA line low during the entire high period of the ninth SCL cycle. When this acknowledge is detected, the
master knows that the communication link with a slave has been established.
l TEXAS INSTRUMENTS iiiiiiiiiiii yyyyyyyyyyyyyyy
DATA
CLK
Data line
stable;
data valid
Change of data allowed
I2C_bittransfer
DATA
CLK
S
P
ST
ART
condition
ST
OP
condition
I2C_start_stop
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The master generates further SCL cycles to either transmit data to the slave (R/W bit 1) or receive data
from the slave (R/W bit 0). In either case, the receiver must acknowledge the data sent by the transmitter.
An acknowledge signal can be generated by the master or the slave, depending on which one is the
receiver. Nine-bit valid data sequences consisting of 8-bit data and 1-bit acknowledge can continue as
long as necessary.
To signal the end of the data transfer, the master generates a STOP condition by pulling the SDA line
from low to high while the SCL line is high (see Figure 6-11). This releases the bus and stops the
communication link with the addressed slave. All I2C-compatible devices must recognize the STOP
condition. Upon the receipt of a STOP condition, all devices know that the bus is released, and they wait
for a START condition followed by a matching address.
Attempting to read data from register addresses not listed in this section results in 0xFF being read out.
6.3.9.1.3 HS Mode Protocol
When the bus is idle, the SDA and SCL lines are pulled high by the pullup devices.
The master generates a START condition followed by a valid serial byte containing HS master code
00001XXX. This transmission is made in F/S mode at no more than 400 kbps. No device is allowed to
acknowledge the HS master code, but all devices must recognize it and switch their internal setting to
support 3.4-Mbps operation.
The master then generates a REPEATED START condition (a REPEATED START condition has the
same timing as the START condition). After the REPEATED START condition, the protocol is the same as
F/S mode, except transmission speeds up to 3.4 Mbps are allowed. A STOP condition ends the HS mode
and switches all the internal settings of the slave devices to support F/S mode. Instead of using a STOP
condition, REPEATED START conditions are used to secure the bus in HS mode.
Attempting to read data from register addresses not listed in this section results in 0xFF being read out.
Figure 6-11. START and STOP Conditions
Figure 6-12. Bit Transfer on the Serial Interface
{L} TEXAS INSTRUMENTS :X :XX \L/\XX: 4»
Recognize
START
or
REPEATED
START
condition
Generate
ACKNOWLEDGE
signal
Recognize
STOP
or
REPEATED
START
condition
P
SDA
MSB
Address
Acknowledgement
Sr
signal from
slave
R/W
SCL
S
or
Sr
ACK
Sr
ACK
or
P
START
or
REPEATED
START
condition
Clock line held low while
i
nterrupts
are
serviced
STOP
or
REPEATED
START
condition
I2C_busprotocol
1 2 78913-8 9
2
Data
output
by
transmitter
Not
acknowledge
Data
output
by
receiver
Acknowledge
SCL from
master
S
ST
ART
condition
12 8
9
Clock pulse for
acknowledgement
I2C_acknowledge
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Figure 6-13. Acknowledge on the I2C Bus
Figure 6-14. Bus Protocol
6.3.9.2 SPI Interface
The SPI is a 4-wire slave interface used to access and configure the device. The SPI allows read-and-
write access to the configuration registers of all resources of the system.
The SPI uses the following signals:
• SCE (I2C2_SCL_SCE): Chip enable – Input driven by host master, used to initiate and terminate a
transaction
• SCK (I2C1_SCL_SCK): Clock – Input driven by host master, used as master clock for data transaction
• SDI (I2C1_SDA_SDI): Data input – Input driven by host master, used as data line from master to slave
• SDO (I2C2_SDA_SDO): Data output – Output driven by TPS65903x-Q1 PMIC device, used as data
line from slave to master and defaults to high impedance
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6.3.9.2.1 SPI Modes
The SPI interface does not have access to the OTP and DVS registers (slave device address 0x4B &
0x12) of the TPS65903x-Q1 device. The SPI_PAGE_CTRL.SPI_PAGE_ACCESS regsiter can be
configured to access all other registers (slave device address 0x48, 0x49, & 0x4A) by:
• SPI_PAGE_CTRL.SPI_PAGE_ACCESS = 0: Page1 = 0x48, Page2 = 0x49
• SPI_PAGE_CTRL.SPI_PAGE_ACCESS = 1: Page1 = 0x48, Page3 = 0x4A
This SPI interface supports two access modes (Note: all shifts are done MSB first (Data, Address, Page):
• Single access (read or write)
– This consists of fetching and storing one single data location. The protocol is depicted in Figure 6-
15.
– The R/W bit is always provided first, followed by page address and register address fields. When
R/W = 0, a read access is performed. When R/W = 1, a write access is performed.
– 1 burst bit indicates if following transfer is a single access (BURST = 0) or a burst access (BURST
= 1).
– 4 unused bits follow the burst bit and finally the 8-bit data is either shifted in (write) or out (read).
– For a write access, the data output line SDO is invalid (useless) during the whole transaction.
– For a read access, the data output line SDO is invalid during the unused bits (time slot used for
data fetch) and then becomes active or valid after the unused bits.
• Burst access (read or write)
– This consists of fetching and storing several data at contiguous locations. The protocol is depicted
in Figure 6-16.
– The R/W bit is always provided first, followed by page address and register address fields. When
R/W = 0, a read access is performed. When R/W = 1, a write access is performed.
– 1 burst bit indicates if following transfer is a single access (BURST = 0) or a burst access (BURST
= 1).
– 4 unused bits follow the burst bit and finally packets of 8-bit data are either shifted in (write) or out
(read).
– The transaction remains active as long as the SCE signal is maintained high by the host.
– The address is automatically incremented internally for each new 8-bit packet received.
– The host must pull the SCE signal low after a complete 8-bit data is transferred, otherwise the last
transaction is discarded.
– For a write access, the data output line SDO is invalid (useless) during the whole transaction.
– For a read access, the data output line SDO is invalid during the unused bits (time slot used for
data fetch) and then becomes active or valid after the unused bits.
i Tans INSTRUMENTS
ES2.0
SCE
SCK
SDI
(SDI) RW Register address (8) Burst Unused bits (5) Data (8)
SCE
SCK
SDI
SDO
(SDO)
(SDI)
SPI write
SPI read
Palmas samples SDI on SCK rising edge
=> Master to assert data on falling edge
Palmas samples SDI on SCK rising edge
=> Master need to assert data on falling edge
Palmas asserts SDO to get it available on SCK rising edge
=> Master need to sample data on rising edge
Page
RW Register address (8) Burst Unused bits (5) 'RQ¶WFDUH
Page
Unused bits Data (8)
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6.3.9.2.2 SPI Protocol
Figure 6-15. SPI Single Read and Write Access
‘5‘ TEXAS INSTRUMENTS
ES2.0
SCE
SCK
SDI
(SDI) RW Register address (8) Burst Unused bits (5) Data (8)
SCE
SCK
SDI
SDO
(SDO)
(SDI)
SPI write
SPI read
Palmas samples SDI on SCK rising edge
=> Master to assert data on falling edge
Palmas samples SDI on SCK rising edge
=> Master need to assert data on falling
edge
Palmas asserts SDO to get it available on SCK rising edge
=> Master need to sample data on rising edge
Page
RW Register address
(8) Burst Unused bits (5) 'RQ¶WFDUH
Page
Unused
bits Data (8)
Data (8)
'RQ¶WFDUH
Data (8)
Data (8)
'RQ¶WFDUH
Data (8)
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Figure 6-16. SPI Burst Read and Write Access
6.3.10 Device Identification
The following registers can differentiate the TPS65903x-Q1 device being used.
Table 6-8. TPS65903x-Q1 Device ID
REGISTER NAME REGISTER DESCRIPTION VALUE
PRODUCT_ID_MSB For all TPS65903x-Q1 devices, this register will have the
same value. 0x90
PRODUCT_ID_LSB For all TPS65903x-Q1 devices, this register will have the
same value. 0x39
DESIGNREV This register distinguishes which silicon
version is used.
Revision 1.0 0x0
Revision 1.1 0x1
Revision 1.2 0x2
Revision 1.3 0x3
Revision 1.4 0x4
SW_REVISION This register will be representative of the OTP version
programmed on the device. OTP dependent
6.4 Device Functional Modes
6.4.1 Embedded Power Controller
The EPC is composed of three main modules:
• An event arbitration module used to prioritize ON, OFF, WAKE, and SLEEP requests.
• A power state-machine used to determine which power sequence to execute, based on the system
state (supplies, temperature, and so forth) and requested transition (from the event arbitration module).
H H } UUL
Resources
Resources
Resources
ON Requests
OFF Requests
SLEEP Requests Event
WAKE Requests
Events
Arbitration
Power State
Machine
Power
Sequence
Pointer Power
Sequencer
System State
(Supplies, Temperature, ...)
Power
Sequences
OFF2ACT
ACT2OFF
SLP2OFF
ACT2SLP
SLP2ACT
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• A power sequencer that fetches the selected power sequence from OTP and executes it. The power
sequencer sets up and controls all resources accordingly, based on the definition of each sequence.
Figure 6-17 shows the EPC block diagram.
Figure 6-17. EPC Block Diagram
The power state-machine is defined through the following states:
•NO SUPPLY: The device is not powered by any energy source on the system power rail (VCC1 <
POR).
•BACKUP: The device is not powered by a valid supply on the system power rail (VCC1 < VSYS_LO)
(VCC > POR).
•OFF: The device is powered by a valid supply on the system power rail (VCC1 > VSYS_LO) and it is
waiting for a start-up event or condition. All device resources are in the OFF state. The approximate
time for device to arrive the OFF state from the NO SUPPLY state, without considering the rise time of
VSYS and the settling time of the VSYS_LO comparator, is approximately 5.5 ms.
•ACTIVE: The device is powered by a valid supply on the system power rail (VCC1 > VSYS_LO) and
has received a start-up event. It has switched to the ACTIVE state, having full capacity to supply the
processor and other platform modules.
•SLEEP: The device is powered by a valid supply on the system power rail (VCC1 > VSYS_LO) and is
in low-power mode. All configured resources are set to their low-power mode, which can be ON,
SLEEP, or OFF depending on the specific resource setting. If a given resource is maintained active
(ON) during low-power mode, then all its linked subsystems are automatically maintained active.
Figure 6-18 shows the state diagram for the power control state-machine.
No Supply
BACKUP
VCC > POR
and
VCC < VSYS_LO
VCC > POR_threshold
OFF
ACTIVE
SLEEP
VCC > VSYS_LO
VCC < POR
VCC < POR
VCC < POR
VCC < VSYS_LO
VCC < VSYS_LO
VCC < VSYS_LO
OFF Request
OFF Request
SLEEP Request WAKE Request
ON Request and
VCC_SENSE > VSYS_HI
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Figure 6-18. State Diagram for the Power Control State-Machine
Power sequences define how a resource state switches between the OFF, ACTIVE, and SLEEP states,
but they have no effect during the NO SUPPLY or BACKUP states. The EPC supervises the system
according to these power sequences, once the device is brought into the OFF state from a NO SUPPLY
or BACKUP state. This is achieved automatically by internal hardware controlling the device before
handing it over to the EPC.
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The allowed power transitions are:
• OFF to ACTIVE (OFF2ACT)
• ACTIVE to OFF (ACT2OFF)
• ACTIVE to SLEEP (ACT2SLP)
• SLEEP to ACTIVE (SLP2ACT)
• SLEEP to OFF (SLP2OFF)
Each power transition consists of a sequence of one or several register accesses that controls the
resources according to the EPC supervision. Because these sequences are stored in nonvolatile memory
(OTP), they cannot be altered.
6.4.2 State Transition Requests
6.4.2.1 ON Requests
ON requests are used to switch on the device, which transitions the device from the OFF to the ACTIVE
state. Table 6-9 lists the ON requests.
Table 6-9. ON Requests
EVENT MASKABLE POLARITY COMMENT DEBOUNCE
RPWRON (terminal) No Low Level sensitive 16 ms ± 1 ms
PWRON (terminal) No Low Level sensitive N/A
Part of interrupts
(event) Yes (INTx_MASK register.
Default: Masked) Event Edge sensitive N/A
POWERHOLD
(terminal) No High Level sensitive 3 - 5 ms typical
If one of the events listed in Table 6-9 occurs, it powers on the device, unless one of the gating conditions
listed in Table 6-10 is present. For interrupt sources that can be configured as ON requests, see Table 6-
6.
Table 6-10. ON Requests Gating Conditions
EVENT MASKABLE POLARITY COMMENT
VSYS_HI (event) No Low VCC_SENSE < VSYS_HI
HOTDIE (event) No High Device temperature exceeds HOTDIE level
PWRDOWN (terminal) No OTP configurable
RESET_IN (terminal) No OTP configurable
6.4.2.2 OFF Requests
OFF requests are used to switch off the device, transitioning the device from the SLEEP or the ACTIVE to
the OFF state. Table 6-11 lists the OFF requests. OFF requests have the highest priority, and there are no
gating conditions. Any OFF request is executed even though a valid SLEEP or ON request is present. The
device goes to the OFF state, and once the OFF request is cleared it reacts to an ON request, if there are
any.
Table 6-11. OFF Requests
EVENT MASKABLE POLARITY DEBOUNCE SWITCH OFF
DELAY RESET LEVEL RESET
SEQUENCE
PWRON
(terminal)
(long press key)
No Low N/A SWOFF_DLY HWRST SD
PWRDOWN
(terminal) No OTP
configurable SWOFF_DLY OTP
Configurable OTP Configurable
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Table 6-11. OFF Requests (continued)
EVENT MASKABLE POLARITY DEBOUNCE SWITCH OFF
DELAY RESET LEVEL RESET
SEQUENCE
WATCHDOG
TIMEOUT
(internal event)
N/A. WDT is
disabled by default
but software can
enable it.
NA N/A SWOFF_DLY OTP
Configurable OTP Configurable
THERMAL
SHUTDOWN
(internal event) No NA N/A 0 OTP
Configurable OTP Configurable
RESET_IN
(terminal) No OTP
configurable N/A SWOFF_DLY OTP
Configurable OTP Configurable
SW_RST
(register bit) No NA N/A 0 OTP
Configurable OTP Configurable
DEV_ON
(register bit) No NA N/A 0 SWORST SD
VSYS_LO
(internal event) No NA 0 OTP
Configurable OTP Configurable
POWERHOLD
(terminal) No Low 0 SWORST SD
GPADC_SHUTD
OWN Yes NA N/A SWOFF_DLY OTP
Configurable OTP Configurable
Notes:
• SWOFF_DLY is the same for all requests. Once configured to a specific value (0, 1, 2, or 4 s) it is
applied to all OFF requests.
• RESET_LEVEL is selectable as HWRST (wide set of registers is reset to default values) or SWORTS
(more limited set of registers is reset).
• OFF requests are configured to force the EPC to either execute a shutdown (SD) or a cold restart
(CR).
– When configured to generate an SD, the EPC executes a transition to the OFF state (SLP2OFF or
ACT2OFF power sequence) and remains in the OFF state.
– When configured to generate a CR, the EPC executes a transition to the OFF state (SLP2OFF or
ACT2OFF power sequence) and restarts, transitioning to the ACTIVE state (OFF2ACT power
sequence) if none of the ON request gating conditions are present.
• Watchdog is disabled by default. SW can enable watchdog and lock (write protect) watchdog register
(WATCHDOG).
• The DEV_ON event has a lower priority over other ON events; it forces the device to go to the OFF
state only if no other ON conditions are keeping the device active (POWERHOLD).
• The POWERHOLD event has a lower priority over other ON events; it forces the device to go to the
OFF state only if no other ON conditions are keeping the device active (DEV_ON).
6.4.2.3 SLEEP and WAKE Requests
SLEEP requests are used to put the device in the SLEEP state, meaning a transition from the ACTIVE to
SLEEP state. This sets internal resources into low-power mode, as well as user-defined resources into
their user predefined low-power mode. The states of the resources during active and sleep modes are
defined in the LDO*_CTRL registers and SMPS*_CTRL registers.
Table 6-12 lists the SLEEP requests. Any of these events trigger the ACT2SLP sequence, unless there
are pending interrupts (unmasked). Only an interrupt or NSLEEP inactive (high) generates a WAKE
request to wake up the device (exit from the SLEEP state). A WAKE request (only during the SLEEP
state) wakes up the device and triggers a SLEEP2ACT or a SLEEP2OFF power sequence.
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Table 6-12. SLEEP Requests
EVENT MASKABLE POLARITY COMMENT
NSLEEP (terminal) Yes (Default: Masked) Low Level sensitive
For each resource, a transition from the ACTIVE to SLEEP state or SLEEP to ACTIVE state can be
controlled in two different ways:
• Through EPC sequencing (ACT2SLP or SLP2ACT power sequence), when the resource is associated
to the NSLEEP signal.
• Through direct control of the resource power mode (active or sleep).
– The user can bypass SLEEP and WAKE sequencing by having resources assigned to one external
control signal (ENABLE1). This signal has direct control on the power modes (active or sleep) of
any resources associated to it and it triggers an immediate switch from one mode to the other,
regardless of the EPC sequencing.
All resources can therefore be associated to two external terminals (NSLEEP and ENABLE1) and they
switch between the SLEEP and ACTIVE states based on Table 6-13.
Table 6-13. Resources SLEEP and ACTIVE Assignments
ENABLE1
ASSIGNMENT NSLEEP
ASSIGNMENT ENABLE1
TERMINAL STATE NSLEEP TERMINAL
STATE STATE TRANSITION
0 0 Don't care Don't care ACTIVE None
0 1 Don't care 0 ↔1 SLEEP ↔ACTIVE Sequenced
1 0 0 ↔1 Don't care SLEEP ↔ACTIVE Immediate
1 1
0 0 ↔1 SLEEP ↔ACTIVE Sequenced
1 0 ↔1 ACTIVE None
0↔1 0 SLEEP ↔ACTIVE Immediate
0↔1 1 ACTIVE None
NOTE
• The polarity of the NSLEEP and ENABLE1 signals is configurable through the
POLARITY_CTRL register. By default:
– ENABLE1 is active high; a transition from 0 to 1 requests a transition from SLEEP to
ACTIVE.
– NSLEEP is active low; a transition from 1 to 0 requests a transition from ACTIVE to
SLEEP.
• Resource assignments to the NSLEEP and ENABLE1 signals are configured in the
ENABLEx_YYY_ASSIGN and NSLEEP_YYY_ASSIGN registers (where x = 1 or 2 and
YYY = RES or SMPS or LDO)
• Several resources can be assigned to the same ENABLE1 signal and therefore, when
triggered, they all switch their power mode at the same time.
• When resources are assigned only to the NSLEEP signal, their respective switching
order is controlled and defined in the power sequence.
• When a resource is not assigned to any signal (NSLEEP and ENABLE1), it never
switches from the ACTIVE to SLEEP state. The resource always remains in active mode.
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CAUTION
A defect in the digital controller of TPS65903x-Q1 was discovered, which may
cause the PLL to shut down unexpectedly under the following sequence of
events:
• PLL is programmed to be OFF under SLEEP mode through the PLLEN_CTRL
register
• NSLEEP is assigned to control the entering of SLEEP mode for the PLL through the
NSLEEP_RES_ASSIGN register
• TPS65903x-Q1 goes through a SLP2OFF state transition followed by an OFF2ACT
state transition
• PLL is again assigned to be OFF in SLEEP mode through the programming of the
PLLEN_CTRL and the NSLEEP_RES_ASSIGN registers while the device remains in
ACTIVE mode
Two possible actions are recommended to help prevent the PLL from shutting
down unexpectedly:
• [Hardware Implementation] Toggle the NSLEEP pin twice to force the ACT2SLP and
SLP2ACT state transitions as soon as TPS65903x-Q1 wakes up from back to back
SLP2OFF and OFF2ACT state transitions
• [Software Implementation] Toggle the NSLEEP_POLARITY bit (0 →1→0) of the
POLARITY_CTRL register to force the ACT2SLP and SLP2ACT device state
transitions as soon as TPS65903x-Q1 wakes up from back to back SLP2OFF and
OFF2ACT state transitions
6.4.3 Power Sequences
A power sequence is an automatic pre-programmed sequence handled by the TPS65903x-Q1 device
series to configure the device resources: SMPSs, LDOs, 32-kHz clock, part of GPIOs, , REGEN signals)
into on, off, or sleep modes. See Section 6.3.6 for GPIO details.
Figure 6-19 shows an example of an OFF2ACT transition followed by an ACT2OFF transition. The
sequence is triggered through PWRON terminal and the resources controlled (for this example) are: VIO,
LDO1, SMPS2, LDO6, REGEN1, LDOLN, LDOUSB, and CLK32KOUT. The time between each resource
enable and disable (TinstX) is also part of the preprogrammed sequence definition.
When a resource is not assigned to any power sequence, it remains in off mode. The user (through
software) can enable and configure this resource independently after the power sequence completes.
l TEXAS INSTRUMENTS
VCC1
VRTC
VIO
CLK32KGO
16.384-MHz oscillator
clock output
RC 32kHz
t2
RESET_OUT
t3
t1
1st rail in
power
sequence
XX XX
PWRON
VIO
LDO1
SMPS2
LDO6
REGEN1
LDOLN
LDOSUB
OSC16MOUT
RESET_OUT
INT
Tinst1
Tinst2
Tinst3
Tinst4
Tinst5
Tinst6
Tinst7
Tinst8
PWRON_IT=1 Interrupt Acknowledge PWRON_IT=1 Interrupt Acknowledge
Tinst9
Tinst10
Tinst11
Tinst12
Tinst13
Tinst14
Tinst15
Tinst16
OFF2ACT Power Sequence ACT2OFF Power Sequence
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Figure 6-19. Power Sequence Example
The power sequences of the TPS65903x-Q1 device series are defined according to the processor
requirements, see the relevant Application Note for more information.
6.4.4 Start Up Timing and RESET_OUT Generation
The total start-up time of TPS65903x-Q1 from the first supply insertion until the release of reset to the
processor is defined by the boot time of internal resources as well as the OTP defined boot sequence.
Following figure shows the power up sequence timing and the generation of the RESET_OUT signal.
Figure 6-20. Start Up Timing Diagram
l TEXAS INSTRUMENTS
Switch-ON event
RESET_OUT Power-up sequence
POWERHOLD
Device maintained
ACTIVE for 8 seconds Device switch off starts
with no delay
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The t1time is the delay between VCC1 crossing the POR threshold and VIO (First rail in the power
sequence) rising up. The t1time must be at least 6 ms. If the time from VCC to VIO is less than 6 ms, the
VIO buffers are supplied while the OTP is still being initialized, which could cause glitches on any VIO
output buffer. Supplying VIO at least 6 ms after supplying VCC makes sure that the OTP is initialized and
the output buffers are held low when VIO is supplied. The VIO_IN pin may be supplied before or after the
first rail in the power sequence is enabled, as long as it is at least 6 ms after VCC.
The t2time is the internal 16.384-MHz crystal oscillator start-up time, or the external 32kHz clock input
availability delay time.
The t3time is the delay between the power up sequence start and RESET_OUT release. RESET_OUT
will be released once power up sequence is complete and:
• the 16.384MHz clock is stabilized if the 16.384MHz Xtal is present and the oscillator is enabled, or
• the external 32kHz clock is stabilized and the 16.384MHz oscillator is bypassed, or
• the GATE_RESET_OUT OTP bit is used to allow the TPS65903x-Q1 to power up without the
presence of the 16.384MHz crystal nor the external 32kHz clock input.
The duration of the power up sequence depends on OTP programming; average value is about 10ms.
6.4.5 Power On Acknowledge
The TPS65903x-Q1 device series is designed to support the following power on acknowledge modes:
POWERHOLD mode and AUTODEVON mode.
6.4.5.1 POWERHOLD Mode
In POWERHOLD mode, the acknowledge of the power on is achieved through a dedicated pin,
POWERHOLD. Upon receipt of an ON request, the device initiates the power-up sequence and asserts
the RESET_OUT pin high once it is in the ACTIVE state (reset released). While in the ACTIVE state, the
device remains active for 8 seconds and then automatically shuts down. During this time-frame, to keep
the device active, the host processor must assert and keep the POWERHOLD pin high. If the
POWERHOLD pin is then set back to low, it is interpreted as an OFF request by the device.
Figure 6-21 shows the POWERHOLD mode timing diagrams.
Figure 6-21. POWERHOLD Mode Timing Diagrams
6.4.5.2 AUTODEVON Mode
In this mode, at the end of the power-up sequence, the register bit DEV_CTRL.DEV_ON is automatically
set to 1 and the device remains in its ACTIVE state until this bit is cleared by the host processor.
Figure 6-22 and Figure 6-23 show the AUTODEVON mode timing diagrams.
l TEXAS INSTRUMENTS
Switch-on event
RESET_OUT Power-up sequence
DEV_ON
Device maintained
ACTIVE for 8 seconds
I2C-SPI access I2C-SPI access
Device switch off starts
with no delay
Switch-on event
RESET_OUT Power-up sequence
DEV_ON
I2C-SPI access
Device switch off starts
with no delay
Device maintained
ACTIVE for 8 seconds
75
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Figure 6-22. AUTODEVON Mode Timing Diagrams
The DEV_ON bit can also be configured so that it is not auto-updated (set to 1) at the end of the power-up
sequence. In this case, the device behaves similarly to the POWERWHOLD mode, except the host has
control over it using the DEV_CTRL.DEV_ON register bit instead of the POWERHOLD terminal.
Therefore, to keep the device active, the host must set and keep this bit at 1.
Figure 6-23. DEV_ON Mode Timing Diagrams
6.4.6 BOOT Configuration
All TPS65903x-Q1 device series resource settings are stored under the form of registers. Therefore, any
platform-related settings are linked to an action altering these registers. This action can be a static update
(register initialization value) or a dynamic update of the register (either from the user or from a power
sequence).
Resources and platform settings are stored in nonvolatile memory (OTP):
• Static platform settings:
– These settings define, for example, SMPS or LDO default voltages, GPIO functionality, and
TPS65903x-Q1 switch-on events. Part of the static platform settings can have two different values,
and these values are selected with the BOOT0 terminal. Static platform settings can be overwritten
by a power sequence or by the user.
• Sequence platform settings:
– These settings define TPS65903x-Q1 power sequences between state transitions, for example, the
OFF2ACT sequence when transitioning from OFF mode to ACTIVE mode. Each power sequence is
composed of several register accesses that define which resources (and their corresponding
registers) must be updated during the respective state transition. Three different sequences can be
defined with the BOOT0 and BOOT1 terminals. These settings can be overwritten by the user once
the power sequence completes its execution.
l TEXAS INSTRUMENTS —> BOOTO I ‘ BOOT1
STATIC
PLATFORM
SETTINGS
(Default config
for
all Boot; IO
Mux,
Default
Voltage, etc.)
Reload
du
r
i
ng
OFF
ST
A
TE
t
r
a
n
s
i
t
i
on
(According to respective
reset domain SWORST and
HWRST)
SELECTABLE
PLATFORM
SETTINGS
Initialization
done at
reset
RD
Platform settings
are modifiable by
µC during
OFF,
ACTIVE, or SLEEP
transition
Switch ON event
BOOT0
Power
IC
Resources
Configuration and
Control
Registers
Voltage
modification,
resource
enable or disable
SEQUENCE
PLATFORM
SETTINGS
(State Transition
Micro
Program)
RD
µC controller
RD
Register updates
during
OFF, ACTIVE, and
SLEEP transitions
BOOT0
BOOT1
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Figure 6-24. Boot Terminal Control
6.4.6.1 Boot Terminal Selection
Table 6-14 lists the boot terminals associated configurations.
NOTE
Generally two of the three power sequence definitions are small modifications from the main
sequence to the respective OTP memory size.
Table 6-14. Boot Terminal Associated Configurations
BOOT0 BOOT1 OTP CONFIGURATION POWER SEQUENCE SELECTOR
0 0 Set_0 Sel_0
0 1 Set_0 Sel_1
1 0 Set_1 Sel_2
1 1 Set_1 Sel_2
The BOOT0 and BOOT1 terminals must be grounded or pulled up, but the terminals must not be
unconnected (high impedance).
The BOOT0 terminal is used to select between two different OTP sets (Set_0 and Set_1) of device
configuration (referred to as selectable platform settings in Figure 6-24). For list of OTP programmable
parameters with programmed values refer to the Application Note of the relevant part number.
l TEXAS INSTRUMENTS
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NOTE
The respective VSEL[6:0] bit field in the SMPSn_VOLTAGE and SMPSn_FORCE registers
is mapped on a same OTP memory location, meaning that they are loaded at reset with the
same value and that the BOOT0 terminal changes the setting for both of them.
The BOOT0 terminal can also be used with the BOOT1 terminal as static selectors during execution of the
power sequence. This is intended to provide a possibility from within a static power sequence, to branch to
different instructions. This allows choosing power sequences (or subpart of power sequences) based on
BOOT terminals without altering power sequences themselves in OTP.
6.4.7 Reset Levels
The device series resource control registers are defined by three categories:
• POR registers: POR registers
• HW registers: HARDWARE registers
• SWO registers: SWITCHOFF registers
These registers are associated to three levels of reset as described below:
• Power-on reset (POR)
– Power-on reset happens when the device gets its supplies and transition from the NOSUPPLY
state to the BACKUP state. This is the global device reset.
– Additionally, SMPS_THERMAL_STATUS, SMPS_SHORT_STATUS,
SMSP_POWERGOOD_MASK, LDO_SHORT_STATUS and SWOFF_STATUS registers are in
POR domain. This list is indicative only.
• HWRST – Hardware reset
– Hardware reset happens when any OFF request is configured to generate a hardware reset. This
reset triggers a transition to the OFF state from either the ACTIVE or SLEEP state (execute either
the ACT2OFF or SLP2OFF sequence).
• SWORST – Switch-off reset
– Switch-off reset happens when any OFF request is configured to not generate a hardware reset.
This reset acts as the HWRST, except only the SWO registers are reset. The device goes in the
OFF state, from either ACTIVE or SLEEP, and therefore executes the ACT2OFF or SLP2OFF
sequence.
– Power resource control registers for SMPS and LDO voltage levels and operating mode control are
in SWORST domain. Additionally some registers control the 32-kHz, REGENx and SYSENx,
watchdog, external charger control, and VSYS_MON comparator. This list is indicative only.
Table 6-15 lists the reset levels, and Figure 6-25 shows the reset levels versus registers.
Table 6-15. Reset Levels
LEVEL RESET TAG REGISTERS AFFECTED COMMENT
0 POR POR, HW, SWO This reset level is the lowest level, for which all registers are reset.
1 HWRST HW, SWO During hardware reset (HWRST), all registers are reset except the
POR registers.
2 SWORST SWO Only the SWO registers are reset.
I TFJms INSTRUMENTS
v
POR reset
HWRST reset
SWORST reset
POR
Registers
HW Registers SWO Registers
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Figure 6-25. Reset Levels versus Registers
6.4.8 Warm Reset
The device series can execute a warm reset. The main purpose of this reset is to recover the device from
a locked or unknown state by reloading the default configuration. The warm reset is triggered by the
NRESWARM terminal. During a warm reset, the OFF2ACT sequence is executed regardless of the actual
state (ACTIVE, SLEEP) and the device returns to or remains in the ACTIVE state. Resources that are not
part of the OFF2ACT sequence are not impacted by warm reset and maintain the previous state.
Resources that are part of power-up sequence go to ACTIVE mode and the output voltage level is
reloaded from OTP or kept in the previous value depending on the WR_S bit in the SMPSx_CTRL register
or the LDOx_CTRL register.
6.4.9 RESET_IN
RESET_IN is a gating signal for on request and causes a switch-off event (Cold Reset or Shutdown).
Table 6-11 shows that the RESET_IN behavior is programmable.
6.4.10 Watchdog Timer (WDT)
The watchdog timer has two modes of operation, periodic mode and interrupt mode.
In periodic mode, an interrupt is generated with a regular period Nthat is defined by the
WATCHDOG.TIMER setting. This interrupt is generated at the beginning of the period (when the
watchdog internal counter equals 1). The IC initiates a shutdown at the end of the period (when the
internal counter has reached N) only if the interrupt has not been cleared within the defined time frame (0
to N). In this mode, when the interrupt is cleared, the internal counter is not reset. The counter continues
to count until it reaches the maximum value (defined by the TIMER setting) and automatically rolls over to
0 in order to start a new counting period. Regardless of when the interrupt is cleared within a given period
(N), the next interrupt is generated only when the ongoing period completes (reaches N). The internal
watchdog counter is initialized and kept at 0 as long as the RESET_OUT terminal is low. The counter
begins counting as soon as the RESET_OUT terminal is released.
In interrupt mode, any interrupt source resets the watchdog counter and begins the counting. If the
sources of the interrupts are not cleared (INT line released) before the end of the predefined period N(set
by WATCHDOG.TIMER setting) then the IC initiates a shutdown. If the sources of the interrupts are
cleared within the predefined period, then the watchdog counter is discarded (DC) and no shutdown
sequence is initiated.
By default, the watchdog is disabled.
Figure 6-26 shows the watchdog timings.
l TEXAS INSTRUMENTS PERIODIC MODE \NTERRUPT MODE
PERIODIC MODE
Watchdog Internal 0
Counter 1 ... i ... N 0 1 ... ... N 0
New Watchdog IT Watchdog IT cleared New Watchdog IT IT Not cleared in
allowed timeframe
INT pin (active high)
Device Switch off
RESET_OUT pin
INTERRUPT MODE
Watchdog Internal X 0 1
Counter ... i dc dc 0 1 ... N 0
IT Not cleared in
New IT (reset WDT counter) New IT (reset WDT counter) allowed timeframe
INT pin (active high)
IT cleared Device Switch off
RESET_OUT pin
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Figure 6-26. Watchdog Timing Diagrams
6.4.11 System Voltage Monitoring
The power state-machine of the devices are controlled by comparators monitoring the voltage on the
VCC_SENSE and VCC1 terminals. For electrical parameters see Section 5.14.
POR: When the supply at the VCC1 terminal is below the POR threshold, the devices are in the
NO SUPPLY state. All functionality, including RTC, is off. When the voltage in VCC1 rises
above the POR threshold, the device enters from the NO SUPPLY to the BACKUP state.
VSYS_LO: When the voltage on VCC1 terminal rises above VSYS_LO, the device enters from the
BACKUP state to the OFF state. When the device is in the ACTIVE, SLEEP, or OFF state
and the voltage on VCC1 decreases below VSYS_LO, the device enters BACKUP state.
When the device transitions from the ACTIVE state to the BACKUP state, all active SMPS
and LDO regulators, except LDOVRTC, are disabled simultaneously. When operating with a
16.384-MHz crystal, the regulators are immediately disabled after VCC1 becomes less than
VSYS_LO. When operating without a crystal, a 180-µs deglitch time occurs after VCC1
becomes less than VSYS_LO and before the regulators are disabled. The VSYS_LO level is
OTP programmable.
NOTE
For silicon revision 1.3 or earlier, when operating without a crystal, transitioning from the
ACTIVE state to the BACKUP state using VSYS_LO while the outputs are active must
always be followed by a POR event to make sure the device is reset properly. See
Section 6.3.10 to identify the silicon version in the device.
VSYS_MON: During power up, the VSYS_HI OTP value is used as a threshold for the VSYS_MON
comparator which is gating the PMIC start-up (as a threshold for transition from OFF to
ACTIVE state). The VSYS_MON comparator monitors the VCC_SENSE terminal. After
power up, software can configure the comparator threshold in the VSYS_MON register.
Figure 6-27 shows a block diagram of the system comparators.
‘5‘ TEXAS INSTRUMENTS
OTP bits
VCC1
VSYS_LO
VSYS_LO
VCC_SENSE
VSYS_MON
VSYS_HI VSYS_MON
VSYS_LO
INT
STATE OFF ACTIVE / SLEEP BACKUP
VBUS_SENSE
VBUS_DET
VBUS_WKUP_UP
VSYS_MON
Default VSYS_HI
Register bits
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Figure 6-27. System Comparators
To use comparators in the system:
• The VSYS_LO and VSYS_HI thresholds are defined in the OTP. Software cannot change these levels.
• After start-up, the VSYS_MON comparator is automatically disabled. Software can select a new
threshold level using the VSYS_MON register and enable the comparator.
• In order for the same coding on the rising and falling edge, the VSYS_MON comparator does not
include hysteresis and therefore can generate multiple interrupts when the voltage level is at the
threshold level. New interrupt generation has a 125-μs debounce time which allows the software to
mask the interrupt and update the threshold level or disable the comparator before receiving a new
interrupt.
Figure 6-28 shows additional details on the VSYS_MON comparator. When the VSYS_MON comparator
is enabled, and the internal buffer is bypassed, input impedance at the VCC_SENSE terminal is 500 kΩ
(typical). When the comparators are disabled, the VCC_SENSE terminal is at high impedance mode. If
GPADC is enabled to measure channel 6 or channel 7, 40 kΩis added in parallel to the corresponding
comparator. See Table 6-3 for the GPADC input range.
‘5‘ TEXAS INSTRUMENTS
discharge
PD O
t (ms)
R (k ) C ( F) 3
: P u
VCC_SENSE
VSYS_MON
GPADC_IN7
HIGH_VCC_SENSE
0 -> buffer bypassed (not enabled)
1 -> buffer enabled, bypass disbaled (Hi-Z at SENSE input)
VCC1
GPADC
Scale down,
divide by 4
HIGH_VCC_SENSE
0
1
10KŸ
30KŸ
500KŸ Default VSYS_HI
VSYS_MON
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To enable system voltage sensing above 5.25 V, an external resistive divider can be used. Internal buffers
are enabled by setting OTP bit HIGH_VCC_SENSE = 1 to provide high impedance for the external
resistive dividers. The maximum input level for the internal buffer is VCC1 – 1 V.
Figure 6-28. VSYS_MON Comparator Details
6.4.11.1 Generating a POR
NOTE
This section applies to silicon revisions 1.3 or earlier. Newer silicon revisions do not have this
requirement because the VCC is continuously sampled. See Section 6.3.10 to identify the
silicon version in the device.
To generate a POR from a falling VCC, VCC is sampled every 1 ms and compared to the POR threshold. In
case VCC is discharged and resupplied quickly, a POR may not be reliably generated if VCC crosses the
POR threshold between samples. Another way to generate POR is to discharge the LDOVRTC regulator
to 0 V after VCC is removed. With no external load, this could take seconds for the LDOVRTC output to
discharge to 0 V. The PMIC should not be restarted after VCC is removed but before LDOVRTC is
discharged to 0 V. If necessary, TI recommends adding a pulldown resistor from the LDOVRTC output to
GND with a minimum of 3.9 kΩto speed up the LDOVRTC discharge time. For more details, refer to POR
Generation in TPS65903x and TPS6591x Devices.
The value of the pulldown resistor should be chosen based on the desired discharge time and acceptable
current draw in the OFF state, but no greater than 0.5 mA. Use Equation 7 to calculate the pulldown
resistor based on the desired discharge time.
where
• tdischarge = discharge time of the VRTC output
• RPD = pulldown resistance from the VRTC output to GND
l TEXAS INSTRUMENTS PD
PD PD
1.8 V
IR
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• CO= output capacitance on the VRTC line (typically 2.2 µF) (7)
Because LDOVRTC is always on when VCC is supplied, additional current is drawn through the pulldown
resistor. The output current of LDOVRTC while the PMIC is in OFF state should not exceed 0.5 mA. Use
Equation 8 to calculate the pulldown current.
where
• IPD = current through the pulldown resistor
• RPD = pulldown resistance from the VRTC regulator (8)
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Application and ImplementationCopyright © 2013–2019, Texas Instruments Incorporated
7 Application and Implementation
NOTE
Information in the following applications sections is not part of the TI component
specification, and TI does not warrant its accuracy or completeness. TI’s customers are
responsible for determining suitability of components for their purposes. Customers should
validate and test their design implementation to confirm system functionality.
7.1 Application Information
The TPS659038-Q1 and TPS659039-Q1 devices are integrated power management integrated circuits
(PMIC), both available in a 169-pin, 0.8-mm pitch, 12-mm × 12-mm nFBGA package. The devices are
designed specifically for automotive applications. Both devices have seven configurable step-down
converter rails, with the ability to combine power rails and supply up to 9 A of output current in multi-phase
mode. The TPS659038-Q1 device also has eleven external LDOs, while TPS659039-Q1 device has 6
external LDOs. Both devices also come with a 12-bit GPADC with three external channels, eight
configurable GPIOs, two I2C interface channels or one SPI interface channel, a real-time clock module
with calendar function, a PLL for external clock sync and phase delay capability, and a programmable
power sequencer and control for supporting different processors and applications.
As both TPS659038-Q1 and TPS659039-Q1 devices are highly integrated PMIC devices, it is very
important that customers should take necessary actions to ensure the PMIC is operating under the
recommended operating conditions to ensure desired performance from the device. Additional cooling
strategies may be necessary to maintain the junction temperature below maximum limit allowed for the
device. To minimize the interferences when turning on a power rail while the device is in operation,
optimal PCB layout and grounding strategy are essential and are recommended in Section 9. In addition,
customer may take steps such as turning on additional rails only when the systems is operating in light
load condition.
Details on how to use this device in automotive infotainment or digital cluster applications are described
throughout this device specification. The following sections provides the typical application use case with
the recommended external components and layout guidelines. A design checklist for the TPS659038-Q1
and TPS659039-Q1 devices is also available on which provides application design guidance and cross
checks.
7.2 Typical Application
Following the typical application schematic and the list of recommended external components will allow
the TPS65903x-Q1 device to achieve accurate and stable regulation with its SMPS and LDO outputs.
These devices are internally compensated and have been designed to operate most effectively with the
component values listed inTable 7-2. Deviating from these values is possible but is highly discouraged.
l TEXAS INSTRUMENTS lLLLLLLLillLi
Processor
TPS659038-Q1
TPS659039-Q1
PWRON
LDO4 (3)
0.3 A
VDD_RTC
OSC, slicer, DPLL
SMPS12
6 A
MPU
SMPS45
4 A
GPU & IVA
FDBK
FDBK
FDBK_GND
FDBK_GND
SMPS6
3 A CORE
SMPS8
1A
1.8-V IO
SMPS7
1.8 V, 2 A
DSPEVE
SMPS9
3.3 V, 1 A
I2C1_SCL_SCK
I2C1_SDA_SDI
I2C2_SCL_SCE
CNTL I2C
I2C2_SDA_SDO
INT
PREQ1
NSLEEP
RESET_OUT
BOOT0
RPWRON (1)
POWERGOOD
REGEN1
GPIO_1
GPIO_2
GPIO_4
GPIO_5
RESET_IN (1)
NRESWARM
CLK32KGO
BOOT1
VBUS
LDO9
1 V, 50 mA
LDOLN
1.8 V, 50 mA
LDOUSB_IN2
PORZ
USB PHY
3V3
SYSEN
1
CLK32KGO1V8
SR I2C
INT
NRESWARM
32-kHz IN
ENABLE1 (1)
POWERDOWN
GPIO_7
1.8-V IO
VSYS
VSYS
GPIO_6 SYSEN
2
GPADC_IN0 (2)
GPADC_IN1 (2)
GPADC_IN2 (2)
GPADC_VREF (1)
VIO_IN
VCC1
VCC_SENSE
VBAT_SENSE
VSYS
VBUS
LDO7_LDOUSB_IN
LDO12_IN
LDO6_IN
LDO58_IN
LDO34_IN
LDOLN_IN
LDO9_IN
FDBK
3.3-V buck
3V3
DDR supply
VSYS
VSYS
VSYS
3.3-V Serial Interfaces
VSYS
LDO7 (3)
0.2 A
LDO6 (3)
0.2 A
LDO5 (3)
0.2 A
LDO8 (3)
0.17 A
LDOUSB
3.25 V, 0.1 A
LDOVRTC
1.8 V, 25 mA VDDA_RTC
LDO2
3.3 V, 0.3 A
LDO1
1.p V, 0.3 A
LDO3
3 V, 0.3 A
Digital Core
RTC IO
VSYS
1.8-V Serial Interfaces
External
Peripheral
External
Peripheral
External
Peripheral
External
Peripheral
External
Peripheral
VBUSDET GPIO_1
POWERHOLD GPIOx
USB PHY
SMPS3
1.8 V,3 A DDR3
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(1) Input can be left floating if not used.
(2) Input can be left floating if not used.
(3) Only available on the TPS659038-Q1 device.
Figure 7-1. Application Schematic
l TEXAS INSTRUMENTS E US E IIIII 15: I I I"I I I I‘I I
SMPS1_IN
SMPS1_SW
SMPS1_GND
SMPS2_IN
SMPS2_SW
SMPS2_GND
SMPS3_IN
SMPS3_SW
SMPS3_FDBK
SMPS3_GND
SMPS4_IN
SMPS4_SW
SMPS4_5_FDBK
SMPS4_GND
SMPS5_IN
SMPS5_SW
SMPS5_GND
INT
BOOT0
BOOT1
PWRON
RPWRON
GPIO_1
GPIO_2
RESET_IN
OSC16MIN
OSC16MOUT
CLK32KGO
GPADC_IN0
GPADC_IN1
GPADC_IN2
GPADC_VREF
RC
32 kHz
Internal
RC
oscillator
Output
buffers
16-MHz
oscillator
12-bit
SD-ADC
Multiplexer
LDOVANA_OUT
LDOVANA
LDOVRTC_OUT
LDOVRTC
Registers
Programmable power
sequencer controller
ECO
PWM
DVS
Switch ON or OFF
RTC
Interrupt handler (24 channels)
Thermal
monitoring
SMPS6_IN
SMPS6_SW
SMPS6_FDBK
SMPS6_GND
SMPS3
3 A
[Multi or
Stand-
alone]
SMPS4
2 A
(DVS)
[Master]
SMPS5
2 A
(DVS)
[Slave]
SMPS6
2 A
SMPS7_IN
SMPS7_SW
SMPS7_FDBK
SMPS7_GND
SMPS7
2 A
SMPS8_IN
SMPS8_SW
SMPS8_FDBK
SMPS8_GND
SMPS8
1 A
SMPS9_IN
SMPS9_SW
SMPS9_FDBK
SMPS9_GND
SMPS9
1 A
SMPS4_5_FDBK_GND
I2C1_SDA_SDI
PWRDOWN
NRESWARM
I2C1_SCL_CLK
I2C2_SDA_SDO
I2C2_SCL_SCE
RESET_OUT
Thermal shutdown
Hot die detection
(DVS)
(DVS)
OTP controller
OTP memory
DFT
WDT
JTAG
I2C CNTL,
I2C DVS
or SPI
POWERGOOD
OSC16MCAP
VCC1
VSYS_LO
VSYS_MON
POR
SMPS1
3 A
(DVS)
[Slave]
SMPS2
3 A
(DVS)
[Master] SMPS1_2_FDBK_GND
EN
VSEL
RAMP
EN
VSEL
ENABLE1
NSLEEP SMPS1_2_FDBK
GPIO_0
GPIO_3
GPIO_4
GPIO_5
GPIO_6
GPIO_7
REGEN1
POWERHOLD
SYSEN2
SYSEN1
TPS659038-Q1
GPIO
VCC1
REGEN2
VBUSDET
VCC_SENSE
Dual-
phases
Triple-
phases
Dual-
phases
Control
inputs
Internal
interrupt
events
Control
outputs
SYNCDCDC
VBUS_SENSE
VBUS_WKUP
TESTV
VIO_IN
VPROG
Test and program
VCC_SENSE2
PwrMgmt
VIO_GND
VCC_SENSE
VCC1
VPROG
VCC internal supply
VBUS
CLK32KGO1V8
Triple-
phases
[Multi or
Stand-
alone]
TPS659039-Q1
VBG
REFGND1 Reference
and
bias
Grounds
PBKG
GND_ANA
GND_DIG
GND_ANA
GND_ANA
GND_ANA
GND_ANA
LDO2_OUT
LDO3_OUT
LDO4_OUT
LDO5_OUT
LDO6_IN
LDO6_OUT
LDO7_OUT
LDO1
300 mA
LDO1_OUT
LDOLN_IN
LDOLN_OUT
LDO8_OUT
LDO9_IN
LDO9_OUT
LDO2
300 mA LDO3
300 mA LDO4(1)
300 mA LDO5(1)
200 mA LDO6(1)
200 mA LDO7(1)
2
LDO8(1)
170 mA
LDO9
50 mA
SDIO
LDOUSB
1
LDOUSB_IN2
LDOLN
50 mA
LDOUSB_OUT
VSEL
EN
VSEL
EN
VSEL
EN
VSEL
EN
VSEL
EN
VSEL
EN
VSEL
EN
VSEL
EN
VSEL
EN
VSEL
EN
VSEL
EN
Bypass
LDO12_IN
LDO34_IN
LDO58_IN
LDO7_LDO
USB_IN
00 mA
00 mA
VCC1
EN
VSEL
RAMP
EN
VSEL
RAMP
EN
VSEL
RAMP
EN
VSEL
EN
VSEL
C30 C32 C33 C35 C36 C38 C34
C31C3 C4 C5C2
VSYS/VPREREGULATED(VPRE)
C1 C39 C41
C29
LDOSDIO
LDOLN
VAUX4
VAUX3
VAUX2
VAUX1
VPHY3
VPHY2
VPHY1
VPHY0
VSYS
VSYS
VSYS
VSYS
L2
VSYS
L3
L4
C16
L6
L7
C10
C12
C14
C19
C23
L8
C25 C26
VSYS
L9
C27
VSYS
L10
VSYS
L11
VSYS
C11, C13
C20, C24
C42 C43
C28
C44 C45
Y1
Application
processor
GPIO signals
and controls
External power request
R2
R3
NTC
(Optional)
R1
External power on
C9
C22C21
C18
C40 C37
C29 C6
C8
VIO
C17
VBUS
VSYS
VSYS
VSYS
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(1) Only available on the TPS659038-Q1 device.
Figure 7-2. Typical Application Schematic
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7.2.1 Design Requirements
For this design example, use the parameters listed in Table 7-1.
Table 7-1. Design Parameters
DESIGN PARAMETER O9039A344IZWSRQ1
Supply voltage 3.3 V to 5 V
Switching frequency 2.2 MHz
SMPS123 voltage 1.1 V
SMPS123 current 9 A
SMPS45 voltage 1.06 V
SMPS45 current 4 A
SMPS6 voltage 1.06 V
SMPS6 current 3 A
SMPS7 voltage 1.06 V
SMPS7 current 2 A
SMPS8 voltage 1.06 V
SMPS8 current 1 A
SMPS9 voltage 1.8 V
SMPS9 current 1 A
LDO1 voltage 3.3 V
LDO1 current 300 mA
LDO2 voltage 3.3 V
LDO2 current 300 mA
LDO3 voltage 1.8 V
LDO3 current 200 mA
LDO9 voltage 1.05 V
LDO9 current 50 mA
LDOLN voltage 1.8 V
LDOLN current 50 mA
LDOUSB voltage 3.3 V
LDOUSB current 100 mA
l TEXAS INSTRUMENTS
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7.2.2 Detailed Design Procedure
7.2.2.1 Recommended External Components
(1) The tank capacitors filter the VSYS/VCC1 input voltage of the LDO and SMPS core architectures.
(2) Component is used on validation boards.
(3) For an AEC-Q200 grade 1-µH inductor, the DFE252012PD-1R0M is available from the manufacturer Toko.
Table 7-2. Recommended External Components for Automotive Usage
REFERENCE
COMPONENTS COMPONENT MANUFACTURER PART NUMBER VALUE EIA SIZE CODE SIZE (mm) CHOICE MASS PRODUCTION
INPUT POWER SUPPLIES EXTERNAL COMPONENTS
C7, C8 VSYS and VCC1 tank
capacitor(1) Murata GCM21BR70J106KE22 10 µF, 6V3 0805 2 × 1.25 × 1.25 Available(2)
C6 Decoupling capacitor Murata GCM155R71C104KA55 100 nF, 16 V 0402 1 × 0.5 × 0.5 Available(2)
CRYSTAL OSCILLATOR EXTERNAL COMPONENTS
Y1 Crystal Kyocera CX8045GB16384H0HEQZ1 16.384 MHz — 8 × 4.5 × 1.8 Available
C21, C22 Crystal decoupling Murata GCM1555C1H100JA16 10 pF, 50 V 0402 1 × 0.5 × 0.5 Available(2)
C18 Crystal supply
decoupling Murata GCM188R70J225KE22 2.2 µF, 6V3 0603 1.6 × 0.8 × 0.8 Available(2)
BANDGAP EXTERNAL COMPONENTS
C9 Capacitor Murata GCM155R71C104KA55 100 nF, 16 V 0402 1 × 0.5 × 0.5 Available(2)
SMPS EXTERNAL COMPONENTS
C10, C12, C14, C19,
C23, C26, C27, C43,
C45 Input capacitor Murata GCM21BC71A475MA73 4.7 µF, 10 V 0805 2 × 1.25 × 1.25 Available(2)
C11, C13, C16, C20,
C24, C25, C28, C42,
C44
Output Capacitance for
all SMPS Murata GCM32ER70J476KE19 47 µF, 6.3 V 1210 3.2 × 2.5 × 2.5 Available(2)
L2, L3, L4, L6, L7, L8,
L9, L10, L11 Inductor (BUCK)(3) Vishay IHLP1616ABER1R0M11 1 µH 4.45 × 4.1 × 1.2 Good efficiency at high
load Available
LDO EXTERNAL COMPONENTS
C1, C2, C3, C4, C5 Input capacitor Murata GCM188R70J225KE22 2.2 µF, 6V3 0603 1.6 × 0.8 × 0.8 Available(2)
C29, C30, C31, C32,
C33, C34, C35, C36,
C37, C38, C39, C40,
C41
Output capacitor Murata GCM188R70J225KE22 2.2 µF, 6V3 0603 1.6 × 0.8 × 0.8 Available(2)
VBUS EXTERNAL COMPONENTS
C17 VBUS decoupling
capacitor Murata GCM155R71C104KA55 100 nF 16 V 0402 1.6 × 0.8 × 0.8 Available(2)
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7.2.2.2 SMPS Input Capacitors
All SMPS inputs need an input decoupling capacitor to minimize input ripple voltage. It is recommended to
use a 10-V, 4.7-µF capacitor for each SMPS. Depending on the input voltage of the SMPS, a 6.3-V or 10-
V capacitor can be used. See Table 7-2 for the specific part number of the input capacitor that is
recommended.
For optimal performance, the input capacitors should be placed as close to the SMPS input balls as
possible. See Section 9.1 for more information about component placement.
7.2.2.3 SMPS Output Capacitors
All SMPS outputs need an output capacitor to hold up the output voltage during a load step or changes to
the input voltage. To ensure stability across the entire switching frequency range, the TPS659038-Q1 and
TPS659039-Q1 devices require an output capacitance value between 33 µF and 57 µF. To meet this
requirement across temperature and DC bias voltage, it is recommended to use a 47-µF capacitor for
each SMPS. It is important to remember that each SMPS needs an output capacitor, not just each output
rail. For example, SMPS12 is a dual phase regulator and an output capacitor is required for the SMPS1
output and the SMPS2 output. Note, this requirement excludes any capacitance seen at the load and only
refers to the capacitance seen close to the device. Additional capacitance placed near the load can be
supported, but the end application or system should be evaluated for stability. See Table 7-2 for the
specific part number of the output capacitor that is recommended.
7.2.2.4 SMPS Inductors
Again, to ensure stability across the entire switching frequency range, it is recommended to use a 1-µH
inductor on each SMPS. It is important to remember that each SMPS needs an inductor, not just each
output rail. For example, SMPS12 is a dual phase regulator and an inductor is required for the
SMPS1_SW balls and the SMPS2_SW balls. See Table 7-2 for the specific part number of the inductor
that is recommended.
7.2.2.5 LDO Input Capacitors
All LDO inputs need an input decoupling capacitor to minimize input ripple voltage. It is recommended to
use a 2.2-µF capacitor for each LDO. Depending on the input voltage of the LDO, a 6.3-V or 10-V
capacitor can be used. SeeTable 7-2 for the specific part number of the input capacitor that is
recommended.
For optimal performance, the input capacitors should be placed as close to the LDO input balls as
possible. See Section 9.1 for more information about component placement.
7.2.2.6 LDO Output Capacitors
All LDO outputs need an output capacitor to hold up the output voltage during a load step or changes to
the input voltage. Using a 2.2-µF capacitor for each LDO output is recommended. Note, this requirement
excludes any capacitance seen at the load and only refers to the capacitance seen close to the device.
Additional capacitance placed near the load can be supported, but the end application or system should
be evaluated for stability. See Table 7-2 for the specific part number of the output capacitor that is
recommended.
7.2.2.7 VCC1
VCC1 is the supply for the analog input voltage of the device. This pin requires a 10-µF decoupling
capacitor.
Texas Instruments recommends to always power down the TPS65903x-Q1 before removing power from
VCC1. If the input voltage to the device is removed while the device is ACTIVE, the device will shut off
when VCC1 reaches the VSYS_LO threshold. As mentioned in the Section 6.4.11 section, once VCC1
reaches VSYS_LO, there is about 180 us delay before all the output rails are disabled simultaneously.
There are two scenarios to consider in the system-level design in the event of unexpected loss of power.
l TEXAS INSTRUMENTS
VIN
(12 V)
PMIC
VCC
ENABLE
GND
Buck
PGOOD
5 V
VIN
(5 V)
PMIC
VCC
ENABLE
Supervisor
GND
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7.2.2.7.1 Meeting the Power Down Sequence
To prevent a sequencing violation, it is important to block reverse current and implement a disable signal
to the PMIC. A Schottky diode can block reverse current when the input is removed. Additionally,
capacitors can help maintain the input voltage level while the power-down sequence occurs. Depending
on the system design, there are a couple ways to implement a disable signal.
For a system where the TPS65903x-Q1 is powered by the system input voltage, a supervisor can be used
to create a logic signal, indicating if the power is at a good level. An example of this solution is shown in
Figure 7-3.
Figure 7-3. Supporting Uncontrolled Power Down When the PMIC is Supplied by the System Input
Voltage
An alternative solution is possible when a pre-regulator is present. In the case of the pre-regulator, the
pre-regulator output capacitance can also act as the energy storage to maintain VCC1 for the necessary
time. The total supply capacitance should be calculated to support the worst-case leakage current during
power down so that the voltage is maintained until the power-down sequence completes. Figure 7-4
shows an example of this configuration.
Figure 7-4. Supporting Uncontrolled Power Down when the PMIC is Supplied by a Preregulator
To determine the capacitance needed at the output of the pre-regulator, use Equation 9. This equation is
used to ensure that the power down sequence is complete before the device is disabled.
C = I × ΔT / (VCC1 – VSYS_LO)
where
• C is total capacitance on VCC1, including pre-regulator output capacitance and PMIC input
capacitance
• I is the total current on the PMIC input supply
•ΔT is the time it takes the power-down sequence to complete
• VCC1 is the voltage at the VCC1 pin
• VSYS_LO is the threshold where the device is disabled (9)
7.2.2.7.2 Maintaining Sufficient Input Voltage
In the event of high loading during loss of input voltage, there is a risk to go below the voltage level
necessary for the internal logic of the device to work properly before the device is disabled. This means
that when the VCC1 voltage supply level becomes lower than the VSYS_LO threshold, the input voltage
may continue dropping to very low voltages during the 180 us ±10% delay before the device is disabled.
1.8 V minimum
SMPSx_IN
VCCA
SMPSx_SW
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If a large input voltage drop occurs before the device is disabled, the internal logic can no longer properly
drive the FETs of the SMPS, and it is possible that the high-side FET and low-side FET of the SMPS are
on at the same time. In the event that the high-side and low-side FETs for an SMPS are on at the same
time, there is a direct path from SMPSx_IN to SMPSx_GND, allowing cross-conduction and possible
damage of the device.
In order to prevent damage or irregular switching behavior, it is important that the voltage at the
SMPSx_IN pin stays above 1.8 V, including negative transients, before the device is disabled. The
minimum voltage seen at the SMPSx_IN pin is dependent on VCC1 and the PCB inductance between the
SMPSx_IN pin and the input capacitor. Use Equation 10 to determine the minimum capacitance needed
on VCC1 to ensure that the device continues switching properly before it is disabled.
C = I × ΔT / (VSYS_LO – VCC1MIN)
where
• C is total capacitance on VCC1, including pre-regulator output capacitance and PMIC input
capacitance
• I is the total current on the PMIC input supply
•ΔT is the maximum debounce time after VCC1 = VSYS_LO before the device switches off (198us)
• VSYS_LO is the threshold where the device is disabled
• VCC1MIN is the minimum VCC1 voltage to keep the SMPSx_IN transients above 1.8 V (10)
When measuring the SMPSx_IN and VCC1 during power down, use active differential probes and a high
resolution oscilloscope (4GS/sec or more). VCC1 can be measured over the 10uF input capacitor.
However, SMPSx_IN must be measured at the pin in order to measure the transients on this rail
accurately. To measure SMPSx_IN, place the negative lead of the differential probe at a nearby GND,
such as the GND of the SMPSx_IN input capacitor. Place the positive lead of the differential probe as
close as possible to the SMPSx_IN pin. With this set up, verify that SMPSx_IN, including the ripple on this
signal, does not drop below 1.8V before the SMPS stops switching. See Figure 7-5 for an example of how
to take this measurement. For ways to decrease the amplitude of the transient spikes, see Table 9-1 for
recommended parasitic inductance requirements.
Figure 7-5. Waveform of SMPSx_IN Transients
7.2.2.8 VIO_IN
VIO_IN is the supply for the digital circuits inside the device. This ball requires a 0.1-µF decoupling
capacitor.
l TEXAS INSTRUMENTS G <]% |:i=""><7; gnd="" gnd="">
2.2 µF
6.3 V
GND
10 pF
10 pF
C1
A3
A2
V1
16.384 MHz
GNDGND
OSC16MCAP
OSC16MIN
OSC16MOUT
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7.2.2.9 16-MHz Crystal
The TPS659038-Q1 and TPS659039-Q1 have the ability to accept a 16-MHz crystal input. Providing the
16-MHz crystal input to the device allows the output of a stable and accurate 32-kHz clock to be used by
the applications processor. The crystal input is divided down by 500 internally to produce the 32-kHz
output clock. The crystal should be connected to the device as shown in Figure 7-6.
Figure 7-6. Crystal Input Configuration
As shown in Figure 7-6, the OSC16MCAP pin requires a 2.2-µF 6.3-V filtering capacitor near the ball.
Also, the crystal requires between 9 pF and 11 pF of load capacitance on both terminals. To meet this
requirement, using two 10-pF capacitors is recommended. See Table 7-2 for the specific load capacitors
that are recommended.
The 16-MHz crystal is not required for operation of the TPS659038-Q1 and TPS659039-Q1 devices. The
OSC16M_CFG OTP bit can be set to disable the 16-MHz crystal completely, and enable the following 2
alternative options for system clock generation:
1. A 32-kHz square wave can be supplied to the OSC16MIN pin. This option is typically used in
applications where the processor requires an accurate system clock and there is one already available
in the system. In that case, the available 32-kHz clock can be provided to the PMIC and added to the
boot sequence as an output. In this configuration, the OSC16MOUT and OSC16MCAP pins can be left
floating, and the internal 16-MHz oscillator is bypassed. Bypassing the 16-MHz oscillator results in a
lower quiescent current.
2. If the application does not require an accurate system clock for the processor, then providing one to
the PMIC is not required. This option produces a lower quiescent current as seen in Section 5. In this
configuration, the OSC16MIN pin should be grounded, while the OSC16MOUT and OSCMCAP pins
can be left floating. Lastly, the GATE_RESET_OUT OTP bit should be used to allow the device to
power up without the presence of the 16.384-MHz crystal nor the 32-kHz clock input.
If the OSC16M_CFG OTP bit is set to 0, a 16-MHz crystal must be present for the proper operation of the
device.
7.2.2.10 GPADC
Instructions on how to perform a software conversion with the GPADC:
1. Enable software conversion mode – GPADC_SW_SELECT.SW_CONV_EN
2. Select the channel to convert – GPADC_SW_SELECT.SW_CONV0_SEL
– For channel 0, set up the current source in the GPADC_CTRL1 register if needed.
3. For minimum latency, the GPADC can be set to always on (instead of default enabled from conversion
request) by GPADC_CTRL1.GPADC_FORCE.
4. Unmask software conversion interrupt – INT3_MASK.GPADC_EOC_SW
5. Start conversion – GPADC_SW_SELECT.SW_START_CONV0.
6. An interrupt is generated at the end of the conversion INT3_STATUS.GPADC_EOC_SW.
7. Read conversion result – GPADC_SW_CONV0_MSB and GPADC_SW_CONV0_LSB
8. Expected result = dec(GPADC_SW_CONV0_MSB[3:0].GPADC_SW_CONV0_LSB[7:0])/ 4096 × 1.25
l TEXAS INSTRUMENTS
Output Current (A)
Load Regulation (%)
0 1.5 3 4.5 6 7.5 9
-0.2
-0.16
-0.12
-0.08
-0.04
0
0.04
0.08
0.12
0.16
0.2
D011
VO = 1.05 V
VO = 1.2 V
Output Current (A)
Load Regulation (%)
0 1 2 3 4 5 6
-0.2
-0.16
-0.12
-0.08
-0.04
0
0.04
0.08
0.12
0.16
0.2
D011D012
VO = 1.05 V
VO = 1.2 V
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× scalar
Instructions on how to perform an auto conversion with the GPADC:
1. Select the channel to convert – GPADC_AUTO_SELECT.AUTO_CONV0_SEL
2. Configure auto conversion frequency – GPADC_AUTO_CTRL.COUNTER_CONV
3. Set the threshold level for comparison – GPADC_THRESH_CONV0_MSB.THRESH_CONV0_MSB,
GPADC_THRESH_CONV0_LSB.THRESH_CONV0_LSB
– Level = expected voltage threshold / (1.25 × scalar) × 4096 (in hexadecimal)
4. Set if the interrupt is triggered when conversion is above or below threshold –
GPADC_THRESH_CONV0_MSB.THRESH_CONV0_POL
5. Triggering the threshold level can also be programmed to generate shutdown –
GPADC_AUTO_CTRL.SHUTDOWN_CONV0
6. Unmask AUTO_CONV_0 interrupt – INT3_MASK.GPADC_AUTO_0
7. Enable AUTO CONV0 – GPADC_AUTO_CTRL.AUTO_CONV0_EN
8. When selected channel crosses programmed threshold, interrupt is generated –
INT3_STATUS.GPADC_AUTO_0
9. Conversion results are available – GPADC_AUTO_CONV0_MSB, GPADC_AUTO_CONV0_LSB
10. If shutdown was enabled, chip switches off after SWOFF_DLY, unless interrupt is cleared
The example above is for CONV0; a similar procedure applies to CONV1.
7.2.3 Application Curves
VI= 3.8 V ƒS= 2.2 MHz
Figure 7-7. SMPS Load Regulation for 9-A Triple Phase
VI= 3.8 V ƒS= 2.2 MHz
Figure 7-8. SMPS Load Regulation for 6-A Dual Phase
l TEXAS INSTRUMENTS 02
VO (20 mV/div, AC coupled)
IO (500 mA/div)
0.5 mA to 500 mA load step,
tr = tf = 1 µs
Time = 2.5 ms/div
VO (10 mV/div, AC coupled)
IO (500 mA/div) 0.5 mA to 500 mA
load step,
tr = tf = 100 ns
Time = 5 ms/div
Output Current (A)
Load Regulation (%)
0 0.4 0.8 1.2 1.6 2
-0.2
-0.16
-0.12
-0.08
-0.04
0
0.04
0.08
0.12
0.16
0.2
D015
VO = 1.05 V
VO = 1.2 V
VO = 1.8 V
VO = 2.5 V
Output Current (A)
Load Regulation (%)
0 0.2 0.4 0.6 0.8 1
-0.2
-0.16
-0.12
-0.08
-0.04
0
0.04
0.08
0.12
0.16
0.2
D016
VO = 1.05 V
VO = 1.2 V
VO = 1.8 V
VO = 2.5 V
Output Current (A)
Load Regulation (%)
0 0.5 1 1.5 2 2.5 3
-0.2
-0.16
-0.12
-0.08
-0.04
0
0.04
0.08
0.12
0.16
0.2
D014
VO = 1.05 V
VO = 1.2 V
VO = 1.8 V
VO = 2.5 V
Output Current (A)
Load Regulation (%)
0 0.8 1.6 2.4 3.2 4
-0.2
-0.16
-0.12
-0.08
-0.04
0
0.04
0.08
0.12
0.16
0.2
D013
VO = 1.05 V
VO = 1.2 V
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VI= 3.8 V ƒS= 2.2 MHz
Figure 7-9. SMPS Load Regulation for 4-A Dual Phase
VI= 3.8 V ƒS= 2.2 MHz
Figure 7-10. SMPS Load Regulation for 3-A Single Phase
VI= 3.8 V ƒS= 2.2 MHz
Figure 7-11. SMPS Regulation for 2-A Single Phase
VI= 3.8 V ƒS= 2.2 MHz
Figure 7-12. SMPS Load Regulation for 1-A Single Phase
VI= 3.5 V VO= 1.05 V ƒS= 2.2 Hz
Figure 7-13. Typical SMPS Load Transient Response for SMPS8
and SMPS9
VI= 3.5 V VO= 1.05 V ƒS= 2.2 Hz
Figure 7-14. Typical SMPS Load Transient Response for
SMPS12, SMPS3, SMPS45, SMPS6 and SMPS7
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8 Power Supply Recommendations
The TPS659038-Q1 and TPS659039-Q1 devices are designed to work with an analog supply voltage
range of 3.135 V to 5.25 V. The input supply should be well regulated and connected to the VCC1 pin, as
well as SMPS and LDO input pins with appropriate bypass capacitors as recommended in the Figure 7-1
diagram. If the input supply is located more than a few inches from the device, additional capacitance may
be required in addition to the recommended input capacitors at the VCC1 pin and the SMPS and LDO
input pins.
9 Layout
9.1 Layout Guidelines
As in every switch-mode-supply design, general layout rules apply:
• Use a solid ground-plane for power-ground (PGND)
• Use an independent ground for Logic, LDOs and Analog (AGND)
• Connect those Grounds at a star-point ideally underneath the IC.
• Place input capacitors as close as possible to the input-balls of the IC. This is paramount and more
important than the output-loop!
• Place the inductor and output capacitor as close as possible to the phase node (or switch-node) of the
IC.
• Keep the loop-area formed by Phase-node, Inductor, output-capacitor and PGND as small as possible.
• For traces and vias on power-lines, keep inductance and resistance as small as possible by using wide
traces, avoid switching layers but if needed, use plenty of vias.
The goal of the previously listed guidelines is a layout that minimizes emissions, maximizes EMI-immunity,
and maintains a safe operating area for the IC.
To minimize the spiking at the phase-node for both, high-side (VIN – SWx) as well as low-side (SWx –
PGND), the decoupling of VIN is paramount. Appropriate decoupling and thorough layout should ensure
that the spikes never exceed 7V across the high-side and low-side FETs.
The guidelines shown in Figure 9-1 regarding parasitic inductance and resistance are recommended.
l TEXAS INSTRUMENTS :
SMPSx_IN
SMPSx_GND
SMPSx_SW
SMPSx_SW
For multiple
capacitors, keep the
parasitic resistance as
small as possible
among capacitors
Parasitic inductance: < 1 nH
Parasitic resistance: < 2 PŸ
Parasitic resistance:
As small as possible to
get best efficiency
Parasitic Inductance: < 1 nH
Parasitic resistance: < 3 PŸ
Connection to power plane
Parasitic resistance:
As small as possible to get best
efficiency
Parasitic inductance: < 1 nH
Parasitic resistance: < 2 PŸ
95
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LayoutCopyright © 2013–2019, Texas Instruments Incorporated
Figure 9-1. Parasitic Inductance and Resistance
Table 9-1 lists the maximum allowable parasitic (inductance measured at 100 MHz) and the achievable
values in an optimized layout.
Table 9-1. Maximum Allowable Parasitic
CONNECTION MAXIMUM ALLOWABLE
INDUCTANCE MAXIMUM ALLOWABLE
RESISTANCE OPTIMIZED LAYOUT
(EVM) INDUCTANCE OPTIMIZED LAYOUT (EVM)
RESISTANCE
PowerPlane – CIN n/a N/A for SOA, keep small for
efficiency N/A N/A for SOA, keep small for
efficiency
CIN – SMPSx_IN 1 nH 3 mΩSMPS1 0.533 nH SMPS1 1.77 mΩ
SMPS2 0.465 nH SMPS2 1.22 mΩ
SMPS3 0.494 nH SMPS3 1.37 mΩ
SMPS4 0.472 nH SMPS4 1.23 mΩ
SMPS5 0.517 nH SMPS5 1.27 mΩ
SMPS6 0.518 nH SMPS6 1.69 mΩ
SMPS7 0.501 nH SMPS7 1.27 mΩ
SMPS8 0.509 nH SMPS8 1.42 mΩ
SMPS9 0.491 nH SMPS9 1.4 mΩ
CIN – SMPSx_GND 1 nH 2 mΩSMPS1 0.552 nH SMPS1 1.21 mΩ
SMPS2 0.583 nH SMPS2 0.8 mΩ
SMPS3 0.668 nH SMPS3 0.93 mΩ
SMPS4 0.57 nH SMPS4 0.81 mΩ
SMPS5 0.577 nH SMPS5 0.76 mΩ
SMPS6 0.608 nH SMPS6 1.13 mΩ
SMPS7 0.646 nH SMPS7 0.83 mΩ
SMPS8 0.67 nH SMPS8 0.73 mΩ
SMPS9 0.622 nH SMPS9 0.82 mΩ
l TEXAS INSTRUMENTS
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Layout Copyright © 2013–2019, Texas Instruments Incorporated
Table 9-1. Maximum Allowable Parasitic (continued)
CONNECTION MAXIMUM ALLOWABLE
INDUCTANCE MAXIMUM ALLOWABLE
RESISTANCE OPTIMIZED LAYOUT
(EVM) INDUCTANCE OPTIMIZED LAYOUT (EVM)
RESISTANCE
SMPSx_SW – Inductor N/A N/A for SOA, keep small for
efficiency N/A SMPS1 1.9 mΩ
SMPS2 0.89 mΩ
SMPS3 1.99 mΩ
SMPS4 0.93 mΩ
SMPS5 1.37 mΩ
SMPS6 1.11 mΩ
SMPS7 1.17 mΩ
SMPS8 1.35 mΩ
SMPS9 0.88 mΩ
Inductor – COUT n/a N/A for SOA, keep small for
efficiency N/A N/A for SOA, keep small for
efficiency
COUT – GND Use dedicated GND plane to
keep inductance low mΩSMPS1 0.552 nH SMPS1 1.21 mΩ
SMPS2 0.583 nH SMPS2 0.8 mΩ
SMPS3 0.668 nH SMPS3 0.93 mΩ
SMPS4 0.57 nH SMPS4 0.81 mΩ
SMPS5 0.577 nH SMPS5 0.76 mΩ
SMPS6 0.608 nH SMPS6 1.13 mΩ
SMPS7 0.646 nH SMPS7 0.83 mΩ
SMPS8 0.67 nH SMPS8 0.73 mΩ
SMPS9 0.622 nH SMPS9 0.82 mΩ
GND(CIN) – GND(COUT) Use dedicated GND plane to
keep inductance low mΩUse dedicated GND plane to
keep inductance low mΩ
Texas Instruments recommends to measure the voltages across the high-side FET (voltage at SMPSx_IN
vs. SMPSx_SW) and the low-side FET (SMPSx_SW vs. SMPSx_GND) with a high-bandwidth high-
sampling rate scope with a low-capacitance probe (ideally a differential probe). Measure the voltages as
close as possible to the IC-balls and verify the amplitude of the spikes. A small-loop-GND-connection to
the closest accessible SMPSx_GND (of the particular rail) is essential. Ideally, this measurement should
be performed during start-up of the respective SMPS-rail (to take in account the inrush-current) and at
high temperature.
When measuring the voltage difference between the SMPSx_IN and SMPSx_SW pins, there should be a
maximum of 7 V when measuring at the pins. Similarly, when measuring the voltage difference between
the SMPSx_SW and SMPSx_GND pins, there should be a maximum of 7 V when measuring at the pins.
For more information on cursor-positioning, see Figure 9-2 and Figure 9-3.
l TEXAS INSTRUMENTS J J l l cm mv n M on Dry: 2 $65!: u an mm A cm / 195v um mv n NI an flux 2 565/: u an flux/m A cm / ‘ 93v
7 V maximum
SMPSx_SW - SMPSx_GND
7 V maximum
SMPSx_IN - SMPSx_SW
97
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LayoutCopyright © 2013–2019, Texas Instruments Incorporated
Measure across the high-side FET (SMPSx_IN – SMPSx_SW) as close to the IC as possible. The preferred
measurement is with a differential probe. The negative side of the probe should be at SMPSx_SW and the positive
side of the probe should measure SMPSx_IN. As shown in this image, the voltage across the high-side FET should
not exceed 7 V. Repeat the measurement for all SMPSs in use.
Figure 9-2. Measuring the High-side FET (Differentially)
Measure across the low-side FET (SMPSx_SW – SMPSx_GND) as close to the IC as possible. The preferred
measurement is with a differential probe. The negative side of the probe should be at SMPSx_GND and the positive
side of the probe should measure SMPSx_SW. As shown in this image, the voltage across the low-side FET should
not exceed 7 V.Repeat the measurement for all SMPSs in use.
Figure 9-3. Measuring the Low-side FET (Differentially)
l TEXAS INSTRUMENTS mamas
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Layout Copyright © 2013–2019, Texas Instruments Incorporated
9.2 Layout Example
Figure 9-4,Figure 9-5,Figure 9-6, and Figure 9-7 show the actual placement and routing on the EVM.
Figure 9-4. Top Layer Overview of Inductor Placement
l TEXAS INSTRUMENTS
COUT
CIN
CIN
COUT
COUT
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LayoutCopyright © 2013–2019, Texas Instruments Incorporated
Figure 9-5. Bottom Layer Overview of Input and Output Capacitor Placement
Figure 9-6. Top Layer Zoomed View of SMPS123 SW Connections to Inductors
l TEXAS INSTRUMENTS
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Layout Copyright © 2013–2019, Texas Instruments Incorporated
Figure 9-7. Bottom Layer Zoomed View of SMPS123 Input and Output Capacitor Layout
l TEXAS INSTRUMENTS
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Device and Documentation SupportCopyright © 2013–2019, Texas Instruments Incorporated
10 Device and Documentation Support
10.1 Device Support
10.1.1 Third-Party Products Disclaimer
TI'S PUBLICATION OF INFORMATION REGARDING THIRD-PARTY PRODUCTS OR SERVICES DOES
NOT CONSTITUTE AN ENDORSEMENT REGARDING THE SUITABILITY OF SUCH PRODUCTS OR
SERVICES OR A WARRANTY, REPRESENTATION OR ENDORSEMENT OF SUCH PRODUCTS OR
SERVICES, EITHER ALONE OR IN COMBINATION WITH ANY TI PRODUCT OR SERVICE.
10.1.2 Device Nomenclature
The following acronyms and terms are used in this data sheet. For a detailed list of terms, acronyms, and
definitions, see the TI glossary.
ADC Analog-to-digital converter
APE Application processor engine
DVS Digital voltage scaling
GPIO General-purpose input-output
LDO Low-dropout voltage linear regulator
PM Power management
PMIC Power-management integrated circuit
PSRR Power-supply rejection ratio
RTC Real-time clock
SMPS Switched-mode power supply
OTP One-time EPROM
10.2 Documentation Support
10.2.1 Related Documentation
For related documentation see the following:
• Texas Instruments, Adaptive (Dynamic) Voltage (Frequency) Scaling—Motivation and Implementation
application report
• Texas Instruments, Automotive Off-Battery Infotainment Processor Power Reference Design
• Texas Instruments, Guide to Using the GPADC in TPS65903x and TPS6591x Devices
• Texas Instruments, POR Generation in TPS65903x and TPS6591x Devices
• Texas Instruments, TPS659038-Q1 and TPS659039-Q1 EVM User's Guide
• Texas Instruments, TPS659038-Q1 and TPS659039-Q1 Register Map
10.3 Related Links
The table below lists quick access links. Categories include technical documents, support and community
resources, tools and software, and quick access to order now.
Table 10-1. Related Links
PARTS PRODUCT FOLDER ORDER NOW TECHNICAL
DOCUMENTS TOOLS &
SOFTWARE SUPPORT &
COMMUNITY
TPS659038-Q1 Click here Click here Click here Click here Click here
TPS659039-Q1 Click here Click here Click here Click here Click here
l TEXAS INSTRUMENTS
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Mechanical, Packaging, and Orderable Information Copyright © 2013–2019, Texas Instruments Incorporated
10.4 Receiving Notification of Documentation Updates
To receive notification of documentation updates, navigate to the device product folder on ti.com. In the
upper right corner, click on Alert me to register and receive a weekly digest of any product information that
has changed. For change details, review the revision history included in any revised document.
10.5 Community Resources
The following links connect to TI community resources. Linked contents are provided "AS IS" by the
respective contributors. They do not constitute TI specifications and do not necessarily reflect TI's views;
see TI's Terms of Use.
TI E2E™ Online Community The TI engineer-to-engineer (E2E) community was created to foster
collaboration among engineers. At e2e.ti.com, you can ask questions, share knowledge,
explore ideas and help solve problems with fellow engineers.
Design Support TI's Design Support Quickly find helpful E2E forums along with design support tools
and contact information for technical support.
10.6 Trademarks
ECO-mode, E2E are trademarks of Texas Instruments.
All other trademarks are the property of their respective owners.
10.7 Electrostatic Discharge Caution
This integrated circuit can be damaged by ESD. Texas Instruments recommends that all integrated circuits be handled with
appropriate precautions. Failure to observe proper handling and installation procedures can cause damage.
ESD damage can range from subtle performance degradation to complete device failure. Precision integrated circuits may be more
susceptible to damage because very small parametric changes could cause the device not to meet its published specifications.
10.8 Glossary
TI Glossary This glossary lists and explains terms, acronyms, and definitions.
11 Mechanical, Packaging, and Orderable Information
The following pages include mechanical packaging and orderable information. This information is the most
current data available for the designated devices. This data is subject to change without notice and
revision of this document. For browser-based versions of this data sheet, refer to the left-hand navigation.
11.1 Package Materials Information
Moisture Sensitivity Level Target: JEDEC MSL3 at 260°C
Table 11-1. Package Characteristics
Device Names TPS659038-Q1 TPS659039-Q1
Package Type nFBGA nFBGA
Orderable Names See See
Size (mm) 12 mm × 12 mm 12 mm × 12 mm
Pitch ball array (mm) 0.8 0.8
ViP (via-in-pad) No No
Array grid 13 × 13, not depopulated 13 × 13, not depopulated
Number of balls 169 169
Thickness (mm)
(maximum height including balls) 1.4 1.4
Moisture sensitivity level target Level-3-260C-168 HR Level-3-260C-168 HR
Others Green, ROHS compliant Green, ROHS compliant
I TEXAS INSTRUMENTS Samples Samples Samples Samples Samples Samples Samples Samples
PACKAGE OPTION ADDENDUM
www.ti.com 10-Dec-2020
Addendum-Page 1
PACKAGING INFORMATION
Orderable Device Status
(1)
Package Type Package
Drawing Pins Package
Qty Eco Plan
(2)
Lead finish/
Ball material
(6)
MSL Peak Temp
(3)
Op Temp (°C) Device Marking
(4/5)
Samples
O9038A342IZWSRQ1 ACTIVE NFBGA ZWS 169 1000 RoHS & Green SNAGCU Level-3-260C-168 HR -40 to 85 TPS659038
OTP 42 1.3
O9038A352IZWSRQ1 ACTIVE NFBGA ZWS 169 1000 RoHS & Green SNAGCU Level-3-260C-168 HR -40 to 85 TPS659038
OTP 52 1.3
O9039A385IZWSRQ1 ACTIVE NFBGA ZWS 169 1000 RoHS & Green SNAGCU Level-3-260C-168 HR -40 to 85 TPS659039
OTP 85 1.3
O9039A385IZWSTQ1 ACTIVE NFBGA ZWS 169 250 RoHS & Green SNAGCU Level-3-260C-168 HR -40 to 85 TPS659039
OTP 85 1.3
O9039A387IZWSRQ1 ACTIVE NFBGA ZWS 169 1000 RoHS & Green SNAGCU Level-3-260C-168 HR -40 to 85 TPS659039
OTP 87 1.3
O9039A387IZWSTQ1 ACTIVE NFBGA ZWS 169 250 RoHS & Green SNAGCU Level-3-260C-168 HR -40 to 85 TPS659039
OTP 87 1.3
O9039A389IZWSRQ1 ACTIVE NFBGA ZWS 169 1000 RoHS & Green SNAGCU Level-3-260C-168 HR -40 to 85 TPS659039
OTP 89 1.3
O9039A389IZWSTQ1 ACTIVE NFBGA ZWS 169 250 RoHS & Green SNAGCU Level-3-260C-168 HR -40 to 85 TPS659039
OTP 89 1.3
(1) The marketing status values are defined as follows:
ACTIVE: Product device recommended for new designs.
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design.
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.
OBSOLETE: TI has discontinued the production of the device.
(2) RoHS: TI defines "RoHS" to mean semiconductor products that are compliant with the current EU RoHS requirements for all 10 RoHS substances, including the requirement that RoHS substance
do not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, "RoHS" products are suitable for use in specified lead-free processes. TI may
reference these types of products as "Pb-Free".
RoHS Exempt: TI defines "RoHS Exempt" to mean products that contain lead but are compliant with EU RoHS pursuant to a specific EU RoHS exemption.
Green: TI defines "Green" to mean the content of Chlorine (Cl) and Bromine (Br) based flame retardants meet JS709B low halogen requirements of <=1000ppm threshold. Antimony trioxide based
flame retardants must also meet the <=1000ppm threshold requirement.
(3) MSL, Peak Temp. - The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature.
(4) There may be additional marking, which relates to the logo, the lot trace code information, or the environmental category on the device.
I TEXAS INSTRUMENTS
PACKAGE OPTION ADDENDUM
www.ti.com 10-Dec-2020
Addendum-Page 2
(5) Multiple Device Markings will be inside parentheses. Only one Device Marking contained in parentheses and separated by a "~" will appear on a device. If a line is indented then it is a continuation
of the previous line and the two combined represent the entire Device Marking for that device.
(6) Lead finish/Ball material - Orderable Devices may have multiple material finish options. Finish options are separated by a vertical ruled line. Lead finish/Ball material values may wrap to two
lines if the finish value exceeds the maximum column width.
Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information
provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and
continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals.
TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited information may not be available for release.
In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI to Customer on an annual basis.
I TEXAS INSTRUMENTS REEL DIMENSIONS TAPE DIMENSIONS 7 “K0 '«Pt» Reel Dlameter AD Dimension designed to accommodate the component Width ED Dimension designed to accommodate the component iengtn K0 Dimension designed to accommodate the component Ihlckness 7 W OveraH wtdlh loe Gamer tape i P1 Pitch between successive cavtty centers f T Reel Width (W1) QUADRANT ASSIGNMENTS FOR PIN 1 ORIENTATION IN TAPE OOODOODD ,,,,,,,,,,, ‘ User Direcllon 0' Feed Sprocket Hoies Pockel Quadrants
TAPE AND REEL INFORMATION
*All dimensions are nominal
Device Package
Type Package
Drawing Pins SPQ Reel
Diameter
(mm)
Reel
Width
W1 (mm)
A0
(mm) B0
(mm) K0
(mm) P1
(mm) W
(mm) Pin1
Quadrant
O9039A385IZWSRQ1 NFBGA ZWS 169 1000 330.0 24.4 12.35 12.35 2.3 16.0 24.0 Q1
O9039A385IZWSTQ1 NFBGA ZWS 169 250 330.0 24.4 12.35 12.35 2.3 16.0 24.0 Q1
O9039A387IZWSRQ1 NFBGA ZWS 169 1000 330.0 24.4 12.35 12.35 2.3 16.0 24.0 Q1
O9039A387IZWSTQ1 NFBGA ZWS 169 250 330.0 24.4 12.35 12.35 2.3 16.0 24.0 Q1
O9039A389IZWSRQ1 NFBGA ZWS 169 1000 330.0 24.4 12.35 12.35 2.3 16.0 24.0 Q1
O9039A389IZWSTQ1 NFBGA ZWS 169 250 330.0 24.4 12.35 12.35 2.3 16.0 24.0 Q1
PACKAGE MATERIALS INFORMATION
www.ti.com 12-Jun-2018
Pack Materials-Page 1
I TEXAS INSTRUMENTS TAPE AND REEL BOX DIMENSIONS
*All dimensions are nominal
Device Package Type Package Drawing Pins SPQ Length (mm) Width (mm) Height (mm)
O9039A385IZWSRQ1 NFBGA ZWS 169 1000 336.6 336.6 41.3
O9039A385IZWSTQ1 NFBGA ZWS 169 250 336.6 336.6 41.3
O9039A387IZWSRQ1 NFBGA ZWS 169 1000 336.6 336.6 41.3
O9039A387IZWSTQ1 NFBGA ZWS 169 250 336.6 336.6 41.3
O9039A389IZWSRQ1 NFBGA ZWS 169 1000 336.6 336.6 41.3
O9039A389IZWSTQ1 NFBGA ZWS 169 250 336.6 336.6 41.3
PACKAGE MATERIALS INFORMATION
www.ti.com 12-Jun-2018
Pack Materials-Page 2
0000000000000 0000000000000 709090000090907 0000000000000\ 0000000000000 0000 46696 O O O O ¢5® ¢5@
www.ti.com
PACKAGE OUTLINE
C
1.4 MAX
0.45
0.35 TYP
9.6
TYP
9.6 TYP
0.8 TYP
0.8 TYP
169X 0.55
0.45
A12.1
11.9 B
12.1
11.9
(1.2) TYP
(1.2) TYP
(0.9)
NFBGA - 1.4 mm max heightZWS0169A
PLASTIC BALL GRID ARRAY
4221886/C 05/2021
NOTES:
1. All linear dimensions are in millimeters. Any dimensions in parenthesis are for reference only. Dimensioning and tolerancing
per ASME Y14.5M.
2. This drawing is subject to change without notice.
11
BALL A1 CORNER
SEATING PLANE
BALL TYP 0.12 C
0.15 C A B
0.05 C
SYMM
SYMM
BALL A1 CORNER
C
D
E
F
G
H
J
K
L
M
12345678910
A
B
12 13
N
SCALE 1.100
v
www.ti.com
EXAMPLE BOARD LAYOUT
169X ( 0.4) (0.8) TYP
(0.8) TYP
( 0.4)
METAL
0.05 MAX
SOLDER MASK
OPENING
METAL UNDER
SOLDER MASK
( 0.4)
SOLDER MASK
OPENING
0.05 MIN
NFBGA - 1.4 mm max heightZWS0169A
PLASTIC BALL GRID ARRAY
4221886/C 05/2021
NOTES: (continued)
3. Final dimensions may vary due to manufacturing tolerance considerations and also routing constraints.
For information, see Texas Instruments literature number SSZA002 (www.ti.com/lit/ssza002).
SYMM
SYMM
LAND PATTERN EXAMPLE
SCALE:8X
12345678910 11
B
A
C
D
E
F
G
H
J
K
L
M
N
12 13
NON-SOLDER MASK
DEFINED
(PREFERRED)
SOLDER MASK DETAILS
NOT TO SCALE
SOLDER MASK
DEFINED
4 0000000000000 000000m000000 000000 000000 0000000000000 0000000000000 OOOOOOmVOOOOOO 7® AYQé ® $®é JO‘ ® AW Ol®\v( @ OOOOOOATOOOOOO 0000006000000 4 000000000000 000000 000000 rfioooomoooooo 00000000
www.ti.com
EXAMPLE STENCIL DESIGN
(0.8) TYP
(0.8) TYP ( 0.4) TYP
NFBGA - 1.4 mm max heightZWS0169A
PLASTIC BALL GRID ARRAY
4221886/C 05/2021
NOTES: (continued)
4. Laser cutting apertures with trapezoidal walls and rounded corners may offer better paste release.
SYMM
SYMM
SOLDER PASTE EXAMPLE
BASED ON 0.15 mm THICK STENCIL
SCALE:8X
12345678910 11
B
A
C
D
E
F
G
H
J
K
L
M
N
12 13
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