Datenblatt für STB10LN80K5 von STMicroelectronics

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February 2016

DocID027750 Rev 2

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This is information on a product in full production.

www.st.com

STB10LN80K5

N-channel 800 V, 0.55 Ω typ., 8 A MDmesh™ K5

Power MOSFET in a D²PAK package

Datasheet - production data

Figure 1: Internal schematic diagram

Features

Order code

VDS

RDS(on) max.

STB10LN80K5

800 V

0.63 Ω

8 A

 Industry’s lowest RDS(on) x area

 Industry’s best figure of merit (FoM)

 Ultra-low gate charge

 100% avalanche tested

 Zener-protected

Applications

 Switching applications

Description

This very high voltage N-channel Power

MOSFET is designed using MDmesh™ K5

technology based on an innovative proprietary

vertical structure. The result is a dramatic

reduction in on-resistance and ultra-low gate

charge for applications requiring superior power

density and high efficiency.

Table 1: Device summary

Order code

Marking

Package

Packing

STB10LN80K5

10LN80K5

D2PAK

Tape and reel

TAB

D²PAK

Contents

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Contents

1 Electrical ratings ............................................................................. 3

2 Electrical characteristics ................................................................ 4

2.2 Electrical characteristics (curves) ...................................................... 6

3 Test circuits ..................................................................................... 9

4 Package information ..................................................................... 10

4.1 D2PAK package information ........................................................... 10

4.2 Packing information ......................................................................... 13

5 Revision history ............................................................................ 15

STB10LN80K5

Electrical ratings

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1 Electrical ratings

Table 2: Absolute maximum ratings

Symbol

Parameter

Value

Unit

VGS

Gate-source voltage

± 30

Drain current (continuous) at TC = 25 °C

Drain current (continuous) at TC = 100 °C

ID(1)

Drain current (pulsed)

PTOT

Total dissipation at TC = 25 °C

110

dv/dt (2)

Peak diode recovery voltage slope

4.5

V/ns

dv/dt (3)

MOSFET dv/dt ruggedness

Operating junction temperature range

- 55 to 150

°C

Tstg

Storage temperature range

Notes:

(1)Pulse width limited by safe operating area.

(2)ISD ≤ 8 A, di/dt ≤ 100 A/µs; VDS peak < V(BR)DSS

(3)VDS ≤ 640 V

Table 3: Thermal data

Symbol

Parameter

Value

Unit

Rthj-case

Thermal resistance junction-case

1.14

°C/W

Rthj-pcb(1)

Thermal resistance junction-pcb

°C/W

Notes:

(1)When mounted on FR-4 board of 1 inch² , 2 oz Cu

Table 4: Avalanche characteristics

Symbol

Parameter

Value

Unit

IAR

Avalanche current, repetitive or not repetitive (pulse width

limited by Tjmax)

2.7

EAS

Single pulse avalanche energy (starting Tj = 25 ° C,

ID = IAR, VDD = 50 V)

240

Electrical characteristics

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2 Electrical characteristics

TC = 25 ° C unless otherwise specified

Table 5: On/off-state

Symbol

Parameter

Test conditions

Min.

Typ.

Max.

Unit

V(BR)DSS

Drain-source breakdown voltage

VGS = 0 V, ID = 1 mA

800

IDSS

Zero gate voltage drain current

VGS = 0 V, VDS = 800 V

µA

VGS = 0 V, VDS = 800 V

TC = 125 °C

µA

IGSS

Gate body leakage current

VDS = 0 V, VGS = ± 20 V

± 10

µA

VGS(th)

Gate threshold voltage

VDS = VGS, ID = 100 µA

RDS(on)

Static drain-source on-resistance

VGS = 10 V, ID = 4 A

0.55

0.63

Table 6: Dynamic

Symbol

Parameter

Test conditions

Min.

Typ.

Max.

Unit

Ciss

Input capacitance

VDS = 100 V, f = 1 MHz,

VGS = 0 V

427

Coss

Output capacitance

Crss

Reverse transfer capacitance

0.25

Co(tr)(1)

Equivalent capacitance time

VDS = 0 to 640 V, VGS = 0

Co(er)(2)

Equivalent capacitance energy

Intrinsic gate resistance

f = 1 MHz , ID= 0 A

Ω

Total gate charge

VDD = 640 V, ID = 8 A

VGS= 10 V

See Figure 16: "Test

circuit for gate charge

behavior"

Qgs

Gate-source charge

4.2

Qgd

Gate-drain charge

Notes:

(1)Time related is defined as a constant equivalent capacitance giving the same charging time as Coss when VDS

increases from 0 to 80% VDSS

(2)Energy related is defined as a constant equivalent capacitance giving the same stored energy as Coss when

VDS increases from 0 to 80% VDSS

Table 7: Switching times

Symbol

Parameter

Test conditions

Min.

Typ.

Max.

Unit

td(on)

Turn-on delay time

VDD= 400 V, ID = 4 A, RG = 4.7 Ω

VGS = 10 V

See Figure 15: "Test circuit for

resistive load switching times"

and Figure 20: "Switching time

waveform"

11.8

Rise time

td(off)

Turn-off delay time

Fall time

STB10LN80K5

Electrical characteristics

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Table 8: Source-drain diode

Symbol

Parameter

Test conditions

Min.

Typ.

Max.

Unit

ISD

Source-drain current

ISDM(1)

Source-drain current

(pulsed)

VSD(2)

Forward on voltage

ISD = 8 A, VGS = 0 V

1.5

trr

Reverse recovery time

ISD = 8 A, di/dt = 100 A/µs,

VDD = 60 V

See Figure 17: "Test circuit for

inductive load switching and

diode recovery times"

350

Qrr

Reverse recovery charge

3.9

µC

IRRM

Reverse recovery current

22.5

trr

Reverse recovery time

ISD = 8 A, di/dt = 100 A/µs,

VDD = 60 V, Tj = 150 °C

See Figure 17: "Test circuit for

inductive load switching and

diode recovery times"

505

Qrr

Reverse recovery charge

µC

IRRM

Reverse recovery current

Notes:

(1)Pulse width limited by safe operating area

(2)Pulsed: pulse duration = 300 µ s, duty cycle 1.5%

Table 9: Gate-source Zener diode

Symbol

Parameter

Test conditions

Min.

Typ.

Max.

Unit

V(BR)GSO

Gate-source breakdown voltage

IGS= ± 1mA, ID= 0 A

The built-in back-to-back Zener diodes are specifically designed to enhance the ESD

performance of the device. The Zener voltage facilitates efficient and cost-effective device

integrity protection,thus eliminating the need for additional external componentry.

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Electrical characteristics

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2.2 Electrical characteristics (curves)

Figure 2: Safe operating area

Figure 3: Thermal impedance

Figure 4: Output characteristics

Figure 5: Transfer characteristics

Figure 6: Gate charge vs gate-source voltage

Figure 7: Static drain-source on-resistance

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STB10LN80K5

Electrical characteristics

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Figure 8: Capacitance variations

Figure 9: Normalized gate threshold voltage

vs temperature

Figure 10: Normalized on-resistance vs

temperature

Figure 11: Normalized V(BR)DSS vs temperature

Figure 12: Output capacitance stored energy

Figure 13: Source-drain diode forward

characteristics

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Electrical characteristics

STB10LN80K5

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DocID027750 Rev 2

Figure 14: Maximum avalanche energy vs starting TJ

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STB10LN80K5

Test circuits

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3 Test circuits

Figure 15: Test circuit for resistive load

switching times

Figure 16: Test circuit for gate charge

behavior

Figure 17: Test circuit for inductive load

switching and diode recovery times

Figure 18: Unclamped inductive load test

circuit

Figure 19: Unclamped inductive waveform

Figure 20: Switching time waveform

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Package information

STB10LN80K5

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4 Package information

In order to meet environmental requirements, ST offers these devices in different grades of

ECOPACK® packages, depending on their level of environmental compliance. ECOPACK®

specifications, grade definitions and product status are available at: www.st.com.

ECOPACK® is an ST trademark.

4.1 D2PAK package information

Figure 21: D²PAK (TO-263) type A package outline

0079457_A_rev22

STB10LN80K5

Package information

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Table 10: D²PAK (TO-263) type A package mechanical data

Dim.

Min.

Typ.

Max.

4.40

4.60

0.03

0.23

0.70

0.93

1.14

1.70

0.45

0.60

1.23

1.36

8.95

9.35

7.50

7.75

8.00

1.10

1.30

1.50

10.40

8.50

8.70

8.90

6.85

7.05

7.25

2.54

4.88

5.28

15.85

2.49

2.69

2.29

2.79

1.27

1.40

1.30

1.75

0.4

0°

8°

722 4. 7.5 * 254 4‘7 J 5.08 3.5 76.9 rompm

Package information

STB10LN80K5

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Figure 22: D²PAK (TO-263) recommended footprint (dimensions are in mm)

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STB10LN80K5

Package information

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4.2 Packing information

Figure 23: Tape outline

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Package information

STB10LN80K5

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DocID027750 Rev 2

Figure 24: Reel outline

Table 11: D²PAK tape and reel mechanical data

Tape

Reel

Dim.

Min.

Max.

Min.

Max.

10.5

10.7

330

15.7

15.9

1.5

1.6

12.8

13.2

1.59

1.61

20.2

1.65

1.85

24.4

26.4

11.4

11.6

100

4.8

5.0

30.4

3.9

4.1

11.9

12.1

Base quantity

1000

1.9

2.1

Bulk quantity

1000

0.25

0.35

23.7

24.3

STB10LN80K5

Revision history

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5 Revision history

Table 12: Document revision history

Date

Revision

Changes

04-May-2015

First release.

08-Feb-2016

Modified: Table 2: "Absolute maximum ratings", Table 3: "Thermal

data", Table 4: "Avalanche characteristics", Table 5: "On/off-state",

Table 7: "Switching times" and Table 8: "Source-drain diode"

Added: Section 3.1: "Electrical characteristics (curves)"

Datasheet promoted from preliminary data to production data

Minor text changes

STB10LN80K5

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