Datenblatt für CD54,74HCT573 von Texas Instruments

U Ordering & Technical Design & Suppon s documentation 3 (raming . . quahly development I TEXAS INSTRUMENTS «57>— LE 11 D c1 H 19 1D 2 101 1D I v \—\—/ To Seven other Channels
CDx4HCT573 Octal Transparent D-Type Latches With 3-State Outputs
1 Features
• 4.5-V to 5.5-V VCC operation
• Wide operating temperature range of −55°C to
125°C
• Balanced propagation delays and transition times
• Standard outputs drive up to 10 LS-TTL loads
• Significant power reduction compared to LS-TTL
Logic ICs
• Inputs are TTL-voltage compatible
2 Description
The ’HCT573 devices are octal transparent D-type
latches. When the latch-enable (LE) input is high, the
Q outputs follow the data (D) inputs. When LE is low,
the Q outputs are latched at the logic levels of the D
inputs.
Device Information
PART NUMBER PACKAGE(1) BODY SIZE (NOM)
CD74HCT573M SOIC (20) 12.80 mm × 7.50 mm
CD74HCT573DBR SSOP (20) 7.20 mm × 5.30 mm
CD74HCT573E PDIP (20) 25.40 mm × 6.35 mm
CD54HCT573F CDIP (20) 26.92 mm × 6.92 mm
(1) For all available packages, see the orderable addendum at
the end of the data sheet.
Functional Block Diagram
CD54HCT573, CD74HCT573
SCLS455E – FEBRUARY 2001 – REVISED JUNE 2022
An IMPORTANT NOTICE at the end of this data sheet addresses availability, warranty, changes, use in safety-critical applications,
intellectual property matters and other important disclaimers. PRODUCTION DATA.
I TEXAS INSTRUMENTS
Table of Contents
1 Features............................................................................1
2 Description.......................................................................1
3 Revision History.............................................................. 2
4 Pin Configuration and Functions...................................3
5 Specifications.................................................................. 4
5.1 Absolute Maximum Ratings........................................ 4
5.2 Recommended Operating Conditions(1) .................... 4
5.3 Thermal Information....................................................4
5.4 Electrical Characteristics.............................................5
5.5 Timing Requirements..................................................5
5.6 Switching Characteristics ...........................................5
5.7 Operating Characteristics........................................... 5
6 Parameter Measurement Information............................ 6
7 Detailed Description........................................................7
7.1 Overview..................................................................... 7
7.2 Functional Block Diagram........................................... 7
7.3 Device Functional Modes............................................7
8 Power Supply Recommendations..................................8
9 Layout...............................................................................8
9.1 Layout Guidelines....................................................... 8
10 Device and Documentation Support............................9
10.1 Receiving Notification of Documentation Updates....9
10.2 Support Resources................................................... 9
10.3 Trademarks...............................................................9
10.4 Electrostatic Discharge Caution................................9
10.5 Glossary....................................................................9
11 Mechanical, Packaging, and Orderable
Information...................................................................... 9
3 Revision History
NOTE: Page numbers for previous revisions may differ from page numbers in the current version.
Changes from Revision D (January 2022) to Revision E (June 2022) Page
• Junction-to-ambient thermal resistance values increased. DW was 58 is now 109.1, DB was 70 is now 122.7,
N was 69 is now 84.6..........................................................................................................................................4
Changes from Revision C (May 2004) to Revision D (January 2022) Page
• Updated the numbering, formatting, tables, figures, and cross-references throughout the doucment to reflect
modern data sheet standards............................................................................................................................. 1
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SCLS455E – FEBRUARY 2001 – REVISED JUNE 2022 www.ti.com
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I TEXAS INSTRUMENTS OE[ 1D[ 20[ 30[ 4D[ 50[ 6D[ 7D[ 8D[ GNDE C omwmwth—n _. O
4 Pin Configuration and Functions
J, DB, N, or DW Package
20-Pin CDIP, SSOP, PDIP, SOIC
Top View
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SCLS455E – FEBRUARY 2001 – REVISED JUNE 2022
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TEXAS INSTRUMENTS
5 Specifications
5.1 Absolute Maximum Ratings
over operating free-air temperature range (unless otherwise noted)(1)
MIN MAX UNIT
VCC Supply voltage range –0.5 7 V
IIK Input clamp current(2) VI < 0 or VI > VCC ±20 mA
IOK Output clamp current(2) VO < 0 or VO > VCC ±20 mA
IOContinuous output drain current per output VO = 0 to VCC ±35 mA
IOContinuous output source or sink current per output VO = 0 to VCC ±25 mA
Continuous current through VCC or GND ±50 mA
TJJunction temperature 150 ℃
Tstg Storage temperature range –65 150 ℃
(1) Stresses beyond those listed under “absolute maximum ratings” may cause permanent damage to the device. These are stress ratings
only, and functional operation of the device at these or any other conditions beyond those indicated under “recommended operating
conditions" is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
(2) The input and output voltage ratings may be exceeded if the input and output current ratings are observed.
5.2 Recommended Operating Conditions(1)
TA = 25°C TA = −55°C to 125°C TA = −40°C to 85°C UNIT
MIN MAX MIN MAX MIN MAX
VCC Supply voltage 4.5 5.5 4.5 5.5 4.5 5.5 V
VIH High-level input voltage 2 2 2 V
VIL Low-level input voltage 0.8 0.8 0.8 V
VIInput voltage VCC VCC VCC V
VOOutput voltage VCC VCC VCC V
Δt/Δv Input transition rise or fall rate 500 500 500 ns
(1) All unused inputs of the device must be held at VCC or GND to ensure proper device operation. Refer to the TI application report,
Implications of Slow or Floating CMOS Inputs, literature number SCBA004.
5.3 Thermal Information
THERMAL METRIC
DW (SOIC) DB (SSOP) N (PDIP)
UNIT20 PINS 20 PINS 20 PINS
RθJA Junction-to-ambient thermal resistance(1) 109.1 122.7 84.6 °C/W
RθJC(top) Junction-to-case (top) thermal resistance 76 81.6 72.5 °C/W
RθJB Junction-to-board thermal resistance 77.6 77.5 65.3 °C/W
ψJT Junction-to-top characterization
parameter 51.5 46.1 55.3 °C/W
ψJB Junction-to-board characterization
parameter 77.1 77.1 65.2 °C/W
RθJC(bot) Junction-to-case (bottom) thermal
resistance N/A N/A N/A °C/W
(1) For more information about traditional and new thermal metrics, see the Semiconductor and IC package thermal metrics application
report.
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TEXAS INSTRUMENTS cc TA
5.4 Electrical Characteristics
over recommended operating free-air temperature range (unless otherwise noted)
PARAMETER TESTCONDITIONS VCC
TA = 25°C TA = −55°C to
125°C TA = −40°C to 85°C UNIT
MIN MAX MIN MAX MIN MAX
VOH VI = VIH or VIL
IOH = −20 μA 4.5 V 4.4 4.4 4.4 V
IOH = −6 mA 3.98 3.7 3.84
VOL VI = VIH or VIL
IOL = 20 μA 4.5 V 0.1 0.1 0.1 V
IOL = 6 mA 0.26 0.4 0.33
IIVI = VCC or 0 5.5 V ±0.1 ±1 ±1 μA
IOZ VO = VCC or 0 5.5 V ±0.5 ±10 ±5 μA
ICC VI = VCC or 0, IO = 0 5.5 V 8 160 80 μA
ΔICC (1)
OE input held at VCC− 2.1 V 4.5 V to
5.5 V 450 612.5 562.5 μA
Any D input held at VCC – 2.1 V 4.5 V to
5.5 V 108 147 135 μA
LE input held at VCC – 2.1 V 4.5 V to
5.5 V 234 318.5 292.5 μA
Ci10 10 10 pF
Co20 20 20 pF
(1) Additional quiescent supply current per input pin, TTL inputs high, 1 unit load. For dual-supply systems, theoretical worst-case (VI = 2.4
V, VCC = 5.5 V) specification is 1.8 mA.
5.5 Timing Requirements
over recommended operating free-air temperature range, VCC = 4.5 V (unless otherwise noted) (see Figure 6-1)
TA = 25°C TA = −55°C to 125°C TA = −40°C to 85°C UNIT
MIN MAX MIN MAX MIN MAX
twPulse duration, LE high 16 24 20 ns
tsu Setup time, data before LE ↓ 13 20 16 ns
thHold time, data after LE ↓ 10 15 13 ns
5.6 Switching Characteristics
over recommended operating free-air temperature range, VCC =4.5 V (unless otherwise noted) (see Figure 6-1)
PARAMETER FROM
(INPUT)
TO
(OUTPUT)
LOAD
CAPACITANCE
TA = 25°C TA = −55°C to
125°C TA = −40°C to 85°C UNIT
MIN MAX MIN MAX MIN MAX
tpd
DQ CL = 50 pF 35 53 44 ns
LE 35 53 44
ten OE Q CL = 50 pF 35 53 44 ns
tdis OE Q CL = 50 pF 35 53 44 ns
ttQ CL = 50 pF 12 18 15 ns
5.7 Operating Characteristics
VCC = 5 V, TA = 25℃
PARAMETER TYP UNIT
Cpd Power dissipation capacitance 53 pF
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From Output unau Ts: LOAD cmcun _ 3 v CLR 1,: v Input ________ l n v H I471,“ ‘ 3 v cm ¥ 1.: v 777777 o v VOLTAGE WAVEFORMS RECOVERY TIME ———————— a v L— ‘ o v I ‘ IPLII -H‘ II- IPHL —>‘ h—Phase I 30% 90% E T T VoII mp“, I 1.3 v I 1.3 v I A! F 'r I 4N HE ‘I‘ H- 'PIIL ->I H- IPLH —>\ v Omof-Pllm 50% 1.3 v 1,: v 90% o“ ouuun ‘ 1w. um 4,7 7 v 4 m a w w ‘1 VOLYAGE WAVEFORMS PROPAGA110N DELAV AND OUTPUT TRANSITION TIMES PARAMETER SI 52 lpzn Open closed 'en IPZL closed Open Isz Open Closed 'dis tpLz closed open I,“ or I. Open Open H7 Iw 4.! | | a v Input 1.: v 0 V VOLTAGE WAVEFORMS PULSE oummou VOLTAGE WAVEFORMS SETUP AND "OLD AND INPUT RISE AND FALL nMEs Output conlrol output wmlmn 2 (see Mm a) VOLTAGE WAVEFORMS OUTPUT ENABLE AND DISABLE TIMES
6 Parameter Measurement Information
A. CL includes probe and test-fixture capacitance.
B. Waveform 1 is for an output with internal conditions such that the output is low, except when disabled by the output control. Waveform 2
is for an output with internal conditions such that the output is high, except when disabled by the output control.
C. Phase relationships between waveforms were chosen arbitrarily. All input pulses are supplied by generators having the following
characteristics: PRR ≤ 1 MHz, ZO = 50 Ω, tr = 6 ns, tf = 6 ns.
D. For clock inputs, fmsx is measured with the input duty cycle at 50%.
E. The outputs are measured one at a time, with one input transition per measurement.
F. tPLZ and tPHZ are the same as tdis.
G. tPZL and tPZH are the same as ten.
H. tPLH and tPHL are the same as tpd.
Figure 6-1. Load Circuit and Voltage Waveforms
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I TEXAS INSTRUMENTS 1Q (Ti—(>— LE 11 D .— c1 g 19 1D 2 1D 7 v \_V_/ T0 Seven other Channels
7 Detailed Description
7.1 Overview
The ’HCT573 devices are octal transparent D-type latches. When the latch-enable (LE) input is high, the Q
outputs follow the data (D) inputs. When LE is low, the Q outputs are latched at the logic levels of the D inputs.
A buffered output-enable (OE) input can be used to place the eight outputs in either a normal logic state (high
or low) or the high-impedance state. In the high-impedance state, the outputs neither load nor drive the bus
lines significantly. The high-impedance state and increased drive provide the capability to drive bus lines without
interface or pullup components.
OE does not affect the internal operations of the latches. Old data can be retained or new data can be entered
while the outputs are in the high-impedance state.
To ensure the high-impedance state during power up or power down, OE should be tied to VCC through a pullup
resistor; the minimum value of the resistor is determined by the current-sinking capability of the driver.
7.2 Functional Block Diagram
7.3 Device Functional Modes
Table 7-1. Function Table
(each latch)
INPUTS OUTPUT Q
OE LE D
L H H H
L H L L
L L X Q0
H X X Z
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8 Power Supply Recommendations
The power supply can be any voltage between the minimum and maximum supply voltage rating located in the
Recommended Operating Conditions. Each VCC terminal should have a good bypass capacitor to prevent power
disturbance. A 0.1-μF capacitor is recommended for this device. It is acceptable to parallel multiple bypass caps
to reject different frequencies of noise. The 0.1-μF and 1-μF capacitors are commonly used in parallel. The
bypass capacitor should be installed as close to the power terminal as possible for best results.
9 Layout
9.1 Layout Guidelines
When using multiple-input and multiple-channel logic devices inputs must not ever be left floating. In many
cases, functions or parts of functions of digital logic devices are unused; for example, when only two inputs of a
triple-input AND gate are used or only 3 of the 4 buffer gates are used. Such unused input pins must not be left
unconnected because the undefined voltages at the outside connections result in undefined operational states.
All unused inputs of digital logic devices must be connected to a logic high or logic low voltage, as defined by the
input voltage specifications, to prevent them from floating. The logic level that must be applied to any particular
unused input depends on the function of the device. Generally, the inputs are tied to GND or VCC, whichever
makes more sense for the logic function or is more convenient.
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I TEXAS INSTRUMENTS Am
10 Device and Documentation Support
TI offers an extensive line of development tools. Tools and software to evaluate the performance of the device,
generate code, and develop solutions are listed below.
10.1 Receiving Notification of Documentation Updates
To receive notification of documentation updates, navigate to the device product folder on ti.com. Click on
Subscribe to updates to register and receive a weekly digest of any product information that has changed. For
change details, review the revision history included in any revised document.
10.2 Support Resources
TI E2E™ support forums are an engineer's go-to source for fast, verified answers and design help — straight
from the experts. Search existing answers or ask your own question to get the quick design help you need.
Linked content is provided "AS IS" by the respective contributors. They do not constitute TI specifications and do
not necessarily reflect TI's views; see TI's Terms of Use.
10.3 Trademarks
TI E2E™ is a trademark of Texas Instruments.
All trademarks are the property of their respective owners.
10.4 Electrostatic Discharge Caution
This integrated circuit can be damaged by ESD. Texas Instruments recommends that all integrated circuits be handled
with appropriate precautions. Failure to observe proper handling and installation procedures can cause damage.
ESD damage can range from subtle performance degradation to complete device failure. Precision integrated circuits may
be more susceptible to damage because very small parametric changes could cause the device not to meet its published
specifications.
10.5 Glossary
TI Glossary This glossary lists and explains terms, acronyms, and definitions.
11 Mechanical, Packaging, and Orderable Information
The following pages include mechanical, packaging, and orderable information. This information is the most
current data available for the designated devices. This data is subject to change without notice and revision of
this document. For browser-based versions of this data sheet, refer to the left-hand navigation.
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PACKAGE OPTION ADDENDUM
www.ti.com 13-Jul-2022
PACKAGING INFORMATION
Orderable Device Status
(1)
Package Type Package
Drawing Pins Package
Qty Eco Plan
(2)
Lead finish/
Ball material
(6)
MSL Peak Temp
(3)
Op Temp (°C) Device Marking
(4/5)
Samples
5962-8685601RA ACTIVE CDIP J 20 1 Non-RoHS
& Green SNPB N / A for Pkg Type -55 to 125 5962-8685601RA
CD54HCT573F3A Samples
CD54HCT573F ACTIVE CDIP J 20 1 Non-RoHS
& Green SNPB N / A for Pkg Type -55 to 125 CD54HCT573F Samples
CD54HCT573F3A ACTIVE CDIP J 20 1 Non-RoHS
& Green SNPB N / A for Pkg Type -55 to 125 5962-8685601RA
CD54HCT573F3A Samples
CD74HCT573DBR ACTIVE SSOP DB 20 2000 RoHS & Green NIPDAU Level-1-260C-UNLIM -55 to 125 HK573 Samples
CD74HCT573E ACTIVE PDIP N 20 20 RoHS &
Non-Green NIPDAU N / A for Pkg Type -55 to 125 CD74HCT573E Samples
CD74HCT573EE4 ACTIVE PDIP N 20 20 TBD Call TI Call TI -55 to 125 Samples
CD74HCT573M ACTIVE SOIC DW 20 25 RoHS & Green NIPDAU Level-1-260C-UNLIM -55 to 125 HCT573M Samples
CD74HCT573M96 ACTIVE SOIC DW 20 2000 RoHS & Green NIPDAU Level-1-260C-UNLIM -55 to 125 HCT573M Samples
CD74HCT573M96G4 ACTIVE SOIC DW 20 2000 RoHS & Green NIPDAU Level-1-260C-UNLIM -55 to 125 HCT573M Samples
(1) The marketing status values are defined as follows:
ACTIVE: Product device recommended for new designs.
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design.
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.
OBSOLETE: TI has discontinued the production of the device.
(2) RoHS: TI defines "RoHS" to mean semiconductor products that are compliant with the current EU RoHS requirements for all 10 RoHS substances, including the requirement that RoHS substance
do not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, "RoHS" products are suitable for use in specified lead-free processes. TI may
reference these types of products as "Pb-Free".
RoHS Exempt: TI defines "RoHS Exempt" to mean products that contain lead but are compliant with EU RoHS pursuant to a specific EU RoHS exemption.
Green: TI defines "Green" to mean the content of Chlorine (Cl) and Bromine (Br) based flame retardants meet JS709B low halogen requirements of <=1000ppm threshold. Antimony trioxide based
flame retardants must also meet the <=1000ppm threshold requirement.
(3) MSL, Peak Temp. - The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature.
(4) There may be additional marking, which relates to the logo, the lot trace code information, or the environmental category on the device.
Addendum-Page 1
TEXAS INSTRUMENTS
PACKAGE OPTION ADDENDUM
www.ti.com 13-Jul-2022
(5) Multiple Device Markings will be inside parentheses. Only one Device Marking contained in parentheses and separated by a "~" will appear on a device. If a line is indented then it is a continuation
of the previous line and the two combined represent the entire Device Marking for that device.
(6) Lead finish/Ball material - Orderable Devices may have multiple material finish options. Finish options are separated by a vertical ruled line. Lead finish/Ball material values may wrap to two
lines if the finish value exceeds the maximum column width.
Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information
provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and
continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals.
TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited information may not be available for release.
In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI to Customer on an annual basis.
OTHER QUALIFIED VERSIONS OF CD54HCT573, CD74HCT573 :
•Catalog : CD74HCT573
•Military : CD54HCT573
NOTE: Qualified Version Definitions:
•Catalog - TI's standard catalog product
•Military - QML certified for Military and Defense Applications
Addendum-Page 2
I-III
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PACKAGE OUTLINE
C
18X 0.65
2X
5.85
20X 0.38
0.22
8.2
7.4 TYP
SEATING
PLANE
0.05 MIN
0.25
GAGE PLANE
0 -8
2 MAX
B5.6
5.0
NOTE 4
A
7.5
6.9
NOTE 3
0.95
0.55
(0.15) TYP
SSOP - 2 mm max heightDB0020A
SMALL OUTLINE PACKAGE
4214851/B 08/2019
1
10
11
20
0.1 C A B
PIN 1 INDEX AREA
SEE DETAIL A
0.1 C
NOTES:
1. All linear dimensions are in millimeters. Any dimensions in parenthesis are for reference only. Dimensioning and tolerancing
per ASME Y14.5M.
2. This drawing is subject to change without notice.
3. This dimension does not include mold flash, protrusions, or gate burrs. Mold flash, protrusions, or gate burrs shall not
exceed 0.15 mm per side.
4. This dimension does not include interlead flash. Interlead flash shall not exceed 0.25 mm per side.
5. Reference JEDEC registration MO-150.
A 15
DETAIL A
TYPICAL
SCALE 2.000
“‘w“‘+“‘w“‘
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EXAMPLE BOARD LAYOUT
0.07 MAX
ALL AROUND 0.07 MIN
ALL AROUND
20X (1.85)
20X (0.45)
18X (0.65)
(7)
(R0.05) TYP
SSOP - 2 mm max heightDB0020A
SMALL OUTLINE PACKAGE
4214851/B 08/2019
NOTES: (continued)
6. Publication IPC-7351 may have alternate designs.
7. Solder mask tolerances between and around signal pads can vary based on board fabrication site.
LAND PATTERN EXAMPLE
EXPOSED METAL SHOWN
SCALE: 10X
SYMM
SYMM
1
10 11
20
15.000
METAL
SOLDER MASK
OPENING METAL UNDER
SOLDER MASK SOLDER MASK
OPENING
EXPOSED METAL
EXPOSED METAL
SOLDER MASK DETAILS
NON-SOLDER MASK
DEFINED
(PREFERRED)
SOLDER MASK
DEFINED
mi: 2.5%
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EXAMPLE STENCIL DESIGN
20X (1.85)
20X (0.45)
18X (0.65)
(7)
(R0.05) TYP
SSOP - 2 mm max heightDB0020A
SMALL OUTLINE PACKAGE
4214851/B 08/2019
NOTES: (continued)
8. Laser cutting apertures with trapezoidal walls and rounded corners may offer better paste release. IPC-7525 may have alternate
design recommendations.
9. Board assembly site may have different recommendations for stencil design.
SOLDER PASTE EXAMPLE
BASED ON 0.125 mm THICK STENCIL
SCALE: 10X
SYMM
SYMM
1
10 11
20
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MECHANICAL DATA N (R—PDlP-T“) PLASTIC DUAL—IN—LINE PACKAGE 16 P15 SHOWN PWS " A L . [NM 15 a 20 16 9 0 775 U 777 0 SZU '1 USE 3 , 1H HH HH r% r’H r"—1 r’H H1 1 A VAX “9‘69? (191591 (23,37) (25,92) 0 250 (6,50‘ A MN [1145‘ 0142‘ 0.350 new 3 O 240 (6.10), 15 92/ (1832/ (2 .59) (23,58) MSiUO‘ (A AA AA Ari AA AA AA R1 &. VAR1AT1CN M RR AC AD 1 B 0070( (17s) 0015 (111) A 0045 (1,111 g n > , ‘ -) 3.020 (0,51) MW w o 5 (0 35) 0200( 38) MAX f, ), Gnu E Home 1 1‘ 9 fix—1%)” 1 0125’ 1/111 4% 0010 (v.37 ) NOM 31a) U L»- J 0450 (13,92) MAX L 202‘ (0,53) » e c 015 (0,35) / \ a; 00‘s (0,Zb)® / \ 1 1 \\¥,// 11/18 Pm (My > @ 20 Pm vendor upho'v mom/r 17/7037 NO'FS A AH Mnec' mmensmr‘fi: B 1m: drawmq 1s sume m muss (m1111mevem) 0 change mm): nofice /c\ FuHs wumn JEDEC M57001, except 15 an: 20 p171 'r1111mLm body 1mm (01m A) A The 70 p171 and 15m} shmflder Md” 15 a ve'vdnr 0311071, eher NIH Dr 111 wkflh INSI'RUMENTS www.1i.com
DW0020A I
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PACKAGE OUTLINE
C
TYP
10.63
9.97
2.65 MAX
18X 1.27
20X 0.51
0.31
2X
11.43
TYP
0.33
0.10
0 - 8
0.3
0.1
0.25
GAGE PLANE
1.27
0.40
A
NOTE 3
13.0
12.6
B7.6
7.4
4220724/A 05/2016
SOIC - 2.65 mm max heightDW0020A
SOIC
NOTES:
1. All linear dimensions are in millimeters. Dimensions in parenthesis are for reference only. Dimensioning and tolerancing
per ASME Y14.5M.
2. This drawing is subject to change without notice.
3. This dimension does not include mold flash, protrusions, or gate burrs. Mold flash, protrusions, or gate burrs shall not
exceed 0.15 mm per side.
4. This dimension does not include interlead flash. Interlead flash shall not exceed 0.43 mm per side.
5. Reference JEDEC registration MS-013.
120
0.25 C A B
11
10
PIN 1 ID
AREA
NOTE 4
SEATING PLANE
0.1 C
SEE DETAIL A
DETAIL A
TYPICAL
SCALE 1.200
DW0020A
www.ti.com
EXAMPLE BOARD LAYOUT
(9.3)
0.07 MAX
ALL AROUND
0.07 MIN
ALL AROUND
20X (2)
20X (0.6)
18X (1.27)
(R )
TYP
0.05
4220724/A 05/2016
SOIC - 2.65 mm max heightDW0020A
SOIC
SYMM
SYMM
LAND PATTERN EXAMPLE
SCALE:6X
1
10 11
20
NOTES: (continued)
6. Publication IPC-7351 may have alternate designs.
7. Solder mask tolerances between and around signal pads can vary based on board fabrication site.
METAL
SOLDER MASK
OPENING
NON SOLDER MASK
DEFINED
SOLDER MASK DETAILS
SOLDER MASK
OPENING
METAL UNDER
SOLDER MASK
SOLDER MASK
DEFINED
DW0020A $$$$$fififiifi%
www.ti.com
EXAMPLE STENCIL DESIGN
(9.3)
18X (1.27)
20X (0.6)
20X (2)
4220724/A 05/2016
SOIC - 2.65 mm max heightDW0020A
SOIC
NOTES: (continued)
8. Laser cutting apertures with trapezoidal walls and rounded corners may offer better paste release. IPC-7525 may have alternate
design recommendations.
9. Board assembly site may have different recommendations for stencil design.
SYMM
SYMM
1
10 11
20
SOLDER PASTE EXAMPLE
BASED ON 0.125 mm THICK STENCIL
SCALE:6X
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