Datenblatt für

January 2008 Rev 5 1/53
1
STW81102
Multi-band RF frequency synthesizer with integrated VCOs
Features
■Integer-N frequency synthesizer
■Dual differential integrated VCOs with
automatic center frequency calibration:
– 3000 - 3620 MHz (direct output)
– 4000 - 4650 MHz (direct output)
– 1500 - 1810 MHz (internal divider by 2)
– 2000 - 2325 MHz (internal divider by 2)
– 750 - 905 MHz (internal divider by 4)
– 1000 - 1162.5 MHz (internal divider by 4)
■Excellent integrated phase noise
■Fast lock time: 150 µs
■Dual modulus programmable prescaler (16/17
or 19/20)
■2 programmable counters to achieve a
feedback division ratio from 256 to 65551
(prescaler 16/17) and from 361 to 77836
(prescaler 19/20).
■Programmable reference frequency divider (10
bits)
■Phase frequency comparator and charge pump
■Programmable charge pump current
■Digital lock detector
■Dual digital bus Interface: SPI and I2C bus with
3 bit programmable address (1100A2A1A0)
■3.3V power supply
■Power down mode (HW and SW)
■Small size exposed pad VFQFPN28 package
5x5x1.0mm
■Process: BICMOS 0.35 µm SiGe
Applications
■2.5G and 3G cellular infrastructure equipment
■CATV equipment
■Instrumentation and test equipment
■Other wireless communication systems
Description
The STMicroelectronics STW81102 is an
integrated RF synthesizer with voltage controlled
oscillators (VCOs). Showing high performance,
high integration, low power, and multi-band
performances, the STW81102 is a low-cost one-
chip alternative to discrete PLL and VCOs
solutions.
The STW81102 includes an Integer-N frequency
synthesizer and two fully integrated VCOs
featuring low phase noise performance and a
noise floor of -155 dBc/Hz.
The combination of wide frequency range VCOs
(using center-frequency calibration over 32 sub-
bands) and multiple output options (direct output,
divided by 2 or divided by 4) allows coverage from
750 MHz to 905 MHz and 1000MHz to 1162.5
MHz, from 1500MHz to 1810 MHz and 2000 MHz
to 2325MHz, from 3000 MHz to 3620 MHz and
4000MHz to 4650 MHz bands.
The STW81102 is designed with
STMicroelectronics advanced 0.35µm SiGe
process.
www.st.com
Contents STW81102
2/53
Contents
1 Block diagram and pin configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . 6
1.1 Block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6
1.2 Pin configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7
2 Electrical specifications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9
2.1 Absolute maximum ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9
2.2 Operating conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9
2.3 Digital logic levels . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10
2.4 Electrical specifications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10
2.5 Phase noise specification . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13
3 Typical performance characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . 15
4 General description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18
5 Circuit description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19
5.1 Reference input stage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19
5.2 Reference divider . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19
5.3 Prescaler . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19
5.4 A and B counters . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20
5.5 Phase frequency detector (PFD) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21
5.6 Lock detect . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21
5.7 Charge pump . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21
5.8 Voltage controlled oscillators . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23
5.8.1 VCO selection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23
5.8.2 VCO frequency calibration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23
5.8.3 VCO voltage amplitude control . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24
5.9 Output stage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25
5.9.1 Output Buffer control mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25
5.10 External VCO Buffer . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26
6I
2C bus interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27
6.1 General features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27
STW81102 Contents
3/53
6.1.1 Data validity . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27
6.1.2 START and STOP conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27
6.1.3 Byte format and acknowledge . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28
6.1.4 Device addressing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28
6.1.5 Single-byte write mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29
6.1.6 Multi-byte write mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29
6.1.7 Current byte address read mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29
6.2 Timing specification . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30
6.3 I2C registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32
6.3.1 Write-only registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32
6.3.2 Read-only register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34
6.3.3 Default configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34
6.4 VCO calibration procedure . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 35
6.4.1 VCO calibration auto-restart feature . . . . . . . . . . . . . . . . . . . . . . . . . . . 35
7 SPI digital interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 36
7.1 General features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 36
7.2 Timing specification . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 37
7.3 Bit tables . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 38
7.3.1 Default configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 40
7.4 VCO calibration procedure . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 40
7.4.1 VCO calibration auto-restart feature . . . . . . . . . . . . . . . . . . . . . . . . . . . 40
8 Application information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 41
8.1 Direct output . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 41
8.2 Divided by 2 output . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 43
8.3 Divided by 4 output . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 45
8.4 Evaluation kit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 46
9 Application diagrams . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 47
10 Package mechanical data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 50
11 Ordering information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 52
12 Revision history . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 52
List of tables STW81102
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List of tables
Table 1. Pin description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7
Table 2. Absolute maximum ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9
Table 3. Operating conditions (refer to
Figure 36: Typical application diagram
) . . . . . . . . . . . . . . . . 9
Table 4. Digital logic levels . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10
Table 5. Electrical specifications. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10
Table 6. Phase noise specification . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13
Table 7. Current value vs. selection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22
Table 8. VCO A performances versus amplitude setting (freq=3.3GHz) . . . . . . . . . . . . . . . . . . . . . 24
Table 9. VCO B performances versus amplitude setting (freq=4.3GHz) . . . . . . . . . . . . . . . . . . . . . 25
Table 10. EXT_PD pin function setting. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25
Table 11. Single-byte write mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29
Table 12. Multi-byte write mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29
Table 13. Current byte address read mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29
Table 14. Data and clock timing specifications. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30
Table 15. Start and stop timing specifications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31
Table 16. Ack timing specifications. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31
Table 17. Write-only registers. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32
Table 18. Functional modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32
Table 19. SPI data structure (MSB is sent first) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 37
Table 20. Address decoder and outputs. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 37
Table 21. SPI timing specification. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 37
Table 22. Bits at 00h and ST1 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 38
Table 23. Bits at 01h and ST2 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 39
Table 24. Order code of the evaluation kit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 46
Table 25. Package dimensions. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 51
Table 26. Order codes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 52
Table 27. Document revision history . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 52
STW81102 List of figures
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List of figures
Figure 1. Block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6
Figure 2. Pin connection (top view) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7
Figure 3. VCO A (direct output) open loop phase noise . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15
Figure 4. VCO B (direct output) open loop phase noise . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15
Figure 5. VCO A (direct output) closed loop phase noise at 3.6GHz
(FSTEP=200kHz; FPFD=200kHz; ICP=3mA) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15
Figure 6. VCO B (direct output) closed loop phase noise at 4.3GHz
(FSTEP=200kHz; FPFD=200kHz; ICP=4mA) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15
Figure 7. VCO A (div. by 2 output) closed loop phase noise at 1.65GHz
(FSTEP=200kHz; FPFD=400kHz; ICP=2mA) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16
Figure 8. VCO B (div. by 2 output) closed loop phase noise at 2.15GHz
(FSTEP=200kHz; FPFD=400kHz; ICP=3mA) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16
Figure 9. VCO A (div. by 4 output) closed loop phase noise at 825MHz
(FSTEP=200kHz; FPFD=800kHz; ICP=1.5mA) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16
Figure 10. VCO B (div. by 4 output) closed loop phase noise at 1.075GHz
(FSTEP=200kHz; FPFD=800kHz; ICP=2.5mA) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16
Figure 11. PFD frequency spurs (direct output; FPFD=200kHz). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17
Figure 12. PFD frequency spurs (div. by 2 output; FPFD=400kHz) . . . . . . . . . . . . . . . . . . . . . . . . . . . 17
Figure 13. PFD frequency spurs (div. by 4 output; FPFD=800kHz) . . . . . . . . . . . . . . . . . . . . . . . . . . . 17
Figure 14. Settling time (final frequency=2.15 GHz; FPFD=400kHz; ICP=3mA) . . . . . . . . . . . . . . . . . . 17
Figure 15. Reference frequency input buffer . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19
Figure 16. VCO divider diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20
Figure 17. PFD diagram. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21
Figure 18. Loop filter connection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22
Figure 19. VCO sub-bands frequency characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23
Figure 20. Data validity . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27
Figure 21. START and STOP conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28
Figure 22. Byte format and acknowledge . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28
Figure 23. Data and clock . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30
Figure 24. Start and stop . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30
Figure 25. Ack . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31
Figure 26. SPI input and output bit order . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 36
Figure 27. SPI timing specification. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 37
Figure 28. Differential/single-ended output network (MATCH_LC_LUMP_4G_DIFF.dsn) . . . . . . . . . 41
Figure 29. LC lumped balun and matching network (MATCH_LC_LUMP_4G.dsn) . . . . . . . . . . . . . . 42
Figure 30. Evaluation board (EVB4G) matching network (MATCH_EVB4G.dsn) . . . . . . . . . . . . . . . . 43
Figure 31. Differential/single-ended output network (MATCH_LC_LUMP_2G_DIFF.dsn) . . . . . . . . . 43
Figure 32. LC lumped balun for divided by 2 output (MATCH_LC_LUMP_2G.dsn) . . . . . . . . . . . . . . 44
Figure 33. Evaluation board (EVB2G) matching network (MATCH_EVB2G.dsn) . . . . . . . . . . . . . . . . 44
Figure 34. LC lumped balun for divided by 4 output (MATCH_LC_LUMP_1G.dsn) . . . . . . . . . . . . . . 45
Figure 35. Evaluation board (EVB1G) matching network (MATCH_EVB1G.dsn) . . . . . . . . . . . . . . . . 46
Figure 36. Typical application diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 47
Figure 37. Ping-pong architecture diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 48
Figure 38. Application diagram with external VCO (LO output from STW81102) . . . . . . . . . . . . . . . . 49
Figure 39. Application diagram with external VCO (LO output from VCO) . . . . . . . . . . . . . . . . . . . . . 49
Figure 40. VFQFPN28 mechanical drawing (
Note 1
) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 50
6/53 EXTVCOJNP EXTVCOJNN VDDJCOA VSSJCOA VDDJCOE VSSJCOE VDDiESD Vssjso
Block diagram and pin configuration STW81102
6/53
1 Block diagram and pin configuration
1.1 Block diagram
Figure 1. Block diagram
VCO
BUFF
EXTVCO_INN
VDD_VCOA
VSS_VCOA
VDD_VCOB
VSS_VCOB
VDD_ESD
VSS_ESD
EXTVCO_INP
DI V4
BUF
DIV 2
BUF
EXT
VCO
BUF
VDD_BUFVCO
VSS_BUFVCO
VDD_OUTBUF
OUTB UFP
VCTRL
TEST1
TEST2
EXT_PD
OUTB UFN
REF_CLK
VDD_PLL
VSS_PLL
REXT
VSS_OUTBUF
VDD_DIV4
VSS_DIV4
VDD_DIV2
VSS_DIV2
ADD0 / LOAD
ADD1
ADD2
VDD_DBUS
VSS_DBUS
VCO
Divider
REF
Divider
BUF
P
F
D
C
P
UP
DN
ICP
LOCK_DET
BUF
VDD_CP
VSS_CP
DBUS
SDA / DATA
SCL / CLK
DBUS_SEL
VCO
Calibrator
VCO
BUF
DIV4
DIV2
STW81102 Block diagram and pin configuration
7/53
1.2 Pin configuration
Figure 2. Pin connection (top view)
Table 1. Pin description
Pin No Name Description Observation
1 VDD_VCOA VCOA power supply
2 VDD_DIV2 Divider by 2 power supply
3 VDD_OUTBUF Output buffer power supply
4 OUTBUFP LO buffer positive output Open collector
5 OUTBUFN LO buffer negative output Open collector
6 VDD_DIV4 Divider by 4 power supply
7 VDD_VCOB VCOB power supply
8 VDD_ESD ESD positive rail power supply
9 VCTRL VCO control voltage
10 ICP PLL charge pump output
QFN 28
VDD_VCOA
ADD2
SCL/CLK
VDD_DBUS
SDA/DATA
EXT_PD
ADD1
ADD0/LOAD
VDD_ESD
REXT
LOCK_DET
VDD_CP
TEST1
VCTRL
ICP
VDD_DIV2
VDD_OUTBUF
OUTBUFP
OUTBUFN
VDD_DIV4
VDD_VCOB
DBUS_SEL
VDD_BUFVCO
EXTVCO_INP
EXTVCO_INN
VDD_PLL
REF_CLK
TEST2
VFQFPN28
Block diagram and pin configuration STW81102
8/53
11 REXT External resistance connection for
PLL charge pump
12 VDD_CP Power supply for charge pump
13 TEST1 Test input 1
For test purposes only;
must be connected to
GND
14 LOCK_DET Lock detector CMOS output
(IOUT = 4 mA)
15 TEST2 Test input 2
For test purposes only;
must be connected to
GND
16 REF_CLK Reference clock input
17 VDD_PLL PLL digital power supply
18 EXTVCO_INN External VCO negative input
For test purposes only;
must be connected to
GND
19 EXTVCO_INP External VCO positive input
For test purposes only;
must be connected to
GND
20 VDD_BUFVCO VCO buffer power supply
21 DBUS_SEL Digital bus interface select CMOS input
22 VDD_DBUS SPI and I2C bus power supply
23 EXT_PD Power down hardware
‘0’ device ON; ‘1’ device OFF CMOS input
24 SDA/DATA I2CBUS/SPI data line CMOS Bidir Schmitt
triggered (IOUT=4 mA)
25 SCL/CLK I2CBUS/SPI clock line CMOS input
Schmitt triggered
26 ADD0/LOAD I2CBUS address select pin/ SPI load
line CMOS input
27 ADD1 I2CBUS address select pin
CMOS input; must be
connected to GND in
SPI mode
28 ADD2 I2CBUS address select pin
CMOS input; must be
connected to GND in
SPI mode
Table 1. Pin description (continued)
Pin No Name Description Observation
STW81102 Electrical specifications
9/53
2 Electrical specifications
2.1 Absolute maximum ratings
2.2 Operating conditions
Table 2. Absolute maximum ratings
Symbol Parameter Values Unit
AVCC Analog supply voltage 0 to 4.6 V
DVCC Digital supply voltage 0 to 4.6 V
Tstg Storage temperature -65 to 150 °C
ESD
Electrical static discharge
- HBM(1)
- CDM-JEDEC standard
- MM
4
1.5
0.2
kV
1. The maximum rating of the ESD protection circuitry on pin 4 and pin 5 is 800V.
Table 3. Operating conditions (refer to
Figure 36: Typical application diagram
)
Symbol Parameter Test conditions Min Typ Max Unit
AVDD Analog supply voltage 3.0 3.3 3.6 V
DVDD Digital supply voltage 3.0 3.3 3.6 V
IVDD1 VDD1 current consumption 90 mA
IVDD2 VDD2 current consumption 12 mA
Tamb
Operating ambient
temperature -40 85 °C
Tj
Maximum junction
temperature 125 °C
Rth j-amb
Junction to ambient package
thermal resistance Multilayer JEDEC board 35 °C/W
Rth j-b
Junction to board package
thermal resistance Multilayer JEDEC board 26.3 °C/W
Rth j-c
Junction to case package
thermal resistance Multilayer JEDEC board 6.3 °C/W
Electrical specifications STW81102
10/53
2.3 Digital logic levels
2.4 Electrical specifications
All the electrical specifications are intended at 3.3V supply voltage.
Table 4. Digital logic levels
Symbol Parameter Test conditions Min Typ Max Unit
Vil Low level input voltage 0.2*Vdd V
Vih High level input voltage 0.8*Vdd V
Vhyst Schmitt trigger hysteresis 0.8 V
Vol Low level output voltage 0.4 V
Voh High level output voltage 0.85*Vdd V
Table 5. Electrical specifications
Symbol Parameter Test conditions Min Typ Max Unit
Output frequency range
FOUTA
Output frequency range with
VCOA
Direct output 3000 3620 MHz
Divider by 2 1500 1810 MHz
Divider by 4 750 905 MHz
FOUTB
Output frequency range with
VCOB
Direct output 4000 4650 MHz
Divider by 2 2000 2325 MHz
Divider by 4 1000 1162.5 MHz
VCO dividers
N VCO divider ratio Prescaler 16/17 256 65551
Prescaler 19/20 361 77836
Reference clock and phase frequency detector
Fref Reference input frequency 10 200 MHz
Reference input sensitivity(1) 0.35 1 1.5 Vpeak
R Reference divider ratio 2 1023
FPFD PFD input frequency 16 MHz
FSTEP Frequency step(2)
Prescaler 16/17 FOUT/
65551
FOUT/
256 Hz
Prescaler 19/20 FOUT/
77836
FOUT/
361 Hz
Charge pump
ICP ICP sink/source(3) 3bit programmable 5 mA
VOCP
Output voltage compliance
range 0.4 Vdd-0.3 V
STW81102 Electrical specifications
11/53
Spurious(4)
Direct output
(FPFD = 200 kHz) -73 dBc
Divider by 2
(FPFD = 400 kHz) -83 dBc
Divider by 4
(FPFD = 800 kHz) -91 dBc
VCOs
KVCOA VCOA sensitivity(5)
Lower frequency range 40 55 70 MHz/V
Intermediate frequency range 60 75 95 MHz/V
Higher frequency range 80 105 140 MHz/V
KVCOB VCOB sensitivity(5)
Lower frequency range 30 45 60 MHz/V
Intermediate frequency range 40 55 70 MHz/V
Higher frequency range 50 70 90 MHz/V
ΔΤLK
Maximum temperature
variation for continuous
lock(5)(6)
VCO A 115 °C
VCO B 95
VCO A pushing(5) 47MHz/V
VCO B pushing(5) 14 20 MHz/V
VCTRL VCO control voltage(5) 0.4 3 V
LO harmonic spurious(5) -20 dBc
IVCOA VCOA current consumption FVCO=3.3GHz; amplitude [11] 30 mA
FVCO=3.3GHz; amplitude [00] 16 mA
IVCOB VCOB current consumption FVCO=4.3GHz; amplitude [11] 22 mA
FVCO=4.3GHz; amplitude [00] 11 mA
IVCOBUF VCO buffer consumption 15 mA
IDIV2 Divider by 2 consumption 17 mA
IDIV4 Divider by 4 consumption 13 mA
LO output buffer
PLO Output level 0 dBm
RLReturn loss(5) Matched to 50 ohms 15 dB
IOUTBUF Current consumption
DIV4 buff 27 mA
DIV2 buff 23 mA
Direct output 39 mA
Output buffer isolation (power
down state)
Direct output (FOUT=4GHz) 43
dB
Divider by 2 output
(FOUT=2GHz) 62
Divider by 4 output
(FOUT=1GHz) 67
Table 5. Electrical specifications (continued)
Symbol Parameter Test conditions Min Typ Max Unit
Electrical specifications STW81102
12/53
External VCO
Frequency range 0.625 5 GHz
Input level -10 +6 dBm
Current consumption VCO internal buffer 28 mA
PLL miscellaneous
IPLL Current consumption Input buffer, prescaler, digital
dividers, misc. 12 mA
tlock Lock up time (5), (7) 25kHz PLL bandwidth; within
1 ppm of frequency error 150 µs
1. In order to achieve best phase noise performance 1V peak level is suggested.
2. The frequency step is related to the PFD input frequency as follows:
- FSTEP = FPFD for direct output
- FSTEP = FPFD/2 for divided by 2 output
- FSTEP = FPFD/4 for divided by 4 output
3. See relationship between ICP and REXT in
Section 5.7: Charge pump
.
4. The level of the spurs may change depending on PFD frequency, charge pump current, selected channel and PLL loop
BW.
5. Guaranteed by design and characterization.
6. When setting a specified output frequency, the VCO calibration procedure must be run in order to select the best sub-range
for the VCO covering the desired frequency. Once programmed at the initial temperature T0 inside the operating
temperature range (-40 °C to +85 °C), the synthesizer is able to maintain the lock status only if the temperature drift (in
either direction) is within the limit specified by ΔTLK, provided that the final temperature T1 is still inside the nominal range.
If higher ΔT are required the ”
VCO calibration auto-restart
“ feature can be enabled, thus allowing to re-start the VCO
calibration procedure automatically when the part loose the lock condition (trigger on lock detector signal)
7. Frequency jump from 2300 to 2150 MHz; it includes the time required by the VCO calibration procedure (7 FPFD cycles with
FPFD=400kHz).
Table 5. Electrical specifications (continued)
Symbol Parameter Test conditions Min Typ Max Unit
STW81102 Electrical specifications
13/53
2.5 Phase noise specification
Table 6. Phase noise specification
Parameter Test conditions Min Typ Max Unit
Phase noise performance(1)
Inband phase noise floor – closed loop(2)
Normalized inband phase noise
floor
ICP=4mA, PLL BW = 50kHz;
including reference clock
contribution
-222 dBc/Hz
Inband phase noise floor
direct output
ICP=4mA, PLL BW = 50kHz;
including reference clock
contribution
-222+20log(N)+10log(FPFD)dBc/Hz
Inband phase noise floor
divider by 2 -228+20log(N)+10log(FPFD)dBc/Hz
Inband phase noise floor
divider by 4 -234+20log(N)+10log(FPFD)dBc/Hz
PLL integrated phase noise – direct output
Integrated phase noise
100 Hz to 40 MHz
FOUT = 4.3 GHz,
FPFD = 200kHz, FSTEP =200 kHz,
PLL BW = 15kHz, ICP=4mA
-35 dBc
1.4 ° rms
PLL integrated phase noise – divider by 2
Integrated phase noise
100Hz to 40MHz
FOUT = 2.15 GHz,
FPFD = 400kHz, FSTEP =200 kHz,
PLL BW = 20kHz, ICP=3mA
-44 dBc
0.52 ° rms
PLL integrated phase noise – divider by 4
Integrated phase noise
100Hz to 40MHz
FOUT = 1.075 GHz,
FPFD = 800kHz, FSTEP =200 kHz,
PLL BW = 30kHz, ICP=2.5mA
-51 dBc
0.22 ° rms
VCO A direct (3000MHz-3620MHz) – open loop(3)
Phase noise @ 1 kHz -57 dBc/Hz
Phase noise @ 10 kHz -84 dBc/Hz
Phase noise @ 100 kHz -107 dBc/Hz
Phase noise @ 1 MHz -129 dBc/Hz
Phase noise @ 10 MHz -149 dBc/Hz
Phase noise @ 40 MHz -159 dBc/Hz
VCO B direct (4000MHz-4650MHz) – open loop(3)
Phase noise @ 1 kHz -55 dBc/Hz
Phase noise @ 10 kHz -83 dBc/Hz
Phase noise @ 100 kHz -106 dBc/Hz
Phase noise @ 1 MHz -128 dBc/Hz
Phase noise @ 10 MHz -148 dBc/Hz
Phase noise @ 40 MHz -158 dBc/Hz
Electrical specifications STW81102
14/53
An evaluation kit is available upon request, including a powerful simulation tool
(STWPLLSim) that allows a very accurate estimation of the device’s phase noise according
to the desired project parameters (VCO frequency, selected output stage, reference clock,
frequency step, and so on); refer to
Chapter 8: Application information
for more details.
VCO A with divider by 2 (1500MHz-1810MHz) – open loop(3)
Phase noise @ 1 kHz -63 dBc/Hz
Phase noise @ 10 kHz -90 dBc/Hz
Phase noise @ 100 kHz -113 dBc/Hz
Phase noise @ 1 MHz -135 dBc/Hz
Phase noise @ 10 MHz -151.5 dBc/Hz
Phase noise floor @ 40 MHz -155 dBc/Hz
VCO B with divider by 2 (2000MHz-2325MHz) – open loop(3)
Phase noise @ 1 kHz -61 dBc/Hz
Phase noise @ 10 kHz -89 dBc/Hz
Phase noise @ 100 kHz -112 dBc/Hz
Phase noise @ 1 MHz -134 dBc/Hz
Phase noise @ 10 MHz -151.5 dBc/Hz
Phase noise floor @ 40 MHz -155 dBc/Hz
VCO A with divider by 4 (750MHz-905MHz) – open loop(3)
Phase noise @ 1 kHz -69 dBc/Hz
Phase noise @ 10 kHz -96 dBc/Hz
Phase noise @ 100 kHz -119 dBc/Hz
Phase noise @ 1 MHz -141 dBc/Hz
Phase noise @ 10 MHz -154 dBc/Hz
Phase noise floor @ 40 MHz -155 dBc/Hz
VCO B with divider by 4 (1000MHz-1162.5MHz) – open loop(3)
Phase noise @ 1 kHz -67 dBc/Hz
Phase noise @ 10 kHz -95 dBc/Hz
Phase noise @ 100 kHz -118 dBc/Hz
Phase noise @ 1 MHz -140 dBc/Hz
Phase noise @ 10 MHz -154 dBc/Hz
Phase noise floor @ 40 MHz -155 dBc/Hz
1. Phase noise SSB.
VCO amplitude setting to value [11].
All the closed-loop performances are specified using a reference clock signal at 76.8 MHz with phase noise of
-135dBc/Hz @1kHz offset, -145 dBc/Hz @10 kHz offset and -149.5dBc/Hz of noise floor.
2. Normalized PN = Measured PN – 20log(N) – 10log(FPFD) where N is the VCO divider ratio (N=B*P+A) and FPFD is the
comparison frequency at the PFD input.
3. Typical phase noise at centre band frequency.
Table 6. Phase noise specification (continued)
Parameter Test conditions Min Typ Max Unit
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STW81102 Typical performance characteristics
15/53
3 Typical performance characteristics
Phase noise is measured with the Agilent E5052A Signal Source Analyzer. All closed-loop
measurements are done with FSTEP=200 kHz, with the FPFD and charge pump current
properly set. The loop filter configuration is depicted in
Figure 36: Typical application
diagram
, and the reference clock signal is at 76.8 MHz with phase noise of -135 dBc/Hz at
1kHz offset, -145 dBc/Hz at10 kHz offset and -149.5 dBc/Hz of noise floor.
Figure 3. VCO A (direct output) open loop
phase noise
Figure 4. VCO B (direct output) open loop
phase noise
Figure 5. VCO A (direct output) closed loop
phase noise at 3.6GHz
(FSTEP=200kHz; FPFD=200kHz;
ICP=3mA)
Figure 6. VCO B (direct output) closed loop
phase noise at 4.3GHz
(FSTEP=200kHz; FPFD=200kHz;
ICP=4mA)
1.2° rms
1.4° rm
s
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Typical performance characteristics STW81102
16/53
Figure 7. VCO A (div. by 2 output) closed
loop phase noise at 1.65GHz
(FSTEP=200kHz; FPFD=400kHz;
ICP=2mA)
Figure 8. VCO B (div. by 2 output) closed
loop phase noise at 2.15GHz
(FSTEP=200kHz; FPFD=400kHz;
ICP=3mA)
0
.
5
° rm
s
0
.
5
7° rm
s
Figure 9. VCO A (div. by 4 output) closed
loop phase noise at 825MHz
(FSTEP=200kHz; FPFD=800kHz;
ICP=1.5mA)
Figure 10. VCO B (div. by 4 output) closed
loop phase noise at 1.075GHz
(FSTEP=200kHz; FPFD=800kHz;
ICP=2.5mA)
0
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s
0
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STW81102 Typical performance characteristics
17/53
Figure 11. PFD frequency spurs (direct
output; FPFD=200kHz)
Figure 12. PFD frequency spurs (div. by 2
output; FPFD=400kHz)
-73 dBc
@200KHz -83 dBc
@400KHz
Figure 13. PFD frequency spurs (div. by 4
output; FPFD=800kHz)
Figure 14. Settling time (final frequency=2.15
GHz; FPFD=400kHz; ICP=3mA)
-91 dBc
@800KHz
General description STW81102
18/53
4 General description
Figure 1: Block diagram
shows the separate blocks that, when integrated, form an Integer-N
PLL frequency synthesizer.
The STW81102 consists of two internal low-noise VCOs with buffer blocks, a divider by 2, a
divider by 4, a low-noise PFD (phase frequency detector), a precise charge pump, a 10-bit
programmable reference divider, two programmable counters and a programmable dual-
modulus prescaler. The 5-bit A-counter and 12-bit B-counter, in conjunction with the dual-
modulus prescaler P/P+1 (16/17 or 19/20), implement an N integer divider, where N = B*P
+A. The division ratio of both reference and VCO dividers is controlled through the selected
digital interface (I2C bus or SPI).
The digital interface type is selected by the proper hardware connection of the pin
DBUS_SEL (0 V for I2C bus, 3.3 V for SPI).
All devices operate with a power supply of 3.3 V and can be powered down when not in use.
5.2 5.3 Reference divider The 107bii programmable reference coumer allows divxsion lo produce ihe inpui clock lo ihe PFD. The division ram is in1erface. Prescaler The dualrmodulus prescaler P/P+1 lakes ihe CML clock fr down lo a manageable frequency lor 1he CMOS A and B c programmable and can be sei 10 16 or 19. The prescaler l core whose division ralio depends on me slale of me mod
STW81102 Circuit description
19/53
5 Circuit description
5.1 Reference input stage
The reference input stage is shown in
Figure 15
. The resistor network feeds a DC bias at the
Fref input while the inverter used as the frequency reference buffer is AC coupled.
Figure 15. Reference frequency input buffer
5.2 Reference divider
The 10-bit programmable reference counter allows division of the input reference frequency
to produce the input clock to the PFD. The division ratio is programmed through the digital
interface.
5.3 Prescaler
The dual-modulus prescaler P/P+1 takes the CML clock from the VCO buffer and divides it
down to a manageable frequency for the CMOS A and B counters. The modulus P is
programmable and can be set to 16 or 19. The prescaler is based on a synchronous 4/5
core whose division ratio depends on the state of the modulus input.
INV BUF
VDD
Fref
Power Down
20/53 5-17“
Circuit description STW81102
20/53
5.4 A and B counters
The 5-bit A-counter and 12-bit B-counter, in conjunction with the selected dual modulus
(16/17 or 19/20) prescaler, make it possible to generate output frequencies which are
spaced only by the reference frequency divided by the reference division ratio. Thus, the
division ratio and the VCO output frequency are given by these formulas:
where:
FVCO: output frequency of VCO
P: modulus of dual modulus prescaler (16 or 19 selected through the digital interface)
B: division ratio of the main counter
A: division ratio of the swallow counter
Fref: input reference frequency
R: division ratio of reference counter
N: division ratio of PLL
For a correct working of the VCO divider, B must be strictly higher than A. A can take any
value ranging from 0 to 31. The range of N can vary from 256 to 65551 (P=16) or from 361
to 77836 (P=19).
Figure 16. VCO divider diagram
NBPA+×=
FVCO
BPA+×()Fref
×
R
---------------------------------------------------=
5-bit 12-bit
To PFD
modulus
VCOBUF+
VCOBUF-
Prescaler
16/17 or 19/20
B-counter
A-counter
T T TT
STW81102 Circuit description
21/53
5.5 Phase frequency detector (PFD)
The PFD takes inputs from the reference and the VCO dividers and produces an output
proportional to the phase error. The PFD includes a delay gate that controls the width of the
anti-backlash pulse. This pulse ensures that there is no dead zone in the PFD transfer
function.
Figure 17
is a simplified schematic of the PFD.
Figure 17. PFD diagram
5.6 Lock detect
This signal indicates that the difference between rising edges of both UP and DOWN PFD
signals is found to be shorter than the fixed delay (roughly 5 ns). The Lock Detect signal is
high when the PLL is locked and low when the PLL is unlocked. Lock Detect consumes
current only during PLL transients.
5.7 Charge pump
This block drives two matched current sources, IUP and IDOWN, which are controlled
respectively by UP and DOWN PFD outputs. The nominal value of the output current is
controlled by an external resistor (connected to the REXT input pin) and a 3-bit word that
allows selection among 8 different values.
The minimum value of the output current is: IMIN = 2*VBG/REXT (VBG~1.17 V)
DFF
R
VDD
R
DFF
VDD
Delay
Up
Down
ABL
F
ref
ref
F
uit description STWB1102 Table 7. Current value vs. selection CPSELZ CPSEL1 CPSELO Current Value for REXT=4J K9 0 o 0 1W 0 5 mA 0 o 1 21W 1 0 mA 0 1 0 sum 1 5 mA 0 1 1 41W 2 0 mA 1 o 0 sum 2 5 mA 1 o 1 mm a 0 mA 1 1 o 71W 3 5 mA 1 1 1 8‘IMW 4 0 mA Note: The current is output on pin ICF? During VCO aurorcalibralion, the ICP and VCTFlL pins are forced to VDD/2 Figure 18. Loop filter connection 22/53 ‘7
Circuit description STW81102
22/53
Note: The current is output on pin ICP. During VCO auto-calibration, the ICP and VCTRL pins are
forced to VDD/2
Figure 18. Loop filter connection
Table 7. Current value vs. selection
CPSEL2 CPSEL1 CPSEL0 Current Value for REXT=4.7 KΩ
000I
MIN 0.5 mA
0012*I
MIN 1.0 mA
0103*I
MIN 1.5 mA
0114*I
MIN 2.0 mA
1005*I
MIN 2.5 mA
1016*I
MIN 3.0 mA
1107*I
MIN 3.5 mA
1118*I
MIN 4.0 mA
Charge
Pump
VDD
BUF
VCTRL
R3
C2
C1
Cal bit
BUF
C3
ICP
R1
FREQ [Hz] VCO Sub-Bands Frequency characteristics VCTRLM name now , , 7 * Mm c}llbr;xor Inc range , 1 ,2 nm _/_,_,_ / 000 050 100 150 200 250 300 350
STW81102 Circuit description
23/53
5.8 Voltage controlled oscillators
5.8.1 VCO selection
The STW81102 integrates two low-noise VCOs to cover a wide band from:
●3000 MHz to 3620 MHz and 4000 MHz to 4650 MHz (direct output)
●1500 MHz to 1810 MHz and 2000 MHz to 2325 MHz (selecting divider by 2)
●750 MHz to 905 MHz and 1000 MHz to 1162.5 MHz (selecting divider by 4)
The frequency range is 3000 MHz to 3620 MHz for VCO A and 4000 MHz to 4650 MHz for
VCO B.
5.8.2 VCO frequency calibration
Both VCOs can operate on 32 frequency ranges that are selected by adding or subtracting
capacitors from the resonator. These frequency ranges are intended to cover the wide band
of operation and compensate for process variation on the VCO center frequency.
The range is automatically selected when the
SERCAL bit is set to 1. The charge pump is
inhibited, and the ICP and VCTRL pins are at VDD/2 volts. The ranges are then tested with
this VCO input voltage to select the one nearest to the desired output frequency (F
OUT
=
N*F
ref
/R).
After this selection, the SERCAL bit is automatically reset to 0 and the charge pump is once
again enabled. To enable a fast settle, t
he PLL needs only to perform fine adjustment around
VDD/2 on the loop filter to reach F
OUT
.
Figure 19. VCO sub-bands frequency characteristics
Circuit description STW81102
24/53
The SERCAL bit should be set to 1 at each division ratio change. VCO calibration procedure
takes approximately 7 periods of the PFD frequency.
The maximum allowed FPFD to perform the calibration process is 1 MHz. When using a
higher FPFD, follow the steps below:
1. Calibrate the VCO at the desired frequency with an FPFD less than 1 MHz.
2. Set the A, B and R divider ratios for the desired FPFD.
VCO calibration auto-restart feature
The VCO calibration auto-restart feature, once activated, allows to restart the calibration
procedure when the Lock Detector reports that the PLL has moved to an unlock condition
(trigger on ‘1’ to ‘0’ transition of Lock Detector signal).
This situation could happen if the device experiences a significant temperature variation.
Once programmed at the initial temperature T0 inside the operating temperature range
(-40 °C to +85 °C), the synthesizer is able to maintain the lock status only if the temperature
drift (in either direction) is within the limit specified by the ΔTLK parameter, provided that the
final temperature T1 is still inside the nominal range.
Each VCO featured by STW81102 has its specific ΔTLK parameter reported in Table 5, that
is typically lower than the maximum allowable drift (ΔTMAX=125; from -40 °C to +85 °C and
vice versa).
By enabling the VCO Calibration Auto-Restart feature (through the CAL_AUTOSTART_EN
bit), the part will be able to select again the proper VCO frequency sub-range if the
temperature drift exceeds the ΔTLK limit, without any external user command.
5.8.3 VCO voltage amplitude control
The voltage swing of the VCOs can be adjusted over four levels by means of two dedicated
programming bits (PLL_A1 and PLL_A0). Higher amplitudes provide best phase noise,
whereas lower amplitudes save power.
Ta bl e 8
gives the voltage swing level expected on the resonator nodes, the current
consumption, and the phase noise at 1 MHz.
Table 8. VCO A performances versus amplitude setting (freq=3.3GHz)
PLL_A[1:0] Differential voltage swing
(Vp)
Current consumption
(mA) PN @1MHz (dBc/Hz)
00 1.1 16 -125
01 1.3 18 -126
10 1.9 27 -128.5
11 2.1 30 -129
STW81102 Circuit description
25/53
5.9 Output stage
The differential output signal of the synthesizer can be selected by software among three
different signal paths (Direct, Divider by 2 and Divider by 4) providing multi-band capability.
The selection of the output stage is done by programming properly the PD[4:0] bits.
The output stage is an open-collector structure which is able to meet different requirements
over the desired output frequency range by proper connections on the PCB. Refer to
Chapter 8: Application information
for more details on PCB connections.
5.9.1 Output Buffer control mode
This control mode allows to enable/disable the output stage by a hardware control pin
(EXT_PD, pin#23) while the PLL stays locked at the desired frequency; in such a way a very
fast switching time is achieved.
This feature can be useful in designing a ping-pong architecture saving the cost of an
external RF switch.
The function of pin#23 (EXT_PD) is set with the OUTBUF_CTRL_EN bit as shown in
Ta bl e 1 0 .
Table 9. VCO B performances versus amplitude setting (freq=4.3GHz)
PLL_A[1:0] Differential voltage swing
(Vp)
Current consumption
(mA) PN @1MHz (dBc/Hz)
00 1.1 11 -124
01 1.3 14 -125
10 1.9 20 -127.5
11 2.1 22 -128
Table 10. EXT_PD pin function setting
OUTBUF_CTRL_EN Function of the EXT_PD pin EXT_PD pin settings
0 Device hardware power down EXT_PD = 0V Î Device ON
EXT_PD = 3.3V Î Device OFF
1 Output Buffer control EXT_PD = 0V Î Output Stage ON
EXT_PD = 3.3V Î Output Stage OFF
Circuit description STW81102
26/53
5.10 External VCO Buffer
Although the main benefits of the STW81102 are the two wideband and low-noise VCOs,
the capability to use an external VCO is also provided.
The external VCO Buffer is able to manage a signal coming from an external VCO in order
to build a synthesizer using the STW81102 only as PLL IC. The output signal of the
synthesizer can also be taken from the output section of the STW81102 (direct, divided by 2
or divided by 4 by) by properly setting the PD[4:0] bits, thus providing additional flexibility.
The external VCO signal can range from 625 MHz up to 5 GHz and its minimum power level
must be -10 dBm.
STW81102 I2C bus interface
27/53
6 I2C bus interface
The I2C bus interface is selected by hardware connection of the pin #21 (DBUS_SEL) to 0 V.
Data is transmitted from microprocessor to the STW81102 through the 2-wire (SDA and
SCL) I2C bus interface. The STW81102 is always a slave device.
The I2C bus protocol defines any device that sends data on the bus as a transmitter, and
any device that reads the data as a receiver. The device controlling the data transfer is the
master, and the others are slaves. The master always initiates the transfer and provides the
serial clock for synchronization.
6.1 General features
6.1.1 Data validity
Data changes on the SDA line must only occur when the SCL is low. SDA transitions while
the clock is high are used to identify a START or STOP condition.
Figure 20. Data validity
6.1.2 START and STOP conditions
START condition
A START condition is identified by a transition of the data bus SDA from high to low while the
clock signal SCL is stable in the high state. A START condition must precede any data
transfer command.
STOP condition
A STOP condition is identified by a transition of the data bus SDA from low to high while the
clock signal SCL is stable in the high state. A STOP condition terminates communications
between the STW81102 and the bus master.
SDA
SCL
Data line Change
Stable datadata
Valid allowed
6.1.3 6.1.4 28/53 \/\/\/\/\ SBA—\flf_ Byte formal and acknowledge Every pyle pul on me SDA line mus1 be 8 his long, and be foliowed by an ackn lo indicale a successfui dala lransler. Dala is 1ransferred wi1h lhe mosl significa firs1. The lransmiller reieases lhe SDA line afler sending 8 bils of dala. During pulse,1he receiver pulls lhe SDA line low lo acknowledge lhe receip1 of 8 bils 0 Figure 22. Byte formal and acknowledge ‘1 m ,m Device addressing The masler musl firsl inmale wi1h a START condmon lo communicale wilh 1he S and lhen send 8 pils (MSB firsl) on me SDA iine which correspond lo 1he dewc address and me read or wrile mode. The firs1 7 MSBs are lhe deVice address idenlilier, which corresponds 10 me l2 deliniiion. For lhe STW81102,1he address iS se1al“1100A2A1A0", 3 oils prog The Blh bil (LSB) is me read or wrile (FlW) operalion bi1, which is sex lo 1 in rea lo 0 in wrile mode. Foilowing a START condiiion, lhe STW81103 idemifieslhe device address on 1h malched, acknowiedges lhe idenlificalion on lhe SDA bus during lhe 91h ciock
I2C bus interface STW81102
28/53
Figure 21. START and STOP conditions
6.1.3 Byte format and acknowledge
Every byte put on the SDA line must be 8 bits long, and be followed by an acknowledge bit
to indicate a successful data transfer. Data is transferred with the most significant bit (MSB)
first. The transmitter releases the SDA line after sending 8 bits of data. During the 9th clock
pulse, the receiver pulls the SDA line low to acknowledge the receipt of 8 bits of data.
Figure 22. Byte format and acknowledge
6.1.4 Device addressing
The master must first initiate with a START condition to communicate with the STW81102,
and then send 8 bits (MSB first) on the SDA line which correspond to the device select
address and the read or write mode.
The first 7 MSBs are the device address identifier, which corresponds to the I2C bus
definition. For the STW81102, the address is set at “1100A2A1A0”, 3 bits programmable.
The 8th bit (LSB) is the read or write (RW) operation bit, which is set to 1 in read mode and
to 0 in write mode.
Following a START condition, the STW81103 identifies the device address on the bus and, if
matched, acknowledges the identification on the SDA bus during the 9th clock pulse.
SDA
SCL
START STOP
SD
A
SC
L
START
/
/
/
/
Acknowledgement
from receiver
891
MSB
237
STW81102 I2C bus interface
29/53
6.1.5 Single-byte write mode
Following a START condition, the master sends a device select code with the RW bit set to
0. The STW81102 sends an acknowledge and waits for the 1-byte internal sub-address that
provides access to the internal registers.
After receiving the sub-address internal byte, the STW81102 again responds with an
acknowledge. A single-byte write to sub-address 00H changes the FUNCTIONAL_MODE
register, a single-byte write with sub-address 04H changes the CONTROL register, and so
on.
6.1.6 Multi-byte write mode
The multi-byte write mode can start from any internal address. The master sends the data
bytes, and each one is acknowledged. The master then terminates the transfer by
generating a STOP condition.
The sub-address decides the starting byte. For example, a multi-byte with sub-address 01H
and 2 DATA_IN bytes changes the B_COUNTER and A_COUNTER registers (01H,02H),
and a multi-byte with sub-address 00H and 6 DATA_IN bytes changes all the STW81102
registers.
6.1.7 Current byte address read mode
In the current byte address read mode, following a START condition, the master sends the
device address with the RW bit set to 1. Note that no sub-address is needed since there is
only one read register. The STW81102 acknowledges this and outputs the data byte. The
master does not acknowledge the received byte, and terminates the transfer with a STOP
condition.
Table 11. Single-byte write mode
S 1100A
2
A
1
A
0
0 ack sub-address byte ack DATA IN ack P
Table 12. Multi-byte write mode
S 1100A
2
A
1
A
0
0 ack sub-address byte ack DATA IN ack .... DATA IN ack P
Table 13. Current byte address read mode
S 1100 A
2
A
1
A
0
1ack DATA OUT No ackP
I2C bus interface STW81102
30/53
6.2 Timing specification
Figure 23. Data and clock
Figure 24. Start and stop
Table 14. Data and clock timing specifications
Symbol Parameter Minimum time Units
tcs Data to clock setup time 2 ns
tch Data to clock hold time 2 ns
tcwh Clock pulse width high 10 ns
tcwl Clock pulse width low 5 ns
tcstch tcwh
tcwl
SDA
SCL
tt
start stop
SDA
SCL
STW81102 I2C bus interface
31/53
Figure 25. Ack
Table 15. Start and stop timing specifications
Symbol Parameter Minimum time Units
tstart Clock to data start time 2 ns
tstop Data to clock down stop time 2 ns
Table 16. Ack timing specifications
Symbol Parameter Minimum time Units
td1 Ack begin delay 2 ns
td2 Ack end delay 2 ns
PC
SCL
SDA
t
d1
t
d2
89
I2C bus interface STW81102
32/53
6.3 I2C registers
The STW81102 has 6 write-only registers and 1 read-only register.
6.3.1 Write-only registers
Ta bl e 1 7
gives a short description of the write-only registers.
FUNCTIONAL_MODE
The bits PD[4:0] allow to select different functional modes for the STW81102 synthesizer
according to the
Table 18
.
Table 17. Write-only registers
HEX code DEC code Description
0x00 0 FUNCTIONAL_MODE
0x01 1 B_COUNTER
0x02 2 A_COUNTER
0x03 3 REF_DIVIDER
0x04 4 CONTROL
0x05 5 CALIBRATION
MSB LSB
b7 b6 b5 b4 b3 b2 b1 b0
OUTBUF_
CTRL_EN
CAL_AUT
OSTART_
EN
PD4 PD3 PD2 PD1 PD0 B11
OUTBUF_CTRL_EN: Output Buffer control mode enable (0 = Off; 1 = ON)
CAL_AUTOSTART_EN: VCO calibration auto-restart enable (0 = Off; 1 = ON)
Table 18. Functional modes
Decimal value Description
0 Power down mode
1 Enable VCO A, output frequency divided by 2
2 Enable VCO B, output frequency divided by 2
3 Enable external VCO, output frequency divided by 2
4 Enable VCO A, output frequency divided by 4
5 Enable VCO B, output frequency divided by 4
6 Enable external VCO, output frequency divided by 4
7 Enable VCO A, direct output
STW81102 I2C bus interface
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B_COUNTER
B[10:3]. B counter value (bit B11 in the previous register, bits B[2:0] in the next register)
A_COUNTER
Bits B[2:0] for B_COUNTER, A_COUNTER values.
REF_DIVIDER
Reference clock divider ratio R[9:1] (bits R1, R0 in the next register).
CONTROL
The CONTROL register is used to set the charge pump current, the VCO output voltage
amplitude and the prescaler modulus:
8 Enable VCO B, direct output
9 Enable external VCO, direct output
MSB LSB
b7 b6 b5 b4 b3 b2 b1 b0
B10B9B8B7B6B5B4B3
MSB LSB
b7 b6 b5 b4 b3 b2 b1 b0
B2 B1 B0 A4 A3 A2 A1 A0
MSB LSB
b7 b6 b5 b4 b3 b2 b1 b0
R9 R8 R7 R6 R5 R4 R3 R2
MSB LSB
b7 b6 b5 b4 b3 b2 b1 b0
R1 R0 PLL_A1 PLL_A0 CPSEL2 CPSEL1 CPSEL0 PSC_SEL
PLL_A[1:0]: VCO amplitude
CPSEL[2:0]: charge pump output current
PSC_SEL: prescaler modulus select ('0' for P=16, '1' for P=19)
Table 18. Functional modes (continued)
Decimal value Description
I2C bus interface STW81102
34/53
The LO output frequency is programmed by setting the proper values for A, B and R
according to the following formula:
CALIBRATION
This register controls the VCO calibrator using the following values:
6.3.2 Read-only register
This register is automatically addressed in the 'current byte address read mode', using the
following values:
6.3.3 Default configuration
At power on, all the bits are set to ‘0’. Consequently the part starts in power down mode.
where DR equals {1 for direct output
0.5 for output divided by 2
0.25 for output divided by 4
and P is the selected prescaler modulus.
MSB LSB
b7 b6 b5 b4 b3 b2 b1 b0
INITCAL SERCAL SELEXTCAL CAL4 CAL3 CAL2 CAL1 CAL0
INITCAL: for test purposes only; must be set to 0.
SERCAL: at 1, starts the VCO auto-calibration (automatically reset to 0 at the end of calibration)
SELEXTCAL: for test purposes only; must be set to 0
CAL[4:0]: for test purposes only; must be set to 0
FOUT DRBPA+×()×
FREF CLK–
R
-------------------------------
×=
MSB LSB
b7 b6 b5 b4 b3 b2 b1 b0
DEV_ID1 DEV_ID0 LOCK_DET INTCAL4 INTCAL3 INTCAL2 INTCAL1 INTCAL0
DEV_ID[1:0]: device identifier bits; returns 01
LOCK_DET: 1 when PLL is locked
INTCAL[4:0]: internal value of the VCO control word
STW81102 I2C bus interface
35/53
6.4 VCO calibration procedure
Calibration of the VCO center frequency is activated when the SERCAL bit (CALIBRATION
register bit[6]) is set to 1.
To program the device properly while ensuring VCO calibration, perform the following steps
before every channel change:
1. Program all the registers using a multi-byte write sequence with the desired settings
(functional mode, B and A counters, R counter, VCO amplitude, charge pump,
prescaler modulus), and all the bits of the CALIBRATION register (05H) set to 0.
2. Program the CALIBRATION register using a single-byte write sequence (subaddress
05H) with the SERCAL bit set to 1.
The maximum allowed PFD frequency (FPFD) during calibration is 1 MHz; if you want a FPFD
higher than 1 MHz, perform the following additional steps:
●Perform all the steps of the calibration procedure, making sure to program the desired
VCO frequency with proper settings for the R, B and A counters so that FPFD is ≤ 1 MHz.
●Program the device with the desired VCO and PFD frequency settings according to
step 1) above.
6.4.1 VCO calibration auto-restart feature
The VCO calibration auto-restart feature can be enabled in two steps:
1. set the desired frequency ensuring VCO calibration as described above (section 6.4)
2. program the FUNCTIONAL_MODE register (sub-address 00H) using a single-byte
write sequence with the CAL_AUTOSTART_EN bit set to '1' while keeping unchanged
the others.
SPI digital interface STW81102
36/53
7 SPI digital interface
7.1 General features
The SPI digital interface is selected by hardware connection of the pin #21 (DBUS_SEL) to
3.3 V.
The STW81102 IC is programmed by means of a high-speed serial-to-parallel interface with
write option only. The 3-wire bus can be clocked at a frequency as high as 100 MHz to allow
fast programming of the registers containing the data for RF IC configuration.
The chip is programmed through serial words with a full length of 26 bits. The first 2 MSBs
represent the address of the registers, and the 24 LSBs represent the value of the registers.
Each data bit is stored in the internal shift register on the rising edge of the CLOCK signal.
The outputs of the selected register are sent to the device on the rising edge of the LOAD
signal.
Figure 26. SPI input and output bit order
Last bit sent
(LSB)0
22324 25(MSB)
A1
LOAD #4
Address
decoder
1
DATA
LOAD
Reg.#4
Reg.#1
Reg.#0
D23 (MSB)
D0 (LSB)
STW81102 SPI digital interface
37/53
7.2 Timing specification
Figure 27. SPI timing specification
Table 19. SPI data structure (MSB is sent first)
MSB LSB
Address Data for register (24 bits)
A1 A0 D23 D22 D21 D20 D19 D18 D17 D16 D15 D14 D13 D12 D11 D10 D9 D8 D7 D6 D5 D4 D3 D2 D1 D0
Table 20. Address decoder and outputs
Address Outputs
A1 A0 Data bits
D23-D0 No Name Function
00 24 0ST1
Reference divider, VCO amplitude, VCO calibration,
charge pump current, prescaler modulus
0 1 24 1 ST2 Functional modes, VCO dividers
10 24 2ST3Reserved
11 24 3ST4Reserved
Table 21. SPI timing specification
Parameter Description Min. Typ. Max. Units
tsetup Data to clock setup time 0.8 ns
thold Data to clock hold time 0.2 ns
tclk Clock cycle period 10 ns
tload Load pulse width 3 ns
tclk_loadr Clock to load rising edge 2 ns
tclk_loadf Clock to load falling edge 0.5 ns
DataMSBMSB-1 LSB
tsetup
tdk
clk_loadr tload
t
t
thold
Clock
Load
clk_loadf
SPI digital interface STW81102
38/53
7.3 Bit tables
Table 22. Bits at 00h and ST1
Serial interface address = 00h Register name = ST1
Bit Name Description
[23] R9
Reference clock divider ratio
[22] R8
[21] R7
[20] R6
[19] R5
[18] R4
[17] R3
[16] R2
[15] R1
[14] R0
[13] PLL_A1 VCO amplitude control
[12] PLL_A0
[11] CPSEL2
Charge pump output current control[10] CPSEL1
[9] CPSEL0
[8] PSC_SEL Prescaler modulus select (0 for P=16, 1 for P=19)
[7] INITCAL For test purposes only; must be set to 0
[6] SERCAL Enable VCO calibration (see
Section 7.4
)
[5] SELEXTCAL For test purposes only; must be set to 0
[4] CAL4
For test purposes only; must be set to 0
[3] CAL3
[2] CAL2
[1] CAL1
[0] CAL0
STW81102 SPI digital interface
39/53
Table 23. Bits at 01h and ST2
Serial interface address = 01h Register name = ST2
Bit Name Description
[23] OUTBUF_CTRL_EN Output buffer control mode enable (0 = Off, 1 = On)
[22] CAL_AUTOSTART_EN VCO calibration auto restart enable (0 = Off, 1 = On)
[21] PD4 Device functional modes:
0. Power down
1. Enable VCO A, output frequency divided by 2
2. Enable VCO B, output frequency divided by 2
3. Enable external VCO, output frequency divided by 2
4. Enable VCO A, output frequency divided by 4
5. Enable VCO B, output frequency divided by 4
6. Enable external VCO, output frequency divided by 4
7. Enable VCO A, direct output
8. Enable VCO B, direct output
9. Enable external VCO, direct output
[20] PD3
[19] PD2
[18] PD1
[17] PD0
[16] B11
B_COUNTER bits
[15] B10
[14] B9
[13] B8
[12] B7
[11] B6
[10] B5
[9] B4
[8] B3
[7] B2
[6] B1
[5] B0
[4] A4
A_COUNTER bits
[3] A3
[2] A2
[1] A1
[0] A0
SPI digital interface STW81102
40/53
The LO output frequency is programmed by setting the proper values for A, B and R
according to the following formula:
7.3.1 Default configuration
At power on, all the bits are set to ‘0’. Consequently the part starts in power down mode.
7.4 VCO calibration procedure
Calibration of the VCO center frequency is activated when the SERCAL bit (ST1 register
bit[6]) is set to 1.
To program the device properly while ensuring VCO calibration, perform the following steps
before every channel change:
1. Program the ST2 register with the desired settings (functional mode, B and A
counters).
2. Program the ST1 register with the desired settings (R counter, VCO amplitude, charge
pump, prescaler modulus) and with the SERCAL bit set to 1.
The maximum allowed PFD frequency (FPFD) during calibration is 1 MHz; if you want a FPFD
higher than 1 MHz, perform the following additional steps:
●Perform all the steps (step 1 and 2 above) of the calibration procedure, making sure to
program the desired VCO frequency with proper settings of the R, B and A counters so
that FPFD is ≤ 1 MHz.
●Program the device with the desired VCO and PFD frequency settings as per steps 1
and 2 above with SERCAL bit set to 0.
7.4.1 VCO calibration auto-restart feature
The VCO calibration auto-restart feature can be enabled in two steps:
1. set the desired frequency ensuring VCO calibration as described above (
Section 7.4
)
2. program the ST2 register with the CAL_AUTOSTART_EN bit set to '1' while keeping
unchanged the others.
where DR equals {1 for direct output
0.5 for output divided by 2
0.25 for output divided by 4
and P is the selected prescaler modulus.
FOUT DRBPA+×()×
FREF CLK–
R
-----------------------------------
×=
STW81102 Application information
41/53
8 Application information
The STW81102 features three different alternately selectable bands: direct output (3.0 to
3.62 GHz and 4.0 to 4.65 GHz), divided by 2 (1.5 to 1.81 GHz and 2.0 to 2.325 GHz) and
divided by 4 (750 to 905 MHz and 1000 to 1162.5 MHz). To achieve a suitable power level, a
good matching network is necessary to adapt the output stage to a 50 Ω load. Moreover,
since most commercial RF components have single-ended input and output terminations, a
differential to single-ended conversion may be required.
The different matching configurations shown below for each of the three bands are
suggested as a guideline when designing your own application board.
Inside the evaluation kit is the ADS design for each matching configuration suggested in this
chapter. The name of the corresponding ADS design is given in each figure.
The ADS designs provide only a first indication of the output stage matching, and should be
reworked according to the choices of layout, board substrate, components and so on.
The ADS designs of the evaluation boards are provided with a complete electromagnetic
modelling (board, components, and so on).
8.1 Direct output
If you do not need a differential to single conversion, you can match the output buffer of the
STW81102 in the simple way shown in
Figure 28
. This illustrates the differential to single-
ended output network in the 3.0 - 4.65GHz range (MATCH_LC_LUMP_4G_DIFF.dsn).
Figure 28. Differential/single-ended output network
(MATCH_LC_LUMP_4G_DIFF.dsn)
Since most discrete components for microwave applications are single-ended, you can
easily use one of the two outputs and terminate the other one to 50 Ω with a 3 dB power
loss.
RF
100 ohm
50 ohm
100 ohm 5.5nH
5.5nH
10pF
50 ohm
10pF
Vcc
Vcc
OUTP
RFOUTN
* T?
Application information STW81102
42/53
Alternatively, you can combine the two outputs in other ways. A first topology for the direct
output (3 GHz to 4.65 GHz) is suggested in
Figure 29
. It basically consists of a simple LC
balun and a matching network to adapt the output to a 50 Ω load. The two LC networks shift
output signal phase of -90° and +90°, thus combining the two outputs. This topology,
designed for a center frequency of 4 GHz, is intrinsically narrow-band since the LC balun is
tuned at a single frequency. If the application requires a different sub-band, the LC combiner
can be easily tuned to the frequency of interest.
Figure 29. LC lumped balun and matching network (MATCH_LC_LUMP_4G.dsn)
The 1.9 nH shunt inductor works as a DC feed for one of the open collector terminals as well
as a matching element along with the other components. The 1.9 nH series inductors are
used to resonate the parasitic capacitance of the chip.
For optimum output matching, it is recommended to use 0402 Murata or AVX capacitors and
0403 or 0604 HQ Coilcraft inductors. It is also advisable to use short interconnection paths
to minimize losses and undesired impedance shift.
An alternative topology that permits a more broadband matching as well as balanced to
unbalanced conversion, is shown in
Figure 30
.
RF
50 ohm
50 ohm
50 ohm 1.9nH
1.9nH
0.8pF
0.8pF
1.9nH
1.9nH
0.8pF
0.8pF 2.5pF
Vcc
Vcc
OUTP
RFOUTN
STW81102 Application information
43/53
Figure 30. Evaluation board (EVB4G) matching network (MATCH_EVB4G.dsn)
For differential to single conversion, the 50 to 100 Ω Johanson balun is recommended
(3700BL15B100).
8.2 Divided by 2 output
If your application does not require a balanced to unbalanced conversion, the output
matching reduces to the simple circuit shown below (
Figure 31
), which illustrates a
differential to single-ended output network in the 1.5 - 2.325 GHz range
(MATCH_LC_LUMP_2G_DIFF.dsn). You can easily use this solution to provide one single-
ended output that terminates the other output at 50 Ω with a 3 dB power loss.
Figure 31. Differential/single-ended output network
(MATCH_LC_LUMP_2G_DIFF.dsn)
1pF 1pF 1.2pF 1.2pF
4.7pF12pF
RF
50 ohm
50 ohm
50 ohm 5.5nH
5.5nH
12pF
2:1
12pF
Vcc
Vcc
OUTP
RFOUTN
RF
50 ohm
50 ohm
50 ohm 22nH
22nH
10pF
50 ohm
10pF
Vcc
Vcc
OUTP
RFOUTN
Application information STW81102
44/53
A first solution to combine the differential outputs is the lumped LC type balun tuned in the
2 GHz band (
Figure 32
).
Figure 32. LC lumped balun for divided by 2 output (MATCH_LC_LUMP_2G.dsn)
The same recommendation for the SMD components also applies to the divided by 2 output.
Another topology suited to combining the two outputs for the divided by 2 frequencies is
represented in
Figure 33
.
Figure 33. Evaluation board (EVB2G) matching network (MATCH_EVB2G.dsn)
RF
50 ohm
50 ohm
50 ohm 2.7nH
2.7nH
2pF
2pF
2.7nH
2.7nH
3nH
2pF
2pF 3pF
Vcc
Vcc
OUTP
RFOUTN
1.2pF
22pF
RF
50 ohm
50 ohm
50 ohm 5.5nH
1.9nH
5.5nH
22pF
2:1
22pF
Vcc
Vcc
OUTP
RFOUTN
STW81102 Application information
45/53
For differential to single conversion, the 50 to 100 Ω Johanson balun (1600BL15B100) is
recommended.
8.3 Divided by 4 output
The topology, components, values and considerations of
Figure 31
also apply to the divided
by 4 output (MATCH_LC_LUMP_1G_DIFF.dsn).
As for the previous sections, a solution to combine the differential outputs is the lumped LC
type balun tuned in the 1 GHz band (
Figure 34
).
Figure 34. LC lumped balun for divided by 4 output (MATCH_LC_LUMP_1G.dsn)
If you prefer to use an RF balun, you can adapt the topology depicted in
Figure 33
, and
change the balun and the matching components (
Figure 35
). The suggested balun for the
0.75 - 1.17 GHz frequency range is the 1:1 Johanson 900BL15C050.
RF
25 ohm
50 ohm
25 ohm 5.5nH
5.5nH
4pF
4pF
5.5nH
5.5nH 14nH
4pF
4pF 6pF
Vcc
Vcc
OUTP
RFOUTN
123$“?
Application information STW81102
46/53
Figure 35. Evaluation board (EVB1G) matching network (MATCH_EVB1G.dsn)
8.4 Evaluation kit
An evaluation kit can be delivered upon request, including the following:
●Evaluation board
●GUI (graphical user interface) to program the device
●Measured S parameters of the RF output
●ADS2005 schematics providing guidelines for application board design
●STWPLLSim software for PLL loop filter design and noise simulation
●Application program interface (API)
Three different evaluation kits are available, each optimized for one of the following
frequency ranges:
●1 GHz
●2 GHz
●4 GHz
When ordering, please specify one of the following order codes:
The three evaluation kits differ only for the output stage network and can be adapted from
one frequency band variant to a different one replacing properly the matching components
and the balun.
0.5pF
22pF
RF
25 ohm
50 ohm
25 ohm 18nH
2.1nH
18nH
8.2pF
1:1
8.2pF
Vcc
Vcc
OUTP
RFOUTN
Table 24. Order code of the evaluation kit
Part number Description
STW81102-EVB1G 1GHz frequency range - divider by 4 output optimized
STW81102-EVB2G 2GHz frequency range - divider by 2 output optimized
STW81102-EVB4G 4GHz frequency range - direct output optimized
STW81102 Application diagrams
47/53
9 Application diagrams
Figure 36. Typical application diagram
Note: 1 See Chapter 8: Application information for further information on output matching topology.
2 EXT_PD, ADD2, ADD1 (and ADD0 when the I
2
C bus is selected) can be hard wired directly
on the board.
3 Loop filter values are for F
STEP
= 200 kHz.
4 For best performance VDD
1
must be a low noise supply (20
μ
V
RMS
in 10 Hz-100 kHz BW).
VDD_ESD
VDD_VCOA DBUS_SEL
SCL/CLK
SDA/DATA
EXT_PD
ADD1
ADD0/LOAD
ADD2
VDD_DBUS
VDD_DIV2
VDD_OUTBUF
OUTBUFP
OUTBUFN
VDD_DIV4
VDD_VCOB
VCTRL
ICP
REXT
VDD_CP
TEST1
LOCK_DET
VDD_BUFVCO
EXTVCO_INP
EXTVCO_INN
VDD_PLL
REF_CLK
TEST2
10P22p1n
10P22p1n
270p 68p
2.7n
10µ22p1n
51
1.8n
STW81103
From/to microcontroller
to microcontrollerloop filter
VDD1
RF Out
ref clk
VDD1
VDD1
VDD1
VDD1
VDD2
10P22p1n
I2C
SPI
100100
15p 15p
100
15p
4.7K
8.2K
2.2K
STW81102
Application diagrams STW81102
48/53
Figure 37. Ping-pong architecture diagram
Note: 1 See Chapter 8: Application information for further information on output matching topology.
2 EXT_PD, ADD2, ADD1 (and ADD0 when the I
2
C bus is selected) can be hard wired directly
on the board.
3 Loop filter values are for F
STEP
= 200 kHz.
4 For best performance VDD
1_1
and VDD
1_2
must be low noise supplies (20
μ
V
RMS
in 10 Hz-
100 kHz BW).
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STW81102 Application diagrams
49/53
Figure 38. Application diagram with external VCO (LO output from STW81102)
Note: See Chapter 8: Application information for further information on output matching topology.
Figure 39. Application diagram with external VCO (LO output from VCO)
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Package mechanical data STW81102
50/53
10 Package mechanical data
In order to meet environmental requirements, ST offers these devices in ECOPACK®
packages, which have a lead-free second level interconnect. The category of second level
interconnect is marked on the package and on the inner box label, in compliance with
JEDEC Standard JESD97. The maximum ratings related to soldering conditions are also
marked on the inner box label. ECOPACK is an ST trademark.
ECOPACK specifications are available at: http://www.st.com.
Figure 40. VFQFPN28 mechanical drawing (
Note 1
)
Note: 1 VFQFPN stands for Thermally Enhanced Very thin Fine pitch Quad Flat Package No lead.
(Very thin: A=1.00 Max)
2 Details of the terminal 1 identifier are optional, but if given, must be located on the top
surface of the package by using either a mold or marked features.
STW81102 Package mechanical data
51/53
Table 25. Package dimensions
Ref. Min. Typ. Max. Unit
A0.800 0.900 1.000 mm
A1 0.020 0.050 mm
A2 0.650 1.000 mm
A3 0.200 mm
b0.180 0.250 0.300 mm
D4.850 5.000 5.150 mm
D1 4.750 mm
D2 2.950 3.100 3.250 mm
E4.850 5.000 5.150 mm
E1 4.750 mm
E2 2.950 3.100 3.250 mm
e0.500 mm
L0.350 0.550 0.750 mm
P0.600 mm
K14 degrees
ddd 0.080 mm
Ordering information STW81102
52/53
11 Ordering information
12 Revision history
Table 26. Order codes
Part number Temp range, °C Package Packing
STW81102AT -40 to 85 VFQFPN28 Tray
STW81102ATR -40 to 85 VFQFPN28 Tape and reel
Table 27. Document revision history
Date Revision Changes
06-Mar-2006 1 Initial release.
16-Jun-2006 2
Changed from preliminary data to maturity.
Updated
Section 2: Electrical specifications
;
Section 8: Application
information
and
Section 9: Application diagrams
.
20-Jul-2007 3
Added information usage of prescaler with modulus 16/17 for VCO
higher than 3300MHz in
Section 2.4: Electrical specifications
,
Section 5.3: Prescaler
and
Section 5.4: A and B counters
.
Moved the ordering information to
Chapter 11
.
14-Aug-2007 4 Updated
Section 6.4: VCO calibration procedure
, pin #23 description
in
Ta b l e 1
.
23-Jan-2008 5
Updated
Table 1: Pin description
.
Updated
Table 3: Operating conditions (refer to Figure 36: Typical
application diagram)
,
Table 5: Electrical specifications
,
Tabl e 6:
Phase noise specification
.
Updated
Section 5.8.2: VCO frequency calibration
.
Added
Section 5.9: Output stage
.
Added
Section 5.10: External VCO Buffer
.
Updated
FUNCTIONAL_MODE
and
CALIBRATION
registers.
Updated
Table 22: Bits at 00h and ST1
.
Updated
Section 6.3.2: Read-only register
.
Updated
Section 6.3.3: Default configuration
.
Updated
Section 6.4: VCO calibration procedure
.
Added
Section 6.4.1: VCO calibration auto-restart feature
.
Updated
Section 7.4: VCO calibration procedure
.
Added
Section 7.4.1: VCO calibration auto-restart feature
.
Added the last bullet ‘Application program interface (API)’ in
Section 8.4
.
Added
Note 4 on page 47
.
Added
Figure 37
,
Figure 38
and
Figure 39
.
STW81102
53/53
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