Datenblatt für NTGS3136P von onsemi

MOSFET L 0N Semimnduuztor® www.0nsemi.com
© Semiconductor Components Industries, LLC, 2015
May, 2019 − Rev. 2
1Publication Order Number:
NTGS3136P/D
NTGS3136P, NVGS3136P
MOSFET – Power, Single,
P-Channel, TSOP-6
-20 V, -5.8 A
Features
•Low RDS(on) in TSOP−6 Package
•1.8 V Gate Rating
•Fast Switching
•NV Prefix for Automotive and Other Applications Requiring Unique
Site and Control Change Requirements; AEC−Q101 Qualified and
PPAP Capable
•These Devices are Pb−Free, Halogen Free/BFR Free and are RoHS
Compliant
Applications
•Optimized for Battery and Load Management Applications in
Portable Equipment
•High Side Load Switch
•Switching Circuits for Game Consoles, Camera Phone, etc.
MAXIMUM RATINGS (TJ = 25°C unless otherwise stated)
Parameter Symbol Value Unit
Drain−to−Source Voltage VDSS −20 V
Gate−to−Source Voltage VGS $8.0 V
Continuous Drain
Current (Note 1) Steady
State
TA = 25°CID−5.1
A
TA = 85°C−3.6
t v 5 s TA = 25°C−5.8
Power Dissipation
(Note 1)
Steady
State TA = 25°C
PD1.25
W
t v 5 s 1.6
Continuous Drain
Current (Note 2) Steady
State
TA = 25°CID−3.7
A
TA = 85°C−2.7
Power Dissipation
(Note 2) TA = 25°CPD0.7 W
Pulsed Drain Current tp = 10 msIDM −20 A
Operating Junction and Storage Temperature TJ,
TSTG
−55 to
150
°C
Lead Temperature for Soldering Purposes
(1/8” from case for 10 s)
TL260 °C
Stresses exceeding those listed in the Maximum Ratings table may damage the
device. If any of these limits are exceeded, device functionality should not be
assumed, damage may occur and reliability may be affected.
1. Surface−mounted on FR4 board using 1 in sq pad size (Cu area = 1.127 in sq
[2 oz] including traces)
2. Surface−mounted on FR4 board using the minimum recommended pad size
(Cu area = 0.0775 in sq).
3
4
1256
P−Channel
TSOP−6
CASE 318G
STYLE 1
MARKING
DIAGRAM
XXX = Device Code
M = Date Code
G= Pb−Free Package
PIN ASSIGNMENT
321
4
GateDrain
Source
56
Drain
DrainDrain
V(BR)DSS RDS(ON) TYP ID MAX
−20 V
25 mW @ −4.5 V
32 mW @ −2.5 V
www.onsemi.com
41 mW @ −1.8 V
XXX MG
G
1
1
−5.1 A
−4.5 A
−2.5 A
(Note: Microdot may be in either location)
See detailed ordering and shipping information in the package
dimensions section on page 5 of this data sheet.
ORDERING INFORMATION
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NTGS3136P, NVGS3136P
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2
THERMAL RESISTANCE MAXIMUM RATINGS
Parameter Symbol Value Unit
Junction−to−Ambient – Steady State (Note 3) RqJA 100
°C/W
Junction−to−Ambient – t = 5 s (Note 3) RqJA 77
Junction−to−Ambient – Steady State (Note 4) RqJA 185
3. Surface−mounted on FR4 board using 1 in sq pad size (Cu area = 1.127 in sq [2 oz] including traces)
4. Surface−mounted on FR4 board using the minimum recommended pad size (Cu area = 0.0775 in sq).
ELECTRICAL CHARACTERISTICS (TJ = 25°C unless otherwise specified)
Parameter Symbol Test Condition Min Typ Max Unit
OFF CHARACTERISTICS
Drain−to−Source Breakdown Voltage V(BR)DSS VGS = 0 V, ID = −250 mA−20 V
Drain−to−Source Breakdown Voltage
Temperature Coefficient
V(BR)DSS/TJID = −250 mA, Reference 25°C−13 mV/°C
Zero Gate Voltage Drain Current IDSS VGS = 0 V,
VDS = −20 V
TJ = 25°C−1.0 mA
TJ = 85°C−5.0
Gate−to−Source Leakage Current IGSS VDS = 0 V, VGS = ±8.0 V$0.1 mA
ON CHARACTERISTICS (Note 5)
Gate Threshold Voltage VGS(TH) VGS = VDS, ID = −250 mA−0.4 −1.0 V
Negative Threshold Temperature Coefficient VGS(TH)/TJ3 mV/°C
Drain−to−Source On Resistance RDS(on) VGS = −4.5 V, ID = −5.1 A 25 33 mW
VGS = −2.5 V, ID = −4.5 A 32 40
VGS = −1.8 V, ID = −2.5 A 41 51
Forward Transconductance gFS VDS = −5.0 V, ID = −5.1 A 22 S
CHARGES, CAPACITANCES AND GATE RESISTANCE
Input Capacitance CISS
VGS = 0 V, f = 1 MHz, VDS = −10 V
1901 pF
Output Capacitance COSS 274
Reverse Transfer Capacitance CRSS 175
Total Gate Charge QG(TOT)
VGS = −4.5 V, VDS = −10 V;
ID = −5.1 A
18 29 nC
Threshold Gate Charge QG(TH) 0.7
Gate−to−Source Charge QGS 2.4
Gate−to−Drain Charge QGD 4.3
Gate Resistance RG7.6 W
SWITCHING CHARACTERISTICS (Note 6)
Turn−On Delay Time td(ON)
VGS = −4.5 V, VDD = −10 V,
ID = −1.0 A, RG = 6.0 W
9 19 ns
Rise Time Tr9 19
Turn−Off Delay Time td(OFF) 99 160
Fall Time Tf48 79
DRAIN−SOURCE DIODE CHARACTERISTICS
Forward Diode Voltage VSD VGS = 0 V,
IS = −1.7 A
TJ = 25°C−0.7 −1.2 V
TJ = 125°C−0.6
Reverse Recovery Time tRR VGS = 0 V, dIS/dt = 100 A/ms,
IS = −1.7 A
37 60 ns
Product parametric performance is indicated in the Electrical Characteristics for the listed test conditions, unless otherwise noted. Product
performance may not be indicated by the Electrical Characteristics if operated under different conditions.
5. Pulse Test: pulse width v 300 ms, duty cycle v 2%
6. Switching characteristics are independent of operating junction temperatures
NTGS3136P, NVGS3136P
www.onsemi.com
3
TYPICAL PERFORMANCE CURVES (TJ = 25°C unless otherwise noted)
0.7
0.8
0.9
1.0
1.1
1.2
1.3
1.4
1.5
−50 −25 0 25 50 75 100 125 150
0
0.02
0.04
0.06
0.08
0.10
0.12
0.14
1.0 1.5 2.0 2.5 3.0 3.5 4.0 4.5 5.0
−VDS, DRAIN−TO−SOURCE VOLTAGE (V)
−ID, DRAIN CURRENT (A)
Figure 1. On−Region Characteristics Figure 2. Transfer Characteristics
−VGS, GATE−TO−SOURCE VOLTAGE (V)
Figure 3. On−Resistance vs. Gate−to−Source
Voltage
−VGS, GATE−TO−SOURCE VOLTAGE (V)
RDS(on), DRAIN−TO−SOURCE RESISTANCE (W)
−ID, DRAIN CURRENT (A)
Figure 4. On−Resistance vs. Drain Current and
Gate Voltage
−ID, DRAIN CURRENT (A)
Figure 5. On−Resistance Variation with
Temperature
TJ, JUNCTION TEMPERATURE (°C)
TJ = 25°C
VGS = −4.5 V
−2.5 V
−2 V
−1.5 V
−1.8 V
TJ = 25°C
TJ = 125°CTJ = −55°C
ID = −5.1 A
VDS = −5 V
TJ = 25°C
VGS = −4.5 V
ID = −4.5 A
VGS = −5.1 V
RDS(on), DRAIN−TO−SOURCE
RESISTANCE (NORMALIZED)
RDS(on), DRAIN−TO−SOURCE RESISTANCE (W)
Figure 6. Capacitance Variation
DRAIN−TO−SOURCE VOLTAGE (V)
C, CAPACITANCE (pF)
VGS = 0 V
TJ = 25°C
f = 1 MHz
Coss
Ciss
Crss
−2 V
−1.8 V
0
4.0
8.0
12
16
20
0 0.5 1.0 1.5 2.0 2.5 3.0 3.5 4.0 4.5 5.0 0
5
10
15
20
0.5 0.75 1 1.25 1.5 1.75 2 2.25 2.5
TJ = 25°C
TJ = 125°C
0
0.01
0.02
0.03
0.04
0.05
0.06
0.07
0.08
0.09
0.10
0 4.0 8.0 12 16 20
−2.5 V
0
200
400
600
800
1000
1200
1400
1600
1800
2000
2200
2400
2600
2800
024681012
ID : -250 “A
NTGS3136P, NVGS3136P
www.onsemi.com
4
TYPICAL PERFORMANCE CURVES (TJ = 25°C unless otherwise noted)
Figure 7. Gate−to−Source and
Drain−to−Source Voltage vs. Total Charge
Figure 8. Diode Forward Voltage vs. Current
Figure 9. Threshold Voltage Figure 10. Single Pulse Maximum Power
Dissipation
SINGLE PULSE TIME (s)
POWER (W)
QG, TOTAL GATE CHARGE (nC)
VDS = −10 V
ID = −5.1 A
TJ = 25°C
−VGS
QGS QGD
−VDS
−VSD, SOURCE−TO−DRAIN VOLTAGE (V)
VGS = 0 V
TJ = 25°C
TJ = 150°C
Figure 11. Maximum Rated Forward Biased
Safe Operating Area
0.01
0.1
1
10
100
0.1 1 10 100
VGS = −8.0 V
SINGLE PULSE
TC = 25°C
RDS(on) LIMIT
Thermal Limit
Package Limit
100 ms
1 ms
10 ms
dc
−ID, DRAIN CURRENT (A)
−VDS, DRAIN−TO−SOURCE VOLTAGE (V)
−50 0−25 25
0.7
0.5
0.3
0.2
50 125100
TJ, JUNCTION TEMPERATURE (°C)
75 150
ID = −250 mA
−VGS(th) (V)
0.8
0.6
0.4
0
1
2
3
4
5
0 2 4 6 8 10 12 14 16 18
0
2
4
6
8
10
12
QT
−VGS, GATE−TO−SOURCE VOLTAGE (V)
1.0
10
30
0 0.2 0.4 0.6 0.8 1.0 1.2
−VDS, DRAIN−TO−SOURCE VOLTAGE (V)
−IS, SOURCE CURRENT (A)
80
70
60
50
40
30
20
10
0
1E−31E−21E−1 1 1E+1 1E+2 1E+3
0.01
0.1
1
1E−04 1E−03 1E−02 1E−01 1 1E+01 1E+02 1E+03
t, TIME (s)
R(t), EFFECTIVE TRANSIENT THERMAL
RESPONSE (NORMALIZED)
Figure 12. FET Thermal Response
Duty Cycle = 0.5
0.2
0.1
0.05
0.01
0.02
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NTGS3136P, NVGS3136P
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5
ORDERING INFORMATION
Device Marking Package Shipping†
NTGS3136PT1G SD TSOP−6
(Pb−Free) 3000 / Tape & Reel
NVGS3136PT1G* VSD
†For information on tape and reel specifications, including part orientation and tape sizes, please refer to our Tape and Reel Packaging
Specifications Brochure, BRD8011/D.
*NV Prefix for Automotive and Other Applications Requiring Unique Site and Control Change Requirements; AEC−Q101 Qualified and PPAP
Capable.
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TSOP−6
CASE 318G−02
ISSUE V
DATE 12 JUN 2012
SCALE 2:1
STYLE 1:
PIN 1. DRAIN
2. DRAIN
3. GATE
4. SOURCE
5. DRAIN
6. DRAIN
23
456
D
1
e
b
E1
A1
A
0.05
NOTES:
1. DIMENSIONING AND TOLERANCING PER ASME Y14.5M, 1994.
2. CONTROLLING DIMENSION: MILLIMETERS.
3. MAXIMUM LEAD THICKNESS INCLUDES LEAD FINISH. MINIMUM
LEAD THICKNESS IS THE MINIMUM THICKNESS OF BASE MATERIAL.
4. DIMENSIONS D AND E1 DO NOT INCLUDE MOLD FLASH,
PROTRUSIONS, OR GATE BURRS. MOLD FLASH, PROTRUSIONS, OR
GATE BURRS SHALL NOT EXCEED 0.15 PER SIDE. DIMENSIONS D
AND E1 ARE DETERMINED AT DATUM H.
5. PIN ONE INDICATOR MUST BE LOCATED IN THE INDICATED ZONE.
c
STYLE 2:
PIN 1. EMITTER 2
2. BASE 1
3. COLLECTOR 1
4. EMITTER 1
5. BASE 2
6. COLLECTOR 2
STYLE 3:
PIN 1. ENABLE
2. N/C
3. R BOOST
4. Vz
5. V in
6. V out
STYLE 4:
PIN 1. N/C
2. V in
3. NOT USED
4. GROUND
5. ENABLE
6. LOAD
XXX MG
G
XXX = Specific Device Code
A =Assembly Location
Y = Year
W = Work Week
G= Pb−Free Package
STYLE 5:
PIN 1. EMITTER 2
2. BASE 2
3. COLLECTOR 1
4. EMITTER 1
5. BASE 1
6. COLLECTOR 2
STYLE 6:
PIN 1. COLLECTOR
2. COLLECTOR
3. BASE
4. EMITTER
5. COLLECTOR
6. COLLECTOR
STYLE 7:
PIN 1. COLLECTOR
2. COLLECTOR
3. BASE
4. N/C
5. COLLECTOR
6. EMITTER
STYLE 8:
PIN 1. Vbus
2. D(in)
3. D(in)+
4. D(out)+
5. D(out)
6. GND
GENERIC
MARKING DIAGRAM*
STYLE 9:
PIN 1. LOW VOLTAGE GATE
2. DRAIN
3. SOURCE
4. DRAIN
5. DRAIN
6. HIGH VOLTAGE GATE
STYLE 10:
PIN 1. D(OUT)+
2. GND
3. D(OUT)−
4. D(IN)−
5. VBUS
6. D(IN)+
1
1
*For additional information on our Pb−Free strategy and soldering
details, please download the ON Semiconductor Soldering and
Mounting Techniques Reference Manual, SOLDERRM/D.
SOLDERING FOOTPRINT*
STYLE 11:
PIN 1. SOURCE 1
2. DRAIN 2
3. DRAIN 2
4. SOURCE 2
5. GATE 1
6. DRAIN 1/GATE 2
STYLE 12:
PIN 1. I/O
2. GROUND
3. I/O
4. I/O
5. VCC
6. I/O
*This information is generic. Please refer to device data sheet
for actual part marking. Pb−Free indicator, “G” or microdot “
G”, may or may not be present.
XXXAYWG
G
1
STANDARDIC
XXX = Specific Device Code
M = Date Code
G= Pb−Free Package
DIM
A
MIN NOM MAX
MILLIMETERS
0.90 1.00 1.10
A1 0.01 0.06 0.10
b0.25 0.38 0.50
c0.10 0.18 0.26
D2.90 3.00 3.10
E2.50 2.75 3.00
e0.85 0.95 1.05
L0.20 0.40 0.60
0.25 BSC
L2
−
0°10°
STYLE 13:
PIN 1. GATE 1
2. SOURCE 2
3. GATE 2
4. DRAIN 2
5. SOURCE 1
6. DRAIN 1
STYLE 14:
PIN 1. ANODE
2. SOURCE
3. GATE
4. CATHODE/DRAIN
5. CATHODE/DRAIN
6. CATHODE/DRAIN
STYLE 15:
PIN 1. ANODE
2. SOURCE
3. GATE
4. DRAIN
5. N/C
6. CATHODE
1.30 1.50 1.70
E1
E
RECOMMENDED
NOTE 5
L
C
M
H
L2
SEATING
PLANE
GAUGE
PLANE
DETAIL Z
DETAIL Z
0.60
6X
3.20 0.95
6X
0.95
PITCH
DIMENSIONS: MILLIMETERS
M
STYLE 16:
PIN 1. ANODE/CATHODE
2. BASE
3. EMITTER
4. COLLECTOR
5. ANODE
6. CATHODE
STYLE 17:
PIN 1. EMITTER
2. BASE
3. ANODE/CATHODE
4. ANODE
5. CATHODE
6. COLLECTOR
MECHANICAL CASE OUTLINE
PACKAGE DIMENSIONS
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TSOP−6
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