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Datenblatt für MAX77650,51 von Analog Devices Inc./Maxim Integrated
MAX77650IMAX77651 Ultra-Low Power PMIC with 3-Output SIMO
maxim
Integrated ,,
General Description
The MAX77650/MAX77651 provide highly-integrated bat-
tery charging and power supply solutions for low-power
wearable applications where size and efficiency are
critical. Both devices feature a SIMO buck-boost regulator
that provides three independently programmable power
rails from a single inductor to minimize total solution
size. A 150mA LDO provides ripple rejection for audio
and other noise-sensitive applications. A highly configu-
rable linear charger supports a wide range of Li+ battery
capacities and includes battery temperature monitoring
for additional safety (JEITA).
The devices include other features such as current sinks
for driving LED indicators and an analog multiplexer that
switches several internal voltage and current signals to an
external node for monitoring with an external ADC. A bidi-
rectional I2C interface allows for configuring and check-
ing the status of the devices. An internal on/off controller
provides a controlled startup sequence for the regulators
and provides supervisory functionality when the devices
are on. Numerous factory programmable options allow
the device to be tailored for many applications, enabling
faster time to market.
Benefits and Features
●Highly Integrated
• Smart Power Selector™ Li+/Li-Poly Charger
• 3 Output, Single-Inductor Multiple-Output (SIMO)
Buck-Boost Regulator
• 150mA LDO
• 3-Channel Current Sink Driver
• Analog MUX Output for Power Monitoring
●Low Power
• 0.3μA Shutdown Current
• 5.6μA Operating Current (3 SIMO Channels +
LDO)
●Charger Optimized for Small Battery Size
• Programmable Fast-Charge Current from 7.5mA to
300mA
• Programmable Battery Regulation Voltage from
3.6V to 4.6V
• Programmable Termination Current from 0.375mA
to 45mA
• JEITA Battery Temperature Monitors Adjust Charge
Current and Battery Regulation Voltage for Safe
Charging
●Flexible and Configurable
• I2C Compatible Interface and GPIO
• Factory OTP Options Available
●Small Size
• 2.75mm x 2.15mm x 0.7mm WLP Package
• 30-Bump, 0.4mm-Pitch WLP, 6x5 Array
• Small Total Solution Size (19.2mm2)
Applications
●Bluetooth Headphones/Hearables
●Fitness, Health, and Activity Monitors
●Portable Devices
●Internet of Things (IoT)
Ordering Information appears at end of data sheet.
19-8550; Rev 7; 9/18
Smart Power Selector is a trademark of Maxim Integrated
Products, Inc.
Simplified Application Circuit
PWR_HLD
GPIO
VBUS
CHGIN VSYS
SYS
GND
PGND
2.05VSBB0
1.2VSBB1
1.5µH
LXA
LXB VIO
SDA
SCL
nIRQ
IN_LDO
1.85VLDO
nEN
nRST
3.3VSBB2
LED0
LED1
LED2 PROCESSOR
VIO/Power
SYS
ADC INPUT
MAX77650
PWR_HLD
nRST
SDA
SCL
nIRQ
SYSTEM
RESOURCES
IN_SBB
GPIO
*
*
AMUX AMUX
BATT
+
THM
TBIAS
*
*
*PULLUP RESISTORS NOT DRAWN
BST
MAX77650/MAX77651 Ultra-Low Power PMIC with 3-Output SIMO
and Power Path Charger for Small Li+
EVALUATION KIT AVAILABLE
Click here for production status of specific part numbers.
General Description ............................................................................ 1
Benefits and Features .......................................................................... 1
Applications .................................................................................. 1
Simplified System Diagram ...................................................................... 1
Absolute Maximum Ratings ...................................................................... 7
Package Information ........................................................................... 7
Electrical Characteristics—Top Level .............................................................. 9
Electrical Characteristics—Global Resources....................................................... 10
Electrical Characteristics—Smart Power Selector Charger ............................................ 12
Electrical Characteristics—Adjustable Thermistor Temperature Monitors ................................. 16
Electrical Characteristics—Analog Multiplexer and Power Monitor AFEs.................................. 16
Electrical Characteristics—SIMO Buck-Boost....................................................... 17
Electrical Characteristics—LDO ................................................................. 19
Electrical Characteristics—Current Sinks .......................................................... 21
Electrical Characteristics—I2C Serial Interface...................................................... 22
Typical Operating Characteristics ................................................................ 25
Pin Configuration ............................................................................. 34
Pin Description ............................................................................... 34
Detailed Description........................................................................... 36
Support Materials ...........................................................................36
Top-Level Interconnect Simplified Diagram .......................................................36
Global Resources............................................................................. 38
Features and Benefits........................................................................38
Voltage Monitors ............................................................................38
SYS POR Comparator .....................................................................38
SYS Undervoltage Lockout Comparator .......................................................38
SYS Overvoltage Lockout Comparator ........................................................38
nEN Enable Input ...........................................................................38
nEN Manual Reset........................................................................38
nEN Dual-functionality: Push-Button vs. Slide-Switch ............................................39
Interrupts (nIRQ) ............................................................................39
Reset Output (nRST) ........................................................................39
Power Hold Input (PWR_HLD) .................................................................39
General-Purpose Input Output (GPIO) ...........................................................40
On/Off Controller............................................................................42
Flexible Power Sequencer ..................................................................46
Debounced Inputs (nEN, GPI, CHGIN) ..........................................................49
Smart Power Selector Charger .................................................................. 50
TABLE OF CONTENTS
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MAX77650/MAX77651 Ultra-Low Power PMIC with 3-Output SIMO
and Power Path Charger for Small Li+
Features ..................................................................................50
Charger Symbol Reference Guide ..............................................................51
Smart Power Selector........................................................................52
Input Current Limiter .........................................................................52
Minimum Input Voltage Regulation ..............................................................52
Minimum System Voltage Regulation ............................................................52
Die Temperature Regulation ...................................................................52
Charger State Machine .......................................................................53
Charger Off State.........................................................................54
Prequalification State......................................................................54
Fast-Charge States .......................................................................54
Top-Off State ............................................................................54
Done State ..............................................................................54
Prequalification Timer Fault State . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 54
Fast-Charge Timer Fault State ..............................................................55
Battery Temperature Fault State .............................................................55
JEITA-Modified States .....................................................................55
Typical Charge Profile .....................................................................55
Charger Applications Information ...............................................................56
Configuring a Valid System Voltage ..........................................................56
CHGIN/SYS/BATT Capacitor Selection........................................................56
Adjustable Thermistor Temperature Monitors ....................................................... 57
Thermistor Bias .............................................................................59
Configurable Temperature Thresholds ...........................................................59
Thermistor Applications Information .............................................................60
Using Different Thermistor β ................................................................60
NTC Thermistor Selection ..................................................................60
Analog Multiplexer & Power Monitor AFEs ......................................................... 61
Measuring Battery Current ....................................................................62
Method for Measuring Discharging Current ....................................................62
Method for Measuring Charging Current.......................................................62
SIMO Buck-Boost............................................................................. 63
SIMO Benefits and Features ..................................................................63
SIMO Control Scheme .......................................................................64
SIMO Soft-Start ............................................................................64
SIMO Registers.............................................................................64
SIMO Active Discharge Resistance .............................................................64
SIMO Applications Information .................................................................65
SIMO Available Output Current ..............................................................65
TABLE OF CONTENTS (CONTINUED)
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MAX77650/MAX77651 Ultra-Low Power PMIC with 3-Output SIMO
and Power Path Charger for Small Li+
TABLE OF CONTENTS (CONTINUED)
Inductor Selection ........................................................................65
Input Capacitor Selection...................................................................66
Boost Capacitor Selection ..................................................................66
Output Capacitor Selection .................................................................66
SIMO Switching Frequency .................................................................66
Unused Outputs ..........................................................................67
LDO ....................................................................................... 67
Features ..................................................................................67
LDO Simplified Block Diagram .................................................................67
LDO Active Discharge Resistor ................................................................67
LDO Soft-Start .............................................................................68
LDO Applications Information..................................................................68
Input and Output Capacitor Selection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 68
Current Sinks ................................................................................ 71
Current Sink Applications Information ...........................................................71
LED Assignment .........................................................................71
Unused Current Sink Ports .................................................................71
I2C Serial Interface ........................................................................... 72
I2C System Configuration .....................................................................72
I2C Interface Power..........................................................................72
I2C Data Transfer ...........................................................................72
I2C Start and Stop Conditions .................................................................72
I2C Acknowledge Bit .........................................................................73
I2C Slave Address...........................................................................73
I2C Clock Stretching .........................................................................74
I2C General Call Address .....................................................................74
I2C Device ID ..............................................................................74
I2C Communication Speed ....................................................................74
I2C Communication Protocols..................................................................75
Writing to a Single Register .................................................................75
Writing Multiple Bytes to Sequential Registers ..................................................76
Reading from a Single Register..............................................................77
Reading from Sequential Registers ...........................................................77
Engaging HS-mode for operation up to 3.4MHz .................................................78
Typical Application Circuit ...................................................................... 79
Ordering Information .......................................................................... 80
Revision History .............................................................................. 81
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MAX77650/MAX77651 Ultra-Low Power PMIC with 3-Output SIMO
and Power Path Charger for Small Li+
LIST OF FIGURES
Figure 1. Top-Level Interconnect Simplified Diagram ................................................. 37
Figure 2. nEN Usage Timing Diagram............................................................. 39
Figure 3. GPIO Block Diagram ...................................................................41
Figure 4. Top-Level On/Off Controller ............................................................. 43
Figure 5. Power-Up/Power-Down Sequence ........................................................ 45
Figure 6. Flexible Power Sequencer Basic Timing Diagram ............................................ 46
Figure 7. Startup Timing Diagram Due to nEN ...................................................... 47
Figure 8. Startup Timing Diagram Due to Charge Source Insertion ...................................... 48
Figure 9. Debounced Inputs..................................................................... 49
Figure 10. Linear Charger Simplified Block Diagram ................................................. 50
Figure 11. Charger Simplified Control Loops........................................................ 51
Figure 12. Charger State Diagram ................................................................ 53
Figure 13. Example Battery Charge Profile ......................................................... 55
Figure 14. Thermistor Logic Functional Diagram..................................................... 57
Figure 15. Safe-Charging Profile Example ......................................................... 58
Figure 16. Thermistor Bias State Diagram.......................................................... 59
Figure 17. Thermistor Circuit with Adjusting Series and Parallel Resistors................................. 60
Figure 18. SIMO Detailed Block Diagram .......................................................... 63
Figure 19. LDO Capacitance for Stability .......................................................... 69
Figure 20. LDO Simplified Block Diagram .......................................................... 69
Figure 21. Current Sink Block Diagram ............................................................ 70
Figure 22. I2C Simplified Block Diagram ........................................................... 71
Figure 23. I2C System Configuration.............................................................. 72
Figure 24. I2 C Start and Stop Conditions .......................................................... 72
Figure 25. Acknowledge Bit ..................................................................... 73
Figure 26. Slave Address Example ............................................................... 73
Figure 27. Writing to a Single Register with the Write Byte Protocol...................................... 75
Figure 28. Writing to Sequential registers X to N .................................................... 76
Figure 29. Reading from a Single Register with the Read Byte Protocol .................................. 77
Figure 30. Reading Continuously from Sequential Registers X to N...................................... 77
Figure 31. Engaging HS Mode ................................................................... 78
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MAX77650/MAX77651 Ultra-Low Power PMIC with 3-Output SIMO
and Power Path Charger for Small Li+
LIST OF TABLES
Table 1. Regulator Summary .................................................................... 36
Table 2. On/Off Controller Transition/State ......................................................... 44
Table 3. Charger Quick Symbol Reference Guide.................................................... 51
Table 4. Trip Temperatures vs. Trip Voltages for Different NTC β........................................ 59
Table 5. Example RS and RP Correcting Values for NTC β Above 3380K ................................ 60
Table 6. NTC Thermistors ...................................................................... 60
Table 7. AMUX Signal Transfer Functions .......................................................... 61
Table 8. Battery Current Direction Decode ......................................................... 62
Table 9. SIMO Available Output Current for Common Applications ...................................... 65
Table 10. Example Inductors .................................................................... 65
Table 11. I2C Slave Address Options...............................................................74
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MAX77650/MAX77651 Ultra-Low Power PMIC with 3-Output SIMO
and Power Path Charger for Small Li+
nEN, PWR_HLD, nIRQ, nRST to GND .....-0.3V to VSYS + 0.3V
SCL, SDA, GPIO to GND ............................. -0.3V to VIO + 0.3V
CHGIN to GND ................................................... -0.3V to +30.0V
SYS, BATT to GND ..............................................-0.3V to +6.0V
SYS to IN_SBB ....................................................-0.3V to +0.3V
VL to GND ............................................................-0.3V to +6.0V
AMUX, THM, TBIAS to GND ................................ -0.3V to +6.0V
nIRQ, nRST, SDA, AMUX, GPIO Continous Current ....... ±20mA
CHGIN Continuous Current...........................................1.2ARMS
SYS Continuous Current ...............................................1.2ARMS
BATT Continuous Current (Note 1) ...............................1.2ARMS
LDO to GND (Note 2) ........................... -0.3V to VIN_LDO + 0.3V
IN_LDO, VIO to GND ................................. -0.3V to the lower of
(VSYS + 0.3V) and +6.0V
LED0, LED1, LED2 to LGND ...............................-0.3V to +6.0V
IN_SBB to PGND .................................................-0.3V to +6.0V
LXA Continuous Current (Note 3) .................................1.2ARMS
LXB Continuous Current (Note 4) .................................1.2ARMS
SBB0, SBB1, SBB2 to PGND (Note 2) ................-0.3V to +6.0V
BST to IN_SBB ..................................................... -0.3V to +6.0V
BST to LXB ........................................................... -0.3V to +6.0V
SBB0, SBB1, SBB2 Short-Circuit Duration ............... Continuous
PGND to GND ......................................................-0.3V to +0.3V
LGND to GND ......................................................-0.3V to +0.3V
Operating Temperature Range ........................... -40°C to +85°C
Junction Temperature ...................................................... +150°C
Storage Temperature Range ............................ -65°C to +150°C
Soldering Temperature (reflow) ....................................... +260°C
Continuous Power Dissipation (Multilayer Board)
(TA = +70°C, derate 20.4mW/°C above +70°C) ........ 1632mW
PACKAGE CHARACTERISTICS VALUES
Package Code W302H2+1
Outline Number 21-100047
Land Pattern Number Refer to Application Note 1891
Thermal Resistance, Four-Layer Board:
Junction-to-Ambient (θJA)49°C/W (2s2p board)
Absolute Maximum Ratings
Stresses beyond those listed under “Absolute Maximum Ratings” may cause permanent damage to the device. These are stress ratings only, and functional operation of the device at these
or any other conditions beyond those indicated in the operational sections of the specifications is not implied. Exposure to absolute maximum rating conditions for extended periods may affect
device reliability.
Package thermal resistances were obtained using the method described in JEDEC specification JESD51-7, using a four-layer board.
For detailed information on package thermal considerations, refer to www.maximintegrated.com/thermal-tutorial.
For the latest package outline information and land patterns (footprints), go to www.maximintegrated.com/packages. Note that a “+”,
“#”, or “-” in the package code indicates RoHS status only. Package drawings may show a different suffix character, but the drawing
pertains to the package regardless of RoHS status.
Package Information
Note 1: Do not repeatedly hot-plug a source to the BATT terminal at a rate greater than 10Hz. Hot plugging low-impedance sources
results in an ~8A momentary (~2µs) current spike.
Note 2: When the active discharge resistor is engaged, limit its power dissipation to an average of 10mW.
Note 3: LXA has internal clamping diodes to PGND and IN_SBB. It is normal for these diodes to briefly conduct during switching
events. Avoid steady-state conduction of these diodes.
Note 4: Do not externally bias LXB. LXB has an internal low-side clamping diode to PGND, and an internal high-side clamping
diode that dynamically shifts to the selected SIMO output. It is normal for these internal clamping diodes to briefly conduct
during switching events. When the SIMO regulator is disabled, the LXB to PGND absolute maximum voltage is -0.3V to
VSBB0 + 0.3V.
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MAX77650/MAX77651 Ultra-Low Power PMIC with 3-Output SIMO
and Power Path Charger for Small Li+
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Package Information (continued)
e
E1
D1
b
SE
SD
0.05
M S
AB
B
A
E
D
Pin 1
Indicator
Marking
see Note 7
A3
A2
A
A1
0.05
S
S
FRONT VIEW
TOP VIEW
BOTTOM VIEW
A
1
0.64
0.19
0.45
0.040
0.27
1.60
2.00
0.40
0.00
0.20
A
AAAA
SIDE VIEW
2.148
2.748
1 65432
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D
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B
TITLE
DOCUMENT CONTROL NO.
REV.
1
1
APPROVAL
COMMON DIMENSIONS
A
A2
A1
A3
b
E1
D1
e
SD
SE
0.05
0.03
0.03
BASIC
REF
BASIC
NOTES:
1. Terminal pitch is defined by terminal center to center value.
2. Outer dimension is defined by center lines between scribe lines.
3. All dimensions in millimeter.
4. Marking shown is for package orientation reference only.
5. Tolerance is ± 0.02 unless specified otherwise.
6. All dimensions apply to PbFree (+) package codes only.
7. Front - side finish can be either Black or Clear.
BASIC
BASIC
- DRAWING NOT TO SCALE -
A
BASIC
BASIC
maxim
integrated
TM
21-100047
PACKAGE OUTLINE 30 BUMPS
WLP PKG. 0.4 mm PITCH,
W302H2+1
D
0.025
0.025
E
DEPOPULATED BUMPS:
NONE
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MAX77650/MAX77651 Ultra-Low Power PMIC with 3-Output SIMO
and Power Path Charger for Small Li+
(VCHGIN = 0V, VSYS = VBATT = VIN_SBB = VIN_LDO = 3.7V, VIO = 1.8V, limits are 100% production tested at TA = +25°C, limits over
the operating temperature range (TA = -40°C to +85°C) are guaranteed by design and characterization, unless otherwise noted.)
PARAMETER SYMBOL CONDITIONS MIN TYP MAX UNITS
Operating Voltage
Range VSYS 2.7 5.5 V
Shutdown Supply
Current ISHDN
Current measured
into BATT and SYS
and IN_SBB and
IN_LDO, all
resources are off
(LDO, SBB0, SBB1,
SBB2, LED0, LED1,
LED2), TA = 25°C
Main bias is off
(SBIA_EN = 0). This
is the standby state
0.3 1
μA
Main bias is on in
low-power mode
(SBIA_EN = 1,
SBIA_LPM = 1)
1
Main bias is on in
normal-power mode
(SBIA_EN = 1,
SBIA_LPM = 0)
28
Quiescent Supply
Current IQ
Current measured
into BATT and SYS
and IN_SBB and
IN_LDO. LDO,
SBB0, SBB1, and
SBB2 are enabled
with no load. LED0,
LED1, and LED2
are disabled
Main bias is in
low-power mode
(SBIA_LPM = 1)
5.6 13
μA
Main bias is in
normal-power mode
(SBIA_LPM = 0)
40 60
Electrical Characteristics—Top Level
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MAX77650/MAX77651 Ultra-Low Power PMIC with 3-Output SIMO
and Power Path Charger for Small Li+
(VSYS = 3.7V, limits are 100% production tested at TA = +25°C, limits over the operating temperature range (TA = -40°C to +85°C) are
guaranteed by design and characterization, unless otherwise noted.)
PARAMETER SYMBOL CONDITIONS MIN TYP MAX UNITS
POWER-ON RESET (POR)
POR Threshold VPOR VSYS falling 1.6 1.9 2.1 V
POR Threshold
Hysteresis 100 mV
UNDERVOLTAGE LOCKOUT (UVLO)
UVLO Threshold VSYSUVLO
VSYS falling, UVLO_F[3:0] = 0xA 2.5 2.6 2.7
V
VSYS falling, UVLO_F[3:0] = 0xF 2.75 2.85 2.95
UVLO Threshold
Hysteresis VSYSUVLO_HYS UVLO_H[3:0] = 0x5 300 mV
OVERVOLTAGE LOCKOUT (OVLO)
OVLO Threshold VSYSOVLO VSYS rising 5.70 5.85 6.00 V
THERMAL MONITORS
Overtemperature
Lockout Threshold TOTLO TJ rising 165 °C
Thermal Alarm
Temperature 1 TJAL1 TJ rising 80 °C
Thermal Alarm
Temperature 2 TJAL2 TJ rising 100 °C
Thermal Alarm
Temperature Hysteresis 15 °C
ENABLE INPUT (nEN)
nEN Input Leakage
Current InEN_LKG VSYS = 5.5V, VnEN =
0V, and 5.5V
TA = +25°C -1 ±0.001 +1 μA
TA = +85°C ±0.01
Electrical Characteristics—Global Resources
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MAX77650/MAX77651 Ultra-Low Power PMIC with 3-Output SIMO
and Power Path Charger for Small Li+
(VSYS = 3.7V, limits are 100% production tested at TA = +25°C, limits over the operating temperature range (TA = -40°C to +85°C) are
guaranteed by design and characterization, unless otherwise noted.)
PARAMETER SYMBOL CONDITIONS MIN TYP MAX UNITS
nEN Input Falling
Threshold VTH_nEN_F nEN falling VSYS
- 1.4
VSYS
- 1.0 V
nEN Input Rising
Threshold VTH_nEN_F nEN falling VSYS
- 0.9
VSYS
- 0.6 V
Debounce Time tDBNC_nEN
DBEN_nEN = 0 100 μs
DBEN_nEN = 1 30 ms
Manual Reset Time tMRST
MRT_OTP = 0 14 16 20 s
MRT_OTP = 1 7 8 10.5
POWER HOLD INPUT (PWR_HLD)
PWR_HLD Input
Leakage Current IPWR_HLD_LKG
VSYS = VIO = 5.5V,
VPWR_HLD = 0V,
and 5.5V
TA = +25°C -1 ±0.001 +1 μA
TA = +85°C ±0.01
PWR_HLD Input
Voltage Low VIL VIO = 1.8V 0.3 x
VIO
V
PWR_HLD Input
Voltage High VIH VIO = 1.8V 0.7 x
VIO
V
PWR_HLD Input
Hysteresis VHYS VIO = 1.8V 50 mV
PWR_HLD Glitch Filter tPWR_HLD_GF Both rising and falling edges are filtered 100 μs
PWR_HLD Wait Time tPWR_HLD_WAIT
Maximum time for PWR_HLD input to assert
after nRST deasserts during the power-up
sequence
3.5 4.0 5.0 s
OPEN-DRAIN INTERRUPT OUTPUT (nIRQ)
Output Voltage Low VOL ISINK = 2mA 0.4 V
Output Falling Edge
Time tf_nIRQ CIRQ = 25pF 2 ns
Leakage Current InIRQ_LKG
VSYS = VIO = 5.5V,
nIRQ set to be high
impedance (i.e., no
interrupts), VnIRQ =
0V and 5.5V
TA = +25°C -1 ±0.001 +1
μA
TA = +85°C ±0.01
OPEN-DRAIN RESET OUTPUT (nRST)
Output Voltage Low VOL ISINK = 2mA 0.4 V
Output Falling Edge
Time tf_nRST CRST = 25pF 2 ns
nRST Deassert Delay
Time tRSTODD
See Figure 5 and Figure 7 for more
information 5.12 ms
nRST Assert Delay Time tRSTOAD See Figure 5 for more information 10.24 ms
Leakage Current InRST_LKG
VSYS = VIO = 5.5V,
nRST set to be high
impedance (i.e., not
reset), VnRST = 0V
and 5.5V
TA = +25°C -1 ±0.001 +1
μA
TA = +85°C ±0.01
Electrical Characteristics—Global Resources (continued)
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MAX77650/MAX77651 Ultra-Low Power PMIC with 3-Output SIMO
and Power Path Charger for Small Li+
(VSYS = 3.7V, limits are 100% production tested at TA = +25°C, limits over the operating temperature range (TA = -40°C to +85°C) are
guaranteed by design and characterization, unless otherwise noted.)
(VCHGIN = 5.0V, VSYS = 4.5V, VBATT = 4.2V, limits are 100% production tested at TA = +25°C, limits over the operating temperature
range (TA = -40°C to +85°C) are guaranteed by design and characterization, unless otherwise noted.)
PARAMETER SYMBOL CONDITIONS MIN TYP MAX UNITS
GENERAL-PURPOSE INPUT/OUTPUT (GPIO)
Input Voltage Low VIL VIO = 1.8V 0.3 x
VIO
V
Input Voltage High VIH VIO = 1.8V 0.7 x
VIO
V
Input Leakage Current IGPI_LKG
DIR = 1, VIO = 5.5V,
VGPIO = 0V and
5.5V
TA = +25°C -1 ±0.001 +1
μA
TA = +85°C ±0.01
Output Voltage Low VOL ISINK = 2mA 0.4 V
Output Voltage High VOH ISOURCE = 1mA 0.8 x
VIO
V
Input Debounce Time tDBNC_GPI DBEN_GPI = 1 30 ms
Output Falling Edge
Time tf_GPIO CGPIO = 25pF 3 ns
Output Rising Edge
Time tr_GPIO CGPIO = 25pF 3 ns
FLEXIBLE POWER SEQUENCER
Power-Up Event Periods tEN See Figure 6 1.28 ms
Power-Down Event
Periods tDIS See Figure 6 2.56 ms
PARAMETER SYMBOL CONDITIONS MIN TYP MAX UNITS
DC INPUT
CHGIN Valid Voltage
Range VCHGIN
Initial CHGIN voltage before enabling
charging 4.10 7.25 V
CHGIN Standoff Voltage
Range VSTANDOFF DC rising 28 V
CHGIN Overvoltage
Threshold VCHGIN_OVP DC rising 7.25 7.50 7.75 V
CHGIN Overvoltage
Hysteresis 100 mV
CHGIN Undervoltage
Lockout VCHGIN_UVLO DC rising 3.9 4.0 4.1 V
CHGIN Undervoltage
Lockout Hysteresis 500 mV
Input Current Limit
Range ICHGIN-LIM
VSYS = VSYS-REG - 100mV , programmable
in 95mA steps 95 475 mA
Electrical Characteristics—Global Resources (continued)
Electrical Characteristics—Smart Power Selector Charger
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MAX77650/MAX77651 Ultra-Low Power PMIC with 3-Output SIMO
and Power Path Charger for Small Li+
(VCHGIN = 5.0V, VSYS = 4.5V, VBATT = 4.2V, limits are 100% production tested at TA = +25°C, limits over the operating temperature
range (TA = -40°C to +85°C) are guaranteed by design and characterization, unless otherwise noted.)
PARAMETER SYMBOL CONDITIONS MIN TYP MAX UNITS
Input Current Limit
Accuracy
ICHGIN-LIM = 95mA, VSYS = VSYS-REG -
100mV 90 95 100 mA
Minimum Input Voltage
Regulation Range VCHGIN-MIN
VCHGIN falling due to loading conditions
and/or high-impedance charge source,
programmable in 100mV increments with
VCHGIN_MIN[2:0].
4.0 4.7 V
Minimum Input Voltage
Regulation Accuracy
VCHGIN-MIN = 4.5V (VCHGIN_MIN[2:0] =
0b101), ICHGIN reduced by 10% 4.32 4.50 4.68 V
Charger Input
Debounce Timer tCHGIN-DB
VCHGIN = 5V, time before CHGIN is
allowed to deliver current to SYS or BATT 100 120 140 ms
SUPPLY AND QUIESCENT CURRENTS
BATT Bias Current IBATT-BIAS
VCHGIN = 5V, charger is not in USB
suspend (USBS = 0), charging is finished
(CHG_DTLS indicate done), ISYS = 0mA
5μA
CHGIN Supply Current ICHGIN
VCHGIN = 5V, charger is not in USB
suspend (USBS = 0), Charging is finished
(CHG_DTLS indicate done), ISYS = 0mA
1.0 1.8 mA
VCHGIN = 0V to 1V, VBATT = 3.3V, ISYS =
0A 50 μA
CHGIN Suspend Supply
Current ICHGIN
VCHGIN = 5V, charger in USB suspend
(USBS = 1) 50 μA
PREQUALIFICATIONS
Charge Current
Soft-Start Slew Time Zero to full scale 1 ms
Input Current
Soft-Start Slew Time Zero to full scale 1 ms
Prequalification Voltage
Threshold Range VPQ
Charger is in prequalification mode when
VBATT < VPQ, this threshold has 100mV of
hysteresis, programmable in 100mV steps
with CHG_PQ[2:0]
2.3 3.0 V
Prequalification Voltage
Threshold Accuracy VPQ = 3.0V -3 +3 %
Prequalification Mode
Charge Current IPQ
VBATT = 2.5V, VPQ = 3.0V, expressed as a
percentage of IFAST-CHG, I_PQ = 0 10
%
VBATT = 2.5V, VPQ = 3.0V, expressed as a
percentage of IFAST-CHG, I_PQ = 1 20
Prequalification Safety
Timer tPQ VBATT < VPQ = 3.0V 27 30 33 minutes
Electrical Characteristics—Smart Power Selector Charger (continued)
www.maximintegrated.com Maxim Integrated
│
13
MAX77650/MAX77651 Ultra-Low Power PMIC with 3-Output SIMO
and Power Path Charger for Small Li+
(VCHGIN = 5.0V, VSYS = 4.5V, VBATT = 4.2V, limits are 100% production tested at TA = +25°C, limits over the operating temperature
range (TA = -40°C to +85°C) are guaranteed by design and characterization, unless otherwise noted.)
PARAMETER SYMBOL CONDITIONS MIN TYP MAX UNITS
FAST CHARGE
Fast-Charge Voltage
Range VFAST-CHG
IBATT = 0mA, programmable in 25mV
steps with CHG_CV[5:0] 3.6 4.6 V
Fast-Charge Voltage
Accuracy
IBATT = 0mA, VFAST-CHG = 4.3V, VSYS =
4.5V, TA = +25°C -0.5 ±0.15 +0.5
%
IBATT = 0mA, VFAST-CHG = 3.6V to 4.6V,
VSYS = 4.8V 1.0
Fast-Charge Current
Range IFAST-CHG
Programmable in 7.5mA steps with CHG_
CC[5:0] 7.5 300 mA
Fast-Charge Current
Accuracy
IFAST-CHG = 15mA, TA = 25°C, VBATT =
VFAST-CHG - 300mV -1.5 +1.5
%
IFAST-CHG = 300mA, TA = 25°C, VBATT =
VFAST-CHG - 300mV -1.5 +1.5
Fast-Charge Current
Accuracy over
Temperature
Across all current settings, VBATT = VFAST-
CHG - 300mV -10 +10 %
Fast-Charge Safety
Timer Range tFC
Programmable in 2 hour increments or
disabled with T_FAST_CHG[1:0], from
prequal done to timer fault
3 7 hours
Fast-Charge Safety
Timer Accuracy tFC = 3 hours -10 +10 %
Fast-Charge Safety
Timer Suspend
Threshold
Fast-charge CC mode, loading conditions
and/or a weak charging source caused
charge current to drop below this threshold,
expressed as a percentage of IFAST-CHG
20 %
Junction Temperature
Regulation Setting
Range
TJ-REG
Programmable in 10°C steps with
TJ_REG[2:0] 60 100 °C
Junction Temperature
Regulation Loop Gain GTJ-REG
Rate at which IFAST-CHG/IPQ is reduced to
maintain TJ-REG, expressed a percentage
of IFAST-CHG/IPQ per degree centigrade
rise
-5.4 %/°C
TERMINATION AND TOPOFF
End-of-Charge
Termination Current ITERM
I_TERM = 0b00 (expressed as a percentage
of IFAST-CHG)5
%
I_TERM = 0b01 (expressed as a percentage
of IFAST-CHG)7.5
I_TERM = 0b10 (expressed as a percentage
of IFAST-CHG)10
I_TERM = 0b11 (expressed as a percentage
of IFAST-CHG)15
Electrical Characteristics—Smart Power Selector Charger (continued)
www.maximintegrated.com Maxim Integrated
│
14
MAX77650/MAX77651 Ultra-Low Power PMIC with 3-Output SIMO
and Power Path Charger for Small Li+
(VCHGIN = 5.0V, VSYS = 4.5V, VBATT = 4.2V, limits are 100% production tested at TA = +25°C, limits over the operating temperature
range (TA = -40°C to +85°C) are guaranteed by design and characterization, unless otherwise noted.)
PARAMETER SYMBOL CONDITIONS MIN TYP MAX UNITS
End-of-Charge Termina-
tion Current Accuracy
IFAST-CHG = 15mA, ITERM = 1.5mA (10%
of IFAST-CHG), TA = +25°C 1.35 1.5 1.65
mA
IFAST-CHG = 300mA, ITERM = 30mA (10%
of IFAST-CHG), TA = +25°C 27 30 33
Top-Off Timer Range tTO
IBATT < ITERM, programmable in 5 minute
steps with T_TOPOFF[2:0] 0 35 minutes
Top-Off Timer Accuracy tTO = 10 minutes -10 +10 %
Charge Restart Thresh-
old VRESTART
CHG = 0 (charging done), charging re-
sumes when VBATT < VFAST-CHG - VRE-
START
65 150 mV
DEVICE ON-RESISTANCE AND LEAKAGE
BATT to SYS
On-Resistance
VBATT = 3.7V, IBATT = 300mA, VCHGIN =
0V, battery is discharging to SYS 100 mΩ
Charger FET Leakage
Current
VSYS = 4.5V, VBATT = 0V, TA = 25°C,
charger disabled 0.1 1.0
μA
VSYS = 4.5V, VBATT = 0V, TA = 85°C,
charger disabled 1
CHGIN to SYS
On-Resistance VCHGIN = 4.65V 600 mΩ
Input FET Leakage
Current
VCHGIN = 0V, VSYS = 4.2V, TA = +25°C,
body-switched diode reverse biased 0.1 1.0
μA
VCHGIN = 0V, VSYS = 4.2V, TA = +85°C,
body-switched diode is reverse biased 1
SYSTEM NODE
System Voltage
Regulation Range VSYS-REG
Programmable in 25mV steps with VSYS_
REG[4:0] 4.1 4.8 V
System Voltage
Regulation Accuracy VSYS
VSYS-REG = 4.5V, ISYS = 1mA, TA = +25°C 4.41 4.50 4.59
V
VSYS-REG = 4.5V, ISYS = 1mA, TA = -40°C
to +85°C 4.365 4.500 4.635
Minimum System
Voltage Regulation
Loop Setpoint
VSYS-MIN
VCHGIN = 5V, VSYS-REG = 4.5V, VSYS <
VSYS-REG due to ICHGIN = ICHGIN-LIM (in-
put in current-limit), battery charging, IBATT
reduced to 50% of IFAST-CHG (minimum
system voltage regulation active)
4.34 4.4 4.45 V
Supplement Mode Sys-
tem Voltage Regulation ISYS = 150mA VBATT
- 0.15V V
Electrical Characteristics—Smart Power Selector Charger (continued)
www.maximintegrated.com Maxim Integrated
│
15
MAX77650/MAX77651 Ultra-Low Power PMIC with 3-Output SIMO
and Power Path Charger for Small Li+
(VCHGIN = 5.0V, VSYS = 4.5V, VBATT = 4.2V, limits are 100% production tested at TA = +25°C, limits over the operating temperature
range (TA = -40°C to +85°C) are guaranteed by design and characterization, unless otherwise noted.)
(VCHGIN = 5.0V, VSYS = 4.5V, VBATT = 4.2V, limits are 100% production tested at TA = +25°C, limits over the operating temperature
range (TA = -40°C to +85°C) are guaranteed by design and characterization, unless otherwise noted.)
PARAMETER SYMBOL CONDITIONS MIN TYP MAX UNITS
JEITA TEMPERATURE MONITORS
TBIAS Voltage VTBIAS THM_EN = 1, VCHGIN = 5V 1.25 V
JEITA Cold Threshold
Range VCOLD
Voltage rising threshold, programmable
with THM_COLD[1:0] in 5ºC increments
when using an NTC β = 3380K
0.867 1.024 V
JEITA Cool Threshold
Range VCOOL
Voltage rising threshold, programmable
with THM_COOL[1:0] in 5ºC increments
when using an NTC β = 3380K
0.747 0.923 V
JEITA Warm Threshold
Range VWARM
Voltage falling threshold, programmable
with THM_WARM[1:0] in 5ºC increments
when using an NTC β = 3380K
0.367 0.511 V
JEITA Hot Threshold
Range VHOT
Voltage falling threshold, programmable
with THM_HOT[1:0] in 5ºC increments
when using an NTC β = 3380K
0.291 0.411 V
Temperature Threshold
Accuracy
Voltage threshold accuracy expressed as
temperature for an NTC β = 3380K ±3 °C
Temperature Threshold
Hysteresis
Temperature hysteresis set on each volt-
age threshold for an NTC β = 3380K 3 °C
JEITA Modified Fast-
Charge Voltage Range
VFAST-CHG_
JEITA
IBATT = 0mA, programmable in 25mV
steps, battery is either cool or warm 3.6 4.6 V
JEITA Modified Fast-
Charge Current Range
IFAST-CHG_JEI-
TA
Programmable in 7.5mA steps, battery is
either cool or warm 7.5 300 mA
PARAMETER SYMBOL CONDITIONS MIN TYP MAX UNITS
ANALOG MULTIPLEXER AND POWER MONITOR AFEs
Full-Scale Voltage VFS 1.25 V
SYS Voltage Monitor
Gain GVSYS
VFS corresponds to maximum VSYS-REG
setting 0.26 V/V
CHGIN POWER
CHGIN Current Monitor
Gain GICHGIN
VFS corresponds to maximum ICHGIN-LIM
setting 2.632 V/A
CHGIN Voltage Monitor
Gain GVCHGIN VFS corresponds to VCHGIN_OVP 0.167 V/V
BATT MONITOR
Battery Charge Current
Monitor Gain GIBATT-CHG
VFS corresponds to 100% of IFAST-CHG
setting (CHG_CC[5:0]) 12.5 mV/%
Electrical Characteristics—Analog Multiplexer and Power Monitor AFEs
Electrical Characteristics—Adjustable Thermistor Temperature Monitors
www.maximintegrated.com Maxim Integrated
│
16
MAX77650/MAX77651 Ultra-Low Power PMIC with 3-Output SIMO
and Power Path Charger for Small Li+
(VCHGIN = 5.0V, VSYS = 4.5V, VBATT = 4.2V, limits are 100% production tested at TA = +25°C, limits over the operating temperature
range (TA = -40°C to +85°C) are guaranteed by design and characterization, unless otherwise noted.)
PARAMETER SYMBOL CONDITIONS MIN TYP MAX UNITS
Charge Current Monitor
Accuracy
IFAST-CHG = 15mA, TA = 25°C, VBATT =
VFAST-CHG - 300mV -3.5 +3.5
%
IFAST-CHG = 300mA, TA = +25°C, VBATT =
VFAST-CHG - 300mV -3.5 +3.5
Charge Current Monitor
Accuracy over
Temperature
Across all current settings, VBATT = VFAST-
CHG - 300mV -10 +10 %
Battery Discharge
Monitor Full-Scale
Current Range
IDISCHG-SCALE
Programmable with IMON_DISCHG_
SCALE[3:0] 8.2 300 mA
Battery Discharge
Current Monitor
Accuracy
15mA to 300mA battery discharge current,
IDISCHG-SCALE = 300mA -15 +15 %
Battery Discharge
Current Monitor Offset IBATT = 0mA -0.5 +0.65 mA
Battery Voltage Monitor
Gain GVBATT
VFS corresponds to maximum VFAST-CHG
setting 0.272 V/V
ANALOG MULTIPLEXER
Channel Switching Time 0.3 μs
Off Leakage Current VAMUX = 0V, AMUX
is high impedance
TA = +25°C 1 500 nA
TA = +85°C 1 μA
THM AND TBIAS
THM Voltage Monitor
Gain GVTHM 1 V/V
TBIAS Voltage Monitor
Gain GVTBIAS 1 V/V
Electrical Characteristics—Analog Multiplexer and Power Monitor AFEs (continued)
www.maximintegrated.com Maxim Integrated
│
17
MAX77650/MAX77651 Ultra-Low Power PMIC with 3-Output SIMO
and Power Path Charger for Small Li+
(VSYS = 3.7V, VIN_SBB = 3.7V, CSBBx = 10μF, L = 1.5μH, limits are 100% production tested at TA = +25°C, limits over the operating
temperature range (TA = -40°C to +85°C) are guaranteed by design and characterization, unless otherwise noted.)
PARAMETER SYMBOL CONDITIONS MIN TYP MAX UNITS
OUTPUT VOLTAGE RANGE (SBB0)
Minimum Output
Voltage 0.8 V
Maximum Output
Voltage 2.375 V
Output DAC Bits 6 bits
Output DAC LSB Size 25 mV
OUTPUT VOLTAGE RANGE (SBB1)
Minimum Output
Voltage
MAX77650 0.8 V
MAX77651 2.4
Maximum Output
Voltage
MAX77650 1.5875 V
MAX77651 5.25
Output DAC Bits 6 bits
Output DAC LSB Size MAX77650 12.5 mV
MAX77651 50
OUTPUT VOLTAGE RANGE (SBB2)
Minimum Output
Voltage
MAX77650 0.8 V
MAX77651 2.4
Maximum Output
Voltage
MAX77650 3.95 V
MAX77651 5.25
Output DAC Bits 6 bits
Output DAC LSB Size 50 mV
OUTPUT VOLTAGE ACCURACY
Output Voltage
Accuracy
VSBBx falling,
threshold where LXA
switches high. Speci-
fied as a percentage
of target output volt-
age (Note 3)
TA = +25°C -2.5 +2.5
%
TA = -40°C to
+85°C -4.0 +4.0
TIMING CHARACTERISTICS
Enable Delay
Delay time from the SIMO receiving its first
enable signal to when it begins to switch in
order to service that output.
60 μs
Soft-Start Slew Rate dV/dtSS 3.3 5.0 6.6 mV/μs
Electrical Characteristics—SIMO Buck-Boost
www.maximintegrated.com Maxim Integrated
│
18
MAX77650/MAX77651 Ultra-Low Power PMIC with 3-Output SIMO
and Power Path Charger for Small Li+
(VSYS = 3.7V, VIN_SBB = 3.7V, CSBBx = 10μF, L = 1.5μH, limits are 100% production tested at TA = +25°C, limits over the operating
temperature range (TA = -40°C to +85°C) are guaranteed by design and characterization, unless otherwise noted.)
Note 3: Measured in an open-loop test that determines the output voltage falling threshold where LXA switches high.
Note 4: Typical values align with bench observations using the stated conditions. Minimum and maximum values are tested in pro-
duction with DC currents. See the Typical Operating Characteristics SIMO switching waveforms to gain more insight on this
specification.
PARAMETER SYMBOL CONDITIONS MIN TYP MAX UNITS
POWER STAGE CHARACTERISTICS
LXA Leakage Current
SBB0, SBB1, SBB2
are disabled,
VIN_SBB = 5.5V,
VLXA = 0V, or 5.5V
TA = +25°C -1.0 ±0.1 +1.0
μA
TA = +85°C ±1.0
LXB Leakage Current
SBB0, SBB1, SBB2
are disabled, VIN_
SBB = 5.5V, VLXA =
0V or 5.5V, all VSBBx
= 5.5V
TA = +25°C -1.0 ±0.1 +1.0
μA
TA = +85°C ±1.0
BST Leakage Current
VIN_SBB = 5.5V,
VLXB = 5.5V,
VBST = 11V
TA = +25°C +0.01 +1.0
μA
TA = +85°C +0.1
Disabled Output
Leakage Current
SBB0, SBB1, SBB2
are disabled, active-
discharge disabled
(ADE_SBBx = 0),
VSBBx = 5.5V,
VLXB = 0V, VSYS =
VIN_SBB = VBST =
5.5V
TA = +25°C +0.1 +1.0
μA
TA = +85°C +0.2
Active Discharge
Impedance RAD_SBBx
SBB0, SBB1, SBB2 are disabled, active
discharge enabled (ADE_SBBx = 1) 80 140 260 Ω
CONTROL SCHEME
Peak Current Limit
(Note 4) IP_SBB
IP_SBBx = 0b11 0.414 0.500 0.586
A
IP_SBBx = 0b10 0.589 0.707 0.806
IP_SBBx = 0b01 0.713 0.866 0.947
IP_SBBx = 0b00 0.892 1.000 1.108
Electrical Characteristics—SIMO Buck-Boost (continued)
www.maximintegrated.com Maxim Integrated
│
19
MAX77650/MAX77651 Ultra-Low Power PMIC with 3-Output SIMO
and Power Path Charger for Small Li+
(VSYS = 3.7V, VIN_LDO = 2.05V, VLDO = 1.85V, CLDO = 10μF, limits are 100% production tested at TA = +25°C, limits over the operating
temperature range (TA = -40°C to +85°C) are guaranteed by design and characterization, unless otherwise noted.)
PARAMETER SYMBOL CONDITIONS MIN TYP MAX UNITS
GENERAL CHARACTERISTICS
Input Voltage VIN_LDO
IN_LDO cannot exceed SYS voltage
(Note 5) 1.8 5.5 V
LDO Shutdown Current IIN_LDO
Current measured into IN_LDO, LDO
output disabled (Note 6) 0.1 1 μA
LDO Quiescent Supply
Current (Note 6) IIN_LDO
Current measured
into IN_LDO,
ILDO = 0mA
LDO output enabled
and in regulation,
VIN_LDO = 2.05V,
VLDO = 1.85V
1.7 5.15
μA
LDO output enabled
and in dropout, VIN_
LDO = 1.8V, VLDO
target is 1.85V
2.3
Maximum Output
Current IOUT 150 mA
Current Limit VLDO externally forced to 1.3V 165 255 375 mA
OUTPUT VOLTAGE RANGE
Output Voltage Range Programmable with TV_LDO[6:0] in
12.5mV steps 1.3500 2.9375 V
Output DAC Bits 7 bits
Output DAC LSB Size 12.5 mV
STATIC CHARACTERISTICS
Initial Output Voltage
Accuracy ILDO = 75mA, TA = +25°C -2.5 +2.5 %
Output Voltage
Accuracy
VLDO programmed from 1.35V to 2.9375V,
VIN_LDO = 1.8V to 5.5V, LDO not in drop-
out, ILDO = 0mA to 150mA, TA = -5°C to
+85°C
-3 +3 %
Output Noise
f = 10Hz to
100kHz, IOUT =
15mA, VSYS =
3.7V, VIN_LDO =
2.05V, VLDO =
1.85V
Main bias circuits
are in normal-power
mode (SBIA_LPM
= 0)
550
μVRMS
Main bias circuits are
in low-power mode
(SBIA_LPM = 1)
800
Electrical Characteristics—LDO
www.maximintegrated.com Maxim Integrated
│
20
MAX77650/MAX77651 Ultra-Low Power PMIC with 3-Output SIMO
and Power Path Charger for Small Li+
(VSYS = 3.7V, VIN_LDO = 2.05V, VLDO = 1.85V, CLDO = 10μF, limits are 100% production tested at TA = +25°C, limits over the operating
temperature range (TA = -40°C to +85°C) are guaranteed by design and characterization, unless otherwise noted.)
Note 5: Dropout is the condition where the input voltage is in its valid input range but the output cannot be properly regulated
because the input voltage is not sufficiently higher than the output voltage. The dropout voltage is the difference between
the input voltage and the output voltage when the regulator is in dropout. The dropout on-resistance is the resistance of the
power MOSFET between the input and the output when the regulator is in dropout. Generally speaking, applications should
avoid dropout by having sufficient input voltage. A dropout detection interrupt is available (DOD_R; see the Programmer’s
Guide for more information). For example, applications with the output voltage target of 1.85V and the maximum load cur-
rent is 80mA (ILDO_MAX), has a dropout voltage of 96mV (VLDO_DO = ILDO_MAX x RDSON_LDO = 80mA x 1.2Ω =
96mV). To avoid dropout, the input voltage should be 1.95V (VIN_LDO = VLDO + VLDO_DO).
Note 6: Guaranteed by design and characterization but not directly production tested. Production test coverage is provided by the
shutdown supply current and quiescent supply current specification in the Electrical Characteristics—Top Level table.
Note 7: Guaranteed by design and characterization but not directly production tested. The ability to disconnect the active discharge
resistance is functionally checked in a production test.
PARAMETER SYMBOL CONDITIONS MIN TYP MAX UNITS
TIMING CHARACTERISTICS
Enable Delay TA = +25°C 0.6 1.25 ms
Soft-Start Slew Rate dV/dtSS
VLDO from 10% to 90% of final value.
TA = +25°C 0.5 1.25 2.50 mV/μs
POWER STAGE CHARACTERISTICS
Dropout Voltage VLDO_DO
VSYS = 3.7V, 1.85V programmed output
voltage (TV_LDO[6:0] = 0x20), VIN_LDO =
1.8V, ILDO = 150mA (Note 5)
90 180 mV
Active-Discharge
Impedance RAD_LDO
Regulator disabled, active discharge
enabled (ADE_LDO = 1) 50 100 200 Ω
Disabled Output
Leakage Current
Regulator disabled,
active discharge
disabled (ADE_
LDO = 0), VSYS =
VIN_LDO = 5.5V,
VLDO = 5.5V and
0V
TA = +25°C (Note 7) +0.1 +1.0
μA
TA = +85°C +1.0
Dropout On-Resistance RDSON
VSYS = 3.7V,
1.85V programmed
output voltage
(TV_LDO[6:0] =
0x20), VIN_LDO =
1.8V, ILDO = IMAX,
(Note 5)
TA = +25°C 0.6 0.9
Ω
TA = +85°C 1.2
Electrical Characteristics—LDO (continued)
www.maximintegrated.com Maxim Integrated
│
21
MAX77650/MAX77651 Ultra-Low Power PMIC with 3-Output SIMO
and Power Path Charger for Small Li+
(VSYS = 3.7V, limits are 100% production tested at TA = +25°C, limits over the operating temperature range (TA = -40°C to +85°C) are
guaranteed by design and characterization, unless otherwise noted.)
PARAMETER SYMBOL CONDITIONS MIN TYP MAX UNITS
GENERAL CHARACTERISTICS
Current Sink Quiescent
Current IQ
Change in supply current at SYS when one
channel is enabled and delivering 12.8mA,
VLEDx = 0.2V
6 12 µA
Current Sink Leakage
All current sink
drivers combined,
outputs disabled,
VLEDx = 5.5V
TA = +25ºC +0.1 +1.0
µA
TA = +85ºC +1.0
3.2mA CURRENT SINK RANGE (LED_FSx[1:0] = 0b01, VLEDx = 0.2V)
Minimum Sink Current BRT_LEDx[4:0] = 0b00000 0.1 mA
Maximum Sink Current BRT_LEDx[4:0] = 0b11111 3.2 mA
Current Sink DAC Bits 5 bits
Current Sink DAC LSB 0.1 mA
Current Sink Accuracy TA = +25ºC 3.10 3.20 3.25 mA
TA = -40ºC to +85ºC 3.03 3.20 3.36
Dropout Voltage VDO BRT_LEDx[4:0] = 0b11111, ILEDx = 2.9mA 35 70 mV
6.4mA CURRENT SINK RANGE (LED_FSx[1:0] = 0b10, VLEDx = 0.2V)
Minimum Sink Current BRT_LEDx[4:0] = 0b00000 0.2 mA
Maximum Sink Current BRT_LEDx[4:0] = 0b11111 6.4 mA
Current Sink DAC Bits 5 bits
Current Sink DAC LSB 0.2 mA
Current Sink Accuracy TA = +25ºC 6.30 6.40 6.50 mA
TA = -40ºC to +85ºC 6.06 6.40 6.72
Dropout Voltage VDO
LED_FSx[1:0] = 0b11, BRT_LEDx[4:0] =
0b11111, ILEDx = 5.75mA 35 70 mV
12.8mA CURRENT SINK RANGE (LED_FSx[1:0] = 0b11, VLEDx = 0.2V)
Minimum Sink Current BRT_LEDx[4:0] = 0b00000 0.4 mA
Maximum Sink Current BRT_LEDx[4:0] = 0b11111 12.8 mA
Current Sink DAC Bits 5 bits
Current Sink DAC LSB 0.4 mA
Current Sink Accuracy TA = +25ºC 12.6 12.8 13.0 mA
TA = -40ºC to +85ºC 12.16 12.80 13.44
Dropout Voltage VDO BRT_LEDx[4:0] = 0b11111, ILEDx = 11.5mA 35 70 mV
TIMING CHARACTERISTICS
Root Clock Frequency 25.6 32.0 38.4 Hz
Electrical Characteristics—Current Sinks
www.maximintegrated.com Maxim Integrated
│
22
MAX77650/MAX77651 Ultra-Low Power PMIC with 3-Output SIMO
and Power Path Charger for Small Li+
(VSYS = 3.7V, limits are 100% production tested at TA = +25°C, limits over the operating temperature range (TA = -40°C to +85°C) are
guaranteed by design and characterization, unless otherwise noted.)
(VSYS = 3.7V, VIO = 1.8V, limits are 100% production tested at TA = +25°C, limits over the operating temperature range (TA = -40°C to
+85°C) are guaranteed by design and characterization, unless otherwise noted.)
PARAMETER SYMBOL CONDITIONS MIN TYP MAX UNITS
TIMING CHARACTERISTICS/BLINK PERIOD SETTINGS
Minimum Blink Period 0.5 s
16 clocks
Maximum Blink Period 8 s
256 clocks
Blink Period LSB 0.5 s
16 clocks
TIMING CHARACTERISTICS/BLINK DUTY CYCLE
Minimum Blink Duty Cycle D_LEDx[3:0] = 0b0000 6.25 %
Maximum Blink Duty Cycle D_LEDx[3:0] = 0b1111 100 %
Blink Duty Cycle LSB 6.25 %
PARAMETER SYMBOL CONDITIONS MIN TYP MAX UNITS
POWER SUPPLY
VIO Voltage Range VIO 1.7 1.8 3.6 V
VIO Bias Current
VIO = 3.6V, VSDA = VSCL = 0V or 3.6V,
TA = +25°C -1 0 +1 μA
VIO = 1.7V, VSDA = VSCL= 0V or 1.7V -1 0 +1
SDA AND SCL I/O STAGE
SCL, SDA Input High
Voltage VIH VIO = 1.7V to 3.6V 0.7 x
VIO
V
SCL, SDA Input Low
Voltage VIL VIO = 1.7V to 3.6V 0.3 x
VIO
V
SCL, SDA Input
Hysteresis VHYS
0.05 x
VIO
V
SCL, SDA Input
Leakage Current IIVIO = 3.6V, VSCL = VSDA = 0V and 3.6V -10 +10 μA
SDA Output Low
Voltage VOL Sinking 20mA 0.4 V
SCL, SDA Pin
Capacitance CI10 pF
Output Fall Time from
VIH to VIL (Note 2) tOF 120 ns
Electrical Characteristics—Current Sinks (continued)
Electrical Characteristics—I2C Serial Interface
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23
MAX77650/MAX77651 Ultra-Low Power PMIC with 3-Output SIMO
and Power Path Charger for Small Li+
(VSYS = 3.7V, VIO = 1.8V, limits are 100% production tested at TA = +25°C, limits over the operating temperature range (TA = -40°C to
+85°C) are guaranteed by design and characterization, unless otherwise noted.)
PARAMETER SYMBOL CONDITIONS MIN TYP MAX UNITS
I2C-COMPATIBLE INTERFACE TIMING (STANDARD, FAST AND FAST MODE PLUS) (Note 8)
Clock Frequency fSCL 0 1000 kHz
Hold Time (REPEATED)
START Condition tHD;STA 0.26 μs
SCL Low Period tLOW 0.5 μs
SCL High Period tHIGH 0.26 μs
Setup Time REPEATED
START Condition tSU_STA 0.26 μs
Data Hold Time tHD_DAT 0μs
Data Setup Time tSU_DAT 50 ns
Setup Time for STOP
Condition tSU_STO 0.26 μs
Bus Free Time between
STOP and START
Condition
tBUF 0.5 μs
Pulse Width of Sup-
pressed Spikes tSP
Maximum pulse width of spikes that must
be suppressed by the input filter 50 ns
I2C-COMPATIBLE INTERFACE TIMING (HIGH-SPEED MODE, CB = 100pF) (Note 8)
Clock Frequency fSCL 3.4 MHz
Setup Time REPEATED
START Condition tSU_STA 160 ns
Hold Time (REPEATED)
START Condition tHD_STA 160 ns
SCL Low Period tLOW 160 ns
SCL High Period tHIGH 60 ns
Data Setup Time tSU_DAT 10 ns
Data Hold Time tHD_DAT 0 70 ns
SCL Rise Time trCL TA = +25°C 10 40 ns
Rise Time of SCL
Signal after REPEATED
START Condition and
after Acknowledge Bit
trCL1 TA = +25°C 10 80 ns
SCL Fall Time tfCL TA = +25°C 10 40 ns
SDA Rise Time trDA TA = +25°C 10 80 ns
SDA Fall Time tfDA TA = +25°C 10 80 ns
Setup Time for STOP
Condition tSU_STO 160 ns
Bus Capacitance CB100 pF
Pulse Width of Sup-
pressed Spikes tSP
Maximum pulse width of spikes that must
be suppressed by the input filter 10 ns
Electrical Characteristics—I2C (continued)
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MAX77650/MAX77651 Ultra-Low Power PMIC with 3-Output SIMO
and Power Path Charger for Small Li+
(VSYS = 3.7V, VIO = 1.8V, limits are 100% production tested at TA = +25°C, limits over the operating temperature range (TA = -40°C to
+85°C) are guaranteed by design and characterization, unless otherwise noted.)
Note 8: Design guidance only. Not production tested.
PARAMETER SYMBOL CONDITIONS MIN TYP MAX UNITS
I2C-COMPATIBLE INTERFACE TIMING (HIGH-SPEED MODE, CB = 400pF) (Note 8)
Clock Frequency fSCL 1.7 MHz
Setup Time REPEATED
START Condition tSU_STA 160 ns
Hold Time (REPEATED)
START Condition tHD_STA 160 ns
SCL Low Period tLOW 320 ns
SCL High Period tHIGH 120 ns
Data Setup Time tSU_DAT 10 ns
Data Hold Time tHD_DAT 0 150 ns
SCL Rise Time tRCL TA = +25°C 20 80 ns
Rise Time of SCL
Signal after REPEATED
START Condition and
after Acknowledge Bit
tRCL1 TA = +25°C 20 80 ns
SCL Fall Time tFCL TA = +25°C 20 80 ns
SDA Rise Time tRDA TA = +25°C 20 160 ns
SDA Fall Time tFDA TA = +25°C 20 160 ns
Setup Time for STOP
Condition tSU_STO 160 ns
Bus Capacitance CB400 pF
Pulse Width of
Suppressed Spikes tSP
Maximum pulse width of spikes that must
be suppressed by the input filter 10 ns
Electrical Characteristics—I2C (continued)
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│
25
MAX77650/MAX77651 Ultra-Low Power PMIC with 3-Output SIMO
and Power Path Charger for Small Li+
smmmwu SUPPLY CURRE sHumown suPPLv cuRRE SHUYDOWN SUPPLY cuRRE
vs. aAnERv VOLYAGE vs. EAYTERVVOLTAGE vs. uIrEvaoLTAGE
me We Lansmmsmw um sma unsmgnmmn mo swo LED’SARED‘SABLED
wmms or; .samm : m MAWB‘AS 0N (swim H mm was 0N (Samara: u
ow PawER MODE ‘sam w : u NORMAL PawER mug (55mm : m i
1.7 can
1;. : we
1.: we
v we
, v we ,
/
I’Wfl
DhlESCENY sumv cums uulEscEm suPPchuR
vs EAT‘IERV VOLYAGE vsJEMPERAWRE
MAW m on @5ij : w wmms ON @5ij : w
owvmn MODE Lsmfim : n mmwm MODE (35mm : u
w w
‘ ‘ saan Sam $532 momma:
ssan Sam saaz mo ENA my 555“ 355‘ SBBQENAMD
aBu Sam saazENABLEni 555“ 355‘ imam)
5350 saw ammo, SEBHWBLED
sBanENAaLED
/
_/
5551 EFFICIENCY vs. DUYPUT cuRREm 555’ W‘D REM-“'0”
Wm; = 3.3V, PER PEAK cuRREm LIMIT] (Vsm : 3 3V. PER PEAKCURRENY LIMIY)
w 358:0 w 5mm ””355 ‘D V ‘3” mm. mom
um = SuF
mm 700nm
mm = 500m
Ham
mm = 1mm
(Typical Application Circuit, VCHGIN = 0V, VSYS = VIN_SBB = 3.7V, VBATT = 3.7V, VIO = 1.8V, TA = +25°C, unless otherwise noted.)
0
1
2
3
4
5
6
2.5 3.5 4.5 5.5
I
B AT T
(
µ
A)
VB AT T (V)
LDO, SIMO, LED'S ARE DISABLED
MAIN-BIAS OFF (SBIA_EN = 0)
TA = +85°C
TA = +25°C
TA= -40°C
SHUTDOWN SUPPLY CURRENT
vs. BATTERY VOLTAGE
toc01
0
1
2
3
4
5
6
2.5 3.5 4.5 5.5
I
B AT T
(µA)
V
B AT T
(V)
LDO, SIMO, LED'S ARE DISABLED
MAIN-BIAS ON (SBIA_EN = 1)
LOW-POWER MODE (SBIA_LPM = 1)
T
A
= +85°C
T
A
= +25°C
T
A
= -40°C
SHUTDOWN SUPPLY CURRENT
vs. BATTERY VOLTAGE
toc02
0
10
20
30
40
50
60
2.5 3.5 4.5 5.5
I
B AT T
(µA)
V
B AT T
(V)
LDO, SIMO, LED'S ARE DISABLED
MAIN-BIAS ON (SBIA_EN = 1)
NORMAL-POWER MODE (SBIA_LPM = 0)
T
A
= +85°C
T
A
= +25°C
T
A
= -40°C
SHUTDOWN SUPPLY CURRENT
vs. BATTERY VOLTAGE
toc03
0
1
2
3
4
5
6
7
8
9
10
2.5 3.5 4.5 5.5
I
B AT T
(µA)
V
B AT T
(V)
MAIN-BIAS ON (SBIA_EN = 1)
LOW-POWER MODE (SBIA_LPM = 1)
SBB0 ENABLED
SBB0, SBB1 ENABLED
SBB0, SBB1, SBB2 ENABLED
SBB0, SBB1, SBB2, LDO ENABLED
QUIESCENT SUPPLY CURRENT
vs. BATTERY VOLTAGE
toc04
0
1
2
3
4
5
6
7
8
9
10
-40 -15 10 35 60 85
I
B AT T
(
µ
A)
TEMPERATURE (°C)
SBB0 ENABLED
SBB0, SBB1 ENABLED
SBB0, SBB1, SBB2 ENABLED
SBB0, SBB1, SBB2, LDO ENABLED
MAIN-BIAS ON (SBIA_EN = 1)
LOW-POWER MODE (SBIA_LPM = 1)
QUIESCENT SUPPLY CURRENT
vs. TEMPERATURE
toc05
70
72
74
76
78
80
82
84
86
88
0.1 110 100 1000
EFFICIENCY (%)
OUTPUT CURRENT (mA)
DRV_SBB = 0, V
IN_SBB
= 3.7V
CSBB2_EFFECTIVE = 3µF
IP_SBB2 = 1000mA
IP_SBB2 = 866mA
IP_SBB2 = 700mA
IP_SBB2 = 500mA
SBB2 EFFICIENCY vs. OUTPUT CURRENT
(VSBB2 = 3.3V, PER PEAK CURRENT LIMIT)
toc06
3.20
3.25
3.30
3.35
3.40
3.45
3.50
0.1 110 100 1000
OUTPUT VOLTAGE (V)
OUTPUT CURRENT (mA)
DRV_SBB = 0, V
IN_SBB
= 3.7V
CSBB2_EFFECTIVE = 3µF
IP_SBB2 = 1000mA
IP_SBB2 = 866mA
IP_SBB2 = 700mA
IP_SBB2 = 500mA
SBB2 LOAD REGULATION
(VSBB2 = 3.3V, PER PEAK CURRENT LIMIT)
toc07
Typical Operating Characteristics
www.maximintegrated.com Maxim Integrated
│
26
MAX77650/MAX77651 Ultra-Low Power PMIC with 3-Output SIMO
and Power Path Charger for Small Li+
3:anch m
53 EFFICIENCY vs, OUYPUY cuRREm
sa EFFICIENCY v5 03mm! CURRENT saan LOAD REGuLATION
(vsm = 2.nsv, PER PEAK cuRRENr Lmun Nam = 2.nsv, PER PEAK CURRENT Lmun ww=12vaR PEAK cuRREm LIMIT]
DR w 53:, mass : a VW “a: 3 w Muss : a VW :33: 3 w
m :5» 8mm may 5UP 7 P 8550 : “mm mm: : aw
mag mm
7 man :100mR
\{sBBu mm
,saau : mm
5531 LOAD REGuLAYIDN “Sgiififl'gh‘g‘g,
(V3331 = 1.2m PER PEAK CURRENT LIMm (visa, : a :v, FER nmvs smsucm)
wisaaw w, SARIGN
Cm , [Uni :EuF
\\
\\
mam : mm
JP sam mm" m,
,sam 71mm
mam : 5mm
CHGIM SUPPLY CURREN
saaz LOAD REGULATION CHGIN voLrAGE
.zv‘ PER DRIVE SYRENGYH) (use SUSPENDED]
we ,, mswe
ms:
DRV:SBB : 3
(Typical Application Circuit, VCHGIN = 0V, VSYS = VIN_SBB = 3.7V, VBATT = 3.7V, VIO = 1.8V, L = 2.2µF (TOKO DFE201210S-2R2M,
127mΩ, 2.0mm x 1.2mm x 1.0mm), TA = +25°C, unless otherwise noted.)
70
72
74
76
78
80
82
84
86
88
0.1 110 100 1000
EFFICIENCY (%)
OUTPUT CURRENT (mA)
DRV_SBB = 0, V
IN_SBB
= 3.7V
CSBB0_EFFECTIVE = 5µF
IP_SBB0 = 1000mA
IP_SBB0 = 866mA
IP_SBB0 = 700mA
IP_SBB0 = 500mA
SBB0 EFFICIENCY vs. OUTPUT CURRENT
(VSBB0 = 2.05V, PER PEAK CURRENT LIMIT)
toc08
1.95
2.00
2.05
2.10
2.15
2.20
2.25
0.1 110 100 1000
OUTPUT VOLTAGE (V)
OUTPUT CURRENT (mA)
DRV_SBB = 0, V
IN_SBB
= 3.7V
CSBB0_EFFECTIVE = 5µF
IP_SBB0 = 1000mA
IP_SBB0 = 866mA
IP_SBB0 = 700mA
IP_SBB0 = 500mA
SBB0 LOAD REGULATION
(VSBB0 = 2.05V, PER PEAK CURRENT LIMIT)
toc09
70
72
74
76
78
80
82
84
86
88
0.1 110 100 1000
EFFICIENCY (%)
OUTPUT CURRENT (mA)
DRV_SBB = 0, V
IN_SBB
= 3.7V
CSBB1_EFFECTIVE =8µF
IP_SBB1 = 1000mA
IP_SBB1 = 866mA
IP_SBB1 = 700mA
IP_SBB1 = 500mA
SBB1 EFFICIENCY vs. OUTPUT CURRENT
(VSBB1 = 1.2V, PER PEAK CURRENT LIMIT)
toc10
1.18
1.19
1.20
1.21
1.22
1.23
1.24
0.1 110 100 1000
OUTPUT VOLTAGE (V)
OUTPUT CURRENT (mA)
DRV_SBB = 0, V
IN_SBB
= 3.7V
CSBB1_EFFECTIVE =8µF
IP_SBB1 = 1000mA
IP_SBB1 = 866mA
IP_SBB1 = 700mA
IP_SBB1 = 500mA
SBB1 LOAD REGULATION
(VSBB1 = 1.2V, PER PEAK CURRENT LIMIT)
toc11
70
72
74
76
78
80
82
84
86
88
0.1 110 100 1000
EFFICIENCY (%)
OUTPUT CURRENT (mA)
IP_SBB2 = 3, V
IN_SBB
= 3.7V
CSBB2_EFFECTIVE = 3µF
DRV_SBB = 0
DRV_SBB = 1
DRV_SBB = 2
DRV_SBB = 3
SBB2 EFFICIENCY
vs. OUTPUT CURRENT
(VSBB2 = 3.3V, PER DRIVE STRENGTH)
toc12
3.26
3.28
3.30
3.32
3.34
3.36
3.38
0.1 110 100 1000
OUTPUT VOLTAGE (V)
OUTPUT CURRENT (mA)
IP_SBB2 = 3, V
IN_SBB
= 3.7V
CSBB2_EFFECTIVE = 3µF
DRV_SBB = 0
DRV_SBB = 1
DRV_SBB = 2
DRV_SBB = 3
SBB2 LOAD REGULATION
(VSBB2 = 3.3V, PER DRIVE STRENGTH)
toc13
0
10
20
30
40
50
60
70
80
90
100
3.5 4.0 4.5 5.0 5.5 6.0
ICHGIN (µA)
VCHGIN (V)
VCHGIN RISING
CHGIN SUPPLY CURRENT vs.
CHGIN VOLTAGE
(USB SUSPENDED)
toc14
Typical Operating Characteristics (continued)
Maxim Integrated
│
27
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MAX77650/MAX77651 Ultra-Low Power PMIC with 3-Output SIMO
and Power Path Charger for Small Li+
as mclzncv vs. oumn CURREN
saan LOAD REGULATION
ZV‘ PER DR'VE STRENG'H‘ CHARGE PROFILE, lnmAh HYTERV
(vmu : z.osv, FER DRWE smsucm) Wsw -
: 3v \ 2: Wk
asvcnamzrflflmA VFBVLNWIO
, nnvrsaa : 0
Drum : ‘
nnvrsaa : 2
W535 : 3
Wm
aaz LOAD REGULAYION
CHARGE PROFILE 11nmAh sanRv (V5.52 : 3 3V, PER INPUT VOLYAGE)
unv sa 0 w saaz:3
w 55
w 5:3
VW 53 '
v , v WW,
saaz LOAD REGULAT‘DN
Wm] : 1.5V‘ PER INPUY vow/35)
saaz EFFIC‘ENCV vs OUYPUY cuRREMr
{vim — 1.5V‘ PER mPur VOLTAGE)
Dwvrsaaw ”552:: W: W
95332 mm HF 7mm W 5 W
WWW
szzn 37v
33v
25v
Dmsas mam : 3
E NE: 5“;
"77 vM
w
2.03
2.04
2.05
2.06
2.07
2.08
2.09
0.1 110 100 1000
OUTPUT VOLTAGE (V)
OUTPUT CURRENT (mA)
IP_SBB0 = 3, V
IN_SBB
= 3.7V
CSBB0_EFFECTIVE = 5µF
DRV_SBB = 0
DRV_SBB = 1
DRV_SBB = 2
DRV_SBB = 3
SBB0 LOAD REGULATION
(VSBB0 = 2.05V, PER DRIVE STRENGTH)
toc15
70
72
74
76
78
80
82
84
86
88
0.1 110 100 1000
EFFICIENCY (%)
OUTPUT CURRENT (mA)
IP_SBB1 = 3, V
IN_SBB
= 3.7V
CSBB1_EFFECTIVE =8µF
DRV_SBB = 0
DRV_SBB = 1
DRV_SBB = 2
DRV_SBB = 3
SBB1 EFFICIENCY vs. OUTPUT CURRENT
(VSBB1 = 1.2V, PER DRIVE STRENGTH)
toc16
0.000
0.006
0.012
0.018
0.024
0.030
0.036
0.042
0.048
0.054
0.060
0.0
0.5
1.0
1.5
2.0
2.5
3.0
3.5
4.0
4.5
5.0
0.0 1.0 2.0 3.0
IB ATT (A)
VB ATT (V)
TIME (hr)
V
PQ
= 3V, I
PQ
= 10%
IFAST-CHARGE = 30mA, VFAST-CHARGE = 4.2V
VB A TT (V)
IB A TT (A)
CHARGE PROFILE, 40mAh BATTERY
toc17
BATTERY LOADED
DURING THE 'DONE'
STATE TO SHOW
THE RESTART
BEHAVIOR
0.000
0.015
0.030
0.045
0.060
0.075
0.090
0.105
0.120
0.135
0.150
0.0
0.5
1.0
1.5
2.0
2.5
3.0
3.5
4.0
4.5
5.0
0.0 1.0 2.0 3.0
IB ATT (A)
VB ATT (V)
TIME (hr)
V
PQ
= 3V, I
PQ
= 10%
IFAST-CHG = 75mA, VFAST-CHG = 4.2V
VBATT (V)
IBATT (A)
CHARGE PROFILE, 110mAh BATTERY
toc18
BATTERY LOADED
DURING THE 'DONE'
STATE TO SHOW
THE RESTART
BEHAVIOR
70
72
74
76
78
80
82
84
86
88
0.1 110 100 1000
EFFICIENCY (%)
OUTPUT CURRENT (mA)
VIN_SBB =5.5V
VIN_SBB =5.0V
VIN_SBB = 4.2V
VIN_SBB =3.7V
VIN_SBB =3.3V
VIN_SBB =3.0V
VIN_SBB =2.8V
DRV_SBB = 0, IP_SBB2 = 3
CSBB2_EFFECTIVE = 5µF
SBB2 EFFICIENCY vs. OUTPUT CURRENT
(VSBB2 = 2.5V, PER INPUT VOLTAGE)
toc20
3.26
3.28
3.30
3.32
3.34
3.36
3.38
0.1 110 100 1000
OUTPUT VOLTAGE (V)
OUTPUT CURRENT (mA)
DRV_SBB=0, IP_SBB2 = 3
CSBB2_EFFECTIVE = 3µF
VIN_SBB = 5.5V
VIN_SBB =5.0V
VIN_SBB = 4.2V
VIN_SBB =3.7V
VIN_SBB =3.3V
VIN_SBB =2.8V
SBB2 LOAD REGULATION
(VSBB2 = 3.3V, PER INPUT VOLTAGE)
toc19
2.46
2.48
2.50
2.52
2.54
2.56
2.58
0.1 110 100 1000
OUTPUT VOLTAGE (V)
OUTPUT CURRENT (mA)
DRV_SBB = 0, IP_SBB2 = 3
CSBB2_EFFECTIVE = 5µF
VIN_SBB = 5.5V
VIN_SBB = 5.0V
VIN_SBB = 4.2V
VIN_SBB = 3.7V
VIN_SBB =3.3V
VIN_SBB =2.8V
SBB2 LOAD REGULATION
(VSBB2 = 2.5V, PER INPUT VOLTAGE)
toc21
Typical Operating Characteristics (continued)
(Typical Application Circuit, VCHGIN = 0V, VSYS = VIN_SBB = 3.7V, VBATT = 3.7V, VIO = 1.8V, L = 2.2µF (TOKO DFE201210S-2R2M,
127mΩ, 2.0mm x 1.2mm x 1.0mm), TA = +25°C, unless otherwise noted.)
Maxim Integrated
│
28
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MAX77650/MAX77651 Ultra-Low Power PMIC with 3-Output SIMO
and Power Path Charger for Small Li+
Sam EFFICIENCV vs. oumn CURRENY
(V5350 nsv‘ PER INPUT VOLTAGE)
mamas» w 5350::
a 7» “75a;
as FICIENCY v: ouwur cuRREu
mm. .asv,PER|~Pu1voL1AsE)
mamas» w 5350::
saga a 7» “75a;
m sag : 33f
w sa 2v,
w
w sag : 2 av’
Vw sag 0v,
Vw sag : 5 av
BED FICIENCsz DUTPUYCURREN
(vim—1 sv, FER INPUT vonmsp
DRVVSBB : 0 mm : a
a mum : BuF
W4 sag N
W sag 3v
W4 sag 2v
W4 sag IN
a sag e
W sag: 5 W
W sag: 5 5v
sum LOAD assuunou
(vim : 2 05v, PER INHH VOLYAGE]
DRVVSBB : 0 mm :3
asasa a EchE 5uF
Sam LOAD REGULAYION
(vim :1asv,PER|~Pu1 VOLYAGE]
DRVVSBB : u w Sam :3
5 F
Vm sag zev
saao LOAD REGULATION
wsm :1.5V‘PERINPUY VOLTAGE)
Dmsas n w saga : 3
(Typical Application Circuit, VCHGIN = 0V, VSYS = VIN_SBB = 3.7V, VBATT = 3.7V, VIO = 1.8V, L = 2.2µF (TOKO DFE201210S-2R2M,
127mΩ, 2.0mm x 1.2mm x 1.0mm), TA = +25°C, unless otherwise noted.)
70
72
74
76
78
80
82
84
86
88
0.1 110 100 1000
EFFICIENCY (%)
OUTPUT CURRENT (mA)
DRV_SBB = 0, IP_SBB0 = 3
CSBB0_EFFECTIVE = 5µF
VIN_SBB =5.5V
VIN_SBB =5.0V
VIN_SBB =4.2V
VIN_SBB = 3.7V
VIN_SBB =3.3V
VIN_SBB =3.0V
VIN_SBB =2.8V
SBB0 EFFICIENCY vs. OUTPUT CURRENT
(VSBB0 = 2.05V, PER INPUT VOLTAGE)
toc22
70
72
74
76
78
80
82
84
86
88
0.1 110 100 1000
EFFICIENCY (%)
OUTPUT CURRENT (mA)
DRV_SBB = 0, IP_SBB0 = 3
CSBB0_EFFECTIVE = 5µF
VIN_SBB = 5.5V
VIN_SBB = 5.0V
VIN_SBB = 4.2V
VIN_SBB =3.7V
VIN_SBB = 3.3V
VIN_SBB = 3.0V
VIN_SBB =2.8V
SBB0 EFFICIENCY vs. OUTPUT CURRENT
(VSBB0= 1.85V, PER INPUT VOLTAGE)
toc24
2.03
2.04
2.05
2.06
2.07
2.08
2.09
0.1 110 100 1000
OUTPUT VOLTAGE (V)
OUTPUT CURRENT (mA)
DRV_SBB = 0, IP_SBB0 = 3
CSBB0_EFFECTIVE = 5µF
VIN_SBB = 5.5V
VIN_SBB = 5.0V
VIN_SBB = 4.2V
VIN_SBB = 3.7V
VIN_SBB = 3.3V
VIN_SBB =3.0V
VIN_SBB =2.8V
SBB0 LOAD REGULATION
(VSBB0 = 2.05V, PER INPUT VOLTAGE)
toc23
1.83
1.84
1.85
1.86
1.87
1.88
1.89
0.1 110 100 1000
OUTPUT VOLTAGE (V)
OUTPUT CURRENT (mA)
DRV_SBB = 0, IP_SBB0 = 3
CSBB0_EFFECTIVE = 5µF
VIN_SBB = 5.5V
VIN_SBB = 5.0V
VIN_SBB = 4.2V
VIN_SBB = 3.7V
VIN_SBB = 3.3V
VIN_SBB = 2.8V
SBB0 LOAD REGULATION
(VSBB0 = 1.85V, PER INPUT VOLTAGE)
toc25
70
72
74
76
78
80
82
84
86
88
0.1 110 100 1000
EFFICIENCY (%)
OUTPUT CURRENT (mA)
DRV_SBB = 0, IP_SBB0 = 3
CSBB0_EFFECTIVE = 6µF
VIN_SBB = 5.5V
VIN_SBB = 5.0V
VIN_SBB = 3.0V
VIN_SBB = 2.8V
SBB0 EFFICIENCY vs. OUTPUT CURRENT
(VSBB0 = 1.5V, PER INPUT VOLTAGE)
toc26
VIN_SBB = 4.2V
VIN_SBB = 3.3V
VIN_SBB = 3.7V
1.48
1.49
1.50
1.51
1.52
1.53
1.54
0.1 110 100 1000
OUTPUT VOLTAGE (V)
OUTPUT CURRENT (mA)
DRV_SBB = 0, IP_SBB0 = 3
CSBB0_EFFECTIVE = 6µF
VIN_SBB = 5.5V
VIN_SBB = 5.0V
VIN_SBB = 4.2V
VIN_SBB = 3.7V
VIN_SBB = 3.3V
VIN_SBB = 2.8V
SBB0 LOAD REGULATION
(VSBB0 = 1.5V, PER INPUT VOLTAGE)
toc27
Typical Operating Characteristics (continued)
Maxim Integrated
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MAX77650/MAX77651 Ultra-Low Power PMIC with 3-Output SIMO
and Power Path Charger for Small Li+
5551 EFFICIENCY vs ouwur CHRRENT
(V5551 :1 1v, FER INPUT VOLTAGE)
7v anus “551:3
SEE1EFFICIENCV vs oumn CURRENT
WSW: .ov‘ PERINPUY vomes)
szsa:37v DRVVSBB 0 \Prsaa‘d
w 555
W 555 : 5 av
W 555 5v
551 FICIENCsz OUYPUYCURREN
{vim .5v‘ PER INPUT VOLTAGE)
muss Ham :3
rm; : 9MP
sz55=37v
’me
sz55 2v
sz55 av
ws55:23v
sz55 av
\NSEE
551 LOAD REGULAYION
(Vina 2v,PERI~PuTvoL1AGE)
vwssmsv
mm nvr
W4555 2v
sz55r N
'szas 3V'
W455;
551 LOAD REGULATION
.nv‘ PER INPm vow/35)
7 w 555 7
W 555 : a 2v
551 LOAD REGULAYION
(vim . 5v, FER INPUT VOLTAGE)
nnvrsaa : a 555m : a Vw SE5: 5 5v
vwsas:5uv
’“szas 2v
sz55 N
sz55=33v
Vms55=23v
(Typical Application Circuit, VCHGIN = 0V, VSYS = VIN_SBB = 3.7V, VBATT = 3.7V, VIO = 1.8V, L = 2.2µF (TOKO DFE201210S-2R2M,
127mΩ, 2.0mm x 1.2mm x 1.0mm), TA = +25°C, unless otherwise noted.)
70
72
74
76
78
80
82
84
86
88
0.1 110 100 1000
EFFICIENCY (%)
OUTPUT CURRENT (mA)
VIN_SBB = 5.5V
VIN_SBB = 5.0V
VIN_SBB = 2.8V
VIN_SBB = 3.0V
DRV_SBB = 0, IP_SBB1 = 3
CSBB1_EFFECTIVE = 8µF
VIN_SBB = 4.2V
VIN_SBB = 3.3V
SBB1 EFFICIENCY vs. OUTPUT CURRENT
(VSBB1 = 1.2V, PER INPUT VOLTAGE)
toc28
VIN_SBB = 3.7V
70
72
74
76
78
80
82
84
86
88
0.1 110 100 1000
EFFICIENCY (%)
OUTPUT CURRENT (mA)
DRV_SBB = 0, IP_SBB1 = 3
CSBB1_EFFECTIVE = 8µF
VIN_SBB =5.5V
VIN_SBB =5.0V
VIN_SBB =4.2V
VIN_SBB = 3.7V
VIN_SBB =3.3V
VIN_SBB =3.0V
VIN_SBB =2.8V
SBB1 EFFICIENCY vs. OUTPUT CURRENT
(VSBB1 = 1.0V, PER INPUT VOLTAGE)
toc30
70
72
74
76
78
80
82
84
86
88
0.1 110 100 1000
EFFICIENCY (%)
OUTPUT CURRENT (mA)
VIN_SBB =5.5V
VIN_SBB =5.0V
VIN_SBB =2.8V
VIN_SBB =3.0V
VIN_SBB =4.2V
VIN_SBB =3.3V
DRV_SBB = 0, IP_SBB1 = 3
CSBB1_EFFECTIVE = 9µF
VIN_SBB = 3.7V
SBB1 EFFICIENCY vs. OUTPUT CURRENT
(VSBB1 = 0.8V, PER INPUT VOLTAGE)
toc32
1.18
1.19
1.20
1.21
1.22
1.23
1.24
0.1 110 100 1000
OUTPUT VOLTAGE (V)
OUTPUT CURRENT (mA)
DRV_SBB = 0, IP_SBB1 = 3
CSBB1_EFFECTIVE = 8µF
VIN_SBB =5.5V
VIN_SBB =5.0V
VIN_SBB =4.2V
VIN_SBB =3.7V
VIN_SBB =3.3V
VIN_SBB =2.8V
SBB1 LOAD REGULATION
(VSBB1 = 1.2V, PER INPUT VOLTAGE)
toc29
0.98
0.99
1.00
1.01
1.02
1.03
1.04
0.1 110 100 1000
OUTPUT VOLTAGE (V)
OUTPUT CURRENT (mA)
VIN_SBB =2.8V
VIN_SBB =3.3V
VIN_SBB =3.7V
VIN_SBB =4.2V
VIN_SBB =5.0V
DRV_SBB = 0, IP_SBB1 = 3
CSBB1_EFFECTIVE = 8µF
VIN_SBB = 5.5V
SBB1 LOAD REGULATION
(VSBB1 = 1.0V, PER INPUT VOLTAGE)
toc31
0.78
0.79
0.80
0.81
0.82
0.83
0.84
0.1 110 100 1000
OUTPUT VOLTAGE (V)
OUTPUT CURRENT (mA)
DRV_SBB = 0, IP_SBB1 = 3
CSBB1_EFFECTIVE = 9µF
VIN_SBB = 5.5V
VIN_SBB =5.0V
VIN_SBB =4.2V
VIN_SBB =3.7V
VIN_SBB =3.3V
VIN_SBB =2.8V
SBB1 LOAD REGULATION
(VSBB1 = 0.8V, PER INPUT VOLTAGE)
toc33
Typical Operating Characteristics (continued)
Maxim Integrated
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MAX77650/MAX77651 Ultra-Low Power PMIC with 3-Output SIMO
and Power Path Charger for Small Li+
slulc SWIYDHING WAVEFDRMs
LIGHr unLIzAnDN LDmA PER CHANNEL
SIMD LINE rRANsIEm
EN
LPVSEEL:5fl0mAV :szc :5»;
LPVSEEHZTMMKV awe Sui
\\\L\\\\M\\
\\\V\\\N\Nw
\\N\\\\\~
SEEL LDAn rRANsIENr
WMWMWLWNMMLWMLW
WWW“
wwwwwmmwm
,__...___;
_J L___._'
saaz LOAD rRANsIEN1
“WSWM‘ILLLVLL‘LLLL\\\‘L\LL\‘L\\LL
my\\\\\\\\\\\\\\\\\\\\N
\\\~\\\\m~w-\5\~w~\\~\~\\\~
m
Sam LDAn rRANsIENr
\LLLWLLNLLLWNWMWMLLLWWLW
WMWMNNNN‘sWNN‘
M“ WWW
r——L L
.—J m
SIMD SWITCHING WAVEFURMS
NEnIuN unLIzAnuN ZSmAFER CHANNEL
SIMU SWIYCHING WAvErcRNs
HEAW unLIzAnoN 75mA PER CHANNEL
fl
LLL
JJLLULLLLL.
WW\
W
dJLLLgLALLU LUL
AX)“
“NYE:
JLLLL LLLL LLLL LLLLLLLL
L\\\\\\\L\\
\‘WN
WNNN‘
(Typical Application Circuit, VCHGIN = 0V, VSYS = VIN_SBB = 3.7V, VBATT = 3.7V, VIO = 1.8V, L = 1.5µF, TA = +25°C, unless otherwise noted.)
1V/div
50mV/div
toc34
10µs/div
VOUTN
VINSIDE
VBACKUP
SIMO LINE TRANSIENT
VSBB2
VSBB1
VSBB0
VIN_SBB
50mV/div
50mV/div
3.2V
4.2V
IP_SBB0 = 707mA, VSBB0 = 2.05V, CSBB0_EFF = 5µF
IP_SBB1 = 500mA, VSBB1 = 1.2V, CSBB1_EFF = 8µF
IP_SBB2 = 866mA, VSBB2 = 3.3V, CSBB2_EFF = 6µF
L=2.2µHISBB0 = ISBB1 = ISBB2 = 10mA
100mA/div
50mV/div
toc36
40µs/div
SBB1 LOAD TRANSIENT
VSBB2
VSBB1
VSBB0
ISBB1
50mV/div
50mV/div
3.3V
2.05V
1.2V
10mA
100mA
ISBB0 = 10mA
ISBB2 = 10mA
IP_SBBx SET T O 500mA
LOW-POWER MODE
CSBB0_EFF = 5µF
CSBB1_EFF = 8µF
CSBB2_EFF = 6µF
50mV/div
500mA/div
toc38
4µs/div
SIMO SWITCHING WAVEFORMS
LIGHT UTILIZATION 10mA PER CHANNEL
VSBB2
VSBB1
VSBB0
IL
50mV/div
50mV/div
IP_SBB2 = 500mA, VSBB2= 3.3V, CSBB2_EFF = 3µF
IP_SBB1 = 500mA, VSBB1= 1.2V, CSBB1_EFF = 8µF
IP_SBB2 = 500mA, VSBB0= 2.05V, CSB B0_EFF = 5µF
100mA/div
50mV/div
toc35
40µs/div
SBB2 LOAD TRANSIENT
VSBB2
VSBB1
VSBB0
ISBB2
50mV/div
50mV/div
3.3V
2.05V
1.2V
10mA
80mA
ISBB0 = 10mA
ISBB1 = 10mA
IP_SBBx SET T O 500mA
LOW-POWER MODE
CSBB0_EFF = 5µF
CSBB1_EFF = 8µF
CSBB2_EFF = 6µF
100mA/div
50mV/div
toc37
40µs/div
SBB0 LOAD TRANSIENT
VSBB2
VSBB1
VSBB0
ISBB0
50mV/div
50mV/div
3.3V
2.05V
1.2V
10mA
100mA
ISBB1 = 10mA
ISBB2 = 10mA
IP_SBBx SET T O 500mA
LOW-POWER MODE
CSBB0_EFF = 5µF
CSBB1_EFF = 8µF
CSBB2_EFF = 6µF
50mV/div
500mA/div
toc39
4µs/div
SIMO SWITCHING WAVEFORMS
MEDIUM UTILIZATION 25mA PER CHANNEL
VSBB2
VSBB1
VSBB0
IL
50mV/div
50mV/div
IP_SBB2 = 866mA, VSBB2= 3.3V, CSBB2_EFF = 3µF
IP_SBB1 = 500mA, VSBB1 = 1.2V, CSBB1_EFF =8µF
IP_SBB2 = 707mA, VSBB0= 2.05V, CSBB0_EFF = 5µF 50mV/div
500mA/div
toc40
4µs/div
SIMO SWITCHING WAVEFORMS
HEAVY UTILIZATION 75mA PER CHANNEL
VSBB2
VSBB1
VSBB0
IL
50mV/div
50mV/div
IP_SBB2 = 1000mA, VSBB2= 3.3V, CSBB2_EFF =3µF
IP_SBB1 = 1000mA, VSBB1= 1.2V, CSBB1_EFF = 8µF
IP_SBB2 = 1000mA, VSBB0= 2.05V, CSBB0_EFF =5µF
Typical Operating Characteristics (continued)
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MAX77650/MAX77651 Ultra-Low Power PMIC with 3-Output SIMO
and Power Path Charger for Small Li+
LDD LOAD REGULAYION LEO LINE REGHWION an LINE TRANSIENY
mm mm a ,
VLm YARGHVOUAGE : ‘ 55v
3 n W we
b 2 W4 we
5 5 vw
r 2 ...._.__.
LDDLOADYRANSIENT LDO LOAD mmslzm
1AM ., fix»...
fl ‘ fl ,
no POWER-SUPPLY
REJECTIDN mmo
LDO LDADTRANSIENY
WV...
1
._1 .
(Typical Application Circuit, VCHGIN = 0V, VSYS = VIN_SBB = 3.7V, VBATT = 3.7V, VIO = 1.8V, L = 1.5µF, TA = +25°C, unless otherwise noted.)
toc46
100µs/div
LDO LOAD TRANSIENT
V
LDO
I
LDO
50mV/div
50mV/div
150mA
1.85V
2mA
1.75
1.77
1.79
1.81
1.83
1.85
1.87
1.89
1.91
1.93
1.95
3.0 4.0 5.0 6.0
VLDO (V)
VIN_LDO (V)
NO LOAD
TA= +25°C
TA= +85°C
TA= -20°C
LDO LINE REGULATION
toc42
toc44
100µs/div
LDO LOAD TRANSIENT
V
LDO
I
LDO
50mV/div
50mV/div
80mA
1.85V
5mA
1.75
1.77
1.79
1.81
1.83
1.85
1.87
1.89
1.91
1.93
1.95
0.000 0.025 0.050 0.075 0.100 0.125 0.150
V
LDO
(V)
ILDO (A)
VLDO TARGET VOLTAGE = 1.85V
5.5 VIN_LDO
3.0 VIN_LDO
4.2 VIN_LDO
LDO LOAD REGULATION
toc41
0
10
20
30
40
50
60
0.1 110 100 1000
PSRR (dB)
INPUT FREQUENCY (kHz)
LDO POWER-SUPPLY
REJECTION RATIO
toc47
V
IN_LDO
AVERAGE
=
2.05V
V
LDO
AVERAG E =
1.85V
LOAD = 15mA
toc43
200µs/div
LDO LINE TRANSIENT
V
IN_LDO
V
LDO
200mV/div
1mV/div
2.05V
2.35V
toc45
100µs/div
LDO LOAD TRANSIENT
V
LDO
I
LDO
50mV/div
50mV/div
135mA
1.85V
15mA
Typical Operating Characteristics (continued)
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MAX77650/MAX77651 Ultra-Low Power PMIC with 3-Output SIMO
and Power Path Charger for Small Li+
HGIN suPPchuRREN CHGIN SUPPLVCURREN
vs CHGIN VDLYAGE vs. CHGIN voLrAGE
‘5 (MA VEHC R R‘SWG
mm R‘swe 5”
BA" EIAS cuRREm ‘41. an" svs to an" IMPEDANCE
CHARGER D‘SABLED
mm = 5v VA
1. : cza'c
R:4wc
svs LOAD YRANSIENY
CHARGE PROFILE, mm». BATTERY CHARGE PROFILE, I1llmAh BATIERV CAUSING aArrERv suPPLEmEm
v : m. v W = m. ,
um‘mz = 3mm VW Emmi = a 2v w m‘ m m, m = ; 2v —
WM “M .. ___;_-_.
« ,
‘sm (A
\m w
am
BAH
(Typical Application Circuit, VCHGIN = 0V, VSYS = VIN_SBB = 3.7V, VBATT = 3.7V, VIO = 1.8V, L = 1.5µF, TA = +25°C, unless otherwise noted.)
0.0
0.2
0.4
0.6
0.8
1.0
1.2
1.4
1.6
1.8
3.5 4.0 4.5 5.0 5.5 6.0 6.5 7.0 7.5 8.0 8.5
ICHGIN (mA)
VCHGIN (V)
VBATT = 2.7V
VBATT = 3.6V
VBATT = 4.4V
I
SYS
= 0mA
VCHGIN RISING
CHGIN SUPPLY CURRENT
vs. CHGIN VOLTAGE
toc48
0
1
2
3
4
5
6
7
8
9
10
2.5 3.0 3.5 4.0 4.5
IB ATT (µA)
VB ATT (V)
CHARGER DISABLED
VCHGIN = 5V
TA= +25°C
TA= -40°C
TA= +85°C
BATT BIAS CURRENT vs. BATT
toc50
0.000
0.005
0.010
0.015
0.020
0.025
0.030
0.035
0.040
0.045
0.050
2.5
2.7
2.9
3.1
3.3
3.5
3.7
3.9
4.1
4.3
4.5
0.0 0.5 1.0 1.5 2.0 2.5
I
BATT
(A)
VBATT (V)
TIME (hr)
V
PQ
= 3V, I
PQ
= 10%
IFAST-CHARGE = 30mA, VFAST-CHARGE = 4.2V
VBATT (V)
IBATT (A)
CHARGE PROFILE, 40mAh BATTERY
toc52
0
10
20
30
40
50
60
70
80
90
100
3.5 4.0 4.5 5.0 5.5 6.0
ICHGIN (µA)
VCHGIN (V)
V
CHGIN
RISING
USB SUSPENDED
CHGIN SUPPLY CURRENT
vs. CHGIN VOLTAGE
toc49
0.08
0.09
0.10
0.11
0.12
0.13
0.14
0.15
0.16
2.5 3.0 3.5 4.0 4.5 5.0
RDS-ON (Ω)
VB ATT (V)
SYS TO BATT IMPEDANCE
toc51
IB A TT = 10mA
IB A TT = 100mA
IB A TT = 300mA
0.000
0.015
0.030
0.045
0.060
0.075
0.090
0.105
0.120
0.135
0.150
2.5
2.7
2.9
3.1
3.3
3.5
3.7
3.9
4.1
4.3
4.5
0.0 0.5 1.0 1.5 2.0 2.5
I
BATT
(A)
VBATT (V)
TIME (hr)
V
PQ
= 3V, I
PQ
= 10%
IFAST-CHG = 90mA, VFAST-CHG = 4.2V
VBATT (V)
IBATT (A)
CHARGE PROFILE, 110mAh BATTERY
toc53
BATTERY
LOADED DURING
THE "DONE"
STATE TO SHOW
THE RESTART
BEHAVIOR
toc54
1ms/div
SYS LOAD TRANSIENT
CAUSING BATTERY SUPPLEMENT
VSYS
IBATT
1V/div
95mA
0mA 30mA
30mA CHARGING
125mA
0mA
30mA DISCHARGING
0mA
4.5V
3.7V
100mA/div
100mA/div
100mA/div
ISYS
ICHGIN
ICHGIN_LIM = 95mA
ICHGIN = 30mA
VSYS_REG = 4.5V
Typical Operating Characteristics (continued)
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MAX77650/MAX77651 Ultra-Low Power PMIC with 3-Output SIMO
and Power Path Charger for Small Li+
POWER HP
No LOAD
POWER UP
mmA LOAD PER CHANNEL
OWER now
No LOAD
mat
"ll wMIurn-NMmlllm‘mmnw-wmmml
PDWER DOWN
mmA LDAD PER CHANNEL
(Typical Application Circuit, VCHGIN = 0V, VSYS = VIN_SBB = 3.7V, VBATT = 3.7V, VIO = 1.8V, L = 1.5µF, TA = +25°C, unless otherwise noted.)
toc57
2ms/div
POWER UP
10mA LOAD PER CHANNEL
1V/div
50mA/div
1V/div
1V/div
1V/div
2V/div
VnRST
IBATT
VSBB2
VSBB0
VLDO
VSBB1
toc55
2ms/div
POWER UP
NO LOAD
1V/div
50mA/div
1V/div
1V/div
1V/div
2V/div
VnRST
IBATT
VSBB2
VSBB0
VLDO
VSBB1
toc58
4ms/div
POWER DOWN
10mA LOAD PER CHANNEL
1V/div
50mA/div
1V/div
1V/div
1V/div
2V/div
VnRST
IBATT
VSBB2
VSBB0
VLDO
VSBB1
toc56
4ms/div
POWER DOWN
NO LOAD
1V/div
50mA/div
1V/div
1V/div
1V/div
2V/div
VnRST
IBATT
VSBB2
VSBB0
VLDO
VSBB1
Typical Operating Characteristics (continued)
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MAX77650/MAX77651 Ultra-Low Power PMIC with 3-Output SIMO
and Power Path Charger for Small Li+
PIN NAME FUNCTION TYPE
TOP LEVEL
A2 nEN Active-Low Enable Input. nEN supports push-button or slide-switch configurations. An external
pullup resistor (10kΩ to 100kΩ) to SYS is required. digital input
C2 nIRQ Active-Low, Open-Drain Interrupt Output. Connect a 100kΩ pullup resistor between nIRQ and a
voltage equal to or less than VSYS.digital output
B2 nRST Active-Low, Open-Drain Reset Output. Connect a 100kΩ pullup resistor between nRST and a
voltage equal to or less than VSYS.digital output
A1 PWR_HLD
Active-High Power Hold Input. Assert PWR_HLD to keep the on/off controller in its on through
on/off controller state. If PWR_HLD is not needed, connect it to SYS and use the SFT_RST bits
to power down the device.
digital input
B1 GPIO General-Purpose Input/Output. The GPIO I/O stage is internally biased with VIO. digital I/O
C4 VIO I2C Interface and GPIO Driver Power power input
B4 SCL I2C Clock digital input
A3 SDA I2C Data digital I/O
C3 GND Quiet Ground. Connect GND to PGND, LGND, and the low-impedance ground plane of the
PCB. ground
Pin Configuration
TOP VIEW
(BUMP SIDE DOWN)
A
B
C
D
WLP
(2.75mm x 2.15mm)
E
PWR_
HLD
1
+
nEN
2
SDA
3
LED2 LED1 LED0
GPIO nRST LGND SCL LDO IN_LDO
AMUX nIRQ GND V
IO
BST SBB0
V
L
THM TBIAS LXA LXB SBB1
CHGIN SYS BATT IN_SBB PGND SBB2
4 5 6
Bump Description
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MAX77650/MAX77651 Ultra-Low Power PMIC with 3-Output SIMO
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PIN NAME FUNCTION TYPE
CHARGER
E1 CHGIN Charger Input. Connect to a DC charging source. Bypass to GND with a 4.7μF ceramic capacitor. power input
E2 SYS System Power Output. SYS provides power to the system resources as well as the control logic
of the device. Connect SYS to IN_SBB and bypass to GND with a 22μF ceramic capacitor. power output
E3 BATT Li+ Battery Connection. Connect to positive battery terminal. Bypass to GND with a 4.7μF
ceramic capacitor. power I/O
D1 VLInternal Charger 3V Logic Supply Powered from CHGIN. Bypass to GND with a 1μF ceramic
capacitor. Do not load VL externally. power
D3 TBIAS Thermistor Bias Supply. Connect a resistor equal to the NTC's room temperature resistance
between TBIAS and THM. Do not load TBIAS with any other external circuitry. analog
D2 THM Thermistor Monitor. Thermally couple an NTC to the battery and connect between THM and GND. analog input
C1 AMUX Analog Multiplexer Output. Connect to system ADC to perform conversions on charger power
signals. analog output
LDO
B5 LDO Linear Regulator Output power output
B6 IN_LDO Linear Regulator Input power input
RGB LED DRIVER
A6 LED0 Current Sink Port 0. LED0 is typically connected to the cathode of an LED and is capable of
sinking up to 12.5mA. Connect to ground if unused. power
A5 LED1 Current Sink Port 1. LED1 is typically connected to the cathode of an LED and is capable of
sinking up to 12.5mA. Connect to ground if unused. power
A4 LED2 Current Sink Port 2. LED2 is typically connected to the cathode of an LED and is capable of
sinking up to 12.5mA. Connect to ground if unused. power
B3 LGND Current Sink Ground. Connect LGND to GND, PGND, and the low-impedance ground plane of
the PCB. ground
SIMO BUCK BOOST
E4 IN_SBB SIMO Power Input. Connect IN_SBB to SYS and bypass to PGND with a 10uF ceramic
capacitor as close as possible to the IN_SBB pin. power input
C6 SBB0 SIMO Buck-Boost Output 0. SBB0 is the power output for channel 0 of the SIMO buck-boost.
Bypass SBB0 to PGND with a 10μF ceramic capacitor. power output
D6 SBB1 SIMO Buck-Boost Output 1. SBB1 is the power output for channel 1 of the SIMO buck-boost.
Bypass SBB1 to PGND with a 10μF ceramic capacitor. power output
E6 SBB2 SIMO Buck-Boost Output 2. SBB2 is the power output for channel 2 of the SIMO buck-boost.
Bypass SBB2 to PGND with a 10μF ceramic capacitor. power output
C5 BST SIMO Power Input for the High-Side Output NMOS Drivers. Connect a 3300pF ceramic capaci-
tor between BST and LXB. power input
D4 LXA
Switching Node A. LXA is driven between PGND and IN_SBB when any SIMO channel is en-
abled. LXA is driven to PGND when all SIMO channels are disabled. Connect a 1.5μH inductor
between LXA and LXB.
power I/O
D5 LXB
Switching Node B. LXB is driven between PGND and SBBx when SBBx is enabled. LXB is
driven to PGND when all SIMO channels are disabled. Connect a 1.5μH inductor between LXA
and LXB.
power I/O
E5 PGND Power ground for the SIMO low-side FETs. Connect PGND to GND, LGND, and the low-imped-
ance ground plane of the PCB. ground
Bump Description (continued)
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MAX77650/MAX77651 Ultra-Low Power PMIC with 3-Output SIMO
and Power Path Charger for Small Li+
Detailed Description
The MAX77650/MAX77651 provide a highly-integrated
battery charging and power management solution for low-
power applications. The linear charger provides a wide
range of charge current and charger termination voltage
options to charge various Li+ batteries. Temperature
monitoring and JEITA compliance settings add additional
functionality and safety to the charger. Four regulators
are integrated within this device (see Table 1). A single-
inductor, multiple output (SIMO) buck-boost regulator
efficiently provides three independently programmable
power rails. A 150mA LDO provides ripple rejection for
audio and other low-noise applications.
The system includes other features such as current sinks
for driving LED indicators and an analog multiplexer that
switches several internal voltage and current signals to
an external node for monitoring with an external ADC.
A bidirectional I2C serial interface allows for configuring
and checking the status of the device. An internal on/off
controller provides regulator sequencing and supervisory
functionality for the device.
Support Materials
Support materials are available to assist engineering
teams in designing with this device. For example, a full
description of the register bits along with software advice
is available in the Programmer’s Guide. Visit the product
page at www.maximintegrated.com/MAX77650 and/
or contact Maxim for more information on support docu-
ments.
Top-Level Interconnect Simplified Diagram
Figure 1 shows the same major blocks as the Typical
Application Circuit with an increased emphasis on the
routing between each block. This diagram is intended
to familiarize the user with the landscape of the device.
Many of the details associated with these signals are
discussed throughout the data sheet. At this stage of
the data sheet, note the addition of the main bias and
clock block that are not shown in the Typical Applications
Circuit. The main bias and clock block provides voltage,
current, and clock references for other blocks as well as
many resources for the top-level digital control.
REGULATOR
NAME
REGULATOR
TOPOLOGY
MAXIMUM IOUT
(mA) VIN RANGE (V)
MAX77650 VOUT
RANGE/
RESOLUTION
MAX77651 VOUT
RANGE/
RESOLUTION
SBB0 SIMO Up to 300* 2.7 to 5.5 0.8V to 2.375V in
25mV steps
0.8 to 2.375V in
25mV steps
SBB1 SIMO Up to 300* 2.7 to 5.5 0.8V to 1.5875V in
12.5mV steps
2.4 to 5.25V in
50mV steps
SBB2 SIMO Up to 300* 2.7 to 5.5 0.8V to 3.95V in
50mV steps
2.4 to 5.25V in
50mV steps
LDO PMOS LDO 150 1.8 to 5.5 1.35V to 2.9375V in
12.5mV steps
1.35 to 2.9375V in
12.5mV steps
Table 1. Regulator Summary
*Shared capacity with other SBBx channels. See the SIMO Available Output Current section for more information.
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MAX77650/MAX77651 Ultra-Low Power PMIC with 3-Output SIMO
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PWRJLD
was;
SYSUVLO
VSOVL
one
FOR
BOK
SVSRST
SVSRST
Figure 1. Top-Level Interconnect Simplified Diagram
nEN
SYS
nRST
RST
TOP-LEVEL
DIGITAL
CONTROL
nIRQ
PWR_HLD
VIO
FPS
GPIO
VIO
MAIN BIAS
AND CLOCK
SYS
SIMO
V
REF
V
IREF
SYSRST
IRQ_TOP
SYSRST
CHGINPOK
SYSUVLO
SYSOVLO
OTLO
POR
BOK
DO
COMM
FPS
100us
GLITCH FILTER
t
PWR_HLD_GF
100us/30ms
DEBOUNCE
TIMER
t
DBNC_nEN
DI
AMUX
SDA
I
2
CSCL
BIAS_EN
SBIA_LPM
PWR_HLD2
DBNEN
CLK
V
REF
V
IREF
CLK
AMUX
STAT_PWR_HLD
COMM
10ns/30ms
DEBOUNCE
TIMER
t
DBNC_nEN
DBEN_GPI
DBEN_nEN
IRQ_CHG
LDO
V
REF
V
IREF
SYSRST
FPS
COMM
CURRENT
SINK
V
REF
V
IREF
SYSRST
CLK
COMM
CHARGER
and
MUX
V
REF
V
IREF
SYSRST CHGINPOK
IRQ_CHG
nEN
COMM
IRQ_CHG
AMUX
MAX77650/MAX77651
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MAX77650/MAX77651 Ultra-Low Power PMIC with 3-Output SIMO
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Global Resources
The global resources encompass a set of circuits that
serve the entire device and ensure safe, consistent, and
reliable operation.
Features and Benefits
●Voltage Monitors
• SYS POR (power-on-reset) comparator generates
a reset signal upon power-up
• SYS undervoltage ensures repeatable behavior when
power is applied to and removed from the device
• SYS overvoltage monitor inhibits operation with
overvoltage power sources to ensure reliability in
faulty environments
●Thermal Monitors
• 165°C junction temperature shutdown
●Manual Reset
• 8s or 16s period
●Wakeup Events
• Charger insertion (with 120ms debounce)
• nEN input assertion
●Interrupt Handler
• Interrupt output (nIRQ)
• All interrupts are maskable
●Push-button/Slide-Switch Onkey (nEN)
• Configurable push-button/slide-switch functionality
• 100μs or 30ms debounce timer interfaces directly
with mechanical switches
●On/Off Controller
• Startup/shut-down sequencing
• Programable sequencing delay
●PWR_HLD, GPIO, RST Digital I/Os
Voltage Monitors
The device monitors the system voltage (VSYS) to ensure
proper operation using three comparators (POR, UVLO,
and OVLO). These comparators include hysteresis to
prevent their outputs from toggling between states during
noisy system transitions.
SYS POR Comparator
The SYS POR comparator monitors VSYS and generates
a power-on reset signal (POR). When VSYS is below
VPOR, the device is held in reset (SYSRST = 1). When
VSYS rises above VPOR, internal signals and on-chip
memory stabilize and the device is released from reset
(SYSRST = 0).
SYS Undervoltage Lockout Comparator
The SYS undervoltage lockout (UVLO) comparator moni-
tors VSYS and generates a SYSUVLO signal when the
VSYS falls below UVLO threshold. The SYSUVLO signal
is provided to the top-level digital controller. See Figure 4
and Table 2 for additional information regarding the UVLO
comparator:
●When the device is in the STANDBY state, the UVLO
comparator is disabled.
●When transitioning out of the STANDBY state, the
UVLO comparator is enabled allowing the device to
check for sufficient input voltage. If the device has
sufficient input voltage, it can transition to the on
state; if there is insufficient input voltage, the device
transitions back to the STANDBY state.
SYS Overvoltage Lockout Comparator
The device is rated for 5.5V maximum operating voltage
(VSYS) with an absolute maximum input voltage of 6.0V.
An overvoltage lockout monitor increases the robustness
of the device by inhibiting operation when the supply volt-
age is greater than VSYSOVLO. See Figure 4 and Table 2
for additional information regarding the OVLO comparator:
●When the device is in the STANDBY state, the OVLO
comparator is disabled.
nEN Enable Input
nEN is an active-low internally debounced digital input
that typically comes from the system’s on key. The
debounce time is programmable with DBEN_nEN. The
primary purpose of this input is to generate a wake-up
signal for the PMIC that turns on the regulators. Maskable
rising/falling interrupts are available for nEN (nEN_R and
nEN_F) for alternate functionality. nEN requires an exter-
nal pullup resistor (10kΩ to 100kΩ) to SYS.
The nEN input can be configured to work either with a
push-button (nEN_MODE = 0) or a slide-switch (nEN_
MODE = 1). See Figure 2 for more information. In both
push-button mode and slide-switch mode, the on/off con-
troller looks for a falling edge on the nEN input to initiate
a power-up sequence.
nEN Manual Reset
nEN works as a manual reset input when the on/off con-
troller is in the on via on/off controller state. The manual
reset function is useful for forcing a power-down in case
the communication with the processor fails. When nEN is
configured for a push-button mode and the input is assert-
ed (nEN = low) for an extended period (tMRST), the on/off
controller initiates a power-down sequence and goes to
standby mode. When nEN is configured for a slide-switch
mode and the input is deasserted (nEN = high) for an
extended period (tMRST), the on/off controller initiates a
power-down sequence and goes to standby mode.
A dedicated internal oscillator is used to create the 30ms
(tDBNC_nEN) and 16s (tMRST) timers for nEN. Whenever
the device is actively counting either of these times, the
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MAX77650/MAX77651 Ultra-Low Power PMIC with 3-Output SIMO
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supply current increases by the oscillator's supply current
(65μA when the battery voltage is at 3.7V). As soon as
the event driving the timer goes away or is fulfilled, the
oscillator automatically turns off and its supply current
goes away.
nEN Dual-functionality:
Push-Button vs. Slide-Switch
The nEN digital input can be configured to work with
a push-button switch or a slide-switch. The timing dia-
gram below shows nEN's dual functionality for power-on
sequencing and manual reset. The default configuration
of the device is push-button mode (nEN_MODE = 0) and
no additional programming is necessary. Applications
that use a slide-switch on-key configuration must set
nEN_MODE = 1 within tMRST.
Interrupts (nIRQ)
nIRQ is an active-low, open-drain output that is typically
routed to the host processor’s interrupt input to signal
an important change in the device’s status. Refer to the
Programmer’s Guide for a comprehensive list of all inter-
rupt bits and status registers.
A pullup resistor to a voltage less than or equal to VSYS
is required for this node. nIRQ is the logical NOR of all
unmasked interrupt bits in the register map
All interrupts are masked by default. Masked interrupt bits
do not cause the nIRQ pin to change. Unmask the inter-
rupt bits to allow nIRQ to assert.
Reset Output (nRST)
nRST is an open-drain, active-low output that is typically
used to hold the processor in a reset state when the device
is powered down. During a power-up sequence, the nRST
deasserts after the last regulator in the power-up chain
is enabled (tRSTODD). During a power-down sequence,
the nRST output asserts before any regulator is powered
down (tRSTOAD). See Figure 5 for nRST timing.
A pullup resistor to a voltage less than or equal to VSYS
is required for this node.
Power Hold Input (PWR_HLD)
PWR_HLD is an active-high digital input. PWR_HLD has a
100μs glitch filter (tPWR_HLD_GF). As shown in Figure 1, the
output of this glitch filter is logically ORed with the wakeup
signal coming from the charger to create a signal called
PWR_HLD2 that drives the top-level digital control.
Figure 2. nEN Usage Timing Diagram
V
SYS
STATE
NOT DRAWN TO SCALE
STANDBY POWER-ON SEQUENCE ON POWER-DOWN SEQUENCE
nEN
SYS
nEN
SYS
t
DBNC_nEN
t
DBNC_nEN
t
DBNC_nEN
t
MRST
t
DBNC_nEN
t
DBNC_nEN
t
MRST
BATTERY
INSERTION
PUSH-BUTTON MODE
SLIDE-SWITCH MODE
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MAX77650/MAX77651 Ultra-Low Power PMIC with 3-Output SIMO
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●When there is no valid charge voltage at CHGIN
(CHGINPOK = 0):
• After the power-up sequence, the system proces-
sor must assert PWR_HLD within the PWR_HLD
wait time (tPWR_HLD_WAIT) to hold the power
supply in the on state. If the PWR_HLD input is
not asserted within the tPWR_HLD_WAIT period, a
power-down sequence is initiated.
• While in the on state, the system processor must
assert PWR_HLD as long as power is required. If
the system processor wants to turn off, it can either
pull PWR_HLD low or it can write the SFT_RST
bits to execute the SFT_CRST or SFT_OFF func-
tions to execute the power-down sequence.
●If there is a valid charge voltage at CHGIN
(CHGINPOK = 1):
• The charger sends a wakeup signal to the on/off
controller which is also logically ORed with PWR_
HLD to assert PWR_HLD2. PWR_HLD2 being
asserted satisfies the on/off controller such that the
PWR_HLD signal is a don't care.
See the Figure 7, Top-Level On/Off Controller section,
and Table 2 for additional information regarding PWR_
HLD. If the power hold function is not used, connect
PWR_HLD to SYS and then use the SFT_RST bits to
power the device down.
General-Purpose Input Output (GPIO)
A general-purpose input/output (GPIO) is provided to
increase system flexibility. See Figure 3 for the GPIO
Block Diagram.
Clear DIR to configure GPIO as a general-purpose output
(GPO). The GPO can either be in push-pull mode (DRV =
1) or open-drain mode (DRV = 0).
●The push-pull output mode is ideal for applications that
need fast (~2ns) edges and low power consumption.
●The open-drain mode requires an external pullup
resistor (typically 10kΩ–100kΩ). Connect the external
pullup resistor to a bias voltage that is less than or
equal to VIO.
• The open-drain mode can be used to communicate
to different logic domains. For example, to send a
signal from the GPO on a 1.8V logic domain (VIO =
1.8V) to a device on a 1.2V logic domain, connect
the external pullup resistor to 1.2V.
• The open-drain mode can be used to connect sever-
al open-drain (or open-collector) devices together on
the same bus to create wired logic (wired AND logic
is positive-true; wired OR logic is negative-true).
The general-purpose input (GPI) functions are still avail-
able while the pin is configured as a GPO. In other words,
the DI (input status) bit still functions properly and does
not collide with the state of the DIR bit.
Set DIR to disable the output drivers associated with the
GPO and have the device function as a GPI. The GPI
features a 30ms debounce timer (tDBNC_GPI) that can be
enabled or disabled with DBEN_GPI.
●Enable the debounce timer (DBEN_GPI = 1) if the
GPI is connected to a device that can bounce or
chatter (like a mechanical switch).
●If the GPI is connected to a circuit with clean logic
transitions and no risk of bounce, disable the
debounce timer (DBEN_GPI = 0) to eliminate unnec-
essary logic delays. With no debounce timer, the GPI
input logic propagates to nIRQ in 10ns.
A dedicated internal oscillator is used to create the 30ms
(tDBNC_GPI) debounce timer. Whenever the device is
actively counting this time, the supply current increases
by the oscillator's supply current (65μA when the battery
voltage is at 3.7V). As soon as the event driving the timer
goes away or is fulfilled, the oscillator automatically turns
off and its supply current goes away.
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MAX77650/MAX77651 Ultra-Low Power PMIC with 3-Output SIMO
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Maskable rising and falling interrupts (GPI_R and GPI_F)
are available to signal a change in the GPI’s status.
●To interrupt on a rising edge only: unmask the rising
edge interrupt and mask the falling edge interrupt (GPI_
RM = 0, GPI_FM = 1).
●To interrupt on a falling edge only: unmask the falling
edge interrupt and mask the rising edge interrupt
(GPI_RM = 1, GPI_FM = 0).
●To interrupt on either rising or falling edge: unmask
both rising and falling edge interrupts (GPI_RM = 0,
GPI_FM = 0). Consult the Register Map for more
details.
Figure 3. GPIO Block Diagram
LOGIC
COMM
GPIO
VIO
D
R
Q 1
READ
D
R
Q 1
READ
(GPI_R)
(GPI_F)
GPI_R
GPI_RM
GPI_FM
GPI_F
nIRQ
IRQ
CNFG_GPIO
SYS
DRV
DIR
DO
DI
GPI_R
GPI_F
GPI_RM
GPI_FM
DRV
DIR
DO
GND
DBNC_EN
30ms DEBOUNCE
(tDBNC_GPI)
0
1
DI
DBNC_EN
OTHER nIRQ ASSERTION
SOURCES NOT SHOWN
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MAX77650/MAX77651 Ultra-Low Power PMIC with 3-Output SIMO
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On/Off Controller
The on/off controller monitors multiple power-up (wakeup)
and power-down (shutdown) conditions to enable or dis-
able resources that are necessary for the system and its
processor to move between its operating modes.
Many systems have one power management controller
and one processor and rely on the on/off controller to be
the master controller. In this case, the on/off controller
receives the wakeup events and enables some or all of
the regulators in order to power up a processor. That pro-
cessor then manages the system. To conceptualize this
master operation see Figure 4 and Table 2. A typical path
through the on/off controller in master mode is:
●Start in the no power state.
●Apply a battery to the system and transition through
path 1 and 2 to the standby state.
●Press the system's on key (nEN = low) and transition
through path 3A and 4 to the "PWR_HLD?" state.
●The processor boots up and drives PWR_HLD high,
which drives the transition through path 4C to the on
through the on/off controller state.
●The device performs its desired functions in the on
through on/off controller state. When it is ready to turn
off, the processor drives PWR_HLD low that drives the
transition through path 5B and 8 to the standby state.
Some systems have several power management blocks,
a main processor, and subprocessors. These systems
can use this device as a subpower management block for
a peripheral portion of circuitry as long as there is an I2C
port available from a higher level processor. To concep-
tualize this slave operation, see Figure 4 and Table 2. A
typical path through the on/off controller in slave mode is:
●Start in the no power state.
●Apply a battery to the system and transition through
path 1 and 2 to the standby state.
●When the higher level processor wants to turn on this
device's resources, it enables the main bias circuits
through I2C (SBIA_EN = 1) to transition along path
2A to the on through software state.
●The higher level processor can now control this
device's resources with I2C commands (i.e., turn on/
off regulators).
●When the higher level processor is ready to turn
this device off, it turns off everything through I2C
and then disables the main bias circuits through I2C
(SBIA_EN = 0) to transition along path 2B to the
standby state.
Note that in this slave style of operation, the SFT_RST
bits should not be used to turn the device off. The SFT_
RST bits establish directives to the on/off controller itself
that does not make sense in slave mode. In slave mode,
since the I2C commands enable the device's resources,
they should also disable them.
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MAX77650/MAX77651 Ultra-Low Power PMIC with 3-Output SIMO
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Figure 4. Top-Level On/Off Controller
X
TRANSITION NAME.
SEE TABLE 2
STATE
ACTION
DECISION
3A
POWER UP
SEQUENCE
(FIGURE 5)
4B
STANDBY
3
DISABLE MAIN BIAS
POWER DOWN
SEQUENCE
(FIGURE 5)
4
4C
4A
ENABLE MAIN BIAS
6
IMMEDIATE
SHUTDOWN
(FIGURE 5)
9
ENABLE MAIN BIAS
86
NO POWER
VCHGIN=0, VSYS<VPOR 0
POWER-ON
RESET (POR)
1
2
2A
5A
7
3
3
ON VIA
SOFTWARE
2B
ON VIA ON/OFF
CONTROLLER 5B
PWR_HLD?
11
12
2B
10
10
ANY
STATE
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MAX77650/MAX77651 Ultra-Low Power PMIC with 3-Output SIMO
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TRANSITION/STATE CONDITION
0System voltage is below the POR threshold (VSYS < VPOR).
1System voltage is above the POR threshold (VSYS > VPOR).
2Internal signals and on-chip memory stabilize and the device is released from reset.
STANDBY
The device is waiting for a wake-up signal or an I2C command to enable the main bias circuits.
* This is the lowest current state of the device (IQ ~0.3μA).
* Main bias circuits are off, POR comparator is on.
* I2C is on when VIO is valid.
* Peripheral functions (LDO, SIMO, LEDs, AMUX) do not operate in this state because the main bias circuits
are off. To utilize a function enter the on through software or on through on/off controller states.
2A Main bias circuits enabled through I2C (SBIA_EN = 1).
2B Main bias circuits disabled through I2C (SBIA_EN = 0).
ON VIA
SOFTWARE*
The main bias circuits are enabled through software and all peripheral functions (LDO, SIMO, LEDs, AMUX)
can be manually enabled or disabled through I2C.
3
A wake-up signal has been received.
* A debounced onkey (nEN) falling edge has been detected (DBNEN = 1) or
* A charge source has been applied and a rising edge on CHGIN has been detected and debounced
(tCHGIN-DB ~120ms) or
* Internal wake-up flag has been set due to SFT_RST = 0b01 (WKUP = 1)
3A Main bias circuits are OK (BOK = 1)
4Power-up sequence complete.
4A PWR_HLD wait time has expired and PWR_HLD2 is low (t > tPWR_HLD_WAIT && PWR_HLD2 = 0).
4B PWR_HLD wait time has not expired and PWR_HLD2 is low (t < tPWR_HLD_WAIT && PWR_HLD2 = 0).
4C PWR_HLD2 = 1
ON VIA ON/OFF
CONTROLLER*
On state.
* All flexible power sequencers (FPS) are on.
* The main bias circuits are enabled.
* IQ ~5.6µA (typ) with all regulators enabled (no load) and the main bias circuits in low power mode.
5A PWR_HLD2 = 1
5B
PWR_HLD2 = 0 OR
System overtemperature lockout (TJ >TOTLO) or
Software cold reset (SFT_RST[1:0] = 0b01) or
Software power off (SFT_RST[1:0] = 0b10) or
Manual reset occurred. See the nEN Manual Reset section for more information.
6
System overtemperature lockout (TJ >TOTLO) or
System undervoltage lockout (VSYS < VSYSUVLO + VSYSUVLO_HYS) or
System overvoltage lockout (VSYS > VSYSOVLO)
7
System undervoltage lockout (VSYS < VSYSUVLO) or
System overvoltage lockout (VSYS > VSYSOVLO)
Note: The overvoltage lockout transition does not apply to the ON VIA SOFTWARE state.
8Finished with the power-down sequence.
9Finished with immediate shutdown.
10 System overtemperature lockout (TJ > TOTLO).
11 Done disabling main bias.
12 Done enabling main bias.
Table 2. On/Off Controller Transition/State
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MAX77650/MAX77651 Ultra-Low Power PMIC with 3-Output SIMO
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N
¢
END
/
BL
BL
END
AT
IF
END
Figure 5. Power-Up/Power-Down Sequence
FPS ENABLE SLOT 2
START
FROM TOP LEVEL #3A
END
TO TOP LEVEL #4
WAIT t
EN
WAIT t
EN
WAIT t
RSTODD
DE-ASSERT nRST
FPS DISABLE SLOT 2
WAIT t
DIS
WAIT t
DIS
WAIT t
RSTOAD
ASSERT nRST
SET THE APPROPRIATE BIT IN THE EVENT
RECORDER REGISTER (ERCFLAG) TO INDICATE
THE SOURCE OF THE POWER DOWN EVENT.
START FROM TOP LEVEL
#4A OR #5B
SFT_RST = 0b01
SFT_RST = 0b10
OR PWR_HLD2 = 0
SET WAKEUP
FLAG (WKUP = 1)
CLEAR WAKEUP FLAGS
WAIT 60ms
FPS ENABLE SLOT 3
WAIT t
EN
WAIT t
DIS
TEMPERATURE IS OKAY
(T
J
<T
OTLO
)
OTLO?
CLEAR WAKEUP
FLAG (WKUP = 0) TEMPERATURE IS
NOT OKAY
(T
J
>T
OTLO
)
IMMEDIATE SHUTDOWN
FPS ENABLE SLOT 1
FPS ENABLE SLOT 0
FPS DISABLE SLOT 3
FPS DISABLE SLOT 1
FPS DISABLE SLOT 0
DISABLE FPS3, FPS2, FPS1, FPS0
ASSERT nRST
END
TO TOP LEVEL #9
SET THE APPROPRIATE BIT IN THE EVENT
RECORDER REGISTER (ERCFLAG) TO INDICATE
THE SOURCE OF THE POWER DOWN EVENT.
START
FROM TOP LEVEL #7
WAIT 125ms
RESET DEVICE
(PULSE SYSRST FOR 5µs)
END
TO TOP LEVEL #8
WAIT 125ms
RESET DEVICE
(PULSE SYSRST FOR 5µs)
SFT_RST = 0b00
OR PWR_HLD2 = 1
RETURN BACK TO
THE ON STATE
POWER-UP SEQUENCE POWER-DOWN SEQUENCE
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46
MAX77650/MAX77651 Ultra-Low Power PMIC with 3-Output SIMO
and Power Path Charger for Small Li+
Flexible Power Sequencer
The flexible power sequencer (FPS) allows resources to
power up under hardware or software control. Additionally,
each resource can power up independently or among a
group of other regulators with adjustable power-up and pow-
er-down delays (sequencing). Figure 6 shows four resources
powering up under the control of flexible power sequencer.
The flexible sequencing structure consists of 1 master
sequencing timer and 4 slave resources (SBB0, SBB1,
SBB2, and LDO). When the FPS is enabled, a master
timer generates four sequencing events for device power-
up and power-down.
Figure 6. Flexible Power Sequencer Basic Timing Diagram
FPS RESOURCES
PLSFPS
t
EN
SAME FOR ALL FPS ENABLE PULSES
0 1 2 3
LDO
SBB1
SBB2
ENFPS
t
DIS
SAME FOR ALL FPS DISABLE PULSES
t
DIS
= 2x t
EN
0123
SBB0
NOT DRAWN TO SCALE
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MAX77650/MAX77651 Ultra-Low Power PMIC with 3-Output SIMO
and Power Path Charger for Small Li+
Figure 7. Startup Timing Diagram Due to nEN
VSYS
BATTERY
INSERTION
tPOR~100µs
POR
NO POWER STANDBY
nEN
tDBNC_nEN
POWER-UP SEQUENCE
REGULATORS
nRST
PWR_HLD
tPWR_HLD_WAIT
ON THROUGH ON/OFF
CONTROLLER
PWR_HLD?
tEN tEN
NOTES: 1 – nEN LOGIC INPUT IS CONFIGURED TO PUSH-BUTTON MODE AND HAS AN EXTERNAL PULLUP TO SYS.
2 – nEN ASSERTION RESULTS IN A WAKE-UP EVEN AFTER A DEBOUNCE TIME (tDBNCEN).
3 – INTERNAL WAKE-UP SIGNAL CAN ALSO BE GENERATED BY CHARGER PLUG-IN EVENT.
4 – nIRQ HAS AN EXTERNAL PULLUP TO VIO WHICH IS ENABLED IN FLEXIBLE POWER SEQUENCER SLOT #1
5 – SYSTEM PROCESSOR ASSERTS PWR_HLD INPUT TO PLACE THE DEVICE IN THE ON THROUGH ON/OFF CONTROLLER STATE.
6 – AS PART OF ITS INITIALIZATION ROUTINE, SOFTWARE READS THE INTERRUPT REGISTERS (CLEAR ON READ) AND PROGRAMS THE INTERRUPT MASKS AS DESIRED.
NOT DRAWN TO SCALE
VPOR~1.9V
NOTE
5
NOTE 2
STATE
BIAS EN
(INTERNAL)
tDBNC_nEN
nIRQ
SYSTEM
SOFTWARE
STAT_EN
tRSTODD
FPS0 FPS1 FPS2
tEN
FPS3
INTERNAL WAKE-UP
SIGNAL NOTE 3
NOTE 1
NOTE 4
nEN_F
nEN_R
NOTE
6
tSBIA_EN
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MAX77650/MAX77651 Ultra-Low Power PMIC with 3-Output SIMO
and Power Path Charger for Small Li+
“4,4;
~44 ;+~H-
Figure 8. Startup Timing Diagram Due to Charge Source Insertion
VSYS
CHARGER
INSERTION
CHGIN DEBOUNCESTATE
nEN
POWER-UP SEQUENCE
REGULATORS
nRST
PWR_HLD2
tPWR_HLD_WAIT
ON THROUGH ON/OFF CONTROLLERPWR_HLD?
tEN tEN tEN
tRSTODD
VCHGIN
CHGINOK=1
VBATT
tCHGIN-DB (~120ms)
CHG_EN = 1
CHARGER ENABLED
SYSTEM VOLTAGEBATTERY VOLTAGE
PRE-QUAL FAST CHARGE (CC) TOP-OFF (CV) DONE
IPQ
VFAST-CHG
ITOPOFF
VPQ
VFAST-CHG
CHARGER
VOLTAGE
CHARGE CURRENT
0V
0V
0V
0mA
5V
INTERNAL CHARGER GENERATED
WAKE SIGNAL
NOTE 3
VPOR~2.0V
VSYSUVLO~2.9V
NOTE 5
NOTE 2
NOTE 1
NOTES: 1 – nEN LOGIC INPUT IN CONFIGURED TO PUSH-BUTTON MODE AND HAS AN
EXTERNAL PULLUP TO SYS.
2 – IF PWR_HLD IS NOT ASSERTED BY THE END OF THE tPWR_HLD_WAIT PERIOD, DEVICE
INITIATES A POWER-DOWN SEQUENCE.
3 - IF CHG_EN = 1 (@ OTP) THEN THE CHARGER ENABLED EVENT COINCIDES WITH THE WAKE
EVENT (CHARGING START ALONG WITH POWER-UP SEQUENCE).
4 – THIS INFLECTION POINT IS SYMBOLIC OF BATTERY PROTECTION FET CLOSING
5 – SOFTWARE SETS CHG_EN = 1 TO ENABLE CHARGING. IF CHG_EN = 1 AT OTP, SEE NOTE 3.
- - - - BLUE DOTTED LINES ARE USER INITIATED EVENTS
NOTE 4
IBATT
VSYS-REG
VFAST-CHG
FPS0 FPS1 FPS2 FPS3
tSBIA_EN
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MAX77650/MAX77651 Ultra-Low Power PMIC with 3-Output SIMO
and Power Path Charger for Small Li+
Debounced Inputs (nEN, GPI, CHGIN)
nEN, CHGIN, and GPIO (when operating as an input), are
debounced on both rising and falling edges to reject unde-
sired transitions. The input must be at a stable logic level
for the entire debounce period for the output to change its
logic state. Figure 9 shows an example timing diagram for
the nEN debounce.
Thermal Alarms and Protection
The device has thermal alarms to monitor if the junction
temperature rises above 80°C (TJAL1) and 100ºC (TJAL2).
Over-temperature lockout (OTLO) is entered if the junc-
tion temperature exceeds TOTLO (approximately 165°C,
typ). OTLO causes transition 10 in Figure 4 which causes
resources to immediately shutdown from the on via on/
off controller state. Resources may not enable until the
temperature falls below TOTLO by approximately 15°C.
The TJAL1_S and TJAL2_S status bits continuously
indicate the junction temperature alarm status. Maskable
interrupts are available to signal a change in either of
these bits. Refer to the Programmer’s Guide for details.
Figure 9. Debounced Inputs
nEN
DBEN
EN
t
DBUF
t
DBNCEN
BOUNCING IS
REJECTED
t
DBUF
t
DBNCEN
BOUNCING IS
REJECTED
STABLE
SIGNALS IS
ACCEPTED
STABLE
SIGNAL IS
ACCEPTED
(INTERNAL)
(INTERNAL)
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MAX77650/MAX77651 Ultra-Low Power PMIC with 3-Output SIMO
and Power Path Charger for Small Li+
now
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MON‘TCRS L" r L
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Smart Power Selector Charger
The linear Li+ charger implements power path with
Maxim's smart power selector. This allows separate input
current limit and battery charge current settings. Batteries
charge faster under the supervision of the smart power
selector because charge current is independently regu-
lated and not shared with variable system loads. See the
Smart Power Selector section for more information.
The programmable constant-current charge rate (7.5mA
to 300mA) supports a wide range of battery capacities.
The programmable input current limit (0mA to 475mA)
supports a range of charge sources, including USB. The
charger's programmable battery regulation voltage range
(3.6V–4.6V) supports a wide variety of cell chemistries.
Small battery capacities are supported; the charger accu-
rately terminates charging by detecting battery currents as
low as 0.375mA.
Additionally, the robust charger input withstands overvoltag-
es up to 28V. To enhance charger safety, an NTC thermis-
tor provides temperature monitoring in accordance with the
JEITA recommendations. See the Adjustable Thermistor
Temperature Monitors section for more information.
Features
●7.25V maximum operating input voltage with 28V
input standoff
●7.5mA to 300mA programmable fast-charge current
●Programmable termination current from 0.375mA to
45mA
●Programmable battery regulation voltage from 3.6V
to 4.6V
● < 1μA battery-only supply current
●Instant-on functionality
●Analog multiplexer enables power monitoring
●JEITA battery temperature monitor adjusts current
and battery regulation voltage for safe charging
●Programmable die temperature regulation
Figure 10. Linear Charger Simplified Block Diagram
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MAX77650/MAX77651 Ultra-Low Power PMIC with 3-Output SIMO
and Power Path Charger for Small Li+
Charger Symbol Reference Guide
Table 3 lists the names and functions of charger-specific
signals and if they can be programmed through I2C.
Consult the Electrical Characteristics and Programmer’s
Guide for more information.
Figure 11 indicates the high-level functions of each control
circuit within the linear charger.
SYMBOL NAME I2C PROGRAMMABLE?
VCHGIN_OVP CHGIN overvoltage threshold No
VCHGIN_UVLO CHGIN undervoltage lockout threshold No
VCHGIN-MIN Minimum CHGIN voltage regulation setpoint Yes, through VCHGIN_MIN[2:0]
ICHGIN-LIM CHGIN input current limit Yes, through ICHGIN_LIM[2:0]
VSYS-REG SYS voltage regulation target Yes, through VSYS_REG[4:0]
VSYS-MIN Minimum SYS voltage regulation setpoint No, tracks VSYS-REG
VFAST-CHG Fast-charge constant-voltage level Yes, through CHG_CV[5:0]
IFAST-CHG Fast-charge constant-current level Yes, through CHG_CC[5:0]
IPQ Prequalification current level Yes, through I_PQ
VPQ Prequalification voltage threshold Yes, through CHG_PQ[2:0]
ITERM Termination current level Yes, through I_TERM[1:0]
TJ-REG Die temperature regulation setpoint Yes, through TJ_REG[2:0]
tPQ Prequalification safety timer No
tFC Fast-charge safety timer Yes, through T_FAST_CHG[1:0]
tTO Top-off timer Yes, through T_TOPOFF[2:0]
Table 3. Charger Quick Symbol Reference Guide
Figure 11. Charger Simplified Control Loops
BODY-
SWITCH
V
CHGIN-MIN
V
CHGIN_OVP
V
CHGIN_UVLO
I
CHGIN-LIM
T
J-REG
V
SYS-REG
DIE TEMP
MONITOR
CHARGE CONTROLLER
V
SYS-MIN
I
FAST-CHG
I
PQ
I
TERM
V
FAST-CHG
V
PQ
SYS
BATT
CHGIN
INPUT
CONTROLLER
t
PQ
t
FC
t
TO
TIMER
BODY-
SWITCH
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MAX77650/MAX77651 Ultra-Low Power PMIC with 3-Output SIMO
and Power Path Charger for Small Li+
Smart Power Selector
The smart power selector seamlessly distributes power
from the input (CHGIN) to the battery (BATT) and the sys-
tem (SYS). The smart power selector basic functions are:
●When the system load current is less than the input
current limit, the battery is charged with residual
power from the input.
●When a valid input source is connected, the sys-
tem regulates to VSYS-REG to power system loads
regardless of the battery's voltage (instant on).
●When the system load current exceeds the input cur-
rent limit, the battery provides additional current to
the system (supplement mode).
●When the battery is finished charging and an input
source is present to power the system, the battery
remains disconnected from the system.
●When the battery is connected and there is no input
power, the system is powered from the battery.
Input Current Limiter
The input current limiter limits CHGIN current so as not to
exceed ICHGIN-LIM (programmed by ICHGIN_LIM[2:0]). A
maskable interrupt (CHGIN_CTRL_I) is available to signal
when the input current limit engages. The state of this
loop is reflected by the ICHGIN_LIM_STAT bit.
The input circuit is capable of standing off 28V from
ground. CHGIN suspends power delivery to the sys-
tem and battery when VCHGIN exceeds VCHGIN_OVP
(7.5V typical). The input circuit also suspends when
VCHGIN falls below VCHGIN_UVLO minus 500mV of hys-
teresis (3.5V typical). While in OVP or UVLO, the charger
remains off, and the battery provides power to the system.
When an valid charge source is connected to CHGIN,
SYS begins delivering power to the system after a 120ms
debounce timer (tCHGIN-DB).
A maskable interrupt (CHGIN_I) signals changes in the
state of CHGIN's voltage quality. The state of CHGIN is
reflected by CHGIN_DTLS[1:0].
Minimum Input Voltage Regulation
In the event of a poor-quality charge source, the mini-
mum input voltage regulation loop works to reduce input
current if VCHGIN falls below VCHGIN-MIN (programmed
by VCHGIN_MIN[2:0]). This is important because many
commonly used charge adapters feature foldback protec-
tion mechanisms where the adapter completely shuts off
if its output droops too low. The minimum input voltage
regulation loop also prevents VCHGIN from dropping
below VCHGIN_UVLO if the cable between the charge
source and the charger's input is long or highly resistive.
The input voltage regulation loop improves performance
with current limited adapters. If the charger’s input current
limit is programmed above the current limit of the given
adapter, the input voltage loop allows the input to regulate
at the current limit of the adapter. The input voltage regu-
lation loop also allows the charger to perform well with
adapters that have poor transient load response times.
A maskable interrupt (CHGIN_CTRL_I) signals when the
minimum input voltage regulation loop engages. The state
of this loop is reflected by VCHGIN_MIN_STAT.
Minimum System Voltage Regulation
The minimum system voltage regulation loop ensures that
the system rail remains close to the programmed SYS
regulation voltage (VSYS-REG) regardless of system load-
ing. The loop engages when the combined battery charge
current and system load current causes the CHGIN input
to current-limit at ICHGIN-LIM. When this happens, the
minimum system voltage loop reduces charge current in
an attempt to keep the input out of current limit, thereby
keeping the system voltage above VSYS-MIN (VSYS-REG
- 100mV typical). If this loop reduces battery current to 0
and the system is in need of more current than the input
can provide, then the smart power selector overrides the
minimum system voltage regulation loop and allows SYS
to collapse to BATT for the battery to provide supplement
current to the system. The smart power selector automati-
cally reenables the minimum system voltage loop when
the supplement event has ended.
A maskable interrupt (SYS_CTRL_I) asserts to signal a
change in VSYS_MIN_STAT. This status bit asserts when
the minimum system voltage regulation loop is active.
Die Temperature Regulation
In case the die temperature exceeds TJ-REG (pro-
grammed by TJ_REG[2:0]) the charger attempts to limit
the temperature increase by reducing battery charge
current. The TJ_REG_STAT bit asserts whenever charge
current is reduced due to this loop. The charger's cur-
rent sourcing capability to SYS remains unaffected when
TJ_REG_STAT is high. A maskable interrupt (TJ_REG_I)
asserts to signal a change in TJ_REG_STAT. It is advis-
able that the TJ_REG_I interrupt be used to signal the
system processor to reduce loads on SYS to reduce total
system temperature.
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MAX77650/MAX77651 Ultra-Low Power PMIC with 3-Output SIMO
and Power Path Charger for Small Li+
v my:
man
nsp m =
one = n
PAUSE IN ms 5
mm on EXW
Charger State Machine
The battery charger follows a strict state-to-state progres-
sion to ensure that a battery is charged safely. The status
bitfield, CHG_DTLS[3:0], reflects the charger's current
operational state. A maskable interrupt (CHG_I) is avail-
able to signal a change in CHG_DTLS[3:0].
Figure 12. Charger State Diagram
DONE
CHG_DTLS[3:0] = 0b1000
CHG = 0
FAST-CHARGE (CC)
CHG_DTLS[3:0] = 0b0010
CHG = 1
I
BATT
= I
FAST-CHG
**
ANY STATE
CHGIN INSERTED
(CHGIN_DTLS[1:0] = 0b10)
TIME ELAPSED > t
PQ
PREQUALIFICATION
CHG_DTLS[3:0] = 0b0001
CHG = 1
I
BATT
= I
PQ
V
BATT
> V
PQ
TOP-OFF
CHG_DTLS[3:0] = 0b0110
CHG = 1
V
BATT
= V
FAST-CHG
V
BATT
< V
PQ
– 100mV
CHARGER OFF
CHG_DTLS[3:0] = 0b0000
CHG = 0
PREQUALIFICATION
TIMER FAULT
CHG_DTLS[3:0] = 0b1010
CHG = 0
FAST-CHARGE
TIMER FAULT
CHG_DTLS[3:0] = 0b1011
CHG = 0
FAST-CHARGE (CV)
CHG_DTLS[3:0] = 0b0100
CHG = 1
V
BATT
= V
FAST-CHG
V
BATT
= V
FAST-CHG
V
BATT
< V
FAST-CHG
I
BATT
< I
TERM
TIME ELAPSED > t
TO
V
BATT
< V
FAST-CHG
– 150mV
CHGIN INVALID
(CHGIN_DTLS[1:0] = 0b00 or 0b01)
OR
CHARGER DISABLED
(CHG_EN = 0)
BATTERY TEMPERATURE
FAULT
CHG_DTLS[3:0] = 0b1100
CHG = 0
TIMERS PAUSE IN THIS STATE,
RESUME ON EXIT.
JEITA-MODIFIED
FAST-CHARGE (CV)
CHG_DTLS[3:0] = 0b0101
CHG = 1
V
BATT
= V
FAST-CHG_JEITA
THM_EN = 1
AND
CHG_EN = 1
AND
(T
BATT
> T
HOT
OR T
BATT
< T
COLD
)
V
BATT
= V
FAST-CHG_JEITA
V
BATT
<
V
FAST-CHG_JEITA
JEITA-MODIFIED
TOP-OFF
CHG_DTLS[3:0] = 0b0111
CHG = 1
V
BATT
= V
FAST-CHG_JEITA
RETURNS TO SAME STATE WHEN:
THM_EN = 0
OR
(T
BATT
< T
HOT
AND T
BATT
> T
COLD
)
JEITA-MODIFIED
FAST-CHARGE (CC)
CHG_DTLS[3:0] = 0b0011
CHG = 1
I
BATT
= I
FAST-CHG_JEITA
**
V
BATT
< V
FAST-CHG_JEITA
– 150mV
DE-BOUNCE
CHG_DTLS[3:0] = 0b0000
CHG = 0
TIME ELAPSED < t
CHGIN-DB
CHGIN DE-BOUNCED
TIME ELAPSED >= t
CHGIN-DB
(CHGIN_DTLS[1:0] = 0b11)
V
BATT
< V
PQ
– 100mV
*TIME ELAPSED IS AGGREGATED
THROUGHOUT THE FAST-CHARGE AND
JEITA-MODIFIED FAST-CHARGE
STATES. ALL FAST-CHARGE STATES
(REGARDLESS OF JEITA STATUS)
SHARE THE SAME SAFETY TIMER.
**I
FAST-CHG
MAY BE REDUCED BY THE
MINIMUM INPUT VOLTAGE REGULATION
LOOP, THE MINIMUM SYSTEM VOLTAGE
REGULATION LOOP, OR THE DIE
TEMPERATURE REGULATION LOOP.
I
BATT
> I
TERM
I
BATT
< I
TERM
I
BATT
> I
TERM
CHARGER ENABLED (CHG_EN = 1)
AND
CHGIN DE-BOUNCED & VALID (CHGIN_DTLS[1:0] = 0b11)
AND
BATTERY LOW BY V
RESTART
(V
BATT
< V
FAST-CHG
– 150mV)
TIME ELAPSED* > t
FC
THM_EN = 1 AND
(T
BATT
> T
WARM
OR T
BATT
< T
COOL
)
THM_EN = 0 OR
(T
BATT
< T
WARM
AND T
BATT
> T
COOL
)
THM_EN = 1 AND
(T
BATT
> T
WARM
OR T
BATT
< T
COOL
)
THM_EN = 0 OR
(T
BATT
< T
WARM
AND T
BATT
> T
COOL
)
THM_EN = 1 AND
(T
BATT
> T
WARM
OR T
BATT
< T
COOL
)
THM_EN = 0 OR
(T
BATT
< T
WARM
AND T
BATT
> T
COOL
)
THM_EN = 0 OR
(T
BATT
< T
WARM
AND T
BATT
> T
COOL
)
JEITA-MODIFIED DONE
CHG_DTLS[3:0] = 0b1001
CHG = 0
TIME ELAPSED > t
TO
ANY FAST-CHARGE OR
JEITA-MODIFIED FAST-CHARGE
STATE
CHG_DTLS[3:0] = 0b0010-0b0101
CHG = 1
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MAX77650/MAX77651 Ultra-Low Power PMIC with 3-Output SIMO
and Power Path Charger for Small Li+
Charger Off State
The charger is off when CHGIN is invalid, the charger is
disabled, or the battery is fresh.
CHGIN is invalid when the CHGIN input is invalid
(VCHGIN < VCHGIN_UVLO or VCHGIN > VCHGIN_OVP).
While CHGIN is invalid, the battery is connected to the
system. CHGIN voltage quality can be separately moni-
tored by the CHGIN_DTLS[1:0] status bitfield. Refer to
the Programmer’s Guide for details.
The charger is disabled when the charger enable bit is 0
(CHG_EN = 0). The battery is connected or disconnected
to the system depending on the validity of VCHGIN while
CHG_EN = 0. See the Smart Power Selector section.
The battery is fresh when CHGIN is valid and the charger
is enabled (CHG_EN = 1) and the battery is not low by
VRESTART (VBATT > VFAST-CHG - VRESTART). The bat-
tery is disconnected from the system and not charged
while the battery is fresh. The charger state machine exits
this state and begin charging when the battery becomes
low by VRESTART (150mV typical). This condition is func-
tionally similar to done state. See Done State section.
Prequalification State
The prequalification state is intended to assess a low-volt-
age battery's health by charging at a reduced rate. If the
battery voltage is less than the VPQ threshold, the charger
is automatically in prequalification. If the cell voltage does
not exceed VPQ in 30 minutes (tPQ), the charger faults.
The prequalification charge rate is a percentage of IFAST-
CHG and is programmable with I_PQ. The prequalifica-
tion voltage threshold (VPQ) is programmable through
CHG_PQ[2:0].
Fast-Charge States
When the battery voltage is above VPQ, the charger
transitions to the fast-charge (CC) state. In this state, the
charger delivers a constant current (IFAST-CHG) to the
cell. The constant current level is programmable from
7.5mA to 300mA by CHG_CC[5:0].
When the cell voltage reaches VFAST-CHG, the charger
state machine transitions to fast-charge (CV). VFAST-
CHG is programmable with CHG_CV[5:0] from 3.6V to
4.6V. The charger holds the battery's voltage constant
at VFAST-CHG while in the fast-charge (CV) state. As
the battery approaches full, the current accepted by the
battery reduces. When the charger detects that battery
charge current has fallen below ITERM, the charger state
machine enters the top-off state.
A fast-charge safety timer starts when the state machine
enters fast-charge (CC) or JEITA-modified fast-charge
(CC) from a non-fast-charge state. The timer continues to
run through all fast-charge states regardless of JEITA sta-
tus. The timer length (tFC) is programmable from 3 hours
to 7 hours in 2 hour increments with T_FAST_CHG[1:0].
If it is desired to charge without a safety timer, program
T_FAST_CHG[1:0] with 0b00 to disable the feature. If the
timer expires before the fast-charge states are exited, the
charger faults. See the Fast-Charge Timer Fault State
section for more information.
If the charge current falls below 20% of the programmed
value during fast-charge (CC), the safety timer pauses.
The timer also pauses for the duration of supplement
mode events. The TIME_SUS bit indicates the status of
the fast-charge safety timer. Refer to the Programmer’s
Guide for more details.
Top-Off State
Top-off state is entered when the battery charge cur-
rent falls below ITERM during the fast-charge (CV) state.
ITERM is a percentage of IFAST-CHG and is program-
mable through I_TERM[1:0]. While in the top-off state,
the battery charger continues to hold the battery's voltage
at VFAST-CHG. A programmable top-off timer starts when
the charger state machine enters the top-off state. When
the timer expires, the charger enters the done state. The
top-off timer value (tTO) is programmable from 0 minutes
to 35 minutes with T_TOPOFF[2:0]. If it is desired to stop
charging as soon as battery current falls below ITERM,
program tTO to 0 minutes.
Done State
The charger enters the done state when the top-off timer
expires. The battery remains disconnected from the
system during done. The charger restarts if the battery
voltage falls more than VRESTART (150mV typ) below the
programmed VFAST-CHG value.
Prequalification Timer Fault State
The prequalification timer fault state is entered when the
battery's voltage fails to rise above VPQ in tTO (30 min-
utes typical) from when the prequalification state was first
entered. If a battery is too deeply discharged, damaged,
or internally shorted, the prequalification timer fault state
can occur. During the timer fault state, the charger stops
delivering current to the battery and the battery remains
disconnected from the system. To exit the prequalification
timer fault state, toggle the charger enable (CHG_EN)
bit or unplug and replug the external voltage source con-
nected to CHGIN.
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MAX77650/MAX77651 Ultra-Low Power PMIC with 3-Output SIMO
and Power Path Charger for Small Li+
Fast-Charge Timer Fault State
The charger enters the fast-charge timer fault state if the
fast-charge safety timer expires. While in this state, the
charger stops delivering current to the battery and the
battery remains disconnected from the system. To exit
the fast-charge timer fault state, toggle the charger enable
bit (CHG_EN) or unplug and replug the external voltage
source connected to CHGIN.
Battery Temperature Fault State
If the thermistor monitoring circuit reports that the battery
is either too hot or too cold to charge (as programmed by
THM_HOT[1:0] and THM_COLD[1:0]), the state machine
enters the battery temperature fault state. While in this
state, the charger stops delivering current to the battery
and the battery remains disconnected from the system.
This state can only be entered if the thermistor is enabled
(THM_EN = 1). Battery temperature fault state has prior-
ity over any other fault state, and can be exited when the
thermistor is disabled (THM_EN = 0) or when the battery
returns to an acceptable temperature. When this fault
state is exited, the state machine returns to the last state it
was in before battery temperature fault state was entered.
All active charger timers (fast-charge safety timer,
prequalification timer, or top-off timer) are paused in this
state. Active timers resume when the state is exited.
The THM_DTLS[2:0] bitfield reports battery tempera-
ture status. See the Adjustable Thermistor Temperature
Monitors section and refer to the Programmer’s Guide for
more information.
JEITA-Modified States
If the thermistor is enabled (THM_EN = 1), then the char-
ger state machine is allowed to enter the JEITA-modified
states. These states are entered if the charger's tem-
perature monitors indicate that the battery temperature
is either warm (greater than TWARM) or cool (lesser than
TCOOL). See the Adjustable Thermistor Temperature
Monitors section for more information about setting the
temperature thresholds.
The charger's current and voltage parameters change
from IFAST-CHG and VFAST-CHG to IFAST-CHG_JEITA and
VFAST-CHG_JEITA while in the JEITA-modified states. The
JEITA modified parameters can be independently set to
lower voltage and current values so that the battery can
charge safely over a wide range of ambient tempera-
tures. If the battery temperature returns to normal, or the
thermistor is disabled (THM_EN = 0) the charger exits the
JEITA-modified states.
Typical Charge Profile
A typical battery charge profile (and state progression) is
illustrated in Figure 13.
Figure 13. Example Battery Charge Profile
2
4
5
3
1
(V)
CHGIN
SYS
BATT
I
BATT
(mA)
500
400
300
200
100
I
FAST-CHG
= 300mA
I
TERM
= 30mA
I
PQ
= 30mA
V
SYS-REG
= 4.5V
V
PQ
= 2.3V
V
FAST-CHG
= 4.25V
(TIME)
PREQUALIFICATION
FAST-CHARGE (CC) FAST-CHARGE (CV) TOP-OFF DONE
t
TO
CHGIN
INVALID
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Charger Applications Information
Configuring a Valid System Voltage
The smart power selector begins to regulate SYS to
VSYS-REG when CHGIN is connected to a valid source. To
ensure the charger's accuracy specified in the Electrical
Characteristics table, the system voltage must always
be programmed at least 200mV above the charger's
constant-voltage level (VFAST-CHG). If this condition is not
met, then the charger's internal configuration logic forces
VFAST-CHG to reduce to satisfy the 200mV requirement. If
this happens, the charger asserts the SYS_CNFG_I inter-
rupt to alert the user that a configuration error has been
made and that the bits in CHG_CV[5:0] have changed to
reduce VFAST-CHG.
CHGIN/SYS/BATT Capacitor Selection
Bypass CHGIN to GND with a 4.7μF ceramic capacitor to
minimize inductive kick caused by long cables between
the DC charge source and the device. Larger values
increase decoupling for the linear charger, but increase
inrush current from the DC charge source when the
device is first connected to a source through a cable/plug.
If the DC charging source is an upstream USB device,
limit the maximum CHGIN input capacitance based on
the appropriate USB specification (typically no more than
10μF). The effective value of the CHGIN capacitor must
be greater than 1µF when biased with 5V.
Bypass SYS to GND with a 22μF ceramic capacitor.
This capacitor is needed to ensure stability of SYS while
it is being regulated from CHGIN. Since SYS must be
connected to IN_SBB, then one capacitor can be used
to bypass this node as long as it is physically close to
the device. Larger values of SYS capacitance increase
decoupling for all SYS loads. When biased with 4.5V, the
effective value of the SYS capacitor must be greater than
4μF and no more than 100μF.
Bypass BATT to GND with a 4.7μF ceramic capacitor.
This capacitor is required to ensure stability of the BATT
voltage regulation loop. When biased with 4.5V, the effec-
tive value of the BATT capacitor must be greater than 1μF.
Ceramic capacitors with X5R or X7R dielectric are highly
recommended due to their small size, low ESR, and small
temperature coefficients. All ceramic capacitors derate
with DC bias voltage (effective capacitance goes down as
DC bias goes up). Generally, small case size capacitors
derate heavily compared to larger case sizes (0603 case
size performs better than 0402). Consider the effective
capacitance value carefully by consulting the manufac-
turer's data sheet.
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U
U
THNLDTLSH u] : mama 0R 0an
THNLDTLSH u] : 0mm 0R omuo
Adjustable Thermistor Temperature
Monitors
The optional use of a negative temperature coeffi-
cient (NTC) thermistor (thermally coupled to the battery)
enables the charger to operate safely over the JEITA tem-
perature range. When the thermistor is enabled (THM_EN
= 1), the charger continuously monitors the voltage at the
THM pin in order to sense the temperature of the battery
being charged.
Figure 14. Thermistor Logic Functional Diagram
THM_EN
CHG_CC[5:0]
CHG_CC_JEITA[5:0]
I
FAST-CHG
CHG_CV[5:0]
CHG_CV_JEITA[5:0]
V
FAST-CHG
S0
D0
D0
D1
D1
S0
TBIAS
1.25V
THM_DTLS[2:0] = 0b001 OR 0b100
(BATTERY COLD OR HOT). CHARGING IS
PAUSED REGARDLESS OF CHG_EN.
0b1
INTERNAL HOT/COLD SIGNAL
THM_DTLS[2:0] = 0b010 OR 0b011
(BATTERY COOL OR WARM). CHARGER
V&I PARAMETERS SWITCH TO JEITA
SETTINGS.
0b1
INTERNAL COOL/WARM SIGNAL
R
BIAS
NTC
THM_DTLS[2:0] = 0b000 OR 0b101 (NTC
DISABLED OR BATTERY NORMAL).
CHARGER V&I PARAMETERS FOLLOW
NORMAL SETTINGS.
0b0
THM_DTLS[2:0] ≠ 0b001 OR 0b100
(BATTERY NOT COLD OR HOT). CHARGER
V&I PARAMETERS FOLLOW NORMAL OR
JEITA SETTINGS.
0b0
THM
THM_HOT[1:0]
THM_COOL[1:0]
THM_COLD[1:0]
THM_WARM[1:0]
TBIAS SWITCH
CONTROL
(FIGURE 16)
MAX77650/
MAX77651
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See Figure 15 for a visual example of what is described
here in text.
●If the battery temperature is higher than TCOOL and
lower than TWARM, the battery charges normally with
the normal values for VFAST-CHG and IFAST-CHG. The
charger state machine does not enter JEITA-modified
states while the battery temperature is normal.
●If the battery temperature is either above TWARM
but below THOT, or, below TCOOL but above TCOLD,
the battery charges with the JEITA-modified volt-
age and current values. These modified values,
VFAST-CHG_JEITA and IFAST-CHG_JEITA, are pro-
grammable through CHG_CV_JEITA[5:0] and
CHG_CC_JEITA[5:0], respectively. These values are
independently programmable from the nonmodified
VFAST-CHG and IFAST-CHG values and can even
be programmed to the same values if an automatic
response to a warm or cool battery is not desired. The
charger state machine enters JEITA-modified states
while the battery temperature is outside of normal.
●If the battery temperature is either above THOT or below
TCOLD, the charger follows the JEITA recommendation
and pauses charging. The charger state machine enters
battery temperature fault state while charging is paused
due to extreme high or low temperatures.
The battery's temperature status is reflected by the
THM_DTLS[2:0] status bitfield. A maskable interrupt
(THM_I) signals a change in THM_DTLS[2:0]. Refer to
the Programmer’s Guide for more information. To com-
pletely disable the charger's automatic response to bat-
tery temperature, disable the feature by programming
THM_EN = 0.
The voltage thresholds corresponding to the JEITA temper-
ature thresholds are independently programmable through
THM_HOT[1:0], THM_WARM[1:0], THM_COOL[1:0], and
THM_COLD[1:0]. Each threshold can be programmed
to one of four voltage options spanning 15°C for an
NTC beta of 3380K. See the Configurable Temperature
Thresholds section and refer to the Programmer’s Guide
for more information.
Figure 15. Safe-Charging Profile Example
BATTERY TEMPERATURE
25
°
C15
°
C 45
°
C 60
°
C 85
°
C
V
FAST-CHG
= 4.2V
(CHG_CV[5:0] = 0b011000)
V
FAST-CHG_JEITA
= 4.075V
(CHG_CV_JEITA[5:0] = 0b010011)
BATT REGULATION VOLTAGE (V)
FAST-CHARGE CURRENT (A)
-40
°
C
I
FAST-CHG
= 150mA
(CHG_CC[5:0] = 0b010011)
4.0V
4.1V
4.2V
4.3V
4.4V EXAMPLE TEMPERATURES
FOR NTC β = 3380K
THM_COLD[1:0] = 0b10 (0
°
C)
THM_COOL[1:0] = 0b11 (15
°
C)
THM_WARM[1:0] = 0b10 (45
°
C)
THM_HOT[1:0] = 0b11 (60
°
C)
75
°
C
-25
°
C
T
COLD
0
°
C
T
COOL
T
WARM
T
HOT
BATTERY TEMPERATURE
25
°
C15
°
C 45
°
C 60
°
C 85
°
C-40
°
C 75
°
C-25
°
C
COLD COOL NORMAL WARM HOT
0
°
C
I
FAST-CHG_JEITA
= 75mA
(CHG_CC_JEITA[5:0] = 0b001001)
T
COLD
T
COOL
T
WARM
T
HOT
0
0.05
0.1
0.15
COLD COOL NORMAL WARM HOT
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Thermistor Bias
An external ADC can optionally perform conversions on
the THM and TBIAS pins to measure the battery's tem-
perature. An on-chip analog multiplexer is used to route
these nodes to the AMUX pin. The operation of the analog
multiplexer does not interfere with the charger's tempera-
ture monitoring comparators or the charger's automatic
JEITA response. See the Analog Multiplexer & Power
Monitor AFEs section for more information.
The NTC thermistor's bias source (TBIAS) follows the
simple operation outlined below:
●If CHGIN is valid and the thermistor is enabled
(THM_EN = 1), then the thermistor is biased so the
charger can automatically respond to battery tem-
perature changes.
●If the analog multiplexer is connecting THM or
TBIAS to AMUX, then the thermistor is biased so an
external ADC can perform a meaningful temperature
conversion.
The AMUX pin is a buffered output. The operation of the
analog multiplexer and external ADC does not collide with
the function of the on-chip temperature monitors. Both
functions may be used simultaneously with no ill effect.
Configurable Temperature Thresholds
Temperature thresholds for different NTC thermistor beta
values are listed in Table 4. The largest possible program-
mable temperature range can be realized by using an NTC
with a beta of 3380K. Using a larger beta compresses the
temperature range. The trip voltage thresholds are pro-
grammable with the THM_HOT[1:0], THM_WARM[1:0],
THM_COOL[1:0], and THM_COLD[1:0] bitfields. All pos-
sible programmable trip voltages are listed in Table 4.
These are theoretical values computed by a formula.
Refer to the particular NTC's data sheet for more accurate
measured data. In all cases, select the value of RBIAS to
be equal to the NTC's effective resistance at +25°C.
TRIP VOLTAGE
(V)
TRIP TEMPERATURES (°C)
3380K 3435K 3940K 4050K 4100K 4250K
1.024 -10.0 -9.5 -5.6 -4.8 -4.5 -3.5
0.976 -5.0 -4.6 -1.1 -0.5 -0.2 0.6
0.923 0.0 0.3 3.3 3.8 4.1 4.8
0.867 5.0 5.3 7.7 8.1 8.3 8.9
0.807 10.0 10.2 12.0 12.4 12.5 12.9
0.747 15.0 15.1 16.4 16.6 16.7 17.0
0.511 35.0 34.8 33.5 33.3 33.2 32.9
0.459 40.0 39.8 37.8 37.4 37.3 36.8
0.411 45.0 44.7 42.0 41.5 41.3 40.7
0.367 50.0 49.6 46.2 45.6 45.3 44.6
0.327 55.0 54.5 50.4 49.7 49.3 48.4
0.291 60.0 59.4 54.6 53.7 53.3 52.2
Table 4. Trip Temperatures vs. Trip Voltages for Different NTC β
Figure 16. Thermistor Bias State Diagram
THERMISTOR BIASED
TBIAS = 1.25V
MUX_SEL = 0b0111 or 0b1000
OR
(THM_EN = 1 AND CHGIN VALID)
MUX_SEL ≠ 0b0111 or 0b1000
AND
(THM_EN = 0 OR CHGIN INVALID)
THERMISTOR OFF
TBIAS = GND
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Thermistor Applications Information
Using Different Thermistor β
If an NTC with a beta larger than 3380K is used and the
resulting available programmable temperature range is
undesirably small, then two adjusting resistors can be
used to expand the temperature range. RS and RP can
be optionally added to the NTC thermistor circuit shown
in Figure 17 to expand the range of programmable tem-
perature thresholds.
Select values for RS and RP based on the information
shown in Table 5.
NTC Thermistor Selection
Popular NTC thermistor options are listed in Table 6.
Table 5. Example RS and RP Correcting Values for NTC β Above 3380K
MANUFACTURER PART Β-CONSTANT
(25°C/50°C) R (Ω) AT 25°C CASE SIZE
TDK NTCG063JF223HTBX 3380K 22k 0201
Murata NCP03XH103F05RL 3380K 10k 0201
Murata NCP15XH103F03RC 3380K 10k 0402
TDK NTCG103JX103DT1 3380K 10k 0402
Cantherm CMFX3435103JNT 3435K 10k 0402
Murata NCP15XV103J03RC 3900K 10k 0402
Panasonic ERT-JZEP473J 4050K 47k 0201
Panasonic ABNTC-0402-473J-4100F-T 4100K 47k 0402
Murata NCP15WF104F03RC 4250K 100k 0402
Table 6. NTC Thermistors
PARAMETER UNIT DESIGN TARGET CASE CASE 1 CASE 2 CASE 3
NTC thermistor beta K3380 3940 4050 4250
25°C NTC resistance
kΩ
10 10 47 100
RBIAS 10 10 47 100
Adjusting parallel resistor, RPopen open 200 open 680 open 1300
Adjusting series resistor, RSshort short 0.62 short 3.3 short 9.1
RNTC at 1.024VCOLD threshold 45.24 45.24 578.5 212.6 306.1 452.4 684.8
RNTC at 0.867VCOOL threshold 22.61 22.61 248.8 106.3 122.7 226.1 264.7
RNTC at 0.459VWARM threshold 5.81 5.81 5.36 27.3 25.1 58.1 51.7
RNTC at 0.291VHOT threshold 3.04 3.04 2.46 14.3 112.7 30.4 22.0
TACTUAL at VCOLD (-10°C expected)
°C
-10.03 -5.56 -9.96 -4.82 -11.14 -3.55 -10.46
TACTUAL at VCOOL (5°C expected) 4.98 7.66 5.76 8.10 5.33 8.86 5.94
TACTUAL at VWARM (40°C expected) 40.02 37.79 39.76 37.43 39.40 36.82 39.48
TACTUAL at VHOT (60°C expected) 60.04 54.56 60.37 53.68 60.02 52.21 60.4
Figure 17. Thermistor Circuit with Adjusting Series and Parallel
Resistors
Figure 17
THM
TBIAS
R
BIAS
NTC
R
P
R
S
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MAX77650/MAX77651 Ultra-Low Power PMIC with 3-Output SIMO
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&
m
M
AMUX
AMUX
Analog Multiplexer & Power Monitor AFEs
An external ADC can be used to measure the chip's vari-
ous signals for general functionality or on-the-fly power
monitoring. The MUX_SEL[3:0] bitfield controls the inter-
nal analog multiplexer responsible for connecting the
proper channel to the AMUX pin. Each measurable signal
is listed below with its appropriate multiplexer channel.
The voltage on the AMUX pin is a buffered output that
ranges from 0V to VFS (1.25V typ). The buffer has a
50μA quiescent current draw and is only active when the
device's main bias is active and a channel is selected
(MUX_SEL[3:0] ≠ 0b0000). Disable the buffer by pro-
gramming to MUX_SEL[3:0] to 0b0000 when not actively
converting the voltage on AMUX.
Table 7 shows how to translate the voltage signal on the
AMUX pin to the value of the parameter being measured.
See the Electrical Characteristics—Analog Multiplexer and
Power Monitor AFEs table and refer to the Programmer’s
Guide for more details.
SIGNAL MUX_SEL
[3:0] TRANSFER FUNCTION
FULL-SCALE
SIGNAL
MEANING
(VAMUX = 1.25V)
ZERO-SCALE
SIGNAL
MEANING
(VAMUX = 0V)
CHGIN pin
voltage 0b0001 VCHGIN =
VAMUX
GVCHGIN
7.5V 0V
CHGIN pin
current 0b0010 ICHGIN =
VAMUX
GICHGIN
0.475A 0A
BATT pin
voltage 0b0011 VBATT =
VAMUX
GVBATT
4.6V 0V
BATT pin
charging
current
0b0100 IBATT
(
CHG
)
=VAMUX
VFS × IFAST − CHG
100% of IFAST-CHG
(CHG_CC[5:0])
0% of
IFAST-CHG
BATT pin
discharge
current
0b0101 IBATT
(
DISCHG
)
=
(
VAMUX − VNULL
)
(
VFS − VNULL
)
× IDISCHG − SCALE
100% of
IDISCHG-SCALE
(IMON_DISCHG_SCALE[3:0])
0% of
IDISCHG-SCALE
BATT pin
discharge
current NULL
0b0110 VNULL = VAMUX 1.25V 0V
THM pin
voltage 0b0111 VTHM = VAMUX 1.25V 0V
TBIAS pin
voltage 0b1000 VTBIAS = VAMUX 1.25V 0V
AGND pin
voltage* 0b1001 VAGND = VAMUX 1.25V 0V
SYS pin
voltage 0b1010 VSYS =
VAMUX
GVSYS
4.8V 0V
Table 7. AMUX Signal Transfer Functions
*AGND pin voltage is accessed through a 100Ω (typ) pulldown resistor. Setting MUX_SEL[3:0] to 0b0000 disables the multiplexer
and changes the AMUX pin to a high-impedance state.
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AM UX
Measuring Battery Current
It is possible to sample the current in the BATT pin at any
time or in any mode with an external ADC. For improved
accuracy, the analog circuitry used for monitoring battery
discharge current is different from the circuitry monitoring
battery charge current. Table 8 outlines how to determine
the direction of battery current.
Method for Measuring Discharging Current
●Program the multiplexer to switch to the discharge
NULL measurement by changing MUX_SEL[3:0] to
0b0110. A NULL conversion must always be per-
formed first to cancel offsets.
● Wait the appropriate channel switching time (0.3μs
typ).
●Convert the voltage on the AMUX pin and store as
VNULL.
●Program the multiplexer to switch to the battery
discharge current measurement by changing MUX_
SEL[3:0] to 0b0101. A nonnulling conversion should
be done immediately after a NULL conversion.
● Wait the appropriate channel switching time (0.3μs
typ).
●Convert the voltage on AMUX pin and use the following
transfer function to determine the discharge current.
IBATT
(
DISCHG
)
=
(
VAMUX − VNULL
)
(
VFS − VNULL
)
× IDISCHG − SCALE
VFS is 1.25V (typ). IDISCHG-SCALE is programmable
through IMON_DISCHG_SCALE[3:0]. The default value
is 300mA. If smaller currents are anticipated, then
IDISCHG-SCALE can be reduced for improved measure-
ment accuracy.
Method for Measuring Charging Current
●Program the multiplexer to switch to the charge
current measurement by changing MUX_SEL[3:0] to
0b0100.
● Wait the appropriate channel switching time (0.3μs
typ).
●Convert the voltage on the AMUX pin and use the fol-
lowing transfer function to determine charging current.
IBATT
(
CHG
)
=VAMUX
VFS × IFAST − CHG
VFS is 1.25V (typ). IFAST-CHG the charger's fast-charge
constant-current setting and is programmable through
CHG_CC[5:0].
MEASUREMENT CHARGING OR DISCHARGING INDICATORS
CHG BIT CHG_DTLS[3:0] CHGIN_DTLS[1:0]
Discharging Battery Current
(Positive Battery Terminal Sourcing Current
into the BATT pin of MAX77650/MAX77651)
Don't care Don't care
0b00
0b01
0b10
Charging Battery Current
(Positive Battery Terminal Sinking Current from
the BATT pin of MAX77650/MAX77651)
10b0001–0b0111 0b11
Table 8. Battery Current Direction Decode
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MAX77650/MAX77651 Ultra-Low Power PMIC with 3-Output SIMO
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ERRDR CUMPARAIOR
ACHVErD‘
J7
SIMO Buck-Boost
The device has a micropower single-inductor, multiple-out-
put (SIMO) buck-boost DC-to-DC converter designed for
applications that emphasize low supply current and small
solution size. A single inductor is used to regulate three
separate outputs, saving board space while delivering
better total system efficiency than equivalent power solu-
tions using one buck and linear regulators.
The SIMO configuration utilizes the entire battery voltage
range due to its ability to create output voltages that are
above, below, or equal to the input voltage. Peak induc-
tor current for each output is programmable to optimize
the balance between efficiency, output ripple, EMI, PCB
design, and load capability.
SIMO Benefits and Features
●3 Output Channels
●Ideal for Low-Power Designs
• Delivers > 300mA at 1.8V from a 3.7V Input
• ±3% Accurate Output Voltage
●Small Solution Size
• Multiple Outputs from a Single 1.5μH (0603) Inductor
• Small 10μF (0402) Output Capacitors
●Flexible and Easy to Use
• Single Mode of Operation
• Programmable Peak Inductor Current
• Programmable On-Chip Active Discharge
●Long Battery Life
• High Efficiency, > 87% at 3.3V Output
• Better Total System Efficient than Buck + LDOs
• Low Quiescent Current, 1μA per Output
• Low Input Operating Voltage, 2.7V (min)
Figure 18. SIMO Detailed Block Diagram
1.5µH
LXB
10µF
(0402)
3300pF
(0201)
PGND
10µF
(0402)
REVERSE
BLOCKING
SBB0
DIGITAL AND
REGISTERS
CNFG_SBB_TOP,
CNFG_SBBX_A,
CNFG_SBBX_B
SIMO
CONTROLLER
/
M1
M2 M4
LXA
ILIM
IZX
DRV_SBB
SYNCHRONOUS RECTIFIER
BST
DRV_SBB
CHG
DIS
SYNCHRONOUS
RECTIFIER (M3_1)
AND
ERROR COMPARATOR
AND
ACTIVE-DISCHARGE
DRV_SBB
BST
DIS_SBB1
DIS_SBB1
10µF
(0402)
SBB1
ERROR COMPARATOR
REG0
REG1
SYNCHRONOUS
RECTIFIER (M3_2)
AND
ERROR COMPARATOR
AND
ACTIVE-DISCHARGE
DRV_SBB
BST
DIS_SBB2
10µF
(0402)
SBB2
REG2
ACTIVE-DISCHARGE
AD_SBB0
AD_SBB1
AD_SBB2
MAIN POWER STAGE
I.ZX
I.LIM CHG
DIS
DIS_SBB[2:0]
REG[2:0]
DRV_SBB
COMM
VREF
SYS IN_SBB
BST
IN_SBB
M3_0
AD_SBB[2:0]
RAD_SSB0
(140Ω)
FPS
VIREF
SYS_RST
MAX77650/MAX77651
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dV
3.3V
SIMO Control Scheme
The SIMO buck-boost is designed to service multiple out-
puts simultaneously. A proprietary controller ensures that
all outputs get serviced in a timely manner, even while
multiple outputs are contending for the energy stored in
the inductor. When no regulator needs service, the state
machine rests in a low-power rest state.
When the controller determines that a regulator requires
service, it charges the inductor (M1 + M4) until the peak
current limit is reached (ILIM = IP_SBB). The inductor
energy then discharges (M2 + M3_x) into the output until
the current reaches zero (IZX). In the event that multiple
output channels need servicing at the same time, the con-
troller ensures that no output utilizes all of the switching
cycles. Instead, cycles interleave between all the outputs
that are demanding service, while outputs that do not
need service are skipped.
SIMO Soft-Start
The soft-start feature of the SIMO limits inrush current dur-
ing startup. The soft-start feature is achieved by limiting
the slew rate of the output voltage during startup to dV/dtSS
(5mV/μs typ).
More output capacitance results in higher input current
surges during startup. The following set of equations and
example describes the input current surge phenomenon
during startup.
The current into the output capacitor (ICSBB) during soft-start is:
ICSBB = CSBB
dV
dtSS (Equation 1)
where CSBB is the capacitance on the output of the regula-
tor, and dV/dtSS is the voltage change rate of the output.
The input current (IIN) during soft-start is:
IIN =
(
ICSBB +I
LOAD
)
VSBBx
VIN
ξ(Equation 2)
where ICSBB is from the calculation above, ILOAD is cur-
rent consumed from the external load, VSBBx is the output
voltage, and VIN is the input voltage, ξ is the efficiency of
the regulator.
For example, given the following conditions, the peak
input current (IIN) during soft-start is ~71mA:
Given:
●VIN is 3.5V
●VSBB2 is 3.3V
●CSBB2 = 10µF
●dV/dtSS = 5mV/µs
●RLOAD2 = 330Ω (ILOAD2 = 3.3V/330Ω = 10mA)
● ξ is 80%
Calculation:
●ICSBB = 10µF x 5mV/µs (from Equation 1)
●ICSBB = 50mA
●IIN =
(
50mA + 10mA
)
3.3V
3.5V
0.85 (from Equation1)
●IIN ~ 71mA
SIMO Registers
Each SIMO buck-boost channel has a dedicated register
to program its target output voltage (TV_SBBx) and its
peak current limit (IP_SBBx). Additional controls are avail-
able for enabling/disabling the active discharge resistors
(ADE_SBBx), as well as enabling/disabling the SIMO
buck-boost channels (EN_SBBx). For a full description of
bits, registers, default values, and reset conditions, refer
to the Programmer’s Guide.
SIMO Active Discharge Resistance
Each SIMO buck-boost channel has an active-discharge
resistor (RAD_SBBx) that is automatically enabled/dis-
abled based on a ADE_SBBx and the status of the SIMO
regulator. The active discharge feature can be enabled
(ADE_SBBx = 1) or disabled (ADE_SBBx = 0) indepen-
dently for each SIMO channel. Enabling the active dis-
charge feature helps ensure a complete and timely power
down of all system peripherals. If the active-discharge
resistor is enabled by default, then the active-discharge
resistor is on whenever VSYS is below VSYSUVLO and
above VPOR.
These resistors discharge the output when ADE_SBBx
= 1, and their respective SIMO channel is off. Note if
the regulator is forced on through EN_SBBx = 0b110 or
0b111, then the resistors do not discharge the output even
if the regulator is disabled by the main-bias.
Note that when VSYS is less than 1.0V, the NMOS transis-
tors that control the active discharge resistors lose their
gate drive and become open.
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SIMO Applications Information
SIMO Available Output Current
The available output current on a given SIMO channel is
a function of the input voltage, output voltage, peak cur-
rent limit setting, and the output current of the other SIMO
channels. Maxim offers a SIMO calculator that outlines
the available capacity for specific conditions. See Support
Materials for more information on this and other engineer-
ing resources. Table 9 is an extraction from the calculator.
Inductor Selection
Choose an inductance from 1.0μH to 2.2uH; 1.5μH induc-
tors work best for most designs. Larger inductances
transfer more energy to the output for each cycle and
typically result in larger output voltage ripple and better
efficiency. See the Output Capacitor Selection section for
more information on how to size your output capacitor in
order to control ripple.
Choose the inductor saturation current to be greater than
or equal to the maximum peak current limit setting that is
used for all of the SIMO buck-boost channels (IP_SBB).
For example, if SBB0 is set for 0.5A, SBB1 is set for
0.866A, and SBB2 is set for 1.0A, then choose the satura-
tion current to be greater than or equal to 1.0A.
Choose the RMS current rating of the inductor (typically
the current at which the temperature rises appreciably)
based on the expected load currents for the system. For
systems where the expected load currents are not well
known, be conservative and choose the RMS current to
be greater than or equal to the half of higher maximum
peak current limit setting [IRMS>=MAX(IP_SBB0, IP_
SBB1, IP_SBB2)/2]. This is a safe/conservative choice
because the SIMO buck-boost regulator implements a
discontinuous conduction mode (DCM) control scheme,
which returns the inductor current to zero each cycle.
Consider the DC-resistance (DCR), AC-resistance (ACR)
and solution size of the inductor. Typically, smaller
sized inductors have larger DC-resistance and larger
AC-resistance that reduces efficiency and the available
output current. Note that many inductor manufacturers
have inductor families which contain different versions
of core material in order to balance trade-offs between
DCR, ACR (i.e., core losses), and component cost. For
this SIMO regulator, inductors with the lowest ACR in
the 1.0MHz to 2.0MHz region tend to provide the best
efficiency.
See Table 10 for examples of inductors that work well
with this device. This table was created in 2016. Inductor
technology advances rapidly. Always consider the most
current inductor technology for new designs to achieve
the best possible performance.
PARAMETERS EXAMPLE 1 EXAMPLE 2 EXAMPLE 3
V.IN.MIN 2.7V 3.2V 3.4V
R.L.DCR 0.1Ω 0.1Ω 0.12Ω
SBB1 1V at 100mA 1.2V at 50mA 1.2V at 20mA
SBB0 1.2V at 75mA 2.05V at
100mA 2.05V at 80mA
SBB2 1.8V at 50mA 3.3V at 30mA 3.3V at 10mA
I.PEAK.0 1A 0.866A 0.5A
I.PEAK.1 1A 0.707A 0.5A
I.PEAK.2 1A 1A 0.5A
Utilized
Capacity 73 79 73
*R.C.IN = R.C.OUT = 5mΩ, L = 1.5μH
Table 9. SIMO Available Output Current
for Common Applications
MANUFACTURER PART L (µH) ISAT (A) IRMS (A) DCR (Ω) X (mm) Y (mm) Z (mm)
Samsung CIGT201610EH2R2MN 2.2 2.9 2.7 0.073 2.0 1.6 1.0
Murata DFE201610E-2R2M 2.2 2.6 1.9 0.117 2.0 1.6 1.0
Murata DFE201610E-1R5M 1.5 2.4 3.2 0.076 2.0 1.6 1.0
Murata DFE201210S-2R2M 2.2 2.3 1.80 0.127 2.0 1.2 1.0
Murata DFE201210S-1R5M 1.5 2.2 2.6 0.086 2.0 1.2 1.0
Samsung CIGT201208EH2R2MN 2.2 2.0 1.8 0.095 2.0 1.25 0.8
Murata DFE201208S-1R5M 1.5 2.4 2.0 0.110 2.0 1.2 0.8
Murata DFE201208S-2R2M 2.2 2.0 1.6 0.170 2.0 1.2 0.8
Table 10. Example Inductors
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Input Capacitor Selection
Choose the input bypass capacitance (CIN_SBB) to be
10µF. Larger values of CIN_SBB improve the decoupling
for the SIMO regulator.
CIN_SBB reduces the current peaks drawn from the battery
or input power source during SIMO regulator operation and
reduces switching noise in the system. The ESR/ESL of the
input capacitor should be very low (i.e., ≤ 5mΩ + ≤ 500pH)
for frequencies up to 2MHz. Ceramic capacitors with X5R
or X7R dielectric are highly recommended due to their
small size, low ESR, and small temperature coefficients.
To fully utilize the available input voltage range of the
SIMO (5.5V max), use a 6.3V capacitor voltage rating.
IN_SBB is a critical discontinuous current path that
requires careful bypassing. When the SIMO detects that
an output is below its regulation threshold, a switching
cycle begins and the IN_SBB current ramps up as a func-
tion of the input voltage and inductor (di/dt = VIN_SBB/L)
until it reaches the peak current limit (IP_SBB). Once
IP_SBB is reached, the IN_SBB current falls to zero
rapidly (~5ns). This rapid current decrease makes the
parasitic inductance in the PGND to input capacitor to
IN_SBB path critical. In the PCB layout, place CIN_SBB as
close as possible to the power pins (IN_SBB and PGND)
to minimize parasitic inductance. If making connections
to the input capacitor through vias, ensure that the vias
are rated for the expected input current so they do not
contribute excess inductance and resistance between the
bypass capacitor and the power pins.
Boost Capacitor Selection
Choose the boost capacitance (CBST) to be 3.3nF. Smaller
values of CBST (< 1nF) result in insufficient gate drive for
M3. Larger values of CBST (> 10nF) have the potential
to degrade the startup performance. Ceramic capacitors
with 0201 or 0402 case size are recommended.
Output Capacitor Selection
Choose each output bypass capacitance (CSBBx) based
on the desired output voltage ripple; typical values are
10µF. Larger values of CSBBx improve the output volt-
age ripple but increase the input surge currents during
soft-start and output voltage changes. The output voltage
ripple is a function of the inductance, the output voltage,
and the peak current limit setting. Maxim offers a SIMO
calculator to aid in the selection of the output capacitance.
See Support Materials for more information on this and
other engineering resources.
Note that most designs concern themselves with having
enough capacitance on the output but there is also a
maximum capacitance limitation that is calculated within
the SIMO Calculator; take care not to exceed the maxi-
mum capacitance.
CSBBx is required to keep the output voltage ripple small.
The impedance of the output capacitor (ESR, ESL) should
be very low (i.e., ≤ 5mΩ + ≤ 500pH) for frequencies up to
2MHz. Ceramic capacitors with X5R or X7R dielectric are
highly recommended due to their small size, low ESR,
and small temperature coefficients.
A capacitor's effective capacitance decreases with
increased DC bias voltage. This effect is more pro-
nounced as capacitor case sizes decrease. Due to this
characteristic, it is possible for an 0603 case size capaci-
tor to perform well, while an 0402 case size capacitor of
the same value performs poorly. The SIMO regulator is
stable with low output capacitance (1μF) but the output
voltage ripple would be large; consider the effective out-
put capacitance value after initial tolerance, bias voltage,
aging, and temperature derating.
SBBx is a critical discontinuous current path that requires
careful bypassing. When the SIMO detects that an output
is below its target, it charges the inductor to a peak cur-
rent limit (IP_SBB) and then discharges that inductor into
the output. At the moment the charge is applied to the
output, the current increases rapidly and then decays
relatively slowly (dt/dt = VOUT/L). This rapid current
increase is a function of the drive strength setting (DRV_
SBB) and makes the parasitic inductance in the SBBx to
output capacitor to PGND path critical. In the PCB layout,
place CSBBx as close as possible to SBBx and PGND
to minimize parasitic inductance. If making connections
to the output capacitor through vias, ensure that the vias
are rated for the expected output current so they do not
contribute excess inductance and resistance.
SIMO Switching Frequency
The SIMO buck-boost regulator utilizes a pulse frequency
modulation (PFM) control scheme. The switching fre-
quency for each output is a function of the input voltage,
output voltage, load current, and inductance. Maxim
offers a SIMO calculator to aid in the understanding of the
switching frequency.
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At no load, switching frequencies can be as low as 10Hz.
It is possible to get SIMO switching frequencies that are
high (5.7MHz) with all of the worst-case conditions: high
input voltage (4.5V), low inductance (1.0µH), high output
voltage (5.0V), low peak current limit (0.5A), and high
utilization (80% which is 90mA with these conditions).
With these high switching frequencies, the SIMO effi-
ciency is poor. The maximum switching frequencies for
designs should be no more than 3MHz. For example, in
the 5.7MHz example above if we change the inductance
to peak current limit from 0.5A to 0.707A while leaving the
load current at 90mA, then the switching frequency drops
to 2.4MHz. If we put the peak current limit at 0.866A and
change the inductance to 1.5µH, then the switching fre-
quency drops to 1MHz which provides a “nice” efficiency.
Unused Outputs
Do not leave unused outputs unconnected. If an output
left unconnected is accidentally enabled, inductor current
dumps into an open pin, and the output voltage can soar
above the absolute maximum rating, potentially causing
damage to the device. If the unused output is always
disabled (EN_SBBx = 0x4 or 0x5), connect that output to
ground. If an unused output can be enabled at any point
during operation (such as startup or accidental software
access), then implement one of the following:
●Bypass the unused output with a 1µF ceramic capacitor
to ground.
●Connect the unused output to the power input (IN_
SBB). This connection is beneficial because it does
not require an external component for the unused
output. The power input and its capacitance receives
the energy packets when the regulator is enabled
and VIN_SBB is below the target output voltage of
the unused output. Circulating the energy back to the
power input ensures that the unused output voltage
does not fly high.
• Note that some OTP options of the device have the
active-discharge resistors enabled by default (ADE_
SBBx) such that connecting an unused output SBBx
to IN_SBB creates a 140Ω (RAD_SBBx) to ground
until software can be ran to disable the active-dis-
charge resistor. Connecting an unused SBBx to
IN_SBB is not recommended if the regulator's
active-discharge resistor is enabled by default.
●Connect the unused output to another power output
that is above the target voltage of the unused output.
In the same way as the option listed above, this con-
nection is beneficial because it does not require an
external component for the unused output. Unlike the
option above, this connection is preferred in cases
where the unused output voltage bias level is always
above the unused output voltage target because no
energy packages are provided to the unused output.
• Note that some OTP options of the device have the
active-discharge resistors enabled by default (ADE_
SBBx). If the other power output used to bias the
unused output is normally off, then the active-dis-
charge resistor of the unused output does not cre-
ate a continuous current draw. Remember that once
the system is enabled, it should turn off the unused
output's active-discharge resistor (ADE_SBBx = 0).
LDO
The device includes one on-chip low-dropout linear regu-
lator (LDO). This LDO is optimized to have low-quiescent
current and low dropout voltage. The input voltage range
of this LDO (VIN_LDO) allows it to be powered directly
from the main energy source such as a Li-Poly battery or
from an intermediate regulator. The linear regulator deliv-
ers up to 150mA.
Features
●150mA LDO
●1.8V to 5.5V Input Voltage Range
●Adjustable Output Voltage
●180mV Maximum Dropout Voltage
●Programmable On-Chip Active Discharge
LDO Simplified Block Diagram
The LDO has one input (IN_LDO) and one output (LDO)
and several ports that exchange information with the rest
of the device (VREF, EN_LDO, ADE_LDO). VREF comes
from the main bias circuits. EN_LDO and ADE_LDO
are register bits for controlling the enable and active-
discharge feature of the LDO. Refer to the Programmer’s
Guide for more information.
LDO Active Discharge Resistor
The LDO has an active-discharge resistor (RAD_LDO)
that automatically enables/disables based on a configura-
tion bit (ADE_LDO) and the status of the LDO regulator.
Enabling the active discharge feature helps ensure a
complete and timely power down of all system peripherals.
The default condition of the active-discharge resistor fea-
ture is enabled such that whenever VSYS is above VPOR
and VIN_LDO is above 1.0V, the LDO active discharge
resistor is turned on. Note that when VIN_LDO is less than
1.0V, the NMOS transistor that controls the LDO active
discharge resistor loses its gate drive and becomes open.
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dV
DO
LDO Soft-Start
The soft-start feature of the LDO limits inrush current dur-
ing startup. The soft-start feature is achieved by limiting the
slew rate of the output voltage during startup (dV/dtSS).
More output capacitance results in higher input cur-
rent surges during startup. The equation and example
describes the input current surge phenomenon during
startup.
The input current (IIN) during soft-start is:
IIN = CLDO
dV
dtSS
+ ILDO
where CLDO is the capacitance on the output of the regula-
tor, and dV/dtSS is the voltage change rate of the output.
For example, given the following conditions, the input
current (IIN) during soft-start is 22.5mA:
Given:
• CLDO = 10µF
• dV/dtSS = 1.25mV/µs
• RLDO = 185Ω (ILDO = 1.85V/185Ω = 10mA)
Calculation:
• IIN = 10µF x 1.25mV/µs + 10mA
• IIN = 22.5mA
LDO Applications Information
Input and Output Capacitor Selection
Sufficient input bypass capacitance (CIN_LDO) and output
capacitance (CLDO) is required for stable operation of the
LDO. Figure 19 provides guidance on capacitor selection
and refers to required effective capacitance, which is the
actual value of capacitance seen by the LDO during oper-
ation. Effective capacitance is almost always lower than
the nominal capacitance and is a commonly overlooked
design parameter. Determine the effective capacitance
by assessing the capacitor’s initial tolerance, variation
with temperature, and variation with DC bias. Consult the
capacitor manufacturer for specific details of derating.
Choose the input capacitor (CIN_LDO) so that the effective
capacitance is equal to or greater than the value found in
Figure 19, based on expected load conditions for the
application. A single 10μF, 1005/0402 (mm/inch) capaci-
tor, is recommended for typical applications but ensure
that the load current and derated capacitance does not
compromise the stability curve in Figure 19. Larger values
of CIN_LDO improve stability and decoupling for the LDO
regulator. The floorplan of the device is such that SBB0
is adjacent to IN_LDO, and if SBB0 powers the input of
the LDO, then the two nodes can share the SBB0 output
capacitor (CSBB0). CIN_LDO reduces the current peaks
drawn from the battery or input power source during LDO
regulator operation.
Choose the output capacitor (CLDO) so that the effective
capacitance is equal to or greater than the value found
in Figure 19, based on expected load conditions for the
application. A single 10μF, 1005/0402 (mm/inch) capacitor
is recommended for typical applications, but ensure that
the load current and derated capacitance does not com-
promise the stability curve in Figure 19. Larger values of
CLDO improve stability and output PSRR, but increases
the input surge currents during soft-start and output volt-
age changes. The effective output capacitance should not
exceed 100μF to maintain LDO stability.
For example, consider the case of the MAX77650A
where:
1. Size is very important.
2. The LDO input is powered by SBB0, which is 2.05V.
3. The LDO output is 1.85V.
4. The LDO output current is ≤80mA.
A small 1005/0402 (mm/inch) capacitor such as the
GRM155R60J106ME15 (Murata, 10μF, 6.3V X5R) gives
5.7μF at 60°C and 5.4μF at -20°C with the 1.85V bias
voltage and has a ± 20% tolerance, so the worst-case
effective capacitance is 4.3μF (5.4μF derated by 20%
tolerance). With just 4.3μF of capacitance at the output,
Figure 19 shows the LDO is stable with load currents of
≤35mA. To get stability at 80mA, 6μF is required. There
are a few options to consider:
●Add more capacitors to the design.
●Replace the 1005/0402 (mm/inch) capacitor with a
1608/0603 (mm/inch) capacitor.
●Consider point-of-load capacitance in your assess-
ment of effective capacitance. For example, if there
is a point-of-load capacitor downstream from the
LDO that is sufficiently close to the local LDO output
capacitor, it can cover the gap. The capacitor can be
considered “sufficiently close” if the PCB does not
add more than 25nH and 25mΩ of extra ESR and
ESL (more or less within 1”).
Note the impedance of either the input or output capacitor
(ESR, ESL) should be very low (i.e., ≤ 50mΩ + ≤ 5nH) for
frequencies up to 0.5MHz. Ceramic capacitors with X5R
or X7R dielectric are highly recommended due to their
small size, low ESR, and small temperature coefficients.
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EFFECTIVE LDO CAPACITANC EFFECTIVE LDO CAPACITANC
REQUIRED FOR STABILITY REQUIRED FOR STABILITY
OUTPUT CAPACITANCE INPUT CAPACITANCE
Figure 20. LDO Simplified Block Diagram
Figure 19. LDO Capacitance for Stability
0
1
2
3
4
5
6
7
8
025 50 75 100 125 150
EFFECTIVE CAPACITANCE (
μF)
LOAD CURRENT (mA)
OUTPUT CAPACITANCE
EFFECTIVE LDO CAPACITANCE
REQUIRED FOR STABILITY
UNSTABLE REGION
STABLE REGION
0
1
2
3
4
5
6
7
8
025 50 75 100 125 150
EFFECTIVE CAPACITANCE (μF)
LOAD CURRENT (mA)
INPUT CAPACITANCE
EFFECTIVE LDO CAPACITANCE
REQUIRED FOR STABILITY
STABLE REGION
UNSTABLE REGION
IN_LDO
LDO
10µF*
(0402)
10µF
(0402)
150mA
LDO
VREF
EN_LDO
ADE_LDO
R
ADE_LDO
LDO
SBB0
*THE FLOORPLAN IS SUCH
THAT THE SBB0 OUTPUT
CAPACITOR IS ALSO THE
IN_LDO INPUT CAPACITOR.
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[LE H
mm a
CLKJZ
quuu
[Lama u]
may a
CLKJZ
quuu
[Lama u]
luau a
Current Sinks
The device has a 3-channel current sink driver designed
to drive LED's in portable devices. This block can also be
used as a general-purpose current sink driver for other
applications. The driver's on-time and frequency are
independently programmable for each output to achieve
a desired blink pattern. Alternatively, the LEDs can be
continuously on (i.e., not blinking). The blink period is
programmable from 0.5s to 8s,with an on-time duty cycle
from 6.25% to 100%.
Figure 21 utilizes a common set of clock dividers to
drive three identical current sink modules. Refer to the
Programmer’s Guide for more information.
Current Sink Applications Information
LED Assignment
The three current sinks (LED0, LED1, LED2) are identi-
cal. In a typical application where a red, green, blue LED
cluster is used (RGB), the assignment of the RGB ele-
ments to the LED0/1/2 pins should be done in whatever
way makes the PCB layout the easiest.
Unused Current Sink Ports
If a current sink port is not utilized in a given applica-
tion, connect that port to ground. Additionally, software
should ensure that the unused current sink is not enabled
(EN_LEDx = 0).
Figure 21. Current Sink Block Diagram
LED0
LED1
LED2
LGND
D_LED0[3:0]
P_LED0[3:0]
INV_LED0
BRT_LED0[4:0]
2/4/8Ω
CLK_32
EN_LED0
LED_FS0[1:0]
BIAS
CLOCK DIVIDER
AND INVERTER
EN_LED_MSTR
CURRENT SINK
D_LED1[3:0]
P_LED1[3:0]
INV_LED0
BRT_LED1[4:0]
CLK_32
LED_FS1[1:0]
CURRENT SINK
D_LED2[3:0]
P_LED2[3:0]
INV_LED0
BRT_LED24:0]
CLK_32
LED_FS2[1:0]
CURRENT SINK
CLK CLOCK
DIVIDER CLK_64 CLK_32
CLK_64_S
PWM
LOGIC
DAC
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I2C Serial Interface
The MAX77650 features a revision 3.0 I2C-compatible,
2-wire serial interface consisting of a bidirectional serial
data line (SDA) and a serial clock line (SCL). The
MAX77650/MAX77651 act as slave-only devices where
they rely on the master to generate a clock signal. SCL
clock rates from 0Hz to 3.4MHz are supported. I2C is
an open-drain bus, and therefore, SDA and SCL require
pullups. Optional resistors (24Ω) in series with SDA and
SCL protect the device inputs from high-voltage spikes
on the bus lines. Series resistors also minimize crosstalk
and undershoot on bus signals. Figure 22 shows the
functional diagram for the I2C based communications
controller. For additional information on I2C, refer to the
I2C Bus Specification and User Manual that is available
for free on the Internet.
Features
●I2C Revision 3 Compatible Serial Communications
Channel
●0Hz to 100kHz (Standard Mode)
●0Hz to 400kHz (Fast Mode)
●0Hz to 1MHz (Fast Mode Plus)
●0Hz to 3.4MHz (High-Speed Mode)
●Does not utilize I2C Clock Stretching
Figure 22. I2C Simplified Block Diagram
SCL
SDA
INTERFACE
DECODERS
SHIFT REGISTERS
BUFFERS
PERIPHERAL
0
PERIPHERAL
1
PERIPHERAL
2
PERIPHERAL
N-1
PERIPHERAL
N
COMMUNICATIONS CONTROLLER
COM
V
IO
GND
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I2C System Configuration
The I2C bus is a multimaster bus. The maximum number
of devices that can attach to the bus is only limited by bus
capacitance.
A device on the I2C bus that sends data to the bus in
called a transmitter. A device that receives data from the
bus is called a receiver. The device that initiates a data
transfer and generates the SCL clock signals to control
the data transfer is a master. Any device that is being
addressed by the master is considered a slave. The
MAX77650/MAX77651 I2C compatible interface oper-
ates as a slave on the I2C bus with transmit and receive
capabilities.
I2C Interface Power
The MAX77650/MAX77651 I2C interface derives its
power from VIO. Typically a power input such as VIO
would require a local 0.1μF ceramic bypass capacitor to
ground. However, in highly integrated power distribution
systems, a dedicated capacitor might not be necessary. If
the impedance between VIO and the next closest capaci-
tor (≥ 0.1μF) is less than 100mΩ in series with 10nH, then
a local capacitor is not needed. Otherwise, bypass VIO to
GND with a 0.1µF ceramic capacitor.
VIO accepts voltages from 1.7V to 3.6V (VIO). Cycling VIO
does not reset the I2C registers. When VIO is less than
VIOUVLO and VSYS is less than VSYSUVLO, SDA and
SCL are high impedance.
I2C Data Transfer
One data bit is transferred during each SCL clock cycle.
The data on SDA must remain stable during the high
period of the SCL clock pulse. Changes in SDA while SCL
is high are control signals. See the I2C Start and Stop
Conditions section. Each transmit sequence is framed by
a START (S) condition and a STOP (P) condition. Each
data packet is nine bits long: eight bits of data followed by
the acknowledge bit. Data is transferred with the MSB first.
I2C Start and Stop Conditions
When the serial interface is inactive, SDA and SCL idle
high. A master device initiates communication by issuing a
START condition. A START condition is a high-to low tran-
sition on SDA with SCL high. A STOP condition is a low-to-
high transition on SDA, while SCL is high. See Figure 24.
A START condition from the master signals the beginning
of a transmission to the MAX77650/MAX77651. The mas-
ter terminates transmission by issuing a not-acknowledge
followed by a STOP condition. See the I2C Acknowledge
Bit section for information on the not-acknowledge. The
STOP condition frees the bus. To issue a series of com-
mands to the slave, the master can issue repeated start
(Sr) commands instead of a STOP command to maintain
control of the bus. In general, a repeated start command
is functionally equivalent to a regular start command.
When a STOP condition or incorrect address is detected,
the MAX77650/MAX77651 internally disconnect SCL
from the serial interface until the next START condition,
minimizing digital noise and feedthrough.
Figure 23. I2C System Configuration
Figure 24. I2 C Start and Stop Conditions
SLAVE
TRANSMITTER/
RECEIVER
SLAVE
TRANSMITTER
SLAVE
RECEIVER
MASTER
TRANSMITTER/
RECEIVER
MASTER
TRANSMITTER/
RECEIVER
SDA
SCL
S PSr
SCL
SDA
tHD;STA
tSU;STA tSU;STO
tHD;STA
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I2C Acknowledge Bit
Both the I2C bus master and the MAX77650/MAX77651
(slave) generate acknowledge bits when receiving data.
The acknowledge bit is the last bit of each nine bit data
packet. To generate an acknowledge (A), the receiving
device must pull SDA low before the rising edge of the
acknowledge-related clock pulse (ninth pulse) and keep it
low during the high period of the clock pulse. See Figure
25. To generate a not-acknowledge (nA), the receiving
device allows SDA to be pulled high before the rising edge
of the acknowledge-related clock pulse and leaves it high
during the high period of the clock pulse.
Monitoring the acknowledge bits allows for detection
of unsuccessful data transfers. An unsuccessful data
transfer occurs if a receiving device is busy or if a system
fault has occurred. In the event of an unsuccessful data
transfer, the bus master should reattempt communication
at a later time.
The MAX77650/MAX77651 issue an ACK for all register
addresses in the possible address space even if the par-
ticular register does not exist.
I2C Slave Address
The I2C controller implements 7-bit slave addressing. An
I2C bus master initiates communication with the slave
by issuing a START condition followed by the slave
address. See Figure 26. The slave address is factory
programmable to one of two options. See Table 11. All
slave addresses not mentioned in the Table 11 are not
acknowledged.
Figure 26. Slave Address Example
Figure 25. Acknowledge Bit
t
SU;DAT
S
SCL
SDA
1 2 8 9
t
HD;DAT
NOT ACKNOWLEDGE (NA) ACKNOWLEDGE (A)
S
SCL
SDA
123
001
8 9
ACKNOWLEDGE
4567
1 0 0 R/W A0
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I2C Clock Stretching
In general, the clock signal generation for the I2C bus is
the responsibility of the master device. The I2C specifica-
tion allows slow slave devices to alter the clock signal by
holding down the clock line. The process in which a slave
device holds down the clock line is typically called clock
stretching. The MAX77650/MAX77651 do not use any
form of clock stretching to hold down the clock line.
I2C General Call Address
The MAX77650/MAX77651 do not implement the I2C
specifications general call address. If the MAX77650/
MAX77651 see the general call address (0b0000_0000),
they do not issue an acknowledge.
I2C Device ID
The MAX77650/MAX77651 do not support the I2C Device
ID feature.
I2C Communication Speed
The MAX77650/MAX77651 are compatible with all 4 com-
munication speed ranges as defined by the Revision 3
I2C specification:
●0Hz to 100kHz (Standard Mode)
●0Hz to 400kHz (Fast Mode)
●0Hz to 1MHz (Fast Mode)
●0Hz to 3.4MHz (High-Speed Mode)
Operating in standard mode, fast mode, and fast mode
plus does not require any special protocols. The main
consideration when changing the bus speed through
this range is the combination of the bus capacitance and
pullup resistors. Higher time constants created by the bus
capacitance and pullup resistance (C x R) slow the bus
operation. Therefore, when increasing bus speeds, the
pullup resistance must be decreased to maintain a rea-
sonable time constant. Refer to the Pullup Resistor Sizing
section of the I2C Bus Specification and User Manual
that is available for free on the Internet for detailed guid-
ance on the pullup resistor selection. In general for bus
capacitances of 200pF, a 100kHz bus needs 5.6kΩ pullup
resistors, a 400kHz bus needs about a 1.5kΩ pullup resis-
tors, and a 1MHz bus needs 680Ω pullup resistors. Note
that when the open-drain bus is low, the pullup resistor is
dissipating power, lower value pullup resistors dissipate
more power (V2/R).
Operating in high-speed mode requires some special con-
siderations. For a full list of considerations, see the I2C
Communication Speed section. The major considerations
with respect to the MAX77650/MAX77651:
●The I2C bus master use current source pull-ups to
shorten the signal rise.
●The I2C slave must use a different set of input filters
on its SDA and SCL lines to accommodate for the
higher bus.
●The communication protocols need to utilize the high-
speed master code.
At power-up and after each stop condition, the MAX77650/
MAX77651 input filters are set for standard mode, fast
mode, and fast mode plus (i.e., 0Hz to 1MHz). To switch
the input filters for high-speed mode, use the high-speed
master code protocols that are described in the I2C
Communication Protocols section.
ADDRESS 7-BIT SLAVE ADDRESS 8-BIT WRITE ADDRESS 8-BIT READ ADDRESS
Main Address
(ADDR = 1)* 0x48, 0b 100 1000 0x90, 0b 1001 0000 0x91, 0b 1001 0001
Main Address
(ADDR = 0)* 0x40, 0b 100 0000 0x80, 0b 1000 0000 0x81, 0b 1000 0001
Test Mode** 0x49, 0b 100 1001 0x92, 0b 1001 0010 0x93, 0b 1001 0011
*Perform all reads and writes on the Main Address. ADDR is a factory one-time programmable (OTP) option, allowing for address
changes in the event of a bus conflict. Contact Maxim for more information.
**When test mode is unlocked, the additional address is acknowledged. Test mode details are confidential. If possible, leave the test
mode address unallocated to allow for the rare event that debugging needs to be performed in cooperation with Maxim.
Table 11. I2C Slave Address Options
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I2C Communication Protocols
The MAX77650/MAX77651 supports both writing and
reading from its registers.
Writing to a Single Register
Figure 27 shows the protocol for the I2C master device to
write one byte of data to the MAX77650/MAX77651. This
protocol is the same as the SMBus specification’s write
byte protocol.
The write byte protocol is as follows:
●The master sends a start command (S).
●The master sends the 7-bit slave address followed by
a write bit (R/W = 0).
●The addressed slave asserts an acknowledge (A) by
pulling SDA low.
●The master sends an 8-bit register pointer.
●The slave acknowledges the register pointer.
●The master sends a data byte.
●The slave updates with the new data
●The slave acknowledges or not acknowledges
the data byte. The next rising edge on SDA loads
the data byte into its target register and the data
becomes active.
●The master sends a stop condition (P) or a repeated
start condition (Sr). Issuing a P ensures that the bus
input filters are set for 1MHz or slower operation. Issuing
an Sr leaves the bus input filters in their current state.
Figure 27. Writing to a Single Register with the Write Byte Protocol
1
S
NUMBER
OF BITS
R/nW
SLAVE ADDRESS
7
0
1 8
REGISTER POINTER
A
1
A
1 8
DATA A OR NA
1
P OR SR*
1
SLAVE TO MASTERMASTER TO SLAVE
LEGEND
8 9
ACKNOWLEDGE
7
B0 A
B1
THE DATA IS LOADED
INTO THE TARGET
REGISTER AND
BECOMES ACTIVE
DURING THIS RISING
EDGE.
SDA
SCL *P FORCES THE BUS FILTERS TO
SWITCH TO THEIR <=1MHZ MODE.
SR LEAVES THE BUS FILTERS IN
THEIR CURRENT STATE.
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Writing Multiple Bytes to Sequential Registers
Figure 28 shows the protocol for writing to a sequential
registers. This protocol is similar to the write byte proto-
col above, except the master continues to write after it
receives the first byte of data. When the master is done
writing it issues a stop or repeated start.
The writing to sequential registers protocol is as follows:
●The master sends a start command (S).
●The master sends the 7-bit slave address followed by
a write bit (R/W = 0).
●The addressed slave asserts an acknowledge (A) by
pulling SDA low.
●The master sends an 8-bit register pointer.
●The slave acknowledges the register pointer.
●The master sends a data byte.
●The slave acknowledges the data byte. The next ris-
ing edge on SDA load the data byte into its target
register and the data will become active.
●Steps 6 to 7 are repeated as many times as the
master requires.
●During the last acknowledge related clock pulse, the
master can issue an acknowledge or a not acknowledge.
●The master sends a stop condition (P) or a repeated
start condition (Sr). Issuing a P ensures that the bus
input filters are set for 1MHz or slower operation.
Issuing an Sr leaves the bus input filters in their
current state.
Figure 28. Writing to Sequential registers X to N
1
S
NUMBER
OF BITS
R/NW
SLAVE ADDRESS
7
0
1 8
REGISTER POINTER X
A
1
A
1 8
DATA X A
1
NUMBER
OF BITS
8
DATA X+1 A
1 8
DATA X+2 A
1
NUMBER
OF BITS
8
DATA N-1 A
1 8
DATA N
SLAVE TO MASTERMASTER TO SLAVE
LEGEND
8 9
ACKNOWLEDGE
7
B0 A
B1
THE DATA IS LOADED
INTO THE TARGET
REGISTER AND
BECOMES ACTIVE
DURING THIS RISING
EDGE.
SDA
SCL
DETAIL: Α
8 9
ACKNOWLEDGE
7
B0 A
B1
THE DATA IS LOADED
INTO THE TARGET
REGISTER AND
BECOMES ACTIVE
DURING THIS RISING
EDGE.
SDA
SCL
DETAIL: Β
1
B9
Α
Α
Α
Α Β
A OR
NA
1
P OR
SR*
1
*P FORCES THE BUS
FILTERS TO SWITCH
TO THEIR <=1MHZ
MODE. SR LEAVES
THE BUS FILTERS IN
THEIR CURRENT
STATE.
REGISTER POINTER = X + 1 REGISTER POINTER = X + 2
REGISTER POINTER = N-1 REGISTER POINTER = N
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Reading from a Single Register
Figure 29 shows the protocol for the I2C master device to
read one byte of data to the MAX77650/MAX77651. This
protocol is the same as the SMBus specification’s read
byte protocol.
The read byte protocol is as follows:
●The master sends a start command (S).
●The master sends the 7-bit slave address followed by
a write bit (R/W = 0).
●The addressed slave asserts an acknowledge (A) by
pulling SDA low.
●The master sends an 8-bit register pointer.
●The slave acknowledges the register pointer.
●The master sends a repeated start command (Sr).
●The master sends the 7-bit slave address followed by
a read bit (R/W = 1).
●The addressed slave asserts an acknowledge by
pulling SDA low.
●The addressed slave places 8-bits of data on the bus
from the location specified by the register pointer.
●The master issues a not acknowledge (nA).
●The master sends a stop condition (P) or a repeated
start condition (Sr). Issuing a P ensures that the bus
input filters are set for 1MHz or slower operation.
Issuing an Sr leaves the bus input filters in their cur-
rent state.
Note that when the MAX77650/MAX77651 receive a stop
they do not modify their register pointer.
Reading from Sequential Registers
Figure 30 shows the protocol for reading from sequential
registers. This protocol is similar to the read byte protocol
except the master issues an acknowledge to signal the
slave that it wants more data: when the master has all the
data it requires it issues a not acknowledge (nA) and a
stop (P) to end the transmission.
Figure 29. Reading from a Single Register with the Read Byte Protocol
Figure 30. Reading Continuously from Sequential Registers X to N
1
S
R/nW
SLAVE ADDRESS
7
0
1 8
REGISTER POINTER XA
1
A
1 1
Sr SLAVE ADDRESS
7
1
1 8
DATA XA
1
nA
1NUMBER
OF BITS
R/nW
SLAVE TO MASTERMASTER TO SLAVE
LEGEND
1
P or Sr*
*P FORCES THE BUS FILTERS TO SWITCH
TO THEIR <=1MHZ MODE. SR LEAVES THE
BUS FILTERS IN THEIR CURRENT STATE.
1
S
R/NW
SLAVE ADDRESS
7
0
1 8
REGISTER POINTER XA
1
A
11
SR SLAVE ADDRESS
7
1
1 8
DATA XA
1
A
1NUMBER
OF BITS
R/nW
8
DATA X+3 A
1NUMBER
OF BITS
8
DATA X+2 A
1
DATA X+1 A
8 1
8
DATA N NA
1
8
DATA N-1 A
1
DATA N-2 A
8 1
SLAVE TO MASTERMASTER TO SLAVE
LEGEND
NUMBER
OF BITS
1
P OR
SR*
*P FORCES THE BUS FILTERS TO SWITCH TO
THEIR <=1MHZ MODE. SR LEAVES THE BUS
FILTERS IN THEIR CURRENT STATE.
REGISTER POINTER = X + 1 REGISTER POINTER = X + 2 REGISTER POINTER = X + 3
REGISTER POINTER =
N-2
REGISTER POINTER =
N-1
REGISTER POINTER =
N
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noo-
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The continuous read from sequential registers protocol is
as follows:
●The master sends a start command (S).
●The master sends the 7-bit slave address followed by
a write bit (R/W = 0).
●The addressed slave asserts an acknowledge (A) by
pulling SDA low.
●The master sends an 8-bit register pointer.
●The slave acknowledges the register pointer.
●The master sends a repeated start command (Sr).
●The master sends the 7-bit slave address followed
by a read bit (R/W = 1). When reading the RTC time-
keeping registers, secondary buffers are loaded with
the timekeeping register data during this operation.
●The addressed slave asserts an acknowledge by
pulling SDA low.
●The addressed slave places 8-bits of data on the bus
from the location specified by the register pointer.
●The master issues an acknowledge (A) signaling the
slave that it wishes to receive more data.
●Steps 9 to 10 are repeated as many times as the
master requires. Following the last byte of data, the
master must issue a not acknowledge (nA) to signal
that it wishes to stop receiving data.
●The master sends a stop condition (P) or a repeated
start condition (Sr). Issuing a stop (P) ensures that
the bus input filters are set for 1MHz or slower opera-
tion. Issuing an Sr leaves the bus input filters in their
current state.
Note that when the MAX77650/MAX77651 receive a stop,
they do not modify their register pointers.
Engaging HS-mode for operation up to 3.4MHz
Figure 31 shows the protocol for engaging HS-mode
operation. HS-mode operation allows for a bus operating
speed up to 3.4MHz.
The engaging HS mode protocol is as follows:
●Begin the protocol while operating at a bus speed of
1MHz or lower
●The master sends a start command (S).
●The master sends the 8-bit master code of 0b0000
1XXX where 0bXXX are don’t care bits.
●The addressed slave issues a not acknowledge (nA).
●The master may now increase its bus speed up to
3.4MHz and issue any read/write operation.
The master can continue to issue high-speed read/write
operations until a stop (P) is issued. To continue opera-
tions in high speed mode, use repeated start (Sr).
Figure 31. Engaging HS Mode
1
S HS-MASTER CODE
8
nA
1 1
SR
SLAVE TO MASTERMASTER TO SLAVE
LEGEND
FAST-MODE HS-MODE
ANY R/W PROTOCOL
FOLLOWED BY SR SR ANY R/W PROTOCOL
FOLLOWED BY SR SR ANY READ/WRITE
PROTOCOL P
FAST-MODE
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MAX77650/MAX77651 Ultra-Low Power PMIC with 3-Output SIMO
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PWR_HLD
GPIO
4.7µF
25V
(0603)
CHGIN VSYS
SYS
BATT
+LITHIUM ION
BATTERY
THM
GND
VSYS IN_SBB
PGND VSBB0
SBB0
VSBB1
SBB1
L
1.5µH
CSYS
22µF/6.3V
(0603)
LXA
LXB
VIO
SDA
SCL
nIRQ
VSBB0
IN_LDO
VLDO
LDO
10µF
6.3V
(0402)
nEN nRST
VL
1µF
10V
(0402)
VSBB2
SBB2
10µF
6.3V
(0402)
LGND
LED0
LED1
LED2
PROCESSOR
VIO/POWER
4.7µF
6.3V
(0603)
BIAS
AMUX
AMUX ADC INPUT
BST
TBIAS
MAX77650/MAX77651
LITHIUM ION BATTERY CHARGER
T
SIMO BUCK-BOOST
LDO
CURRENT
SINKS
SUCH AS:
SYS, BATT, SBB2
ANALOG
MULTIPLEXER
I2C
GPIO
TOP LEVEL
CBST
3300pF/6.3V
(0201)
PWR_HLD
nRST
SDA
SCL
nIRQ
SYSTEM
RESOURCES
GPIO
AMUX
GPIO
*
*
*THE PROCESSOR HAS INTERNAL
PULLUP RESISTORS FOR NRST AND
NIRQ.
DC CHARGING SOURCE
Typical Application Circuit
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PART TEMP RANGE PIN-PACKAGE OPTIONS
MAX77650EWV+T* -40°C to +85°C 30 WLP Samples with various OTP options
MAX77650AEWV+T -40°C to +85°C 30 WLP SBB0/SBB1/SBB2 values 2.05V/1.2V/3.3V,
production device, DIDM = 0b00, CID = 0b0011**
MAX77650BEWV+T -40°C to +85°C 30 WLP SBB0/SBB1/SBB2 values 1.8V/1.2V/3.15V, production device,
DIDM = 0b00, CID = 0b1110**
MAX77650CEWV+T -40°C to +85°C 30 WLP SBB0/SBB1/SBB2 values 1.8V/1.0V/1.2V,
production device, DIDM = 0b00, CID = 0b1010**
MAX77650MEWV+T -40°C to +85°C 30 WLP SBB0/SBB1/SBB2 values 1.8V/1.2V/3.15V, production device,
DIDM = 0b00, CID = 0b1000**
MAX77651EWV+T* -40°C to +85°C 30 WLP Samples with various OTP options
MAX77651AEWV+T -40°C to +85°C 30 WLP SBB0/SBB1/SBB2 values 1.8V/4.6V/3.6V,
production device, DIDM = 0b01, CID = 0b0110**
MAX77651BEWVA+T -40°C to +85°C 30 WLP SBB0/SBB1/SBB2 values 1.9V/3.2V/5.2V,
production device, DIDM = 0b01, CID = 0b1000**
+Denotes a lead(Pb)-free/RoHS-compliant package.
T = Tape and reel.
*Custom samples only. Not for production or stock. Contact factory for more information.
**See the Programmer’s Guide for the options associated with a specified DIDM and CID.
Ordering Information
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REVISION
NUMBER
REVISION
DATE DESCRIPTION PAGES
CHANGED
0 2/17 Initial release —
1 5/17
Updated Electrical Characteristics—SIMO Buck-Boost table, Typical Operating
Characteristics, Table 1. Regulator Summary, Manual Reset in Features and Benefits
section, Inductor Selection section, and LDO Applications Information section, added
new Figure 19, removed future product notation from MAX77651AEWV+T in Ordering
Information table
1, 9, 19, 25,
26, 30, 32, 36,
38, 65, 68, 79
2 6/17 Updated solution size in Benefits and Features section, updated Absolute Maximum
Ratings section and Figure 18 1, 7, 63
3 7/17
Fixed typos, added common conditions to Electrical Characteristics tables, updated
Typical Operating Characteristics, updated Figure 19, updated Typical Application
Circuit
7, 10−12, 17,
18, 20, 21, 24,
30, 36, 68, 69,
79
4 7/17 Added hyperlink to Programmer’s Guide, added MAX77650CEWV+ to Ordering
Information table
21, 37, 40, 52,
55, 56, 59, 62,
65, 68, 71, 81
5 7/18 Updated various sections, added and removed part numbers to Ordering Information
table
1, 7, 17-19, 23,
26, 27, 33, 35,
36, 39-42, 44,
48-51, 61, 65,
66, 68, 72, 74,
77, 78, 80, 82
6 7/18 Updated Ordering Information table 81
7 9/18 Updated Ordering Information table 81
Revision History
Maxim Integrated cannot assume responsibility for use of any circuitry other than circuitry entirely embodied in a Maxim Integrated product. No circuit patent licenses
are implied. Maxim Integrated reserves the right to change the circuitry and specifications without notice at any time. The parametric values (min and max limits)
shown in the Electrical Characteristics table are guaranteed. Other parametric values quoted in this data sheet are provided for guidance.
Maxim Integrated and the Maxim Integrated logo are trademarks of Maxim Integrated Products, Inc. © 2018 Maxim Integrated Products, Inc.
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For pricing, delivery, and ordering information, please contact Maxim Direct at 1-888-629-4642, or visit Maxim Integrated’s website at www.maximintegrated.com.
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