Datenblatt für STD3LN80K5 von STMicroelectronics

K ’I hiegugmented TAB / L23 DPAK
July 2016
DocID027714 Rev 2
1/15
This is information on a product in full production.
www.st.com
STD3LN80K5
N-channel 800 V, 2.75 Ω typ., 2 A MDmesh™ K5
Power MOSFET in a DPAK package
Datasheet - production data
Figure 1: Internal schematic diagram
Features
Order code
RDS(on) max
ID
STD3LN80K5
800 V
3.25 Ω
2 A
Industry’s lowest RDS(on) x area
Industry’s best FoM (figure of merit)
Ultra-low gate charge
100% avalanche tested
Zener-protected
Applications
Switching applications
Description
This very high voltage N-channel Power
MOSFET is designed using MDmesh™ K5
technology based on an innovative proprietary
vertical structure. The result is a dramatic
reduction in on-resistance and ultra-low gate
charge for applications requiring superior power
density and high efficiency.
Table 1: Device summary
Order code
Marking
Package
Packing
STD3LN80K5
3LN80K5
DPAK
Tape and reel
D(2, TAB)
G(1)
S(3)
AM01476v1
Contents
STD3LN80K5
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DocID027714 Rev 2
Contents
1 Electrical ratings ............................................................................. 3
2 Electrical characteristics ................................................................ 4
2.1 Electrical characteristics (curves) ...................................................... 6
3 Test circuits ..................................................................................... 8
4 Package information ....................................................................... 9
4.1 DPAK package information ............................................................... 9
4.2 DPAK packing information .............................................................. 12
5 Revision history ............................................................................ 14
STD3LN80K5
Electrical ratings
DocID027714 Rev 2
3/15
1 Electrical ratings
Table 2: Absolute maximum ratings
Symbol
Parameter
Value
Unit
VGS
Gate-source voltage
± 30
V
ID
Drain current (continuous) at TC = 25 °C
2
A
ID
Drain current (continuous) at TC = 100 °C
1.25
A
ID(1)
Drain current (pulsed)
8
A
PTOT
Total dissipation at TC = 25 °C
45
W
dv/dt (2)
Peak diode recovery voltage slope
4.5
V/ns
dv/dt (3)
MOSFET dv/dt ruggedness
50
Tstg
Storage temperature range
- 55 to 150
°C
Tj
Operating junction temperature range
Notes:
(1)Pulse width limited by safe operating area.
(2)ISD ≤ 2 A, di/dt ≤ 100 A/µs; VDSpeak < V(BR)DSS, VDD = 640 V
(3)VDS ≤ 640 V.
Table 3: Thermal data
Symbol
Parameter
Value
Unit
Rthj-case
Thermal resistance junction-case
2.78
°C/W
Rthj-pcb(1)
Thermal resistance junction-pcb
50
°C/W
Notes:
(1)When mounted on 1inch² FR-4 board, 2 oz Cu.
Table 4: Avalanche characteristics
Symbol
Parameter
Value
Unit
IAR
Avalanche current, repetitive or not repetitive (pulse width limited by Tjmax)
0.7
A
EAS
Single pulse avalanche energy (starting Tj = 25°C, ID = IAR; VDD = 50 V)
155
mJ
Electrical characteristics
STD3LN80K5
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DocID027714 Rev 2
2 Electrical characteristics
(TC = 25 °C unless otherwise specified)
Table 5: On /off states
Symbol
Parameter
Test conditions
Min.
Typ.
Max.
Unit
V(BR)DSS
Drain-source breakdown
voltage
ID = 1 mA, VGS = 0 V
800
V
IDSS
Zero gate voltage
drain current
VDS = 800 V, VGS = 0 V
1
µA
VDS = 800 V, VGS = 0 V,
TC = 125 °C(1)
50
µA
IGSS
Gate body leakage
current
VGS = ± 20 V, VGS = 0 V
±10
µA
VGS(th)
Gate threshold voltage
VDS = VGS, ID = 100 µA
3
4
5
V
RDS(on)
Static drain-source
on-resistance
VGS = 10 V, ID = 1 A
2.75
3.25
Ω
Notes:
(1)Defined by design, not subject to production test.
Table 6: Dynamic
Symbol
Parameter
Test conditions
Min.
Typ.
Max.
Unit
Ciss
Input capacitance
VDS = 100 V, f = 1 MHz,
VGS = 0 V
-
102
-
pF
Coss
Output capacitance
-
11
-
pF
Crss
Reverse transfer capacitance
-
0.1
-
pF
Cotr(1)
Equivalent capacitance time
related
VDS = 0 to 640 V, VGS = 0 V
-
20
-
pF
Coer(2)
Equivalent capacitance
energy related
-
7
-
pF
RG
Intrinsic gate resistance
f = 1 MHz, ID = 0 A
-
12
-
Ω
Qg
Total gate charge
VDD = 640 V, ID = 2 A,
VGS = 10 V ( see Figure 15:
"Test circuit for gate charge
behavior" )
-
2.63
-
nC
Qgs
Gate-source charge
-
0.91
-
nC
Qgd
Gate-drain charge
-
1.53
-
nC
Notes:
(1)Time related is defined as a constant equivalent capacitance giving the same charging time as Coss when VDS
increases from 0 to 80% VDSS
(2)Energy related is defined as a constant equivalent capacitance giving the same stored energy as Coss when VDS
increases from 0 to 80% VDSS
STD3LN80K5
Electrical characteristics
DocID027714 Rev 2
5/15
Table 7: Switching times
Symbol
Parameter
Test conditions
Min.
Typ.
Max.
Unit
td(on)
Turn-on delay time
VDD = 400 V, ID = 1 A, RG = 4.7 Ω,
VGS = 10 V ( see Figure 14: "Test
circuit for resistive load switching
times" and Figure 19: "Switching
time waveform" )
-
6.2
-
ns
tr
Rise time
-
7
-
ns
td(off)
Turn-off delay time
-
30
-
ns
tf
Fall time
-
26
-
ns
Table 8: Source drain diode
Symbol
Parameter
Test conditions
Min.
Typ.
Max.
Unit
ISD
Source-drain current
-
2
A
ISDM(1)
Source-drain current
(pulsed)
-
8
A
VSD(2)
Forward on voltage
ISD = 2 A, VGS = 0 V
-
1.5
V
trr
Reverse recovery time
ISD = 2 A, di/dt = 100 A/µs,
VDD = 60 V ( see Figure 16: "Test
circuit for inductive load
switching and diode recovery
times" )
-
210
ns
Qrr
Reverse recovery
charge
-
0.8
µC
IRRM
Reverse recovery
current
-
7.6
A
trr
Reverse recovery time
ISD = 2 A, di/dt = 100 A/µs,
VDD = 60 V, Tj = 150 °C, (see
Figure 16: "Test circuit for
inductive load switching and
diode recovery times" )
-
345
ns
Qrr
Reverse recovery
charge
-
1.2
µC
IRRM
Reverse recovery
current
-
7.2
A
Notes:
(1)Pulse width limited by safe operating area.
(2)Pulsed: pulse duration = 300 µs, duty cycle 1.5%.
Table 9: Gate-source Zener diode
Symbol
Parameter
Test conditions
Min.
Typ.
Max.
Unit
V(BR)GSO
Gate-source breakdown voltage
IGS = ± 1 mA, ID = 0 A
30
-
-
V
The built-in back-to-back Zener diodes are specifically designed to enhance the ESD
performance of the device. The Zener voltage facilitates efficient and cost-effective device
integrity protection, thus eliminating the need for additional external componentry.
9: um 10" |,= IODus F 1m: 10‘ g=1oms T,s15u 'c 1: we sing‘e pmse 102 1o" 10“ 10‘ 1o2 10’ “M as (VD 7 a s 10 vssw) (V) 600 500 400 300 200 100 a (n0) Rnslw (D) 325 2 75 2.5 225 0.5 1 1.5 ID (A)
Electrical characteristics
STD3LN80K5
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DocID027714 Rev 2
2.1 Electrical characteristics (curves)
Figure 2: Safe operating area
Figure 3: Thermal impedance
Figure 4: Output characteristics
Figure 5: Transfer characteristics
Figure 6: Gate charge vs gate-source
voltage
Figure 7: Static drain-source on-resistance
KCG34360
c
10-4 10-3 10-2 10-1 tp (s)
10-5
10-1
10-2
100
(PF) 10I 1o2 10‘ T‘=150“C 1 ‘5» (A) chm) (norm ) 12 08 06 0.4 775 Rnsm (norm ) 2 s 2 2 1.23 1.4 06 0.2 775 725 25 75 125 T, (”c) VIBRDSS (Harm > 1 DE 104 096 092 use (m) 150 120 60 Smg‘e pmsa \D=D7A‘ vnn=sov 0 -75 -25 25 75 125 T, (”C) E]
STD3LN80K5
Electrical characteristics
DocID027714 Rev 2
7/15
Figure 8: Capacitance variations
Figure 9: Source-drain diode forward
characteristics
Figure 10: Normalized gate threshold voltage
vs temperature
Figure 11: Normalized on-resistance vs
temperature
Figure 12: Normalized V(BR)DSS vs
temperature
Figure 13: Maximum avalanche energy vs
starting TJ
22cm vfl 4‘ W »_4 -‘ i. J, L 4 vwm W L W n 0,. V“ 7 m a#m \ K17
Test circuits
STD3LN80K5
8/15
DocID027714 Rev 2
3 Test circuits
Figure 14: Test circuit for resistive load
switching times
Figure 15: Test circuit for gate charge
behavior
Figure 16: Test circuit for inductive load
switching and diode recovery times
Figure 17: Unclamped inductive load test
circuit
Figure 18: Unclamped inductive waveform
Figure 19: Switching time waveform
AM01469v10
47 kΩ
2.7 kΩ
1 kΩ
IG= CONST 100 Ω D.U.T.
+
pulse width
VGS
2200
μF
VG
VDD
RL
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STD3LN80K5
Package information
DocID027714 Rev 2
9/15
4 Package information
In order to meet environmental requirements, ST offers these devices in different grades of
ECOPACK® packages, depending on their level of environmental compliance. ECOPACK®
specifications, grade definitions and product status are available at: www.st.com.
ECOPACK® is an ST trademark.
4.1 DPAK package information
Figure 20: DPAK (TO-252) type A package outline
0068772_A_21
Package information
STD3LN80K5
10/15
DocID027714 Rev 2
Table 10: DPAK (TO-252) type A mechanical data
Dim.
mm
Min.
Typ.
Max.
A
2.20
2.40
A1
0.90
1.10
A2
0.03
0.23
b
0.64
0.90
b4
5.20
5.40
c
0.45
0.60
c2
0.48
0.60
D
6.00
6.20
D1
4.95
5.10
5.25
E
6.40
6.60
E1
4.60
4.70
4.80
e
2.16
2.28
2.40
e1
4.40
4.60
H
9.35
10.10
L
1.00
1.50
(L1)
2.60
2.80
3.00
L2
0.65
0.80
0.95
L4
0.60
1.00
R
0.20
V2
0°
8°
‘ c w Humming;
STD3LN80K5
Package information
DocID027714 Rev 2
11/15
Figure 21: DPAK (TO-252) recommended footprint (dimensions are in mm)
1-: mm cumlillvn mhmrmmlam H-nlmm m F01 mxhirlmfiflrly In Fl m mumm am: am mummmm —> —’ Harding rdius AMOGESZVI
Package information
STD3LN80K5
12/15
DocID027714 Rev 2
4.2 DPAK packing information
Figure 22: DPAK (TO-252) tape outline
40mm mil. mess hole at SIG locaticll Tape sto‘ 'n one br tape 5hr! 25mm mllI,Ildm G manned numb AMDSOGBM
STD3LN80K5
Package information
DocID027714 Rev 2
13/15
Figure 23: DPAK (TO-252) reel outline
Table 11: DPAK (TO-252) tape and reel mechanical data
Tape
Reel
Dim.
mm
Dim.
mm
Min.
Max.
Min.
Max.
A0
6.8
7
A
330
B0
10.4
10.6
B
1.5
B1
12.1
C
12.8
13.2
D
1.5
1.6
D
20.2
D1
1.5
G
16.4
18.4
E
1.65
1.85
N
50
F
7.4
7.6
T
22.4
K0
2.55
2.75
P0
3.9
4.1
Base qty.
2500
P1
7.9
8.1
Bulk qty.
2500
P2
1.9
2.1
R
40
T
0.25
0.35
W
15.7
16.3
Revision history
STD3LN80K5
14/15
DocID027714 Rev 2
5 Revision history
Table 12: Document revision history
Date
Revision
Changes
13-May-2015
1
Initial release
27-Jul-2016
2
Updated title and features in cover page.
Updated Section 1: "Electrical ratings" and Section 2: "Electrical
characteristics".
Added Section 2.1: "Electrical characteristics (curves)".
Document status promoted from preliminary to production data.
Minor text changes.
STD3LN80K5
DocID027714 Rev 2
15/15
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