Datenblatt für LDBL20 von STMicroelectronics

‘ ’ I hieaugmen'ed /"‘> \/ STSTAMPW (U.47x0.47) mm2 /
Features
• Input voltage from 1.5 to 5.5 V
• Ultra low dropout voltage (200 mV typ. at 200 mA load)
• Very low quiescent current (20 µA typ. at no-load, 0.03 µA typ. in off mode)
• Output voltage tolerance: ± 1.5% @ 25 °C
• 200 mA guaranteed output current
• High PSRR (80 dB@1 kHz, 50 db@100 kHz)
• Wide range of output voltages available on request: from 0.8 V up to 5.0 V in 50
mV step
• Logic-controlled electronic shutdown
• Internal soft-start
• Optional output voltage discharge feature
• Compatible with ceramic capacitor COUT = 0.47 µF
• Internal constant current and thermal protections
• Available in STSTAMP™ (0.47 x 0.47) mm² package
• Operating temperature range: -40 °C to 125 °C
Applications
• Mobile phones
• Tablet
• Digital still cameras (DSC)
• Wearable devices
• Portable media players
Description
The LDBL20 high accuracy voltage regulator provides 200 mA of maximum current
from an input voltage ranging from 1.5 V to 5.5 V, with a typical dropout voltage of
200 mV.
It is available in the new STSTAMP™ package, allowing the maximum space saving.
The device is stabilized with a ceramic capacitor on the output. The ultra low drop
voltage, low quiescent current and low noise features, together with the internal soft-
start circuit, make the LDBL20 suitable for low power battery-operated applications.
An enable logic control function puts the LDBL20 in shutdown mode with a total
current consumption lower than 0.2 µA. Constant current and thermal protection are
provided.
Maturity status link
LDBL20
200 mA very low quiescent current linear regulator IC in (0.47x0.47) mm²
STSTAMP™ package
LDBL20
Datasheet
DS11244 - Rev 3 - January 2021
For further information contact your local STMicroelectronics sales office.
www.st.com
t- —Z§
1Diagram
Figure 1. Block diagram
AM13852V1
VIN
GND
VOUT
OPAMP
Bias
generator
Bandgap
reference
EN
Thermal
protection
Enable
*
Note: The output discharge MOSFET is optional.
LDBL20
Diagram
DS11244 - Rev 3 page 2/22
2Pin configuration
Figure 2. Pin connection
3 4
2 1
VIN
VOUT
EN
GND
Bottom view Marking view
1
2
3
4
#
EN
GND
VIN
VOUT
AMG110520171240MT
Note: "#" indicates the marking digit. Refer to Table 7. Order code. The top horizontal bar identifies pin 1 on top right
corner.
Table 1. Pin description
Pin Symbol Function
3 OUT Output voltage
4 GND Common ground
1 EN Enable pin logic input: low = shutdown, high = active
2 IN Input voltage
LDBL20
Pin configuration
DS11244 - Rev 3 page 3/22
EN I||—¢— g
3Typical application
Figure 3. Typical application circuits
VIN
G ND
VI
E N
CIn
VO
VOUT
COut
L DB L 20
OFF
ON
GIPD310820151119MT
LDBL20
Typical application
DS11244 - Rev 3 page 4/22
4Maximum ratings
Table 2. Absolute maximum ratings
Symbol Parameter Value Unit
VIN Input voltage - 0.3 to 7 V
VOUT Output voltage - 0.3 to VIN + 0.3 V
VEN Enable input voltage - 0.3 to 7 V
IOUT Output current Internally limited mA
PDPower dissipation Internally limited mW
TSTG Storage temperature range - 40 to 150 °C
TOP Operating junction temperature range - 40 to 125 °C
Note: Absolute maximum ratings are those values beyond which damage to the device may occur. Functional
operation under these conditions is not implied. All values are referred to GND.
Table 3. ESD performance
Symbol Parameter Test conditions Value Unit
ESD ESD protection voltage
HBM 4 kV
MM 400 V
CDM 500 V
Table 4. Thermal performance
Symbol Parameter Value Unit
RthJA Thermal resistance junction-ambient 230 °C/W
LDBL20
Maximum ratings
DS11244 - Rev 3 page 5/22
5Electrical characteristics
TJ = 25 °C, VIN = VOUT(NOM) + 1 V or 1.5 V, whichever is greater, CIN = COUT = 1 µF, IOUT = 1 mA, VEN = VIN,
unless otherwise specified.
Table 5. LDBL20 electrical characteristics
Symbol Parameter Test conditions Min. Typ. Max. Unit
VIN Operating input voltage 1.5 5.5 V
VOUT VOUT accuracy
IOUT = 1 mA, TJ = 25 °C -1.5 +1.5 %
IOUT = 1 mA,
-40 °C<TJ<125 °C -3 +3 %
∆VOUT Static line regulation (1)
VOUT(NOM) + 1 V ≤ VIN ≤ 5.5 V, IOUT = 10
mA 0.02
%/V
-40 °C<TJ<125 °C 0.2
∆VOUT Static load regulation
IOUT = 0 mA to 200 mA 10 mV
-40 °C<TJ<125 °C 0.01 %/mA
VDROP Dropout voltage
IOUT = 30 mA,VOUT = 2.8 V 35
mV
IOUT = 200 mA, VOUT = 2.8 V
-40 °C<TJ<125 °C 200 350
eNOutput noise voltage 10 Hz to 100 kHz, IOUT = 10 mA 45 µVRMS/VOUT
SVR Supply voltage rejection
VIN = VOUT(NOM)+ 1 V +/- VRIPPLE
VRIPPLE = 0.2 V Frequency =1 kHz
IOUT = 30 mA
80
dB
VIN = VOUT(NOM)+ 1 V +/- VRIPPLE
VRIPPLE = 0.2 V Frequency = 100 kHz
IOUT = 30 mA
55
IQQuiescent current
IOUT = 0 mA 20 40
µA
IOUT = 200 mA 100
IStandby Standby current VIN input current in OFF mode:
VEN = GND 0.03 0.2 µA
ISC Short-circuit current RL = 0 250 350 mA
RON Output voltage discharge
MOSFET 100 Ω
VEN
Enable input logic low
VIN = 1.5 V to 5.5 V
-40 °C<TJ<125 °C 0.4
V
Enable input logic high
VIN = 1.5 V to 5.5 V
-40 °C<TJ<125 °C 1
IEN Enable pin input current VEN = VIN 100 nA
TON (2) Turn-on time 100 µs
TSHDN
Thermal shutdown 160
°C
Hysteresis 20
LDBL20
Electrical characteristics
DS11244 - Rev 3 page 6/22
Symbol Parameter Test conditions Min. Typ. Max. Unit
COUT Output capacitor Capacitance 0.47 22 µF
1. Not applicable for Vout(nom) > 4.5 V
2. Turn-on time is time measured between the enable input just exceeding VEN high value and the output voltage just reaching
95 % of its nominal value
LDBL20
Electrical characteristics
DS11244 - Rev 3 page 7/22
6Application information
6.1 Soft-start function
The LDBL20 has an internal soft-start circuit. By increasing the startup time up to 100 µs, without the need of any
external soft-start capacitor, this feature keeps the regulator inrush current at startup under control.
6.2 Output discharge function
The LDBL20 integrates a MOSFET connected between VOUT and GND. This transistor is activated when the
EN pin goes to low logic level and has the function to quickly discharge the output capacitor when the device is
disabled by the user.
The device is available with or without the auto-discharge feature. See Table 7. Order code.
6.3 Input and output capacitors
The LDBL20 requires external capacitors to assure the regulator control loop stability.
Any good quality ceramic capacitor can be used but, the X5R and the X7R are suggested since they guarantee a
very stable combination of capacitance and ESR overtemperature.
Locating the input/output capacitors as closer as possible to the relative pins is recommended.
The LDBL20 requires an input capacitor with a minimum value of 1 μF.
This capacitor must be located as closer as possible to the input pin of the device and returned to a clean analog
ground.
The control loop of the LDBL20 is designed to work with an output ceramic capacitor.
This capacitor must meet the requirements of minimum capacitance and equivalent series resistance (ESR), as
shown in Figure 17. Stability area vs (COUT, ESR). To assure stability, the output capacitor must maintain its ESR
and capacitance in the stable region, over the full operating temperature range.
The LDBL20 shows stability with a minimum effective output capacitance of 220 nF.
However, to keep stability in all operating conditions (temperature, input voltage and load variations), a minimum
output capacitor of 0.47 µF is recommended.
The suggested combination of 1 μF input and output capacitors offers a good compromise among the stability of
the regulator, optimum transient response and total PCB area occupation.
LDBL20
Application information
DS11244 - Rev 3 page 8/22
a. m m n. 332 a: m m m 322 :rz AM13855V1 AM13856V1 n 2 m 0 IS cos u m 0‘ an: — a a: o as E o m a u a .1 a :12 a 1 n a: a 64 4; n5 0 2 4: as mum". 'c] vwaz w :0": u m zoom AM13857V1 AM13858VI
7Typical characteristics
(CIN = COUT = 1 µF, VEN to VIN, TJ = 25 °C unless otherwise specified)
Figure 4. Output voltage vs temp. (I OUT = 1 mA)
AM13855V1
-40 -25 0 25 55 85 125
Output Voltage [V]
Temperature [ °C]
VIN = 4.3 V, IOUT = 1 mA
Figure 5. Output voltage vs temp. (I OUT = 200 mA)
AM13856V1
3.2
3.22
3.24
3.26
3.28
3.3
3.32
3.34
3.36
3.38
3.4
-40 -25 0 25 55 85 125
Output Voltage [V]
Temperature [ °C]
VIN=4.3V, IOUT=200mA
Figure 6. Line regulation vs temperature
AM13857V1
-0.15
-0.05
Line reg ulation [%/V]
Temperature [ °C]
VIN = 4.3 V to 5.5 V, IOUT = 10 mA
Figure 7. Load regulation vs temperature
Load regulation
LDBL20
Typical characteristics
DS11244 - Rev 3 page 9/22
AM13859V1 AM13860V1 AM 1 3862V1
Figure 8. Quiescent current vs temp. (IOUT = 0 mA)
AM13859V1
0
5
10
15
20
25
30
35
40
45
50
-40 -25 0 25 55 85 125
Quiesce nt current [µA]
Temperature [ °C]
VIN = 4.3 V, IOUT = 0 mA
Figure 9. Quiescent current vs temp. (IOUT = 200 mA)
AM13860V1
0
20
40
60
80
100
120
140
160
180
200
-40 -25 0 25 55 85 125
Quiescent current [µA]
Temperature [ °C]
VIN=4.3V, IOUT= 200mA
Figure 10. Shutdown current vs temperature
AM13861V1
0
0.1
0.2
0.3
0.4
0.5
0.6
0.7
0.8
0.9
1
-40 -25 0 25 55 85 125
Quiescent curr ent [µA]
Temperature [°C]
VIN = V, VEN = GND
Figure 11. Quiescent current vs load current
AM13862V1
VIN=2V, VOUT=1V
0
20
40
60
80
100
120
140
160
0 0.02 0.04 0.06 0.08 0.1 0.12 0.14 0.16 0.18 0.2
Quiescent current [µA]
Output current [A]
Figure 12. Quiescent current vs input voltage
AM13863V1
VIN
= 2 V, V OUT
= 1 V
0
10
20
30
40
50
60
70
80
90
100
0 1 2 3 4 5 6
Quiescent current [µA]
Input voltage [V]
Iout = 0 mA
Iout = 1 mA
Iout = 10 mA
Figure 13. Dropout voltage vs temperature
AM13864V1
0
25
50
75
100
125
150
175
200
225
250
275
-40 -25 0 25 55 85 125
Dropout voltage [mV]
Temperature [
°
C]
Iout = 30 mA
Iout = 50 mA
Iout = 100 mA
Iout = 200 mA
LDBL20
Typical characteristics
DS11244 - Rev 3 page 10/22
Figure 14. Supply voltage rejection vs frequency
AM13865V1
V
IN
= 2 V +/
-
200 m
V, V
OUT = 1 V, C OUT = 1 µF
0
10
20
30
40
50
60
70
80
90
100
100 1000 10000 100000 1000000
SVR [dB]
Frequency [Hz]
Iout = 1 mA
Iout = 30 mA
Iout = 100 mA
Iout = 200 mA
Figure 15. Supply voltage rejection vs input voltage
AM13866V1
I
OUT = 30mA
, V
OUT
=
1 V
, C
OUT = 1 µF
0
10
20
30
40
50
60
70
80
90
1 1.5 2 2.5 3 3.5 4 4.5 5 5.5 6
SVR [dB]
Input voltage [V]
f
= 1 kHz
f
= 10 kHz
f
= 100 kHz
Figure 16. Output noise spectral density
AM13867V1
V
IN
= 2.
0 V,
V
OUT
=
1.0 V,
C
IN
= C
OUT = 1 µF
0.0
0.5
1.0
1.5
2.0
2.5
3.0
3.5
4.0
10 100 1000 10000 100000
eN
[
uV / SQRT(Hz)]
Frequency [Hz]
Iout = 0 mA
Iout = 10 mA
Figure 17. Stability area vs (COUT, ESR)
AM13868V1
0
0.2
0.4
0.6
0.8
1
1.2
1.4
0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23
ESR @ 100KHz[Ω]
C
OUT [µF] (nominal value)
STABILITY AREA
VIN
from 2 to 5.5 V,
I
OUT from 0 to 300 mA,
C
IN = 1 µF
Figure 18. Enable startup (VOUT = 1 V)
AM13869V1
V
IN = 2 V
,
VEN = 0 V to V IN
, I
OUT = 0.2 A ,
V
OUT =1 V,
Tr
= 5 µs
VEN
VOUT
IOUT
Figure 19. Enable startup (VOUT = 5 V)
AM13870V1
V
IN = 5.5 V ,
V
EN = 0 V to 2 V, I OUT = 0.2A
, V
OUT = 5 V,
Tr
= 5 µs
VEN
VOUT
IOUT
LDBL20
Typical characteristics
DS11244 - Rev 3 page 11/22
“bra? :r-w AM1aa73VI
Figure 20. Turn-on time (VOUT = 1 V)
AM13871V1
V
IN = V EN = from 0 V to 5.5 V, I OUT = 0.2 A
, V
OUT = 1 V,
Tr
= 5 µs
VIN
VOUT
IOUT
Figure 21. Turn-off time (VOUT = 1 V)
AM13872V1
V
IN = V EN = from 5.5 V to 0 V, I OUT = 0.2 A
, V
OUT = 1 V,
Tf
= 5 µs
VIN
VOUT
IOUT
Figure 22. Turn-on time (VOUT = 5 V)
VI N
VO U T
IO U T
V
IN = V EN = from 0 V to 5.5 V, I OUT = 0.2A
, V
OUT = 5 V,
Tr
= 5 µs
AM13873V1
Figure 23. Turn-off time (VOUT = 5 V)
VI N
VO U T
IO U T
V
IN = V EN = from 5.5 V to 0 V, I OUT = 0.2 A
, V
OUT = 5 V,
Tf
= 5 µs
AM13874V1
Figure 24. Line transient (VOUT = 1 V)
VI N
VO U T
V
IN
= V
EN = from 2 V to 3 V , I OUT = 10 mA
, V
OUT = 1 V,
Tr= Tf
= 5 µs
AM13875V1
Figure 25. Line transient (VOUT = 5 V)
VI N
VO U T
V
IN
= V
EN = from 5.1 V to 5.5 V, I OUT = 10 mA
, V
OUT = 5 V,
Tr=Tf
= 5 µs
AM13876V1
LDBL20
Typical characteristics
DS11244 - Rev 3 page 12/22
Figure 26. Load transient (V OUT = 1 V)
VO U T
IO U T
V
IN
= V
EN = 2 V,
I
OUT = from 0 to 0.2 A
, V
OUT = 1 V,
tr=tf
= 5 µs
AM13877V1
Figure 27. Load transient (V OUT = 5 V)
VO U T
IO U T
V
IN
= V
EN = 5.5 V,
I
OUT = from 0 to 0.2 A
, V
OUT = 5 V,
tr= tf
= 5 µs
AM13878V1
LDBL20
Typical characteristics
DS11244 - Rev 3 page 13/22
8Recommendation on PCB assembly
8.1 PCB design recommendations
• PCB PAD design: non solder mask defined
• PCB pad size: see drawing in Figure 30. STSTAMP™ (0.47x0.47) mm² recommended footprint
• Solder mask opening: 50 μm between the edge of the pad and the edge of the solder mask
• To keep under control the solder paste amount, closed vias are recommended instead of open vias
• The position of tracks and open vias in the solder area should be well balanced. A symmetrical layout is
recommended, to reduce the effect of tilt phenomena caused by asymmetrical solder paste amount due to
the solder flowing away
8.2 Stencil
• Stencil aperture: see drawing in Figure 31. STSTAMP™ (0.47x0.47) mm² recommended solder stencil
• Stencil thickness: 75 μm
8.3 Solder paste
• 95.8% Sn, 3.5% Ag, 0.7% Cu solder paste
• Halide-free flux qualification ROL0 according to ANSI/J-STD-004
• “No clean” solder paste is recommended.
• Offers a high tack force to resist component movement during high speed
• Solder paste with fine particles: powder particle size is 20-45 μm.• type 4
8.4 Placement
• Manual positioning is not recommended
• It is recommended to use the lead recognition capabilities of the placement system, not the outline centering
• Standard tolerance of ± 0.05 mm is recommended
• 3.5 N placement force is recommended. Too much placement force can lead to squeezed out solder paste
and cause solder joints to short. Too low placement force can lead to insufficient contact between package
and solder paste that could cause open solder joints or badly centered packages
• To improve the package placement accuracy, a bottom side optical control should be performed with a high
resolution tool
• For assembly, a perfect supporting of the PCB (all the more on flexible PCB) is recommended during solder
paste printing, pick and place and reflow soldering by using optimized tools
LDBL20
Recommendation on PCB assembly
DS11244 - Rev 3 page 14/22
A a 40—245 QC 250 Temperature( C) ‘ W 9-3 d zoo _._._._. ----- ._._._._ _. SOsec "— / (90max) \Efil 150 / 6 "CE W, / \g E9 “C/s \ so Tlme (s) o co m m m 2 o 2 2% : menuszom 34cm
8.5 Reflow profile
Figure 28. ST ECOPACK® recommended soldering reflow profile for PCB mounting
Note: Minimize air convection currents in the reflow oven to avoid component movement. Maximum soldering profile
corresponds to the latest IPC/JEDEC J-STD-020.
LDBL20
Reflow profile
DS11244 - Rev 3 page 15/22
9Package information
In order to meet environmental requirements, ST offers these devices in different grades of ECOPACK packages,
depending on their level of environmental compliance. ECOPACK specifications, grade definitions and product
status are available at: www.st.com. ECOPACK is an ST trademark.
LDBL20
Package information
DS11244 - Rev 3 page 16/22
D1 FD E2 ‘7 D2 mu
9.1 STSTAMP™ (0.47x0.47) mm² package information
Figure 29. STSTAMP™ (0.47x0.47) mm² package outline
LDBL20
STSTAMP™ (0.47x0.47) mm² package information
DS11244 - Rev 3 page 17/22
Table 6. STSTAMP™ (0.47x0.47) mm² mechanical data
Dim.
mm
Min. Typ. Max.
A0.18 0.200 0.220
b 0.060 0.065 0.070
b1 0.109 0.114 0.119
E 0.450 0.480 0.510
E1 0.208 0.213 0.218
E2 0.019 0.024 0.029
E3 0.034 0.039 0.044
D 0.450 0.480 0.510
D1 0.252 0.257 0.262
D2 0.255 0.260 0.265
fE 0.095 0.101 0.106
fD 0.106 0.111 0.116
Figure 30. STSTAMP™ (0.47x0.47) mm² recommended footprint
0.25 0.25
0.1
0.25 0.25
0.1
Figure 31. STSTAMP™ (0.47x0.47) mm² recommended solder stencil
180 µm 180 µm
120 µm
180 µm 180 µm
120 µm
LDBL20
STSTAMP™ (0.47x0.47) mm² package information
DS11244 - Rev 3 page 18/22
10 Order code
Table 7. Order code
Order code Output voltage (V) Auto-discharge Marking Packing
LDBL20D-11 (1) 1.1
Yes Tape and reel
LDBL20D-12 1.2 D
LDBL20D-18R 1.8 A
LDBL20D-25R 2.5 B
LDBL20D-33R 3.3 C
1. Available on request.
10.1 Marking information
Figure 32. Marking composition (marking view)
1
2
3
4
#
EN
GND
VIN
VOUT
AMG110520171241MT
Note: The symbol "#" indicates the marking digit, as per Table 7. Order code.
LDBL20
Order code
DS11244 - Rev 3 page 19/22
Revision history
Table 8. Document revision history
Date Revision Changes
10-Nov-2015 1 Initial release
02-Aug-2017 2
Updated Section 2: "Pin configuration", Table 5: "LDBL20 electrical
characteristics ".
Added Section 8: "Recommendation on PCB assembly".
Updated Section 10: "Ordering information".
Minor text changes.
27-Jan-2021 3 Added new order codes in Table 7.
LDBL20
DS11244 - Rev 3 page 20/22
Contents
1Diagram ...........................................................................2
2Pin configuration ..................................................................3
3Typical application.................................................................4
4Maximum ratings ..................................................................5
5Electrical characteristics...........................................................6
6Application information............................................................8
6.1 Soft-start function ..............................................................8
6.2 Output discharge function .......................................................8
6.3 Input output capacitors ..........................................................8
7Typical characteristics .............................................................9
8Recommendation on PCB assembly ..............................................14
8.1 PCB design recommendations ..................................................14
8.2 Stencil.......................................................................14
8.3 Solder paste..................................................................14
8.4 Placement ...................................................................14
8.5 Reflow profile .................................................................15
9Package information..............................................................16
9.1 STSTAMP™ (0.47x0.47) mm² package information .................................17
10 Ordering information .............................................................19
10.1 Marking information ...........................................................19
Revision history .......................................................................20
LDBL20
Contents
DS11244 - Rev 3 page 21/22
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LDBL20
DS11244 - Rev 3 page 22/22