Datenblatt für MSP430FR263x,253x von Texas Instruments

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An IMPORTANT NOTICE at the end of this data sheet addresses availability, warranty, changes, use in safety-critical applications,

intellectual property matters and other important disclaimers. PRODUCTION DATA.

MSP430FR2633, MSP430FR2632, MSP430FR2533, MSP430FR2532

SLAS942E –NOVEMBER 2015–REVISED DECEMBER 2019

MSP430FR263x, MSP430FR253x Capacitive Touch Sensing Mixed-Signal Microcontrollers

1 Device Overview

1.1 Features

•CapTIvate™ technology – capacitive touch

– Performance

– Fast electrode scanning with four

simultaneous scans

– Support for high-resolution sliders with up to

1024 points

– Proximity sensing

– Reliability

– Increased immunity to power line, RF, and

other environmental noise

– Built-in spread spectrum, automatic tuning,

noise filtering, and debouncing algorithms

– Enables reliable touch solutions with 10-V

RMS common-mode noise, 4-kV electrical

fast transients, and 15-kV electrostatic

discharge, allowing for IEC‑61000-4-6,

IEC‑61000-4-4, and IEC‑61000-4-2

compliance

– Reduced RF emissions to simplify electrical

designs

– Support for metal touch and water rejection

designs

– Flexibility

– Up to 16 self-capacitance and 64 mutual-

capacitance electrodes

– Mix and match self- and mutual-capacitive

electrodes in the same design

– Supports multitouch functionality

– Wide range of capacitance detection, wide

electrode range of 0 to 300 pF

– Low power

– <5 µA wake-on-touch with four sensors

– Wake-on-touch state machine allows

electrode scanning while CPU is asleep

– Hardware acceleration for environmental

compensation, filtering, and threshold

detection

– Ease of use

–CapTIvate Design Center PC GUI lets

engineers design and tune capacitive buttons

in real time without having to write code

– CapTIvate software library in ROM provides

ample FRAM for customer application

• Embedded microcontroller

– 16-bit RISC architecture

– Clock supports frequencies up to 16 MHz

– Wide supply voltage range from 3.6 V down to

1.8 V (minimum supply voltage is restricted by

SVS levels, see the SVS specifications)

• Optimized ultra-low-power modes

– Active mode: 126 µA/MHz (typical)

– Standby: <5 µA wake-on-touch with four

sensors

– LPM3.5 real-time clock (RTC) counter with

32768-Hz crystal: 730 nA (typical)

– Shutdown (LPM4.5): 16 nA (typical)

• High-performance analog

– 8-channel 10-bit analog-to-digital converter

(ADC)

– Internal 1.5-V reference

– Sample-and-hold 200 ksps

• Enhanced serial communications

– Two enhanced universal serial communication

interfaces (eUSCI_A) support UART, IrDA, and

SPI

– One eUSCI (eUSCI_B) supports SPI and I2C

• Intelligent digital peripherals

– Four 16-bit timers

– Two timers with three capture/compare

registers each (Timer_A3)

– Two timers with two capture/compare

registers each (Timer_A2)

– One 16-bit timer associated with CapTIvate

technology

– One 16-bit counter-only RTC

– 16-bit cyclic redundancy check (CRC)

• Low-power ferroelectric RAM (FRAM)

– Up to 15.5KB of nonvolatile memory

– Built-in error correction code (ECC)

– Configurable write protection

– Unified memory of program, constants, and

storage

– 1015 write cycle endurance

– Radiation resistant and nonmagnetic

– High FRAM-to-SRAM ratio, up to 4:1

l TEXAS INSTRUMENTS

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SLAS942E –NOVEMBER 2015–REVISED DECEMBER 2019

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Product Folder Links: MSP430FR2633 MSP430FR2632 MSP430FR2533 MSP430FR2532

• Clock system (CS)

– On-chip 32-kHz RC oscillator (REFO)

– On-chip 16-MHz digitally controlled oscillator

(DCO) with frequency-locked loop (FLL)

– ±1% accuracy with on-chip reference at room

temperature

– On-chip very low-frequency 10-kHz oscillator

(VLO)

– On-chip high-frequency modulation oscillator

(MODOSC)

– External 32-kHz crystal oscillator (LFXT)

– Programmable MCLK prescalar of 1 to 128

– SMCLK derived from MCLK with programmable

prescalar of 1, 2, 4, or 8

• General input/output and pin functionality

– Total of 19 I/Os on TSSOP-32 package

– 16 interrupt pins (P1 and P2) can wake MCU

from low-power modes

• Development tools and software

– Development tools

– MSP CapTIvate™ MCU development kit

evaluation: use with CAPTIVATE-PGMR

programmer and capacitive touch

MSP430FR2633 MCU board

CAPTIVATE‑FR2633

– Target development board

(MSP‑TS430RGE24A)

– Ease-of-use ecosystem

–CapTIvate Design Center – code generation,

customizable GUI, real-time tuning

• Family members (also see Device Comparison)

– MSP430FR2633: 15KB of program FRAM,

512 bytes of information FRAM, 4KB of RAM,

up to 16 self-capacitive or 64 mutual-capacitive

sensors

– MSP430FR2533: 15KB of program FRAM,

512 bytes of information FRAM, 2KB of RAM,

up to 16 self-capacitive or 24 mutual-capacitive

sensors

– MSP430FR2632: 8KB of program FRAM,

512 bytes of information FRAM, 2KB of RAM,

up to 8 self-capacitive or 16 mutual-capacitive

sensors

– MSP430FR2532: 8KB of program FRAM,

512 bytes of information FRAM, 1KB of RAM,

up to 8 self-capacitive or 8 mutual-capacitive

sensors

• Package options

– 32 pin: VQFN (RHB)

– 32 pin: TSSOP (DA)

– 24 pin: VQFN (RGE)

– 24-pin: DSBGA (YQW)

1.2 Applications

• Electronic smart locks, door keypads, and readers

• Garage door systems

• Intrusion HMI keypads and control panels

• Motorized window blinds

• Remote controls

• Personal electronics

• Wireless speakers and headsets

• Handheld video game controllers

• A/V receivers

• White goods

• Small appliances

• Garden and power tools

1.3 Description

The MSP430FR263x and MSP430FR253x are ultra-low-power MSP430™ microcontrollers for capacitive

touch sensing that feature CapTIvate™ touch technology for buttons, sliders, wheels, and proximity

applications. MSP430 MCUs with CapTIvate technology provide the most integrated and autonomous

capacitive-touch solution in the market with high reliability and noise immunity at the lowest power. TI's

capacitive touch technology supports concurrent self-capacitance and mutual-capacitance electrodes on

the same design for maximum flexibility. MSP430 MCUs with CapTIvate technology operate through thick

glass, plastic enclosures, metal, and wood with operation in harsh environments including wet, greasy,

and dirty environments.

TI capacitive touch sensing MSP430 MCUs are supported by an extensive hardware and software

ecosystem with reference designs and code examples to get your design started quickly. Development

kits include the MSP-CAPT-FR2633 CapTIvate technology development kit. TI also provides free software

including the CapTIvate Design Center, where engineers can quickly develop applications with an easy-to-

use GUI and MSP430Ware™ software and comprehensive documentation with the CapTIvate Technology

Guide.

l TEXAS INSTRUMENTS

MSP430FR2633, MSP430FR2632, MSP430FR2533, MSP430FR2532

www.ti.com

SLAS942E –NOVEMBER 2015–REVISED DECEMBER 2019

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Product Folder Links: MSP430FR2633 MSP430FR2632 MSP430FR2533 MSP430FR2532

TI's MSP430 ultra-low-power (ULP) FRAM microcontroller platform combines uniquely embedded FRAM

and a holistic ultra-low-power system architecture, allowing system designers to increase performance

while lowering energy consumption. FRAM technology combines the low-energy fast writes, flexibility, and

endurance of RAM with the nonvolatility of flash.

For complete module descriptions, see the MSP430FR4xx and MSP430FR2xx Family User's Guide.

(1) For the most current part, package, and ordering information, see the Package Option Addendum in

Section 9, or see the TI website at www.ti.com.

(2) The sizes shown here are approximations. For the package dimensions with tolerances, see the

Mechanical Data in Section 9.

Device Information(1)

PART NUMBER PACKAGE BODY SIZE(2)

MSP430FR2633IRHB VQFN (32) 5 mm × 5 mm

MSP430FR2533IRHB VQFN (32) 5 mm × 5 mm

MSP430FR2633IDA TSSOP (32) 11 mm × 6.2 mm

MSP430FR2533IDA TSSOP (32) 11 mm × 6.2 mm

MSP430FR2632IRGE VQFN (24) 4 mm × 4 mm

MSP430FR2532IRGE VQFN (24) 4 mm × 4 mm

MSP430FR2633IYQW DSBGA (24) 2.29 mm × 2.34 mm

MSP430FR2632IYQW DSBGA (24) 2.29 mm × 2.34 mm

CAUTION

System-level ESD protection must be applied in compliance with the device-

level ESD specification to prevent electrical overstress or disturbing of data or

code memory. See MSP430 System-Level ESD Considerations for more

information.

l TEXAS INSTRUMENTS

DVCC

RST/NMI

XIN XOUT P3.xP1.x/P2.x

DVSS

I/O Ports

P1, P2

2×8 IOs

Interrupt

and Wakeup

1×16 IOs

ADC

Up to 8-ch

single-ended

10 bit

200 ksps

Clock

System

LFXT FRAM

15KB+512B

8KB+512B

RAM

4KB

2KB

Watchdog

SYS

CRC16

16-bit

Cyclic

Redundancy

Check

CapTIvate

16-channel

8-channel

JTAG

SBW

I/O Ports

1×3 IOs

2×TA

Timer_A3

3 CC

Registers

EEM

MAB

MDB

16-MHz CPU

including

16 Registers

Power

Management

Module

MPY32

32-bit

Hardware

Multiplier

2×eUSCI_A

(UART,

IrDA, SPI)

eUSCI_B0

(SPI, I C)

RTC

Counter

16-bit

Real-Time

Clock

2×TA

Timer_A2

2 CC

Registers

VREG

BAKMEM

32-byte

Backup

Memory

LPM3.5 Domain

SBWTDIO

SBWTCK

TDO

TDI/TCLK

TMS

TCK

MSP430FR2633, MSP430FR2632, MSP430FR2533, MSP430FR2532

SLAS942E –NOVEMBER 2015–REVISED DECEMBER 2019

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1.4 Functional Block Diagram

Figure 1-1 shows the functional block diagram.

Figure 1-1. Functional Block Diagram

• The MCU has one main power pair of DVCC and DVSS that supplies digital and analog modules.

Recommended bypass and decoupling capacitors are 4.7 µF to 10 µF and 0.1 µF, respectively, with

±5% accuracy.

• VREG is the decoupling capacitor of the CapTIvate regulator. The recommended value for the required

decoupling capacitor is 1 µF, with a maximum ESR of ≤200 mΩ.

• P1 and P2 feature the pin interrupt function and can wake the MCU from all LPMs, including LPM3.5

and LPM4.

• Each Timer_A3 has three capture/compare registers. Only CCR1 and CCR2 are externally connected.

CCR0 registers can be used only for internal period timing and interrupt generation.

• Each Timer_A2 has two capture/compare registers. Both registers can be used only for internal period

timing and interrupt generation.

• In LPM3 mode, the CapTIvate module can be functional while the rest of the peripherals are off.

l TEXAS INSTRUMENTS \cnmx um

MSP430FR2633, MSP430FR2632, MSP430FR2533, MSP430FR2532

www.ti.com

SLAS942E –NOVEMBER 2015–REVISED DECEMBER 2019

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Product Folder Links: MSP430FR2633 MSP430FR2632 MSP430FR2533 MSP430FR2532

Table of Contents

1 Device Overview ......................................... 1

1.1 Features .............................................. 1

1.2 Applications........................................... 2

1.3 Description............................................ 2

1.4 Functional Block Diagram ............................ 4

2 Revision History ......................................... 6

3 Device Comparison ..................................... 8

3.1 Related Products ..................................... 8

4 Terminal Configuration and Functions.............. 9

4.1 Pin Diagrams ......................................... 9

4.2 Pin Attributes........................................ 13

4.3 Signal Descriptions.................................. 16

4.4 Pin Multiplexing ..................................... 19

4.5 Buffer Types......................................... 19

4.6 Connection of Unused Pins ......................... 19

5 Specifications........................................... 20

5.1 Absolute Maximum Ratings......................... 20

5.2 ESD Ratings ........................................ 20

5.3 Recommended Operating Conditions............... 20

5.4 Active Mode Supply Current Into VCC Excluding

External Current..................................... 21

5.5 Active Mode Supply Current Per MHz .............. 21

5.6 Low-Power Mode LPM0 Supply Currents Into VCC

Excluding External Current.......................... 21

5.7 Low-Power Mode (LPM3 and LPM4) Supply

Currents (Into VCC) Excluding External Current .... 22

5.8 Low-Power Mode LPMx.5 Supply Currents (Into

VCC) Excluding External Current.................... 23

5.9 Typical Characteristics - Low-Power Mode Supply

Currents ............................................. 24

5.10 Thermal Resistance Characteristics ................ 25

5.11 Timing and Switching Characteristics............... 26

6 Detailed Description ................................... 45

6.1 Overview ............................................ 45

6.2 CPU ................................................. 45

6.3 Operating Modes.................................... 45

6.4 Interrupt Vector Addresses.......................... 47

6.5 Bootloader (BSL).................................... 48

6.6 JTAG Standard Interface............................ 49

6.7 Spy-Bi-Wire Interface (SBW)........................ 49

6.8 FRAM................................................ 49

6.9 Memory Protection .................................. 49

6.10 Peripherals .......................................... 50

6.11 Input/Output Diagrams .............................. 60

6.12 Device Descriptors .................................. 67

6.13 Memory.............................................. 68

6.14 Identification......................................... 76

7 Applications, Implementation, and Layout........ 77

7.1 Device Connection and Layout Fundamentals...... 77

7.2 Peripheral- and Interface-Specific Design

Information .......................................... 80

7.3 CapTIvate Technology Evaluation .................. 83

8 Device and Documentation Support ............... 84

8.1 Getting Started and Next Steps..................... 84

8.2 Device Nomenclature ............................... 84

8.3 Tools and Software ................................. 85

8.4 Documentation Support ............................. 87

8.5 Related Links........................................ 88

8.6 Community Resources.............................. 88

8.7 Trademarks.......................................... 88

8.8 Electrostatic Discharge Caution..................... 89

8.9 Export Control Notice ............................... 89

8.10 Glossary............................................. 89

9 Mechanical, Packaging, and Orderable

Information .............................................. 90

l TEXAS INSTRUMENTS ww—t

MSP430FR2633, MSP430FR2632, MSP430FR2533, MSP430FR2532

SLAS942E –NOVEMBER 2015–REVISED DECEMBER 2019

www.ti.com

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Product Folder Links: MSP430FR2633 MSP430FR2632 MSP430FR2533 MSP430FR2532

2 Revision History

NOTE: Page numbers for previous revisions may differ from page numbers in the current version.

Changes from revision D to revision E

Changes from August 20, 2019 to December 9, 2019 Page

• Changed the note that begins "Supply voltage changes faster than 0.2 V/µs can trigger a BOR reset..." in

Section 5.3,Recommended Operating Conditions ............................................................................. 20

• Added the note that begins "TI recommends that power to the DVCC pin must not exceed the limits..." in

Section 5.3,Recommended Operating Conditions ............................................................................. 20

• Changed the note that begins "A capacitor tolerance of ±20% or better is required..." in Section 5.3,

Recommended Operating Conditions ............................................................................................ 20

• Changed the note that begins "Requires external capacitors at both terminals..." in Table 5-4,XT1 Crystal

Oscillator (Low Frequency) ........................................................................................................ 28

• Added the t(int) parameter in Table 5-10,Digital Inputs ........................................................................ 32

• Added the tTA,cap parameter in Table 5-13,Timer_A............................................................................ 34

• Corrected the test conditions for the RI,MUX parameter in Table 5-20,ADC, Power Supply and Input Range

Conditions ............................................................................................................................ 40

• Added the note that begins "tSample = ln(2n+1) × τ..." in Table 5-21,ADC, 10-Bit Timing Parameters.................... 40

• Moved CREG and CELECTRODE from Section 5.3,Recommended Operating Conditions to Table 5-23,CapTIvate

Electrical Characteristics ........................................................................................................... 42

• Changed the CRC covered end address to 0x1AF5 in note (1) in Table 6-22,Device Descriptors ..................... 67

Changes from revision C to revision D

Changes from August 29, 2018 to August 19, 2019 Page

• Updated Section 1.1,Features ..................................................................................................... 1

• Added "Target development board" information in Section 1.1,Features .................................................... 2

• Changed "fCONVER = 2 MHz" to "fCONVER = 4 MHz" in the note that begins "CapTIvate technology works in LPM3

with 64 mutual-capacitance buttons" on Section 5.7,Low-Power Mode (LPM3 and LPM4) Supply Currents (Into

VCC) Excluding External Current .................................................................................................. 22

• Added the tTA,cap parameter in Table 5-13,Timer_A............................................................................ 34

• Changed the parameter symbol from RIto RI,MUX in Table 5-20 ,ADC, Power Supply and Input Range Conditions .40

• Added RI,Misc TYP value of 34 kΩin Table 5-20 ,ADC, Power Supply and Input Range Conditions ................... 40

• Added formula for RIcalculation in Table 5-21 ,ADC, 10-Bit Timing Parameters ......................................... 40

• Removed the description of "±3°C" in table note that starts "The device descriptor structure ..." of Table 5-22,

ADC, 10-Bit Linearity Parameters................................................................................................. 41

• Moved CREG and CELECTRODE from Section 5.3,Recommended Operating Conditions to Table 5-23,CapTIvate

Electrical Characteristics ........................................................................................................... 42

• Added test condition for CELECTRODE in Table 5-23 ,CapTIvate Electrical Characteristics................................. 42

• Changed the symbol and description of the DCCAPCLK parameter in Table 5-23,CapTIvate Electrical

Characteristics ...................................................................................................................... 42

• Moved the SNR parameter to Table 5-24,CapTIvate Signal-to-Noise Ratio Characteristics ............................ 42

• Corrected bitfield from IRDSEL to IRDSSEL in Section 6.10.8,Timers (Timer0_A3, Timer1_A3, Timer2_A2 and

Timer3_A2), in the description that starts "The interconnection of Timer0_A3 and ..." .................................... 56

• Corrected the ADCINCHx column heading in Table 6-15,ADC Channel Connections ................................... 58

• Corrected the ADCSHSx column heading in Table 6-16,ADC Trigger Signal Connections.............................. 58

• Added P1SELC information in Table 6-32,Port P1, P2 Registers (Base Address: 0200h) .............................. 71

• Added P2SELC information in Table 6-32,Port P1, P2 Registers (Base Address: 0200h) .............................. 71

• Added P3SELC information in Table 6-33,Port P3 Registers (Base Address: 0220h) ................................... 71

• Updated Section 7.2.2,CapTIvate Peripheral .................................................................................. 81

l TEXAS INSTRUMENTS qgwgwmm‘ w W" m N M"? g _. u WW" " " o on m‘w‘mmxm‘mwwwwd PM” a m m ‘ m m

MSP430FR2633, MSP430FR2632, MSP430FR2533, MSP430FR2532

www.ti.com

SLAS942E –NOVEMBER 2015–REVISED DECEMBER 2019

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Changes from revision B to revision C

Changes from June 9, 2017 to August 28, 2018 Page

• Removed "30-cm" from the "Proximity Sensing" item in Section 1.1,Features ............................................. 1

• Updated Section 3.1,Related Products ........................................................................................... 8

• Corrected package type in VQFN row (changed from QFN to VQFN) in Table 4-2,Signal Descriptions .............. 18

• Changed HBM limit to ±1000 V and CDM limit to ±250 V in Section 5.2,ESD Ratings .................................. 20

• Added note to VSVSH- and VSVSH+ parameters in Table 5-2,PMM, SVS and BOR.......................................... 26

• Added the tTA,cap parameter in Table 5-13,Timer_A............................................................................ 34

• Moved CREG and CELECTRODE from Section 5.3,Recommended Operating Conditions to Table 5-23,CapTIvate

Electrical Characteristics ........................................................................................................... 42

• Added the SNR parameter in Table 5-23,CapTIvate Electrical Characteristics ........................................... 42

• Moved "FRAM access time error" to "System Reset" row and added ACCTEIFG to interrupt flag column in

Table 6-2,Interrupt Sources, Flags, and Vectors............................................................................... 47

• Corrected the offset for P2SEL1 in Table 6-32,Port P1, P2 Registers (Base Address: 0200h) ......................... 71

• Updated text and figure in Section 8.2,Device Nomenclature................................................................ 84

Changes from revision A to revision B

Changes from December 10, 2015 to June 8, 2017 Page

• Changed the organization of the Features list .................................................................................... 1

• Added DSBGA (YQW) package to "Package Options" list in Section 1.1,Features ........................................ 2

• Updated list in Section 1.2,Applications........................................................................................... 2

• Updated Section 1.3,Description................................................................................................... 2

• Added DSBGA (YQW) package option to Device Information table in Section 1.3,Description........................... 3

• Added MSP430FR2633IYQW and MSP430FR2632IYQW to Table 3-1,Device Comparison............................. 8

• Added Section 3.1,Related Products.............................................................................................. 8

• Added DSBGA (YQW) pinout ..................................................................................................... 12

• Added DSBGA (YQW) package to Table 4-1,Pin Attributes.................................................................. 13

• Added DSBGA (YQW) package to Table 4-2,Signal Descriptions........................................................... 16

• Added row for VQFN thermal pad in Table 4-2,Signal Descriptions......................................................... 18

• Removed FRAM reflow note....................................................................................................... 20

• Updated the notes on ILPM3, CapTIvate, 16 buttons and ILPM3, CapTIvate, 64 buttons in Section 5.7,Low-Power Mode (LPM3

and LPM4) Supply Currents (Into VCC) Excluding External Current ......................................................... 22

• Added DSBGA (YQW) package and changed notes for Section 5.10,Thermal Resistance Characteristics........... 25

• Added the tTA,cap parameter in Table 5-13,Timer_A............................................................................ 34

• Removed ADCDIV from the formula for the TYP value in the second row of the tCONVERT parameter in Table 5-

21,ADC, 10-Bit Timing Parameters (removed because ADCCLK is after division)........................................ 40

• Moved CREG and CELECTRODE from Section 5.3,Recommended Operating Conditions to Table 5-23,CapTIvate

Electrical Characteristics ........................................................................................................... 42

• Add description of blank device detection ....................................................................................... 48

• Changed the paragraph that starts "Quickly switching digital signals and ..." in Section 7.2.1.2,Design

Requirements........................................................................................................................ 80

• Updated Figure 8-1,Device Nomenclature ...................................................................................... 84

• Replaced former section Development Tools Support with Section 8.3,Tools and Software ............................ 85

• Updated format and content of Section 8.4,Documentation Support........................................................ 87

Changes from initial release to revision A

Changes from November 6, 2015 to December 9, 2015 Page

• Changed document status from PRODUCT PREVIEW to PRODUCTION DATA ........................................... 1

• Changed list item that starts "Enables Reliable Touch Solutions..." ........................................................... 1

• Added note to list item that starts "Wide Supply Voltage Range..." ........................................................... 1

• In the note that starts "Low-power mode 3, VLO, excludes SVS test conditions...", changed "fXT1 = 0 Hz" to

"fXT1 = 32768 Hz" .................................................................................................................... 22

l TEXAS INSTRUMENTS

MSP430FR2633, MSP430FR2632, MSP430FR2533, MSP430FR2532

SLAS942E –NOVEMBER 2015–REVISED DECEMBER 2019

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Product Folder Links: MSP430FR2633 MSP430FR2632 MSP430FR2533 MSP430FR2532

• Added note that starts "The VLO clock frequency is reduced by 15%...".................................................... 31

• Added the tTA,cap parameter in Table 5-13,Timer_A............................................................................ 34

• Moved CREG and CELECTRODE from Section 5.3,Recommended Operating Conditions to Table 5-23,CapTIvate

Electrical Characteristics ........................................................................................................... 42

• Added note to "Clock" in Table 6-1,Operating Modes......................................................................... 46

• Added note that starts "XT1CLK and VLOCLK can be active during LPM4..." ............................................. 46

• Corrected description in Section 6.10.10,Backup Memory (BKMEM) ....................................................... 57

l TEXAS INSTRUMENTS

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SLAS942E –NOVEMBER 2015–REVISED DECEMBER 2019

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(1) For the most current package and ordering information, see the Package Option Addendum in Section 9, or see the TI website at

www.ti.com

(2) Package drawings, standard packing quantities, thermal data, symbolization, and PCB design guidelines are available at

www.ti.com/packaging

(3) A CCR register is a configurable register that provides internal and external capture or compare inputs, or internal and external PWM

outputs.

(4) Eight dedicated CapTIvate channels are included.

(5) Four dedicated CapTIvate channels are included.

(6) Two dedicated CapTIvate channels are included.

3 Device Comparison

Table 3-1 summarizes the features of the available family members.

Table 3-1. Device Comparison(1)(2)

DEVICE PROGRAM FRAM

+ INFORMATION

FRAM (BYTES)

SRAM

(BYTES) TA0 TO TA3 eUSCI_A eUSCI_B 10-BIT ADC

CHANNELS CapTIvate™

CHANNELS GPIOs PACKAGE

TYPE

UART SPI

MSP430FR2633IRHB 15360 + 512 4096 2, 3 × CCR(3)

2, 2 × CCR up to 2 up to 2 1 8 16(4) 19 32 RHB

(VQFN)

MSP430FR2533IRHB 15360 + 512 2048 2, 3 × CCR(3)

2, 2 × CCR up to 2 up to 2 1 8 16(4) 19 32 RHB

(VQFN)

MSP430FR2633IDA 15360 + 512 4096 2, 3 × CCR(3)

2, 2 × CCR up to 2 up to 2 1 8 16(4) 19 32 DA

(TSSOP)

MSP430FR2533IDA 15360 + 512 2048 2, 3 × CCR(3)

2, 2 × CCR up to 2 up to 2 1 8 16(4) 19 32 DA

(TSSOP)

MSP430FR2632IRGE 8192 + 512 2048 2, 3 × CCR(3)

2, 2 × CCR up to 2 1 1 8 8(5) 15 24 RGE

(VQFN)

MSP430FR2532IRGE 8192 + 512 1024 2, 3 × CCR(3)

2, 2 × CCR up to 2 1 1 8 8(5) 15 24 RGE

(VQFN)

MSP430FR2633IYQW 15360 + 512 4096 2, 3 × CCR(3)

2, 2 × CCR up to 2 1 1 8 8(6) 17 24 YQW

(DSBGA)

MSP430FR2632IYQW 8192 + 512 2048 2, 3 × CCR(3)

2, 2 × CCR up to 2 1 1 8 8(6) 17 24 YQW

(DSBGA)

3.1 Related Products

For information about other devices in this family of products or related products, see the following links.

TI 16-bit and 32-bit microcontrollers

High-performance, low-power solutions to enable the autonomous future

Products for MSP430 ultra-low-power sensing & measurement MCUs

One platform. One ecosystem. Endless possibilities.

Companion products for MSP430FR2633

Review products that are frequently purchased or used with this product.

Reference designs for MSP430FR2633

Find reference designs leveraging the best in TI technology – from analog and power management to

embedded processors

‘5‘ TEXAS INSTRUMENTS

RST/NMI/SBWTDIO

TEST/SBWTCK

P1.4/UCA0TXD/UCA0SIMO/TA1.2/TCK/A4/VREF+

P1.5/UCA0RXD/UCA0SOMI/TA1.1/TMS/A5

P1.6/UCA0CLK/TA1CLK/TDI/TCLK/A6

P1.7/UCA0STE/SMCLK/TDO/A7

P1.0/UCB0STE/TA0CLK/A0/Veref+

P1.1/UCB0CLK/TA0.1/A1

P1.2/UCB0SIMO/UCB0SDA/TA0.2/A2/Veref-

P1.3/UCB0SOMI/UCB0SCL/MCLK/A3

P2.2/SYNC/ACLK

P3.0/CAP0.0

CAP0.1

P2.3/CAP0.2

CAP0.3

P3.1/UCA1STE/CAP1.0

P2.4/UCA1CLK/CAP1.1

P2.5/UCA1RXD/UCA1SOMI/CAP1.2

P2.6/UCA1TXD/UCA1SIMO/CAP1.3

VREG

CAP2.0

CAP2.1

CAP2.2

CAP2.3

P2.7/CAP3.0

CAP3.1

P3.2/CAP3.2

CAP3.3

P2.0/XOUT

P2.1/XIN

DVSS

DVCC

MSP430FR2633IRHB

MSP430FR2533IRHB

9 10 11 12 13 14

272829303132

15 16

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4 Terminal Configuration and Functions

4.1 Pin Diagrams

Figure 4-1 shows the pinout for the 32-pin RHB package.

Figure 4-1. 32-Pin RHB Package (Top View)

*9 TEXAS INSTRUMENTS DDDDDDDDDDDDDDDD o EEEEEEEEEEEEEEEE

P3.2/CAP3.2

CAP3.3

P2.0/XOUT

P2.1/XIN

DVSS

DVCC

RST/NMI/SBWTDIO

TEST/SBWTCK

P1.4/UCA0TXD/UCA0SIMO/TA1.2/TCK/A4/VREF+

P1.5/UCA0RXD/UCA0SOMI/TA1.1/TMS/A5

P1.6/UCA0CLK/TA1CLK/TDI/TCLK/A6

P1.7/UCA0STE/SMCLK/TDO/A7

P1.0/UCB0STE/TA0CLK/A0/Veref+

P1.1/UCB0CLK/TA0.1/A1

P1.2/UCB0SIMO/UCB0SDA/TA0.2/A2/Veref-

P1.3/UCB0SOMI/UCB0SCL/MCLK/A3

P2.2/SYNC/ACLK

P3.0/CAP0.0

P2.3/CAP0.2

CAP0.3

P3.1/UCA1STE/CAP1.0

P2.4/UCA1CLK/CAP1.1

P2.5/UCA1RXD/UCA1SOMI/CAP1.2

P2.6/UCA1TXD/UCA1SIMO/CAP1.3

VREG

CAP2.0

CAP2.1

CAP2.2

P2.7/CAP3.0

CAP3.1

MSP430FR2633IDA

MSP430FR2533IDA

CAP2.3

CAP0.1

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Figure 4-2 shows the pinout for the 32-pin DA package.

Figure 4-2. 32-Pin DA Package (Top View)

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RST/NMI/SBWTDIO

TEST/SBWTCK

P1.4/UCA0TXD/UCA0SIMO/TA1.2/TCK/A4/VREF+

P1.5/UCA0RXD/UCA0SOMI/TA1.1/TMS/A5

P1.6/UCA0CLK/TA1CLK/TDI/TCLKA6

P1.7/UCA0STE/SMCLK/TDO/A7

P1.0/UCB0STE/TA0CLK/A0/Veref+

P1.1/UCB0CLK/TA0.1/A1

P1.2/UCB0SIMO/UCB0SDA/TA0.2/A2/Veref-

P1.3/UCB0SOMI/UCB0SCL/MCLK/A3

P2.2/SYNC/ACLK

P2.3/CAP0.2

CAP0.3

P2.5/UCA1RXD/UCA1SOMI/CAP1.2

P2.6/UCA1TXD/UCA1SIMO/CAP1.3

VREG

CAP2.0

CAP2.1

P2.7/CAP3.0

CAP3.1

P2.0/XOUT

P2.1/XIN

DVSS

DVCC

MSP430FR2632IRGE

MSP430FR2532IRGE

7 8 9 10 11 12

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Figure 4-3 shows the pinout for the 24-pin RGE package.

Figure 4-3. 24-Pin RGE Package (Top View)

l TEXAS INSTRUMENTS Tara View mm v.“ O O O O O O O O O O rw /\ A r K) \J K; L) U \ 4 f x (\ K) \J 0000 O

A2 A3 A4 A5

B1 B2 B3 B4 B5

D1 D2 D4 D5

E1 E2 E4 E5

Ball-SIde View

C4 C5

P2.3/CAP0.2

P1.7/UCA0STE/SMCLK/TDO/A7

P1.2/UCB0SIMO/UCB0SDA/TA0.2/A2/Veref-

P1.0/UCB0STE/TA0CLK/A0/Veref+

P2.6/UCA1TXD/CAP1.3

P2.5/UCA1RXD/CAP1.2

DVSS

TEST/SBWTCK

P1.4/UCA0TXD/UCA0SIMO/TA1.2/TCK/A4/VREF+

P3.2/CAP3.2

P1.3/UCB0SOMI/UCB0SCL/MCLK/A3

P2.2/SYNC/ACLK

P3.0/CAP0.0

P1.1/UCB0CLK/TA0.1/A1

P1.6/UCA0CLK/TA1CLK/TDI/TCLK/A6

P1.5/UCA0RXD/UCA0SOMI/TA1.1/TMS/A5

DVCC

P2.1/XIN

P2.0/XOUT

P2.7/CAP3.0

RST/NMI/SBWTDIO

PIN NO. SIGNAL NAME SIGNAL NAME

PIN NO.

CAP2.0

VREG

CAP2.2

Top View

B1B2

D1D2D4

E1E2E4

P2.3/CAP0.2

P1.7/UCA0STE/SMCLK/TDO/A7

P1.2/UCB0SIMO/UCB0SDA/TA0.2/A2/Veref-

P1.0/UCB0STE/TA0CLK/A0/Veref+

P2.6/UCA1TXD/CAP1.3

P2.5/UCA1RXD/CAP1.2

DVSS

TEST/SBWTCK

P1.4/UCA0TXD/UCA0SIMO/TA1.2/TCK/A4/VREF+

P3.2/CAP3.2

P1.3/UCB0SOMI/UCB0SCL/MCLK/A3

P2.2/SYNC/ACLK

P3.0/CAP0.0

P1.1/UCB0CLK/TA0.1/A1

P1.6/UCA0CLK/TA1CLK/TDI/TCLK/A6

P1.5/UCA0RXD/UCA0SOMI/TA1.1/TMS/A5

DVCC

P2.1/XIN

P2.0/XOUT

P2.7/CAP3.0

RST/NMI/SBWTDIO

PIN NO. SIGNAL NAME SIGNAL NAME

PIN NO.

CAP2.0

VREG

CAP2.2

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Figure 4-4 shows the top view of the YQW package, and Figure 4-5 shows the bottom (ball-side) view.

Figure 4-4. 24-Pin YQW Package (Top View)

Figure 4-5. 24-Pin YQW Package (Bottom View)

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(1) Signals names with (RD) denote the reset default pin name.

(2) To determine the pin mux encodings for each pin, see Section 6.11,Input/Output Diagrams.

(3) Signal Types: I = Input, O = Output, I/O = Input or Output

(4) Buffer Types: LVCMOS, Analog, or Power (see Table 4-3)

(5) The power source shown in this table is the I/O power source, which may differ from the module power source.

(6) Reset States:

OFF = High-impedance with Schmitt trigger and pullup or pulldown (if available) disabled

N/A = Not applicable

4.2 Pin Attributes

Table 4-1 lists the attributes of all pins.

Table 4-1. Pin Attributes

PIN NUMBER SIGNAL NAME(1)

(2) SIGNAL

TYPE(3) BUFFER TYPE(4) POWER

SOURCE(5) RESET STATE

AFTER BOR(6)

RHB DA RGE YQW

1 5 1 E1

RST (RD) I LVCMOS DVCC OFF

NMI I LVCMOS DVCC –

SBWTDIO I/O LVCMOS DVCC –

2 6 2 D2 TEST (RD) I LVCMOS DVCC OFF

SBWTCK I LVCMOS DVCC –

3 7 3 D1

P1.4 (RD) I/O LVCMOS DVCC OFF

UCA0TXD O LVCMOS DVCC –

UCA0SIMO I/O LVCMOS DVCC –

TA1.2 I/O LVCMOS DVCC –

TCK I LVCMOS DVCC –

A4 I Analog DVCC –

VREF+ O Power DVCC –

4 8 4 C2

P1.5 (RD) I/O LVCMOS DVCC OFF

UCA0RXD I LVCMOS DVCC –

UCA0SOMI I/O LVCMOS DVCC –

TA1.1 I/O LVCMOS DVCC –

TMS I LVCMOS DVCC –

A5 I Analog DVCC –

5 9 5 C3

P1.6 (RD) I/O LVCMOS DVCC OFF

UCA0CLK I/O LVCMOS DVCC –

TA1CLK I LVCMOS DVCC –

TDI I LVCMOS DVCC –

TCLK I LVCMOS DVCC –

A6 I Analog DVCC –

6 10 6 B3

P1.7 (RD) I/O LVCMOS DVCC OFF

UCA0STE I/O LVCMOS DVCC –

SMCLK O LVCMOS DVCC –

TDO O LVCMOS DVCC –

A7 I Analog DVCC –

7 11 7 B1

P1.0 (RD) I/O LVCMOS DVCC OFF

UCB0STE I/O LVCMOS DVCC –

TA0CLK I LVCMOS DVCC –

A0 I Analog DVCC –

Veref+ I Power DVCC –

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Table 4-1. Pin Attributes (continued)

PIN NUMBER SIGNAL NAME(1)

(2) SIGNAL

TYPE(3) BUFFER TYPE(4) POWER

SOURCE(5) RESET STATE

AFTER BOR(6)

RHB DA RGE YQW

8 12 8 A1

P1.1 (RD) I/O LVCMOS DVCC OFF

UCB0CLK I/O LVCMOS DVCC –

TA0.1 I/O LVCMOS DVCC –

A1 I Analog DVCC –

9 13 9 B2

P1.2 (RD) I/O LVCMOS DVCC OFF

UCB0SIMO I/O LVCMOS DVCC –

UCB0SDA I/O LVCMOS DVCC –

TA0.2 I/O LVCMOS DVCC –

A2 I Analog DVCC –

Veref- I Power DVCC –

10 14 10 A2

P1.3 (RD) I/O LVCMOS DVCC OFF

UCB0SOMI I/O LVCMOS DVCC –

UCB0SCL I/O LVCMOS DVCC –

MCLK O LVCMOS DVCC –

A3 I Analog DVCC –

11 15 11 A3

P2.2 (RD) I/O LVCMOS DVCC OFF

SYNC I LVCMOS DVCC –

ACLK O LVCMOS DVCC –

12 16 – A4 P3.0 (RD) I/O LVCMOS DVCC OFF

CAP0.0 I/O Analog VREG –

13 17 – – CAP0.1 I/O Analog VREG OFF

14 18 12 A5 P2.3 (RD) I/O LVCMOS DVCC OFF

CAP0.2 I/O Analog VREG –

15 19 13 – CAP0.3 I/O Analog VREG OFF

16 20 – –

P3.1 (RD) I/O LVCMOS DVCC OFF

UCA1STE I/O LVCMOS DVCC –

CAP1.0 I/O Analog VREG –

17 21 – –

P2.4 (RD) I/O LVCMOS DVCC OFF

UCA1CLK I/O LVCMOS DVCC –

CAP1.1 I/O Analog VREG –

18 22 14 B4

P2.5 (RD) I/O LVCMOS DVCC OFF

UCA1RXD I LVCMOS DVCC –

UCA1SOMI I/O LVCMOS DVCC –

CAP1.2 I/O Analog VREG –

19 23 15 B5

P2.6 (RD) I/O LVCMOS DVCC OFF

UCA1TXD O LVCMOS DVCC –

UCA1SIMO I/O LVCMOS DVCC –

CAP1.3 I/O Analog VREG –

20 24 16 C5 VREG P Power VREG N/A

21 25 17 C4 CAP2.0 I/O Analog VREG OFF

22 26 18 – CAP2.1 I/O Analog VREG OFF

23 27 – D5 CAP2.2 I/O Analog VREG OFF

24 28 – – CAP2.3 I/O Analog VREG OFF

25 29 19 E5 P2.7 (RD) I/O LVCMOS DVCC OFF

CAP3.0 I/O Analog VREG –

26 30 20 – CAP3.1 I/O Analog VREG OFF

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Table 4-1. Pin Attributes (continued)

PIN NUMBER SIGNAL NAME(1)

(2) SIGNAL

TYPE(3) BUFFER TYPE(4) POWER

SOURCE(5) RESET STATE

AFTER BOR(6)

RHB DA RGE YQW

27 31 – D4 P3.2 (RD) I/O LVCMOS DVCC OFF

CAP3.2 I/O Analog VREG –

28 32 – – CAP3.3 I/O Analog VREG OFF

29 1 21 E4 P2.0 (RD) I/O LVCMOS DVCC OFF

XOUT O LVCMOS DVCC –

30 2 22 E3 P2.1 (RD) I/O LVCMOS DVCC OFF

XIN I LVCMOS DVCC –

31 3 23 D3 DVSS P Power DVCC N/A

32 4 24 E2 DVCC P Power DVCC N/A

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(1) Pin Types: I = Input, O = Output, I/O = Input or Output, P = Power

4.3 Signal Descriptions

Table 4-2 describes the signals for all device variants and package options.

Table 4-2. Signal Descriptions

FUNCTION SIGNAL NAME PIN NUMBER PIN

TYPE(1) DESCRIPTION

RHB DA RGE YQW

ADC

A0 7 11 7 B1 I Analog input A0

A1 8 12 8 A1 I Analog input A1

A2 9 13 9 B2 I Analog input A2

A3 10 14 10 A2 I Analog input A3

A4 3 7 3 D1 I Analog input A4

A5 4 8 4 C2 I Analog input A5

A6 5 9 5 C3 I Analog input A6

A7 6 10 6 B3 I Analog input A7

Veref+ 7 11 7 B1 I ADC positive reference

Veref- 9 13 9 B2 I ADC negative reference

CapTIvate

CAP0.0 12 16 – A4 I/O CapTIvate channel

CAP0.1 13 17 – – I/O CapTIvate channel

CAP0.2 14 18 12 A5 I/O CapTIvate channel

CAP0.3 15 19 13 – I/O CapTIvate channel

CAP1.0 16 20 – – I/O CapTIvate channel

CAP1.1 17 21 – – I/O CapTIvate channel

CAP1.2 18 22 14 B4 I/O CapTIvate channel

CAP1.3 19 23 15 B5 I/O CapTIvate channel

CAP2.0 21 25 17 C4 I/O CapTIvate channel

CAP2.1 22 26 18 – I/O CapTIvate channel

CAP2.2 23 27 – D5 I/O CapTIvate channel

CAP2.3 24 28 – – I/O CapTIvate channel

CAP3.0 25 29 19 E5 I/O CapTIvate channel

CAP3.1 26 30 20 – I/O CapTIvate channel

CAP3.2 27 31 – D4 I/O CapTIvate channel

CAP3.3 28 32 – – I/O CapTIvate channel

SYNC 11 15 11 A3 I CapTIvate synchronous trigger input for processing and

conversion

Clock

ACLK 11 15 11 A3 O ACLK output

MCLK 10 14 10 A2 O MCLK output

SMCLK 6 10 6 B3 O SMCLK output

XIN 30 2 22 E3 I Input terminal for crystal oscillator

XOUT 29 1 21 E4 O Output terminal for crystal oscillator

Debug

SBWTCK 2 6 2 D2 I Spy-Bi-Wire input clock

SBWTDIO 1 5 1 E1 I/O Spy-Bi-Wire data input/output

TCK 3 7 3 D1 I Test clock

TCLK 5 9 5 C3 I Test clock input

TDI 5 9 5 C3 I Test data input

TDO 6 10 6 B3 O Test data output

TEST 2 6 2 D2 I Test Mode pin – selected digital I/O on JTAG pins

TMS 4 8 4 C2 I Test mode select

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Table 4-2. Signal Descriptions (continued)

FUNCTION SIGNAL NAME PIN NUMBER PIN

TYPE(1) DESCRIPTION

RHB DA RGE YQW

(2) Because this pin is multiplexed with the JTAG function, TI recommends disabling the pin interrupt function while in JTAG debug to

prevent collisions.

GPIO

P1.0 7 11 7 B1 I/O General-purpose I/O

P1.1 8 12 8 A1 I/O General-purpose I/O

P1.2 9 13 9 B2 I/O General-purpose I/O

P1.3 10 14 10 A2 I/O General-purpose I/O

P1.4 3 7 3 D1 I/O General-purpose I/O(2)

P1.5 4 8 4 C2 I/O General-purpose I/O(2)

P1.6 5 9 5 C3 I/O General-purpose I/O(2)

P1.7 6 10 6 B3 I/O General-purpose I/O(2)

P2.0 29 1 21 E4 I/O General-purpose I/O

P2.1 30 2 22 E3 I/O General-purpose I/O

P2.2 11 15 11 A3 I/O General-purpose I/O

P2.3 14 18 12 A5 I/O General-purpose I/O

P2.4 17 21 – – I/O General-purpose I/O

P2.5 18 22 14 B4 I/O General-purpose I/O

P2.6 19 23 15 B5 I/O General-purpose I/O

P2.7 25 29 19 E5 I/O General-purpose I/O

P3.0 12 16 – A4 I/O General-purpose I/O

P3.1 16 20 – – I/O General-purpose I/O

P3.2 27 31 – D4 I/O General-purpose I/O

I2CUCB0SCL 10 14 10 A2 I/O eUSCI_B0 I2C clock

UCB0SDA 9 13 9 B2 I/O eUSCI_B0 I2C data

Power

DVCC 32 4 24 E2 P Power supply

DVSS 31 3 23 D3 P Power ground

VREF+ 3 7 3 D1 P Output of positive reference voltage with ground as

reference

VREG 20 24 16 C5 O CapTIvate regulator external decoupling capacitor

SPI

UCA0CLK 5 9 5 C3 I/O eUSCI_A0 SPI clock input/output

UCA0SIMO 3 7 3 D1 I/O eUSCI_A0 SPI slave in/master out

UCA0SOMI 4 8 4 C2 I/O eUSCI_A0 SPI slave out/master in

UCA0STE 6 10 6 B3 I/O eUSCI_A0 SPI slave transmit enable

UCA1CLK 17 21 – – I/O eUSCI_A1 SPI clock input/output

UCA1SIMO 19 23 15 B5 I/O eUSCI_A1 SPI slave in/master out

UCA1SOMI 18 22 14 B4 I/O eUSCI_A1 SPI slave out/master in

UCA1STE 16 20 – – I/O eUSCI_A1 SPI slave transmit enable

UCB0CLK 8 12 8 A1 I/O eUSCI_B0 clock input/output

UCB0SIMO 9 13 9 B2 I/O eUSCI_B0 SPI slave in/master out

UCB0SOMI 10 14 10 A2 I/O eUSCI_B0 SPI slave out/master in

UCB0STE 7 11 7 B1 I/O eUSCI_B0 slave transmit enable

System NMI 1 5 1 E1 I Nonmaskable interrupt input

RST 1 5 1 E1 I Active-low reset input

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Table 4-2. Signal Descriptions (continued)

FUNCTION SIGNAL NAME PIN NUMBER PIN

TYPE(1) DESCRIPTION

RHB DA RGE YQW

Timer_A

TA0.1 8 12 8 A1 I/O Timer TA0 CCR1 capture: CCI1A input, compare: Out1

outputs

TA0.2 9 13 9 B2 I/O Timer TA0 CCR2 capture: CCI2A input, compare: Out2

outputs

TA0CLK 7 11 7 B1 I Timer clock input TACLK for TA0

TA1.1 4 8 4 C2 I/O Timer TA1 CCR1 capture: CCI1A input, compare: Out1

outputs

TA1.2 3 7 3 D1 I/O Timer TA1 CCR2 capture: CCI2A input, compare: Out2

outputs

TA1CLK 5 9 5 C3 I Timer clock input TACLK for TA1

UART

UCA0RXD 4 8 4 C2 I eUSCI_A0 UART receive data

UCA0TXD 3 7 3 D1 O eUSCI_A0 UART transmit data

UCA1RXD 18 22 14 B4 I eUSCI_A1 UART receive data

UCA1TXD 19 23 15 B5 O eUSCI_A1 UART transmit data

VQFN Pad VQFN thermal pad Pad N/A Pad N/A VQFN package exposed thermal pad. TI recommends

connecting to VSS.

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(1) Only for input pins.

4.4 Pin Multiplexing

Pin multiplexing for these MCUs is controlled by both register settings and operating modes (for example,

if the MCU is in test mode). For details of the settings for each pin and schematics of the multiplexed

ports, see Section 6.11.

4.5 Buffer Types

Table 4-3 defines the pin buffer types that are listed in Table 4-1.

Table 4-3. Buffer Types

BUFFER TYPE

(STANDARD) NOMINAL

VOLTAGE HYSTERESIS PU OR PD

NOMINAL

PU OR PD

STRENGTH

(µA)

OUTPUT

DRIVE

STRENGTH

(mA)

OTHER

CHARACTERISTICS

LVCMOS 3.0 V Y(1) Programmable See

Section 5.11.4 See

Section 5.11.4

Analog 3.0 V N N/A N/A N/A See analog modules in

Section 5 for details.

Power (DVCC) 3.0 V N N/A N/A N/A SVS enables hysteresis on

DVCC.

Power (AVCC) 3.0 V N N/A N/A N/A

(1) Any unused pin with a secondary function that is shared with general-purpose I/O should follow the Px.0 to Px.7 unused pin connection

guidelines.

(2) The pulldown capacitor should not exceed 1.1 nF when using MCUs with Spy-Bi-Wire interface in Spy-Bi-Wire mode with TI tools like

FET interfaces or GANG programmers.

4.6 Connection of Unused Pins

Table 4-4 lists the correct termination of unused pins.

Table 4-4. Connection of Unused Pins(1)

PIN POTENTIAL COMMENT

Px.0 to Px.7 Open Switched to port function, output direction (PxDIR.n = 1)

RST/NMI DVCC 47-kΩpullup or internal pullup selected with 10-nF (or 1.1-nF) pulldown(2)

TEST Open This pin always has an internal pulldown enabled.

CAP2.x, CAPx.1, CAPx.3 Open These pins have internal pullup and pulldown resistors, and high impedance is their

default setting.

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(1) Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. These are stress ratings

only, and functional operation of the device at these or any other conditions beyond those indicated under Recommended Operating

Conditions is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.

(2) This applies to dedicated CapTIvate I/Os only or I/Os worked in CapTIvate mode.

(3) All voltages referenced to VSS.

(4) Higher temperature may be applied during board soldering according to the current JEDEC J-STD-020 specification with peak reflow

temperatures not higher than classified on the device label on the shipping boxes or reels.

5 Specifications

5.1 Absolute Maximum Ratings(1)

over operating free-air temperature range (unless otherwise noted)

MIN MAX UNIT

Voltage applied at DVCC pin to VSS –0.3 4.1 V

Voltage applied to any dedicated CapTIvate pin or pin in CapTIvate mode (2) –0.3 VREG V

Voltage applied to any other pin(3) –0.3 VCC + 0.3

(4.1 V Max) V

Diode current at any device pin ±2 mA

Maximum junction temperature, TJ85 °C

Storage temperature, Tstg(4) –40 125 °C

(1) JEDEC document JEP155 states that 500-V HBM allows safe manufacturing with a standard ESD control process. Pins listed as

±1000 V may actually have higher performance.

(2) JEDEC document JEP157 states that 250-V CDM allows safe manufacturing with a standard ESD control process. Pins listed as ±250 V

may actually have higher performance.

5.2 ESD Ratings

VALUE UNIT

V(ESD) Electrostatic discharge Human-body model (HBM), per ANSI/ESDA/JEDEC JS‑001(1) ±1000 V

Charged-device model (CDM), per JEDEC specification JESD22‑C101(2) ±250

(1) Supply voltage changes faster than 0.2 V/µs can trigger a BOR reset even within the recommended supply voltage range. Following the

data sheet recommendation for capacitor CDVCC limits the slopes accordingly.

(2) Modules may have a different supply voltage range specification. See the specification of the respective module in this data sheet.

(3) TI recommends that power to the DVCC pin must not exceed the limits specified in Recommended Operating Conditions. Exceeding the

specified limits can cause malfunction of the device including erroneous writes to RAM and FRAM.

(4) The minimum supply voltage is defined by the SVS levels. See the SVS threshold parameters in Table 5-2.

(5) A capacitor tolerance of ±20% or better is required. A low-ESR ceramic capacitor of 100 nF (minimum) should be placed as close as

possible (within a few millimeters) to the respective pin pair.

(6) Modules may have a different maximum input clock specification. See the specification of the respective module in this data sheet.

(7) Wait states only occur on actual FRAM accesses (that is, on FRAM cache misses). RAM and peripheral accesses are always executed

without wait states.

(8) If clock sources such as HF crystals or the DCO with frequencies >16 MHz are used, the clock must be divided in the clock system to

comply with this operating condition.

5.3 Recommended Operating Conditions

MIN NOM MAX UNIT

VCC Supply voltage applied at DVCC pin(1)(2)(3)(4) 1.8 3.6 V

VSS Supply voltage applied at DVSS pin 0 V

TAOperating free-air temperature –40 85 °C

TJOperating junction temperature –40 85 °C

CDVCC Recommended capacitor at DVCC(5) 4.7 10 µF

fSYSTEM Processor frequency (maximum MCLK frequency)(6)

No FRAM wait states

(NWAITSx = 0) 0 8

MHz

With FRAM wait states

(NWAITSx = 1)(7) 0 16(8)

fACLK Maximum ACLK frequency 40 kHz

fSMCLK Maximum SMCLK frequency 16(8) MHz

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(1) All inputs are tied to 0 V or to VCC. Outputs do not source or sink any current. Characterized with program executing typical data

processing.

fACLK = 32768 Hz, fMCLK = fSMCLK = fDCO at specified frequency

Program and data entirely reside in FRAM. All execution is from FRAM.

(2) Program and data reside entirely in RAM. All execution is from RAM. No access to FRAM.

5.4 Active Mode Supply Current Into VCC Excluding External Current(1)

VCC = 3 V, TA= 25°C (unless otherwise noted)

PARAMETER EXECUTION

MEMORY TEST

CONDITION

FREQUENCY (fMCLK = fSMCLK)

UNIT

1 MHz

0 WAIT STATES

(NWAITSx = 0)

8 MHz

0 WAIT STATES

(NWAITSx = 0)

16 MHz

1 WAIT STATE

(NWAITSx = 1)

TYP MAX TYP MAX TYP MAX

IAM, FRAM(0%) FRAM

0% cache hit ratio

3 V, 25°C 504 2772 3047 3480 µA

3 V, 85°C 516 2491 2871

IAM, FRAM(100%) FRAM

100% cache hit

ratio

3 V, 25°C 203 625 1000 1215 µA

3 V, 85°C 212 639 1016

IAM, RAM(2) RAM 3 V, 25°C 229 818 1377 µA

5.5 Active Mode Supply Current Per MHz

VCC = 3 V, TA= 25°C (unless otherwise noted)

PARAMETER TEST CONDITIONS TYP UNIT

dIAM,FRAM/df Active mode current consumption per MHz,

execution from FRAM, no wait states [IAM (75% cache hit rate) at 8 MHz –

IAM (75% cache hit rate) at 1 MHz)] / 7 MHz 126 µA/MHz

(1) All inputs are tied to 0 V or to VCC. Outputs do not source or sink any current.

(2) Current for watchdog timer clocked by SMCLK included.

fACLK = 32768 Hz, fMCLK = 0 MHz, fSMCLK at specified frequency.

5.6 Low-Power Mode LPM0 Supply Currents Into VCC Excluding External Current

VCC = 3 V, TA= 25°C (unless otherwise noted)(1)(2)

PARAMETER VCC

FREQUENCY (fSMCLK)

UNIT1 MHz 8 MHz 16 MHz

TYP MAX TYP MAX TYP MAX

ILPM0 2 V 156 328 420 µA

3 V 166 342 433

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(1) All inputs are tied to 0 V or to VCC. Outputs do not source or sink any current.

(2) Not applicable for MCUs with HF crystal oscillator only.

(3) Characterized with a Micro Crystal MS1V-T1K crystal with a load capacitance of 12.5 pF. The internal and external load capacitance are

chosen to closely match the required 12.5-pF load.

(4) Low-power mode 3, 12.5-pF crystal, includes SVS test conditions:

Current for watchdog timer clocked by ACLK and RTC clocked by XT1 included. Current for brownout and SVS included (SVSHE = 1).

CPUOFF = 1, SCG0 = 1 SCG1 = 1, OSCOFF = 0 (LPM3),

fXT1 = 32768 Hz, fACLK = fXT1, fMCLK = fSMCLK = 0 MHz

(5) Low-power mode 3, VLO, excludes SVS test conditions:

Current for watchdog timer clocked by VLO included. RTC disabled. Current for brownout included. SVS disabled (SVSHE = 0).

CPUOFF = 1, SCG0 = 1 SCG1 = 1, OSCOFF = 0 (LPM3)

fXT1 = 32768 Hz, fACLK = fMCLK = fSMCLK = 0 MHz

(6) RTC periodically wakes up every second with external 32768-Hz input as source.

(7) CapTIvate technology works in LPM3 with one proximity sensor for wake on touch. CapTIvate BSWP demonstration board with 1.5-mm

overlay. Current for brownout included. SVS disabled (SVSHE = 0).

fSCAN = 8 Hz, fCONVER = 2 MHz, COUNTS = 800

(8) CapTIvate technology works in LPM3 with one button, wake on touch. CapTIvate BSWP demonstration board with 1.5-mm overlay,

Current for brownout included. SVS disabled (SVSHE = 0).

fSCAN = 8 Hz, fCONVER = 2 MHz, COUNTS = 250

(9) CapTIvate technology works in LPM3 with four self-capacitance buttons, wake on touch. CapTIvate BSWP demonstration board with

1.5-mm overlay. Current for brownout included. SVS disabled (SVSHE = 0).

fSCAN = 8 Hz, fCONVER = 2 MHz, COUNTS = 250

(10) CapTIvate technology works in LPM3 with 16 self-capacitance buttons. The CPU enters active mode between time cycles to configure

the conversions and read the results. CapTIvate BSWP demonstration board with 1.5-mm overlay. Current for brownout included. SVS

disabled (SVSHE = 0).

fSCAN = 8 Hz, fCONVER = 2 MHz, COUNTS = 250

(11) CapTIvate technology works in LPM3 with 64 mutual-capacitance buttons. The CPU enters active mode between time cycles to

configure the conversions and read the results. TIDM-CAPTIVATE-64-BUTTON 64-Button Capacitive Touch Panel. Current for

brownout included. SVS disabled (SVSHE = 0).

fSCAN = 8 Hz, fCONVER = 4 MHz, COUNTS = 250

(12) CapTIvate technology works in LPM4 with one proximity sensor for wake on touch. CapTIvate BSWP demonstration board with 1.5-mm

overlay. Current for brownout included. SVS disabled (SVSHE = 0). VLO (10 kHz) sources to CapTIvate timer, no external crystal.

fSCAN = 8 Hz, fCONVER = 2 MHz, COUNTS = 800

5.7 Low-Power Mode (LPM3 and LPM4) Supply Currents (Into VCC) Excluding External Current

over recommended ranges of supply voltage and operating free-air temperature (unless otherwise noted) (1)

PARAMETER VCC –40°C 25°C 85°C UNIT

TYP MAX TYP MAX TYP MAX

ILPM3,XT1 Low-power mode 3, 12.5-pF crystal, includes

SVS(2)(3)(4) 3 V 0.98 1.18 1.65 3.24 µA

2 V 0.96 1.16 3.21

ILPM3,VLO Low-power mode 3, VLO, excludes SVS(5) 3 V 0.78 0.98 1.40 3.04 µA

2 V 0.76 0.96 3.01

ILPM3, RTC Low-power mode 3, RTC, excludes SVS(6)

(see Figure 5-1)3 V 0.93 1.13 3.19 µA

ILPM3, CapTIvate,

1 proximity, wake on touch

Low-power mode 3, CapTIvate, excludes

SVS(7) 3.3 V 5 µA

ILPM3, CapTIvate,

1 button, wake on touch

Low-power mode 3, CapTIvate, excludes

SVS(8) 3.3 V 3.4 µA

ILPM3, CapTIvate,

4 buttons, wake on touch

Low-power mode 3, CapTIvate, excludes

SVS(9) 3.3 V 3.6 µA

ILPM3, CapTIvate,

16 buttons

Low-power mode 3, CapTIvate, excludes

SVS(10) 3.3 V 27.2 µA

ILPM3, CapTIvate,

64 buttons

Low-power mode 3, CapTIvate, excludes

SVS(11) 3.3 V 109.2 µA

ILPM4, SVS Low-power mode 4, includes SVS 3 V 0.51 0.65 2.65 µA

2 V 0.49 0.64 2.63

ILPM4 Low-power mode 4, excludes SVS 3 V 0.35 0.49 2.49 µA

2 V 0.34 0.48 2.46

ILPM4, CapTIvate,

1 proximity, wake on touch

Low-power mode 4, CapTIvate, excludes

SVS(12) 3 V 4.4 µA

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Low-Power Mode (LPM3 and LPM4) Supply Currents (Into VCC) Excluding External

Current (continued)

over recommended ranges of supply voltage and operating free-air temperature (unless otherwise noted) (1)

PARAMETER VCC –40°C 25°C 85°C UNIT

TYP MAX TYP MAX TYP MAX

(13) CapTIvate technology works in LPM4 with one button, wake on touch. CapTIvate BSWP demonstration board with 1.5-mm overlay,

Current for brownout included. SVS disabled (SVSHE = 0). VLO (10 kHz) sources to CapTIvate timer, no external crystal.

fSCAN = 8 Hz, fCONVER = 2 MHz, COUNTS = 250

(14) CapTIvate technology works in LPM4 with four self-capacitance buttons, wake on touch. CapTIvate BSWP demonstration board with

1.5-mm overlay. Current for brownout included. SVS disabled (SVSHE = 0). VLO (10 kHz) sources to CapTIvate timer, no external

crystal.

fSCAN = 8 Hz, fCONVER = 2 MHz, COUNTS = 250

ILPM4, CapTIvate,

1 button, wake on touch

Low-power mode 4, CapTIvate, excludes

SVS(13) 3 V 2.7 µA

ILPM4, CapTIvate,

4 buttons, wake on touch

Low-power mode 4, CapTIvate, excludes

SVS(14) 3 V 3.0 µA

(1) Not applicable for MCUs with HF crystal oscillator only.

(2) Characterized with a Micro Crystal MS1V-T1K crystal with a load capacitance of 12.5 pF. The internal and external load capacitance are

chosen to closely match the required 12.5-pF load.

(3) Low-power mode 3.5, 12.5-pF crystal, includes SVS test conditions:

Current for RTC clocked by XT1 included. Current for brownout and SVS included (SVSHE = 1). Core regulator disabled.

PMMREGOFF = 1, CPUOFF = 1, SCG0 = 1 SCG1 = 1, OSCOFF = 1 (LPMx.5),

fXT1 = 32768 Hz, fACLK = 0, fMCLK = fSMCLK = 0 MHz

(4) Low-power mode 4.5, includes SVS test conditions:

Current for brownout and SVS included (SVSHE = 1). Core regulator disabled.

PMMREGOFF = 1, CPUOFF = 1, SCG0 = 1 SCG1 = 1, OSCOFF = 1 (LPMx.5),

fXT1 = 0 Hz, fACLK = fMCLK = fSMCLK = 0 MHz

(5) Low-power mode 4.5, excludes SVS test conditions:

Current for brownout included. SVS disabled (SVSHE = 0). Core regulator disabled.

PMMREGOFF = 1, CPUOFF = 1, SCG0 = 1 SCG1 = 1, OSCOFF = 1 (LPMx.5),

fXT1 = 0 Hz, fACLK = fMCLK = fSMCLK = 0 MHz

5.8 Low-Power Mode LPMx.5 Supply Currents (Into VCC) Excluding External Current

over recommended ranges of supply voltage and operating free-air temperature (unless otherwise noted)

PARAMETER VCC –40°C 25°C 85°C UNIT

TYP MAX TYP MAX TYP MAX

ILPM3.5, XT1 Low-power mode 3.5, 12.5-pF crystal, includes

SVS(1)(2)(3) (see Figure 5-2)

3 V 0.65 0.73 0.95 0.99 1.42 µA

2 V 0.63 0.71 0.87

ILPM4.5, SVS Low-power mode 4.5, includes SVS(4) (see Figure 5-

3 V 0.22 0.24 0.31 0.30 0.38 µA

2 V 0.21 0.23 0.28

ILPM4.5 Low-power mode 4.5, excludes SVS(5) 3 V 0.012 0.016 0.055 0.061 0.120 µA

2 V 0.002 0.007 0.044

I TEXAS INSTRUMENTS Temperamre rc) Temperature rc) Temperature 1'0)

0.00

0.05

0.10

0.15

0.20

0.25

0.30

0.35

0.40

0.45

0.50

-40 -30 -20 -10 0 10 20 30 40 50 60 70 80

LPM4.5 Supply Current (µA)

Temperature (°C)

-40 -30 -20 -10 0 10 20 30 40 50 60 70 80

LPM3 Supply Current (µA)

Temperature (°C)

0.0

0.5

1.0

1.5

2.0

2.5

3.0

-40 -30 -20 -10 0 10 20 30 40 50 60 70 80

LPM3.5 Supply Current (µA)

Temperature (°C)

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5.9 Typical Characteristics - Low-Power Mode Supply Currents

VCC = 3 V RTC SVS Disabled

Figure 5-1. LPM3 Supply Current vs Temperature

VCC = 3 V XT1 SVS Enabled

Figure 5-2. LPM3.5 Supply Current vs Temperature

VCC = 3 V SVS Enabled

Figure 5-3. LPM4.5 Supply Current vs Temperature

Table 5-1. Typical Characteristics – Current Consumption Per Module

MODULE TEST CONDITIONS REFERENCE CLOCK MIN TYP MAX UNIT

Timer_A Module input clock 5 µA/MHz

eUSCI_A UART mode Module input clock 7 µA/MHz

eUSCI_A SPI mode Module input clock 5 µA/MHz

eUSCI_B SPI mode Module input clock 5 µA/MHz

eUSCI_B I2C mode, 100 kbaud Module input clock 5 µA/MHz

RTC 32 kHz 85 nA

CRC From start to end of operation MCLK 8.5 µA/MHz

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(1) For more information about traditional and new thermal metrics, see Semiconductor and IC Package Thermal Metrics.

(2) These values are based on a JEDEC-defined 2S2P system (with the exception of the Theta JC (RθJC) value, which is based on a

JEDEC-defined 1S0P system) and will change based on environment and application. For more information, see these EIA/JEDEC

standards:

• JESD51-2, Integrated Circuits Thermal Test Method Environmental Conditions - Natural Convection (Still Air)

• JESD51-3, Low Effective Thermal Conductivity Test Board for Leaded Surface Mount Packages

• JESD51-7, High Effective Thermal Conductivity Test Board for Leaded Surface Mount Packages

• JESD51-9, Test Boards for Area Array Surface Mount Package Thermal Measurements

5.10 Thermal Resistance Characteristics

THERMAL METRIC(1) VALUE(2) UNIT

RθJA Junction-to-ambient thermal resistance, still air

VQFN 32 pin (RHB) 33.5

ºC/W

TSSOP 32 pin (DA) 69.4

VQFN 24 pin (RGE) 32.6

DSBGA 24 pin (YQW) 63.7

RθJC(top) Junction-to-case (top) thermal resistance

VQFN 32 pin (RHB) 25.7

ºC/W

TSSOP 32 pin (DA) 18.1

VQFN 24 pin (RGE) 32.4

DSBGA 24 pin (YQW) 0.3

RθJB Junction-to-board thermal resistance

VQFN 32 pin (RHB) 7.6

ºC/W

TSSOP 32 pin (DA) 33.1

VQFN 24 pin (RGE) 10.1

DSBGA 24 pin (YQW) 9.2

M V V1 /

VBOR

VSVS–

VSVS+

Power Cycle Reset SVS Reset BOR Reset

tBOR

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5.11 Timing and Switching Characteristics

5.11.1 Power Supply Sequencing

Table 5-2 lists the characteristics of the SVS and BOR.

(1) A safe BOR can be correctly generated only if DVCC drops below this voltage before it rises.

(2) When an BOR occurs, a safe BOR can be correctly generated only if DVCC is kept low longer than this period before it reaches VSVSH+.

(3) For additional information, see the Dynamic Voltage Scaling Power Solution for MSP430 Devices With Single-Channel LDO Reference

Design.

(4) This is a characterized result with external 1-mA load to ground from –40°C to 85°C.

Table 5-2. PMM, SVS and BOR

over recommended ranges of supply voltage and operating free-air temperature (unless otherwise noted) (see Figure 5-4)

PARAMETER TEST CONDITIONS MIN TYP MAX UNIT

VBOR, safe Safe BOR power-down level(1) 0.1 V

tBOR, safe Safe BOR reset delay(2) 10 ms

ISVSH,AM SVSHcurrent consumption, active mode VCC = 3.6 V 1.5 µA

ISVSH,LPM SVSHcurrent consumption, low-power modes VCC = 3.6 V 240 nA

VSVSH- SVSHpower-down level(3) 1.71 1.80 1.86 V

VSVSH+ SVSHpower-up level(3) 1.74 1.89 1.99 V

VSVSH_hys SVSHhysteresis 80 mV

tPD,SVSH, AM SVSHpropagation delay, active mode 10 µs

tPD,SVSH, LPM SVSHpropagation delay, low-power modes 100 µs

VREF, 1.2V 1.2-V REF voltage(4) 1.158 1.20 1.242 V

Figure 5-4. Power Cycle, SVS, and BOR Reset Conditions

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5.11.2 Reset Timing

Table 5-3 lists the wake-up times.

(1) The wake-up time is measured from the edge of an external wake-up signal (for example, port interrupt or wake-up event) to the first

externally observable MCLK clock edge.

(2) The wake-up time is measured from the edge of an external wake-up signal (for example, port interrupt or wake-up event) until the first

instruction of the user program is executed.

Table 5-3. Wake-up Times From Low-Power Modes and Reset

over recommended ranges of supply voltage and operating free-air temperature (unless otherwise noted)

PARAMETER TEST

CONDITIONS VCC MIN TYP MAX UNIT

tWAKE-UP FRAM

Additional wake-up time to activate the FRAM in

AM if previously disabled by the FRAM controller or

from a LPM if immediate activation is selected for

wakeup(1)

3 V 10 µs

tWAKE-UP LPM0 Wake-up time from LPM0 to active mode (1) 3 V 200 +

2.5 / fDCO ns

tWAKE-UP LPM3 Wake-up time from LPM3 to active mode (2) 3 V 10 µs

tWAKE-UP LPM4 Wake-up time from LPM4 to active mode 3 V 10 µs

tWAKE-UP LPM3.5 Wake-up time from LPM3.5 to active mode (2) 3 V 350 µs

tWAKE-UP LPM4.5 Wake-up time from LPM4.5 to active mode (2) SVSHE = 1 3 V 350 µs

SVSHE = 0 1 ms

tWAKE-UP-RESET Wake-up time from RST or BOR event to active

mode (2) 3 V 1 ms

tRESET Pulse duration required at RST/NMI pin to accept a

reset 3 V 2 µs

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5.11.3 Clock Specifications

Table 5-4 lists the characteristics of XT1.

(1) To improve EMI on the LFXT oscillator, observe the following guidelines:

• Keep the trace between the device and the crystal as short as possible.

• Design a good ground plane around the oscillator pins.

• Prevent crosstalk from other clock or data lines into oscillator pins XIN and XOUT.

• Avoid running PCB traces underneath or adjacent to the XIN and XOUT pins.

• Use assembly materials and processes that avoid any parasitic load on the oscillator XIN and XOUT pins.

• If conformal coating is used, make sure that it does not induce capacitive or resistive leakage between the oscillator pins.

(2) When LFXTBYPASS is set, LFXT circuits are automatically powered down. Input signal is a digital square wave with parametrics

defined in the Schmitt-trigger inputs section of this data sheet. Duty cycle requirements are defined by DCLFXT, SW.

(3) Maximum frequency of operation of the entire device cannot be exceeded.

(4) Oscillation allowance is based on a safety factor of 5 for recommended crystals. The oscillation allowance is a function of the

LFXTDRIVE settings and the effective load. In general, comparable oscillator allowance can be achieved based on the following

guidelines, but should be evaluated based on the actual crystal selected for the application:

• For LFXTDRIVE = {0}, CL,eff = 3.7 pF

• For LFXTDRIVE = {1}, 6 pF ≤CL,eff ≤9 pF

• For LFXTDRIVE = {2}, 6 pF ≤CL,eff ≤10 pF

• For LFXTDRIVE = {3}, 6 pF ≤CL,eff ≤12 pF

(5) Includes parasitic bond and package capacitance (approximately 2 pF per pin).

(6) Requires external capacitors at both terminals to meet the effective load capacitance specified by crystal manufacturers. Recommended

effective load capacitance values supported are 3.7 pF, 6 pF, 9 pF, and 12.5 pF. Maximum shunt capacitance of 1.6 pF. The PCB adds

additional capacitance, so it must also be considered in the overall capacitance. Verify that the recommended effective load capacitance

of the selected crystal is met.

(7) Includes start-up counter of 1024 clock cycles.

(8) Frequencies above the MAX specification do not set the fault flag. Frequencies between the MIN and MAX specifications might set the

flag. A static condition or stuck at fault condition sets the flag.

(9) Measured with logic-level input frequency but also applies to operation with crystals.

Table 5-4. XT1 Crystal Oscillator (Low Frequency)

over recommended ranges of supply voltage and operating free-air temperature (unless otherwise noted)(1)

PARAMETER TEST CONDITIONS VCC MIN TYP MAX UNIT

fXT1, LF XT1 oscillator crystal, low

frequency LFXTBYPASS = 0 32768 Hz

DCXT1, LF XT1 oscillator LF duty cycle Measured at MCLK,

fLFXT = 32768 Hz 30% 70%

fXT1,SW XT1 oscillator logic-level square-

wave input frequency LFXTBYPASS = 1 (2)(3) 32.768 kHz

DCXT1, SW LFXT oscillator logic-level square-

wave input duty cycle LFXTBYPASS = 1 40% 60%

OALFXT Oscillation allowance for

LF crystals (4) LFXTBYPASS = 0, LFXTDRIVE = {3},

fLFXT = 32768 Hz, CL,eff = 12.5 pF 200 kΩ

CL,eff Integrated effective load

capacitance(5) See (6) 1 pF

tSTART,LFXT Start-up time (7) fOSC = 32768 Hz,

LFXTBYPASS = 0, LFXTDRIVE = {3},

TA= 25°C, CL,eff = 12.5 pF 1000 ms

fFault,LFXT Oscillator fault frequency (8) XTS = 0(9) 0 3500 Hz

Table 5-5 lists the characteristics of the FLL.

Table 5-5. DCO FLL, Frequency

over recommended operating free-air temperature (unless otherwise noted)

PARAMETER TEST CONDITIONS VCC MIN TYP MAX UNIT

fDCO, FLL

FLL lock frequency, 16 MHz, 25°C Measured at MCLK, Internal

trimmed REFO as reference

3 V –1.0% 1.0%

FLL lock frequency, 16 MHz, –40°C to 85°C 3 V –2.0% 2.0%

FLL lock frequency, 16 MHz, –40°C to 85°C Measured at MCLK, XT1

crystal as reference 3 V –0.5% 0.5%

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Table 5-5. DCO FLL, Frequency (continued)

over recommended operating free-air temperature (unless otherwise noted)

PARAMETER TEST CONDITIONS VCC MIN TYP MAX UNIT

fDUTY Duty cycle

Measured at MCLK, XT1

crystal as reference

3 V 40% 50% 60%

Jittercc Cycle-to-cycle jitter, 16 MHz 3 V 0.25%

Jitterlong Long term jitter, 16 MHz 3 V 0.022%

tFLL, lock FLL lock time 3 V 280 ms

tstart-up DCO start-up time, 2 MHz Measured at MCLK 3 V 16 µs

Table 5-6 lists the characteristics of the DCO.

Table 5-6. DCO Frequency

over recommended operating free-air temperature (unless otherwise noted) (also see Figure 5-5)

PARAMETER TEST CONDITIONS VCC TYP UNIT

fDCO, 16MHz DCO frequency, 16 MHz

DCORSEL = 101b, DISMOD = 1b, DCOFTRIMEN = 1b,

DCOFTRIM = 000b, DCO = 0

3 V

7.46

MHz

DCORSEL = 101b, DISMOD = 1b, DCOFTRIMEN = 1b,

DCOFTRIM = 000b, DCO = 511 12.26

DCORSEL = 101b, DISMOD = 1b, DCOFTRIMEN = 1b,

DCOFTRIM = 111b, DCO = 0 17.93

DCORSEL = 101b, DISMOD = 1b, DCOFTRIMEN = 1b,

DCOFTRIM = 111b, DCO = 511 29.1

fDCO, 12MHz DCO frequency, 12 MHz

DCORSEL = 100b, DISMOD = 1b, DCOFTRIMEN = 1b,

DCOFTRIM = 000b, DCO = 0

3 V

5.75

MHz

DCORSEL = 100b, DISMOD = 1b, DCOFTRIMEN = 1b,

DCOFTRIM = 000b, DCO = 511 9.5

DCORSEL = 100b, DISMOD = 1b, DCOFTRIMEN = 1b,

DCOFTRIM = 111b, DCO = 0 13.85

DCORSEL = 100b, DISMOD = 1b, DCOFTRIMEN = 1b,

DCOFTRIM = 111b, DCO = 511 22.5

fDCO, 8MHz DCO frequency, 8 MHz

DCORSEL = 011b, DISMOD = 1b, DCOFTRIMEN = 1b,

DCOFTRIM = 000b, DCO = 0

3 V

3.91

MHz

DCORSEL = 011b, DISMOD = 1b, DCOFTRIMEN = 1b,

DCOFTRIM = 000b, DCO = 511 6.49

DCORSEL = 011b, DISMOD = 1b, DCOFTRIMEN = 1b,

DCOFTRIM = 111b, DCO = 0 9.5

DCORSEL = 011b, DISMOD = 1b, DCOFTRIMEN = 1b,

DCOFTRIM = 111b, DCO = 511 15.6

fDCO, 4MHz DCO frequency, 4 MHz

DCORSEL = 010b, DISMOD = 1b, DCOFTRIMEN = 1b,

DCOFTRIM = 000b, DCO = 0

3 V

2.026

MHz

DCORSEL = 010b, DISMOD = 1b, DCOFTRIMEN = 1b,

DCOFTRIM = 000b, DCO = 511 3.407

DCORSEL = 010b, DISMOD = 1b, DCOFTRIMEN = 1b,

DCOFTRIM = 111b, DCO = 0 4.95

DCORSEL = 010b, DISMOD = 1b, DCOFTRIMEN = 1b,

DCOFTRIM = 111b, DCO = 511 8.26

fDCO, 2MHz DCO frequency, 2 MHz

DCORSEL = 001b, DISMOD = 1b, DCOFTRIMEN = 1b,

DCOFTRIM = 000b, DCO = 0

3 V

1.0225

MHz

DCORSEL = 001b, DISMOD = 1b, DCOFTRIMEN = 1b,

DCOFTRIM = 000b, DCO = 511 1.729

DCORSEL = 001b, DISMOD = 1b, DCOFTRIMEN = 1b,

DCOFTRIM = 111b, DCO = 0 2.525

DCORSEL = 001b, DISMOD = 1b, DCOFTRIMEN = 1b,

DCOFTRIM = 111b, DCO = 511 4.25

‘5‘ TEXAS INSTRUMENTS

Frequency (MHz)

0 1 2 3 4 5DCORSEL

0DCO 511 0511 0 0 0 0

511 511 511 511

DCOFTRIM = 0

DCOFTRIM = 7

DCOFTRIM = 0

DCOFTRIM = 7

DCOFTRIM = 0

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Table 5-6. DCO Frequency (continued)

over recommended operating free-air temperature (unless otherwise noted) (also see Figure 5-5)

PARAMETER TEST CONDITIONS VCC TYP UNIT

fDCO, 1MHz DCO frequency, 1 MHz

DCORSEL = 000b, DISMOD = 1b, DCOFTRIMEN = 1b,

DCOFTRIM = 000b, DCO = 0

3 V

0.5319

MHz

DCORSEL = 000b, DISMOD = 1b, DCOFTRIMEN = 1b,

DCOFTRIM = 000b, DCO = 511 0.9029

DCORSEL = 000b, DISMOD = 1b, DCOFTRIMEN = 1b,

DCOFTRIM = 111b, DCO = 0 1.307

DCORSEL = 000b, DISMOD = 1b, DCOFTRIMEN = 1b,

DCOFTRIM = 111b, DCO = 511 2.21

VCC = 3 V TA= –40°C to 85°C

Figure 5-5. Typical DCO Frequency

Table 5-7 lists the characteristics of the REFO.

(1) Calculated using the box method: (MAX(–40°C to 85°C) – MIN(–40°C to 85°C)) / MIN(–40°C to 85°C) / (85°C – (–40°C))

(2) Calculated using the box method: (MAX(1.8 V to 3.6 V) – MIN(1.8 V to 3.6 V)) / MIN(1.8 V to 3.6 V) / (3.6 V – 1.8 V)

Table 5-7. REFO

over recommended operating free-air temperature (unless otherwise noted)

PARAMETER TEST CONDITIONS VCC MIN TYP MAX UNIT

IREFO REFO oscillator current consumption TA= 25°C 3 V 15 µA

fREFO REFO calibrated frequency Measured at MCLK 3 V 32768 Hz

REFO absolute calibrated tolerance –40°C to 85°C 1.8 V to 3.6 V –3.5% +3.5%

dfREFO/dTREFO frequency temperature drift Measured at MCLK(1) 3 V 0.01 %/°C

dfREFO/

dVCC REFO frequency supply voltage drift Measured at MCLK at 25°C(2) 1.8 V to 3.6 V 1 %/V

fDC REFO duty cycle Measured at MCLK 1.8 V to 3.6 V 40% 50% 60%

tSTART REFO start-up time 40% to 60% duty cycle 50 µs

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Table 5-8 lists the characteristics of the VLO.

NOTE

The VLO clock frequency is reduced by 15% (typical) when the device switches from active

mode to LPM3 or LPM4, because the reference changes. This lower frequency is not a

violation of the VLO specifications (see Table 5-8).

(1) Calculated using the box method: (MAX(–40°C to 85°C) – MIN(–40°C to 85°C)) / MIN(–40°C to 85°C) / (85°C – (–40°C))

(2) Calculated using the box method: (MAX(1.8 V to 3.6 V) – MIN(1.8 V to 3.6 V)) / MIN(1.8 V to 3.6 V) / (3.6 V – 1.8 V)

Table 5-8. Internal Very-Low-Power Low-Frequency Oscillator (VLO)

over recommended ranges of supply voltage and operating free-air temperature (unless otherwise noted)

PARAMETER TEST CONDITIONS VCC TYP UNIT

fVLO VLO frequency Measured at MCLK 3 V 10 kHz

dfVLO/dTVLO frequency temperature drift Measured at MCLK(1) 3 V 0.5 %/°C

dfVLO/dVCC VLO frequency supply voltage drift Measured at MCLK(2) 2 V to 3.6 V 4 %/V

fVLO,DC Duty cycle Measured at MCLK 3 V 50%

Table 5-9 lists the characteristics of the MODOSC.

Table 5-9. Module Oscillator (MODOSC)

over recommended ranges of supply voltage and operating free-air temperature (unless otherwise noted)

PARAMETER VCC MIN TYP MAX UNIT

fMODOSC MODOSC frequency 3 V 3.8 4.8 5.8 MHz

fMODOSC/dT MODOSC frequency temperature drift 3 V 0.102 %/℃

fMODOSC/dVCC MODOSC frequency supply voltage drift 1.8 V to 3.6 V 1.02 %/V

fMODOSC,DC Duty cycle 3 V 40% 50% 60%

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5.11.4 Digital I/Os

Table 5-10 lists the characteristics of the digital inputs.

(1) The leakage current is measured with VSS or VCC applied to the corresponding pins, unless otherwise noted.

(2) The leakage of the digital port pins is measured individually. The port pin is selected for input and the pullup or pulldown resistor is

disabled.

(3) An external signal sets the interrupt flag every time the minimum interrupt pulse duration t(int) is met. It may be set by trigger signals

shorter than t(int).

Table 5-10. Digital Inputs

over recommended ranges of supply voltage and operating free-air temperature (unless otherwise noted)

PARAMETER TEST CONDITIONS VCC MIN TYP MAX UNIT

VIT+ Positive-going input threshold voltage 2 V 0.90 1.50 V

3 V 1.35 2.25

VIT– Negative-going input threshold voltage 2 V 0.50 1.10 V

3 V 0.75 1.65

Vhys Input voltage hysteresis (VIT+ – VIT–)2 V 0.3 0.8 V

3 V 0.4 1.2

RPull Pullup or pulldown resistor For pullup: VIN = VSS

For pulldown: VIN = VCC 20 35 50 kΩ

CI,dig Input capacitance, digital only port pins VIN = VSS or VCC 3 pF

CI,ana Input capacitance, port pins with shared analog

functions VIN = VSS or VCC 5 pF

Ilkg(Px.y) High-impedance leakage current See (1) (2) 2 V, 3 V –20 20 nA

t(int) External interrupt timing (external trigger pulse

duration to set interrupt flag)(3)

Ports with interrupt capability

(see block diagram and

terminal function descriptions) 2 V, 3 V 50 ns

Table 5-11 lists the characteristics of the digital outputs.

(1) The maximum total current, I(OHmax) and I(OLmax), for all outputs combined should not exceed ±48 mA to hold the maximum voltage drop

specified.

(2) The port can output frequencies at least up to the specified limit and might support higher frequencies.

Table 5-11. Digital Outputs

over recommended ranges of supply voltage and operating free-air temperature (unless otherwise noted) (also see Figure 5-

6,Figure 5-7,Figure 5-8, and Figure 5-9)

PARAMETER TEST CONDITIONS VCC MIN TYP MAX UNIT

VOH High-level output voltage I(OHmax) = –3 mA(1) 2 V 1.4 2.0 V

I(OHmax) = –5 mA(1) 3 V 2.4 3.0

VOL Low-level output voltage I(OLmax) = 3 mA(1) 2 V 0.0 0.60 V

I(OHmax) = 5 mA(1) 3 V 0.0 0.60

fPort_CLK Clock output frequency CL= 20 pF(2) 2 V 16 MHz

3 V 16

trise,dig Port output rise time, digital only port pins CL= 20 pF 2 V 10 ns

3 V 7

tfall,dig Port output fall time, digital only port pins CL= 20 pF 2 V 10 ns

3 V 5

l TEXAS INSTRUMENTS LwLeveI OmputVuhage (V) Lawieve‘ Oumm Vul|age (w HighrLevel ompmvmnage (V) HIgIvLeve‘ ompm Vunage (vp

–10

–7.5

–5

–2.5

0 0.25 0.5 0.75 1 1.25 1.5 1.75 2

High-Level Output Current (mA)

High-Level Output Voltage (V)

85°C

25°C

–40°C

–30

–25

–20

–15

–10

–5

0 0.5 1 1.5 2 2.5 3

High-Level Output Current (mA)

High-Level Output Voltage (V)

85°C

25°C

–40°C

2.5

7.5

0 0.25 0.5 0.75 1 1.25 1.5 1.75 2

Low-Level Output Current (mA)

Low-Level Output Voltage (V)

85°C

25°C

–40°C

–5

0 0.5 1 1.5 2 2.5 3

Low-Level Output Current (mA)

Low-Level Output Voltage (V)

85°C

25°C

–40°C

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5.11.4.1 Typical Characteristics – Outputs at 3 V and 2 V

DVCC = 3 V

Figure 5-6. Typical Low-Level Output Current vs Low-Level

Output Voltage

DVCC = 2 V

Figure 5-7. Typical Low-Level Output Current vs Low-Level

Output Voltage

DVCC = 3 V

Figure 5-8. Typical High-Level Output Current vs High-Level

Output Voltage

DVCC = 2 V

Figure 5-9. Typical High-Level Output Current vs High-Level

Output Voltage

‘5‘ TEXAS INSTRUMENTS

Capture

tTIMR

Timer Clock

TAx.CCIA

tSU,CCIA t,HD,CCIA

tTIMR

Timer Clock

TAx.1

tVALID,PWM

0h 1h

CCR0-1 CCR0 0h

CCR0-1 CCR0

Timer

tHD,PWM

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5.11.5 VREF+ Built-in Reference

Table 5-12 lists the characteristics of VREF+.

Table 5-12. VREF+

over recommended ranges of supply voltage and operating free-air temperature (unless otherwise noted)

PARAMETER TEST CONDITIONS VCC MIN TYP MAX UNIT

VREF+ Positive built-in reference voltage EXTREFEN = 1 with 1-mA load current 2 V, 3 V 1.15 1.19 1.23 V

TCREF+ Temperature coefficient of built-in

reference voltage 30 µV/°C

5.11.6 Timer_A

Table 5-13 lists the characteristics of Timer_A.

Table 5-13. Timer_A

over recommended ranges of supply voltage and operating free-air temperature (unless otherwise noted) (see Figure 5-10

and Figure 5-11)

PARAMETER TEST CONDITIONS VCC MIN TYP MAX UNIT

fTA Timer_A input clock frequency Internal: SMCLK or ACLK,

External: TACLK,

duty cycle = 50% ±10% 2 V, 3 V 16 MHz

tTA,cap Timer_A capture timing All capture inputs, minimum pulse

duration required for capture 2 V, 3 V 20 ns

Figure 5-10. Timer PWM Mode

Figure 5-11. Timer Capture Mode

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5.11.7 eUSCI

Table 5-14 lists the supported frequencies of the eUSCI in UART mode.

Table 5-14. eUSCI (UART Mode) Clock Frequency

over recommended ranges of supply voltage and operating free-air temperature (unless otherwise noted)

PARAMETER TEST CONDITIONS VCC MIN MAX UNIT

feUSCI eUSCI input clock frequency Internal: SMCLK or MODCLK, External: UCLK,

duty cycle = 50% ±10% 2 V, 3 V 16 MHz

fBITCLK BITCLK clock frequency

(equals baud rate in Mbaud) 2 V, 3 V 5 MHz

Table 5-15 lists the characteristics of the eUSCI in UART mode.

(1) Pulses on the UART receive input (UCxRX) shorter than the UART receive deglitch time are suppressed. To ensure that pulses are

correctly recognized, their duration should exceed the maximum specification of the deglitch time.

Table 5-15. eUSCI (UART Mode)

over recommended ranges of supply voltage and operating free-air temperature (unless otherwise noted)

PARAMETER TEST CONDITIONS VCC TYP UNIT

ttUART receive deglitch time (1)

UCGLITx = 0

2 V, 3 V

UCGLITx = 1 40

UCGLITx = 2 68

UCGLITx = 3 110

Table 5-16 lists the supported frequencies of the eUSCI in SPI master mode.

Table 5-16. eUSCI (SPI Master Mode) Clock Frequency

over recommended ranges of supply voltage and operating free-air temperature (unless otherwise noted)

PARAMETER TEST CONDITIONS MIN MAX UNIT

feUSCI eUSCI input clock frequency Internal: SMCLK or MODCLK, duty cycle = 50% ±10% 8 MHz

Table 5-17 lists the characteristics of the eUSCI in SPI master mode.

(1) fUCxCLK = 1 / 2tLO/HI with tLO/HI = max(tVALID,MO(eUSCI) + tSU,SI(Slave), tSU,MI(eUSCI) + tVALID,SO(Slave))

For the slave parameters tSU,SI(Slave) and tVALID,SO(Slave), see the SPI parameters of the attached slave.

(2) Specifies the time to drive the next valid data to the SIMO output after the output changing UCLK clock edge. See the timing diagrams

in Figure 5-12 and Figure 5-13.

(3) Specifies how long data on the SIMO output is valid after the output changing UCLK clock edge. Negative values indicate that the data

on the SIMO output can become invalid before the output changing clock edge observed on UCLK. See the timing diagrams in Figure 5-

12 and Figure 5-13.

Table 5-17. eUSCI (SPI Master Mode)

over recommended ranges of supply voltage and operating free-air temperature (unless otherwise noted)(1)

PARAMETER TEST CONDITIONS VCC MIN MAX UNIT

tSTE,LEAD STE lead time, STE active to clock UCSTEM = 0, UCMODEx = 01 or 10 1UCxCLK

cycles

UCSTEM = 1, UCMODEx = 01 or 10

tSTE,LAG STE lag time, last clock to STE inactive UCSTEM = 0, UCMODEx = 01 or 10 1UCxCLK

cycles

UCSTEM = 1, UCMODEx = 01 or 10

tSU,MI SOMI input data setup time 2 V 45 ns

3 V 35

tHD,MI SOMI input data hold time 2 V 0 ns

3 V 0

tVALID,MO SIMO output data valid time(2) UCLK edge to SIMO valid,

CL= 20 pF

2 V 20 ns

3 V 20

tHD,MO SIMO output data hold time(3) CL= 20 pF 2 V 0 ns

3 V 0

*9 TEXAS INSTRUMENTS

tSU,MI

tHD,MI

UCLK

SOMI

SIMO

tVALID,MO

CKPL = 0

CKPL = 1

tLOW/HIGH tLOW/HIGH

1/fUCxCLK

tSU,MI

tHD,MI

UCLK

SOMI

SIMO

tVALID,MO

CKPL = 0

CKPL = 1

tLOW/HIGH tLOW/HIGH

1/fUCxCLK

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Figure 5-12. SPI Master Mode, CKPH = 0

Figure 5-13. SPI Master Mode, CKPH = 1

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Table 5-18 lists the characteristics of the eUSCI in SPI slave mode.

(1) fUCxCLK = 1/2tLO/HI with tLO/HI ≥max(tVALID,MO(Master) + tSU,SI(eUSCI), tSU,MI(Master) + tVALID,SO(eUSCI))

For the master parameters tSU,MI(Master) and tVALID,MO(Master), see the SPI parameters of the attached master.

(2) Specifies the time to drive the next valid data to the SOMI output after the output changing UCLK clock edge. See the timing diagrams

in Figure 5-14 and Figure 5-15.

(3) Specifies how long data on the SOMI output is valid after the output changing UCLK clock edge. See the timing diagrams in Figure 5-14

and Figure 5-15.

Table 5-18. eUSCI (SPI Slave Mode)

over recommended ranges of supply voltage and operating free-air temperature (unless otherwise noted)(1)

PARAMETER TEST CONDITIONS VCC MIN MAX UNIT

tSTE,LEAD STE lead time, STE active to clock 2 V 55 ns

3 V 45

tSTE,LAG STE lag time, Last clock to STE inactive 2 V 20 ns

3 V 20

tSTE,ACC STE access time, STE active to SOMI data out 2 V 65 ns

3 V 40

tSTE,DIS STE disable time, STE inactive to SOMI high

impedance

2 V 40 ns

3 V 35

tSU,SI SIMO input data setup time 2 V 6 ns

3 V 4

tHD,SI SIMO input data hold time 2 V 12 ns

3 V 12

tVALID,SO SOMI output data valid time(2) UCLK edge to SOMI valid,

CL= 20 pF

2 V 65 ns

3 V 40

tHD,SO SOMI output data hold time (3) CL= 20 pF 2 V 5 ns

3 V 5

*9 TEXAS INSTRUMENTS

STE

UCLK

CKPL = 0

CKPL = 1

SOMI

SIMO

tSU,SI

tHD,SI

tVALID,SO

tSTE,LEAD

tLOW/HIGH

1/fUCxCLK

tLOW/HIGH

tSTE,LAG

tDIS

tACC

STE

UCLK

CKPL = 0

CKPL = 1

SOMI

SIMO

tSU,SIMO

tHD,SIMO

tVALID,SOMI

tSTE,LEAD

tLOW/HIGH

1/fUCxCLK

tLOW/HIGH

tSTE,LAG

tDIS

tACC

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Figure 5-14. SPI Slave Mode, CKPH = 0

Figure 5-15. SPI Slave Mode, CKPH = 1

‘5‘ TEXAS INSTRUMENTS

SDA

SCL

tHD,DAT

tSU,DAT

tHD,STA

tHIGH

tLOW

tBUF

tHD,STA

tSU,STA

tSP

tSU,STO

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Table 5-19 lists the characteristics of the eUSCI in I2C mode.

Table 5-19. eUSCI (I2C Mode)

over recommended ranges of supply voltage and operating free-air temperature (unless otherwise noted) (see Figure 5-16)

PARAMETER TEST CONDITIONS VCC MIN TYP MAX UNIT

feUSCI eUSCI input clock frequency Internal: SMCLK or MODCLK,

External: UCLK

Duty cycle = 50% ±10% 16 MHz

fSCL SCL clock frequency 2 V, 3 V 0 400 kHz

tHD,STA Hold time (repeated) START fSCL = 100 kHz 2 V, 3 V 4.0 µs

fSCL > 100 kHz 0.6

tSU,STA Setup time for a repeated START fSCL = 100 kHz 2 V, 3 V 4.7 µs

fSCL > 100 kHz 0.6

tHD,DAT Data hold time 2 V, 3 V 0 ns

tSU,DAT Data setup time 2 V, 3 V 250 ns

tSU,STO Setup time for STOP fSCL = 100 kHz 2 V, 3 V 4.0 µs

fSCL > 100 kHz 0.6

tSP Pulse duration of spikes suppressed by

input filter

UCGLITx = 0

2 V, 3 V

50 600

UCGLITx = 1 25 300

UCGLITx = 2 12.5 150

UCGLITx = 3 6.3 75

tTIMEOUT Clock low time-out

UCCLTOx = 1

2 V, 3 V

msUCCLTOx = 2 30

UCCLTOx = 3 33

Figure 5-16. I2C Mode Timing

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5.11.8 ADC

Table 5-20 lists the input requirements of the ADC.

Table 5-20. ADC, Power Supply and Input Range Conditions

over operating free-air temperature range (unless otherwise noted)

PARAMETER TEST CONDITIONS VCC MIN TYP MAX UNIT

DVCC ADC supply voltage 2.0 3.6 V

V(Ax) Analog input voltage range All ADC pins 0 DVCC V

IADC

Operating supply current into DVCC

terminal, reference current not

included, repeat-single-channel

mode

fADCCLK = 5 MHz, ADCON = 1,

REFON = 0, SHT0 = 0, SHT1 = 0,

ADCDIV = 0, ADCCONSEQx = 10b

2 V 185

µA

3 V 207

CIInput capacitance Only one terminal Ax can be selected at one

time, from the pad to the ADC capacitor

array, including wiring and pad 2.2 V 1.6 2.0 pF

RI,MUX Input MUX ON resistance DVCC = 2 V, 0 V ≤VAx ≤DVCC 2 kΩ

RI,Misc Input miscellaneous resistance 34 kΩ

Table 5-21 lists the timing parameters of the ADC.

(1) RI= RI,MUX + RI,Misc

(2) tSample = ln(2n+1) × τ, where n = ADC resolution, τ= (RI+ RS)×CI

Table 5-21. ADC, 10-Bit Timing Parameters

over operating free-air temperature range (unless otherwise noted)

PARAMETER TEST CONDITIONS VCC MIN TYP MAX UNIT

fADCCLK For specified performance of ADC linearity

parameters 2 V to

3.6 V 0.45 5 5.5 MHz

fADCOSC Internal ADC oscillator

(MODOSC) ADCDIV = 0, fADCCLK = fADCOSC 2 V to

3.6 V 4.5 5.0 5.5 MHz

tCONVERT Conversion time

REFON = 0, Internal oscillator,

10 ADCCLK cycles, 10-bit mode,

fADCOSC = 4.5 MHz to 5.5 MHz

2 V to

3.6 V 2.18 2.67

µs

External fADCCLK from ACLK or SMCLK,

ADCSSEL ≠02 V to

3.6 V 12 ×

1 / fADCCLK

tADCON Turnon settling time of

the ADC

The error in a conversion started after tADCON is

less than ±0.5 LSB,

Reference and input signal already settled 100 ns

tSample Sampling time RS= 1000 Ω, RI(1) = 36000 Ω, CI= 3.5 pF,

Approximately 8 Tau (t) are required for an error

of less than ±0.5 LSB(2)

2 V 1.5 µs

3 V 2.0

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Table 5-22 lists the linearity parameters of the ADC.

(1) The temperature sensor offset can vary significantly. TI recommends a single-point calibration to minimize the offset error of the built-in

temperature sensor.

(2) The device descriptor structure contains calibration values for 30°C and 85°C for each available reference voltage level. The sensor

voltage can be computed as VSENSE = TCSENSOR × (Temperature, °C) + VSENSOR , where TCSENSOR and VSENSOR can be computed

from the calibration values for higher accuracy.

(3) The typical equivalent impedance of the sensor is 700 kΩ. The sample time required includes the sensor on time, tSENSOR(on).

Table 5-22. ADC, 10-Bit Linearity Parameters

over operating free-air temperature range (unless otherwise noted)

PARAMETER TEST CONDITIONS VCC MIN TYP MAX UNIT

Integral linearity error (10-bit mode)

Veref+ as reference

2.4 V to

3.6 V –2 2

LSB

Integral linearity error (8-bit mode) 2 V to

3.6 V –2 2

Differential linearity error (10-bit mode)

Veref+ as reference

2.4 V to

3.6 V –1 1

LSB

Differential linearity error (8-bit mode) 2 V to

3.6 V –1 1

Offset error (10-bit mode)

Veref+ as reference

2.4 V to

3.6 V –6.5 6.5

Offset error (8-bit mode) 2 V to

3.6 V –6.5 6.5

Gain error (10-bit mode) Veref+ as reference 2.4 V to

3.6 V

–2.0 2.0 LSB

Internal 1.5-V reference –3.0% 3.0%

Gain error (8-bit mode) Veref+ as reference 2 V to

3.6 V

–2.0 2.0 LSB

Internal 1.5-V reference –3.0% 3.0%

Total unadjusted error (10-bit mode) Veref+ as reference 2.4 V to

3.6 V

–2.0 2.0 LSB

Internal 1.5-V reference –3.0% 3.0%

Total unadjusted error (8-bit mode) Veref+ as reference 2 V to

3.6 V

–2.0 2.0 LSB

Internal 1.5-V reference –3.0% 3.0%

VSENSOR See (1) ADCON = 1, INCH = 0Ch,

TA= 0°C 3 V 913 mV

TCSENSOR See (2) ADCON = 1, INCH = 0Ch 3 V 3.35 mV/°C

tSENSOR

(sample)

Sample time required if channel 12 is

selected(3)

ADCON = 1, INCH = 0Ch, Error

of conversion result ≤1 LSB,

AM and all LPMs above LPM3 3 V 30

µs

ADCON = 1, INCH = 0Ch, Error

of conversion result ≤1 LSB,

LPM3 3 V 100

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5.11.9 CapTIvate

Table 5-23 lists the characteristics of the CapTIvate module.

Table 5-23. CapTIvate Electrical Characteristics

over operating free-air temperature range (unless otherwise noted)

PARAMETER TEST CONDITIONS MIN TYP MAX UNIT

VREG Reference voltage output 1.5 1.55 1.6 V

CREG External buffer capacitor ESR ≤200 mΩ0.8 1 1.2 µF

CELECTRODE Maximum capacitance of all external

electrodes on all CapTIvate blocks Running a conversion at 4 MHz 300 pF

tWAKEUP,COLD Voltage regulator wake-up time LDO completely off then turned on 1 ms

tWAKEUP,WARM Voltage regulator wake-up time LDO in low-power mode then turned on 300 us

fCAPCLK Captivate oscillator frequency, nominal TA= 25ºC, CAPCLK0, FREQSHFT = 00b –3% 16 +3% MHz

DCCAPCLK CapTIvate oscillator duty cycle Excluding first clock cycle, DC = thigh × f 40% 50% 60%

Table 5-24 lists the signal-to-noise ratio of the CapTIvate module.

(1) SNR is defined as the ratio of the measured change in electrode capacitance due to a touch compared with the measured change in

capacitance due to the device noise floor. For additional detail on SNR in capacitive sensing applications and how to measure it in your

system, see Sensitivity, SNR, and Design Margin in Capacitive Touch Applications.

(2) Ctrepresents the increase or decrease in electrode capacitance due to a touch. Cprepresents the inherent parasitic capacitance of the

sensing electrode that is present when no touch is applied. Therefore, the touch signal is defined as Ct/Cp, expressed as a percent

change in capacitance. Increasing Ctor decreasing Cpincreases signal.

Table 5-24. CapTIvate Signal-to-Noise Ratio Characteristics

over operating free-air temperature range from –40°C to 105°C ambient (TA), unless otherwise noted

PARAMETER TEST CONDITIONS MIN TYP MAX UNIT

SNR Signal-to-noise ratio(1)

TA= 25°C, Ct> 0.5 pF, Cp< 20 pF, >2.5% change in

capacitance(2) 5:1 36:1

TA= 0°C, Ct> 0.5 pF, Cp< 20 pF, >2.5% change in

capacitance(2) 28:1

TA= –40°C, Ct> 0.5 pF, Cp< 20 pF, >2.5% change in

capacitance(2) 19:1

5.11.10 FRAM

Table 5-25 lists the characteristics of the FRAM.

(1) Writing to FRAM does not require a setup sequence or additional power when compared to reading from FRAM. The FRAM read

current IREAD is included in the active mode current consumption parameter IAM,FRAM.

(2) FRAM does not require a special erase sequence.

(3) Writing into FRAM is as fast as reading.

(4) The maximum read (and write) speed is specified by fSYSTEM using the appropriate wait state settings (NWAITSx).

Table 5-25. FRAM

over recommended ranges of supply voltage and operating free-air temperature (unless otherwise noted)

PARAMETER TEST CONDITIONS MIN TYP MAX UNIT

Read and write endurance 1015 cycles

tRetention Data retention duration

TJ= 25°C 100

yearsTJ= 70°C 40

TJ= 85°C 10

IWRITE Current to write into FRAM IREAD(1) nA

IERASE Erase current N/A(2) nA

tWRITE Write time tREAD(3) ns

tREAD Read time NWAITSx = 0 1/fSYSTEM(4) ns

NWAITSx = 1 2/fSYSTEM(4)

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1/fSBW

tSU,SBWTDIO tHD,SBWTDIO

tSBW,High

tSBW,Low

RST/NMI/SBWTDIO

tValid,SBWTDIO

tSBW,EN

tSBW,Ret

tEN,SBWTDIO

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5.11.11 Debug and Emulation

Table 5-26 lists the characteristics of the Spy-Bi-Wire interface.

(1) Tools that access the Spy-Bi-Wire interface must wait for the tSBW,En time after pulling the TEST/SBWTCK pin high before applying the

first SBWTCK clock edge.

(2) Maximum tSBW,Ret time after pulling or releasing the TEST/SBWTCK pin low until the Spy-Bi-Wire pins revert from their Spy-Bi-Wire

function to their application function. This time applies only if the Spy-Bi-Wire mode is selected.

Table 5-26. JTAG, Spy-Bi-Wire Interface

over recommended ranges of supply voltage and operating free-air temperature (unless otherwise noted) (see Figure 5-17)

PARAMETER VCC MIN TYP MAX UNIT

fSBW Spy-Bi-Wire input frequency 2 V, 3 V 0 10 MHz

tSBW,Low Spy-Bi-Wire low clock pulse duration 2 V, 3 V 0.028 15 µs

tSU, SBWTDIO SBWTDIO setup time (before falling edge of SBWTCK in TMS and

TDI slot, Spy-Bi-Wire) 2 V, 3 V 4 ns

tHD, SBWTDIO SBWTDIO hold time (after rising edge of SBWTCK in TMS and TDI

slot, Spy-Bi-Wire) 2 V, 3 V 19 ns

tValid, SBWTDIO SBWTDIO data valid time (after falling edge of SBWTCK in TDO

slot, Spy-Bi-Wire) 2 V, 3 V 31 ns

tSBW, En Spy-Bi-Wire enable time (TEST high to acceptance of first clock

edge) (1) 2 V, 3 V 110 µs

tSBW,Ret Spy-Bi-Wire return to normal operation time(2) 2 V, 3 V 15 100 µs

Rinternal Internal pulldown resistance on TEST 2 V, 3 V 20 35 50 kΩ

Figure 5-17. JTAG Spy-Bi-Wire Timing

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TCK

1/fTCK

tSU,TMS

tHD,TMS

tTCK,High

tTCK,Low

TEST

tJTAG,Ret

TMS

TDO

tZ-Valid,TDO tValid,TDO tValid-Z,TDO

tSU,TDI

tHD,TDI

TDI

(or TDO as TDI)

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Table 5-27 lists the characteristics of the 4-wire JTAG interface.

(1) fTCK may be restricted to meet the timing requirements of the module selected.

Table 5-27. JTAG, 4-Wire Interface

over recommended ranges of supply voltage and operating free-air temperature (unless otherwise noted) (see Figure 5-18)

PARAMETER VCC MIN TYP MAX UNIT

fTCK TCK input frequency(1) 2 V, 3 V 0 10 MHz

tTCK,Low TCK low clock pulse duration 2 V, 3 V 15 ns

tTCK,High TCK high clock pulse duration 2 V, 3 V 15 ns

tSU,TMS TMS setup time (before rising edge of TCK) 2 V, 3 V 11 ns

tHD,TMS TMS hold time (after rising edge of TCK) 2 V, 3 V 3 ns

tSU,TDI TDI setup time (before rising edge of TCK) 2 V, 3 V 13 ns

tHD,TDI TDI hold time (after rising edge of TCK) 2 V, 3 V 5 ns

tZ-Valid,TDO TDO high impedance to valid output time (after falling edge of TCK) 2 V, 3 V 26 ns

tValid,TDO TDO to new valid output time (after falling edge of TCK) 2 V, 3 V 26 ns

tValid-Z,TDO TDO valid to high-impedance output time (after falling edge of TCK) 2 V, 3 V 26 ns

tJTAG,Ret Spy-Bi-Wire return to normal operation time 15 100 µs

Rinternal Internal pulldown resistance on TEST 2 V, 3 V 20 35 50 kΩ

Figure 5-18. JTAG 4-Wire Timing

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6 Detailed Description

6.1 Overview

The MSP430FR263x and MSP430FR253x ultra-low-power MCUs are the first FRAM-based MCUs with

integrated high-performance charge-transfer CapTIvate technology in ultra-low-power high-reliability high-

flexibility MCUs. The MSP430FR263x and MSP430FR253x MCUs feature up to 16 self-capacitance or 64

mutual-capacitance electrodes, proximity sensing, and high accuracy up to 1-fF detection. The MCUs also

include four 16-bit timers, eUSCIs that support UART, SPI, and I2C, a hardware multiplier, an RTC module

with alarm capabilities, and a high-performance 10-bit ADC.

6.2 CPU

The MSP430 CPU has a 16-bit RISC architecture that is highly transparent to the application. All

operations, other than program-flow instructions, are performed as register operations in conjunction with

seven addressing modes for source operand and four addressing modes for destination operand.

The CPU is integrated with 16 registers that provide reduced instruction execution time. The register-to-

Four of the registers, R0 to R3, are dedicated as program counter (PC), stack pointer (SP), status register

(SR), and constant generator (CG), respectively. The remaining registers are general-purpose registers.

Peripherals are connected to the CPU using data, address, and control buses. Peripherals can be

managed with all instructions.

6.3 Operating Modes

The MSP430FR263x and MSP430FR253x MCUs have one active mode and several software-selectable

low-power modes of operation (see Table 6-1). An interrupt event can wake the MCU from low-power

mode (LPM0 or LPM3), service the request, and restore the MCU back to the low-power mode on return

from the interrupt program. Low-power modes LPM3.5 and LPM4.5 disable the core supply to minimize

power consumption.

Table 6-1. Operating Modes

MODE

AM LPM0 LPM3 LPM4 LPM3.5 LPM4.5

ACTIVE

MODE

(FRAM ON) CPU OFF STANDBY OFF ONLY RTC SHUTDOWN

Maximum system clock 16 MHz 16 MHz 40 kHz 0 40 kHz 0

Power consumption at 25°C, 3 V 126 µA/MHz 40 µA/MHz 1.7 µA/button

average with

8-Hz scan

0.49 µA

without SVS

0.73 µA with

RTC counter

only in LFXT

16 nA without

SVS

Wake-up time N/A Instant 10 µs 10 µs 350 µs 350 µs

Wake-up events N/A All All CapTIvate

I/O RTC

I/O I/O

Power

Regulator Full

Regulation Full

Regulation Partial Power

Down Partial Power

Down Power Down

SVS On On Optional Optional Optional Optional

Brownout On On On On On On

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Table 6-1. Operating Modes (continued)

MODE

AM LPM0 LPM3 LPM4 LPM3.5 LPM4.5

ACTIVE

MODE

(FRAM ON) CPU OFF STANDBY OFF ONLY RTC SHUTDOWN

(1) The status shown for LPM4 applies to internal clocks only.

(2) Backup memory contains 32 bytes of register space in peripheral memory. See Table 6-24 and Table 6-43 for its memory allocation.

Clock(1)

MCLK Active Off Off Off Off Off

SMCLK Optional Optional Off Off Off Off

FLL Optional Optional Off Off Off Off

DCO Optional Optional Off Off Off Off

MODCLK Optional Optional Off Off Off Off

REFO Optional Optional Optional Off Off Off

ACLK Optional Optional Optional Off Off Off

XT1CLK Optional Optional Optional Off Optional Off

VLOCLK Optional Optional Optional Off Optional Off

CapTIvate MODCLK Optional Optional Optional Off Off Off

Core

CPU On Off Off Off Off Off

FRAM On On Off Off Off Off

RAM On On On On Off Off

Backup memory(2) On On On On On Off

Peripherals

Timer0_A3 Optional Optional Optional Off Off Off

Timer1_A3 Optional Optional Optional Off Off Off

Timer2_A2 Optional Optional Optional Off Off Off

Timer3_A2 Optional Optional Optional Off Off Off

WDT Optional Optional Optional Off Off Off

eUSCI_A0 Optional Optional Off Off Off Off

eUSCI_A1 Optional Optional Off Off Off Off

eUSCI_B0 Optional Optional Off Off Off Off

CRC Optional Optional Off Off Off Off

ADC Optional Optional Optional Off Off Off

RTC Optional Optional Optional Off Optional Off

CapTIvate Optional Optional Optional Off Off Off

I/O General-purpose

digital input/output On Optional State Held State Held State Held State Held

NOTE

XT1CLK and VLOCLK can be active during LPM4 if requested by low-frequency peripherals,

such as RTC, WDT, or CapTIvate.

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6.4 Interrupt Vector Addresses

The interrupt vectors and the power-up start address are in the address range 0FFFFh to 0FF80h (see

Table 6-2). The vector contains the 16-bit address of the appropriate interrupt-handler instruction

sequence.

Table 6-2. Interrupt Sources, Flags, and Vectors

INTERRUPT SOURCE INTERRUPT FLAG SYSTEM

INTERRUPT WORD

ADDRESS PRIORITY

System Reset

Power up, Brownout, Supply supervisor

External reset RST

Watchdog time-out, Key violation

FRAM access time error

FRAM uncorrectable bit error detection

Software POR, BOR

FLL unlock error

PMMPORIFG, PMMBORIFG, SVSHIFG

PMMRSTIFG

WDTIFG

ACCTEIFG

UBDIFG

SYSRSTIV

FLLUNLOCKIFG

Reset FFFEh 63, Highest

System NMI

Vacant memory access

JTAG mailbox

FRAM bit error detection

VMAIFG

JMBINIFG, JMBOUTIFG

CBDIFG, UBDIFG

Nonmaskable FFFCh 62

User NMI

External NMI

Oscillator fault NMIIFG

OFIFG Nonmaskable FFFAh 61

Timer0_A3 TA0CCR0 CCIFG0 Maskable FFF8h 60

Timer0_A3 TA0CCR1 CCIFG1, TA0CCR2 CCIFG2,

TA0IFG (TA0IV) Maskable FFF6h 59

Timer1_A3 TA1CCR0 CCIFG0 Maskable FFF4h 58

Timer1_A3 TA1CCR1 CCIFG1, TA1CCR2 CCIFG2,

TA1IFG (TA1IV) Maskable FFF2h 57

Timer2_A2 TA2CCR0 CCIFG0 Maskable FFF0h 56

Timer2_A2 TA2CCR1 CCIFG1, TA2IFG (TA2IV) FFEEh 55

Timer3_A2 TA3CCR0 CCIFG0 Maskable FFECh 54

Timer3_A2 TA3CCR1 CCIFG1, TA3IFG (TA3IV) FFEAh 53

RTC RTCIFG Maskable FFE8h 52

Watchdog timer interval mode WDTIFG Maskable FFE6h 51

eUSCI_A0 receive or transmit

UCTXCPTIFG, UCSTTIFG, UCRXIFG,

UCTXIFG (UART mode)

UCRXIFG, UCTXIFG (SPI mode)

(UCA0IV)

Maskable FFE4h 50

eUSCI_A1 receive or transmit

UCTXCPTIFG, UCSTTIFG, UCRXIFG,

UCTXIFG (UART mode)

UCRXIFG, UCTXIFG (SPI mode)

(UCA1IV)

Maskable FFE2h 49

eUSCI_B0 receive or transmit

UCB0RXIFG, UCB0TXIFG (SPI mode)

UCALIFG, UCNACKIFG, UCSTTIFG,

UCSTPIFG, UCRXIFG0, UCTXIFG0,

UCRXIFG1, UCTXIFG1, UCRXIFG2,

UCTXIFG2, UCRXIFG3, UCTXIFG3,

UCCNTIFG, UCBIT9IFG (I2C mode)

(UCB0IV)

Maskable FFE0h 48

ADC ADCIFG0, ADCINIFG, ADCLOIFG,

ADCHIIFG, ADCTOVIFG, ADCOVIFG

(ADCIV) Maskable FFDEh 47

P1 P1IFG.0 to P1IFG.7 (P1IV) Maskable FFDCh 46

P2 P2IFG.0 to P2IFG.7 (P2IV) Maskable FFDAh 45

CapTIvate (See CapTivate Design Center for details) Maskable FFD8h 44, Lowest

Reserved Reserved Maskable FFD6h to

FF88h

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Table 6-2. Interrupt Sources, Flags, and Vectors (continued)

INTERRUPT SOURCE INTERRUPT FLAG SYSTEM

INTERRUPT WORD

ADDRESS PRIORITY

Signatures

BSL Signature 2 0FF86h

BSL Signature 1 0FF84h

JTAG Signature 2 0FF82h

JTAG Signature 1 0FF80h

6.5 Bootloader (BSL)

The BSL lets users program the FRAM or RAM using either the UART serial interface or the I2C interface.

Access to the MCU memory through the BSL is protected by an user-defined password. Use of the BSL

requires four pins (see Table 6-3 and Table 6-4). BSL entry requires a specific entry sequence on the

RST/NMI/SBWTDIO and TEST/SBWTCK pins. This device supports the blank device detection to

automatically invoke the BSL, skipping this special entry sequence, to save time and simplify onboard

programming. For a complete description of the features of the BSL, see the MSP430 FRAM Device

Bootloader (BSL) User's Guide.

Table 6-3. UART BSL Pin Requirements and Functions

DEVICE SIGNAL BSL FUNCTION

RST/NMI/SBWTDIO Entry sequence signal

TEST/SBWTCK Entry sequence signal

P1.4 Data transmit

P1.5 Data receive

VCC Power supply

VSS Ground supply

Table 6-4. I2C BSL Pin Requirements and Functions

DEVICE SIGNAL BSL FUNCTION

RST/NMI/SBWTDIO Entry sequence signal

TEST/SBWTCK Entry sequence signal

P1.2 Data transmit and receive

P1.3 Clock

VCC Power supply

VSS Ground supply

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6.6 JTAG Standard Interface

The MSP low-power microcontrollers support the standard JTAG interface, which requires four signals for

sending and receiving data. The JTAG signals are shared with general-purpose I/O. The TEST/SBWTCK

pin enables the JTAG signals. In addition to these signals, the RST/NMI/SBWTDIO is required to interface

with MSP430 development tools and device programmers. Table 6-5 lists the JTAG pin requirements. For

further details on interfacing to development tools and device programmers, see the MSP430 Hardware

Tools User's Guide. For details on using the JTAG interface, see MSP430 Programming With the JTAG

Interface.

Table 6-5. JTAG Pin Requirements and Function

DEVICE SIGNAL DIRECTION JTAG FUNCTION

P1.4/UCA0TXD/UCA0SIMO/TA1.2/TCK/A4/VREF+ IN JTAG clock input

P1.5/UCA0RXD/UCA0SOMI/TA1.1/TMS/A5 IN JTAG state control

P1.6/UCA0CLK/TA1CLK/TDI/TCLK/A6 IN JTAG data input, TCLK input

P1.7/UCA0STE/SMCLK/TDO/A7 OUT JTAG data output

TEST/SBWTCK IN Enable JTAG pins

RST/NMI/SBWTDIO IN External reset

DVCC – Power supply

DVSS – Ground supply

6.7 Spy-Bi-Wire Interface (SBW)

The MSP low-power microcontrollers support the 2-wire SBW interface. SBW can be used to interface

with MSP development tools and device programmers. Table 6-6 lists the SBW interface pin requirements.

For further details on interfacing to development tools and device programmers, see the MSP430

Hardware Tools User's Guide. For details on using the SBW interface, see the MSP430 Programming

With the JTAG Interface.

Table 6-6. Spy-Bi-Wire Pin Requirements and Functions

DEVICE SIGNAL DIRECTION SBW FUNCTION

TEST/SBWTCK IN Spy-Bi-Wire clock input

RST/NMI/SBWTDIO IN, OUT Spy-Bi-Wire data input and output

DVCC – Power supply

DVSS – Ground supply

6.8 FRAM

The FRAM can be programmed using the JTAG port, SBW, the BSL, or in-system by the CPU. Features

of the FRAM include:

• Byte and word access capability

• Programmable wait state generation

• Error correction coding (ECC)

6.9 Memory Protection

The device features memory protection for user access authority and write protection, including options to:

• Secure the whole memory map to prevent unauthorized access from JTAG port or BSL, by writing

JTAG and BSL signatures using the JTAG port, SBW, the BSL, or in-system by the CPU.

• Enable write protection to prevent unwanted write operation to FRAM contents by setting the control

bits in the System Configuration 0 register. For detailed information, see the System Resets, Interrupts,

and Operating Modes, System Control Module (SYS) chapter in the MP430FR4xx and MP430FR2xx

Family User's Guide.

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6.10 Peripherals

Peripherals are connected to the CPU through data, address, and control buses. All peripherals can be

handled by using all instructions in the memory map. For complete module description, see the

MP430FR4xx and MP430FR2xx Family User's Guide.

6.10.1 Power-Management Module (PMM)

The PMM includes an integrated voltage regulator that supplies the core voltage to the device. The PMM

also includes supply voltage supervisor (SVS) and brownout protection. The brownout reset circuit (BOR)

is implemented to provide the proper internal reset signal to the device during power on and power off.

The SVS circuitry detects if the supply voltage drops below a user-selectable safe level. SVS circuitry is

available on the primary supply.

The device contains two on-chip reference: 1.5 V for internal reference and 1.2 V for external reference.

The 1.5-V reference is internally connected to ADC channel 13. DVCC is internally connected to ADC

channel 15. When DVCC is set as the reference voltage for ADC conversion, the DVCC can be easily

represent as Equation 1 by using ADC sampling 1.5-V reference without any external components

support.

DVCC = (1023 × 1.5 V) ÷ 1.5-V reference ADC result (1)

A 1.2-V reference voltage can be buffered and output to P1.4/MCLK/TCK/A4/VREF+, when

EXTREFEN = 1 in the PMMCTL1 register. ADC channel 4 can also be selected to monitor this voltage.

For more detailed information, see the MP430FR4xx and MP430FR2xx Family User's Guide.

6.10.2 Clock System (CS) and Clock Distribution

The clock system includes a 32-kHz crystal oscillator (XT1), an internal very-low-power low-frequency

oscillator (VLO), an integrated 32-kHz RC oscillator (REFO), an integrated internal digitally controlled

oscillator (DCO) that may use frequency-locked loop (FLL) locking with internal or external 32-kHz

reference clock, and an on-chip asynchronous high-speed clock (MODOSC). The clock system is

designed for cost-effective designs with minimal external components. A fail-safe mechanism is included

for XT1. The clock system module offers the following clock signals.

• Main Clock (MCLK): The system clock used by the CPU and all relevant peripherals accessed by the

bus. All clock sources except MODOSC can be selected as the source with a predivider of 1, 2, 4, 8,

16, 32, 64, or 128.

• Sub-Main Clock (SMCLK): The subsystem clock used by the peripheral modules. SMCLK derives from

the MCLK with a predivider of 1, 2, 4, or 8. This means SMCLK is always equal to or less than MCLK.

• Auxiliary Clock (ACLK): This clock is derived from the external XT1 clock or internal REFO clock up to

40 kHz.

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All peripherals may have one or several clock sources depending on specific functionality. Table 6-7 lists

the clock distribution used in this device.

Table 6-7. Clock Distribution

CLOCK

SOURCE

SELECT

BITS

MCLK SMCLK ACLK MODCLK XT1CLK VLOCLK EXTERNAL PIN

Frequency

Range DC to

16 MHz DC to

40 kHz 5 MHz

±10% DC to

40 kHz 10 kHz

±50% –

CPU N/A Default – – – – – –

FRAM N/A Default – – – – – –

RAM N/A Default – – – – – –

CRC N/A Default – – – – – –

I/O N/A Default – – – – – –

TA0 TASSEL – 10b 01b – – – 00b (TA0CLK pin)

TA1 TASSEL – 10b 01b – – – 00b (TA1CLK pin)

TA2 TASSEL – 10b 01b – – – –

TA3 TASSEL – 10b 01b – – – –

eUSCI_A0 UCSSEL – 10b or 11b – 01b – – 00b (UCA0CLK pin)

eUSCI_A1 UCSSEL – 10b or 11b – 01b – – 00b (UCA1CLK pin)

eUSCI_B0 UCSSEL – 10b or 11b – 01b – – 00b (UCB0CLK pin)

WDT WDTSSEL – 00b 01b – – 10b or 11b –

ADC ADCSSEL – 11b 01b 00b – – –

CapTIvate CAPTSSEL – 00b – – 01b –

CAPCLKSEL – 1b – – – – –

RTC RTCSS – 01b – – 10b 11b –

6.10.3 General-Purpose Input/Output Port (I/O)

Up to 19 I/O ports are implemented.

• P1 and P2 are full 8-bit ports; P3 has 3 bits implemented.

• All individual I/O bits are independently programmable.

• Any combination of input, output, and interrupt conditions is possible.

• All ports support programmable pullup or pulldown.

• Edge-selectable interrupt and LPM3.5 and LPM4.5 wake-up input capability is available for P1 and P2.

• Read and write access to port-control registers is supported by all instructions.

• Ports can be accessed byte-wise or word-wise in pairs.

• CapTIvate functionality is supported on all CAPx.y pins.

NOTE

Configuration of digital I/Os after BOR reset

To prevent any cross currents during start-up of the device, all port pins are high-impedance

with Schmitt triggers and module functions disabled. To enable the I/O functions after a BOR

reset, the ports must be configured first and then the LOCKLPM5 bit must be cleared. For

details, see the Configuration After Reset section in the Digital I/O chapter of the

MP430FR4xx and MP430FR2xx Family User's Guide.

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6.10.4 Watchdog Timer (WDT)

The primary function of the WDT module is to perform a controlled system restart after a software problem

occurs. If the selected time interval expires, a system reset is generated. If the watchdog function is not

needed in an application, the module can be configured as interval timer and can generate interrupts at

selected time intervals. Table 6-8 lists the system clocks that can be used to source the WDT.

Table 6-8. WDT Clocks

WDTSSEL NORMAL OPERATION

(WATCHDOG AND INTERVAL TIMER MODE)

00 SMCLK

01 ACLK

10 VLOCLK

11 Reserved

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6.10.5 System (SYS) Module

The SYS module handles many of the system functions within the device. These features include power-

on reset (POR) and power-up clear (PUC) handling, NMI source selection and management, reset

interrupt vector generators, bootloader entry mechanisms, and configuration management (device

descriptors). The SYS module also includes a data exchange mechanism through SBW called a JTAG

mailbox mail box that can be used in the application. Table 6-9 summarizes the interrupts that are

managed by the SYS module.

Table 6-9. System Module Interrupt Vector Registers

INTERRUPT VECTOR

SYSRSTIV, System Reset 015Eh

No interrupt pending 00h

Brownout (BOR) 02h Highest

RSTIFG RST/NMI (BOR) 04h

PMMSWBOR software BOR (BOR) 06h

LPMx.5 wake up (BOR) 08h

Security violation (BOR) 0Ah

Reserved 0Ch

SVSHIFG SVSH event (BOR) 0Eh

Reserved 10h

Reserved 12h

PMMSWPOR software POR (POR) 14h

WDTIFG watchdog time-out (PUC) 16h

WDTPW password violation (PUC) 18h

FRCTLPW password violation (PUC) 1Ah

Uncorrectable FRAM bit error detection 1Ch

Peripheral area fetch (PUC) 1Eh

PMMPW PMM password violation (PUC) 20h

FLL unlock (PUC) 24h

Reserved 22h, 26h to 3Eh Lowest

SYSSNIV, System NMI 015Ch

No interrupt pending 00h

SVS low-power reset entry 02h Highest

Uncorrectable FRAM bit error detection 04h

Reserved 06h

Reserved 08h

Reserved 0Ah

Reserved 0Ch

Reserved 0Eh

Reserved 10h

VMAIFG Vacant memory access 12h

JMBINIFG JTAG mailbox input 14h

JMBOUTIFG JTAG mailbox output 16h

Correctable FRAM bit error detection 18h

Reserved 1Ah to 1Eh Lowest

SYSUNIV, User NMI 015Ah

No interrupt pending 00h

NMIIFG NMI pin or SVSHevent 02h Highest

OFIFG oscillator fault 04h

Reserved 06h to 1Eh Lowest

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6.10.6 Cyclic Redundancy Check (CRC)

The 16-bit cyclic redundancy check (CRC) module produces a signature based on a sequence of data

values and can be used for data checking purposes. The CRC generation polynomial is compliant with

CRC-16-CCITT standard of x16 + x12 + x5+ 1.

6.10.7 Enhanced Universal Serial Communication Interface (eUSCI_A0, eUSCI_B0)

The eUSCI modules are used for serial data communications. The eUSCI_A module supports either

UART or SPI communications. The eUSCI_B module supports either SPI or I2C communications.

Additionally, eUSCI_A supports automatic baud-rate detection and IrDA. Table 6-10 lists the pin

configurations that are required for each eUSCI mode.

Table 6-10. eUSCI Pin Configurations

eUSCI_A0

PIN UART SPI

P1.4 TXD SIMO

P1.5 RXD SOMI

P1.6 – SCLK

P1.7 – STE

eUSCI_A1

P2.6 TXD SIMO

P2.5 RXD SOMI

P2.4 – SCLK

P3.1 – STE

eUSCI_B0

PIN I2C SPI

P1.0 – STE

P1.1 – SCLK

P1.2 SDA SIMO

P1.3 SCL SOMI

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6.10.8 Timers (Timer0_A3, Timer1_A3, Timer2_A2 and Timer3_A2)

The Timer0_A3 and Timer1_A3 modules are 16-bit timers and counters with three capture/compare

registers each. Both timers support multiple captures or compares, PWM outputs, and interval timing (see

Table 6-11 and Table 6-12). Both timers have extensive interrupt capabilities. Interrupts may be generated

from the counter on overflow conditions and from each capture/compare register.

The CCR0 registers on Timer0_A3 and Timer1_A3 are not externally connected and can be used only for

hardware period timing and interrupt generation. In Up mode, these CCR0 registers can be used to set the

overflow value of the counter.

Table 6-11. Timer0_A3 Signal Connections

PORT PIN DEVICE INPUT

SIGNAL MODULE INPUT

NAME MODULE BLOCK MODULE OUTPUT

SIGNAL DEVICE OUTPUT

SIGNAL

P1.0 TA0CLK TACLK

Timer N/AACLK (internal) ACLK

SMCLK (internal) SMCLK

CCI0A

CCR0 TA0

CCI0B Timer1_A3 CCI0B

input

DVSS GND

DVCC VCC

P1.1 TA0.1 CCI1A

CCR1 TA1

TA0.1

from RTC (internal) CCI1B Timer1_A3 CCI1B

input

DVSS GND

DVCC VCC

P1.2 TA0.2 CCI2A

CCR2 TA2

TA0.2

CCI2B Timer1_A3 CCI2B

input,

IR Input

DVSS GND

DVCC VCC

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Table 6-12. Timer1_A3 Signal Connections

PORT PIN DEVICE INPUT

SIGNAL MODULE INPUT

NAME MODULE BLOCK MODULE OUTPUT

SIGNAL DEVICE OUTPUT

SIGNAL

P1.6 TA1CLK TACLK

Timer N/AACLK (internal) ACLK

SMCLK (internal) SMCLK

CCI0A

CCR0 TA0

Timer0_A3 CCR0B

output (internal) CCI0B

DVSS GND

DVCC VCC

P1.5 TA1.1 CCI1A

CCR1 TA1

TA1.1

Timer0_A3 CCR1B

output (internal) CCI1B to ADC trigger

DVSS GND

DVCC VCC

P1.4 TA1.2 CCI2A

CCR2 TA2

TA1.2

Timer0_A3 CCR2B

output (internal) CCI2B IR Input

DVSS GND

DVCC VCC

The interconnection of Timer0_A3 and Timer1_A3 can be used to modulate the eUSCI_A pin of

UCA0TXD/UCA0SIMO in either ASK or FSK mode, with which a user can easily acquire a modulated

infrared command for directly driving an external IR diode. The IR functions are fully controlled by SYS

configuration registers 1 including IREN (enable), IRPSEL (polarity select), IRMSEL (mode select),

IRDSSEL (data select), and IRDATA (data) bits. For more information, see the System Resets, Interrupts,

and Operating Modes, System Control Module (SYS) chapter in the MP430FR4xx and MP430FR2xx

Family User's Guide.

The Timer2_A2 and Timer3_A2 modules are 16-bit timers and counters with two capture/compare

registers each. Both timers support multiple captures or compares and interval timing (see Table 6-13 and

Table 6-14). Both timers have extensive interrupt capabilities. Interrupts may be generated from the

counter on overflow conditions and from each capture register.

The CCR0 registers on Timer2_TA2 and Timer3_TA2 are not externally connected and can be used only

for hardware period timing and interrupt generation. In Up mode, these CCR0 registers can be used to set

the overflow value of the counter. Timer2_A2 and Timer3_A2 are only internally connected and do not

support PWM output.

Table 6-13. Timer2_A2 Signal Connections

DEVICE INPUT SIGNAL MODULE INPUT NAME MODULE BLOCK MODULE OUTPUT

SIGNAL DEVICE OUTPUT SIGNAL

ACLK (internal) ACLK Timer N/A

SMCLK (internal) SMCLK

CCI0A

CCR0 TA0

CCI0B Timer3_A3 CCI0B input

DVSS GND

DVCC VCC

CCI1A

CCR1 CCR1

CCI1B Timer3_A3 CCI1B input

DVSS GND

DVCC VCC

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Table 6-14. Timer3_A2 Signal Connections

DEVICE INPUT SIGNAL MODULE INPUT NAME MODULE BLOCK MODULE OUTPUT

SIGNAL DEVICE OUTPUT SIGNAL

ACLK (internal) ACLK Timer N/A

SMCLK (internal) SMCLK

CCI0A

CCR0 TA0

Timer3_A3 CCI0B input CCI0B

DVSS GND

DVCC VCC

CCI1A

CCR1 CCR1

Timer3_A3 CCI1B input CCI1B

DVSS GND

DVCC VCC

6.10.9 Hardware Multiplier (MPY)

The multiplication operation is supported by a dedicated peripheral module. The module performs

operations with 32-, 24-, 16-, and 8-bit operands. The MPY module supports signed multiplication,

unsigned multiplication, signed multiply-and-accumulate, and unsigned multiply-and-accumulate

operations.

6.10.10 Backup Memory (BAKMEM)

The BAKMEM supports data retention during LPM3.5. This device provides up to 32 bytes that are

retained during LPM3.5.

6.10.11 Real-Time Clock (RTC)

The RTC is a 16-bit modulo counter that is functional in AM, LPM0, LPM3, and LPM3.5. This module may

periodically wake up the CPU from LPM0, LPM3, and LPM3.5 based on timing from a low-power clock

source such as the XT1 and VLO clocks. In AM, SMCLK can drive the RTC to generate high-frequency

timing events and interrupts. The RTC overflow events trigger:

• Timer0_A3 CCR1B

• ADC conversion trigger when ADCSHSx bits are set as 01b

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6.10.12 10-Bit Analog-to-Digital Converter (ADC)

The 10-bit ADC module supports fast 10-bit analog-to-digital conversions with single-ended input. The

module implements a 10-bit SAR core, sample select control, reference generator and a conversion result

buffer. A window comparator with lower and upper limits allows CPU-independent result monitoring with

three window comparator interrupt flags.

The ADC supports 10 external inputs and 4 internal inputs (see Table 6-15).

(1) When A4 is used, the PMM 1.2-V reference voltage can be output to this pin by setting the PMM

control register. The 1.2-V voltage can be directly measured by A4 channel.

Table 6-15. ADC Channel Connections

ADCINCHx ADC CHANNELS EXTERNAL PINOUT

0 A0/Veref+ P1.0

1 A1 P1.1

2 A2/Veref- P1.2

3 A3 P1.3

4 A4(1) P1.4

5 A5 P1.5

6 A6 P1.6

7 A7 P1.7

8 A8 NA

9 A9 NA

10 Not used N/A

11 Not used N/A

12 On-chip temperature sensor N/A

13 Reference voltage (1.5 V) N/A

14 DVSS N/A

15 DVCC N/A

Software or a hardware trigger can start the analog-to-digital conversion. Table 6-16 lists the trigger

sources that are available.

Table 6-16. ADC Trigger Signal Connections

ADCSHSx TRIGGER SOURCE

BINARY DECIMAL

00 0 ADCSC bit (software trigger)

01 1 RTC event

10 2 TA1.1B

11 3 --

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6.10.13 CapTIvate Technology

The CapTIvate module detects the capacitance changed with a charge-transfer method and is functional

in AM, LPM0, LPM3, and LPM4. The CapTIvate module can periodically wake the CPU from LPM0,

LPM3, or LPM4 based on a CapTIvate timer source such as ACLK or VLO clock. The CapTIvate module

supports the following touch-sensing capability:

• Up to 64 CapTIvate buttons composed of 4 CapTIvate blocks. Each block consists of 4 I/Os, and these

blocks scan in parallel of 4 electrodes.

• Each block can be individually configured in self or mutual mode. Each CapTIvate I/O can be used for

either self or mutual electrodes.

• Supports a wake-on-touch state machine.

• Supports synchronized conversion on a zero-crossing event trigger.

• Processing logic to perform filter calculation and threshold detection.

To learn more about MSP MCUs featuring CapTIvate technology, see the CapTIvate™ Technology Guide.

6.10.14 Embedded Emulation Module (EEM)

The EEM supports real-time in-system debugging. The EEM on these devices has the following features:

• Three hardware triggers or breakpoints on memory access

• One hardware trigger or breakpoint on CPU register write access

• Up to four hardware triggers that can be combined to form complex triggers or breakpoints

• One cycle counter

• Clock control on module level

• EEM version: S

Edge

Select

P1IES.x

P1IFG.x

P1 Interrupt

P1IE.x

P1IN.x

To module

P1SEL.x

From Module1

P1OUT.x

P1DIR.x

From SYS (ADCPCTLx)

A0..A7

From Module1

DVCC

DVSS

P1REN.x

Bus

Keeper

From JTAG

To JTAG

P1.0/UCB0STE/TA0CLK/A0/Veref+

P1.1/UCB0CLK/TA0.1/A1

P1.2/UCB0SIMO/UCB0SDA/TA0.2/A2/Veref-

P1.3/UCB0SOMI/UCB0SCL/MCLK/A3

P1.4/UCA0TXD/UCA0SIMO/TA1.2/TCK/A4/VREF+

P1.5/UCA0RXD/UCA0SOMI/TA1.1/TMS/A5

P1.6/UCA0CLK/TA1CLK/TDI/TCLK/A6

P1.7/UCA0STE/SMCLK/TDO/A7

2 bit

From Module2

DVSS

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6.11 Input/Output Diagrams

6.11.1 Port P1 Input/Output With Schmitt Trigger

Figure 6-1 shows the port diagram. Table 6-17 summarizes the selection of pin function.

Figure 6-1. Port P1 (P1.0 to P1.7) Input/Output With Schmitt Trigger

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(1) X = don't care

(2) Setting the ADCPCTLx bit in SYSCFG2 register disables both the output driver and input Schmitt trigger to prevent leakage when

analog signals are applied.

Table 6-17. Port P1 (P1.0 to P1.7) Pin Functions

PIN NAME (P1.x) x FUNCTION CONTROL BITS AND SIGNALS(1)

P1DIR.x P1SELx ADCPCTLx(2) JTAG

P1.0/UCB0STE/

TA0CLK/A0 0

P1.0 (I/O) I: 0; O: 1 00 0 N/A

UCB0STE X 01 0 N/A

TA0CLK 0 10 0 N/A

A0/Veref+ X X 1 (x = 0) N/A

P1.1/UCB0CLK/TA0.1/

A1 1

P1.1 (I/O) I: 0; O: 1 00 0 N/A

UCB0CLK X 01 0 N/A

TA0.CCI1A 0 10 0 N/A

TA0.1 1

A1 X X 1 (x = 1) N/A

P1.2/UCB0SIMO/

UCB0SDA/TA0.2/A2 2

P1.2 (I/O) I: 0; O: 1 00 0 N/A

UCB0SIMO/UCB0SDA X 01 0 N/A

TA0.CCI2A 0 10 0 N/A

TA0.2 1

A2/Veref- X X 1 (x = 2) N/A

P1.3/UCB0SOMI/

UCB0SCL/MCLK/A3 3

P1.3 (I/O) I: 0; O: 1 00 0 N/A

UCB0SOMI/UCB0SCL X 01 0 N/A

MCLK 1 10 0 N/A

A3 X X 1 (x = 3) N/A

P1.4/UCA0TXD/

UCA0SIMO/TA1.2/TCK/

A4 /VREF+ 4

P1.4 (I/O) I: 0; O: 1 00 0 Disabled

UCA0TXD/UCA0SIMO X 01 0 Disabled

TA1.CCI2A 0 10 0 Disabled

TA1.2 1

A4, VREF+ X X 1 (x = 4) Disabled

JTAG TCK X X X TCK

P1.5/UCA0RXD/

UCA0SOMI/TA1.1/TMS/

A5 5

P1.5 (I/O) I: 0; O: 1 00 0 Disabled

UCA0RXD/UCA0SOMI X 01 0 Disabled

TA1.CCI1A 0 10 0 Disabled

TA1.1 1

A5 X X 1 (x = 5) Disabled

JTAG TMS X X X TMS

P1.6/UCA0CLK/

TA1CLK/TDI/TCLK/A6 6

P1.6 (I/O) I: 0; O: 1 00 0 Disabled

UCA0CLK X 01 Disabled

TA1CLK 0 10 0 Disabled

A6 X X 1 (x = 6) Disabled

JTAG TDI/TCLK X X X TDI/TCLK

P1.7/UCA0STE/SMCLK/

TDO/A7 7

P1.7 (I/O) I: 0; O: 1 00 0 Disabled

UCA0STE X 01 0 Disabled

SMCLK 1 10 0 Disabled

A7 X X 1 (x = 7) Disabled

JTAG TDO X X X TDO

———————————— ____________

Edge

Select

P2IES.x

P2IFG.x

P2 Interrupt

P2IE.x

P2IN.x

To module

P2SEL.x

From Module1

P2OUT.x

P2DIR.x

DVCC

DVSS

P2REN.x

Bus

Keeper

2 bit

DVSS

P2.0/XOUT

P2.1/XIN

P2.2/SYNC/ACLK

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(1) X = don't care

6.11.2 Port P2 (P2.0 to P2.2) Input/Output With Schmitt Trigger

Figure 6-2 shows the port diagram. Table 6-18 summarizes the selection of pin function.

Figure 6-2. Port P2 (P2.0 to P2.2) Input/Output With Schmitt Trigger

Table 6-18. Port P2 (P2.0 to P2.2) Pin Functions

PIN NAME (P2.x) x FUNCTION CONTROL BITS AND SIGNALS(1)

P2DIR.x P2SELx

P2.0/XOUT 0 P2.0 (I/O) I: 0; O: 1 00

XOUT X 01

P2.1/XIN 1 P2.1 (I/O) I: 0; O: 1 00

XIN X 01

P2.2/SYNC/ACLK 2

P2.2 (I/O) I: 0; O: 1 00

SYNC 0 01

ACLK 1 10

‘5‘ TEXAS INSTRUMENTS

Edge

Select

P2IES.x

P2IFG.x

P2 Interrupt

P2IE.x

P2IN.x

To module

P2SEL.x

From Module1

P2OUT.x

P2DIR.x

From CapTIvate

CAP0.2, CAP1.1, CAP1.2

CAP1.3, CAP3.0

From Module1

DVCC

DVSS

P2REN.x

Bus

Keeper

P2.4/UCA1CLK/CAP1.1

P2.5/UCA1RXD/UCA1SOMI/CAP1.2

P2.6/UCA1TXD/UCA1SIMO/CAP1.3

P2.7/CAP3.0

P2.3/CAP0.2

2 bit

DVSS

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6.11.3 Port P2 (P2.3 to P2.7) Input/Output With Schmitt Trigger

Figure 6-3 shows the port diagram. Table 6-19 summarizes the selection of pin function.

Figure 6-3. Port P2 (P2.3 to P2.7) Input/Output With Schmitt Trigger

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(1) X = don't care

Table 6-19. Port P2 (P2.3 to P2.7) Pin Functions

PIN NAME (P2.x) x FUNCTION

CONTROL BITS AND SIGNALS(1)

P2DIR.x P2SELx ANALOG

FUNCTION

P2.3/CAP0.2 3 P2.3 (I/O) I: 0; O: 1 00 0

CAP0.2 X X 1

P2.4/UCA1CLK/

CAP1.1 4

P2.4 (I/O) I: 0; O: 1 00 0

UCA1CLK X 01 0

CAP1.1 X X 1

P2.5/UCA1RXD/

UCA1SOMI/CAP1.2 5

P2.5 (I/O) I: 0; O: 1 00 0

UCA1RXD/UCA1SOMI X 01 0

CAP1.2 X X 1

P2.6/UCA1TXD/

UCA1SIMO/CAP1.3 6

P2.6 (I/O) I: 0; O: 1 00 0

UCA1TXD/UCA1SIMO X 01 0

CAP1.3 X X 1

P2.7/CAP3.0 7 P2.7 (I/O) I: 0; O: 1 0 0

CAP3.0 X X 1

‘5‘ TEXAS INSTRUMENTS P3 2/CAP3 2

P3IN.x

To module

P3SEL.x

From Module1

P3OUT.x

P3DIR.x

From CapTIvate

CAP0.0, CAP1.0, CAP3.2

From Module1

DVCC

DVSS

P3REN.x

Bus

Keeper

2 bit

DVSS

P3.0/CAP0.0

P3.1/UCA1STE/CAP1.0

P3.2/CAP3.2

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6.11.4 Port P3 (P3.0 to P3.2) Input/Output With Schmitt Trigger

Figure 6-4 shows the port diagram. Table 6-20 summarizes the selection of pin function.

Figure 6-4. Port P3 (P3.0 to P3.2) Input/Output With Schmitt Trigger

NOTE

CapTIvate shared with I/Os configuration

The CapTIvate function and GPIOs are powered by different power supplies (1.5 V and

3.3 V, respectively).

To prevent pad damage when changing the function, TI recommends checking the external

application circuit of each pad before enabling the alternate function.

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(1) X = don't care

Table 6-20. Port P3 (P3.0 to P3.2) Pin Functions

PIN NAME (P3.x) x FUNCTION

CONTROL BITS AND SIGNALS(1)

P3DIR.x P3SEL.x ANALOG

FUNCTION

P3.0/CAP0.0 0 P3.0 (I/O) I: 0; O: 1 00 0

CAP0.0 X X 1

P3.1/UCA1STE/

CAP1.0 1

P3.1 (I/O) I: 0; O: 1 00 0

UCA1STE X 01 0

CAP1.0 X X 1

P3.2/CAP3.2 2 P3.2 (I/O) I: 0; O: 1 00 0

CAP3.2 X X 1

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6.12 Device Descriptors

Table 6-21 lists the Device IDs of the devices. Table 6-22 lists the contents of the device descriptor tag-

length-value (TLV) structure for the devices.

Table 6-21. Device IDs

DEVICE DEVICE ID

1A05h 1A04h

MSP430FR2633 82h 3Ch

MSP430FR2533 82h 3Dh

MSP430FR2632 82h 3Eh

MSP430FR2532 82h 3Fh

(1) The CRC value covers the checksum from 0x1A04h to 0x1AF5h by applying the CRC-CCITT-16 polynomial of x16 + x12 + x5+ 1.

Table 6-22. Device Descriptors

DESCRIPTION

MSP430FR2633, MSP430FR2632,

MSP430FR2533, MSP430FR2532

ADDRESS VALUE

Information Block

Info length 1A00h 06h

CRC length 1A01h 06h

CRC value(1) 1A02h Per unit

1A03h Per unit

Device ID 1A04h See Table 6-21.

1A05h

Hardware revision 1A06h Per unit

Firmware revision 1A07h Per unit

Die Record

Die record tag 1A08h 08h

Die record length 1A09h 0Ah

Lot wafer ID

1A0Ah Per unit

1A0Bh Per unit

1A0Ch Per unit

1A0Dh Per unit

Die X position 1A0Eh Per unit

1A0Fh Per unit

Die Y position 1A10h Per unit

1A11h Per unit

Test result 1A12h Per unit

1A13h Per unit

ADC Calibration

ADC calibration tag 1A14h Per unit

ADC calibration length 1A15h Per unit

ADC gain factor 1A16h Per unit

1A17h Per unit

ADC offset 1A18h Per unit

1A19h Per unit

ADC 1.5-V reference temperature 30°C 1A1Ah Per unit

1A1Bh Per unit

ADC 1.5-V reference temperature 85°C 1A1Ch Per unit

1A1Dh Per unit

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Table 6-22. Device Descriptors (continued)

DESCRIPTION

MSP430FR2633, MSP430FR2632,

MSP430FR2533, MSP430FR2532

ADDRESS VALUE

(2) This value can be directly loaded into DCO bits in CSCTL0 registers to get accurate 16-MHz frequency at room temperature, especially

when the MCU exits from LPM3 and below. TI suggests using the predivider to decrease the frequency if the temperature drift might

result an overshoot beyond 16 MHz.

Reference and DCO Calibration

Calibration tag 1A1Eh 12h

Calibration length 1A1Fh 04h

1.5-V reference factor 1A20h Per unit

1A21h Per unit

DCO tap setting for 16 MHz, temperature 30°C(2) 1A22h Per unit

1A23h Per unit

(1) The Program FRAM can be write protected by setting the PFWP bit in the SYSCFG0 register. See the SYS chapter in the

MSP430FR4xx and MSP430FR2xx Family User's Guide for more details.

(2) The Information FRAM can be write protected by setting the DFWP bit in the SYSCFG0 register. See the SYS chapter in the

MSP430FR4xx and MSP430FR2xx Family User's Guide for more details.

6.13 Memory

6.13.1 Memory Organization

Table 6-23 summarizes the memory map of the devices.

Table 6-23. Memory Organization

ACCESS MSP430FR2633 MSP430FR2632 MSP430FR2533 MSP430FR2532

Memory (FRAM)

Main: interrupt vectors and

signatures

Main: code memory

Read/Write

(Optional Write

Protect)(1)

15KB

FFFFh to FF80h

FFFFh to C400h

8KB

FFFFh to FF80h

FFFFh to E000h

15KB

FFFFh to FF80h

FFFFh to C400h

8KB

FFFFh to FF80h

FFFFh to E000h

RAM Read/Write 4KB

2FFFh to 2000h 2KB

27FFh to 2000h 2KB

27FFh to 2000h 1KB

23FFh to 2000h

Information Memory (FRAM) Read/Write

(Optional Write

Protect)(2)

512 bytes

19FFh to 1800h 512 bytes

19FFh to 1800h

Bootstrap loader (BSL1)

Memory (ROM) Read only 2KB

17FFh to 1000h 2KB

17FFh to 1000h

Bootstrap loader (BSL2)

Memory (ROM) Read only 1KB

FFFFFh to FFC00h 1KB

FFFFFh to FFC00h

CapTIvate Libraries and

Driver Libraries (ROM) Read only 12KB

6FFFh to 4000h 12KB

6FFFh to 4000h

Peripherals Read/Write 4KB

0FFFh to 0000h 4KB

0FFFh to 0000h

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6.13.2 Peripheral File Map

Table 6-24 lists the available peripherals and the register base address for each. Table 6-25 to list the

registers and address offsets for each peripheral.

Table 6-24. Peripherals Summary

MODULE NAME BASE ADDRESS SIZE

Special Functions (See Table 6-25) 0100h 0010h

PMM (See Table 6-26) 0120h 0020h

SYS (See Table 6-27) 0140h 0040h

CS (See Table 6-28) 0180h 0020h

FRAM (See Table 6-29) 01A0h 0010h

CRC (See Table 6-30) 01C0h 0008h

WDT (See Table 6-31) 01CCh 0002h

Port P1, P2 (See Table 6-32) 0200h 0020h

Port P3 (See Table 6-33) 0220h 0020h

RTC (See Table 6-34) 0300h 0010h

Timer0_A3 (See Table 6-35) 0380h 0030h

Timer1_A3 (See Table 6-36) 03C0h 0030h

Timer2_A2 (See Table 6-37) 0400h 0030h

Timer3_A2 (See Table 6-38) 0440h 0030h

MPY32 (See Table 6-39) 04C0h 0030h

eUSCI_A0 (See Table 6-40) 0500h 0020h

eUSCI_A1 (See Table 6-41) 0520h 0020h

eUSCI_B0 (See Table 6-42) 0540h 0030h

Backup Memory (See Table 6-43) 0660h 0020h

ADC (See Table 6-44) 0700h 0040h

CapTIvate (See CapTivate Design Center for details) 0A00h 0200h

Table 6-25. Special Function Registers (Base Address: 0100h)

SFR interrupt enable SFRIE1 00h

SFR interrupt flag SFRIFG1 02h

SFR reset pin control SFRRPCR 04h

Table 6-26. PMM Registers (Base Address: 0120h)

PMM control 0 PMMCTL0 00h

PMM control 1 PMMCTL1 02h

PMM control 2 PMMCTL2 04h

PMM interrupt flags PMMIFG 0Ah

PM5 control 0 PM5CTL0 10h

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Table 6-27. SYS Registers (Base Address: 0140h)

System control SYSCTL 00h

Bootloader configuration area SYSBSLC 02h

JTAG mailbox control SYSJMBC 06h

JTAG mailbox input 0 SYSJMBI0 08h

JTAG mailbox input 1 SYSJMBI1 0Ah

JTAG mailbox output 0 SYSJMBO0 0Ch

JTAG mailbox output 1 SYSJMBO1 0Eh

Bus error vector generator SYSBERRIV 18h

User NMI vector generator SYSUNIV 1Ah

System NMI vector generator SYSSNIV 1Ch

Reset vector generator SYSRSTIV 1Eh

System configuration 0 SYSCFG0 20h

System configuration 1 SYSCFG1 22h

System configuration 2 SYSCFG2 24h

Table 6-28. CS Registers (Base Address: 0180h)

CS control 0 CSCTL0 00h

CS control 1 CSCTL1 02h

CS control 2 CSCTL2 04h

CS control 3 CSCTL3 06h

CS control 4 CSCTL4 08h

CS control 5 CSCTL5 0Ah

CS control 6 CSCTL6 0Ch

CS control 7 CSCTL7 0Eh

CS control 8 CSCTL8 10h

Table 6-29. FRAM Registers (Base Address: 01A0h)

FRAM control 0 FRCTL0 00h

General control 0 GCCTL0 04h

General control 1 GCCTL1 06h

Table 6-30. CRC Registers (Base Address: 01C0h)

CRC data input CRC16DI 00h

CRC data input reverse byte CRCDIRB 02h

CRC initialization and result CRCINIRES 04h

CRC result reverse byte CRCRESR 06h

Table 6-31. WDT Registers (Base Address: 01CCh)

Watchdog timer control WDTCTL 00h

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Table 6-32. Port P1, P2 Registers (Base Address: 0200h)

Port P1 input P1IN 00h

Port P1 output P1OUT 02h

Port P1 direction P1DIR 04h

Port P1 pulling enable P1REN 06h

Port P1 selection 0 P1SEL0 0Ah

Port P1 selection 1 P1SEL1 0Ch

Port P1 interrupt vector word P1IV 0Eh

Port P1 complement selection P1SELC 16h

Port P1 interrupt edge select P1IES 18h

Port P1 interrupt enable P1IE 1Ah

Port P1 interrupt flag P1IFG 1Ch

Port P2 input P2IN 01h

Port P2 output P2OUT 03h

Port P2 direction P2DIR 05h

Port P2 pulling enable P2REN 07h

Port P2 selection 0 P2SEL0 0Bh

Port P2 selection 1 P2SEL1 0Dh

Port P2 interrupt vector word P2IV 1Eh

Port P2 complement selection P2SELC 17h

Port P2 interrupt edge select P2IES 19h

Port P2 interrupt enable P2IE 1Bh

Port P2 interrupt flag P2IFG 1Dh

Table 6-33. Port P3 Registers (Base Address: 0220h)

Port P3 input P3IN 00h

Port P3 output P3OUT 02h

Port P3 direction P3DIR 04h

Port P3 pulling enable P3REN 06h

Port P3 selection 0 P3SEL0 0Ah

Port P3 selection 1 P3SEL1 0

Port P3 complement selection P3SELC 16h

Table 6-34. RTC Registers (Base Address: 0300h)

RTC control RTCCTL 00h

RTC interrupt vector RTCIV 04h

RTC modulo RTCMOD 08h

RTC counter RTCCNT 0Ch

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Table 6-35. Timer0_A3 Registers (Base Address: 0380h)

TA0 control TA0CTL 00h

Capture/compare control 0 TA0CCTL0 02h

Capture/compare control 1 TA0CCTL1 04h

Capture/compare control 2 TA0CCTL2 06h

TA0 counter TA0R 10h

Capture/compare 0 TA0CCR0 12h

Capture/compare 1 TA0CCR1 14h

Capture/compare 2 TA0CCR2 16h

TA0 expansion 0 TA0EX0 20h

TA0 interrupt vector TA0IV 2Eh

Table 6-36. Timer1_A3 Registers (Base Address: 03C0h)

TA1 control TA1CTL 00h

Capture/compare control 0 TA1CCTL0 02h

Capture/compare control 1 TA1CCTL1 04h

Capture/compare control 2 TA1CCTL2 06h

TA1 counter TA1R 10h

Capture/compare 0 TA1CCR0 12h

Capture/compare 1 TA1CCR1 14h

Capture/compare 2 TA1CCR2 16h

TA1 expansion 0 TA1EX0 20h

TA1 interrupt vector TA1IV 2Eh

Table 6-37. Timer2_A2 Registers (Base Address: 0400h)

TA2 control TA2CTL 00h

Capture/compare control 0 TA2CCTL0 02h

Capture/compare control 1 TA2CCTL1 04h

TA2 counter TA2R 10h

Capture/compare 0 TA2CCR0 12h

Capture/compare 1 TA2CCR1 14h

TA2 expansion 0 TA2EX0 20h

TA2 interrupt vector TA2IV 2Eh

Table 6-38. Timer3_A2 Registers (Base Address: 0440h)

TA3 control TA3CTL 00h

Capture/compare control 0 TA3CCTL0 02h

Capture/compare control 1 TA3CCTL1 04h

TA3 counter TA3R 10h

Capture/compare 0 TA3CCR0 12h

Capture/compare 1 TA3CCR1 14h

TA3 expansion 0 TA3EX0 20h

TA3 interrupt vector TA3IV 2Eh

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Table 6-39. MPY32 Registers (Base Address: 04C0h)

16-bit operand 1 – multiply MPY 00h

16-bit operand 1 – signed multiply MPYS 02h

16-bit operand 1 – multiply accumulate MAC 04h

16-bit operand 1 – signed multiply accumulate MACS 06h

16-bit operand 2 OP2 08h

16 × 16 result low word RESLO 0Ah

16 × 16 result high word RESHI 0Ch

16 × 16 sum extension SUMEXT 0Eh

32-bit operand 1 – multiply low word MPY32L 10h

32-bit operand 1 – multiply high word MPY32H 12h

32-bit operand 1 – signed multiply low word MPYS32L 14h

32-bit operand 1 – signed multiply high word MPYS32H 16h

32-bit operand 1 – multiply accumulate low word MAC32L 18h

32-bit operand 1 – multiply accumulate high word MAC32H 1Ah

32-bit operand 1 – signed multiply accumulate low word MACS32L 1Ch

32-bit operand 1 – signed multiply accumulate high word MACS32H 1Eh

32-bit operand 2 – low word OP2L 20h

32-bit operand 2 – high word OP2H 22h

32 × 32 result 0 – least significant word RES0 24h

32 × 32 result 1 RES1 26h

32 × 32 result 2 RES2 28h

32 × 32 result 3 – most significant word RES3 2Ah

MPY32 control 0 MPY32CTL0 2Ch

Table 6-40. eUSCI_A0 Registers (Base Address: 0500h)

eUSCI_A control word 0 UCA0CTLW0 00h

eUSCI_A control word 1 UCA0CTLW1 02h

eUSCI_A control rate 0 UCA0BR0 06h

eUSCI_A control rate 1 UCA0BR1 07h

eUSCI_A modulation control UCA0MCTLW 08h

eUSCI_A status UCA0STAT 0Ah

eUSCI_A receive buffer UCA0RXBUF 0Ch

eUSCI_A transmit buffer UCA0TXBUF 0Eh

eUSCI_A LIN control UCA0ABCTL 10h

eUSCI_A IrDA transmit control lUCA0IRTCTL 12h

eUSCI_A IrDA receive control IUCA0IRRCTL 13h

eUSCI_A interrupt enable UCA0IE 1Ah

eUSCI_A interrupt flags UCA0IFG 1Ch

eUSCI_A interrupt vector word UCA0IV 1Eh

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Table 6-41. eUSCI_A1 Registers (Base Address: 0520h)

eUSCI_A control word 0 UCA1CTLW0 00h

eUSCI_A control word 1 UCA1CTLW1 02h

eUSCI_A control rate 0 UCA1BR0 06h

eUSCI_A control rate 1 UCA1BR1 07h

eUSCI_A modulation control UCA1MCTLW 08h

eUSCI_A status UCA1STAT 0Ah

eUSCI_A receive buffer UCA1RXBUF 0Ch

eUSCI_A transmit buffer UCA1TXBUF 0Eh

eUSCI_A LIN control UCA1ABCTL 10h

eUSCI_A IrDA transmit control lUCA1IRTCTL 12h

eUSCI_A IrDA receive control IUCA1IRRCTL 13h

eUSCI_A interrupt enable UCA1IE 1Ah

eUSCI_A interrupt flags UCA1IFG 1Ch

eUSCI_A interrupt vector word UCA1IV 1Eh

Table 6-42. eUSCI_B0 Registers (Base Address: 0540h)

eUSCI_B control word 0 UCB0CTLW0 00h

eUSCI_B control word 1 UCB0CTLW1 02h

eUSCI_B bit rate 0 UCB0BR0 06h

eUSCI_B bit rate 1 UCB0BR1 07h

eUSCI_B status word UCB0STATW 08h

eUSCI_B byte counter threshold UCB0TBCNT 0Ah

eUSCI_B receive buffer UCB0RXBUF 0Ch

eUSCI_B transmit buffer UCB0TXBUF 0Eh

eUSCI_B I2C own address 0 UCB0I2COA0 14h

eUSCI_B I2C own address 1 UCB0I2COA1 16h

eUSCI_B I2C own address 2 UCB0I2COA2 18h

eUSCI_B I2C own address 3 UCB0I2COA3 1Ah

eUSCI_B receive address UCB0ADDRX 1Ch

eUSCI_B address mask UCB0ADDMASK 1Eh

eUSCI_B I2C slave address UCB0I2CSA 20h

eUSCI_B interrupt enable UCB0IE 2Ah

eUSCI_B interrupt flags UCB0IFG 2Ch

eUSCI_B interrupt vector word UCB0IV 2Eh

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Table 6-43. Backup Memory Registers (Base Address: 0660h)

Backup memory 0 BAKMEM0 00h

Backup memory 1 BAKMEM1 02h

Backup memory 2 BAKMEM2 04h

Backup memory 3 BAKMEM3 06h

Backup memory 4 BAKMEM4 08h

Backup memory 5 BAKMEM5 0Ah

Backup memory 6 BAKMEM6 0Ch

Backup memory 7 BAKMEM7 0Eh

Backup memory 8 BAKMEM8 10h

Backup memory 9 BAKMEM9 12h

Backup memory 10 BAKMEM10 14h

Backup memory 11 BAKMEM11 16h

Backup memory 12 BAKMEM12 18h

Backup memory 13 BAKMEM13 1Ah

Backup memory 14 BAKMEM14 1Ch

Backup memory 15 BAKMEM15 1Eh

Table 6-44. ADC Registers (Base Address: 0700h)

ADC control 0 ADCCTL0 00h

ADC control 1 ADCCTL1 02h

ADC control 2 ADCCTL2 04h

ADC window comparator low threshold ADCLO 06h

ADC window comparator high threshold ADCHI 08h

ADC memory control 0 ADCMCTL0 0Ah

ADC conversion memory ADCMEM0 12h

ADC interrupt enable ADCIE 1Ah

ADC interrupt flags ADCIFG 1Ch

ADC interrupt vector word ADCIV 1Eh

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6.14 Identification

6.14.1 Revision Identification

The device revision information is included as part of the top-side marking on the device package. The

device-specific errata sheet describes these markings (see Section 8.4).

The hardware revision is also stored in the Device Descriptor structure in the Information Block section.

For details on this value, see the Hardware Revision entries in Table 6-22.

6.14.2 Device Identification

The device type can be identified from the top-side marking on the device package. The device-specific

errata sheet describes these markings (see Section 8.4).

A device identification value is also stored in the Device Descriptor structure in the Information Block

section. For details on this value, see the Device ID entries in Table 6-22.

6.14.3 JTAG Identification

Programming through the JTAG interface, including reading and identifying the JTAG ID, is described in

MSP430 Programming With the JTAG Interface.

l TEXAS INSTRUMENTS H:

CL1 CL2

XIN XOUT

Digital

Power Supply

Decoupling

100 nF10 Fµ

DVCC

DVSS

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7 Applications, Implementation, and Layout

NOTE

Information in the following Applications section is not part of the TI component specification,

and TI does not warrant its accuracy or completeness. TI's customers are responsible for

determining suitability of components for their purposes. Customers should validate and test

their design implementation to confirm system functionality.

7.1 Device Connection and Layout Fundamentals

This section discusses the recommended guidelines when designing with the MSP430 devices. These

guidelines are to make sure that the device has proper connections for powering, programming,

debugging, and optimum analog performance.

7.1.1 Power Supply Decoupling and Bulk Capacitors

TI recommends connecting a combination of a 10-µF and a 100-nF low-ESR ceramic decoupling capacitor

to the DVCC and DVSS pins (see Figure 7-1). Higher-value capacitors may be used but can impact

supply rail ramp-up time. Decoupling capacitors must be placed as close as possible to the pins that they

decouple (within a few millimeters). Additionally, TI recommends separated grounds with a single-point

connection for better noise isolation from digital-to-analog circuits on the board and to achieve high analog

accuracy.

Figure 7-1. Power Supply Decoupling

7.1.2 External Oscillator

This device supports only a low-frequency crystal (32 kHz) on the XIN and XOUT pins. External bypass

capacitors for the crystal oscillator pins are required.

It is also possible to apply digital clock signals to the XIN input pin that meet the specifications of the

respective oscillator if the appropriate XT1BYPASS mode is selected. In this case, the associated XOUT

pin can be used for other purposes. If the XIN and XOUT pins are not used, they must be terminated

according to Section 4.6.

Figure 7-2 shows a typical connection diagram.

Figure 7-2. Typical Crystal Connection

‘5‘ TEXAS INSTRUMENTS

TDO/TDI

TDI

TMS

TCK

GND

TEST

JTAG

VCC TOOL

VCC TARGET

J1 (see Note A)

J2 (see Note A)

VCC

47 kW

DVCC

RST/NMI/SBWTDIO

TDO/TDI

TDI

TMS

TCK

TEST/SBWTCK

DVSS

MSP430FRxxx

1 nF

(see Note B)

RST

Important to connect

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See MSP430 32-kHz Crystal Oscillators for more information on selecting, testing, and designing a crystal

oscillator with the MSP430 devices.

7.1.3 JTAG

With the proper connections, the debugger and a hardware JTAG interface (such as the MSP-FET or

MSP-FET430UIF) can be used to program and debug code on the target board. In addition, the

connections also support the MSP-GANG production programmers, thus providing an easy way to

program prototype boards, if desired. Figure 7-3 shows the connections between the 14-pin JTAG

connector and the target device required to support in-system programming and debugging for 4-wire

JTAG communication. Figure 7-4 shows the connections for 2-wire JTAG mode (Spy-Bi-Wire).

The connections for the MSP-FET and MSP-FET430UIF interface modules and the MSP-GANG are

identical. Both can supply VCC to the target board (through pin 2). In addition, the MSP-FET and MSP-

FET430UIF interface modules and MSP-GANG have a VCC sense feature that, if used, requires an

alternate connection (pin 4 instead of pin 2). The VCC sense feature detects the local VCC present on the

target board (that is, a battery or other local power supply) and adjusts the output signals accordingly.

Figure 7-3 and Figure 7-4 show a jumper block that supports both scenarios of supplying VCC to the target

board. If this flexibility is not required, the desired VCC connections may be hard-wired to eliminate the

jumper block. Pins 2 and 4 must not be connected at the same time.

For additional design information regarding the JTAG interface, see the MSP430 Hardware Tools User's

Guide.

A. If a local target power supply is used, make connection J1. If power from the debug or programming adapter is used,

make connection J2.

B. The upper limit for C1 is 1.1 nF when using current TI tools.

Figure 7-3. Signal Connections for 4-Wire JTAG Communication

‘5‘ TEXAS INSTRUMENTS

TEST/SBWTCK

MSP430FRxxx

RST/NMI/SBWTDIO

TDO/TDI

TCK

GND

JTAG

47 kΩ

(see Note B)

VCC TOOL

VCC TARGET

1 nF

(see Note B)

J1 (see Note A)

J2 (see Note A)

Important to connect

DVCC

DVSS

VCC

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A. Make connection J1 if a local target power supply is used, or make connection J2 if the target is powered from the

debug or programming adapter.

B. The device RST/NMI/SBWTDIO pin is used in 2-wire mode for bidirectional communication with the device during

JTAG access, and any capacitance that is attached to this signal may affect the ability to establish a connection with

the device. The upper limit for C1 is 1.1 nF when using current TI tools.

Figure 7-4. Signal Connections for 2-Wire JTAG Communication (Spy-Bi-Wire)

7.1.4 Reset

The reset pin can be configured as a reset function (default) or as an NMI function in the Special Function

In reset mode, the RST/NMI pin is active low, and a pulse applied to this pin that meets the reset timing

specifications generates a BOR-type device reset.

Setting SYSNMI causes the RST/NMI pin to be configured as an external NMI source. The external NMI is

edge sensitive, and its edge is selectable by SYSNMIIES. Setting the NMIIE enables the interrupt of the

external NMI. When an external NMI event occurs, the NMIIFG is set.

The RST/NMI pin can have either a pullup or pulldown that is enabled or not. SYSRSTUP selects either

pullup or pulldown, and SYSRSTRE causes the pullup (default) or pulldown to be enabled (default) or not.

If the RST/NMI pin is unused, it is required either to select and enable the internal pullup or to connect an

external 47-kΩpullup resistor to the RST/NMI pin with a 1.1-nF pulldown capacitor. The pulldown

capacitor should not exceed 1.1 nF when using devices with Spy-Bi-Wire interface in Spy-Bi-Wire mode or

in 4-wire JTAG mode with TI tools like FET interfaces or GANG programmers.

See the MSP430FR4xx and MSP430FR2xx Family User's Guide for more information on the referenced

control registers and bits.

7.1.5 Unused Pins

For details on the connection of unused pins, see Section 4.6.

l TEXAS INSTRUMENTS

Using an external

positive reference

Using an external

negative reference VEREF-

VREF+/VEREF+

100 nF

10 Fµ

100 nF10 Fµ

DVSS

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7.1.6 General Layout Recommendations

• Proper grounding and short traces for external crystal to reduce parasitic capacitance. For

recommended layout guidelines, see MSP430 32-kHz Crystal Oscillators.

• Proper bypass capacitors on DVCC and reference pins, if used.

• Avoid routing any high-frequency signal close to an analog signal line. For example, keep digital

switching signals such as PWM or JTAG signals away from the oscillator circuit and ADC signals.

• Proper ESD level protection should be considered to protect the device from unintended high-voltage

electrostatic discharge. For guidelines see MSP430 System-Level ESD Considerations.

7.1.7 Do's and Don'ts

During power up, power down, and device operation, DVCC must not exceed the limits specified in

Section 5.1. Exceeding the specified limits may cause malfunction of the device including erroneous writes

to RAM and FRAM.

7.2 Peripheral- and Interface-Specific Design Information

7.2.1 ADC Peripheral

7.2.1.1 Partial Schematic

Figure 7-5 shows the recommended decoupling circuit when an external voltage reference is used.

Figure 7-5. ADC Grounding and Noise Considerations

7.2.1.2 Design Requirements

As with any high-resolution ADC, appropriate PCB layout and grounding techniques must be followed to

eliminate ground loops, unwanted parasitic effects, and noise.

Ground loops are formed when return current from the ADC flows through paths that are common with

other analog or digital circuitry. If care is not taken, this current can generate small unwanted offset

voltages that can add to or subtract from the reference or input voltages of the ADC. The general

guidelines in Section 7.1.1 combined with the connections shown in Figure 7-5 prevent this.

Quickly switching digital signals and noisy power supply lines can corrupt the conversion results, so keep

the ADC input trace shielded from those digital and power supply lines. Putting the MCU in low-power

mode during the ADC conversion improves the ADC performance in a noisy environment. If the device

includes the analog power pair inputs (AVCC and AVSS), TI recommends a noise-free design using

separate analog and digital ground planes with a single-point connection to achieve high accuracy.

Figure 7-5 shows the recommended decoupling circuit when an external voltage reference is used. The

internal reference module has a maximum drive current as described in the sections ADC Pin Enable and

1.2-V Reference Settings of the MSP430FR4xx and MSP430FR2xx Family User's Guide.

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The reference voltage must be a stable voltage for accurate measurements. The capacitor values that are

selected in the general guidelines filter out the high- and low-frequency ripple before the reference voltage

enters the device. In this case, the 10-µF capacitor buffers the reference pin and filters any low-frequency

ripple. A bypass capacitor of 100 nF filters out any high-frequency noise.

7.2.1.3 Layout Guidelines

Components that are shown in the partial schematic (see Figure 7-5) should be placed as close as

possible to the respective device pins to avoid long traces, because they add additional parasitic

capacitance, inductance, and resistance on the signal.

Avoid routing analog input signals close to a high-frequency pin (for example, a high-frequency PWM),

because the high-frequency switching can be coupled into the analog signal.

7.2.2 CapTIvate Peripheral

This section provides a brief introduction to the CapTIvate technology with examples of PCB layout and

performance from the design kit. A more detailed description of the CapTIvate technology and the tools

needed to be successful, application development tools, hardware design guides, and software library,

can be found in the CapTIvate™ Technology Guide.

7.2.2.1 Device Connection and Layout Fundamentals

To learn more on how to design the CapTIvate Technology, see the Capacitive Touch Design Flow for

MSP430™ MCUs With CapTIvate™ Technology application report.

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7.2.2.2 Measurements

The following measurements are taken from the CapTIvate Technology Design Center, using the

CAPTIVATE-PHONE and CAPTIVATE-BSWP panels. Unless otherwise stated, the settings used are the

out-of-box settings, which can be found in the example projects. The intent of these measurements is to

show performance in a configuration that is readily available and reproducible.

Figure 7-6. CAPTIVATE-PHONE and CAPTIVATE-BSWP Panels

7.2.2.2.1 SNR

The Sensitivity, SNR, and Design Margin in Capacitive Touch Applications application report provides a

specific view for analyzing the signal-to-noise ratio of each element.

7.2.2.2.2 Sensitivity

To show sensitivity, in terms of farads, the internal reference capacitor is used as the change in

capacitance. In the mutual-capacitance case, the 0.1-pF capacitor is used. In the self-capacitance case,

the 1-pF reference capacitor is used. For simplicity, the results for only button 1 on both the CAPTIVATE-

PHONE and CAPTIVATE-BSWP panels are reported in Table 7-1.

Table 7-1. Button Sensitivity

CONVERSION

COUNT CONVERSION

GAIN

CAPTIVATE-PHONE BUTTON 1 CAPTIVATE-BSWP BUTTON 1

CONVERSION

TIME (µs)

COUNTS FOR

0.1-pF

CHANGE

CONVERSION

TIME (µs) COUNTS FOR

1-pF CHANGE

100 100 25 6 50 8

200 200 50 10 100 16

200 100 50 21 100 31

800 400 200 70 400 112

800 200 200 140 400 202

800 100 200 257 400 333

An alternative measure in sensitivity is the ability to resolve capacitance change over a wide range of base

capacitance. Table 7-2 shows example conversion times (for a self-mode measurement of discrete

capacitors) that can be used to achieve the desired resolution for a given parasitic load capacitance.

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(1) These measurements were taken with the CapTIvate MCU processor board with the 470-Ωseries resistors replaced with 0-Ωresistors.

(2) 0-V discharge voltage is used.

Table 7-2. Button Sensitivity

CAPACITANCE, Cp

(pF)(1) CONVERSION

COUNT/GAIN CONVERSION TIME

(µs) COUNTS FOR

0.130-pF CHANGE COUNTS FOR

0.260-pF CHANGE COUNTS FOR

0.520-pF CHANGE

23 400/100 200 10 23 35

50 550/100 275 11 24 37

78 650/100 325 11 23 36

150 850/100 425 11 22 35

150(2) 1200/200 600 11 23 37

200(2) 1200/150 600 13 26 41

7.2.2.2.3 Power

The low-power mode LPM3 specifications in Section 5.7 are derived from the CapTIvate technology

design kit as indicated in the notes.

7.3 CapTIvate Technology Evaluation

Table 7-3 lists tools that demonstrate the use of the MSP430FR263x devices. See CapTIvate Evaluation

Tools to get started with evaluating the CapTIvate technology in various real-world application scenarios.

Consult these evaluation tool designs for additional guidance regarding schematics, layout, and software

implementation.

Table 7-3. Evaluation Tools

NAME LINK

MSP CapTIvate MCU Development Kit http://www.ti.com/tool/msp-capt-fr2633

Capacitive Touch Thermostat User Interface Reference Design http://www.ti.com/tool/tidm-captivate-thermostat-ui

gb% J L A 4

Processor Family MSP = Mixed-signal processor

XMS = Experimental silicon

MCU Platform 430 = MSP430 16-bit low-power platform

Memory Type

Series

Feature Set

(see note)

Temperature Range

FR = FRAM

2 = Up to 16 MHz without LCD

CapTIvate Performance

633 = 4 CapTIvate blocks, 16KB of FRAM, 4KB of SRAM, up to 16 CapTIvate I/Os

533 = 4 CapTIvate blocks, 16KB of FRAM, 2KB of SRAM, up to 16 CapTIvate I/Os

632 = 4 CapTIvate blocks, 8KB of FRAM, 2KB of SRAM, up to 8 CapTIvate I/Os

532 = 4 CapTIvate blocks, 8KB of FRAM, 1KB of SRAM, up to 8 CapTIvate I/Os

I = –40 C to 85 C° °

Packaging www.ti.com/packaging

Distribution Format T = Small reel

R = Large reel

No marking = Tube or tray

MSP 430 FR 2633 IRHB R

Processor Family

Series

Packaging

MCU Platform

Distribution Format

Memory Type Temperature Range

Feature Set

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8 Device and Documentation Support

8.1 Getting Started and Next Steps

For more information on the MSP low-power microcontrollers and the tools and libraries that are available

to help with your development, visit the MSP430™ ultra-low-power sensing & measurement MCUs

overview.

8.2 Device Nomenclature

To designate the stages in the product development cycle, TI assigns prefixes to the part numbers of all

MSP MCU devices. Each MSP MCU commercial family member has one of two prefixes: MSP or XMS.

These prefixes represent evolutionary stages of product development from engineering prototypes (XMS)

through fully qualified production devices (MSP).

XMS – Experimental device that is not necessarily representative of the final device's electrical

specifications

MSP – Fully qualified production device

XMS devices are shipped against the following disclaimer:

"Developmental product is intended for internal evaluation purposes."

MSP devices have been characterized fully, and the quality and reliability of the device have been

demonstrated fully. TI's standard warranty applies.

Predictions show that prototype devices (XMS) have a greater failure rate than the standard production

devices. TI recommends that these devices not be used in any production system because their expected

end-use failure rate still is undefined. Only qualified production devices are to be used.

TI device nomenclature also includes a suffix with the device family name. This suffix indicates the

temperature range, package type, and distribution format. Figure 8-1 provides a legend for reading the

complete device name.

NOTE: For more guidance on devices with CapTIvate touch technology, see the device selection benchmarks in the

CapTIvate Technology Guide.

Figure 8-1. Device Nomenclature

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8.3 Tools and Software

All MSP microcontrollers are supported by a wide variety of software and hardware development tools.

Tools are available from TI and various third parties. See them all at Development Kits and Software for

Low-Power MCUs.

Table 8-1 lists the debug features of the MSP430FR211x microcontrollers. See the Code Composer

Studio IDE for MSP430 MCUs User's Guide for details on the available features.

Table 8-1. Hardware Debug Features

MSP430

ARCHITECTURE 4-WIRE

JTAG 2-WIRE

JTAG

BREAK-

POINTS

(N)

RANGE

BREAK-

POINTS

CLOCK

CONTROL STATE

SEQUENCER TRACE

BUFFER

LPMx.5

DEBUGGING

SUPPORT

EEM

VERSION

MSP430Xv2 Yes Yes 3 Yes Yes No No No S

Design Kits and Evaluation Modules

MSP CapTIvate MCU Development Kit

The MSP CapTIvate MCU Development Kit is a comprehensive, easy-to-use platform to evaluate

MSP430FR2633 microcontroller with capacitive touch technology. The kit contains the MSP430FR2633-

based processor board, a programmer and debugger board with EnergyTrace technology to measure

energy consumption with the Code Composer Studio IDE, and sensor boards for evaluating self-

capacitance, mutual capacitance, gesture, and proximity sensing.

Software

MSP430Ware Software

MSP430Ware is a collection of design resources that help users to effectively create and build MSP430

code. MSP430Ware includes a wide selection of highly abstracted software libraries – ranging from device

and peripheral-specific libraries such as MSP430 Driver Library or USB, to application-specific libraries

such as the graphics and capacitive touch libraries. In particular, the MSP430 Driver Library is an

essential library to help software developers leverage convenient APIs to control low-level and intricate

hardware peripherals, making the resulting code much easier to read and maintain.

MSP430FR243x, MSP430FR253x, MSP430FR263x Code Examples

C code examples are available for every MSP device that configures each integrated peripheral for

various application needs.

MSP Driver Library

The abstracted API of MSP Driver Library provides easy-to-use function calls that free you from directly

manipulating the bits and bytes of the MSP430 hardware. Thorough documentation is delivered through a

helpful API Guide, which includes details on each function call and the recognized parameters.

Developers can use Driver Library functions to write complete projects with minimal overhead.

MSP EnergyTrace™ Technology

EnergyTrace technology for MSP430 microcontrollers is an energy-based code analysis tool that

measures and displays the energy profile of the application and helps to optimize it for ultra-low-power

consumption.

ULP (Ultra-Low Power) Advisor

ULP Advisor™ software is a tool for guiding developers to write more efficient code to fully use the unique

ultra-low-power features of MSP and MSP432 microcontrollers. Aimed at both experienced and new

microcontroller developers, ULP Advisor checks your code against a thorough ULP checklist to help

minimize the energy consumption of your application. At build time, ULP Advisor provides notifications and

remarks to highlight areas of your code that can be further optimized for lower power.

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IEC60730 Software Package

The IEC60730 MSP430 software package was developed to help customers comply with IEC 60730-

1:2010 (Automatic Electrical Controls for Household and Similar Use – Part 1: General Requirements) for

up to Class B products, which includes home appliances, arc detectors, power converters, power tools, e-

bikes, and many others. The IEC60730 MSP430 software package can be embedded in customer

applications running on MSP430s to help simplify the customer's certification efforts of functional safety-

compliant consumer devices to IEC 60730-1:2010 Class B.

Fixed Point Math Library for MSP

The MSP IQmath and Qmath libraries are collections of highly optimized and high-precision mathematical

functions for C programmers to seamlessly port a floating-point algorithm into fixed-point code on MSP430

and MSP432 devices. These routines are typically used in computationally intensive real-time applications

where optimal execution speed, high accuracy, and ultra-low energy are critical. By using the IQmath and

Qmath libraries, it is possible to achieve execution speeds considerably faster and energy consumption

considerably lower than equivalent code written using floating-point math.

Floating Point Math Library for MSP430

Continuing to innovate in the low-power and low-cost microcontroller space, TI provides MSPMATHLIB.

Leveraging the intelligent peripherals of our devices, this floating-point math library of scalar functions that

are up to 26 times faster than the standard MSP430 math functions. Mathlib is easy to integrate into your

designs. This library is free and is integrated in both Code Composer Studio IDE and IAR Embedded

Workbench IDE.

Development Tools

Code Composer Studio™ Integrated Development Environment for MSP Microcontrollers

Code Composer Studio (CCS) integrated development environment (IDE) supports all MSP

microcontroller devices. CCS comprises a suite of embedded software utilities used to develop and debug

embedded applications. It includes an optimizing C/C++ compiler, source code editor, project build

environment, debugger, profiler, and many other features.

Command-Line Programmer

MSP Flasher is an open-source shell-based interface for programming MSP microcontrollers through a

FET programmer or eZ430 using JTAG or Spy-Bi-Wire (SBW) communication. MSP Flasher can

download binary files (.txt or .hex) directly to the MSP microcontroller without an IDE.

MSP MCU Programmer and Debugger

The MSP-FET is a powerful emulation development tool – often called a debug probe – that lets users

quickly begin application development on MSP low-power microcontrollers (MCU). Creating MCU software

usually requires downloading the resulting binary program to the MSP device for validation and

debugging. The MSP-FET provides a debug communication pathway between a host computer and the

target MSP. Furthermore, the MSP-FET also provides a backchannel UART connection between the

computer's USB interface and the MSP UART. This affords the MSP programmer a convenient method for

communicating serially between the MSP and a terminal running on the computer.

MSP-GANG Production Programmer

The MSP Gang Programmer can program up to eight identical MSP430 or MSP432 flash or FRAM

devices at the same time. The MSP Gang Programmer connects to a host PC using a standard RS-232 or

USB connection and provides flexible programming options that allow the user to fully customize the

process. The MSP Gang Programmer is provided with an expansion board, called the Gang Splitter, that

implements the interconnections between the MSP Gang Programmer and multiple target devices.

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8.4 Documentation Support

The following documents describe the MSP430FR263x and MSP430FR253x MCUs. Copies of these

documents are available on the Internet at www.ti.com.

Receiving Notification of Document Updates

To receive notification of documentation updates—including silicon errata—go to the product folder for

your device on ti.com (see Section 8.5 for links to product folders). In the upper-right corner, click the

"Alert me" button. This registers you to receive a weekly digest of product information that has changed (if

any). For change details, check the revision history of any revised document.

Errata

MSP430FR2633 Device Erratasheet

Describes the known exceptions to the functional specifications.

MSP430FR2533 Device Erratasheet

Describes the known exceptions to the functional specifications.

MSP430FR2632 Device Erratasheet

Describes the known exceptions to the functional specifications.

MSP430FR2532 Device Erratasheet

Describes the known exceptions to the functional specifications.

User's Guides

MSP430FR4xx and MSP430FR2xx Family User's Guide

Detailed information on the modules and peripherals available in this device family.

MSP430 FRAM Device Bootloader (BSL) User's Guide

The bootloader (BSL) provides a method to program memory during MSP430 MCU project development

and updates. It can be activated by a utility that sends commands using a serial protocol. The BSL

enables the user to control the activity of the MSP430 MCU and to exchange data using a personal

computer or other device.

MSP430 Hardware Tools User's Guide

This manual describes the hardware of the TI MSP-FET430 Flash Emulation Tool (FET). The FET is the

program development tool for the MSP430 ultra-low-power microcontroller.

Application Reports

MSP430 FRAM Technology – How To and Best Practices

FRAM is a nonvolatile memory technology that behaves similar to SRAM while enabling a whole host of

new applications, but also changing the way firmware should be designed. This application report outlines

the how to and best practices of using FRAM technology in MSP430 from an embedded software

development perspective. It discusses how to implement a memory layout according to application-specific

code, constant, data space requirements, and the use of FRAM to optimize application energy

consumption.

VLO Calibration on the MSP430FR4xx and MSP430FR2xx Family

MSP430FR4xx and MSP430FR2xx (FR4xx/FR2xx) family microcontrollers (MCUs) provide various clock

sources, including some high-speed high-accuracy clocks and some low-power low-system-cost clocks.

Users can select the best balance of performance, power consumption, and system cost. The on-chip very

low-frequency oscillator (VLO) is a clock source with 10-kHz typical frequency included in FR4xx/FR2xx

family MCUs. The VLO is widely used in a range of applications because of its ultra-low power

consumption.

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MSP430 32-kHz Crystal Oscillators

Selection of the right crystal, correct load circuit, and proper board layout are important for a stable crystal

oscillator. This application report summarizes crystal oscillator function and explains the parameters to

select the correct crystal for MSP430 ultra-low-power operation. In addition, hints and examples for correct

board layout are given. The document also contains detailed information on the possible oscillator tests to

ensure stable oscillator operation in mass production.

MSP430 System-Level ESD Considerations

System-level ESD has become increasingly demanding with silicon technology scaling towards lower

voltages and the need for designing cost-effective and ultra-low-power components. This application

report addresses different ESD topics to help board designers and OEMs understand and design robust

system-level designs.

8.5 Related Links

Table 8-2 lists quick access links. Categories include technical documents, support and community

resources, tools and software, and quick access to order now.

Table 8-2. Related Links

PARTS PRODUCT FOLDER ORDER NOW TECHNICAL

DOCUMENTS TOOLS &

SOFTWARE SUPPORT &

COMMUNITY

MSP430FR2633 Click here Click here Click here Click here Click here

MSP430FR2632 Click here Click here Click here Click here Click here

MSP430FR2533 Click here Click here Click here Click here Click here

MSP430FR2532 Click here Click here Click here Click here Click here

8.6 Community Resources

The following links connect to TI community resources. Linked contents are provided "AS IS" by the

respective contributors. They do not constitute TI specifications and do not necessarily reflect TI's views;

see TI's Terms of Use.

TI E2E™ Community

TI's Engineer-to-Engineer (E2E) Community. Created to foster collaboration among engineers. At

e2e.ti.com, you can ask questions, share knowledge, explore ideas, and help solve problems with fellow

engineers.

TI Embedded Processors Wiki

Texas Instruments Embedded Processors Wiki. Established to help developers get started with embedded

processors from Texas Instruments and to foster innovation and growth of general knowledge about the

hardware and software surrounding these devices.

8.7 Trademarks

CapTIvate, EnergyTrace, ULP Advisor, Code Composer Studio, E2E are trademarks of Texas

Instruments.

All other trademarks are the property of their respective owners.

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8.8 Electrostatic Discharge Caution

This integrated circuit can be damaged by ESD. Texas Instruments recommends that all integrated circuits be handled with

appropriate precautions. Failure to observe proper handling and installation procedures can cause damage.

ESD damage can range from subtle performance degradation to complete device failure. Precision integrated circuits may be more

susceptible to damage because very small parametric changes could cause the device not to meet its published specifications.

8.9 Export Control Notice

Recipient agrees to not knowingly export or re-export, directly or indirectly, any product or technical data

(as defined by the U.S., EU, and other Export Administration Regulations) including software, or any

controlled product restricted by other applicable national regulations, received from disclosing party under

nondisclosure obligations (if any), or any direct product of such technology, to any destination to which

such export or re-export is restricted or prohibited by U.S. or other applicable laws, without obtaining prior

authorization from U.S. Department of Commerce and other competent Government authorities to the

extent required by those laws.

8.10 Glossary

TI Glossary This glossary lists and explains terms, acronyms, and definitions.

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9 Mechanical, Packaging, and Orderable Information

The following pages include mechanical, packaging, and orderable information. This information is the

most current data available for the designated devices. This data is subject to change without notice and

revision of this document. For browser-based versions of this data sheet, see the left-hand navigation.

I TEXAS INSTRUMENTS Samples Samples Samples Samples Samples Samples Samples Sample: Sample: Samples Samples Samples Samples Samples Samples Samples

PACKAGE OPTION ADDENDUM

www.ti.com 10-Dec-2020

Addendum-Page 1

PACKAGING INFORMATION

Orderable Device Status

(1)

Package Type Package

Drawing Pins Package

Qty Eco Plan

(2)

Lead finish/

Ball material

(6)

MSL Peak Temp

(3)

Op Temp (°C) Device Marking

(4/5)

Samples

MSP430FR2532IRGER ACTIVE VQFN RGE 24 3000 RoHS & Green NIPDAU Level-2-260C-1 YEAR -40 to 85 FR2532

MSP430FR2532IRGET ACTIVE VQFN RGE 24 250 RoHS & Green NIPDAU Level-2-260C-1 YEAR -40 to 85 FR2532

MSP430FR2533IDA ACTIVE TSSOP DA 32 46 RoHS & Green NIPDAU Level-2-260C-1 YEAR -40 to 85 FR2533

MSP430FR2533IDAR ACTIVE TSSOP DA 32 2000 RoHS & Green NIPDAU Level-2-260C-1 YEAR -40 to 85 FR2533

MSP430FR2533IRHBR ACTIVE VQFN RHB 32 3000 RoHS & Green NIPDAU Level-2-260C-1 YEAR -40 to 85 FR2533

MSP430FR2533IRHBT ACTIVE VQFN RHB 32 250 RoHS & Green NIPDAU Level-2-260C-1 YEAR -40 to 85 FR2533

MSP430FR2632IRGER ACTIVE VQFN RGE 24 3000 RoHS & Green NIPDAU Level-2-260C-1 YEAR -40 to 85 FR2632

MSP430FR2632IRGET ACTIVE VQFN RGE 24 250 RoHS & Green NIPDAU Level-2-260C-1 YEAR -40 to 85 FR2632

MSP430FR2632IYQWR ACTIVE DSBGA YQW 24 3000 RoHS & Green SNAGCU Level-1-260C-UNLIM -40 to 85 430FR2632

MSP430FR2632IYQWT ACTIVE DSBGA YQW 24 250 RoHS & Green SNAGCU Level-1-260C-UNLIM -40 to 85 430FR2632

MSP430FR2633IDA ACTIVE TSSOP DA 32 46 RoHS & Green NIPDAU Level-2-260C-1 YEAR -40 to 85 FR2633

MSP430FR2633IDAR ACTIVE TSSOP DA 32 2000 RoHS & Green NIPDAU Level-2-260C-1 YEAR -40 to 85 FR2633

MSP430FR2633IRHBR ACTIVE VQFN RHB 32 3000 RoHS & Green NIPDAU Level-2-260C-1 YEAR -40 to 85 FR2633

MSP430FR2633IRHBT ACTIVE VQFN RHB 32 250 RoHS & Green NIPDAU Level-2-260C-1 YEAR -40 to 85 FR2633

MSP430FR2633IYQWR ACTIVE DSBGA YQW 24 3000 RoHS & Green SNAGCU Level-1-260C-UNLIM -40 to 85 430FR2633

MSP430FR2633IYQWT ACTIVE DSBGA YQW 24 250 RoHS & Green SNAGCU Level-1-260C-UNLIM -40 to 85 430FR2633

(1) The marketing status values are defined as follows:

ACTIVE: Product device recommended for new designs.

LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.

NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design.

PREVIEW: Device has been announced but is not in production. Samples may or may not be available.

OBSOLETE: TI has discontinued the production of the device.

I TEXAS INSTRUMENTS

PACKAGE OPTION ADDENDUM

www.ti.com 10-Dec-2020

Addendum-Page 2

(2) RoHS: TI defines "RoHS" to mean semiconductor products that are compliant with the current EU RoHS requirements for all 10 RoHS substances, including the requirement that RoHS substance

do not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, "RoHS" products are suitable for use in specified lead-free processes. TI may

reference these types of products as "Pb-Free".

RoHS Exempt: TI defines "RoHS Exempt" to mean products that contain lead but are compliant with EU RoHS pursuant to a specific EU RoHS exemption.

Green: TI defines "Green" to mean the content of Chlorine (Cl) and Bromine (Br) based flame retardants meet JS709B low halogen requirements of <=1000ppm threshold. Antimony trioxide based

flame retardants must also meet the <=1000ppm threshold requirement.

(3) MSL, Peak Temp. - The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature.

(4) There may be additional marking, which relates to the logo, the lot trace code information, or the environmental category on the device.

(5) Multiple Device Markings will be inside parentheses. Only one Device Marking contained in parentheses and separated by a "~" will appear on a device. If a line is indented then it is a continuation

of the previous line and the two combined represent the entire Device Marking for that device.

(6) Lead finish/Ball material - Orderable Devices may have multiple material finish options. Finish options are separated by a vertical ruled line. Lead finish/Ball material values may wrap to two

lines if the finish value exceeds the maximum column width.

Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information

provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and

continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals.

TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited information may not be available for release.

In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI to Customer on an annual basis.

l TEXAS INSTRUMENTS REEL DIMENSIONS TAPE DIMENSIONS 7 “KO '«Pt» Reel Dlameter A0 Dimension designed to accommodate the component Width Bo Dimension designed to accommodate the component tengtn K0 Dimension designed to accommodate the component thickness 7 w Overau Wiotn ot the carrier tape i P1 Ptlch between successwe cavtty centers f T Reel Width (W1) QUADRANT ASSIGNMENTS FOR PIN 1 ORIENTATION IN TAPE a O O D O O D D SprocketHotes ,,,,,,,,,,, ‘ User Dtrecllon 0' Feed Pockel Quadrants

TAPE AND REEL INFORMATION

*All dimensions are nominal

Device Package

Type Package

Drawing Pins SPQ Reel

Diameter

(mm)

Reel

Width

W1 (mm)

(mm) B0

(mm) K0

(mm) P1

(mm) W

(mm) Pin1

Quadrant

MSP430FR2532IRGER VQFN RGE 24 3000 330.0 12.4 4.25 4.25 1.15 8.0 12.0 Q2

MSP430FR2533IDAR TSSOP DA 32 2000 330.0 24.4 8.6 11.5 1.6 12.0 24.0 Q1

MSP430FR2533IRHBR VQFN RHB 32 3000 330.0 12.4 5.3 5.3 1.1 8.0 12.0 Q2

MSP430FR2632IRGER VQFN RGE 24 3000 330.0 12.4 4.25 4.25 1.15 8.0 12.0 Q2

MSP430FR2632IYQWR DSBGA YQW 24 3000 180.0 8.4 2.38 2.4 0.8 4.0 8.0 Q1

MSP430FR2632IYQWT DSBGA YQW 24 250 180.0 8.4 2.38 2.4 0.8 4.0 8.0 Q1

MSP430FR2633IDAR TSSOP DA 32 2000 330.0 24.4 8.6 11.5 1.6 12.0 24.0 Q1

MSP430FR2633IRHBR VQFN RHB 32 3000 330.0 12.4 5.3 5.3 1.1 8.0 12.0 Q2

MSP430FR2633IYQWR DSBGA YQW 24 3000 180.0 8.4 2.38 2.4 0.8 4.0 8.0 Q1

MSP430FR2633IYQWT DSBGA YQW 24 250 180.0 8.4 2.38 2.4 0.8 4.0 8.0 Q1

PACKAGE MATERIALS INFORMATION

www.ti.com 5-Jan-2022

Pack Materials-Page 1

l TEXAS INSTRUMENTS TAPE AND REEL BOX DIMENSIONS

*All dimensions are nominal

Device Package Type Package Drawing Pins SPQ Length (mm) Width (mm) Height (mm)

MSP430FR2532IRGER VQFN RGE 24 3000 367.0 367.0 35.0

MSP430FR2533IDAR TSSOP DA 32 2000 350.0 350.0 43.0

MSP430FR2533IRHBR VQFN RHB 32 3000 367.0 367.0 35.0

MSP430FR2632IRGER VQFN RGE 24 3000 367.0 367.0 35.0

MSP430FR2632IYQWR DSBGA YQW 24 3000 182.0 182.0 20.0

MSP430FR2632IYQWT DSBGA YQW 24 250 182.0 182.0 20.0

MSP430FR2633IDAR TSSOP DA 32 2000 350.0 350.0 43.0

MSP430FR2633IRHBR VQFN RHB 32 3000 367.0 367.0 35.0

MSP430FR2633IYQWR DSBGA YQW 24 3000 182.0 182.0 20.0

MSP430FR2633IYQWT DSBGA YQW 24 250 182.0 182.0 20.0

PACKAGE MATERIALS INFORMATION

www.ti.com 5-Jan-2022

Pack Materials-Page 2

l TEXAS INSTRUMENTS T - Tube height| L - Tube length l ,g + w-Tuhe _______________ _ ______________ width 47 — B - Alignment groove width

TUBE

*All dimensions are nominal

Device Package Name Package Type Pins SPQ L (mm) W (mm) T (µm) B (mm)

MSP430FR2533IDA DA TSSOP 32 46 530 11.89 3600 4.9

MSP430FR2633IDA DA TSSOP 32 46 530 11.89 3600 4.9

PACKAGE MATERIALS INFORMATION

www.ti.com 5-Jan-2022

Pack Materials-Page 3

MECHANICAL DATA DA (R—PDSO—G**) PLASTlC SMALL—OUTL‘NE PACKAGE 35 PIN SHOWN <— a="" —=""> 38 207 HHHHHHHHHHHHHHHHHHH M 6.00 5,30 0,15 NOM 7,90 0 A HHHHHHHHHHHHHHHHHHH L 4L2; Seating Piane 1,20 MAX m 0,05 DIM PM" 30 32 35 A MAX 11,10 11,10 12,60 A MW 1090 10.90 12.40 A $743 DB—‘i DC 00—1 4040066/F 01/2009 NOTES: A. Ail linear dimensions are in miilirneters, a. inis drawing is subject 10 cnange wiinoui noiice. C. Body dimensions do not inciude mold ﬂash or protrusion Moid flash and pm‘rusion shali n01 exceed 0.15 per side. 1% Falis within JEDEC 140—155, excepi 30 pin body iengin. ”11-3055 ”.100!“

---I

www.ti.com

PACKAGE OUTLINE

0.625 MAX

0.30

0.12

1.6

TYP

1.6

TYP

0.4

TYP

0.4 TYP

24X 0.3

0.2

B E A

4221561/A 02/2016

DSBGA - 0.625 mm max heightYQW0024

DIE SIZE BALL GRID ARRAY

NOTES:

1. All linear dimensions are in millimeters. Any dimensions in parenthesis are for reference only. Dimensioning and tolerancing

per ASME Y14.5M.

2. This drawing is subject to change without notice.

BALL A1

CORNER

SEATING PLANE

BALL TYP 0.05 C

1 2 3

0.015 C A B

SYMM

SCALE 6.000

D: Max =

E: Max =

2.37 mm, Min =

2.32 mm, Min =

2.31 mm

2.26 mm

www.ti.com

EXAMPLE BOARD LAYOUT

24X ( )0.25

(0.4) TYP

( )

METAL

0.25 0.05 MAX

SOLDER MASK

OPENING

METAL UNDER

SOLDER MASK

( )

SOLDER MASK

OPENING

0.25

0.05 MIN

4221561/A 02/2016

DSBGA - 0.625 mm max heightYQW0024

DIE SIZE BALL GRID ARRAY

NOTES: (continued)

3. Final dimensions may vary due to manufacturing tolerance considerations and also routing constraints.

See Texas Instruments Literature No. SNVA009 (www.ti.com/lit/snva009).

SOLDER MASK DETAILS

NOT TO SCALE

SYMM

LAND PATTERN EXAMPLE

SCALE:30X

1 2 345

NON-SOLDER MASK

DEFINED

(PREFERRED) SOLDER MASK

DEFINED

Human In...

www.ti.com

EXAMPLE STENCIL DESIGN

(0.4) TYP

24X ( 0.25) (R ) TYP0.05

METAL

TYP

4221561/A 02/2016

DSBGA - 0.625 mm max heightYQW0024

DIE SIZE BALL GRID ARRAY

NOTES: (continued)

4. Laser cutting apertures with trapezoidal walls and rounded corners may offer better paste release.

SYMM

SOLDER PASTE EXAMPLE

BASED ON 0.1 mm THICK STENCIL

SCALE:30X

12345

I TEXAS INSTRUMENTS

GENERIC PACKAGE VIEW

Images above are just a representation of the package family, actual package may vary.

Refer to the product data sheet for package details.

RGE 24 VQFN - 1 mm max height

PLASTIC QUAD FLATPACK - NO LEAD

4204104/H

uuwmm W WWWDWUWC‘W W , i D rim—w W WWWWW A T ﬂuuwuu hnn ﬂﬂﬂ mﬂmmmm Q

NOTES:

1. All linear dimensions are in millimeters. Any dimensions in parenthesis are for reference only. Dimensioning and tolerancing

per ASME Y14.5M.

2. This drawing is subject to change without notice.

3. The package thermal pad must be soldered to the printed circuit board for thermal and mechanical performance.

PACKAGE OUTLINE

www.ti.com

4219016 / A 08/2017

VQFN - 1 mm max height

PLASTIC QUAD FLATPACK- NO LEAD

RGE0024H

0.08 C

0.1 C A B

0.05 C

SYMM

4.1

3.9

4.1

3.9

PIN 1 INDEX AREA

1 MAX

0.05

0.00

SEATING PLANE

2X 2.5



2.5

20X 0.5

712

24X 0.30

0.18

24X 0.48

0.28

(0.2) TYP

PIN 1 ID

(OPTIONAL)

‘ \ L ‘ D LLELEL i L rt L, L} :L CU L L CU WULéL ‘‘‘‘‘ Lv LLLLLL MW WUL L } ma 13 L EL E JJ % /

NOTES: (continued)

4. This package is designed to be soldered to a thermal pad on the board. For more information, see Texas Instruments

literature number SLUA271 (www.ti.com/lit/slua271).

5. Solder mask tolerances between and around signal pads can vary based on board fabrication site.

EXAMPLE BOARD LAYOUT

4219016 / A 08/2017

www.ti.com

VQFN - 1 mm max height

RGE0024H

PLASTIC QUAD FLATPACK- NO LEAD

SYMM

LAND PATTERN EXAMPLE

SCALE: 20X

(1.1)

2X(1.1)

(3.825)

( 2.7)

712

24X (0.58)

24X (0.24)

20X (0.5)

(R0.05)



TYP

SOLDER MASK DETAILS

NON SOLDER MASK

DEFINED

(PREFERRED)

SOLDER MASK

DEFINED

0.07 MAX

ALL AROUND 0.07 MIN

ALL AROUND

METAL

SOLDER MASK

OPENING

SOLDER MASK

OPENING

METAL UNDER

SOLDER MASK

l ’VTV’VW @Bﬁ ‘ 8%

NOTES: (continued)

6. Laser cutting apertures with trapezoidal walls and rounded corners may offer better paste release. IPC-7525 may have alternate

design recommendations..

EXAMPLE STENCIL DESIGN

4219016 / A 08/2017

www.ti.com

VQFN - 1 mm max height

RGE0024H

PLASTIC QUAD FLATPACK- NO LEAD

SYMM

SOLDER PASTE EXAMPLE

BASED ON 0.125 mm THICK STENCIL

EXPOSED PAD

78% PRINTED COVERAGE BY AREA

SCALE: 20X

(3.825)

(0.694)

TYP

(0.694)

TYP

4X ( 1.188)

712

24X (0.24)

24X (0.58)

20X (0.5)

(R0.05) TYP

METAL

TYP

www.ti.com

GENERIC PACKAGE VIEW

Images above are just a representation of the package family, actual package may vary.

Refer to the product data sheet for package details.

VQFN - 1 mm max heightRHB 32

PLASTIC QUAD FLATPACK - NO LEAD

5 x 5, 0.5 mm pitch

4224745/A

uUUUlUUUJU C C C ,,,,,,,,, g C C C ‘C \ Qﬂﬂﬂiﬂﬂﬂﬂ I:

www.ti.com

PACKAGE OUTLINE

32X 0.3

0.2

3.45 0.1

32X 0.5

0.3

1 MAX

(0.2) TYP

0.05

0.00

28X 0.5

3.5

2X 3.5

A5.1

4.9 B

5.1

4.9 (0.1)

VQFN - 1 mm max heightRHB0032E

PLASTIC QUAD FLATPACK - NO LEAD

4223442/B 08/2019

PIN 1 INDEX AREA

0.08 C

SEATING PLANE

817

916

32 25

(OPTIONAL)

PIN 1 ID

0.1 C A B

0.05 C

EXPOSED

THERMAL PAD

33 SYMM

SYMM

NOTES:

1. All linear dimensions are in millimeters. Any dimensions in parenthesis are for reference only. Dimensioning and tolerancing

per ASME Y14.5M.

2. This drawing is subject to change without notice.

3. The package thermal pad must be soldered to the printed circuit board for thermal and mechanical performance.

SCALE 3.000

SEE SIDE WALL

DETAIL

20.000

SIDE WALL DETAIL

OPTIONAL METAL THICKNESS

www.ti.com

EXAMPLE BOARD LAYOUT

(1.475)

0.07 MIN

ALL AROUND

0.07 MAX

ALL AROUND

32X (0.25)

32X (0.6)

( 0.2) TYP

VIA

28X (0.5)

(4.8)

(1.475)

( 3.45)

(R0.05)

TYP

VQFN - 1 mm max heightRHB0032E

PLASTIC QUAD FLATPACK - NO LEAD

4223442/B 08/2019

SYMM

916

SYMM

LAND PATTERN EXAMPLE

SCALE:18X

NOTES: (continued)

4. This package is designed to be soldered to a thermal pad on the board. For more information, see Texas Instruments literature

number SLUA271 (www.ti.com/lit/slua271).

5. Vias are optional depending on application, refer to device data sheet. If any vias are implemented, refer to their locations shown

on this view. It is recommended that vias under paste be filled, plugged or tented.

SOLDER MASK

OPENING

METAL UNDER

SOLDER MASK

DEFINED

METAL

SOLDER MASK

OPENING

SOLDER MASK DETAILS

NON SOLDER MASK

DEFINED

(PREFERRED)

F L_J CD :11 \ i 1 1

www.ti.com

EXAMPLE STENCIL DESIGN

32X (0.6)

32X (0.25)

28X (0.5)

(4.8)

4X ( 1.49)

(0.845)

(R0.05) TYP

VQFN - 1 mm max heightRHB0032E

PLASTIC QUAD FLATPACK - NO LEAD

4223442/B 08/2019

NOTES: (continued)

6. Laser cutting apertures with trapezoidal walls and rounded corners may offer better paste release. IPC-7525 may have alternate

design recommendations.

SYMM

METAL

TYP

SOLDER PASTE EXAMPLE

BASED ON 0.125 mm THICK STENCIL

EXPOSED PAD 33:

75% PRINTED SOLDER COVERAGE BY AREA UNDER PACKAGE

SCALE:20X

SYMM

916

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TI PROVIDES TECHNICAL AND RELIABILITY DATA (INCLUDING DATA SHEETS), DESIGN RESOURCES (INCLUDING REFERENCE

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AND WITH ALL FAULTS, AND DISCLAIMS ALL WARRANTIES, EXPRESS AND IMPLIED, INCLUDING WITHOUT LIMITATION ANY

IMPLIED WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE OR NON-INFRINGEMENT OF THIRD

PARTY INTELLECTUAL PROPERTY RIGHTS.

These resources are intended for skilled developers designing with TI products. You are solely responsible for (1) selecting the appropriate

TI products for your application, (2) designing, validating and testing your application, and (3) ensuring your application meets applicable

standards, and any other safety, security, regulatory or other requirements.

These resources are subject to change without notice. TI grants you permission to use these resources only for development of an

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TI’s products are provided subject to TI’s Terms of Sale or other applicable terms available either on ti.com or provided in conjunction with

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TI objects to and rejects any additional or different terms you may have proposed. IMPORTANT NOTICE

Mailing Address: Texas Instruments, Post Office Box 655303, Dallas, Texas 75265

Datenblatt für MSP430FR263x,253x von Texas Instruments

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