Datenblatt für LTP5901,LTP5902 Hardware Integration Guide von Analog Devices Inc.

L7LII‘IEAI2 «SE-=2?- TECHNOLOGY networksw Dust Networks Elerna LTP5901 / LTP5902 Integration Guide
L7 LII‘IEAIZ dus TECHNOLOGY networks‘" Table 0! Contents Design Process About This Guide . Audien oe, Related Documents, ........ Conventions and Terminology Revrsion History, ....................................................................................................................... 4 1 Design Guidelines" 5 Schem atic Destgn Manager Variations *IPMA *IPRA, -IPRB, -IPRC, Manager Variations rlPMA (Only tor Software versions 12.4 and later), ......... Manager Variations rlPRA, >|PRB, -IPRC (Only tor Soltware versions 1.23 and earlier) PCB Layout Eterna LTP5901 Recommended Land Pattern (Chip Antenna), ........... Etema LTP5902 Recommended Land Pattern (MMCX) Antenna ESD Considerations ......................... . Supply Design ....................................................................................................................... Voltage Supervisron and Reset 2 Manulactuling Guidelines. Reflow, .......... Solder Paste/Cleaning, Packaging is'zszsam List of Figures Figure l Eterna Example Schematic Figure 2 Eterna Ext ended Memory Example Sch em atic (page l at 2) Figure 3 Eterna Ext ended Memory Example Sch em atic (page 2 at 2) Figure 4 LTP5901 Land Pattern (Chip Antenna), ..................... Figure 5 LTP5902 Land Pattern (MMCX) ................................................................................... 14 List otTahles Table 1 Programming Header Table 2 External Memory Reference Bill of Materia 2 ETERNA LTP5901 AND LTPSgDZ INTEGRATION GUIDE
2 ETERNA LTP5901 AND LTP5902 INTEGRATION GUIDE
L7 'ILEICIJBEAGQY networks‘" Design Process The design process when working with the LTP590x module based products varies based upon the products use, For customers not using the OCSDK in SmartMesh leotes, SmanMesh WirelessHART motes and SmanMesh IP Managers the LTP590>< based="" products="" should="" be="" treated="" like="" fixed="" lunction="" icsprogrammable="" le.="" connect="" to="" thedevices="" los="" as="" described="" in="" the="" respective="" data="" sheet="" and="" include="" a="" programming="" header="" est="" p0ints="" to="" provide="" a="" method="" to="" load="" software="" onto="" the="" product.="" products="" are="" not="" shipped="" with="" software="" preloaded.="" for="" customers="" writing="" applications="" on="" the="" ocsdk="" the="" ltp590x="" products="" should="" be="" treated="" much="" like="" a="" microcontroller="" product="" with="" a="" few="" key="" exceptions.="" the="" integration="" guide="" focuses="" on="" the="" steps="" to="" design="" and="" manutacture="" ltp590="">< module="" based="" pcas="" design="" ot="" asystem="" solution="" should="" be="" completed="" with="" an="" understanding="" ol="" the="" integration="" guide="" and="" the="" network="" as="" described="" in="" either="" the="" smartmesh="" lp="" user="" guide="" or="" the="" smartmesh="" wirelesshart="" user="" m,="" inaddition,="" il="" developing="" software="" on="" the="" ltp590x-ipm,="" the="" software="" development="" process="" and="" api="" definitions="" are="" prowded="" on="" www.dustcloud,org.="" after="" defining="" how="" the="" product(s)="" should="" operate="" in="" network="" and="" how="" the="" design="" wlll="" be="" partitioned="" between="" hardware="" and="" software="" the="" design="" wlll="" typically="" take="" the="" lollowmg="" steps:="" t)="" review="" the="" example="" schematic="" provided="" in="" this="" document="" to="" gain="" tamiliarity="" with="" the="" required="" additional="" pcacomponents="" 2)="" for="" customers="" developing="" software="" on="" the="" ltcsqot/z-ipm,="" use="" thefuse="" table="" application="" as="" described="" in="" the="" etema="" board="" specitic="" configuration="" guide="" to="" assign="" functions,="" such="" as="" spi.="" izc="" and="" gplo="" to="" ios.="" stan="" by="" loading="" the="" default="" fuse="" table="" lor="" the="" ltpsox="" product="" fuse="" tables="" can="" be="" found="" in="" the="" smartmesh="" lp.zipliie="" on="" a="" customer="" account="" at="" httgs://www.linearcom/mylihear/log="" in="" php="" 3)="" follow="" this="" document="" to="" complete="" the="" schematic="" design="" and="" layout.="" 4)="" use="" the="" fuse="" table="" application="" as="" described="" in="" the="" etema="" board="" specific="" configuration="" guide="" to="" create="" a="" fuse="" table="" for="" the="" design.="" 5)="" use="" the="" etema="" serial="" programmer="" to="" load="" all="" of="" the="" required="" images="" onto="" the="" ltpsqux,="" the="" fuse="" table,="" loader,="" panition="" table="" and="" lmage,="" 6)="" develop="" and="" debug="" the="" design.="" 7)="" develop="" production="" tests,="" the="" eterna="" serial="" programmer="" is="" intended="" forloading="" flash="" images="" in="" production.="" the="" ltcssou="" bdslliie="" provides="" an="" efficient="" method="" to="" test="" pcb="" interconnect.="" 8)="" the="" eternaz="" users="" guide="" prowdes="" guidelines="" forantenna="" usage="" and="" regulatory="" documentation="" requirements="" forthe="" geographies="" the="" ltp590x="" products="" have="" been="" cenified="" in="" addition,="" the="" guide="" includes="" a="" complete="" set="" of="" the="" ltcsbou="" specific="" information="" and="" commands="" required="" to="" certify="" an="" lpt590x="" based="" pcb="" worldwide,="" certification="" can="" bealengthy="" process="" requiring="" signilicarit="" supporting="" documentation="" lrom="" the="" manufacturer.="" customers="" are="" recommended="" to="" work="" with="" a="" certification="" agency="" lamiliar="" with="" the="" regulations="" in="" the="" geography/geographies="" the="" design="" wlll="" be="" certified.="" eterna="" ltp="" 5901="" and="" ltp59="" 02="" integration="" guide="" 3="">
ETERNA LTP 5901 AND LTP59 02 INTEGRATION GUIDE 3
L7 LII‘IEAIZ dus TECHNOLOGY networks“ AhoutThis Guide This document proVides the design guidelines essential tor incorporating either an Eterna LTP5901 or LTP5902 module. The document covers design, layout, EMI, and some manufacturing considerations, Audience This document isintended forsystem developers hardware designers, and layout engineers. Related Documents The tollowing related documents are available: Etema Serial Programmer Guide ETERNA2 User's Guide Etema Board Sgecific Configuration Guide Conventions and Terminology This guide uses the following ten conventions: indicates information that you enter, such as a URL Bold type indicates buttons, tields, and menu commands. italic type is used to introduce a new term, Note: Notes provide more detailed information about concepts. Caution: Cautions adVise about actions that might result in loss of data Warning: Warnings advise about actions that might cause DhySlCal harm tothe hardware or your person. Revision History 0400119 levl 6/7/2012 Initial verSion 0400119 rev2 7/18/2012 Updated relerenms 040-0119 revs 8/20/2012 Corrected keep out lorLTP5901 land pattern 0400119 rev4 4/2/2018 Added support documentation lorexlernal SRAM, 04041119 rev5 5/8/2013 Added hyper link to programmer. 0400119 revs 10/24/2013 Update SDRAM schematics and BOM 0400119 rev7 1/16/2014 Added description for LTP5902 mechanical leads 0400119 levfl 1/11/2016 Added Design Process Section Added description of Software Version / Part Number dependency. 4 ETERNA LTP5901 AND LTPSgoZ INTEGRATION GurDE
4 ETERNA LTP5901 AND LTP5902 INTEGRATION GUIDE
Computer type
Revision
Date
Description
L7 LELUEAGB 1 Design Guidelines Schematic Design dus networks‘" The LTPSBOT and LTP5902 require little external Circuitry, as the devices references, decoupling and power supply tiltering are integrated. The LTP5901 and LTP5902 have been modularly certified tor operation in many geographies rsee the ETERNAZ User's Guide torthe currently supponed geographies and regulatory related specifications. It further certifications may be necessary, it is essential to provide a method to deliver SDBCiflC radio test APIsvra the APIUART interface during testing. Test connections should be included lll the schematic it the product does not provrde a natural means or delivering the API calls. LTP59IJ1 and LTP59I]2 are not shipped with sotlware lire-loaded. Customers are required to load software onto the LTP5901 /LTP5902 during development and production. mew Senal Programmer can be used to load all or the required images onto the LTP590x, the Fuse Table, Loader, Panitron table and Image. Refer to the software release zip file available from https://wwvv.linear.com/mylinear/log in phg tor software images and programming instmctrons. The schematic shown in Figure 1 includes the signal connections necessary torthe programming header. The part number tor the header is provided in Table l. r: meme 1 2 was gs" r chs MlSO FLASH p ENn sl RESETn uachn RX Figure1 Eterna Example Schematic Tahle1 Programming Header Rulers-tee Value Vendor Vendor PM .13 5>Q header Molex 87831-1020 Manager Variations-lPMA-IPHA, -IPRB, -lPfiC Manager hardware dependencies were changed with the release otSmanMesh lP Manager software release 1.2.4 Releases earlier than 1.2.4 require the use or specific matching hardware to versions Wthh supported the use of external memory. For customers using release 1.2.3 or prior see the tollowrng subsection: Manager Variations rlPRAsIPRB, -IPRC. When using SmanMesh IP Manager software release l.2.4 and later see the tollowrng subsection: Manager Variations rlPMA (Only torSottware versions l 2.4 and later) ETERNA LTP 5901 AND LTPSg 02 INTEGRATION GUIDE 5
ETERNA LTP 5901 AND LTP59 02 INTEGRATION GUIDE 5
L7 LII‘IEAIZ dus TECHNOLOGY networks‘" Manager Varialiaiis 4PMA (Only for Software versions 1.2.4 and later) Without the addition ol enemal SRAM Etema IP managers are limited to supporting networks of 32 orfewer motes. Etemai memory may be added to Eterna lP Manager products to: a. manage networks ol up to 100 motes and. b. increase throughput ot the manager from 24 to 36 packets per second To support external RAM with software release 1.2.40rlater customers must either create a Fuse Table image or install a Fuse Table image configured forextemal memory support See the Etema Board Specific Configuration Guide lor instructions on how tocreate afuse table image. See the tile, Readme -File Organization and Programming lnstnictionspdf, in the Etema subdirectory ofthe SmartMesh IP Zip file available lrom httgs://www.linear.com/mylinear/loginghg to locate the default fuse table image. To support external SRAM customers should use the fuse table corresponding tothe product (either LTP5901 or LTP5902) which includes the “*IPRB" sub-string in the file name. To support a design without external SRAM customers should use the fuse table corresponding to the product (either LTP5901 0r LTP5902) which includes the “*IPRA" substring in the file name. The schematic shown in Figure 2 and Figure 3inciudes all the external connections and components necessary to add the enemal RAM. The connections differ from the configuration Without external RAM as follows: 1) CLI access is on UARTCt, not UARTCO 2) Mapping of extemai bus signals to Etema‘s general purpose function pins 3) The Memony, latches and pulse generators shown in Figure 3 The reference Bill of Materials (BOM) torthe addition components needed iorthe external memory interface is shown in Table 2. Manager Varialiaiis 4PM, —IPRB, 4PM? (Only for SnIlware versions 1.2.3 and earlier) Without the addition otextemai SRAM, Etema IP managers are limited to supporting networks of 32 orfewer motes. Eternal memory may be added to Etema IP Manager products to: c. manage networks of up to 100 motes , and I 0,, d. increase throughput ol the manager from 24 to 36 packets per second The LTPSQOTILTPSQOZ-IPRA is limited to Supporting a maximum of 32 motes and a maximum throughput of 24 packets per second. The LTPSQOTILTPSQOZ-IPRA does not support the use of external RAM. The LTPSQOt/LTPSQOZ-IPRC natively supports up to 32 motes With a maximum throughput of 36 packets per second. Alicense key can be purchased to raise the limit ot the LTP5901/LTP5902—IPRC maximum network size to 100 motes. Contact your Linear Sales representative for details on how to order license key certificates. The certiticate contains a product key and instructions tor requesting the generation of a license key, which typically takes one totwo business days to receive a license key. License keys are entered via either the set contig command documented in SmartMesh IP Manager CLl Guide or the setLicense command documaited in the SmartMesh IP Manager APl Guide. The LTP5901/LTP5902- IPRC requires the use ol enemal RAM. 5 ETERNA LTP5901 AND LTPSgdZ INTEGRATION GutDE
6 ETERNA LTP5901 AND LTP5902 INTEGRATION GUIDE
L7 LII‘IEAIZ dus TECHNOLOGY networks" The LTCSaOU-IPRB supports networks of up To 100 motes and has a maxrmum Throughput oi 36 packets per second The LTPSQUi/LTPSQOZ-IPRB requires the use otexiemai RAM. The schematic shown in Figure 2 and Figure Sinciudes ail the external connections and components necessary to add the enernal RAM, The connections differ from the LTP5901- IPRA as ioilows: 4) CLI access is on UARTCT, not UARTCO 5) Mapping of exiernai bus signals to Eterna’s generai purpose function pins 6) The Memow, latches and puise generators shown in Figure 3 The reference Bill of Materials (BOM) iorthe addition components needed iorthe external memory interface is shown in Table 2. ETERNA LTP 5901 AND LTPSg 02 INTEGRATION GUIDE 7
ETERNA LTP 5901 AND LTP59 02 INTEGRATION GUIDE 7
L) TECHNOLOGY networks" Finale 2 Elerna Exlended MemoryExarnple Schemaliupaum M 2) B ETERNA LTP5901 AND LTPSgDZ INTEGRATION GUIDE
8 ETERNA LTP5901 AND LTP5902 INTEGRATION GUIDE
eb_data_0
DP4
eb_io_le0
eb_data_1
R2
100k
0201
IPCS_MISO
IPCS_MOSI
IPCS_SCK
RADIO_INHIBIT
TIMEn
UART_TX
UART_TX_CTSn
UART_TX_RTSn
UART_RX
UART_RX_CTSn
UART_RX_RTSn
VSUPPLY
eb_io_le1
eb_io_oen
eb_io_wen
R3
100k
NoStuf f
0201
UARTC1_RX
UARTC1_TX
eb_io_cs0n
eb_data_5
eb_data_2
eb_data_3
eb_addr_0
eb_addr_1
IPCS_SSn
eb_io_le2
VSUPPLY
eb_data_4
eb_data_6
eb_data_7
TCK
TMS
M1
LPT5901IPC-IPRB
290-0007
ATL_PN=290-0003
RADIO_INHIBIT 64
RESERVED
2
GPIO17
4
GPIO18
5
GPIO19
6
RESERVED
12
AI_0
10
AI_1
8
AI_3
9
AI_2
7
RESETn
15
TDI
16
TDO
17
TMS
18
TCK
19
DP4
21
RESERVED
22
RESERVED
23
RESERVED
24
EB_DATA_7
25
EB_DATA_6
26
EB_DATA_4
27
EB_DATA_0
28
UARTC0_TX/EB_IO_LE0
31
UARTC0_RX/EB_DATA_1
32
EB_IO_LE2 38
IPCS_MISO
33
EB_ADDR_1 40
IPCS_MOSI
35
EB_ADDR_0 41
IPCS_SCK
36
IPCS_SSn 39
EB_DATA_3 43
EB_DATA_2 44
EB_DATA_5 45
EB_IO_CS0n 46
RESERVED/UARTC1_TX 47
RESERVED/UARTC1_RX 48
EB_IO_WEn 49
EB_IO_OEn 50
FLASH_P_ENn/EB_IO_LE1 51
RESERVED 54
VSUPPLY 55
UART_RX_RTSn 57
UART_RX_CTSn 58
UART_RX 59
UART_TX_RTSn 60
UART_TX_CTSn 61
UART_TX 62
TIMEn 63
GND 66
GND
1
NC
3
GND
11
NC
13
NC
14
GND
20
NC 65
NC 52
NC 53
GND 56
GND
30
GND
34
GND 37
NC
29
GND 42
TDO
TDI
RESETn
L7 LLEA dlétwfiu 25 ml traces for VSUPFLYJ’I vsuPp or u me 0402 vsumv M vsUPPLv M vsuww < eb_re="" csorr="" m="" nahcsn="" eb="" in="" sun="" m="" r="" 10%="" oz"="" vcc="" eb="" data="" 0="" an="" no="" h="" “23,?="" m="" 01="" d2="" m="" e="" srsoeez="" m="" a:="" do="" 04="" us="" as="" us="" as="" or="" m="" em:="" le="" gnd="" u="" 15="" «a="" rr="" u="" 32="" eh="" is="" can="" al="" 1="" din="" a5="" no="" a!="" cerr="" a13="" rm="" wan="" roe="" a13="" res="" m="" 5="" ma="" vcc="" lo:="" a17="" vss="" a15="" r02="" m="" 101="" a12="" ndstuff="" r12="" for="" 128kb="" ’”="" en="" mar="" 17="" eh="" m;="" 2="" m="" 0201="" 0="" inf="" m2="" vsupnlm="" us="" 74ahc573="" 0e"="" vcc="" no="" no="" or="" m="" in="" 02="" eb="" date="" 7="" us="" a:="" no="" 04="" us="" as="" as="" as="" m="" 07="" cw="" le="" em:="" u="" pulse="" genexatox="" cumin:="" m="" 5mm="" “mesa="" vsupplv="" m="" a="" 5="" 5="" ‘="" 4="" r13="" oeb_ra_lel_p="" em="" (:4="" mn:="" ‘35="" 1="" place="" r13="" and="" r15="" close="" to="" u4="" and="" u5,="" 3255;="" v="" us="" respectively="" -="" songs="" place="" r14,="" c5,="" and="" r16,="" (.7,="" vsumvn="" (71059="" to="" u4="" and="" u5,="" respectively="" a="" 5="" g,="" am="" «up;="" an:="" finale="" 3="" eterna="" extended="" memory="" example="" sehemalielpaue="" 2="" ol="" 2)="" eterna‘s="" external="" memory="" tunotron="" has="" been="" tesled="" wrlh="" the="" bom="" options="" shown="" in="" table="" 2.="" the="" ram="" components="" shown="" have="" been="" selected="" torlow="" power="" operation="" and="" their="" use="" will="" result="" rn="" an="" increase="" of="" atew="" pa="" ol="" current="" consumption.="" for="" desrgns="" that="" are="" not="" energy="" constrained,="" substrlutron="" of="" general="" purpose="" rams="" wrlh="" equal="" orfaster="" speed="" grades="" should="" be="" possrole.="" substitution="" ol="" the="" multhunction="" logic="" and="" oolal="" latch="" oomponents="" should="" be="" done="" carefully="" to="" maintain="" the="" timing="" generated="" by="" the="" pulse="" generation="" circuits.="" el'erna="" ltp="" 5901="" and="" ltp59="" 02="" integration="" guide="" 9="">
ETERNA LTP 5901 AND LTP59 02 INTEGRATION GUIDE 9
‘IEAIZ L] TECH NOLOGY dus networks‘" PCB Layout Table 2 External Memory Helerenoe Bill 0! Materials Rermnne Value Vendor Venrtnr PIN R12, R13. 0 Panasonic ERJ-tGEOROOC R15 R2. R3. R11 100 kOhm Panasonic ERJ-1GEJ104C R14, R16 499 Ohm Vishay CRCWOZOMBQRFKED R1 1 kOhm Panasonic ERJ-tGEJtOZC R10 237 Ohm Vishay CRCW0402237RFKED CS. C7 30 pF Murata GRM0335C1E300JD01 D C1 . CZ. 03. 100 nF Murata GRM155R710104KA88 04.06 D U2 128K x 8-bit RAM Cypress CY62128EV30LL» 4SZAX| U2 Alternate 128K x 8-bit RAM Renesas R1 LV0108ESA-53|#BO U4. U5 Multifunction Logic NXP 74AUP1G’58GM. 132 U1. U3 Octal Latch NXP 74AHC573E0‘115 P1 5X2 header Molex 87831-1020 M1 ETERNA Module (Chip antenna) Linear LTP5901|PC-IPMA M1 (alt. ETERNA Module (MMCX Linear LTP5902|PC-IPMA application) connector) Technology M1 (alt. ETERNA Module (SE-mote Linear LTP5901|PC-IPRC application) network chip antenna) Technology M1 (alt. ETERNA Module (too-mote Linear LTP5901IPC-IPRB application) network chip antenna) Technology M1 (alt. ETERNA Module (SE-mote Linear LTP5902|PC-IPRC application) network, MMCX connector) Technology M1 (alt. ETERNA Module (TOO-mote Linear LTP5902|PC-IPRB application) network, MMCX connector) Technology Eternabased designs should adhere to the tollowrng layoutsensrtive guidelines: 1. The Eterna modules include exposed test points, and pads on the bottom (mounting) side of the PCB. Exposed metal should be avoided in the on the top surface of the mating PCB in the area where the module will be mounted. 2. The LTP5901 includes achip antenna with layout designed to work over 1 mm thick FR4, as used in the LTP5902. It rs recommended to maintain an opening free of FR4 and any conductive material as far as practically possible to lTlalelZB the radio performance. ETERNA LTP5901 AND LTPSgoZ INTEGRATION GurDE
10 ETERNA LTP5901 AND LTP5902 INTEGRATION GUIDE
L7 LINEAR dUS' TECHNOLOGY networks‘" 3. The LTP5902 includes athrough hole mounted MMCX connector. A sutfrcient opening in the mating PCB must be provided rsee the LTP5902 recommended land pattern later in this document for details. 4. Eterna‘s radios can be sensitive to EMI generated by DC/DC conveners, It is recommended that such inductors are placed a minimum ol 2 inches from the radio and antenna orMMCX connector. ll space constraints prevent this degree of separation, inductor selection can reduce the EMI generated Difterent core materials and shapes will change the size/ current and pncflcurrent relationship oi an inductor. Toroid or shielded pot cores in lerrite or permalloy materials are small and don’t radiate much energy but generally cost more than powdered iron core inductors with similar electrical characteristics. Eterna LTP5901Reenmmended Land Pattern (chip Antenna) Two common practices for defining land patterns are Non Solder Mask Defined, NSMD, and Solder Mask Defined, SMD, Given the lead pitch at the LTP5901 and tolerances lor metal etch are commonly more precise than solder mask deposition, the recommended practice rs to use NSMD land patterns. The solder mask opening should provide sutfrcient margin tor registration tolerance toavord solder mask inlringing onthe pad, typically 601o 75 um trom the edge at the pad and the solder mask. Land Pattern dimensions are illustiated in Figure 4. ETERNA LTP 5901 AND LTPSg 02 INTEGRATION GUIDE 11
ETERNA LTP 5901 AND LTP59 02 INTEGRATION GUIDE 11
L7 LLUEAR 0'55“?“ 25 mm, ‘ v ‘ 1 1mm P ‘ ‘ n n \ ‘ :Fad - =SolderMask 1.8 mm , 42.5 mm, 33.5 mm “HULLLLLJLJLJLAJLAJAAALAAAALLJ‘ 4 135 mm. . Flam: 4 LTP59II1 Lana Paneln (chlp Antenna) 12 ETERNA LTP5901 AND LTP5902 INTEGRATION GUIDE
12 ETERNA LTP5901 AND LTP5902 INTEGRATION GUIDE
L7 LII‘IEAIZ dus TECHNOLOGY networks‘" Elerna LTP59IJZ Recommended Land Pattern (MMCX) Two common praciioes for defining land patterns are Non Solder Mask Defined, NSMD, and Solder Mask Delined, SMD. Given the lead pitch at the LTP5902 and tolerances tor metal etch are commonly more precise than solder mask deposition, the recommended practice is to use NSMD land patterns The solder mask opening should provide sufficient margin tor registration tolerance toavord solder mask inlringing on the pad, typically 60 to 75 um from the edge olme pad and the solder mask. The LTP5902 includes 4 mechanical leads, the corresponding pads labeled M in in Figure 5, are recommended to be soldered to the carrier PCBinrdesigns targeting high vrbraiion applications. Recommended practioe is not to oonnect mechanical leads to ground orany other signal on the carrier PCB. Land Pattern dimensrons are illustrated in Figure 5. ETERNA LTP 5901 AND LTPSg 02 INTEGRATION GUIDE 13
ETERNA LTP 5901 AND LTP59 02 INTEGRATION GUIDE 13
L7 LELUEAGB 4 25 mm » 1 $5 5 mm THRU = Pad = Soldev Mask 18mm 33 465 mm v v 1 mm. 1 mm 1 ‘ ‘ ‘ . s 5 mm .‘ v—IG 5 mm. Finure 5 LTP5902LanflPanern1MMCX) 14 ETERNA LTP5901 AND LTPSgDZ INTEGRATION GUIDE
14 ETERNA LTP5901 AND LTP5902 INTEGRATION GUIDE
L7 LII‘IEAIZ dUS' TECHNOLOGY network?“ Antenna ESD Considerations The antenna pin isa particularly senSitive node for electrostatic discharge (ESD) since itmust detect small, high-trequency Signals. ESD damage may result in decreased receive ortransmit performance, or other system failure. Many applications forEterna have an exposed antenna that proVides an entry point tor ESD events. Proper consideration of antenna design as well as antenna protection can substantially improve ESD robustness in harsh environments. A radome (protective covering) made of highly resistive material may be used to prevent direct contact with the antenna and/or dissipate charge To avoid ESD events caused by triboelectric charging generated by wind passing over the antenna in dry climates, the radome design should consider bulk and surface resistiVity as well as the size of the gap between the antenna metal and the interior of the radome. In general DCgrounded antennas (the antenna and ground have a DC short) provide superior protection to ESD events. DCgrounded antennas are highly recommended in harsh enwronments. Additionally, a DC path»toeaith ground should he proVided whenever possible to help bleed off accumulated charge from the antenna as well as leak charge trom the radcme, While these general guidelines should improve robustness to ESD events, individual implementations may have unique factors that complicate ESD protection. Supply Design Due to the heavy duty cycling, Eterna’s current consumption can change substantially over a short period. This does not represent an issue tor systems with supplies haVing low source impedance (less than 5 Ohms). Regulated supplies, however, may have difiiculty in the sudden changes in current consumption (more than an order of magnitude in less thant ps), resulting in transient voltages on the supply coincident with the higher current consumption at the radio operation. To ensure proper operation of the radio, a supply should be able to ramp trom 250 pA to to mA in less than 1 ps Without generating atransient greater than 200 mV.For systems with regulated supplies, consultation with Linear Technology is strongly recommended. Eterna can be configured to support current limited supplies, Contact Linear Technology tor details. Voltage Supervision and Reset Eterna includes a power-on reset to sately set in own state during power up, and includes a brownput Circuit that immediately halts flash erase cycles and interrupts llash write cycles at the next 32bit boundary, generating an interrupt to the CPU and maintaining state for the CPU to correct should the power supply return to normal operating levels. In the interest 01 av0iding flash corruption, it is not considered best practice to connect the RESETn lead to a voltage summer or to asyndironously assert RESETn Without preViously suspending network and flash activity, ETERNA LTP 5901 AND LTPSg 02 INTEGRATION GUIDE 15
ETERNA LTP 5901 AND LTP59 02 INTEGRATION GUIDE 15
L7 LII‘IEAIZ dus TECHNOLOGY networks‘" 2 ManufacturingGuidelines Bellow Given that Eterna modules are assembled using either “SA0305",“AIpha OM-338 CSP“ or“ SMIC ECO M705-GRN860“ No Clean Solder Paste, carelul adherence toJ-STD-UZU to avoid reflowrng the modules during the assembly process is necessary The solder joint quality of the “castellatrons” where they contact the mating PCB should meet IPC-Afito Acceptabrlity of Electronic Assemblies, section 8.24 Castellated Terminations. Solder Paste/Cleaning “No Clean" soldering paste rs strongly recommended, as it does not require cleaning lollowrng the soldering process. Cleaning the populated modules rs strongly discouraged due tothe potential issues that may result Residuals under the module are difficult to remove with any cleaning process Cleaning with water can lead to capillary eltects where water is absorbed into the gap between the host board and the module potentially resulting in combination with soldering llux residuals leading to shon circuits between neighboring pads. Cleaning with alcohol ora similar organic solvent will likely llood soldering tlux resrduals under the shield, which rs not accessible lorpostwvashing inspection. Ultrasonic cleaning could damage the module permanently. Packaging The LTP5901 and LTP5902 modules are MSLS, however baking rs required when pans are packaged in individual ESD bags. 16 ETERNA LTP5901 AND LTPSgDZ INTEGRATION GutDE
16 ETERNA LTP5901 AND LTP5902 INTEGRATION GUIDE
L7 TEICH [@GY dnlethsorL" Trademarks SmartMesh lttduslrtal and Eterna aretrademarks 0' Dust Networks, no The Dust Networks logo, Dust, Dust Networks, and Smarthlleslt are registered trademarks orDust Networks, tnc The Ltnear logo rs a registered trademark orLtnear Technology Corporation All thtmrparty orand and product names are the trademarks otthetr respectrve owners and are used solely tor rntorrnatronal purposes. ARM and Cortex are tradenrarks or registered trademarks othRM Ltmrted m the EU and other countrtes. Copyright Thts documentation is protected try Urttted States and tnternattonal copyrtghtahd other intellectual and industrial property laws. ltis solely owned by DustNetworks. inc and its licehsors and ts dtstrtbuted under a restrtctivelicehse Thts product, or any portion thereot, rrtay nothe used, copted, modtrted, reverse assembled, reverse compiled, reverseengtneered, dtstrtputed, or redrstrthuted tn any torm by any means wttnout the prtor written authortzatton or Dust Networks, tnc RESTRlCTED RIGHTS Use, dupltcatton, or dtsclosure by me 0.5 Government ts suprectto restrtcttons ol FAR 52.227714(g) (Que/Wt and FAR 52.22749r6/or). or DFAR 25222777015 torts/est and DFAR zzmzozrara),andanyandatt stmtlar and successor legtstattonand regutauorr Disclaimer Thts documentation rs provided “as rs" wrtnout warranty otany kmd. ettner expressed or implied. rncludtng out not ttmrted to, the rmplred warranties ot merchantahtltty or fitness for a particular purpose Thts documentatton might Include techntcal tnaccuractes or other errors. Corrections and tmprovements mtghthe Incorporated tn new verstons ot the documentanoh Dust Networks does not assume any trathtrty arrstng out orthe application or use otany products or servtces and specrttcatty dtsclatms any and all Iraptlrty, rnctudtng wrthout ttmrtatron consequenttal or incidental damages Dust Networks products are notdestgned lor use tn the supportappttances, devtces, or other systems where rnaltunctton can reasonably he expected to result tn stgntrtcantpersonal tnrury to the user, or as a crtncatcomponent tn any ttte supportdevrce or system whose tarlure to periorm can be reasonably expected to cause the tatlure ot the ltie supportdevtce or system. orto atlectits saiety or eitecttveness. Dust Networks customers using or selttng these products tor use tn such appltcatrons do so attherr own rrsk and agree to truly indemnity and hold Dust Networks and its otttcers. employees. suhstdrartes, atttttales. and dtstrtputors harmless agatnstalt datms, costs. damages, and expenses, and reasonable attorney tees arrstng out or, drrectty or mdrrectly, any chtmorpersonal tnrnry or death assoctated wttn such unintended or unauthortzed use, even ttsucn claim alleges thatDustNetworks was negligent regardmg the desrgn or manulacture ot tts products. Dust Networks reserves the rtgnt to make correcttons, modrttcaltons, enhancements, improvements, and other changes to tts products or servtces atany ttme and to dtscontrnue any productor servrce wtthoutnonce Customers should ohtatn the tatestretevantrrnormatton before placing orders and should verily tnatsucn mtormatron rs currentand complete. All products are sold suorectto Dust Network‘s terms and cohdtttons oi sale supplied at the ttme otorder acknowledgmehtor sale. Dust Networks does not warrantor represent tnatany ttcense, either expre$ or implied, rs granted under any Dust Networks patent right, copyrtpht. mask work right or other Dust Networks intellectual property rtghtrelating to any combination, rnaclrtrte, or process tn which Dust Networks products or servtces are used tntormatron puotrshed hy DustNetworks regardmg thtrdrparty products or servtces does not constttute a ttcense rrom DustNetworks to use such products or servtces or a warranty or endorsementthereor. Use orsuch tnrormatton may regutre a ttcense troma thtrd party under the patents or other tntettectual property at the third party, or a ttcense rrom Dust Networks under the patents or other tntettectual property orDustNetworks. Dust Networks. Inc Is a wholly owned suusrdrary ot Ltnear technology corporaoon © DustNetworks. Inc. zerontt atoms Reserved. Document Number 04070119 Eterna LTPSQOT and LTP5902 Integratton Guide LastRevised Jahuary11,2016 El'ERNA LTP 5901 AND LTPSg oz INTEGRATION GUIDE 17
ETERNA LTP 5901 AND LTP59 02 INTEGRATION GUIDE 17