Datenblatt für SY88083L von Microchip Technology

-| ® 16 to 12.56 Limiting Post Amplifier with a Digital Offset Correction ppon documenta www.micrei com htIE:/lwww. mlcrel .com HBWheig@miCrel,com or (408) 9554 690
SY88083L
1G to 12.5G Limiting Post Amplifier with
Digital Offset Correction
Revision 1.0
.
Micrel Inc. • 2180 Fortune Drive • San Jose, CA 95131 • USA • tel +1 (408) 944-0800 • fax + 1 (408) 474-1000 • http://www.micrel.com
November
8, 2013
Revision 1.0
HBWhelp@micrel.com or (408) 955-1690
General Description
The SY88083L limiting post amplifier is designed for use in
fiber-optic receivers for continuous mode, multi-rate
applications from 1Gbps to 12.5Gbps.
The SY88083L contains a high-bandwidth, high-sensitivity
input stage with user-programmable, wide-range SD
assert/LOS de-assert threshold levels, which enables
optimized system reach. Typically, 4dB of electrical
hysteresis is provided to minimize LOS or SD chattering
caused by noisy input signals. A logic level control pin is
provided to enable user selection of an open-collector,
TTL-compatible LOS or SD status indication signal with an
external 5kΩ to 10kΩ pull-up resistor.
The SY88083L provides faster SD assert and LOS de-
assert times than typical continuous mode devices over
the entire differential input voltage range of 10mVPP to
1800mVPP.
The SY88083L input stage also provides a user-selectable
digital offset correction (DOC) function to automatically
compensate for internal device offsets in the high-speed
data path.
The SY88083L provides integrated 50Ω input and output
impedances to optimize the high-speed signal paths and
reduce component count. A TTL-compatible JAM input is
provided to enable a SQUELCH function by feeding back
the LOS or SD signal. The JAM input disables only the
post amplifier output.
The SY88083L operates from a single +3.3V power
supply, over temperatures ranging from –40°C to +85°C.
Datasheets and support documentation are available on
Micrel’s web site at: www.micrel.com.
Features
• Multi-rate operation from 1.0625Gbps to 12.5Gbps
• Selectable digital offset correction for internal offset
compensation in the high-speed data path
• Wide differential input range (10mVPP to 1800mVPP)
• Wide SD de-assert or LOS assert threshold range
− 4.5mVPP to 30mVPP
− 4dB typical electrical hysteresis
• Fast SD assert and LOS de-assert times
− 1µs typical; 2µs maximum
• Selectable LOS or SD status signal indicator
• TTL-compatible JAM input with internal pull-up
• Low-noise CML data inputs with integrated 50Ω
termination impedance to internal reference VREF
• Low-noise CML data outputs with integrated 50Ω
termination impedance
− 30ps typical rise/fall times
• Wide range power supply: 3.3V ±10%
• Industrial temperature range: −40°C to +85°C
• Available in a tiny 3mm × 3mm QFN package
Applications
• 10G/8G Fibre Channel
• 10Gigabit Ethernet
• OTN equipment
• SONET OC192; SDH STM64
• WDM/DWDM systems
Markets
• Fibre Channel storage area networks
• Datacom/Enterprise
• High-performance computing
• Telecom
• Wireless base stations
Micrel, Inc. SYSSOBSL SDILOSisEID— SQUELcI-D— DOC_EN D— g 2 | (I) u.” g .- 8 E 5 3 Vcc = 3.3V 0 -a (I) I— 0 U U U U GND 16 15 14 13 Vcc 3 1 12[ DATA7IN+ 100" Rm“ 100n DATA70UT+ :l 2 SY88083L 11E—1 - . RXOUT+ _ 500 Llnes 16-pln 3mm x 3mm QFN 500 Lmes D—H—j 3 (Top View) 10E RXOUT‘ DATA_|N— 100" RXIN- 100n DATA_OUT— :I 4 9 l: GND 5 a 7 8 Vcc H F] F] F] o 0 u) 4 z z 3 a Rsmmswc a g M V D H U) ll SQUELCHG— 10n J10” :100" V HBWhelg @mlcrelLom or (408) 955-1690
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Typical Application Circuit
Ordering Information
Part Number Package Type Operating Range Package Marking Lead Finish
SY88083LMG 3mm × 3mm QFN-16 Industrial 083L with Pb-Free bar-line indicator NiPdAu Pb-Free
SY88083LMG TR
(1)
3mm × 3mm QFN-16 Industrial 083L with Pb-Free bar-line indicator NiPdAu Pb-Free
Note:
1. Tape and reel.
Micrel, Inc. SYSSOBSL 4 N (/J z 1 PIN 1 |NDICATOR “1‘ 8 ._ (TOP OF PACKAGE) 0 2 fi w 0 < d="" l|j="" \="" a="" a="" w="" r—="" ‘0="" li="" ll="" |_|="" ll="" 1s="" 15="" 14="" 13="" em)="" :|="" 1="" 12e="" vcc="" rx|n+="" :|="" 2="" 11="" |:="" rxout+="" rxin-="" :|="" 3="" 10e="" rxout—="" gnd="" :|4="" 9="" |:="" vcc="" 5="" 6="" 7="" 8="" epad="" (gnd)="" 21/="" l—i="" 7'="" e1="" l]="" (bottom="" of="" packag="" g="" g="" 9="" 3="" note="" 5="" 8="" e-pad="" must="" be="" connected="" to="" "1="" :1="" the="" pcb="" negative="" power="" 8="" supply="" plane="" using="" the="" recommended="" viaarray="" hbwhelg="" @micrellom="" or="" (408)="" 955-1690="">
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Pin Configuration
16-Pin 3mm × 3mm QFN
(Top View)
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Pin Description
Pin Number Pin Name Pin Type Pin Function
1 GND Negative Supply
Rail
Negative Supply Rail. Connect to the PCB negative power supply plane that is
also connected to the ePad.
2 RXIN+ High-Speed
Data Input
Differential Noninverting Data Input. LVPECL/CML compatible. AC-coupled
with 100nF (high-frequency, low-ESR capacitor is recommended).
Internally terminated with 50Ω to VCC – 0.9V. AC-coupled only.
3 RXIN− High-Speed
Data Input
Differential Inverting Data Input. LVPECL/CML-compatible. AC-coupled with
100nF (high-frequency, low-ESR capacitor is recommended).
Internally terminated by 50Ω to VCC – 0.9V. AC-coupled only.
4 GND Negative Supply
Rail
Negative Supply Rail. Connect to the PCB negative power supply plane that is
also connected to the ePad.
5 NC No Connect No Connect. Do not connect to logic circuits or power supply rails.
6 NC No Connect No Connect. Do not connect to logic circuits or power supply rails.
7 SD/LOS Open Collector
Logic Output
Output Status Indicator. Loss-of-signal (LOS) or signal detect (SD) open
collector output externally terminated with 5kΩ to 10kΩ resistor to VCC. TTL
compatible.
LOS = High when RXIN± amplitude falls below the threshold set at the
SD/LOSLVL pin.
SD = Low when RXIN± amplitude falls below the threshold set at the
SD/LOSLVL pin.
8 SD/LOSLVL Analog Input
Analog control input. Sets the trigger threshold for the LOS or SD status
indicator signals.
If SD/LOS_SEL = High (LOS selected), connect a resistor from the
SD/LOSLVL pin (loss of signal threshold level) to VCC to adjust the
LOS_Assert threshold for the RXIN± data inputs.
If SD/LOS_SEL = Low (SD selected), connect a resistor from the SD/LOSLVL
pin (signal detect threshold level) to VCC to adjust the SD_De-assert threshold
for the RXIN± data inputs.
9, 12 VCC Positive Supply
Rail
Positive power supply input. Bypass with a 0.1µF capacitor in parallel with a
0.01µF low-ESR capacitor to GND as close as possible to the VCC pin.
10 RXOUT− High-Speed
Data Output
Differential inverting data output. CML compatible and internally terminated by
50Ω to VCC. Can be AC- or DC-coupled to downstream devices.
11 RXOUT+ High-Speed
Data Output
Differential noninverting data output. CML compatible and internally
terminated by 50Ω to VCC. Can be AC- or DC-coupled to downstream devices.
13 TEST Test Pin Factory test pin. For factory use only. Do not connect to logic circuits or power
supply rails.
14 SD/LOS_SEL Logic Level
Input
Input control signal. TTL-compatible logic input signal to select LOS or SD as
the output signal. Internal ~18kΩ pull-up to VCC.
Default = High (NC): LOS selected – normal operation
LOS/SD_SEL = Low: SD selected and JAM operation is inverted
15 JAM Logic Level
Input
Input control signal. TTL-compatible input signal that enables or disables the
RXOUT± output signals. Internal 27kΩ pull-up resistor to VCC. Can be
connected to SD/LOS to form a SQUELCH function.
When SD/LOS_SEL = High
Default = High and RXOUT± outputs are disabled.
Low = RXOUT± outputs are enabled
Operation is inverted when SD/LOS_SEL = Low and SD is selected.
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Pin Description (Continued)
Pin Number Pin Name Pin Type Pin Function
16 DOC_EN Logic Level
Input
Input Control Signal. TTL-compatible logic input signal that enables or
disables the digital offset correction (DOC) circuit.
Default:
DOC_EN = High = Enable with internal 18kΩ pull-up to VCC if not connected to
an external logic low or high signal.
DOC_EN = Low disables the digital offset correction function.
Toggling the DOC_EN signal from high to low to high will cause a reset of the
DOC circuitry and initiate a new DOC routine to lock in new DOC values.
Note: Digital offset correction is not applied to large input signals.
ePad GND Negative Supply
Rail
Exposed Thermal Pad. Must be soldered to PCB plane connected to the
negative supply rail. The recommended via array is needed to remove heat
from the device.
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Absolute Maximum Ratings(2)
Supply Voltage (VCC) ......................................... 0V to +4.0V
Input Voltage (RXIN±) .............................. VCC – 1.5V to VCC
CML Output Voltage (VOUT)…….. .. VCC − 1.0V to VCC + 0.5V
JAM Voltage ........................................................... 0 to VCC
SD/LOSLVL Voltage ................................ VCC – 1.3V to VCC
Lead Temperature (soldering, 20s) ............................ 260°C
Storage Temperature (Ts) ......................... –65°C to +150°C
Operating Ratings(3)
Supply Voltage (VCC) .................................... +3.0V to +3.6V
Ambient Temperature (TA) .......................... –40°C to +85°C
Junction Temperature (TJ) ........................ –40°C to +120°C
Package Thermal Resistance(4)
QFN (θJA) Still-Air ............................................... 60°C/W
QFN (ψJB) ........................................................... 33°C/W
DC Electrical Characteristics
VCC = 3.0 to 3.6V; TA = –40°C to +85°C, typical values at VCC = 3.3V, TA = 25°C.
Symbol Parameter Condition Min. Typ. Max. Units
ICC
Power Supply Current
Note 5 60 75 mA
SD/LOSLVL SD or LOS Threshold Voltage VCC − 1.3 VCC V
VOH RXOUT±
High Voltage
VCC − 0.020 VCC − 0.005 VCC V
VOL RXOUT±
Low Voltage
VCC − 0.400 VCC − 0.350 VCC − 0.300 V
VOS_DOC_ON Differential Output Offset Digital Offset Correction = ON ±10 mV
Z0 Single-Ended Output
Impedance 45 50 55 Ω
ZI Single-Ended Input
Impedance 45 50 55 Ω
Notes:
2. Permanent device damage may occur if absolute maximum ratings are exceeded. This is a stress rating only and functional operation is not implied
at conditions other than those detailed in the operational sections of this datasheet. Exposure to absolute maximum ratings conditions may affect
device reliability.
3. The datasheet limits are not guaranteed if the device is operated beyond the recommended operating conditions.
4. Package thermal resistance assumes that the exposed pad is soldered (or equivalent) to the devices most negative potential on the PCB. ψJB and
θJA assumes still air and a 4-layer PCB, unless otherwise stated. It also assumes that the recommended via pattern and via sizes on the PCB are
used.
5. DOC is enabled, outputs RXOUT± are loaded with external 50Ω loads, and the outputs are enabled.
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TTL DC Electrical Characteristics
VCC = 3.0 to 3.6V; TA = –40°C to +85°C, typical values at VCC = 3.3V, TA = 25°C.
Symbol Parameter Condition Min. Typ. Max. Units
VIH JAM, DOC_EN, SD/LOS_SEL
Input High Voltage 2.0 V
VIL JAM, DOC_EN, SD/LOS_SEL
Input Low Voltage 0.8 V
IIH JAM, DOC_EN, SD/LOS_SEL
Input High Current
VIN = 2.7V 20
µA
VIN = VCC 100
IIL JAM, DOC_EN, SD/LOS_SEL
Input Low Current VIN = 0.4V −0.3 mA
VOH SD or LOS Output High Level Sourcing 100µA 2.4 V
VOL SD or LOS Output Low Level Sinking 2mA 0.4 V
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AC Electrical Characteristics
VCC = 3.3V ±10%, TA = –40°C to +85°C. Typical values at VCC = 3.3V, TA = 25°C; RLOAD = 50Ω to VCC.
Symbol Parameter Condition Min. Typ. Max. Units
tr, tf Output Rise/Fall Time
(20% to 80%) Note 6 30 45 ps
tJITTER
Deterministic Note 7 10 ps
Random Note 8 1
VID Differential Input Voltage Swing Note 10. See Figure 1. 10 1800 mVPP
VOD Differential Output Voltage Swing Note 6 600 700 800 mVPP
tLOS_D; tLOS_A
tSD_D; tSD_A
LOS De-assert, LOS Assert Time
SD De-assert, SD Assert Time Note 11 1 2 us
LOSAM_10k Medium LOS Assert Level RLOSLVL = 10kΩ, Note 9 4.5 mVPP
LOSDM_10k Medium LOS De-assert Level RLOSLVL = 10kΩ, Note 9 7.3 mVPP
HYSM_10k Medium LOS Hysteresis RLOSLVL = 10kΩ, Note 12 2 4.1 6 dB
LOSAH1_1k High1 LOS Assert Level RLOSLVL = 1kΩ, Note 9 18.6 mVPP
LOSDH1_1k High1 LOS De-assert Level RLOSLVL = 1kΩ, Note 9 28.3 mVPP
HYSH1_1k High1 LOS Hysteresis RLOSLVL = 1kΩ, Note 12 2 3.6 6 dB
LOSAH2_100 High2 LOS Assert Level RLOSLVL = 100Ω, Note 9 29.7 mVPP
LOSDH2_100 High2 LOS De-assert Level RLOSLVL = 100Ω, Note 9 44.6 mVPP
HYSH2_100 High2 LOS Hysteresis RLOSLVL = 100Ω, Note 12 2 3.5 6 dB
AV(Diff)_063C Differential Voltage Gain 44 dB
S21_063C Single-Ended Small-Signal Gain 32 38 dB
tDOC_DELAY DOC Delay Time 15 µs
tDOC_LOCK DOC Lock Time 150 µs
Note:
6. Amplifier is in limiting mode. Input is a 200MHz square wave.
7. Deterministic jitter is measured using 10Gbps K28.5 pattern, VID = 20mVPP.
8. Random jitter is measured using 10Gbps K28.7 pattern, VID = 20mVPP.
9. See “Typical Operating Characteristics” for a graph showing how to choose a particular RLOSLVL for a particular LOS assert and its associated de-
assert amplitude.
10. Differential input swing amplitude for data rates up to 12.5Gbps
11. In real world applications, the LOS de-assert/assert time can be strongly influenced by the RC time constant of the AC-coupling capacitor and the
50Ω input termination. To keep this time low, use a decoupling capacitor with the lowest value that is allowed by the data rate and the number of
consecutive identical bits in the application (typical values are in the range of 0.001µF to 0.1µF).
12. This specification defines electrical hysteresis as 20log (LOS de-assert/LOS assert). The ratio between optical hysteresis and electrical hysteresis is
found to vary between 1.5 and 2, depending on the level of received optical power and ROSA characteristics.
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Typical Operating Characteristics
VCC = 3.3V, TA = 25°C, RLOAD = 50Ω to VCC, unless otherwise stated.
20 ps/div,
Typical 10.3G Output with 10mVPP Input Signal
20 ps/div,
Typical 12.5G Output with 10mVPP Input Signal
1
10
100
10 100 1000 10000 100000
Input Signal Amplitude (mV
PP
)
SD/LOSLVL Resistor (Ω)
V
ID
(LOS Assert) and
V
ID
(LOS De-Assert) vs. R
SD/LOSLVL
0.00
1.00
2.00
3.00
4.00
5.00
6.00
10 100 1000 10000 100000
Hysteresis (dB)
SD/LOSLVL Resistor (Ω)
LOS Hysteresis
vs. LOSLVL Resistor
Micrel, Inc. SY88083L TEST DOC_EN Vcc .—. .—. .—. LJ NC [] vqiosv 500 § § 500 500 g g 500 DIG‘TAL OFFSET ,— CORRECTION E RX|N+ [3 V IIF' pRE, BUFFER! AMP AMP DR‘VER RXIN- [] n m E BUFFER J BUFFER $ngch —’ I .0— H M r[ u u 1.: NC GND SDILOSLVL RXOUT+ RXOUT- JAM SD/LosisEL SDILOS HBWhelg @micrelLom or (408) 955-1690
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Functional Block Diagram
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Functional Description
The SY88083L is a high-sensitivity, high-bandwidth
limiting post amplifier. It operates from a single +3.3V
power supply across the entire industrial temperature
range of –40°C to +85°C.
Signals with data rates from 1.0625Gbps to 12.5Gbps
and amplitudes as small as 10mVPP are supported.
Figure 1 shows the allowed input voltage swing.
RXIN+
RXIN-
V
IS
(mV)
5 (mV)
900 (mV)
(RXIN+) –
(RXIN-) V
ID
(mV
PP
)
10 (mV
PP
)
1800 (mV
PP
)
Figure 1. VIS and VID Definition
The SY88083L has a selectable SD or LOS status output
signal that can be fed back to the JAM input to perform
the SQUELCH function for output stability if there is no
signal at the input. SD/LOSLVL sets the sensitivity of the
input amplitude detection.
The SY88083L has a user-selectable, integrated digital
offset correction function to cancel internally generated
output offsets.
Input Amplifier/Buffer
Figure 2 shows a simplified schematic of the input stage.
The high sensitivity of the input amplifier allows signals
as small as 10mVPP to be detected and amplified. The
input amplifier allows input signals as large as 1800mVPP.
Input small signals are amplified with a typical 44dB
differential voltage gain.
Output Buffer
The SY88083L CML output buffer is designed to drive
50Ω impedance transmission lines and is internally
terminated with 50Ω to VCC. Figure 3 shows a simplified
schematic of the output stage.
Signal Detect/Loss-of-Signal (SD/LOS)
The SY88083L generates a user-selectable
(SD/LOS_SEL pin) signal detect (SD) or loss-of-signal
(LOS) open-collector TTL output, as shown in Figure 4.
LOS is used to determine whether the input amplitude is
too small to be considered as a valid input. LOS asserts
high if the input amplitude falls below the threshold set by
SD/LOSLVL and de-asserts low otherwise. LOS can be
fed back to the JAM input to perform the SQUELCH
function and to maintain output stability under a LOS
condition. JAM de-asserts the true output signal low
without removing the input signals. Typically, 4dB LOS
hysteresis is provided to prevent chattering.
When SD/LOS_SEL is used to select the SD output on
the SD/LOS pin, SD is asserted when the differential
input signal amplitude exceeds the level set by the
SD/LOSLVL resistor. The JAM operation is inverted when
SD is selected.
Signal Detect/Loss-of-Signal Level Setting
A programmable SD/LOS level set pin (SD/LOSLVL) sets
the threshold of the input amplitude detection.
Connecting an external resistor between VCC and
SD/LOSLVL sets the threshold voltage. This voltage
ranges from VCC to VCC − 1.3V. The external resistor
creates a voltage divider between VCC and VCC − 1.3V, as
shown in Figure 5.
Hysteresis
The SY88083L provides typically 4dB LOS electrical
hysteresis, which is defined as 20log (VINLOS_De-Assert ÷
VINLOS_Assert). Because the relationship of the voltage
output of the ROSA to optical power at its input is linear,
the optical hysteresis is typically half of the electrical
hysteresis reported in the datasheet. In practice the ratio
between electrical and optical hysteresis is found to be
between 1.5 and 1.8. Thus, 4dB electrical hysteresis
corresponds to an optical hysteresis within the range of
2dB to 2.4dB.
Digital Offset Correction (DOC)
The digital offset correction (DOC) circuit compensates
for the inherent offsets found in high-gain amplifier
circuits and minimizes the offset seen at the outputs.
DOC is a user-selectable feature using the DOC_EN pin
as defined in the “Pin Description” table.
Conventional analog offset compensation techniques
may be susceptible to drift from long continuous identical
digit (CID) patterns. They can also add additional cost
due to the extra DAC and manufacturing setup time
needed to optimize each individual module. The
SY88083L avoids both of these issues and provides a
performance/cost optimized solution.
The DOC circuitry automatically detects any internal
device offsets and locks the correction values but does
not apply offset correction to large input signals.
The DOC is enabled by default unless DOC_EN is pulled
low by an external logic level signal. It can be reset by
toggling the DOC_EN pin high-to-low-to-high. The DOC
reset routine typically completes in 200µs.
Micrel, Inc. SYSSOBSL 0.1 uF —' RXIN+ 0,1uF RXIN— ESD STRUCTURE V VCC CC 500 500 a = 509 0.1|.IF AC-COUPLING CAPACITORS ESD STRUCTURE HBWhelg @mlcrelLom or (408) 955-1690
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Functional Circuit Structures
Figure 2. Input Structure
Figure 3. Output Structure
Micrel, Inc. SY88083L SD/LOS Vcc R SDILOSLVL SD/LOSLVL 1.5k vCC — 1.3V www.mlcremom/ PDF/HBW/Apngoles/aHVAS gdf hllunwwmwcreLcom/ PDF/EvaLBoard/SY88073L 83L EBJde HBWhelg @mlcrelLom or (408) 955-1690
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Functional Circuit Structures (Continued)
Figure 4. SD/LOS Output Structure
Figure 5. SD/LOSLVL Setting Circuit
Related Product and Support Documentation
Document Number Title Application Note Link
AN-45 Notes on Sensitivity and Hysteresis
in Micrel Post Amplifiers www.micrel.com/_PDF/HBW/App-Notes/an-45.pdf
SY88073L_83L_EB SY88073L/SY88083L Evaluation
Board http://www.micrel.com/_PDF/Eval-Board/SY88073L_83L_EB.pdf
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Package Information(12)
16-Pin (3mm × 3mm) QFN-16
Note:
13. Package information is correct as of the publication date. For updates and most current information, go to www.micrel.com.
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MICREL, INC. 2180 FORTUNE DRIVE SAN JOSE, CA 95131 USA
TEL +1 (408) 944-0800 FAX +1 (408) 474-1000 WEB http://www.micrel.com
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