Datenblatt für TMX320F2837xS von Texas Instruments

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TMS320F2837xS Microcontrollers
1 Features
• TMS320C28x 32-bit CPU
– 200 MHz
– IEEE 754 single-precision Floating-Point Unit
(FPU)
– Trigonometric Math Unit (TMU)
– Viterbi/Complex Math Unit (VCU-II)
• Programmable Control Law Accelerator (CLA)
– 200 MHz
– IEEE 754 single-precision floating-point
instructions
– Executes code independently of main CPU
• On-chip memory
– 512KB (256KW) or 1MB (512KW) of flash
(ECC-protected)
– 132KB (66KW) or 164KB (82KW) of RAM
(ECC-protected or parity-protected)
– Dual-zone security supporting third-party
development
– Unique identification number
• Clock and system control
– Two internal zero-pin 10-MHz oscillators
– On-chip crystal oscillator
– Windowed watchdog timer module
– Missing clock detection circuitry
• 1.2-V core, 3.3-V I/O design
• System peripherals
– Two External Memory Interfaces (EMIFs) with
ASRAM and SDRAM support
– 6-channel Direct Memory Access (DMA)
controller
– Up to 169 individually programmable,
multiplexed General-Purpose Input/Output
(GPIO) pins with input filtering
– Expanded Peripheral Interrupt controller (ePIE)
– Multiple Low-Power Mode (LPM) support with
external wakeup
• Communications peripherals
– USB 2.0 (MAC + PHY)
– Support for 12-pin 3.3 V-compatible Universal
Parallel Port (uPP) interface
– Two Controller Area Network (CAN) modules
(pin-bootable)
– Three high-speed (up to 50-MHz) SPI ports
(pin-bootable)
– Two Multichannel Buffered Serial Ports
(McBSPs)
– Four Serial Communications Interfaces (SCI/
UART) (pin-bootable)
– Two I2C interfaces (pin-bootable)
• Analog subsystem
– Up to four Analog-to-Digital Converters (ADCs)
• 16-bit mode
– 1.1 MSPS each (up to 4.4-MSPS system
throughput)
– Differential inputs
– Up to 12 external channels
• 12-bit mode
– 3.5 MSPS each (up to 14-MSPS system
throughput)
– Single-ended inputs
– Up to 24 external channels
• Single Sample-and-Hold (S/H) on each ADC
• Hardware-integrated post-processing of
ADC conversions
– Saturating offset calibration
– Error from setpoint calculation
– High, low, and zero-crossing compare,
with interrupt capability
– Trigger-to-sample delay capture
– Eight windowed comparators with 12-bit Digital-
to-Analog Converter (DAC) references
– Three 12-bit buffered DAC outputs
• Enhanced control peripherals
– 24 PWM channels with enhanced features
– 16 High-Resolution Pulse Width Modulator
(HRPWM) channels
• High resolution on both A and B channels of
8 PWM modules
• Dead-band support (on both standard and
high resolution)
– Six Enhanced Capture (eCAP) modules
– Three Enhanced Quadrature Encoder Pulse
(eQEP) modules
– Eight Sigma-Delta Filter Module (SDFM) input
channels, 2 parallel filters per channel
• Standard SDFM data filtering
• Comparator filter for fast action for out of
range
• Configurable Logic Block (CLB)
– Augments existing peripheral capability
– Supports position manager solutions
•Functional Safety-Compliant
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TMS320F28379S, TMS320F28378S, TMS320F28377S, TMS320F28377S-Q1
TMS320F28376S, TMS320F28375S, TMS320F28375S-Q1, TMS320F28374S
SPRS881J – AUGUST 2014 – REVISED FEBRUARY 2021
Copyright © 2021 Texas Instruments Incorporated Submit Document Feedback 1
Product Folder Links: TMS320F28379S TMS320F28378S TMS320F28377S TMS320F28377S-Q1
TMS320F28376S TMS320F28375S TMS320F28375S-Q1 TMS320F28374S
TMS320F28379S, TMS320F28378S, TMS320F28377S, TMS320F28377S-Q1
TMS320F28376S, TMS320F28375S, TMS320F28375S-Q1, TMS320F28374S
SPRS881J – AUGUST 2014 – REVISED FEBRUARY 2021
An IMPORTANT NOTICE at the end of this data sheet addresses availability, warranty, changes, use in safety-critical applications,
intellectual property matters and other important disclaimers. PRODUCTION DATA.
I TEXAS INSTRUMENTS
– Developed for functional safety applications
– Documentation available to aid ISO 26262
system design up to ASIL D; IEC 61508 up to
SIL 3; IEC 60730 up to Class C; and UL 1998
up to Class 2
–Hardware integrity up to ASIL B, SIL 2
• Safety-related certification
–ISO 26262 certified up to ASIL B and IEC
61508 certified up to SIL 2 by TUV SUD
• Package options:
– Lead-free, green packaging
– 337-ball New Fine Pitch Ball Grid Array
(nFBGA) [ZWT suffix]
– 176-pin PowerPAD™ Thermally Enhanced Low-
Profile Quad Flatpack (HLQFP)
[PTP suffix]
– 100-pin PowerPAD Thermally Enhanced Thin
Quad Flatpack (HTQFP) [PZP suffix]
• Temperature options:
– T: –40°C to 105°C junction
– S: –40°C to 125°C junction
– Q: –40°C to 125°C free-air
(AEC Q100 qualification for automotive
applications)
2 Applications
•Medium/short range radar
•Traction inverter motor control
•HVAC large commercial motor control
•Automated sorting equipment
•CNC control
•AC charging (pile) station
•DC charging (pile) station
•EV charging station power module
•Energy storage power conversion system (PCS)
•Central inverter
•Solar power optimizer
•String inverter
•Inverter & motor control
•On-board (OBC) & wireless charger
•Linear motor segment controller
•Servo drive control module
•AC-input BLDC motor drive
•DC-input BLDC motor drive
•Industrial AC-DC
•Three phase UPS
3 Description
C2000™ 32-bit microcontrollers are optimized for processing, sensing, and actuation to improve closed-loop
performance in real-time control applications such as industrial motor drives; solar inverters and digital power;
electrical vehicles and transportation; motor control; and sensing and signal processing. The C2000 line includes
the Premium performance MCUs and the Entry performance MCUs.
The TMS320F2837xS is a powerful 32-bit floating-point microcontroller unit (MCU) designed for advanced
closed-loop control applications such as industrial motor drives; solar inverters and digital power; electrical
vehicles and transportation; and sensing and signal processing. To accelerate application development, the
DigitalPower software development kit (SDK) for C2000 MCUs and the MotorControl software development kit
(SDK) for C2000™ MCUs are available.
The real-time control subsystem is based on TI’s 32-bit C28x floating-point CPU, which provides 200 MHz of
signal processing performance. The C28x CPU is further boosted by the new TMU accelerator, which enables
fast execution of algorithms with trigonometric operations common in transforms and torque loop calculations;
and the VCU accelerator, which reduces the time for complex math operations common in encoded applications.
The F2837xS microcontroller family features a CLA real-time control coprocessor. The CLA is an independent
32-bit floating-point processor that runs at the same speed as the main CPU. The CLA responds to peripheral
triggers and executes code concurrently with the main C28x CPU. This parallel processing capability can
effectively double the computational performance of a real-time control system. By using the CLA to service
time-critical functions, the main C28x CPU is free to perform other tasks, such as communications and
diagnostics.
The TMS320F2837xS supports up to 1MB (512KW) of onboard flash memory with error correction code (ECC)
and up to 164KB (82KW) of SRAM. Two 128-bit secure zones are also available on the CPU for code protection.
Performance analog and control peripherals are also integrated on the F2837xS MCU to further enable system
consolidation. Four independent 16-bit ADCs provide precise and efficient management of multiple analog
signals, which ultimately boosts system throughput. The new sigma-delta filter module (SDFM) works in
conjunction with the sigma-delta modulator to enable isolated current shunt measurements. The Comparator
TMS320F28379S, TMS320F28378S, TMS320F28377S, TMS320F28377S-Q1
TMS320F28376S, TMS320F28375S, TMS320F28375S-Q1, TMS320F28374S
SPRS881J – AUGUST 2014 – REVISED FEBRUARY 2021 www.ti.com
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TMS320F28376S TMS320F28375S TMS320F28375S-Q1 TMS320F28374S
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Subsystem (CMPSS) with windowed comparators allows for protection of power stages when current limit
conditions are exceeded or not met. Other analog and control peripherals include DACs, PWMs, eCAPs,
eQEPs, and other peripherals.
Peripherals such as EMIFs, CAN modules (ISO 11898-1/CAN 2.0B-compliant), and a new uPP interface extend
the connectivity of the F2837xS. The uPP interface is a new feature of the C2000™ MCUs and supports high-
speed parallel connection to FPGAs or other processors with similar uPP interfaces. Lastly, a USB 2.0 port with
MAC and PHY lets users easily add universal serial bus (USB) connectivity to their application.
To learn more about the C2000 MCUs, visit the C2000 Overview at www.ti.com/c2000.
Device Information
PART NUMBER(1) PACKAGE BODY SIZE
TMS320F28379SZWT nFBGA (337) 16.0 mm × 16.0 mm
TMS320F28377SZWT nFBGA (337) 16.0 mm × 16.0 mm
TMS320F28376SZWT nFBGA (337) 16.0 mm × 16.0 mm
TMS320F28375SZWT nFBGA (337) 16.0 mm × 16.0 mm
TMS320F28374SZWT nFBGA (337) 16.0 mm × 16.0 mm
TMS320F28379SPTP HLQFP (176) 24.0 mm × 24.0 mm
TMS320F28378SPTP HLQFP (176) 24.0 mm × 24.0 mm
TMS320F28377SPTP HLQFP (176) 24.0 mm × 24.0 mm
TMS320F28376SPTP HLQFP (176) 24.0 mm × 24.0 mm
TMS320F28375SPTP HLQFP (176) 24.0 mm × 24.0 mm
TMS320F28374SPTP HLQFP (176) 24.0 mm × 24.0 mm
TMS320F28379SPZP HTQFP (100) 14.0 mm × 14.0 mm
TMS320F28378SPZP HTQFP (100) 14.0 mm × 14.0 mm
TMS320F28377SPZP HTQFP (100) 14.0 mm × 14.0 mm
TMS320F28376SPZP HTQFP (100) 14.0 mm × 14.0 mm
TMS320F28375SPZP HTQFP (100) 14.0 mm × 14.0 mm
TMS320F28374SPZP HTQFP (100) 14.0 mm × 14.0 mm
(1) For more information on these devices, see Mechanical, Packaging, and Orderable Information.
Functional Block Diagram
Figure 4-1 shows the CPU system and associated peripherals.
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TMS320F28379S, TMS320F28378S, TMS320F28377S, TMS320F28377S-Q1
TMS320F28376S, TMS320F28375S, TMS320F28375S-Q1, TMS320F28374S
SPRS881J – AUGUST 2014 – REVISED FEBRUARY 2021
Copyright © 2021 Texas Instruments Incorporated Submit Document Feedback 3
Product Folder Links: TMS320F28379S TMS320F28378S TMS320F28377S TMS320F28377S-Q1
TMS320F28376S TMS320F28375S TMS320F28375S-Q1 TMS320F28374S
I TEXAS INSTRUMENTS [III ‘fié‘ 11%m% MIMMMH ‘TH H M MHITHHHTHT Hmmuu MU H H unlimmm H
16-/12-bit ADC
x4
ADC
Result
Regs
Peripheral Frame 1
GPIO MUX, Input X-BAR, Output X-BAR
Secure Memories
shown in Red
CPU1 Buses
Comparator
Subsystem
(CMPSS)
DAC
x3
Config
Data Bus
Bridge
ePWM-1/../12 eCAP-
1/../6 eQEP-1/2/3
HRPWM-1/../8
SDFM-1/2
EXTSYNCIN
EXTSYNCOUT
TZ1-TZ6
ECAPx
EQEPxA
EQEPxB
EPWMxA
EPWMxB
EQEPxI
EQEPxS
SDx_Dy
SDx_Cy
SCI-
A/B/C/D
(16L FIFO)
I2C-A/B
(16L FIFO)
Data Bus Bridge
SCITXDx
SCIRXDx
SDAx
SCLx
CAN-
A/B
(32-MBOX)
Data Bus
Bridge
CANRXx
CANTXx
Data Bus
Bridge
USBDP
USBDM
USB
Ctrl /
PHY
GPIO
Data Bus
Bridge
GPIOn
EMIF1
Data Bus
Bridge
EM1Dx
EM1Ax
EM1CTLx
EMIF2
Data Bus
Bridge
EM2Dx
EM2Ax
EM2CTLx
A
D
B
C
JTAG
AUXCLKIN
External Crystal or
Oscillator
Watchdog
Main PLL
Aux PLL
INTOSC1
INTOSC2
Low-Power
Mode Control GPIO MUX
TRST
TCK
TDI
TMS
TDO
MEMCPU1
Global Shared
16x 4Kx16
GS0-GS15 RAMs
CPU1.CLA1 Bus
C28 CPU-1
CPU Timer 0
CPU Timer 1
CPU Timer 2
ePIE
(up to 192
interrupts)
WD Timer
NMI-WDT
CPU1.CLA1 Data ROM
(4Kx16)
CPU1.CLA1 to CPU1
128x16 MSG RAM
CPU1 to CPU1.CLA1
128x16 MSG RAM
Boot-ROM 32Kx16
Nonsecure
Secure-ROM 32Kx16
Secure
CPU1.M0 RAM 1Kx16
CPU1.M1 RAM 1Kx16
CPU1.D0 RAM 2Kx16
CPU1.D1 RAM 2Kx16
CPU1 Local Shared
6x 2Kx16
LS0-LS5 RAMs
CPU1.CLA1
CPU1.DMA
PSWD
Dual
Code
Security
Module
+
Emulation
Code
Security
Logic
(ECSL)
PUMP
Flash Bank 0
256K x 16
Secure
Flash Bank 1
256K x 16
Secure
User-Configurable
DCSM
OTP
1K x 16
Flash Wrapper for
Bank 1
Flash Wrapper for
Bank 0
FPU
VCU-II
TMU
Analog
MUX
A5:0
B5:0
C5:2
ADCIN14
ADCIN15
D5:0
Peripheral Frame 2
SPI-
A/B/C
(16L FIFO)
SPISIMOx
SPISOMIx
SPICLKx
SPISTEx
McBSP-A/B
MDXx
MDRx
MCLKXx
MCLKRx
MFSXx
MFSRx
UPPAD[7:0]
UPPACLK
UPPAEN
UPPAWT
UPPAST
uPP RAM
Figure 4-1. Functional Block Diagram
TMS320F28379S, TMS320F28378S, TMS320F28377S, TMS320F28377S-Q1
TMS320F28376S, TMS320F28375S, TMS320F28375S-Q1, TMS320F28374S
SPRS881J – AUGUST 2014 – REVISED FEBRUARY 2021 www.ti.com
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Product Folder Links: TMS320F28379S TMS320F28378S TMS320F28377S TMS320F28377S-Q1
TMS320F28376S TMS320F28375S TMS320F28375S-Q1 TMS320F28374S
I TEXAS INSTRUMENTS
Table of Contents
1 Features............................................................................1
2 Applications.....................................................................2
3 Description.......................................................................2
4 Revision History.............................................................. 5
5 Device Comparison.........................................................6
5.1 Related Products........................................................ 8
6 Terminal Configuration and Functions..........................9
6.1 Pin Diagrams.............................................................. 9
6.2 Signal Descriptions................................................... 16
6.3 Pins With Internal Pullup and Pulldown.................... 39
6.4 Pin Multiplexing.........................................................40
6.5 Connections for Unused Pins................................... 47
7 Specifications................................................................ 48
7.1 Absolute Maximum Ratings...................................... 48
7.2 ESD Ratings – Commercial...................................... 49
7.3 ESD Ratings – Automotive....................................... 49
7.4 Recommended Operating Conditions.......................50
7.5 Power Consumption Summary................................. 51
7.6 Electrical Characteristics...........................................55
7.7 Thermal Resistance Characteristics......................... 56
7.8 Thermal Design Considerations................................57
7.9 System......................................................................58
7.10 Analog Peripherals..................................................93
7.11 Control Peripherals............................................... 123
7.12 Communications Peripherals................................142
8 Detailed Description....................................................175
8.1 Overview.................................................................175
8.2 Functional Block Diagram.......................................175
8.3 Memory...................................................................177
8.4 Identification............................................................186
8.5 Bus Architecture – Peripheral Connectivity.............187
8.6 C28x Processor...................................................... 187
8.7 Control Law Accelerator..........................................191
8.8 Direct Memory Access............................................192
8.9 Boot ROM and Peripheral Booting..........................194
8.10 Dual Code Security Module.................................. 197
8.11 Timers................................................................... 198
8.12 Nonmaskable Interrupt With Watchdog Timer
(NMIWD)................................................................... 198
8.13 Watchdog..............................................................199
8.14 Configurable Logic Block (CLB)............................200
8.15 Functional Safety.................................................. 202
9 Applications, Implementation, and Layout............... 204
9.1 TI Reference Design...............................................204
10 Device and Documentation Support........................205
10.1 Device and Development Support Tool
Nomenclature............................................................205
10.2 Markings............................................................... 206
10.3 Tools and Software............................................... 207
10.4 Documentation Support........................................ 209
10.5 Support Resources............................................... 209
10.6 Trademarks...........................................................210
10.7 Electrostatic Discharge Caution............................210
10.8 Glossary................................................................210
11 Mechanical, Packaging, and Orderable
Information.................................................................. 211
11.1 Packaging Information...........................................211
4 Revision History
Changes from June 25, 2020 to January 31, 2021 (from Revision I (June 2020) to Revision J
(January 2021)) Page
•Device Comparison: Updated part numbers.......................................................................................................6
•ESD Ratings – Commercial: Updated part numbers........................................................................................ 49
•ESD Ratings – Automotive: Updated part numbers......................................................................................... 49
•Device and Development Support Tool Nomenclature: Updated Device Nomenclature image to show -Q1 part
number............................................................................................................................................................205
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TMS320F28379S, TMS320F28378S, TMS320F28377S, TMS320F28377S-Q1
TMS320F28376S, TMS320F28375S, TMS320F28375S-Q1, TMS320F28374S
SPRS881J – AUGUST 2014 – REVISED FEBRUARY 2021
Copyright © 2021 Texas Instruments Incorporated Submit Document Feedback 5
Product Folder Links: TMS320F28379S TMS320F28378S TMS320F28377S TMS320F28377S-Q1
TMS320F28376S TMS320F28375S TMS320F28375S-Q1 TMS320F28374S
TEXAS INSTRUMENTS
5 Device Comparison
Table 5-1 lists the features of each 2837xS device.
Table 5-1. Device Comparison
FEATURE(1) 28379S 28378S 28377S
28377S-Q1 28376S 28375S
28375S-Q1 28374S
Package Type
(ZWT is an nFBGA package.
PTP is an HLQFP package.
PZP is an HTQFP package.)
337-
Ball
ZWT
176-
Pin
PTP
100-
Pin
PZP
176-
Pin
PTP
100-
Pin
PZP
337-
Ball
ZWT
176-
Pin
PTP
100-
Pin
PZP
337-
Ball
ZWT
176-
Pin
PTP
100-
Pin
PZP
337-
Ball
ZWT
176-
Pin
PTP
100-
Pin
PZP
337-
Ball
ZWT
176-
Pin
PTP
100-
Pin
PZP
Processor and Accelerators
C28x
Number 1
Frequency (MHz) 200
Floating-Point Unit
(FPU) Yes
VCU-II Yes
TMU – Type 0 Yes
CLA – Type 1 Number 1
Frequency (MHz) 200
6-Channel DMA – Type 0 1
Memory
Flash (16-bit words) 1MB (512KW) 1MB (512KW) 1MB (512KW) 512KB (256KW) 1MB (512KW) 512KB (256KW)
RAM
(16-bit words)
Dedicated and Local
Shared RAM 36KB (18KW)
Global Shared RAM 128KB (64KW) 128KB (64KW) 128KB (64KW) 96KB (48KW) 128KB (64KW) 96KB (48KW)
Total RAM 164KB (82KW) 164KB
(82KW) 164KB (82KW) 132KB (66KW) 164KB (82KW) 132KB (66KW)
Code security for on-chip flash, RAM,
and OTP blocks Yes
Boot ROM Yes
System
Configurable Logic Block (CLB) 4 tiles No
32-bit CPU timers 3
Watchdog timers 1
Nonmaskable Interrupt Watchdog
(NMIWD) timers 1
Crystal oscillator/External clock input 1
0-pin internal oscillator 2
I/O pins
(shared) GPIO 169 97 41 97 41 169 97 41 169 97 41 169 97 41 169 97 41
External interrupts 5
EMIF EMIF1 (16-bit or 32-bit) 1 – 1 – 1 – 1 – 1 – 1 –
EMIF2 (16-bit) 1 – – – – 1 – – 1 – – 1 – – 1 – –
TMS320F28379S, TMS320F28378S, TMS320F28377S, TMS320F28377S-Q1
TMS320F28376S, TMS320F28375S, TMS320F28375S-Q1, TMS320F28374S
SPRS881J – AUGUST 2014 – REVISED FEBRUARY 2021 www.ti.com
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Product Folder Links: TMS320F28379S TMS320F28378S TMS320F28377S TMS320F28377S-Q1
TMS320F28376S TMS320F28375S TMS320F28375S-Q1 TMS320F28374S
TEXAS INSTRUMENTS
Table 5-1. Device Comparison (continued)
FEATURE(1) 28379S 28378S 28377S
28377S-Q1 28376S 28375S
28375S-Q1 28374S
Package Type
(ZWT is an nFBGA package.
PTP is an HLQFP package.
PZP is an HTQFP package.)
337-
Ball
ZWT
176-
Pin
PTP
100-
Pin
PZP
176-
Pin
PTP
100-
Pin
PZP
337-
Ball
ZWT
176-
Pin
PTP
100-
Pin
PZP
337-
Ball
ZWT
176-
Pin
PTP
100-
Pin
PZP
337-
Ball
ZWT
176-
Pin
PTP
100-
Pin
PZP
337-
Ball
ZWT
176-
Pin
PTP
100-
Pin
PZP
Analog Peripherals
ADC 16-bit
mode
MSPS 1.1 – 1.1 –
Conversion Time (ns)(2) 915 – 915 –
Input pins 24 20 14 – 24 20 14 24 20 14 –
Channels (differential) 12 9 7 – 12 9 7 12 9 7 –
ADC 12-bit
mode
MSPS 3.5
Conversion Time (ns)(2) 280
Input pins 24 20 14 20 14 24 20 14 24 20 14 24 20 14 24 20 14
Channels
(single-ended) 24 20 14 20 14 24 20 14 24 20 14 24 20 14 24 20 14
Number of 16-bit or 12-bit ADCs 4 2 – 4 2 4 2 –
Number of 12-bit only ADCs – 4 2 – 4 2 4 2
Temperature sensor 1
CMPSS (each CMPSS has two
comparators and two internal DACs) 8 4 8 4 8 4 8 4 8 4 8 4
Buffered DAC 3
Control Peripherals (3)
eCAP inputs – Type 0 6
Enhanced Pulse Width Modulator
(ePWM) channels – Type 4 24 15 24 15 24 15 24 15 24 15 24 15
eQEP modules – Type 0 3 2 3 2 3 2 3 2 3 2 3 2
High-resolution ePWM channels –
Type 4 16 9 16 9 16 9 16 9 16 9 16 9
SDFM channels – Type 0 8 6 8 6 8 6 8 6 8 6 8 6
Communication Peripherals (3)
Controller Area Network (CAN) –
Type 0(4) 2
Inter-Integrated Circuit (I2C) – Type 0 2
Multichannel Buffered Serial Port
(McBSP) – Type 1 2
Serial Communications Interface (SCI) –
Type 0 4 3 4 3 4 3 4 3 4 3 4 3
Serial Peripheral Interface (SPI) –
Type 2 3
Universal Serial Bus (USB) – Type 0 1
uPP – Type 0 1
Temperature and Qualification
Junction
Temperature (
TJ)
T: –40°C to 105°C Yes No Yes
S: –40°C to 125°C Yes
Q: –40°C to 150°C(5) No No Yes No No Yes No
Free-Air
Temperature (
TA)
Q: –40°C to 125°C(5) No No Yes No No Yes No
(1) A type change represents a major functional feature difference in a peripheral module. Within a peripheral type, there may be minor
differences between devices that do not affect the basic functionality of the module. For more information, see the C2000 Real-Time
Control Peripherals Reference Guide.
(2) Time between start of sample-and-hold window to start of sample-and-hold window of the next conversion.
(3) For devices that are available in more than one package, the peripheral count listed in the smaller package is reduced because the
smaller package has less device pins available. The number of peripherals internally present on the device is not reduced compared to
the largest package offered within a part number. See Section 6 to identify which peripheral instances are accessible on pins in the
smaller package.
(4) The CAN module uses the IP known as D_CAN. This document uses the names CAN and D_CAN interchangeably to reference this
peripheral.
(5) The letter Q refers to AEC Q100 qualification for automotive applications.
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TMS320F28379S, TMS320F28378S, TMS320F28377S, TMS320F28377S-Q1
TMS320F28376S, TMS320F28375S, TMS320F28375S-Q1, TMS320F28374S
SPRS881J – AUGUST 2014 – REVISED FEBRUARY 2021
Copyright © 2021 Texas Instruments Incorporated Submit Document Feedback 7
Product Folder Links: TMS320F28379S TMS320F28378S TMS320F28377S TMS320F28377S-Q1
TMS320F28376S TMS320F28375S TMS320F28375S-Q1 TMS320F28374S
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5.1 Related Products
For information about similar products, see the following links:
TMS320F2837xD Microcontrollers
The F2837xD series sets a new standard for performance with dual subsystems. Each subsystem consists of a
C28x CPU and a parallel control law accelerator (CLA), each running at 200 MHz. Enhancing performance are
TMU and VCU accelerators. New capabilities include multiple 16-bit/12-bit mode ADCs, DAC, Sigma-Delta
filters, USB, configurable logic block (CLB), on-chip oscillators, and enhanced versions of all peripherals. The
F2837xD is available with up to 1MB of Flash. It is available in a 176-pin QFP or 337-pin BGA package.
TMS320F2837xS Microcontrollers
The F2837xS series is a pin-to-pin compatible version of F2837xD but with only one C28x-CPU-and-CLA
subsystem enabled. It is also available in a 100-pin QFP to enable compatibility with the TMS320F2807x series.
TMS320F28379S, TMS320F28378S, TMS320F28377S, TMS320F28377S-Q1
TMS320F28376S, TMS320F28375S, TMS320F28375S-Q1, TMS320F28374S
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TEXAS INSTRUMENTS m
6 Terminal Configuration and Functions
6.1 Pin Diagrams
Figure 6-1 to Figure 6-4 show the terminal assignments on the 337-ball ZWT New Fine Pitch Ball Grid Array.
Each figure shows a quadrant of the terminal assignments. Figure 6-5 shows the pin assignments on the 176-pin
PTP PowerPAD Thermally Enhanced Low-Profile Quad Flatpack. Figure 6-6 shows the pin assignments on the
100-pin PZP PowerPAD Thermally Enhanced Thin Quad Flatpack.
W
V
U
T
R
P
N
M
L
K
10987654321
654321
VSS
VSSA
VSSA
VSSA
VSSA
VSSA
VDDA
VDDA
VREFHIB
VREFLOB
VREFHID
VREFLOD
VREFHIA
VREFHIC VREFLOA
VREFLOC
W
V
U
T
GPIO129GPIO125
GPIO23
GPIO24GPIO25GPIO26
GPIO27 GPIO108GPIO107GPIO106
GPIO111GPIO112GPIO110
GPIO109 GPIO114 GPIO113
GPIO122
ADCIND4ADCIND2ADCIND0ADCIN14
ADCIN15
ADCINC5
ADCINC3
ADCINC2
ADCINA5
ADCINA3
ADCINA1
ADCINA0 ADCINA2 ADCINA4
ADCINC4
ADCIND1 ADCIND3
ADCINB4ADCINB2ADCINB0
ADCINB1 ADCINB3 ADCINB5
ADCIND5 GPIO123
GPIO124
GPIO126
GPIO127
GPIO128
GPIO130
GPIO131
GPIO116
R
P
VSS
VSS
VSS
VSS
VSS
VDD
VDD
VDD
VDDIO
VDDIO
VDDIO
VDDIO
VDDIO
VDDIO VDD
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS VSS
1098
M
L
K
N
M
L
K
10987
A. Only the GPIO function is shown on GPIO terminals. See Section 6.2.1 for the complete, muxed signal name.
Figure 6-1. 337-Ball ZWT New Fine Pitch Ball Grid Array (Bottom View) – [Quadrant A]
www.ti.com
TMS320F28379S, TMS320F28378S, TMS320F28377S, TMS320F28377S-Q1
TMS320F28376S, TMS320F28375S, TMS320F28375S-Q1, TMS320F28374S
SPRS881J – AUGUST 2014 – REVISED FEBRUARY 2021
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I TEXAS INSTRUMENTS 11 12 13 14 15 16 17 18 19 W 14 ' 15 1s 7 17
W
V
U
T
R
P
17161514131211
17161514
VDD
VDD VSS
VSS VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
GPIO66GPIO65
GPIO61
GPIO59
GPIO56
GPIO52
GPIO48
GPIO38
GPIO119
GPIO35GPIO33
GPIO118
GPIO30
GPIO31
GPIO28
GPIO29
GPIO117
GPIO115
GPIO32 GPIO34 GPIO120
TCK
TRST
TDO
TDI TMS
FLT1
FLT2
GPIO37
GPIO36
GPIO121
GPIO64
GPIO60
GPIO58
GPIO53
GPIO49
GPIO136
GPIO41
GPIO40
GPIO39
VDDIO
VDDIO
VDDIO
VDDIO
VDD3VFL VDD3VFL
1918
1918
VSS
W
V
U
T
R
P
N
M
L
K
GPIO45GPIO44
GPIO142
GPIO140GPIO141
GPIO57 GPIO139
GPIO55GPIO54
GPIO50
GPIO137
GPIO135
GPIO134
GPIO132
GPIO51
GPIO138
ERRORSTS
VDDIO
VSS
1211
M
L
K
N
M
L
K
131211
A. Only the GPIO function is shown on GPIO terminals. See Section 6.2.1 for the complete, muxed signal name.
Figure 6-2. 337-Ball ZWT New Fine Pitch Ball Grid Array (Bottom View) – [Quadrant B]
TMS320F28379S, TMS320F28378S, TMS320F28377S, TMS320F28377S-Q1
TMS320F28376S, TMS320F28375S, TMS320F28375S-Q1, TMS320F28374S
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TEXAS INSTRUMENTS H 12 13 14 15 16 17 18 19
F
E
D
C
B
A
191817161514
191817161514131211
X1
X2
VREGENZ
GPIO67GPIO69
GPIO70
GPIO73
GPIO77GPIO81GPIO149
GPIO153
GPIO84
GPIO85
GPIO86
GPIO87
GPIO154
GPIO155
GPIO156
GPIO150
GPIO151
GPIO152
GPIO82
GPIO83
GPIO148
GPIO78
GPIO79
GPIO80
GPIO72
GPIO76
GPIO75
GPIO71
GPIO74
GPIO147
GPIO145
GPIO144
GPIO68
GPIO146
GPIO143
GPIO133
GPIO62
GPIO63
GPIO47
GPIO43
GPIO42
GPIO46
XRS
H
G
F
E
D
C
B
A
J
VSS
VSS
VSS
VSS
VSS VSS VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VDD
VDD
VDD
VDD
VDD VDD
VDDIO
VDDOSC
VDDOSC
VDDIO
VDDIO
VDDIO
VDDIO
VSSOSC VSSOSC
H
J
1211
131211
H
G
J
A. Only the GPIO function is shown on GPIO terminals. See Section 6.2.1 for the complete, muxed signal name.
Figure 6-3. 337-Ball ZWT New Fine Pitch Ball Grid Array (Bottom View) – [Quadrant C]
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TMS320F28379S, TMS320F28378S, TMS320F28377S, TMS320F28377S-Q1
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I TEXAS INSTRUMENTS 10
J
H
G
F
E
D
C
B
A
654321
7654321
GPIO2GPIO6GPIO90GPIO92GPIO94GPIO97
GPIO10
GPIO11
GPIO13
GPIO16
GPIO98
GPIO99
GPIO100
GPIO103
GPIO12
GPIO14
GPIO17
GPIO20
GPIO95
GPIO96
GPIO15
GPIO18
GPIO21
GPIO9GPIO8
GPIO101
GPIO104
GPIO102
GPIO105
GPIO93
GPIO167
GPIO168
GPIO19
GPIO22
GPIO91
GPIO165
GPIO166
GPIO7
GPIO88
GPIO89
GPIO3
GPIO4
GPIO5
VDDIO
VDDIO
VSS
VSS
VSS VSS
VSS
VSS
VSS
VDDIO
VDDIO
VDDIO
VDDIO
VDDIO
VDDIO
VDDIO
NC
VSS
VSS VSS VSS
VSS VSS
1098
J
H
J
H
G
1098
F
E
D
C
B
GPIO157GPIO160
GPIO163
GPIO164
GPIO0
GPIO1
GPIO161
GPIO162
GPIO158
GPIO159
A
VDD
VDD
VSS
VSS
VSS
VDDIO
VDDIO
VDDIO
10987
A. Only the GPIO function is shown on GPIO terminals. See Section 6.2.1 for the complete, muxed signal name.
Figure 6-4. 337-Ball ZWT New Fine Pitch Ball Grid Array (Bottom View) – [Quadrant D]
TMS320F28379S, TMS320F28378S, TMS320F28377S, TMS320F28377S-Q1
TMS320F28376S, TMS320F28375S, TMS320F28375S-Q1, TMS320F28374S
SPRS881J – AUGUST 2014 – REVISED FEBRUARY 2021 www.ti.com
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TMS320F28376S TMS320F28375S TMS320F28375S-Q1 TMS320F28374S
M TEXAS INSTRUMENTS wkwmommm 43210 665 55565566 G GS 5655 665 555
88
87
86
85
84
83
82
81
80
79
78
77
76
75
74
73
72
71
70
69
68
67
66
65
64
63
62
61
60
59
58
57
56
55
54
53
52
51
50
49
48
47
46
45
133
134
135
136
137
138
139
140
141
142
143
144
145
146
147
148
149
150
151
152
153
154
155
156
157
158
159
160
161
162
163
164
165
166
167
168
169
170
171
172
173
174
175
176
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40
41
42
43
44
132
131
130
129
128
127
126
125
124
123
122
121
120
119
118
117
116
115
114
113
112
111
110
109
108
107
106
105
104
103
102
101
100
99
98
97
96
95
94
93
92
91
90
89
VDD
VDD
VDDA
VREFHIB
VREFLOB
VREFLOD
VREFHID
VSSA
GPIO40
GPIO39
GPIO38
GPIO37
TCK
TMS
TDO
TDI
GPIO35
GPIO34
GPIO33
GPIO32
GPIO31
GPIO29
GPIO28
GPIO30
ADCIND4
ADCIND3
ADCIND2
ADCIND1
ADCIND0
ADCINB3
ADCINB2
ADCINB1
ADCINB0
ADCIN15
FLT1
FLT2
TRST
GPIO36
VDDIO
VDDIO
VDDIO
VDDIO
VDDIO
VDD3VFL
GPIO67
GPIO133
GPIO45
GPIO44
GPIO66
GPIO65
GPIO64
GPIO63
GPIO62
GPIO61
GPIO60
GPIO59
GPIO58
GPIO57
GPIO56
GPIO55
GPIO54
GPIO53
GPIO52
GPIO51
GPIO50
GPIO49
GPIO48
GPIO41
ERRORSTS
VREGENZ
X1
X2
XRS
GPIO43
GPIO42
GPIO47
GPIO46
VSSOSC
VDD
VDD
VDDIO
VDDOSC
VDDOSC
VDDIO
VDDIO
VDDIO
VDDIO
VDDIO
GPIO10
GPIO11
GPIO12
GPIO13
GPIO14
GPIO15
GPIO16
GPIO17
GPIO18
GPIO19
GPIO20
GPIO8
GPIO9
GPIO22
GPIO23
GPIO24
GPIO25
GPIO26
GPIO27
ADCINC4
ADCINC3
ADCINC2
ADCINA5
ADCINA4
ADCINA3
ADCINA2
ADCINA1
ADCINA0
ADCIN14
GPIO21
VSSA
VDDA
VREFHIC
VREFLOC
VREFLOA
VREFHIA
VDD
GPIO99
VDD
VDDIO
VDDIO
VDDIO
VDDIO
VDDIO
GPIO68
GPIO69
GPIO70
GPIO71
GPIO72
GPIO73
GPIO74
GPIO75
GPIO76
GPIO77
GPIO78
GPIO79
GPIO80
GPIO81
GPIO82
GPIO83
GPIO0
GPIO1
GPIO2
GPIO3
GPIO4
GPIO5
GPIO6
GPIO7
GPIO88
GPIO89
GPIO90
GPIO91
GPIO92
GPIO93
GPIO94
GPIO84
GPIO85
GPIO86
GPIO87
VDD
VDD
VDD
VDDIO
VDDIO
VDDIO
VDDIO
VDDIO
VDD
A. Only the GPIO function is shown on GPIO pins. See Section 6.2.1 for the complete, muxed signal name.
Figure 6-5. 176-Pin PTP PowerPAD Thermally Enhanced Low-Profile Quad Flatpack (Top View)
www.ti.com
TMS320F28379S, TMS320F28378S, TMS320F28377S, TMS320F28377S-Q1
TMS320F28376S, TMS320F28375S, TMS320F28375S-Q1, TMS320F28374S
SPRS881J – AUGUST 2014 – REVISED FEBRUARY 2021
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w TEXAS INSTRUMENTS szomm> G 6 secs 543210 G
75
74
73
72
71
70
69
68
67
66
65
64
63
62
50
49
48
47
46
45
44
43
42
41
40
39
38
37
76
77
78
79
80
81
82
83
84
85
86
87
88
89
1
2
3
4
5
6
7
8
9
10
11
12
13
14
61
60
59
58
57
56
15
16
17
18
19
20
90
91
92
93
94
95
36
35
34
33
32
31
21
22
23
24
25
30
29
28
27
26
55
54
53
52
51
96
97
98
99
100
GPIO70
GPIO71
GPIO72
GPIO73
GPIO78
GPIO84
GPIO85
GPIO86
GPIO87
GPIO2
GPIO3
GPIO4
GPIO89
GPIO90
GPIO91
GPIO92
GPIO10
VDD
VDD
VDD
VDDIO
VDDIO
VDDIO
VDDIO
VDD
GPIO11
ADCINA3
ADCINA0
ADCINA1
ADCINA2
ADCINA4
ADCINA5
GPIO21
GPIO20
GPIO99
GPIO18
GPIO19
GPIO17
GPIO16
GPIO15
GPIO14
GPIO13
GPIO12
TCK
TDO
TDI
FLT1
FLT2
ADCINB5
ADCINB4
ADCINB3
ADCINB2
ADCINB1
ADCINB0
ADCIN15
ADCIN14
VDD
VDD
VSSA
VDD3VFL
VDDIO
VDDA
VREFHIB
VSSA
VREFLOB
VDDIO
TMS
TRST
GPIO69
GPIO41
GPIO58
GPIO59
GPIO60
GPIO61
GPIO62
GPIO63
GPIO64
GPIO65
GPIO66
VREGENZ
X1
X2
GPIO43
GPIO42
XRS
VDDIO
VDDOSC
VDDIO
VDDIO
VDDOSC
VDD
VDD
VSSOSC
VDDIO
VDDIO
VDDIO
VDD
V /V
SSA REFLOA
VDDA
VREFHIA
A. Only the GPIO function is shown on GPIO pins. See Section 6.2.1 for the complete, muxed signal name.
Figure 6-6. 100-Pin PZP PowerPAD HTQFP (Top View)
Note
The exposed lead frame die pad of the PowerPAD™ package serves two functions: to remove heat
from the die and to provide ground path for the digital ground (analog ground is provided through
dedicated pins). Thus, the PowerPAD should be soldered to the ground (GND) plane of the PCB
because this will provide both the digital ground path and good thermal conduction path. To make
optimum use of the thermal efficiencies designed into the PowerPAD package, the PCB must be
designed with this technology in mind. A thermal land is required on the surface of the PCB directly
underneath the body of the PowerPAD. The thermal land should be soldered to the exposed lead
frame die pad of the PowerPAD package; the thermal land should be as large as needed to dissipate
the required heat. An array of thermal vias should be used to connect the thermal pad to the internal
GND plane of the board. See PowerPAD™ Thermally Enhanced Package for more details on using
the PowerPAD package.
TMS320F28379S, TMS320F28378S, TMS320F28377S, TMS320F28377S-Q1
TMS320F28376S, TMS320F28375S, TMS320F28375S-Q1, TMS320F28374S
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I TEXAS INSTRUMENTS
Note
PCB footprints and schematic symbols are available for download in a vendor-neutral format, which
can be exported to the leading EDA CAD/CAE design tools. See the CAD/CAE Symbols section in the
product folder for each device, under the Packaging section. These footprints and symbols can also
be searched for at http://webench.ti.com/cad/.
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TMS320F28379S, TMS320F28378S, TMS320F28377S, TMS320F28377S-Q1
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TEXAS INSTRUMENTS
6.2 Signal Descriptions
Section 6.2.1 describes the signals. The GPIO function is the default at reset, unless otherwise mentioned. The
peripheral signals that are listed under them are alternate functions. Some peripheral functions may not be
available in all devices. See Table 5-1 for details. All GPIO pins are I/O/Z and have an internal pullup, which can
be selectively enabled or disabled on a per-pin basis. This feature only applies to the GPIO pins. The pullups are
not enabled at reset.
6.2.1 Signal Descriptions
TERMINAL
I/O/Z(1) DESCRIPTION
NAME MUX
POSITION
ZWT
BALL
NO.
PTP
PIN
NO.
PZP
PIN
NO.
ADC, DAC, AND COMPARATOR SIGNALS
VREFHIA V1 37 19 I
ADC-A high reference. This voltage must be driven into
the pin from external circuitry. Place at least a 1-µF
capacitor on this pin for the 12-bit mode, or at least a 22-
µF capacitor for the 16-bit mode. This capacitor should be
placed as close to the device as possible between the
VREFHIA and VREFLOA pins.
NOTE: Do not load this pin externally.
VREFHIB W5 53 37 I
ADC-B high reference. This voltage must be driven into
the pin from external circuitry. Place at least a 1-µF
capacitor on this pin for the 12-bit mode, or at least a 22-
µF capacitor for the 16-bit mode. This capacitor should be
placed as close to the device as possible between the
VREFHIB and VREFLOB pins.
NOTE: Do not load this pin externally.
VREFHIC R1 35 – I
ADC-C high reference. This voltage must be driven into
the pin from external circuitry. Place at least a 1-µF
capacitor on this pin for the 12-bit mode, or at least a 22-
µF capacitor for the 16-bit mode. This capacitor should be
placed as close to the device as possible between the
VREFHIC and VREFLOC pins.
NOTE: Do not load this pin externally.
VREFHID V5 55 – I
ADC-D high reference. This voltage must be driven into
the pin from external circuitry. Place at least a 1-µF
capacitor on this pin for the 12-bit mode, or at least a 22-
µF capacitor for the 16-bit mode. This capacitor should be
placed as close to the device as possible between the
VREFHID and VREFLOD pins.
NOTE: Do not load this pin externally.
VREFLOA R2 33 17 I
ADC-A low reference.
On the PZP package, pin 17 is double-bonded to VSSA
and VREFLOA. On the PZP package, pin 17 must be
connected to VSSA on the system board.
VREFLOB V6 50 34 I ADC-B low reference
VREFLOC P2 32 – I ADC-C low reference
VREFLOD W6 51 – I ADC-D low reference
ADCIN14
T4 44 26
I Input 14 to all ADCs. This pin can be used as a general-
purpose ADCIN pin or it can be used to calibrate all ADCs
together (either single-ended or differential) from an
external reference.
CMPIN4P I Comparator 4 positive input
ADCIN15
U4 45 27
I Input 15 to all ADCs. This pin can be used as a general-
purpose ADCIN pin or it can be used to calibrate all ADCs
together (either single-ended or differential) from an
external reference.
CMPIN4N I Comparator 4 negative input
TMS320F28379S, TMS320F28378S, TMS320F28377S, TMS320F28377S-Q1
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TMS320F28376S TMS320F28375S TMS320F28375S-Q1 TMS320F28374S
TEXAS INSTRUMENTS
TERMINAL
I/O/Z(1) DESCRIPTION
NAME MUX
POSITION
ZWT
BALL
NO.
PTP
PIN
NO.
PZP
PIN
NO.
ADCINA0
U1 43 25
I ADC-A input 0. There is a 50-kΩ internal pulldown on this
pin in both an ADC input or DAC output mode which
cannot be disabled.
DACOUTA O DAC-A output
ADCINA1
T1 42 24
I ADC-A input 1. There is a 50-kΩ internal pulldown on this
pin in both an ADC input or DAC output mode which
cannot be disabled.
DACOUTB O DAC-B output
ADCINA2 U2 41 23 I ADC-A input 2
CMPIN1P I Comparator 1 positive input
ADCINA3 T2 40 22 I ADC-A input 3
CMPIN1N I Comparator 1 negative input
ADCINA4 U3 39 21 I ADC-A input 4
CMPIN2P I Comparator 2 positive input
ADCINA5 T3 38 20 I ADC-A input 5
CMPIN2N I Comparator 2 negative input
ADCINB0
V2 46 28
I ADC-B input 0. There is a 100-pF capacitor to VSSA on
this pin in both ADC input or DAC reference mode which
cannot be disabled. If this pin is being used as a
reference for the on-chip DACs, place at least a 1-µF
capacitor on this pin.
VDAC I Optional external reference voltage for on-chip DACs.
There is a 100-pF capacitor to VSSA on this pin in both
ADC input or DAC reference mode which cannot be
disabled. If this pin is being used as a reference for the
on-chip DACs, place at least a 1-µF capacitor on this pin.
ADCINB1
W2 47 29
I ADC-B input 1. There is a 50-kΩ internal pulldown on this
pin in both an ADC input or DAC output mode which
cannot be disabled.
DACOUTC O DAC-C output
ADCINB2 V3 48 30 I ADC-B input 2
CMPIN3P I Comparator 3 positive input
ADCINB3 W3 49 31 I ADC-B input 3
CMPIN3N I Comparator 3 negative input
ADCINB4 V4 – 32 I ADC-B input 4
ADCINB5 W4 – 33 I ADC-B input 5
ADCINC2 R3 31 – I ADC-C input 2
CMPIN6P I Comparator 6 positive input
ADCINC3 P3 30 – I ADC-C input 3
CMPIN6N I Comparator 6 negative input
ADCINC4 R4 29 – I ADC-C input 4
CMPIN5P I Comparator 5 positive input
ADCINC5 P4 – – I ADC-C input 5
CMPIN5N I Comparator 5 negative input
ADCIND0 T5 56 – I ADC-D input 0
CMPIN7P I Comparator 7 positive input
ADCIND1 U5 57 – I ADC-D input 1
CMPIN7N I Comparator 7 negative input
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TMS320F28379S, TMS320F28378S, TMS320F28377S, TMS320F28377S-Q1
TMS320F28376S, TMS320F28375S, TMS320F28375S-Q1, TMS320F28374S
SPRS881J – AUGUST 2014 – REVISED FEBRUARY 2021
Copyright © 2021 Texas Instruments Incorporated Submit Document Feedback 17
Product Folder Links: TMS320F28379S TMS320F28378S TMS320F28377S TMS320F28377S-Q1
TMS320F28376S TMS320F28375S TMS320F28375S-Q1 TMS320F28374S
TEXAS INSTRUMENTS
TERMINAL
I/O/Z(1) DESCRIPTION
NAME MUX
POSITION
ZWT
BALL
NO.
PTP
PIN
NO.
PZP
PIN
NO.
ADCIND2 T6 58 – I ADC-D input 2
CMPIN8P I Comparator 8 positive input
ADCIND3 U6 59 – I ADC-D input 3
CMPIN8N I Comparator 8 negative input
ADCIND4 T7 60 – I ADC-D input 4
ADCIND5 U7 – – I ADC-D input 5
GPIO AND PERIPHERAL SIGNALS
GPIO0 0, 4, 8, 12
C8 160 –
I/O General-purpose input/output 0
EPWM1A 1 O Enhanced PWM1 output A (HRPWM-capable)
SDAA 6 I/OD I2C-A data open-drain bidirectional port
GPIO1 0, 4, 8, 12
D8 161 –
I/O General-purpose input/output 1
EPWM1B 1 O Enhanced PWM1 output B (HRPWM-capable)
MFSRB 3 I/O McBSP-B receive frame synch
SCLA 6 I/OD I2C-A clock open-drain bidirectional port
GPIO2 0, 4, 8, 12
A7 162 91
I/O General-purpose input/output 2
EPWM2A 1 O Enhanced PWM2 output A (HRPWM-capable)
OUTPUTXBAR1 5 O Output 1 of the output XBAR
SDAB 6 I/OD I2C-B data open-drain bidirectional port
GPIO3 0, 4, 8, 12
B7 163 92
I/O General-purpose input/output 3
EPWM2B 1 O Enhanced PWM2 output B (HRPWM-capable)
OUTPUTXBAR2 2 O Output 2 of the output XBAR
MCLKRB 3 I/O McBSP-B receive clock
OUTPUTXBAR2 5 O Output 2 of the output XBAR
SCLB 6 I/OD I2C-B clock open-drain bidirectional port
GPIO4 0, 4, 8, 12
C7 164 93
I/O General-purpose input/output 4
EPWM3A 1 O Enhanced PWM3 output A (HRPWM-capable)
OUTPUTXBAR3 5 O Output 3 of the output XBAR
CANTXA 6 O CAN-A transmit
GPIO5 0, 4, 8, 12
D7 165 –
I/O General-purpose input/output 5
EPWM3B 1 O Enhanced PWM3 output B (HRPWM-capable)
MFSRA 2 I/O McBSP-A receive frame synch
OUTPUTXBAR3 3 O Output 3 of the output XBAR
CANRXA 6 I CAN-A receive
GPIO6 0, 4, 8, 12
A6 166 –
I/O General-purpose input/output 6
EPWM4A 1 O Enhanced PWM4 output A (HRPWM-capable)
OUTPUTXBAR4 2 O Output 4 of the output XBAR
EXTSYNCOUT 3 O External ePWM synch pulse output
EQEP3A 5 I Enhanced QEP3 input A
CANTXB 6 O CAN-B transmit
GPIO7 0, 4, 8, 12
B6 167 –
I/O General-purpose input/output 7
EPWM4B 1 O Enhanced PWM4 output B (HRPWM-capable)
MCLKRA 2 I/O McBSP-A receive clock
OUTPUTXBAR5 3 O Output 5 of the output XBAR
EQEP3B 5 I Enhanced QEP3 input B
CANRXB 6 I CAN-B receive
TMS320F28379S, TMS320F28378S, TMS320F28377S, TMS320F28377S-Q1
TMS320F28376S, TMS320F28375S, TMS320F28375S-Q1, TMS320F28374S
SPRS881J – AUGUST 2014 – REVISED FEBRUARY 2021 www.ti.com
18 Submit Document Feedback Copyright © 2021 Texas Instruments Incorporated
Product Folder Links: TMS320F28379S TMS320F28378S TMS320F28377S TMS320F28377S-Q1
TMS320F28376S TMS320F28375S TMS320F28375S-Q1 TMS320F28374S
TEXAS INSTRUMENTS
TERMINAL
I/O/Z(1) DESCRIPTION
NAME MUX
POSITION
ZWT
BALL
NO.
PTP
PIN
NO.
PZP
PIN
NO.
GPIO8 0, 4, 8, 12
G2 18 –
I/O General-purpose input/output 8
EPWM5A 1 O Enhanced PWM5 output A (HRPWM-capable)
CANTXB 2 O CAN-B transmit
ADCSOCAO 3 O ADC start-of-conversion A output for external ADC
EQEP3S 5 I/O Enhanced QEP3 strobe
SCITXDA 6 O SCI-A transmit data
GPIO9 0, 4, 8, 12
G3 19 –
I/O General-purpose input/output 9
EPWM5B 1 O Enhanced PWM5 output B (HRPWM-capable)
SCITXDB 2 O SCI-B transmit data
OUTPUTXBAR6 3 O Output 6 of the output XBAR
EQEP3I 5 I/O Enhanced QEP3 index
SCIRXDA 6 I SCI-A receive data
GPIO10 0, 4, 8, 12
B2 1 100
I/O General-purpose input/output 10
EPWM6A 1 O Enhanced PWM6 output A (HRPWM-capable)
CANRXB 2 I CAN-B receive
ADCSOCBO 3 O ADC start-of-conversion B output for external ADC
EQEP1A 5 I Enhanced QEP1 input A
SCITXDB 6 O SCI-B transmit data
UPP-WAIT 15 I/O Universal parallel port wait. Receiver asserts to request a
pause in transfer.
GPIO11 0, 4, 8, 12
C1 2 1
I/O General-purpose input/output 11
EPWM6B 1 O Enhanced PWM6 output B (HRPWM-capable)
SCIRXDB 2, 6 I SCI-B receive data
OUTPUTXBAR7 3 O Output 7 of the output XBAR
EQEP1B 5 I Enhanced QEP1 input B
UPP-START 15 I/O Universal parallel port start. Transmitter asserts at start of
DMA line.
GPIO12 0, 4, 8, 12
C2 4 3
I/O General-purpose input/output 12
EPWM7A 1 O Enhanced PWM7 output A (HRPWM-capable)
CANTXB 2 O CAN-B transmit
MDXB 3 O McBSP-B transmit serial data
EQEP1S 5 I/O Enhanced QEP1 strobe
SCITXDC 6 O SCI-C transmit data
UPP-ENA 15 I/O Universal parallel port enable. Transmitter asserts while
data bus is active.
GPIO13 0, 4, 8, 12
D1 5 4
I/O General-purpose input/output 13
EPWM7B 1 O Enhanced PWM7 output B (HRPWM-capable)
CANRXB 2 I CAN-B receive
MDRB 3 I McBSP-B receive serial data
EQEP1I 5 I/O Enhanced QEP1 index
SCIRXDC 6 I SCI-C receive data
UPP-D7 15 I/O Universal parallel port data line 7
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TMS320F28379S, TMS320F28378S, TMS320F28377S, TMS320F28377S-Q1
TMS320F28376S, TMS320F28375S, TMS320F28375S-Q1, TMS320F28374S
SPRS881J – AUGUST 2014 – REVISED FEBRUARY 2021
Copyright © 2021 Texas Instruments Incorporated Submit Document Feedback 19
Product Folder Links: TMS320F28379S TMS320F28378S TMS320F28377S TMS320F28377S-Q1
TMS320F28376S TMS320F28375S TMS320F28375S-Q1 TMS320F28374S
TEXAS INSTRUMENTS
TERMINAL
I/O/Z(1) DESCRIPTION
NAME MUX
POSITION
ZWT
BALL
NO.
PTP
PIN
NO.
PZP
PIN
NO.
GPIO14 0, 4, 8, 12
D2 6 5
I/O General-purpose input/output 14
EPWM8A 1 O Enhanced PWM8 output A (HRPWM-capable)
SCITXDB 2 O SCI-B transmit data
MCLKXB 3 I/O McBSP-B transmit clock
OUTPUTXBAR3 6 O Output 3 of the output XBAR
UPP-D6 15 I/O Universal parallel port data line 6
GPIO15 0, 4, 8, 12
D3 7 6
I/O General-purpose input/output 15
EPWM8B 1 O Enhanced PWM8 output B (HRPWM-capable)
SCIRXDB 2 I SCI-B receive data
MFSXB 3 I/O McBSP-B transmit frame synch
OUTPUTXBAR4 6 O Output 4 of the output XBAR
UPP-D5 15 I/O Universal parallel port data line 5
GPIO16 0, 4, 8, 12
E1 8 7
I/O General-purpose input/output 16
SPISIMOA 1 I/O SPI-A slave in, master out
CANTXB 2 O CAN-B transmit
OUTPUTXBAR7 3 O Output 7 of the output XBAR
EPWM9A 5 O Enhanced PWM9 output A
SD1_D1 7 I Sigma-Delta 1 channel 1 data input
UPP-D4 15 I/O Universal parallel port data line 4
GPIO17 0, 4, 8, 12
E2 9 8
I/O General-purpose input/output 17
SPISOMIA 1 I/O SPI-A slave out, master in
CANRXB 2 I CAN-B receive
OUTPUTXBAR8 3 O Output 8 of the output XBAR
EPWM9B 5 O Enhanced PWM9 output B
SD1_C1 7 I Sigma-Delta 1 channel 1 clock input
UPP-D3 15 I/O Universal parallel port data line 3
GPIO18 0, 4, 8, 12
E3 10 9
I/O General-purpose input/output 18
SPICLKA 1 I/O SPI-A clock
SCITXDB 2 O SCI-B transmit data
CANRXA 3 I CAN-A receive
EPWM10A 5 O Enhanced PWM10 output A
SD1_D2 7 I Sigma-Delta 1 channel 2 data input
UPP-D2 15 I/O Universal parallel port data line 2
GPIO19 0, 4, 8, 12
E4 12 11
I/O General-purpose input/output 19
SPISTEA 1 I/O SPI-A slave transmit enable
SCIRXDB 2 I SCI-B receive data
CANTXA 3 O CAN-A transmit
EPWM10B 5 O Enhanced PWM10 output B
SD1_C2 7 I Sigma-Delta 1 channel 2 clock input
UPP-D1 15 I/O Universal parallel port data line 1
TMS320F28379S, TMS320F28378S, TMS320F28377S, TMS320F28377S-Q1
TMS320F28376S, TMS320F28375S, TMS320F28375S-Q1, TMS320F28374S
SPRS881J – AUGUST 2014 – REVISED FEBRUARY 2021 www.ti.com
20 Submit Document Feedback Copyright © 2021 Texas Instruments Incorporated
Product Folder Links: TMS320F28379S TMS320F28378S TMS320F28377S TMS320F28377S-Q1
TMS320F28376S TMS320F28375S TMS320F28375S-Q1 TMS320F28374S
TEXAS INSTRUMENTS
TERMINAL
I/O/Z(1) DESCRIPTION
NAME MUX
POSITION
ZWT
BALL
NO.
PTP
PIN
NO.
PZP
PIN
NO.
GPIO20 0, 4, 8, 12
F2 13 12
I/O General-purpose input/output 20
EQEP1A 1 I Enhanced QEP1 input A
MDXA 2 O McBSP-A transmit serial data
CANTXB 3 O CAN-B transmit
EPWM11A 5 O Enhanced PWM11 output A
SD1_D3 7 I Sigma-Delta 1 channel 3 data input
UPP-D0 15 I/O Universal parallel port data line 0
GPIO21 0, 4, 8, 12
F3 14 13
I/O General-purpose input/output 21
EQEP1B 1 I Enhanced QEP1 input B
MDRA 2 I McBSP-A receive serial data
CANRXB 3 I CAN-B receive
EPWM11B 5 O Enhanced PWM11 output B
SD1_C3 7 I Sigma-Delta 1 channel 3 clock input
UPP-CLK 15 I/O Universal parallel port transmit clock
GPIO22 0, 4, 8, 12
J4 22 –
I/O General-purpose input/output 22
EQEP1S 1 I/O Enhanced QEP1 strobe
MCLKXA 2 I/O McBSP-A transmit clock
SCITXDB 3 O SCI-B transmit data
EPWM12A 5 O Enhanced PWM12 output A
SPICLKB 6 I/O SPI-B clock
SD1_D4 7 I Sigma-Delta 1 channel 4 data input
GPIO23 0, 4, 8, 12
K4 23 –
I/O General-purpose input/output 23
EQEP1I 1 I/O Enhanced QEP1 index
MFSXA 2 I/O McBSP-A transmit frame synch
SCIRXDB 3 I SCI-B receive data
EPWM12B 5 O Enhanced PWM12 output B
SPISTEB 6 I/O SPI-B slave transmit enable
SD1_C4 7 I Sigma-Delta 1 channel 4 clock input
GPIO24 0, 4, 8, 12
K3 24 –
I/O General-purpose input/output 24
OUTPUTXBAR1 1 O Output 1 of the output XBAR
EQEP2A 2 I Enhanced QEP2 input A
MDXB 3 O McBSP-B transmit serial data
SPISIMOB 6 I/O SPI-B slave in, master out
SD2_D1 7 I Sigma-Delta 2 channel 1 data input
GPIO25 0, 4, 8, 12
K2 25 –
I/O General-purpose input/output 25
OUTPUTXBAR2 1 O Output 2 of the output XBAR
EQEP2B 2 I Enhanced QEP2 input B
MDRB 3 I McBSP-B receive serial data
SPISOMIB 6 I/O SPI-B slave out, master in
SD2_C1 7 I Sigma-Delta 2 channel 1 clock input
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TMS320F28379S, TMS320F28378S, TMS320F28377S, TMS320F28377S-Q1
TMS320F28376S, TMS320F28375S, TMS320F28375S-Q1, TMS320F28374S
SPRS881J – AUGUST 2014 – REVISED FEBRUARY 2021
Copyright © 2021 Texas Instruments Incorporated Submit Document Feedback 21
Product Folder Links: TMS320F28379S TMS320F28378S TMS320F28377S TMS320F28377S-Q1
TMS320F28376S TMS320F28375S TMS320F28375S-Q1 TMS320F28374S
TEXAS INSTRUMENTS
TERMINAL
I/O/Z(1) DESCRIPTION
NAME MUX
POSITION
ZWT
BALL
NO.
PTP
PIN
NO.
PZP
PIN
NO.
GPIO26 0, 4, 8, 12
K1 27 –
I/O General-purpose input/output 26
OUTPUTXBAR3 1 O Output 3 of the output XBAR
EQEP2I 2 I/O Enhanced QEP2 index
MCLKXB 3 I/O McBSP-B transmit clock
OUTPUTXBAR3 5 O Output 3 of the output XBAR
SPICLKB 6 I/O SPI-B clock
SD2_D2 7 I Sigma-Delta 2 channel 2 data input
GPIO27 0, 4, 8, 12
L1 28 –
I/O General-purpose input/output 27
OUTPUTXBAR4 1 O Output 4 of the output XBAR
EQEP2S 2 I/O Enhanced QEP2 strobe
MFSXB 3 I/O McBSP-B transmit frame synch
OUTPUTXBAR4 5 O Output 4 of the output XBAR
SPISTEB 6 I/O SPI-B slave transmit enable
SD2_C2 7 I Sigma-Delta 2 channel 2 clock input
GPIO28 0, 4, 8, 12
V11 64 –
I/O General-purpose input/output 28
SCIRXDA 1 I SCI-A receive data
EM1CS4 2 O External memory interface 1 chip select 4
OUTPUTXBAR5 5 O Output 5 of the output XBAR
EQEP3A 6 I Enhanced QEP3 input A
SD2_D3 7 I Sigma-Delta 2 channel 3 data input
GPIO29 0, 4, 8, 12
W11 65 –
I/O General-purpose input/output 29
SCITXDA 1 O SCI-A transmit data
EM1SDCKE 2 O External memory interface 1 SDRAM clock enable
OUTPUTXBAR6 5 O Output 6 of the output XBAR
EQEP3B 6 I Enhanced QEP3 input B
SD2_C3 7 I Sigma-Delta 2 channel 3 clock input
GPIO30 0, 4, 8, 12
T11 63 –
I/O General-purpose input/output 30
CANRXA 1 I CAN-A receive
EM1CLK 2 O External memory interface 1 clock
OUTPUTXBAR7 5 O Output 7 of the output XBAR
EQEP3S 6 I/O Enhanced QEP3 strobe
SD2_D4 7 I Sigma-Delta 2 channel 4 data input
GPIO31 0, 4, 8, 12
U11 66 –
I/O General-purpose input/output 31
CANTXA 1 O CAN-A transmit
EM1WE 2 O External memory interface 1 write enable
OUTPUTXBAR8 5 O Output 8 of the output XBAR
EQEP3I 6 I/O Enhanced QEP3 index
SD2_C4 7 I Sigma-Delta 2 channel 4 clock input
GPIO32 0, 4, 8, 12
U13 67 –
I/O General-purpose input/output 32
SDAA 1 I/OD I2C-A data open-drain bidirectional port
EM1CS0 2 O External memory interface 1 chip select 0
GPIO33 0, 4, 8, 12
T13 69 –
I/O General-purpose input/output 33
SCLA 1 I/OD I2C-A clock open-drain bidirectional port
EM1RNW 2 O External memory interface 1 read not write
TMS320F28379S, TMS320F28378S, TMS320F28377S, TMS320F28377S-Q1
TMS320F28376S, TMS320F28375S, TMS320F28375S-Q1, TMS320F28374S
SPRS881J – AUGUST 2014 – REVISED FEBRUARY 2021 www.ti.com
22 Submit Document Feedback Copyright © 2021 Texas Instruments Incorporated
Product Folder Links: TMS320F28379S TMS320F28378S TMS320F28377S TMS320F28377S-Q1
TMS320F28376S TMS320F28375S TMS320F28375S-Q1 TMS320F28374S
TEXAS INSTRUMENTS
TERMINAL
I/O/Z(1) DESCRIPTION
NAME MUX
POSITION
ZWT
BALL
NO.
PTP
PIN
NO.
PZP
PIN
NO.
GPIO34 0, 4, 8, 12
U14 70 –
I/O General-purpose input/output 34
OUTPUTXBAR1 1 O Output 1 of the output XBAR
EM1CS2 2 O External memory interface 1 chip select 2
SDAB 6 I/OD I2C-B data open-drain bidirectional port
GPIO35 0, 4, 8, 12
T14 71 –
I/O General-purpose input/output 35
SCIRXDA 1 I SCI-A receive data
EM1CS3 2 O External memory interface 1 chip select 3
SCLB 6 I/OD I2C-B clock open-drain bidirectional port
GPIO36 0, 4, 8, 12
V16 83 –
I/O General-purpose input/output 36
SCITXDA 1 O SCI-A transmit data
EM1WAIT 2 I External memory interface 1 Asynchronous SRAM WAIT
CANRXA 6 I CAN-A receive
GPIO37 0, 4, 8, 12
U16 84 –
I/O General-purpose input/output 37
OUTPUTXBAR2 1 O Output 2 of the output XBAR
EM1OE 2 O External memory interface 1 output enable
CANTXA 6 O CAN-A transmit
GPIO38 0, 4, 8, 12
T16 85 –
I/O General-purpose input/output 38
EM1A0 2 O External memory interface 1 address line 0
SCITXDC 5 O SCI-C transmit data
CANTXB 6 O CAN-B transmit
GPIO39 0, 4, 8, 12
W17 86 –
I/O General-purpose input/output 39
EM1A1 2 O External memory interface 1 address line 1
SCIRXDC 5 I SCI-C receive data
CANRXB 6 I CAN-B receive
GPIO40 0, 4, 8, 12
V17 87 –
I/O General-purpose input/output 40
EM1A2 2 O External memory interface 1 address line 2
SDAB 6 I/OD I2C-B data open-drain bidirectional port
GPIO41 0, 4, 8, 12
U17 89 51
I/O General-purpose input/output 41. For applications using
the Hibernate low-power mode, this pin serves as the
GPIOHIBWAKE signal. For details, see the Low Power
Modes section of the System Control chapter in the
TMS320F2837xS Microcontrollers Technical Reference
Manual .
EM1A3 2 O External memory interface 1 address line 3
SCLB 6 I/OD I2C-B clock open-drain bidirectional port
GPIO42 0, 4, 8, 12
D19 130 73
I/O General-purpose input/output 42
SDAA 6 I/OD I2C-A data open-drain bidirectional port
SCITXDA 15 O SCI-A transmit data
USB0DM Analog I/O USB PHY differential data
GPIO43 0, 4, 8, 12
C19 131 74
I/O General-purpose input/output 43
SCLA 6 I/OD I2C-A clock open-drain bidirectional port
SCIRXDA 15 I SCI-A receive data
USB0DP Analog I/O USB PHY differential data
GPIO44 0, 4, 8, 12 K18 113 – I/O General-purpose input/output 44
EM1A4 2 O External memory interface 1 address line 4
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TMS320F28379S, TMS320F28378S, TMS320F28377S, TMS320F28377S-Q1
TMS320F28376S, TMS320F28375S, TMS320F28375S-Q1, TMS320F28374S
SPRS881J – AUGUST 2014 – REVISED FEBRUARY 2021
Copyright © 2021 Texas Instruments Incorporated Submit Document Feedback 23
Product Folder Links: TMS320F28379S TMS320F28378S TMS320F28377S TMS320F28377S-Q1
TMS320F28376S TMS320F28375S TMS320F28375S-Q1 TMS320F28374S
TEXAS INSTRUMENTS
TERMINAL
I/O/Z(1) DESCRIPTION
NAME MUX
POSITION
ZWT
BALL
NO.
PTP
PIN
NO.
PZP
PIN
NO.
GPIO45 0, 4, 8, 12 K19 115 – I/O General-purpose input/output 45
EM1A5 2 O External memory interface 1 address line 5
GPIO46 0, 4, 8, 12
E19 128 –
I/O General-purpose input/output 46
EM1A6 2 O External memory interface 1 address line 6
SCIRXDD 6 I SCI-D receive data
GPIO47 0, 4, 8, 12
E18 129 –
I/O General-purpose input/output 47
EM1A7 2 O External memory interface 1 address line 7
SCITXDD 6 O SCI-D transmit data
GPIO48 0, 4, 8, 12
R16 90 –
I/O General-purpose input/output 48
OUTPUTXBAR3 1 O Output 3 of the output XBAR
EM1A8 2 O External memory interface 1 address line 8
SCITXDA 6 O SCI-A transmit data
SD1_D1 7 I Sigma-Delta 1 channel 1 data input
GPIO49 0, 4, 8, 12
R17 93 –
I/O General-purpose input/output 49
OUTPUTXBAR4 1 O Output 4 of the output XBAR
EM1A9 2 O External memory interface 1 address line 9
SCIRXDA 6 I SCI-A receive data
SD1_C1 7 I Sigma-Delta 1 channel 1 clock input
GPIO50 0, 4, 8, 12
R18 94 –
I/O General-purpose input/output 50
EQEP1A 1 I Enhanced QEP1 input A
EM1A10 2 O External memory interface 1 address line 10
SPISIMOC 6 I/O SPI-C slave in, master out
SD1_D2 7 I Sigma-Delta 1 channel 2 data input
GPIO51 0, 4, 8, 12
R19 95 –
I/O General-purpose input/output 51
EQEP1B 1 I Enhanced QEP1 input B
EM1A11 2 O External memory interface 1 address line 11
SPISOMIC 6 I/O SPI-C slave out, master in
SD1_C2 7 I Sigma-Delta 1 channel 2 clock input
GPIO52 0, 4, 8, 12
P16 96 –
I/O General-purpose input/output 52
EQEP1S 1 I/O Enhanced QEP1 strobe
EM1A12 2 O External memory interface 1 address line 12
SPICLKC 6 I/O SPI-C clock
SD1_D3 7 I Sigma-Delta 1 channel 3 data input
GPIO53 0, 4, 8, 12
P17 97 –
I/O General-purpose input/output 53
EQEP1I 1 I/O Enhanced QEP1 index
EM1D31 2 I/O External memory interface 1 data line 31
EM2D15 3 I/O External memory interface 2 data line 15
SPISTEC 6 I/O SPI-C slave transmit enable
SD1_C3 7 I Sigma-Delta 1 channel 3 clock input
TMS320F28379S, TMS320F28378S, TMS320F28377S, TMS320F28377S-Q1
TMS320F28376S, TMS320F28375S, TMS320F28375S-Q1, TMS320F28374S
SPRS881J – AUGUST 2014 – REVISED FEBRUARY 2021 www.ti.com
24 Submit Document Feedback Copyright © 2021 Texas Instruments Incorporated
Product Folder Links: TMS320F28379S TMS320F28378S TMS320F28377S TMS320F28377S-Q1
TMS320F28376S TMS320F28375S TMS320F28375S-Q1 TMS320F28374S
TEXAS INSTRUMENTS
TERMINAL
I/O/Z(1) DESCRIPTION
NAME MUX
POSITION
ZWT
BALL
NO.
PTP
PIN
NO.
PZP
PIN
NO.
GPIO54 0, 4, 8, 12
P18 98 –
I/O General-purpose input/output 54
SPISIMOA 1 I/O SPI-A slave in, master out
EM1D30 2 I/O External memory interface 1 data line 30
EM2D14 3 I/O External memory interface 2 data line 14
EQEP2A 5 I Enhanced QEP2 input A
SCITXDB 6 O SCI-B transmit data
SD1_D4 7 I Sigma-Delta 1 channel 4 data input
GPIO55 0, 4, 8, 12
P19 100 –
I/O General-purpose input/output 55
SPISOMIA 1 I/O SPI-A slave out, master in
EM1D29 2 I/O External memory interface 1 data line 29
EM2D13 3 I/O External memory interface 2 data line 13
EQEP2B 5 I Enhanced QEP2 input B
SCIRXDB 6 I SCI-B receive data
SD1_C4 7 I Sigma-Delta 1 channel 4 clock input
GPIO56 0, 4, 8, 12
N16 101 –
I/O General-purpose input/output 56
SPICLKA 1 I/O SPI-A clock
EM1D28 2 I/O External memory interface 1 data line 28
EM2D12 3 I/O External memory interface 2 data line 12
EQEP2S 5 I/O Enhanced QEP2 strobe
SCITXDC 6 O SCI-C transmit data
SD2_D1 7 I Sigma-Delta 2 channel 1 data input
GPIO57 0, 4, 8, 12
N18 102 –
I/O General-purpose input/output 57
SPISTEA 1 I/O SPI-A slave transmit enable
EM1D27 2 I/O External memory interface 1 data line 27
EM2D11 3 I/O External memory interface 2 data line 11
EQEP2I 5 I/O Enhanced QEP2 index
SCIRXDC 6 I SCI-C receive data
SD2_C1 7 I Sigma-Delta 2 channel 1 clock input
GPIO58 0, 4, 8, 12
N17 103 52
I/O General-purpose input/output 58
MCLKRA 1 I/O McBSP-A receive clock
EM1D26 2 I/O External memory interface 1 data line 26
EM2D10 3 I/O External memory interface 2 data line 10
OUTPUTXBAR1 5 O Output 1 of the output XBAR
SPICLKB 6 I/O SPI-B clock
SD2_D2 7 I Sigma-Delta 2 channel 2 data input
SPISIMOA 15 I/O SPI-A slave in, master out(2)
GPIO59 0, 4, 8, 12
M16 104 53
I/O General-purpose input/output 59(3)
MFSRA 1 I/O McBSP-A receive frame synch
EM1D25 2 I/O External memory interface 1 data line 25
EM2D9 3 I/O External memory interface 2 data line 9
OUTPUTXBAR2 5 O Output 2 of the output XBAR
SPISTEB 6 I/O SPI-B slave transmit enable
SD2_C2 7 I Sigma-Delta 2 channel 2 clock input
SPISOMIA 15 I/O SPI-A slave out, master in(2)
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TMS320F28379S, TMS320F28378S, TMS320F28377S, TMS320F28377S-Q1
TMS320F28376S, TMS320F28375S, TMS320F28375S-Q1, TMS320F28374S
SPRS881J – AUGUST 2014 – REVISED FEBRUARY 2021
Copyright © 2021 Texas Instruments Incorporated Submit Document Feedback 25
Product Folder Links: TMS320F28379S TMS320F28378S TMS320F28377S TMS320F28377S-Q1
TMS320F28376S TMS320F28375S TMS320F28375S-Q1 TMS320F28374S
TEXAS INSTRUMENTS
TERMINAL
I/O/Z(1) DESCRIPTION
NAME MUX
POSITION
ZWT
BALL
NO.
PTP
PIN
NO.
PZP
PIN
NO.
GPIO60 0, 4, 8, 12
M17 105 54
I/O General-purpose input/output 60
MCLKRB 1 I/O McBSP-B receive clock
EM1D24 2 I/O External memory interface 1 data line 24
EM2D8 3 I/O External memory interface 2 data line 8
OUTPUTXBAR3 5 O Output 3 of the output XBAR
SPISIMOB 6 I/O SPI-B slave in, master out
SD2_D3 7 I Sigma-Delta 2 channel 3 data input
SPICLKA 15 I/O SPI-A clock(2)
GPIO61 0, 4, 8, 12
L16 107 56
I/O General-purpose input/output 61(3)
MFSRB 1 I/O McBSP-B receive frame synch
EM1D23 2 I/O External memory interface 1 data line 23
EM2D7 3 I/O External memory interface 2 data line 7
OUTPUTXBAR4 5 O Output 4 of the output XBAR
SPISOMIB 6 I/O SPI-B slave out, master in
SD2_C3 7 I Sigma-Delta 2 channel 3 clock input
SPISTEA 15 I/O SPI-A slave transmit enable(2)
GPIO62 0, 4, 8, 12
J17 108 57
I/O General-purpose input/output 62
SCIRXDC 1 I SCI-C receive data
EM1D22 2 I/O External memory interface 1 data line 22
EM2D6 3 I/O External memory interface 2 data line 6
EQEP3A 5 I Enhanced QEP3 input A
CANRXA 6 I CAN-A receive
SD2_D4 7 I Sigma-Delta 2 channel 4 data input
GPIO63 0, 4, 8, 12
J16 109 58
I/O General-purpose input/output 63
SCITXDC 1 O SCI-C transmit data
EM1D21 2 I/O External memory interface 1 data line 21
EM2D5 3 I/O External memory interface 2 data line 5
EQEP3B 5 I Enhanced QEP3 input B
CANTXA 6 O CAN-A transmit
SD2_C4 7 I Sigma-Delta 2 channel 4 clock input
SPISIMOB 15 I/O SPI-B slave in, master out(2)
GPIO64 0, 4, 8, 12
L17 110 59
I/O General-purpose input/output 64(3)
EM1D20 2 I/O External memory interface 1 data line 20
EM2D4 3 I/O External memory interface 2 data line 4
EQEP3S 5 I/O Enhanced QEP3 strobe
SCIRXDA 6 I SCI-A receive data
SPISOMIB 15 I/O SPI-B slave out, master in(2)
GPIO65 0, 4, 8, 12
K16 111 60
I/O General-purpose input/output 65
EM1D19 2 I/O External memory interface 1 data line 19
EM2D3 3 I/O External memory interface 2 data line 3
EQEP3I 5 I/O Enhanced QEP3 index
SCITXDA 6 O SCI-A transmit data
SPICLKB 15 I/O SPI-B clock(2)
TMS320F28379S, TMS320F28378S, TMS320F28377S, TMS320F28377S-Q1
TMS320F28376S, TMS320F28375S, TMS320F28375S-Q1, TMS320F28374S
SPRS881J – AUGUST 2014 – REVISED FEBRUARY 2021 www.ti.com
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Product Folder Links: TMS320F28379S TMS320F28378S TMS320F28377S TMS320F28377S-Q1
TMS320F28376S TMS320F28375S TMS320F28375S-Q1 TMS320F28374S
TEXAS INSTRUMENTS
TERMINAL
I/O/Z(1) DESCRIPTION
NAME MUX
POSITION
ZWT
BALL
NO.
PTP
PIN
NO.
PZP
PIN
NO.
GPIO66 0, 4, 8, 12
K17 112 61
I/O General-purpose input/output 66(3)
EM1D18 2 I/O External memory interface 1 data line 18
EM2D2 3 I/O External memory interface 2 data line 2
SDAB 6 I/OD I2C-B data open-drain bidirectional port
SPISTEB 15 I/O SPI-B slave transmit enable(2)
GPIO67 0, 4, 8, 12
B19 132 –
I/O General-purpose input/output 67
EM1D17 2 I/O External memory interface 1 data line 17
EM2D1 3 I/O External memory interface 2 data line 1
GPIO68 0, 4, 8, 12
C18 133 –
I/O General-purpose input/output 68
EM1D16 2 I/O External memory interface 1 data line 16
EM2D0 3 I/O External memory interface 2 data line 0
GPIO69 0, 4, 8, 12
B18 134 75
I/O General-purpose input/output 69
EM1D15 2 I/O External memory interface 1 data line 15
SCLB 6 I/OD I2C-B clock open-drain bidirectional port
SPISIMOC 15 I/O SPI-C slave in, master out(2)
GPIO70 0, 4, 8, 12
A17 135 76
I/O General-purpose input/output 70(3)
EM1D14 2 I/O External memory interface 1 data line 14
CANRXA 5 I CAN-A receive
SCITXDB 6 O SCI-B transmit data
SPISOMIC 15 I/O SPI-C slave out, master in(2)
GPIO71 0, 4, 8, 12
B17 136 77
I/O General-purpose input/output 71
EM1D13 2 I/O External memory interface 1 data line 13
CANTXA 5 O CAN-A transmit
SCIRXDB 6 I SCI-B receive data
SPICLKC 15 I/O SPI-C clock(2)
GPIO72 0, 4, 8, 12
B16 139 80
I/O General-purpose input/output 72.(3) This is the factory
default boot mode select pin 1.
EM1D12 2 I/O External memory interface 1 data line 12
CANTXB 5 O CAN-B transmit
SCITXDC 6 O SCI-C transmit data
SPISTEC 15 I/O SPI-C slave transmit enable(2)
GPIO73 0, 4, 8, 12
A16 140 81
I/O General-purpose input/output 73
EM1D11 2 I/O External memory interface 1 data line 11
XCLKOUT 3 O/Z External clock output. This pin outputs a divided-down
version of a chosen clock signal from within the device.
The clock signal is chosen using the
CLKSRCCTL3.XCLKOUTSEL bit field while the divide
ratio is chosen using the
XCLKOUTDIVSEL.XCLKOUTDIV bit field.
CANRXB 5 I CAN-B receive
SCIRXDC 6 I SCI-C receive
GPIO74 0, 4, 8, 12 C17 141 – I/O General-purpose input/output 74
EM1D10 2 I/O External memory interface 1 data line 10
GPIO75 0, 4, 8, 12 D16 142 – I/O General-purpose input/output 75
EM1D9 2 I/O External memory interface 1 data line 9
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TMS320F28379S, TMS320F28378S, TMS320F28377S, TMS320F28377S-Q1
TMS320F28376S, TMS320F28375S, TMS320F28375S-Q1, TMS320F28374S
SPRS881J – AUGUST 2014 – REVISED FEBRUARY 2021
Copyright © 2021 Texas Instruments Incorporated Submit Document Feedback 27
Product Folder Links: TMS320F28379S TMS320F28378S TMS320F28377S TMS320F28377S-Q1
TMS320F28376S TMS320F28375S TMS320F28375S-Q1 TMS320F28374S
TEXAS INSTRUMENTS
TERMINAL
I/O/Z(1) DESCRIPTION
NAME MUX
POSITION
ZWT
BALL
NO.
PTP
PIN
NO.
PZP
PIN
NO.
GPIO76 0, 4, 8, 12
C16 143 –
I/O General-purpose input/output 76
EM1D8 2 I/O External memory interface 1 data line 8
SCITXDD 6 O SCI-D transmit data
GPIO77 0, 4, 8, 12
A15 144 –
I/O General-purpose input/output 77
EM1D7 2 I/O External memory interface 1 data line 7
SCIRXDD 6 I SCI-D receive data
GPIO78 0, 4, 8, 12
B15 145 82
I/O General-purpose input/output 78
EM1D6 2 I/O External memory interface 1 data line 6
EQEP2A 6 I Enhanced QEP2 input A
GPIO79 0, 4, 8, 12
C15 146 –
I/O General-purpose input/output 79
EM1D5 2 I/O External memory interface 1 data line 5
EQEP2B 6 I Enhanced QEP2 input B
GPIO80 0, 4, 8, 12
D15 148 –
I/O General-purpose input/output 80
EM1D4 2 I/O External memory interface 1 data line 4
EQEP2S 6 I/O Enhanced QEP2 strobe
GPIO81 0, 4, 8, 12
A14 149 –
I/O General-purpose input/output 81
EM1D3 2 I/O External memory interface 1 data line 3
EQEP2I 6 I/O Enhanced QEP2 index
GPIO82 0, 4, 8, 12 B14 150 – I/O General-purpose input/output 82
EM1D2 2 I/O External memory interface 1 data line 2
GPIO83 0, 4, 8, 12 C14 151 – I/O General-purpose input/output 83
EM1D1 2 I/O External memory interface 1 data line 1
GPIO84 0, 4, 8, 12
A11 154 85
I/O General-purpose input/output 84. This is the factory
default boot mode select pin 0.
SCITXDA 5 O SCI-A transmit data
MDXB 6 O McBSP-B transmit serial data
MDXA 15 O McBSP-A transmit serial data
GPIO85 0, 4, 8, 12
B11 155 86
I/O General-purpose input/output 85
EM1D0 2 I/O External memory interface 1 data line 0
SCIRXDA 5 I SCI-A receive data
MDRB 6 I McBSP-B receive serial data
MDRA 15 I McBSP-A receive serial data
GPIO86 0, 4, 8, 12
C11 156 87
I/O General-purpose input/output 86
EM1A13 2 O External memory interface 1 address line 13
EM1CAS 3 O External memory interface 1 column address strobe
SCITXDB 5 O SCI-B transmit data
MCLKXB 6 I/O McBSP-B transmit clock
MCLKXA 15 I/O McBSP-A transmit clock
GPIO87 0, 4, 8, 12
D11 157 88
I/O General-purpose input/output 87
EM1A14 2 O External memory interface 1 address line 14
EM1RAS 3 O External memory interface 1 row address strobe
SCIRXDB 5 I SCI-B receive data
MFSXB 6 I/O McBSP-B transmit frame synch
MFSXA 15 I/O McBSP-A transmit frame synch
TMS320F28379S, TMS320F28378S, TMS320F28377S, TMS320F28377S-Q1
TMS320F28376S, TMS320F28375S, TMS320F28375S-Q1, TMS320F28374S
SPRS881J – AUGUST 2014 – REVISED FEBRUARY 2021 www.ti.com
28 Submit Document Feedback Copyright © 2021 Texas Instruments Incorporated
Product Folder Links: TMS320F28379S TMS320F28378S TMS320F28377S TMS320F28377S-Q1
TMS320F28376S TMS320F28375S TMS320F28375S-Q1 TMS320F28374S
TEXAS INSTRUMENTS
TERMINAL
I/O/Z(1) DESCRIPTION
NAME MUX
POSITION
ZWT
BALL
NO.
PTP
PIN
NO.
PZP
PIN
NO.
GPIO88 0, 4, 8, 12
C6 170 –
I/O General-purpose input/output 88
EM1A15 2 O External memory interface 1 address line 15
EM1DQM0 3 O External memory interface 1 Input/output mask for byte 0
GPIO89 0, 4, 8, 12
D6 171 96
I/O General-purpose input/output 89
EM1A16 2 O External memory interface 1 address line 16
EM1DQM1 3 O External memory interface 1 Input/output mask for byte 1
SCITXDC 6 O SCI-C transmit data
GPIO90 0, 4, 8, 12
A5 172 97
I/O General-purpose input/output 90
EM1A17 2 O External memory interface 1 address line 17
EM1DQM2 3 O External memory interface 1 Input/output mask for byte 2
SCIRXDC 6 I SCI-C receive data
GPIO91 0, 4, 8, 12
B5 173 98
I/O General-purpose input/output 91
EM1A18 2 O External memory interface 1 address line 18
EM1DQM3 3 O External memory interface 1 Input/output mask for byte 3
SDAA 6 I/OD I2C-A data open-drain bidirectional port
GPIO92 0, 4, 8, 12
A4 174 99
I/O General-purpose input/output 92
EM1A19 2 O External memory interface 1 address line 19
EM1BA1 3 O External memory interface 1 bank address 1
SCLA 6 I/OD I2C-A clock open-drain bidirectional port
GPIO93 0, 4, 8, 12
B4 175 –
I/O General-purpose input/output 93
EM1BA0 3 O External memory interface 1 bank address 0
SCITXDD 6 O SCI-D transmit data
GPIO94 0, 4, 8, 12 A3 176 – I/O General-purpose input/output 94
SCIRXDD 6 I SCI-D receive data
GPIO95 0, 4, 8, 12 B3 – – I/O General-purpose input/output 95
GPIO96 0, 4, 8, 12
C3 – –
I/O General-purpose input/output 96
EM2DQM1 3 O External memory interface 2 Input/output mask for byte 1
EQEP1A 5 I Enhanced QEP1 input A
GPIO97 0, 4, 8, 12
A2 – –
I/O General-purpose input/output 97
EM2DQM0 3 O External memory interface 2 Input/output mask for byte 0
EQEP1B 5 I Enhanced QEP1 input B
GPIO98 0, 4, 8, 12
F1 – –
I/O General-purpose input/output 98
EM2A0 3 O External memory interface 2 address line 0
EQEP1S 5 I/O Enhanced QEP1 strobe
GPIO99 0, 4, 8, 12
G1 17 14
I/O General-purpose input/output 99
EM2A1 3 O External memory interface 2 address line 1
EQEP1I 5 I/O Enhanced QEP1 index
GPIO100 0, 4, 8, 12
H1 – –
I/O General-purpose input/output 100
EM2A2 3 O External memory interface 2 address line 2
EQEP2A 5 I Enhanced QEP2 input A
SPISIMOC 6 I/O SPI-C slave in, master out
GPIO101 0, 4, 8, 12
H2 – –
I/O General-purpose input/output 101
EM2A3 3 O External memory interface 2 address line 3
EQEP2B 5 I Enhanced QEP2 input B
SPISOMIC 6 I/O SPI-C slave out, master in
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TMS320F28379S, TMS320F28378S, TMS320F28377S, TMS320F28377S-Q1
TMS320F28376S, TMS320F28375S, TMS320F28375S-Q1, TMS320F28374S
SPRS881J – AUGUST 2014 – REVISED FEBRUARY 2021
Copyright © 2021 Texas Instruments Incorporated Submit Document Feedback 29
Product Folder Links: TMS320F28379S TMS320F28378S TMS320F28377S TMS320F28377S-Q1
TMS320F28376S TMS320F28375S TMS320F28375S-Q1 TMS320F28374S
TEXAS INSTRUMENTS
TERMINAL
I/O/Z(1) DESCRIPTION
NAME MUX
POSITION
ZWT
BALL
NO.
PTP
PIN
NO.
PZP
PIN
NO.
GPIO102 0, 4, 8, 12
H3 – –
I/O General-purpose input/output 102
EM2A4 3 O External memory interface 2 address line 4
EQEP2S 5 I/O Enhanced QEP2 strobe
SPICLKC 6 I/O SPI-C clock
GPIO103 0, 4, 8, 12
J1 – –
I/O General-purpose input/output 103
EM2A5 3 O External memory interface 2 address line 5
EQEP2I 5 I/O Enhanced QEP2 index
SPISTEC 6 I/O SPI-C slave transmit enable
GPIO104 0, 4, 8, 12
J2 – –
I/O General-purpose input/output 104
SDAA 1 I/OD I2C-A data open-drain bidirectional port
EM2A6 3 O External memory interface 2 address line 6
EQEP3A 5 I Enhanced QEP3 input A
SCITXDD 6 O SCI-D transmit data
GPIO105 0, 4, 8, 12
J3 – –
I/O General-purpose input/output 105
SCLA 1 I/OD I2C-A clock open-drain bidirectional port
EM2A7 3 O External memory interface 2 address line 7
EQEP3B 5 I Enhanced QEP3 input B
SCIRXDD 6 I SCI-D receive data
GPIO106 0, 4, 8, 12
L2 – –
I/O General-purpose input/output 106
EM2A8 3 O External memory interface 2 address line 8
EQEP3S 5 I/O Enhanced QEP3 strobe
SCITXDC 6 O SCI-C transmit data
GPIO107 0, 4, 8, 12
L3 – –
I/O General-purpose input/output 107
EM2A9 3 O External memory interface 2 address line 9
EQEP3I 5 I/O Enhanced QEP3 index
SCIRXDC 6 I SCI-C receive data
GPIO108 0, 4, 8, 12 L4 – – I/O General-purpose input/output 108
EM2A10 3 O External memory interface 2 address line 10
GPIO109 0, 4, 8, 12 N2 – – I/O General-purpose input/output 109
EM2A11 3 O External memory interface 2 address line 11
GPIO110 0, 4, 8, 12 M2 – – I/O General-purpose input/output 110
EM2WAIT 3 I External memory interface 2 Asynchronous SRAM WAIT
GPIO111 0, 4, 8, 12 M4 – – I/O General-purpose input/output 111
EM2BA0 3 O External memory interface 2 bank address 0
GPIO112 0, 4, 8, 12 M3 – – I/O General-purpose input/output 112
EM2BA1 3 O External memory interface 2 bank address 1
GPIO113 0, 4, 8, 12 N4 – – I/O General-purpose input/output 113
EM2CAS 3 O External memory interface 2 column address strobe
GPIO114 0, 4, 8, 12 N3 – – I/O General-purpose input/output 114
EM2RAS 3 O External memory interface 2 row address strobe
GPIO115 0, 4, 8, 12 V12 – – I/O General-purpose input/output 115
EM2CS0 3 O External memory interface 2 chip select 0
GPIO116 0, 4, 8, 12 W10 – – I/O General-purpose input/output 116
EM2CS2 3 O External memory interface 2 chip select 2
TMS320F28379S, TMS320F28378S, TMS320F28377S, TMS320F28377S-Q1
TMS320F28376S, TMS320F28375S, TMS320F28375S-Q1, TMS320F28374S
SPRS881J – AUGUST 2014 – REVISED FEBRUARY 2021 www.ti.com
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Product Folder Links: TMS320F28379S TMS320F28378S TMS320F28377S TMS320F28377S-Q1
TMS320F28376S TMS320F28375S TMS320F28375S-Q1 TMS320F28374S
TEXAS INSTRUMENTS
TERMINAL
I/O/Z(1) DESCRIPTION
NAME MUX
POSITION
ZWT
BALL
NO.
PTP
PIN
NO.
PZP
PIN
NO.
GPIO117 0, 4, 8, 12 U12 – – I/O General-purpose input/output 117
EM2SDCKE 3 O External memory interface 2 SDRAM clock enable
GPIO118 0, 4, 8, 12 T12 – – I/O General-purpose input/output 118
EM2CLK 3 O External memory interface 2 clock
GPIO119 0, 4, 8, 12 T15 – – I/O General-purpose input/output 119
EM2RNW 3 O External memory interface 2 read not write
GPIO120 0, 4, 8, 12
U15 – –
I/O General-purpose input/output 120
EM2WE 3 O External memory interface 2 write enable
USB0PFLT 15 I/O USB external regulator power fault indicator
GPIO121 0, 4, 8, 12
W16 – –
I/O General-purpose input/output 121
EM2OE 3 O External memory interface 2 output enable
USB0EPEN 15 I/O USB external regulator enable
GPIO122 0, 4, 8, 12
T8 – –
I/O General-purpose input/output 122
SPISIMOC 6 I/O SPI-C slave in, master out
SD1_D1 7 I Sigma-Delta 1 channel 1 data input
GPIO123 0, 4, 8, 12
U8 – –
I/O General-purpose input/output 123
SPISOMIC 6 I/O SPI-C slave out, master in
SD1_C1 7 I Sigma-Delta 1 channel 1 clock input
GPIO124 0, 4, 8, 12
V8 – –
I/O General-purpose input/output 124
SPICLKC 6 I/O SPI-C clock
SD1_D2 7 I Sigma-Delta 1 channel 2 data input
GPIO125 0, 4, 8, 12
T9 – –
I/O General-purpose input/output 125
SPISTEC 6 I/O SPI-C slave transmit enable
SD1_C2 7 I Sigma-Delta 1 channel 2 clock input
GPIO126 0, 4, 8, 12 U9 – – I/O General-purpose input/output 126
SD1_D3 7 I Sigma-Delta 1 channel 3 data input
GPIO127 0, 4, 8, 12 V9 – – I/O General-purpose input/output 127
SD1_C3 7 I Sigma-Delta 1 channel 3 clock input
GPIO128 0, 4, 8, 12 W9 – – I/O General-purpose input/output 128
SD1_D4 7 I Sigma-Delta 1 channel 4 data input
GPIO129 0, 4, 8, 12 T10 – – I/O General-purpose input/output 129
SD1_C4 7 I Sigma-Delta 1 channel 4 clock input
GPIO130 0, 4, 8, 12 U10 – – I/O General-purpose input/output 130
SD2_D1 7 I Sigma-Delta 2 channel 1 data input
GPIO131 0, 4, 8, 12 V10 – – I/O General-purpose input/output 131
SD2_C1 7 I Sigma-Delta 2 channel 1 clock input
GPIO132 0, 4, 8, 12 W18 – – I/O General-purpose input/output 132
SD2_D2 7 I Sigma-Delta 2 channel 2 data input
GPIO133/AUXCLKIN 0, 4, 8, 12
G18 118 –
I/O General-purpose input/output 133. The AUXCLKIN
function of this GPIO pin could be used to provide a
single-ended 3.3-V level clock signal to the Auxiliary
Phase-Locked Loop (AUXPLL), whose output is used for
the USB module. The AUXCLKIN clock may also be used
for the CAN module.
SD2_C2 7 I Sigma-Delta 2 channel 2 clock input
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TMS320F28379S, TMS320F28378S, TMS320F28377S, TMS320F28377S-Q1
TMS320F28376S, TMS320F28375S, TMS320F28375S-Q1, TMS320F28374S
SPRS881J – AUGUST 2014 – REVISED FEBRUARY 2021
Copyright © 2021 Texas Instruments Incorporated Submit Document Feedback 31
Product Folder Links: TMS320F28379S TMS320F28378S TMS320F28377S TMS320F28377S-Q1
TMS320F28376S TMS320F28375S TMS320F28375S-Q1 TMS320F28374S
TEXAS INSTRUMENTS
TERMINAL
I/O/Z(1) DESCRIPTION
NAME MUX
POSITION
ZWT
BALL
NO.
PTP
PIN
NO.
PZP
PIN
NO.
GPIO134 0, 4, 8, 12 V18 – – I/O General-purpose input/output 134
SD2_D3 7 I Sigma-Delta 2 channel 3 data input
GPIO135 0, 4, 8, 12
U18 – –
I/O General-purpose input/output 135
SCITXDA 6 O SCI-A transmit data
SD2_C3 7 I Sigma-Delta 2 channel 3 clock input
GPIO136 0, 4, 8, 12
T17 – –
I/O General-purpose input/output 136
SCIRXDA 6 I SCI-A receive data
SD2_D4 7 I Sigma-Delta 2 channel 4 data input
GPIO137 0, 4, 8, 12
T18 – –
I/O General-purpose input/output 137
SCITXDB 6 O SCI-B transmit data
SD2_C4 7 I Sigma-Delta 2 channel 4 clock input
GPIO138 0, 4, 8, 12 T19 – – I/O General-purpose input/output 138
SCIRXDB 6 I SCI-B receive data
GPIO139 0, 4, 8, 12 N19 – – I/O General-purpose input/output 139
SCIRXDC 6 I SCI-C receive data
GPIO140 0, 4, 8, 12 M19 – – I/O General-purpose input/output 140
SCITXDC 6 O SCI-C transmit data
GPIO141 0, 4, 8, 12 M18 – – I/O General-purpose input/output 141
SCIRXDD 6 I SCI-D receive data
GPIO142 0, 4, 8, 12 L19 – – I/O General-purpose input/output 142
SCITXDD 6 O SCI-D transmit data
GPIO143 0, 4, 8, 12 F18 – – I/O General-purpose input/output 143
GPIO144 0, 4, 8, 12 F17 – – I/O General-purpose input/output 144
GPIO145 0, 4, 8, 12 E17 – – I/O General-purpose input/output 145
EPWM1A 1 O Enhanced PWM1 output A (HRPWM-capable)
GPIO146 0, 4, 8, 12 D18 – – I/O General-purpose input/output 146
EPWM1B 1 O Enhanced PWM1 output B (HRPWM-capable)
GPIO147 0, 4, 8, 12 D17 – – I/O General-purpose input/output 147
EPWM2A 1 O Enhanced PWM2 output A (HRPWM-capable)
GPIO148 0, 4, 8, 12 D14 – – I/O General-purpose input/output 148
EPWM2B 1 O Enhanced PWM2 output B (HRPWM-capable)
GPIO149 0, 4, 8, 12 A13 – – I/O General-purpose input/output 149
EPWM3A 1 O Enhanced PWM3 output A (HRPWM-capable)
GPIO150 0, 4, 8, 12 B13 – – I/O General-purpose input/output 150
EPWM3B 1 O Enhanced PWM3 output B (HRPWM-capable)
GPIO151 0, 4, 8, 12 C13 – – I/O General-purpose input/output 151
EPWM4A 1 O Enhanced PWM4 output A (HRPWM-capable)
GPIO152 0, 4, 8, 12 D13 – – I/O General-purpose input/output 152
EPWM4B 1 O Enhanced PWM4 output B (HRPWM-capable)
GPIO153 0, 4, 8, 12 A12 – – I/O General-purpose input/output 153
EPWM5A 1 O Enhanced PWM5 output A (HRPWM-capable)
GPIO154 0, 4, 8, 12 B12 – – I/O General-purpose input/output 154
EPWM5B 1 O Enhanced PWM5 output B (HRPWM-capable)
TMS320F28379S, TMS320F28378S, TMS320F28377S, TMS320F28377S-Q1
TMS320F28376S, TMS320F28375S, TMS320F28375S-Q1, TMS320F28374S
SPRS881J – AUGUST 2014 – REVISED FEBRUARY 2021 www.ti.com
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Product Folder Links: TMS320F28379S TMS320F28378S TMS320F28377S TMS320F28377S-Q1
TMS320F28376S TMS320F28375S TMS320F28375S-Q1 TMS320F28374S
TEXAS INSTRUMENTS
TERMINAL
I/O/Z(1) DESCRIPTION
NAME MUX
POSITION
ZWT
BALL
NO.
PTP
PIN
NO.
PZP
PIN
NO.
GPIO155 0, 4, 8, 12 C12 – – I/O General-purpose input/output 155
EPWM6A 1 O Enhanced PWM6 output A (HRPWM-capable)
GPIO156 0, 4, 8, 12 D12 – – I/O General-purpose input/output 156
EPWM6B 1 O Enhanced PWM6 output B (HRPWM-capable)
GPIO157 0, 4, 8, 12 B10 – – I/O General-purpose input/output 157
EPWM7A 1 O Enhanced PWM7 output A (HRPWM-capable)
GPIO158 0, 4, 8, 12 C10 – – I/O General-purpose input/output 158
EPWM7B 1 O Enhanced PWM7 output B (HRPWM-capable)
GPIO159 0, 4, 8, 12 D10 – – I/O General-purpose input/output 159
EPWM8A 1 O Enhanced PWM8 output A (HRPWM-capable)
GPIO160 0, 4, 8, 12 B9 – – I/O General-purpose input/output 160
EPWM8B 1 O Enhanced PWM8 output B (HRPWM-capable)
GPIO161 0, 4, 8, 12 C9 – – I/O General-purpose input/output 161
EPWM9A 1 O Enhanced PWM9 output A
GPIO162 0, 4, 8, 12 D9 – – I/O General-purpose input/output 162
EPWM9B 1 O Enhanced PWM9 output B
GPIO163 0, 4, 8, 12 A8 – – I/O General-purpose input/output 163
EPWM10A 1 O Enhanced PWM10 output A
GPIO164 0, 4, 8, 12 B8 – – I/O General-purpose input/output 164
EPWM10B 1 O Enhanced PWM10 output B
GPIO165 0, 4, 8, 12 C5 – – I/O General-purpose input/output 165
EPWM11A 1 O Enhanced PWM11 output A
GPIO166 0, 4, 8, 12 D5 – – I/O General-purpose input/output 166
EPWM11B 1 O Enhanced PWM11 output B
GPIO167 0, 4, 8, 12 C4 – – I/O General-purpose input/output 167
EPWM12A 1 O Enhanced PWM12 output A
GPIO168 0, 4, 8, 12 D4 – – I/O General-purpose input/output 168
EPWM12B 1 O Enhanced PWM12 output B
RESET
XRS F19 124 69 I/OD
Device Reset (in) and Watchdog Reset (out). The devices
have a built-in power-on reset (POR) circuit. During a
power-on condition, this pin is driven low by the device.
An external circuit may also drive this pin to assert a
device reset. This pin is also driven low by the MCU when
a watchdog reset or NMI watchdog reset occurs. During
watchdog reset, the XRS pin is driven low for the
watchdog reset duration of 512 OSCCLK cycles. A
resistor with a value from 2.2 kΩ to 10 kΩ should be
placed between XRS and VDDIO. If a capacitor is placed
between XRS and VSS for noise filtering, it should be
100 nF or smaller. These values will allow the watchdog
to properly drive the XRS pin to VOL within 512 OSCCLK
cycles when the watchdog reset is asserted. The output
buffer of this pin is an open drain with an internal pullup. If
this pin is driven by an external device, it should be done
using an open-drain device.
CLOCKS
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TEXAS INSTRUMENTS
TERMINAL
I/O/Z(1) DESCRIPTION
NAME MUX
POSITION
ZWT
BALL
NO.
PTP
PIN
NO.
PZP
PIN
NO.
X1 G19 123 68 I
On-chip crystal-oscillator input. To use this oscillator, a
quartz crystal must be connected across X1 and X2. If
this pin is not used, it must be tied to GND.
This pin can also be used to feed a single-ended 3.3-V
level clock. In this case, X2 is a No Connect (NC).
X2 J19 121 66 O
On-chip crystal-oscillator output. A quartz crystal may be
connected across X1 and X2. If X2 is not used, it must be
left unconnected.
NO CONNECT
NC H4 – – No connect. BGA ball is electrically open and not
connected to the die.
JTAG
TCK V15 81 50 I JTAG test clock with internal pullup (see Section 7.6)
TDI W13 77 46 I
JTAG test data input (TDI) with internal pullup. TDI is
clocked into the selected register (instruction or data) on a
rising edge of TCK.
TDO W15 78 47 O/Z
JTAG scan out, test data output (TDO). The contents of
the selected register (instruction or data) are shifted out of
TDO on the falling edge of TCK.(3)
TMS W14 80 49 I
JTAG test-mode select (TMS) with internal pullup. This
serial control input is clocked into the TAP controller on
the rising edge of TCK.
TRST V14 79 48 I
JTAG test reset with internal pulldown. TRST, when
driven high, gives the scan system control of the
operations of the device. If this signal is driven low, the
device operates in its functional mode, and the test reset
signals are ignored. NOTE: TRST must be maintained low
at all times during normal device operation. An external
pulldown resistor is required on this pin. The value of this
resistor should be based on drive strength of the
debugger pods applicable to the design. A 2.2-kΩ or
smaller resistor generally offers adequate protection. The
value of the resistor is application-specific. TI
recommends that each target board be validated for
proper operation of the debugger and the application. This
pin has an internal 50-ns (nominal) glitch filter.
INTERNAL VOLTAGE REGULATOR CONTROL
VREGENZ J18 119 64 I
Internal voltage regulator enable with internal pulldown.
The internal VREG is not supported and must be
disabled. Connect VREGENZ to VDDIO.
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TERMINAL
I/O/Z(1) DESCRIPTION
NAME MUX
POSITION
ZWT
BALL
NO.
PTP
PIN
NO.
PZP
PIN
NO.
VDD
E9 16 16
1.2-V digital logic power pins. TI recommends placing a
decoupling capacitor near each VDD pin with a minimum
total capacitance of approximately 20 uF. The exact value
of the decoupling capacitance should be determined by
your system voltage regulation solution.
E11 21 39
F9 61 45
F11 76 63
G14 117 71
G15 126 78
J14 137 84
J15 153 89
K5 158 95
K6 169 –
P10 – –
P13 – –
R10 – –
R13 – –
VDD3VFL
R11 72 41 3.3-V Flash power pin. Place a minimum 0.1-µF
decoupling capacitor on each pin.
R12 – –
VDDA
P6 36 18 3.3-V analog power pins. Place a minimum 2.2-µF
decoupling capacitor to VSSA on each pin.
R6 54 38
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TEXAS INSTRUMENTS
TERMINAL
I/O/Z(1) DESCRIPTION
NAME MUX
POSITION
ZWT
BALL
NO.
PTP
PIN
NO.
PZP
PIN
NO.
VDDIO
A9 3 2
3.3-V digital I/O power pins. Place a minimum 0.1-µF
decoupling capacitor on each pin. The exact value of the
decoupling capacitance should be determined by your
system voltage regulation solution.
A18 11 10
B1 15 15
E7 20 40
E10 26 44
E13 62 55
E16 68 62
F4 75 72
F7 82 79
F10 88 83
F13 91 90
F16 99 94
G4 106 –
G5 114 –
G6 116 –
H5 127 –
H6 138 –
L14 147 –
L15 152 –
M1 159 –
M5 168 –
M6 – –
N14 – –
N15 – –
P9 – –
R9 – –
V19 – –
W8 – –
VDDOSC
H16 120 65 Power pins for the 3.3-V on-chip crystal oscillator (X1 and
X2) and the two zero-pin internal oscillators (INTOSC).
Place a 0.1-μF (minimum) decoupling capacitor on each
pin.
H17 125 70
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TEXAS INSTRUMENTS
TERMINAL
I/O/Z(1) DESCRIPTION
NAME MUX
POSITION
ZWT
BALL
NO.
PTP
PIN
NO.
PZP
PIN
NO.
VSS
A1
PWR
PAD
PWR
PAD
Device ground. For Quad Flatpacks (QFPs), the
PowerPAD on the bottom of the package must be
soldered to the ground plane of the PCB.
A10
A19
E5
E6
E8
E12
E14
E15
F5
F6
F8
F12
F14
F15
G16
G17
H8
H9
H10
H11
H12
H14
H15
J5
J6
J8
J9
J10
J11
J12
K8
K9
K10
K11
K12
K14
K15
L5
L6
L8
L9
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TEXAS INSTRUMENTS
TERMINAL
I/O/Z(1) DESCRIPTION
NAME MUX
POSITION
ZWT
BALL
NO.
PTP
PIN
NO.
PZP
PIN
NO.
VSS
L10
PWR
PAD
PWR
PAD
Device ground. For Quad Flatpacks (QFPs), the
PowerPAD on the bottom of the package must be
soldered to the ground plane of the PCB.
L11
L12
L18
M8
M9
M10
M11
M12
M14
M15
N1
N5
N6
P7
P8
P11
P12
P14
P15
R7
R8
R14
R15
W7
W19
VSSOSC
H18 122 67 Crystal oscillator (X1 and X2) ground pin. When using an
external crystal, do not connect this pin to the board
ground. Instead, connect it to the ground reference of the
external crystal oscillator circuit.
If an external crystal is not used, this pin may be
connected to the board ground.
H19 – –
VSSA
P1 34 17
Analog ground.
On the PZP package, pin 17 is double-bonded to VSSA
and VREFLOA. This pin must be connect to VSSA.
P5 52 35
R5 – 36
V7 – –
W1 – –
SPECIAL FUNCTIONS
ERRORSTS U19 92 – O Error status output. This pin has an internal pulldown.
TEST PINS
FLT1 W12 73 42 I/O Flash test pin 1. Reserved for TI. Must be left
unconnected.
FLT2 V13 74 43 I/O Flash test pin 2. Reserved for TI. Must be left
unconnected.
(1) I = Input, O = Output, OD = Open Drain, Z = High Impedance
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(2) High-Speed SPI-enabled GPIO mux option. This pin mux option is required when using the SPI in High-Speed Mode (HS_MODE = 1
in SPICCR). This mux option is still available when not using the SPI in High-Speed Mode (HS_MODE = 0 in SPICCR).
(3) This pin has output impedance that can be as low as 22 Ω. This output could have fast edges and ringing depending on the system
PCB characteristics. If this is a concern, the user should take precautions such as adding a 39Ω (10% tolerance) series termination
resistor or implement some other termination scheme. It is also recommended that a system-level signal integrity analysis be
performed with the provided IBIS models. The termination is not required if this pin is used for input function.
6.3 Pins With Internal Pullup and Pulldown
Some pins on the device have internal pullups or pulldowns. Table 6-1 lists the pull direction and when it is
active. The pullups on GPIO pins are disabled by default and can be enabled through software. In order to avoid
any floating unbonded inputs, the Boot ROM will enable internal pullups on GPIO pins that are not bonded out in
a particular package. Other pins noted in Table 6-1 with pullups and pulldowns are always on and cannot be
disabled.
Table 6-1. Pins With Internal Pullup and Pulldown
PIN RESET
( XRS = 0) DEVICE BOOT APPLICATION SOFTWARE
GPIOx Pullup disabled Pullup disabled(1) Pullup enable is application-
defined
TRST Pulldown active
TCK Pullup active
TMS Pullup active
TDI Pullup active
XRS Pullup active
VREGENZ Pulldown active
ERRORSTS Pulldown active
Other pins No pullup or pulldown present
(1) Pins not bonded out in a given package will have the internal pullups enabled by the Boot ROM.
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TEXAS INSTRUMENTS
6.4 Pin Multiplexing
6.4.1 GPIO Muxed Pins
Table 6-2 shows the GPIO muxed pins. The default for each pin is the GPIO function, secondary functions can
be selected by setting both the GPyGMUXn.GPIOz and GPyMUXn.GPIOz register bits. The GPyGMUXn
register should be configured prior to the GPyMUXn to avoid transient pulses on GPIO's from alternate mux
selections. Columns not shown and blank cells are reserved GPIO Mux settings.
Table 6-2. GPIO Muxed Pins
GPIO Mux Selection(1) (2)
GPIO Index 0, 4, 8, 12 1 2 3 5 6 7 15
GPyGMUXn.
GPIOz =
00b, 01b,
10b, 11b 00b 01b 11b
GPyMUXn.
GPIOz = 00b 01b 10b 11b 01b 10b 11b 11b
GPIO0 EPWM1A (O) SDAA (I/OD)
GPIO1 EPWM1B (O) MFSRB (I/O) SCLA (I/OD)
GPIO2 EPWM2A (O) OUTPUTXBAR1 (O) SDAB (I/OD)
GPIO3 EPWM2B (O) OUTPUTXBAR2 (O) MCLKRB (I/O) OUTPUTXBAR2 (O) SCLB (I/OD)
GPIO4 EPWM3A (O) OUTPUTXBAR3 (O) CANTXA (O)
GPIO5 EPWM3B (O) MFSRA (I/O) OUTPUTXBAR3 (O) CANRXA (I)
GPIO6 EPWM4A (O) OUTPUTXBAR4 (O) EXTSYNCOUT (O) EQEP3A (I) CANTXB (O)
GPIO7 EPWM4B (O) MCLKRA (I/O) OUTPUTXBAR5 (O) EQEP3B (I) CANRXB (I)
GPIO8 EPWM5A (O) CANTXB (O) ADCSOCAO (O) EQEP3S (I/O) SCITXDA (O)
GPIO9 EPWM5B (O) SCITXDB (O) OUTPUTXBAR6 (O) EQEP3I (I/O) SCIRXDA (I)
GPIO10 EPWM6A (O) CANRXB (I) ADCSOCBO (O) EQEP1A (I) SCITXDB (O) UPP-WAIT (I/O)
GPIO11 EPWM6B (O) SCIRXDB (I) OUTPUTXBAR7 (O) EQEP1B (I) SCIRXDB (I) UPP-START (I/O)
GPIO12 EPWM7A (O) CANTXB (O) MDXB (O) EQEP1S (I/O) SCITXDC (O) UPP-ENA (I/O)
GPIO13 EPWM7B (O) CANRXB (I) MDRB (I) EQEP1I (I/O) SCIRXDC (I) UPP-D7 (I/O)
GPIO14 EPWM8A (O) SCITXDB (O) MCLKXB (I/O) OUTPUTXBAR3 (O) UPP-D6 (I/O)
GPIO15 EPWM8B (O) SCIRXDB (I) MFSXB (I/O) OUTPUTXBAR4 (O) UPP-D5 (I/O)
GPIO16 SPISIMOA (I/O) CANTXB (O) OUTPUTXBAR7 (O) EPWM9A (O) SD1_D1 (I) UPP-D4 (I/O)
GPIO17 SPISOMIA (I/O) CANRXB (I) OUTPUTXBAR8 (O) EPWM9B (O) SD1_C1 (I) UPP-D3 (I/O)
GPIO18 SPICLKA (I/O) SCITXDB (O) CANRXA (I) EPWM10A (O) SD1_D2 (I) UPP-D2 (I/O)
GPIO19 SPISTEA (I/O) SCIRXDB (I) CANTXA (O) EPWM10B (O) SD1_C2 (I) UPP-D1 (I/O)
GPIO20 EQEP1A (I) MDXA (O) CANTXB (O) EPWM11A (O) SD1_D3 (I) UPP-D0 (I/O)
GPIO21 EQEP1B (I) MDRA (I) CANRXB (I) EPWM11B (O) SD1_C3 (I) UPP-CLK (I/O)
GPIO22 EQEP1S (I/O) MCLKXA (I/O) SCITXDB (O) EPWM12A (O) SPICLKB (I/O) SD1_D4 (I)
GPIO23 EQEP1I (I/O) MFSXA (I/O) SCIRXDB (I) EPWM12B (O) SPISTEB (I/O) SD1_C4 (I)
GPIO24 OUTPUTXBAR1 (O) EQEP2A (I) MDXB (O) SPISIMOB (I/O) SD2_D1 (I)
GPIO25 OUTPUTXBAR2 (O) EQEP2B (I) MDRB (I) SPISOMIB (I/O) SD2_C1 (I)
GPIO26 OUTPUTXBAR3 (O) EQEP2I (I/O) MCLKXB (I/O) OUTPUTXBAR3 (O) SPICLKB (I/O) SD2_D2 (I)
GPIO27 OUTPUTXBAR4 (O) EQEP2S (I/O) MFSXB (I/O) OUTPUTXBAR4 (O) SPISTEB (I/O) SD2_C2 (I)
GPIO28 SCIRXDA (I) EM1CS4 (O) OUTPUTXBAR5 (O) EQEP3A (I) SD2_D3 (I)
GPIO29 SCITXDA (O) EM1SDCKE (O) OUTPUTXBAR6 (O) EQEP3B (I) SD2_C3 (I)
GPIO30 CANRXA (I) EM1CLK (O) OUTPUTXBAR7 (O) EQEP3S (I/O) SD2_D4 (I)
GPIO31 CANTXA (O) EM1WE (O) OUTPUTXBAR8 (O) EQEP3I (I/O) SD2_C4 (I)
GPIO32 SDAA (I/OD) EM1CS0 (O)
GPIO33 SCLA (I/OD) EM1RNW (O)
GPIO34 OUTPUTXBAR1 (O) EM1CS2 (O) SDAB (I/OD)
GPIO35 SCIRXDA (I) EM1CS3 (O) SCLB (I/OD)
GPIO36 SCITXDA (O) EM1WAIT (I) CANRXA (I)
GPIO37 OUTPUTXBAR2 (O) EM1OE (O) CANTXA (O)
GPIO38 EM1A0 (O) SCITXDC (O) CANTXB (O)
GPIO39 EM1A1 (O) SCIRXDC (I) CANRXB (I)
GPIO40 EM1A2 (O) SDAB (I/OD)
GPIO41 EM1A3 (O) SCLB (I/OD)
GPIO42 SDAA (I/OD) SCITXDA (O)
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TEXAS INSTRUMENTS
Table 6-2. GPIO Muxed Pins (continued)
GPIO Mux Selection(1) (2)
GPIO Index 0, 4, 8, 12 1 2 3 5 6 7 15
GPyGMUXn.
GPIOz =
00b, 01b,
10b, 11b 00b 01b 11b
GPyMUXn.
GPIOz = 00b 01b 10b 11b 01b 10b 11b 11b
GPIO43 SCLA (I/OD) SCIRXDA (I)
GPIO44 EM1A4 (O)
GPIO45 EM1A5 (O)
GPIO46 EM1A6 (O) SCIRXDD (I)
GPIO47 EM1A7 (O) SCITXDD (O)
GPIO48 OUTPUTXBAR3 (O) EM1A8 (O) SCITXDA (O) SD1_D1 (I)
GPIO49 OUTPUTXBAR4 (O) EM1A9 (O) SCIRXDA (I) SD1_C1 (I)
GPIO50 EQEP1A (I) EM1A10 (O) SPISIMOC (I/O) SD1_D2 (I)
GPIO51 EQEP1B (I) EM1A11 (O) SPISOMIC (I/O) SD1_C2 (I)
GPIO52 EQEP1S (I/O) EM1A12 (O) SPICLKC (I/O) SD1_D3 (I)
GPIO53 EQEP1I (I/O) EM1D31 (I/O) EM2D15 (I/O) SPISTEC (I/O) SD1_C3 (I)
GPIO54 SPISIMOA (I/O) EM1D30 (I/O) EM2D14 (I/O) EQEP2A (I) SCITXDB (O) SD1_D4 (I)
GPIO55 SPISOMIA (I/O) EM1D29 (I/O) EM2D13 (I/O) EQEP2B (I) SCIRXDB (I) SD1_C4 (I)
GPIO56 SPICLKA (I/O) EM1D28 (I/O) EM2D12 (I/O) EQEP2S (I/O) SCITXDC (O) SD2_D1 (I)
GPIO57 SPISTEA (I/O) EM1D27 (I/O) EM2D11 (I/O) EQEP2I (I/O) SCIRXDC (I) SD2_C1 (I)
GPIO58 MCLKRA (I/O) EM1D26 (I/O) EM2D10 (I/O) OUTPUTXBAR1 (O) SPICLKB (I/O) SD2_D2 (I) SPISIMOA(3) (I/O)
GPIO59 MFSRA (I/O) EM1D25 (I/O) EM2D9 (I/O) OUTPUTXBAR2 (O) SPISTEB (I/O) SD2_C2 (I) SPISOMIA(3) (I/O)
GPIO60 MCLKRB (I/O) EM1D24 (I/O) EM2D8 (I/O) OUTPUTXBAR3 (O) SPISIMOB (I/O) SD2_D3 (I) SPICLKA(3) (I/O)
GPIO61 MFSRB (I/O) EM1D23 (I/O) EM2D7 (I/O) OUTPUTXBAR4 (O) SPISOMIB (I/O) SD2_C3 (I) SPISTEA (3) (I/O)
GPIO62 SCIRXDC (I) EM1D22 (I/O) EM2D6 (I/O) EQEP3A (I) CANRXA (I) SD2_D4 (I)
GPIO63 SCITXDC (O) EM1D21 (I/O) EM2D5 (I/O) EQEP3B (I) CANTXA (O) SD2_C4 (I) SPISIMOB(3) (I/O)
GPIO64 EM1D20 (I/O) EM2D4 (I/O) EQEP3S (I/O) SCIRXDA (I) SPISOMIB(3) (I/O)
GPIO65 EM1D19 (I/O) EM2D3 (I/O) EQEP3I (I/O) SCITXDA (O) SPICLKB(3) (I/O)
GPIO66 EM1D18 (I/O) EM2D2 (I/O) SDAB (I/OD) SPISTEB (3) (I/O)
GPIO67 EM1D17 (I/O) EM2D1 (I/O)
GPIO68 EM1D16 (I/O) EM2D0 (I/O)
GPIO69 EM1D15 (I/O) SCLB (I/OD) SPISIMOC(3) (I/O)
GPIO70 EM1D14 (I/O) CANRXA (I) SCITXDB (O) SPISOMIC(3) (I/O)
GPIO71 EM1D13 (I/O) CANTXA (O) SCIRXDB (I) SPICLKC(3) (I/O)
GPIO72 EM1D12 (I/O) CANTXB (O) SCITXDC (O) SPISTEC (3) (I/O)
GPIO73 EM1D11 (I/O) XCLKOUT (O) CANRXB (I) SCIRXDC (I)
GPIO74 EM1D10 (I/O)
GPIO75 EM1D9 (I/O)
GPIO76 EM1D8 (I/O) SCITXDD (O)
GPIO77 EM1D7 (I/O) SCIRXDD (I)
GPIO78 EM1D6 (I/O) EQEP2A (I)
GPIO79 EM1D5 (I/O) EQEP2B (I)
GPIO80 EM1D4 (I/O) EQEP2S (I/O)
GPIO81 EM1D3 (I/O) EQEP2I (I/O)
GPIO82 EM1D2 (I/O)
GPIO83 EM1D1 (I/O)
GPIO84 SCITXDA (O) MDXB (O) MDXA (O)
GPIO85 EM1D0 (I/O) SCIRXDA (I) MDRB (I) MDRA (I)
GPIO86 EM1A13 (O) EM1CAS (O) SCITXDB (O) MCLKXB (I/O) MCLKXA (I/O)
GPIO87 EM1A14 (O) EM1RAS (O) SCIRXDB (I) MFSXB (I/O) MFSXA (I/O)
GPIO88 EM1A15 (O) EM1DQM0 (O)
GPIO89 EM1A16 (O) EM1DQM1 (O) SCITXDC (O)
GPIO90 EM1A17 (O) EM1DQM2 (O) SCIRXDC (I)
GPIO91 EM1A18 (O) EM1DQM3 (O) SDAA (I/OD)
GPIO92 EM1A19 (O) EM1BA1 (O) SCLA (I/OD)
GPIO93 EM1BA0 (O) SCITXDD (O)
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Table 6-2. GPIO Muxed Pins (continued)
GPIO Mux Selection(1) (2)
GPIO Index 0, 4, 8, 12 1 2 3 5 6 7 15
GPyGMUXn.
GPIOz =
00b, 01b,
10b, 11b 00b 01b 11b
GPyMUXn.
GPIOz = 00b 01b 10b 11b 01b 10b 11b 11b
GPIO94 SCIRXDD (I)
GPIO95
GPIO96 EM2DQM1 (O) EQEP1A (I)
GPIO97 EM2DQM0 (O) EQEP1B (I)
GPIO98 EM2A0 (O) EQEP1S (I/O)
GPIO99 EM2A1 (O) EQEP1I (I/O)
GPIO100 EM2A2 (O) EQEP2A (I) SPISIMOC (I/O)
GPIO101 EM2A3 (O) EQEP2B (I) SPISOMIC (I/O)
GPIO102 EM2A4 (O) EQEP2S (I/O) SPICLKC (I/O)
GPIO103 EM2A5 (O) EQEP2I (I/O) SPISTEC (I/O)
GPIO104 SDAA (I/OD) EM2A6 (O) EQEP3A (I) SCITXDD (O)
GPIO105 SCLA (I/OD) EM2A7 (O) EQEP3B (I) SCIRXDD (I)
GPIO106 EM2A8 (O) EQEP3S (I/O) SCITXDC (O)
GPIO107 EM2A9 (O) EQEP3I (I/O) SCIRXDC (I)
GPIO108 EM2A10 (O)
GPIO109 EM2A11 (O)
GPIO110 EM2WAIT (I)
GPIO111 EM2BA0 (O)
GPIO112 EM2BA1 (O)
GPIO113 EM2CAS (O)
GPIO114 EM2RAS (O)
GPIO115 EM2CS0 (O)
GPIO116 EM2CS2 (O)
GPIO117 EM2SDCKE (O)
GPIO118 EM2CLK (O)
GPIO119 EM2RNW (O)
GPIO120 EM2WE (O) USB0PFLT
GPIO121 EM2OE (O) USB0EPEN
GPIO122 SPISIMOC (I/O) SD1_D1 (I)
GPIO123 SPISOMIC (I/O) SD1_C1 (I)
GPIO124 SPICLKC (I/O) SD1_D2 (I)
GPIO125 SPISTEC (I/O) SD1_C2 (I)
GPIO126 SD1_D3 (I)
GPIO127 SD1_C3 (I)
GPIO128 SD1_D4 (I)
GPIO129 SD1_C4 (I)
GPIO130 SD2_D1 (I)
GPIO131 SD2_C1 (I)
GPIO132 SD2_D2 (I)
GPIO133/
AUXCLKIN SD2_C2 (I)
GPIO134 SD2_D3 (I)
GPIO135 SCITXDA (O) SD2_C3 (I)
GPIO136 SCIRXDA (I) SD2_D4 (I)
GPIO137 SCITXDB (O) SD2_C4 (I)
GPIO138 SCIRXDB (I)
GPIO139 SCIRXDC (I)
GPIO140 SCITXDC (O)
GPIO141 SCIRXDD (I)
GPIO142 SCITXDD (O)
GPIO143
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Table 6-2. GPIO Muxed Pins (continued)
GPIO Mux Selection(1) (2)
GPIO Index 0, 4, 8, 12 1 2 3 5 6 7 15
GPyGMUXn.
GPIOz =
00b, 01b,
10b, 11b 00b 01b 11b
GPyMUXn.
GPIOz = 00b 01b 10b 11b 01b 10b 11b 11b
GPIO144
GPIO145 EPWM1A (O)
GPIO146 EPWM1B (O)
GPIO147 EPWM2A (O)
GPIO148 EPWM2B (O)
GPIO149 EPWM3A (O)
GPIO150 EPWM3B (O)
GPIO151 EPWM4A (O)
GPIO152 EPWM4B (O)
GPIO153 EPWM5A (O)
GPIO154 EPWM5B (O)
GPIO155 EPWM6A (O)
GPIO156 EPWM6B (O)
GPIO157 EPWM7A (O)
GPIO158 EPWM7B (O)
GPIO159 EPWM8A (O)
GPIO160 EPWM8B (O)
GPIO161 EPWM9A (O)
GPIO162 EPWM9B (O)
GPIO163 EPWM10A (O)
GPIO164 EPWM10B (O)
GPIO165 EPWM11A (O)
GPIO166 EPWM11B (O)
GPIO167 EPWM12A (O)
GPIO168 EPWM12B (O)
(1) I = Input, O = Output, OD = Open Drain
(2) GPIO Index settings of 9, 10, 11, 13, and 14 are reserved.
(3) High-Speed SPI-enabled GPIO mux option. This pin mux option is required when using the SPI in High-Speed Mode (HS_MODE = 1
in SPICCR). This mux option is still available when not using the SPI in High-Speed Mode (HS_MODE = 0 in SPICCR).
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6.4.2 Input X-BAR
The Input X-BAR is used to route any GPIO input to the ADC, eCAP, and ePWM peripherals as well as to
external interrupts (XINT) (see Figure 6-7). Table 6-3 shows the input X-BAR destinations. For details on
configuring the Input X-BAR, see the Crossbar (X-BAR) chapter of the TMS320F2837xS Microcontrollers
Technical Reference Manual .
Figure 6-7. Input X-BAR
Table 6-3. Input X-BAR Destinations
INPUT DESTINATIONS
INPUT1 EPWM[TZ1,TRIP1], EPWM X-BAR, Output X-BAR
INPUT2 EPWM[TZ2,TRIP2], EPWM X-BAR, Output X-BAR
INPUT3 EPWM[TZ3,TRIP3], EPWM X-BAR, Output X-BAR
INPUT4 XINT1, EPWM X-BAR, Output X-BAR
INPUT5 XINT2, ADCEXTSOC, EXTSYNCIN1, EPWM X-BAR, Output X-BAR
INPUT6 XINT3, EPWM[TRIP6], EXTSYNCIN2, EPWM X-BAR, Output X-BAR
INPUT7 ECAP1
INPUT8 ECAP2
INPUT9 ECAP3
INPUT10 ECAP4
INPUT11 ECAP5
INPUT12 ECAP6
INPUT13 XINT4
INPUT14 XINT5
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6.4.3 Output X-BAR and ePWM X-BAR
The Output X-BAR has eight outputs which can be selected on the GPIO mux as OUTPUTXBARx. The ePWM
X-BAR has eight outputs which are connected to the TRIPx inputs of the ePWM. The sources for both the
Output X-BAR and ePWM X-BAR are shown in Figure 6-8. For details on the Output X-BAR and ePWM X-BAR,
see the Crossbar (X-BAR) chapter of the TMS320F2837xS Microcontrollers Technical Reference Manual .
CMPSSx
ePWM and eCAP
Sync
ADCSOCAO
Select Ckt
ADCSOCBO
Select Ckt
eCAPx
ADCx
Input X-Bar
CTRIPOUTH
CTRIPOUTL
CTRIPH
CTRIPL
EXTSYNCOUT
ADCSOCAO
ADCSOCBO
ECAPxOUT
EVT1
INPUT1
INPUT2
INPUT3
INPUT4
INPUT5
INPUT6
FLT1.COMPH
FLT1.COMPL
FLT4.COMPH
FLT4.COMPL
GPIO
Mux
OUTPUT1
OUTPUT2
OUTPUT3
OUTPUT4
OUTPUT5
OUTPUT6
OUTPUT7
OUTPUT8
Output
X-BAR
X-BAR Flags
(shared)
All
ePWM
Modules
TRIP4
TRIP5
TRIP7
TRIP8
TRIP9
TRIP10
TRIP11
TRIP12
ePWM
X-BAR
SDFMx
(Output X-BAR only)
(ePWM X-BAR only)
EVT2
EVT3
EVT4
OTHER DESTINATIONS
(see Input X-BAR)
Figure 6-8. Output X-BAR and ePWM X-BAR
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6.4.4 USB Pin Muxing
Table 6-4 shows assignment of the alternate USB function mapping. These can be configured with the
GPBAMSEL register.
Table 6-4. Alternate USB Function
GPIO GPBAMSEL SETTING USB FUNCTION
GPIO42 GPBAMSEL[10] = 1b USB0DM
GPIO43 GPBAMSEL[11] = 1b USB0DP
6.4.5 High-Speed SPI Pin Muxing
The SPI module on this device has a high-speed mode. To achieve the highest possible speed, a special GPIO
configuration is used on a single GPIO mux option for each SPI. These GPIOs may also be used by the SPI
when not in high-speed mode (HS_MODE = 0).
To select the mux options that enable the SPI high-speed mode, configure the GPyGMUX and GPyMUX
registers as shown in Table 6-5.
Table 6-5. GPIO Configuration for High-Speed SPI
GPIO SPI SIGNAL MUX CONFIGURATION
SPIA
GPIO58 SPISIMOA GPBGMUX2[21:20]=11b GPBMUX2[21:20]=11b
GPIO59 SPISOMIA GPBGMUX2[23:22]=11b GPBMUX2[23:22]=11b
GPIO60 SPICLKA GPBGMUX2[25:24]=11b GPBMUX2[25:24]=11b
GPIO61 SPISTEA GPBGMUX2[27:26]=11b GPBMUX2[27:26]=11b
SPIB
GPIO63 SPISIMOB GPBGMUX2[31:30]=11b GPBMUX2[31:30]=11b
GPIO64 SPISOMIB GPCGMUX1[1:0]=11b GPCMUX1[1:0]=11b
GPIO65 SPICLKB GPCGMUX1[3:2]=11b GPCMUX1[3:2]=11b
GPIO66 SPISTEB GPCGMUX1[5:4]=11b GPCMUX1[5:4]=11b
SPIC
GPIO69 SPISIMOC GPCGMUX1[11:10]=11b GPCMUX1[11:10]=11b
GPIO70 SPISOMIC GPCGMUX1[13:12]=11b GPCMUX1[13:12]=11b
GPIO71 SPICLKC GPCGMUX1[15:14]=11b GPCMUX1[15:14]=11b
GPIO72 SPISTEC GPCGMUX1[17:16]=11b GPCMUX1[17:16]=11b
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6.5 Connections for Unused Pins
For applications that do not need to use all functions of the device, Table 6-6 lists acceptable conditioning for any
unused pins. When multiple options are listed in Table 6-6, any are acceptable. Pins not listed in Table 6-6 must
be connected according to Section 6.2.1.
Table 6-6. Connections for Unused Pins
SIGNAL NAME ACCEPTABLE PRACTICE
Analog
VREFHIx Tie to VDDA
VREFLOx Tie to VSSA
ADCINx • No Connect
• Tie to VSSA
Digital
GPIOx
• No connection (input mode with internal pullup enabled)
• No connection (output mode with internal pullup disabled)
• Pullup or pulldown resistor (any value resistor, input mode, and with internal pullup disabled)
X1 Tie to VSS
X2 No Connect
TCK • No Connect
• Pullup resistor
TDI • No Connect
• Pullup resistor
TDO No Connect
TMS No Connect
TRST Pulldown resistor (2.2 kΩ or smaller)
VREGENZ Tie to VDDIO. VREG is not supported.
ERRORSTS No Connect
FLT1 No Connect
FLT2 No Connect
Power and Ground
VDD All VDD pins must be connected per Section 6.2.1.
VDDA If a dedicated analog supply is not used, tie to VDDIO.
VDDIO All VDDIO pins must be connected per Section 6.2.1.
VDD3VFL Must be tied to VDDIO
VDDOSC Must be tied to VDDIO
VSS All VSS pins must be connected to board ground.
VSSA If a dedicated analog ground is not used, tie to VSS.
VSSOSC If an external crystal is not used, this pin may be connected to the board ground.
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7 Specifications
7.1 Absolute Maximum Ratings
over operating free-air temperature range (unless otherwise noted)
MIN MAX(1) (2) UNIT
Supply voltage
VDDIO with respect to VSS –0.3 4.6
V
VDD3VFL with respect to VSS –0.3 4.6
VDDOSC with respect to VSS –0.3 4.6
VDD with respect to VSS –0.3 1.5
Analog voltage VDDA with respect to VSSA –0.3 4.6 V
Input voltage VIN (3.3 V) –0.3 4.6 V
Output voltage VO–0.3 4.6 V
Input clamp current
Digital/analog input (per pin), IIK
(VIN < VSS/VSSA or VIN > VDDIO/VDDA)(3) –20 20
mA
Total for all inputs, IIKTOTAL
(VIN < VSS/VSSA or VIN > VDDIO/VDDA)–20 20
Output current Digital output (per pin), IOUT –20 20 mA
Free-Air temperature TA–40 125 °C
Operating junction temperature TJ–40 150 °C
Storage temperature(4) Tstg –65 150 °C
(1) Stresses beyond those listed under absolute maximum ratings may cause permanent damage to the device. These are stress ratings
only, and functional operation of the device at these or any other conditions beyond those indicated under Section 7.4 is not implied.
Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
(2) All voltage values are with respect to VSS, unless otherwise noted.
(3) Continuous clamp current per pin is ±2 mA. Do not operate in this condition continuously as VDDIO/VDDA voltage may internally rise and
impact other electrical specifications.
(4) Long-term high-temperature storage or extended use at maximum temperature conditions may result in a reduction of overall device
life. For additional information, see Semiconductor and IC Package Thermal Metrics.
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7.2 ESD Ratings – Commercial
VALUE UNIT
TMS320F28379S, TMS320F28376S, TMS320F28375S, TMS320F28375S-Q1, and TMS320F23874S in 337-ball ZWT package
V(ESD) Electrostatic discharge (ESD)
Human-body model (HBM), per ANSI/ESDA/JEDEC JS-001(1) ±2000
V
Charged-device model (CDM), per JEDEC specification JESD22-
C101 or ANSI/ESDA/JEDEC JS-002(2) ±500
TMS320F28379S, TMS320F28378S, TMS320F28376S, TMS320F28375S, TMS320F28375S-Q1, and
TMS320F23874S in 176-pin PTP package
V(ESD) Electrostatic discharge (ESD)
Human-body model (HBM), per ANSI/ESDA/JEDEC JS-001(1) ±2000
V
Charged-device model (CDM), per JEDEC specification JESD22-
C101 or ANSI/ESDA/JEDEC JS-002(2) ±500
TMS320F28379S, TMS320F28378S, TMS320F28376S, and TMS320F23874S in 100-pin PZP package
V(ESD) Electrostatic discharge (ESD)
Human-body model (HBM), per ANSI/ESDA/JEDEC JS-001(1) ±2000
V
Charged-device model (CDM), per JEDEC specification JESD22-
C101 or ANSI/ESDA/JEDEC JS-002(2) ±500
(1) JEDEC document JEP155 states that 500-V HBM allows safe manufacturing with a standard ESD control process.
(2) JEDEC document JEP157 states that 250-V CDM allows safe manufacturing with a standard ESD control process.
7.3 ESD Ratings – Automotive
VALUE UNIT
TMS320F28377S and TMS320F28377S-Q1 in 337-ball ZWT package
V(ESD) Electrostatic discharge
Human body model (HBM), per
AEC Q100-002(1) All pins ±2000
VCharged device model (CDM),
per AEC Q100-011
All pins ±500
Corner balls on 337-ball ZWT:
A1, A19, W1, W19
±750
TMS320F28377S and TMS320F28377S-Q1 in 176-pin PTP package
V(ESD) Electrostatic discharge
Human body model (HBM), per
AEC Q100-002(1) All pins ±2000
VCharged device model (CDM),
per AEC Q100-011
All pins ±500
Corner pins on 176-pin PTP:
1, 44, 45, 88, 89, 132, 133, 176
±750
TMS320F28377S and TMS320F28377S-Q1 and TMS320F28375S in 100-pin PZP package
V(ESD) Electrostatic discharge
Human body model (HBM), per
AEC Q100-002(1) All pins ±2000
VCharged device model (CDM),
per AEC Q100-011
All pins ±500
Corner pins on 100-pin PZP:
1, 25, 26, 50, 51, 75, 76, 100
±750
(1) AEC Q100-002 indicates HBM stressing is done in accordance with the ANSI/ESDA/JEDEC JS-001 specification.
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7.4 Recommended Operating Conditions
MIN NOM MAX UNIT
Device supply voltage, I/O, VDDIO (1) 3.14 3.3 3.47 V
Device supply voltage, VDD 1.14 1.2 1.26 V
Supply ground, VSS 0 V
Analog supply voltage, VDDA 3.14 3.3 3.47 V
Analog ground, VSSA 0 V
Junction temperature, TJ
T version –40 105
°C
S version(2) –40 125
Q version (AEC Q100 qualification)(2) –40 150
Free-Air temperature, TAQ version (AEC Q100 qualification) –40 125 °C
(1) VDDIO, VDD3VFL, and VDDOSC should be maintained within 0.3 V of each other.
(2) Operation above TJ = 105°C for extended duration will reduce the lifetime of the device. See Calculating Useful Lifetimes of Embedded
Processors for more information.
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7.5 Power Consumption Summary
Current values listed in this section are representative for the test conditions given and not the absolute
maximum possible. The actual device currents in an application will vary with application code and pin
configurations. Section 7.5.1 shows the device current consumption at 200-MHz SYSCLK.
7.5.1 Device Current Consumption at 200-MHz SYSCLK
MODE TEST CONDITIONS IDD IDDIO (1) IDDA IDD3VFL
TYP(3) MAX(2) TYP(3) MAX(2) TYP(3) MAX(2) TYP(3) MAX(2)
Operational
• Code is running out of RAM.(4)
• All I/O pins are left unconnected.
• Peripherals not active have their
clocks disabled.
• FLASH is read and in active state.
• XCLKOUT is enabled at SYSCLK/4.
245 mA 400 mA 30 mA 13 mA 20 mA 33 mA 40 mA
IDLE
• CPU1 is in IDLE mode.
• Flash is powered down.
• XCLKOUT is turned off.
80 mA 215 mA 3 mA 10 mA 10 µA 150 µA 10 µA 150 µA
STANDBY
• CPU1 is in STANDBY mode.
• Flash is powered down.
• XCLKOUT is turned off.
30 mA 170 mA 3 mA 10 mA 5 µA 150 µA 10 µA 150 µA
HALT
• CPU1 watchdog is running.
• Flash is powered down.
• XCLKOUT is turned off.
1.5 mA 120 mA 750 µA 2 mA 5 µA 150 µA 10 µA 150 µA
HIBERNATE • CPU1.M0 and CPU1.M1 RAMs are
in low-power data retention mode. 300 µA 5 mA 750 µA 2 mA 5 µA 75 µA 1 µA 50 µA
Flash
Erase/Program(5)
• CPU1 is running from RAM.
• All I/O pins are left unconnected.
• Peripheral clocks are disabled.
• CPU1 is performing Flash Erase and
Programming.
• XCLKOUT is turned off.
154 mA 230 mA 3 mA 10 mA 10 µA 150 µA 45 mA 55 mA
(1) IDDIO current is dependent on the electrical loading on the I/O pins.
(2) MAX: Vmax, 125°C
(3) TYP: Vnom, 30°C
(4) The following is executed in a loop on CPU1:
• All of the communication peripherals are exercised in loop-back mode: CAN-A to CAN-B; SPI-A to SPI-C; SCI-A to SCI-D; I2C-A to
I2C-B; McBSP-A to McBSP-B; USB
• SDFM1 to SDFM4 active
• ePWM1 to ePWM12 generate 400-kHz PWM output on 24 pins
• CPU TIMERs active
• DMA does 32-bit burst transfers
• CLA1 does multiply-accumulate tasks
• All ADCs perform continuous conversion
• All DACs ramp voltage up/down at 150 kHz
• CMPSS1 to CMPSS8 active
• VCU does complex multiply/accumulate with parallel load
• TMU calculates a cosine
• FPU does multiply/accumulate with parallel load
(5) Brownout events during flash programming can corrupt flash data. Programming environments using alternate power sources (such as
a USB programmer) must be capable of supplying the rated current for the device and other system components with sufficient margin
to avoid supply brownout conditions.
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7.5.2 Current Consumption Graphs
Figure 7-1 and Figure 7-2 are a typical representation of the relationship between frequency and current
consumption/power on the device. The operational test from Section 7.5.1 was run across frequency at Vmax and
high temperature. Actual results will vary based on the system implementation and conditions.
0
0.05
0.1
0.15
0.2
0.25
0.3
0.35
0.4
0.45
0.5
10 20 30 40 50 60 70 80 90 100 110 120 130 140 150 160 170 180 190 200
VDD VDDIO VDDA VDD3VFL
Current (A)
SYSCLK (MHz)
Figure 7-1. Operational Current Versus Frequency
0
0.1
0.2
0.3
0.4
0.5
0.6
0.7
0.8
0.9
1
10 20 30 40 50 60 70 80 90 100 110 120 130 140 150 160 170 180 190 200
Power
Power (W)
SYSCLK (MHz)
Figure 7-2. Power Versus Frequency
TMS320F28379S, TMS320F28378S, TMS320F28377S, TMS320F28377S-Q1
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TEXAS INSTRUMENTS 0.09 0.08 0.07 99 9 ea c am a IDD Currem (A) P o w / / 45 -35 -25 -15 -5 5 15 25 35 45 55 as 75 Temperature [“C) 85 95 105 115 115
Leakage current will increase with operating temperature in a nonlinear manner. The difference in VDD current
between TYP and MAX conditions can be seen in Figure 7-3. The current consumption in HALT mode is
primarily leakage current as there is no active switching if the internal oscillator has been powered down.
Figure 7-3 shows the typical leakage current across temperature. The device was placed into HALT mode under
nominal voltage conditions.
Figure 7-3. IDD Leakage Current Versus Temperature
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7.5.3 Reducing Current Consumption
The F2837xS devices provide some methods to reduce the device current consumption:
• Any one of the four low-power modes—IDLE, STANDBY, HALT, and HIBERNATE—could be entered during
idle periods in the application.
• The flash module may be powered down if the code is run from RAM.
• Disable the pullups on pins that assume an output function.
• Each peripheral has an individual clock-enable bit (PCLKCRx). Reduced current consumption may be
achieved by turning off the clock to any peripheral that is not used in a given application. Table 7-1 indicates
the typical current reduction that may be achieved by disabling the clocks using the PCLKCRx register.
• To realize the lowest VDDA current consumption in a low-power mode, see the respective analog chapter of
the TMS320F2837xS Microcontrollers Technical Reference Manual to ensure each module is powered down
as well.
Table 7-1. Current on VDD Supply by Various
Peripherals (at 200 MHz)
PERIPHERAL
MODULE(1) (2)
IDD CURRENT
REDUCTION (mA)
ADC(3) 3.3
CAN 3.3
CLA 1.4
CMPSS(3) 1.4
CPUTIMER 0.3
DAC(3) 0.6
DMA 2.9
eCAP 0.6
EMIF1 2.9
EMIF2 2.6
ePWM1 to ePWM4(4) 4.5
ePWM5 to ePWM12(4) 1.7
HRPWM(4) 1.7
I2C 1.3
McBSP 1.6
SCI 0.9
SDFM 2
SPI 0.5
uPP 7.3
USB and AUXPLL at 60 MHz 23.8
(1) At Vmax and 125°C.
(2) All peripherals are disabled upon reset. Use the PCLKCRx
register to individually enable peripherals. For peripherals with
multiple instances, the current quoted is for a single module.
(3) This number represents the current drawn by the digital portion
of the ADC, CMPSS, and DAC modules.
(4) The ePWM is at /2 of SYSCLK.
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7.6 Electrical Characteristics
over recommended operating conditions (unless otherwise noted)
PARAMETER TEST
CONDITIONS MIN TYP MAX UNIT
VOH High-level output voltage IOH = IOH MIN VDDIO * 0.8 V
IOH = –100 μA VDDIO – 0.2
VOL Low-level output voltage IOL = IOL MAX 0.4 V
IOL = 100 µA 0.2
IOH High-level output source current for all output pins –4 mA
IOL Low-level output sink current for all output pins 4 mA
VIH High-level input voltage
(3.3 V)
GPIO0–GPIO7,
GPIO42–GPIO43,
GPIO46–GPIO47
VDDIO * 0.7 VDDIO + 0.3 V
All other pins 2.0 VDDIO + 0.3
VIL Low-level input voltage (3.3 V) VSS – 0.3 0.8 V
VHYSTERESIS Input hysteresis 150 mV
Ipulldown Input current Digital inputs with
pulldown(1) VDDIO = 3.3 V
VIN = VDDIO 120 µA
Ipullup Input current Digital inputs with pullup
enabled(1) VDDIO = 3.3 V
VIN = 0 V 150 µA
ILEAK Pin leakage
Digital Pullups disabled
0 V ≤ VIN ≤ VDDIO 2
µA
Analog (except
ADCINB0 or DACOUTx)
0 V ≤ VIN ≤ VDDA
2
ADCINB0 2 11(2)
DACOUTx 66
CIInput capacitance 2 pF
VDDIO-POR VDDIO power-on reset voltage 2.3 V
(1) See Table 6-1 for a list of pins with a pullup or pulldown.
(2) The MAX input leakage shown on ADCINB0 is at high temperature.
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7.7 Thermal Resistance Characteristics
7.7.1 ZWT Package
°C/W(1) AIR FLOW (lfm)(2)
RΘJC Junction-to-case thermal resistance 8.3 N/A
RΘJB Junction-to-board thermal resistance 11.6 N/A
RΘJA (High k PCB) Junction-to-free air thermal resistance 21.5 0
RΘJMA Junction-to-moving air thermal resistance
19.0 150
17.8 250
16.5 500
PsiJT Junction-to-package top
0.2 0
0.3 150
0.4 250
0.5 500
PsiJB Junction-to-board
11.4 0
11.3 150
11.2 250
11.0 500
(1) These values are based on a JEDEC-defined 2S2P system (with the exception of the Theta JC [RΘJC] value, which is based on a
JEDEC-defined 1S0P system) and will change based on environment as well as application. For more information, see these EIA/
JEDEC standards:
• JESD51-2, Integrated Circuits Thermal Test Method Environmental Conditions - Natural Convection (Still Air)
• JESD51-3, Low Effective Thermal Conductivity Test Board for Leaded Surface Mount Packages
• JESD51-7, High Effective Thermal Conductivity Test Board for Leaded Surface Mount Packages
• JESD51-9, Test Boards for Area Array Surface Mount Package Thermal Measurements
(2) lfm = linear feet per minute
7.7.2 PTP Package
°C/W(1) AIR FLOW (lfm)(2)
RΘJC Junction-to-case thermal resistance 6.97 N/A
RΘJB Junction-to-board thermal resistance 6.05 N/A
RΘJA (High k PCB) Junction-to-free air thermal resistance 17.8 0
RΘJMA Junction-to-moving air thermal resistance
12.8 150
11.4 250
10.1 500
PsiJT Junction-to-package top
0.11 0
0.24 150
0.33 250
0.42 500
PsiJB Junction-to-board
6.1 0
5.5 150
5.4 250
5.3 500
(1) These values are based on a JEDEC-defined 2S2P system (with the exception of the Theta JC [RΘJC] value, which is based on a
JEDEC-defined 1S0P system) and will change based on environment as well as application. For more information, see these EIA/
JEDEC standards:
• JESD51-2, Integrated Circuits Thermal Test Method Environmental Conditions - Natural Convection (Still Air)
• JESD51-3, Low Effective Thermal Conductivity Test Board for Leaded Surface Mount Packages
• JESD51-7, High Effective Thermal Conductivity Test Board for Leaded Surface Mount Packages
• JESD51-9, Test Boards for Area Array Surface Mount Package Thermal Measurements
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(2) lfm = linear feet per minute
7.7.3 PZP Package
°C/W(1) AIR FLOW (lfm)(2)
RΘJC Junction-to-case thermal resistance 4.3 N/A
RΘJB Junction-to-board thermal resistance 5.9 N/A
RΘJA (High k PCB) Junction-to-free air thermal resistance 19.1 0
RΘJMA Junction-to-moving air thermal resistance
14.3 150
12.8 250
11.4 500
PsiJT Junction-to-package top
0.03 0
0.09 150
0.12 250
0.20 500
PsiJB Junction-to-board
6.0 0
5.5 150
5.5 250
5.3 500
(1) These values are based on a JEDEC-defined 2S2P system (with the exception of the Theta JC [RΘJC] value, which is based on a
JEDEC-defined 1S0P system) and will change based on environment as well as application. For more information, see these EIA/
JEDEC standards:
• JESD51-2, Integrated Circuits Thermal Test Method Environmental Conditions - Natural Convection (Still Air)
• JESD51-3, Low Effective Thermal Conductivity Test Board for Leaded Surface Mount Packages
• JESD51-7, High Effective Thermal Conductivity Test Board for Leaded Surface Mount Packages
• JESD51-9, Test Boards for Area Array Surface Mount Package Thermal Measurements
(2) lfm = linear feet per minute
7.8 Thermal Design Considerations
Based on the end application design and operational profile, the IDD and IDDIO currents could vary. Systems that
exceed the recommended maximum power dissipation in the end product may require additional thermal
enhancements. Ambient temperature (TA) varies with the end application and product design. The critical factor
that affects reliability and functionality is TJ, the junction temperature, not the ambient temperature. Hence, care
should be taken to keep TJ within the specified limits. Tcase should be measured to estimate the operating
junction temperature TJ. Tcase is normally measured at the center of the package top-side surface. The thermal
application report Semiconductor and IC Package Thermal Metrics helps to understand the thermal metrics and
definitions.
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7.9 System
7.9.1 Power Sequencing
7.9.1.1 Signal Pin Requirements
Before powering the device, no voltage larger than 0.3 V above VDDIO can be applied to any digital pin, and no
voltage larger than 0.3 V above VDDA can be applied to any analog pin (including VREFHI).
7.9.1.2 VDDIO, VDDA, VDD3VFL, and VDDOSC Requirements
The 3.3-V supplies should be powered up together and kept within 0.3 V of each other during functional
operation.
7.9.1.3 VDD Requirements
The internal VREG is not supported. The VREGENZ pin must be tied to VDDIO and an external source used to
supply 1.2 V to VDD. During the ramp, VDD should be kept no more than 0.3 V above VDDIO.
VDDOSC and VDD must be powered on and off at the same time. VDDOSC should not be powered on when VDD is
off. For applications not powering VDDOSC and VDD at the same time, see the "INTOSC: VDDOSC Powered
Without VDD Can Cause INTOSC Frequency Drift" advisory in the TMS320F2837xS MCUs Silicon Errata .
There is an internal 12.8-mA current source from VDD3VFL to VDD when the flash banks are active. When the
flash banks are active and the device is in a low-activity state (for example, a low-power mode), this internal
current source can cause VDD to rise to approximately 1.3 V. There will be zero current load to the external
system VDD regulator while in this condition. This is not an issue for most regulators; however, if the system
voltage regulator requires a minimum load for proper operation, then an external 82Ω resistor can be added to
the board to ensure a minimal current load on VDD. See the "Low-Power Modes: Power Down Flash or Maintain
Minimum Device Activity" advisory in the TMS320F2837xS MCUs Silicon Errata .
7.9.1.4 Supply Ramp Rate
The supplies should ramp to full rail within 10 ms. Section 7.9.1.4.1 shows the supply ramp rate.
7.9.1.4.1 Supply Ramp Rate
MIN MAX UNIT
Supply ramp rate VDDIO, VDD, VDDA, VDD3VFL, VDDOSC with respect to VSS 330 105V/s
7.9.1.5 Supply Supervision
An internal power-on-reset (POR) circuit keeps the I/Os in a high-impedance state during power up. External
supply voltage supervisors (SVS) can be used to monitor the voltage on the 3.3-V and 1.2-V rails and drive XRS
low when supplies are outside operational specifications.
Note
If the supply voltage is held near the POR threshold, then the device may drive periodic resets onto
the XRS pin.
7.9.2 Reset Timing
XRS is the device reset pin. It functions as an input and open-drain output. The device has a built-in power-on
reset (POR). During power up, the POR circuit drives the XRS pin low. A watchdog or NMI watchdog reset also
drives the pin low. An external circuit may drive the pin to assert a device reset.
A resistor with a value from 2.2 kΩ to 10 kΩ should be placed between XRS and VDDIO. A capacitor should be
placed between XRS and VSS for noise filtering; the capacitance should be 100 nF or smaller. These values will
allow the watchdog to properly drive the XRS pin to VOL within 512 OSCCLK cycles when the watchdog reset is
asserted. Figure 7-4 shows the recommended reset circuit.
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XRS
£100 nF
2.2 k – 10 kW W
VDDIO
Figure 7-4. Reset Circuit
7.9.2.1 Reset Sources
The following reset sources exist on this device: XRS, WDRS, NMIWDRS, SYSRS, SCCRESET, and
HIBRESET. See the Reset Signals table in the System Control chapter of the TMS320F2837xS Microcontrollers
Technical Reference Manual .
The parameter th(boot-mode) must account for a reset initiated from any of these sources.
CAUTION
Some reset sources are internally driven by the device. Some of these sources will drive XRS low.
Use this to disable any other devices driving the boot pins. The SCCRESET and debugger reset
sources do not drive XRS; therefore, the pins used for boot mode should not be actively driven by
other devices in the system. The boot configuration has a provision for changing the boot pins in
OTP; for more details, see the TMS320F2837xS Microcontrollers Technical Reference Manual .
7.9.2.2 Reset Electrical Data and Timing
Section 7.9.2.2.1 shows the reset ( XRS) timing requirements. Section 7.9.2.2.2 shows the reset ( XRS)
switching characteristics. Figure 7-5 shows the power-on reset. Figure 7-6 shows the warm reset.
7.9.2.2.1 Reset ( XRS) Timing Requirements
MIN MAX UNIT
th(boot-mode) Hold time for boot-mode pins 1.5 ms
tw(RSL2) Pulse duration, XRS low on
warm reset
All cases 3.2
µs
Low-power modes used in
application and SYSCLKDIV > 16 3.2 * (SYSCLKDIV/16)
7.9.2.2.2 Reset ( XRS) Switching Characteristics
over recommended operating conditions (unless otherwise noted)
PARAMETER MIN TYP MAX UNIT
tw(RSL1) Pulse duration, XRS driven low by device after supplies are
stable 100 µs
tw(WDRS) Pulse duration, reset pulse generated by watchdog 512tc(OSCCLK) cycles
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TEXAS INSTRUMENTS M/ //X‘ W X, User-code dependem wwwowwwwo'wwV" — ’o!202fotofofofiofiofofotéofoféofiotw 1‘ \ X ‘ X y X X/ User-Code Dependem
th(boot-mode)(B)
XRS(A)
Boot-Mode
Pins
V V
(3.3 V)
DDIO DDA
,
V (1.2 V)
DD
User-code dependent
Boot-ROM execution starts Peripheral/GPIO function
Based on boot code
GPIO pins as input
CPU
Execution
Phase
Boot ROM
User-code
I/O Pins GPIO pins as input (pullups are disabled)
User-code dependent
tw(RSL1)
A. The XRS pin can be driven externally by a supervisor or an external pullup resistor, see Section 6.2.1.
B. After reset from any source (see Section 7.9.2.1), the boot ROM code samples Boot Mode pins. Based on the status of the Boot Mode
pin, the boot code branches to destination memory or boot code function. If boot ROM code executes after power-on conditions (in
debugger environment), the boot code execution time is based on the current SYSCLK speed. The SYSCLK will be based on user
environment and could be with or without PLL enabled.
Figure 7-5. Power-on Reset
th(boot-mode)(A)
XRS
Boot-Mode
Pins
I/O Pins
CPU
Execution
Phase
Boot-ROM execution starts
(initiated by any reset source)
User-Code Execution Starts
User Code
Boot ROM
User-Code Dependent
User Code
Peripheral/GPIO Function
User-Code Dependent
GPIO Pins as Input (Pullups are Disabled)
GPIO Pins as Input Peripheral/GPIO Function
tw(RSL2)
A. After reset from any source (see Section 7.9.2.1), the Boot ROM code samples BOOT Mode pins. Based on the status of the Boot Mode
pin, the boot code branches to destination memory or boot code function. If Boot ROM code executes after power-on conditions (in
debugger environment), the Boot code execution time is based on the current SYSCLK speed. The SYSCLK will be based on user
environment and could be with or without PLL enabled.
Figure 7-6. Warm Reset
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7.9.3 Clock Specifications
7.9.3.1 Clock Sources
Table 7-2 lists four possible clock sources. Figure 7-7 provides an overview of the device's clocking system.
Table 7-2. Possible Reference Clock Sources
CLOCK SOURCE MODULES CLOCKED COMMENTS
INTOSC1 Can be used to provide clock for:
• Watchdog block
• Main PLL
• CPU-Timer 2
Internal oscillator 1.
Zero-pin overhead 10-MHz internal oscillator.
INTOSC2(1) Can be used to provide clock for:
• Main PLL
• Auxiliary PLL
• CPU-Timer 2
Internal oscillator 2.
Zero-pin overhead 10-MHz internal oscillator.
XTAL Can be used to provide clock for:
• Main PLL
• Auxiliary PLL
• CPU-Timer 2
External crystal or resonator connected between the X1 and X2 pins
or single-ended clock connected to the X1 pin.
AUXCLKIN Can be used to provide clock for:
• Auxiliary PLL
• CPU-Timer 2
Single-ended 3.3-V level clock source. GPIO133/AUXCLKIN pin
should be used to provide the input clock.
(1) On reset, internal oscillator 2 (INTOSC2) is the default clock source for both system PLL (OSCCLK) and auxiliary PLL (AUXOSCCLK).
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Efifi G
PLLSYSCLK
System PLL
CPU
Auxiliary PLL
LSP
Divider
OSCCLK
AUXOSCCLK
AUXPLLRAWCLK
AUXPLLCLK
PLLRAWCLK
CPU1.CPUCLKSYSCLK
PLLSYSCLK
PCLKCRx
LOSPCP PCLKCRx
To GS RAMs, GPIOs,
and NMIWDs
To ePWMs
To SCIs, SPIs, and
McBSPs
To USB bit clock
To watchdog timer
WDCLK
CLKSRCCTL1
CLKSRCCTL2 AUXPLLCTL1
SYSPLLCTL1
One per SYSCLK peripheral
One per LSPCLK peripheral
LSPCLK
SYSCLK
Divider
SYSCLKDIVSEL
INTOSC1
INTOSC2
X1(XTAL)
AUXCLKIN
AUXCLK
Divider
AUXCLKDIVSEL
CAN Bit Clock
CLKSRCCTL2
To CANs
One per CAN module
To ePIEs, LS RAMs,
CLA message RAMs,
and DCSMs
To local memories
CPU1.SYSCLK
PERx.LSPCLK
PCLKCRx
To peripherals
One per ePWM
PERx.SYSCLK
EPWMCLK
EPWMCLKDIV
/1
/2
To HRPWMs
HRPWM
HRPWMCLK
PCLKCRx
Figure 7-7. Clocking System
TMS320F28379S, TMS320F28378S, TMS320F28377S, TMS320F28377S-Q1
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7.9.3.2 Clock Frequencies, Requirements, and Characteristics
This section provides the frequencies and timing requirements of the input clocks, PLL lock times, frequencies of
the internal clocks, and the frequency and switching characteristics of the output clock.
7.9.3.2.1 Input Clock Frequency and Timing Requirements, PLL Lock Times
Section 7.9.3.2.1.1 shows the frequency requirements for the input clocks. Table 7-3 shows the crystal
equivalent series resistance requirements. Section 7.9.3.2.1.2 shows the X1 input level characteristics when
using an external clock source. Section 7.9.3.2.1.3 and Section 7.9.3.2.1.4 show the timing requirements for the
input clocks. Section 7.9.3.2.1.5 shows the PLL lock times for the Main PLL and the USB PLL.
7.9.3.2.1.1 Input Clock Frequency
MIN MAX UNIT
f(XTAL) Frequency, X1/X2, from external crystal or resonator 10 20 MHz
f(X1) Frequency, X1, from external oscillator 2 25 MHz
f(AUXI) Frequency, AUXCLKIN, from external oscillator 2 60 MHz
7.9.3.2.1.2 X1 Input Level Characteristics When Using an External Clock Source (Not a Crystal)
over recommended operating conditions (unless otherwise noted)
PARAMETER MIN MAX UNIT
X1 VIL Valid low-level input voltage –0.3 0.3 * VDDIO V
X1 VIH Valid high-level input voltage 0.7 * VDDIO VDDIO + 0.3 V
7.9.3.2.1.3 X1 Timing Requirements
MIN MAX UNIT
tf(X1) Fall time, X1 6 ns
tr(X1) Rise time, X1 6 ns
tw(X1L) Pulse duration, X1 low as a percentage of tc(X1) 45% 55%
tw(X1H) Pulse duration, X1 high as a percentage of tc(X1) 45% 55%
7.9.3.2.1.4 AUXCLKIN Timing Requirements
MIN MAX UNIT
tf(AUXI) Fall time, AUXCLKIN 6 ns
tr(AUXI) Rise time, AUXCLKIN 6 ns
tw(AUXL) Pulse duration, AUXCLKIN low as a percentage of tc(XCI) 45% 55%
tw(AUXH) Pulse duration, AUXCLKIN high as a percentage of tc(XCI) 45% 55%
7.9.3.2.1.5 PLL Lock Times
MIN NOM MAX UNIT
t(PLL) Lock time, Main PLL (X1, from external oscillator) 50 µs + 2500 * tc(OSCCLK) (1) µs
t(USB) Lock time, USB PLL (AUXCLKIN, from external oscillator) 50 µs + 2500 * tc(OSCCLK) (1) µs
(1) The PLL lock time here defines the typical time of execution for the PLL workaround as defined in the TMS320F2837xS MCUs Silicon
Errata . Cycle count includes code execution of the PLL initialization routine, which could vary depending on compiler optimizations
and flash wait states. TI recommends using the latest example software from C2000Ware for initializing the PLLs. For the system PLL,
see InitSysPll() or SysCtl_setClock(). For the auxillary PLL, see InitAuxPll() or SysCtl_setAuxClock().
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7.9.3.2.2 Internal Clock Frequencies
Section 7.9.3.2.2.1 provides the clock frequencies for the internal clocks.
7.9.3.2.2.1 Internal Clock Frequencies
MIN NOM MAX UNIT
f(SYSCLK) Frequency, device (system) clock 2 200(2) MHz
tc(SYSCLK) Period, device (system) clock 5(2) 500 ns
f(PLLRAWCLK) Frequency, system PLL output (before SYSCLK
divider) 120 400 MHz
f(AUXPLLRAWCLK) Frequency, auxiliary PLL output (before AUXCLK
divider) 120 400 MHz
f(AUXPLL) Frequency, AUXPLLCLK 2 60 60 MHz
f(PLL) Frequency, PLLSYSCLK 2 200(2) MHz
f(LSP) Frequency, LSPCLK 2 200(2) MHz
tc(LSPCLK) Period, LSPCLK 5(2) 500 ns
f(OSCCLK) Frequency, OSCCLK (INTOSC1 or INTOSC2 or
XTAL or X1) See respective clock MHz
f(EPWM) Frequency, EPWMCLK(1) 100 MHz
f(HRPWM) Frequency, HRPWMCLK 60 100 MHz
(1) For SYSCLK above 100 MHz, the EPWMCLK must be half of SYSCLK.
(2) Using an external clock source. If INTOSC1 or INTOSC2 is used as the clock source, then the maximum frequency is 194 MHz and
the minimum period is 5.15 ns.
7.9.3.2.3 Output Clock Frequency and Switching Characteristics
Section 7.9.3.2.3.1 provides the frequency of the output clock. Section 7.9.3.2.3.2 shows the switching
characteristics of the output clock, XCLKOUT.
7.9.3.2.3.1 Output Clock Frequency
MIN MAX UNIT
f(XCO) Frequency, XCLKOUT 50 MHz
7.9.3.2.3.2 XCLKOUT Switching Characteristics (PLL Bypassed or Enabled)
over recommended operating conditions (unless otherwise noted)
PARAMETER(1) (2) MIN MAX UNIT
tf(XCO) Fall time, XCLKOUT 5 ns
tr(XCO) Rise time, XCLKOUT 5 ns
tw(XCOL) Pulse duration, XCLKOUT low H – 2 H + 2 ns
tw(XCOH) Pulse duration, XCLKOUT high H – 2 H + 2 ns
(1) A load of 40 pF is assumed for these parameters.
(2) H = 0.5tc(XCO)
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ii? *9 ¥§§¢§UMENTS A A R L! g
7.9.3.3 Input Clocks and PLLs
In addition to the internal 0-pin oscillators, multiple external clock source options are available. Figure 7-8 shows
the recommended methods of connecting crystals, resonators, and oscillators to pins X1/X2 (also referred to as
XTAL) and AUXCLKIN.
X1 X2
CRYSTAL
X1 X2
X1 X2
3.3V
OUTVDD
GND
CLK
RDCL2 CL1
RESONATOR
3.3V OSCILLATOR
NC
vssosc
GPIO133/AUXCLKIN
3.3V
OUTVDD
GND
CLK
3.3V OSCILLATOR
vssosc
vssosc
Figure 7-8. Connecting Input Clocks to a 2837xS Device
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7.9.3.4 Crystal Oscillator
When using a quartz crystal, it may be necessary to include a damping resistor (RD) in the crystal circuit to
prevent over-driving the crystal (drive level can be found in the crystal data sheet). In higher-frequency
applications (10 MHz or greater), RD is generally not required. If a damping resistor is required, RD should be as
small as possible because the size of the resistance affects start-up time (smaller RD = faster start-up time). TI
recommends that the crystal manufacturer characterize the crystal with the application board. Section 7.9.3.4.1
shows the crystal oscillator parameters. Table 7-3 shows the crystal equivalent series resistance (ESR)
requirements. Section 7.9.3.4.2 shows the crystal oscillator electrical characteristics.
7.9.3.4.1 Crystal Oscillator Parameters
MIN MAX UNIT
CL1, CL2 Load capacitance 12 24 pF
C0 Crystal shunt capacitance 7 pF
Table 7-3. Crystal Equivalent Series Resistance (ESR) Requirements
CRYSTAL FREQUENCY (MHz)
(1) (2)
MAXIMUM ESR (Ω)
(CL1 = CL2 = 12 pF)
MAXIMUM ESR (Ω)
(CL1 = CL2 = 24 pF)
10 55 110
12 50 95
14 50 90
16 45 75
18 45 65
20 45 50
(1) Crystal shunt capacitance (C0) should be less than or equal to 7 pF.
(2) ESR = Negative Resistance/3
7.9.3.4.2 Crystal Oscillator Electrical Characteristics
over recommended operating conditions (unless otherwise noted)
PARAMETER TEST CONDITIONS MIN TYP MAX UNIT
Start-up time(1)
f = 20 MHz
ESR MAX = 50 Ω
CL1 = CL2 = 24 pF
C0 = 7 pF
2 ms
Crystal drive level (DL) 1 mW
(1) Start-up time is dependent on the crystal and tank circuit components. TI recommends that the crystal vendor characterize the
application with the chosen crystal.
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7.9.3.5 Internal Oscillators
To reduce production board costs and application development time, all F2837xS devices contain two
independent internal oscillators, referred to as INTOSC1 and INTOSC2. By default, both oscillators are enabled
at power up. INTOSC2 is set as the source for the system reference clock (OSCCLK) and INTOSC1 is set as the
backup clock source. INTOSC1 can also be manually configured as the system reference clock (OSCCLK).
Section 7.9.3.5.1 provides the electrical characteristics of the internal oscillators to determine if this module
meets the clocking requirements of the application.
Section 7.9.3.5.1 provides the electrical characteristics of the two internal oscillators.
Note
This oscillator cannot be used as the PLL source if the PLLSYSCLK is configured to frequencies
above 194 MHz.
7.9.3.5.1 Internal Oscillator Electrical Characteristics
over recommended operating conditions (unless otherwise noted)
PARAMETER TEST CONDITIONS MIN TYP MAX UNIT
f(INTOSC) Frequency, INTOSC1 and INTOSC2 9.7 10.0 10.3 MHz
f(INTOSC-STABILITY)
Frequency stability at room temperature 30°C, Nominal VDD ±0.1%
Frequency stability over VDD 30°C ±0.2%
Frequency stability –3.0% 3.0%
f(INTOSC-ST) Start-up and settling time 20 µs
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7.9.4 Flash Parameters
The on-chip flash memory is tightly integrated to the CPU, allowing code execution directly from flash through
128-bit-wide prefetch reads and a pipeline buffer. Flash performance for sequential code is equal to execution
from RAM. Factoring in discontinuities, most applications will run with an efficiency of approximately 80% relative
to code executing from RAM. This flash efficiency lets designers realize a 2× improvement in performance when
migrating from the previous generation of MCUs. Note that an extra wait state is automatically added when code
is fetched or data is read from Bank 1 (compared to that of Bank 0), even for prefetched data.
This device also has an OTP (One-Time-Programmable) sector used for the dual code security module (DCSM),
which cannot be erased after it is programmed.
Table 7-4 shows the minimum required flash wait states at different frequencies. Section 7.9.4.1 shows the flash
parameters.
Table 7-4. Flash Wait States
CPUCLK (MHz) MINIMUM WAIT STATES (1)
EXTERNAL OSCILLATOR OR CRYSTAL INTOSC1 OR INTOSC2
150 < CPUCLK ≤ 200 145 < CPUCLK ≤ 194 3
100 < CPUCLK ≤ 150 97 < CPUCLK ≤ 145 2
50 < CPUCLK ≤ 100 48 < CPUCLK ≤ 97 1
CPUCLK ≤ 50 CPUCLK ≤ 48 0
(1) Minimum required FRDCNTL[RWAIT].
7.9.4.1 Flash Parameters
PARAMETER MIN TYP MAX UNIT
Program Time(1)
128 data bits + 16 ECC bits 40 300 µs
8KW sector 90 180 ms
32KW sector 360 720 ms
Erase Time(2) at < 25 cycles 8KW sector 25 50 ms
32KW sector 30 55
Erase Time(2) at 20k cycles 8KW sector 105 4000 ms
32KW sector 110 4000
Nwec Write/erase cycles 20000 cycles
tretention Data retention duration at TJ = 85°C 20 years
(1) Program time is at the maximum device frequency. Program time includes overhead of the flash state machine but does not include
the time to transfer the following into RAM:
• Code that uses flash API to program the flash
• Flash API itself
• Flash data to be programmed
In other words, the time indicated in this table is applicable after all the required code/data is available in the device RAM, ready for
programming. The transfer time will significantly vary depending on the speed of the JTAG debug probe used.
Program time calculation is based on programming 144 bits at a time at the specified operating frequency. Program time includes
Program verify by the CPU. The program time does not degrade with write/erase (W/E) cycling, but the erase time does.
Erase time includes Erase verify by the CPU and does not involve any data transfer.
(2) Erase time includes Erase verify by the CPU.
Note
The Main Array flash programming must be aligned to 64-bit address boundaries and each 64-bit
word may only be programmed once per write/erase cycle. For more details, see the "Flash: Minimum
Programming Word Size" advisory in the TMS320F2837xS MCUs Silicon Errata .
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I TEXAS INSTRUMENTS Dusmhce between the header and the targex shomd be ‘255 than 6 mches 115.24 cm).
7.9.5 Emulation/JTAG
The JTAG port has five dedicated pins: TRST, TMS, TDI, TDO, and TCK. The TRST signal should always be
pulled down through a 2.2-kΩ pulldown resistor on the board. This MCU does not support the EMU0 and EMU1
signals that are present on 14-pin and 20-pin emulation headers. These signals should always be pulled up at
the emulation header through a pair of board pullup resistors ranging from 2.2 kΩ to 4.7 kΩ (depending on the
drive strength of the debugger ports). Typically, a 2.2-kΩ value is used.
See Figure 7-9 to see how the 14-pin JTAG header connects to the MCU’s JTAG port signals. Figure 7-10 shows
how to connect to the 20-pin header. The 20-pin JTAG header terminals EMU2, EMU3, and EMU4 are not used
and should be grounded.
The PD (Power Detect) terminal of the JTAG debug probe header should be connected to the board 3.3-V
supply. Header GND terminals should be connected to board ground. TDIS (Cable Disconnect Sense) should
also be connected to board ground. The JTAG clock should be looped from the header TCK output terminal back
to the RTCK input terminal of the header (to sense clock continuity by the JTAG debug probe). Header terminal
RESET is an open-drain output from the JTAG debug probe header that enables board components to be reset
through JTAG debug probe commands (available only through the 20-pin header).
Typically, no buffers are needed on the JTAG signals when the distance between the MCU target and the JTAG
header is smaller than 6 inches (15.24 cm), and no other devices are present on the JTAG chain. Otherwise,
each signal should be buffered. Additionally, for most JTAG debug probe operations at 10 MHz, no series
resistors are needed on the JTAG signals. However, if high emulation speeds are expected (35 MHz or so), 22-Ω
resistors should be placed in series on each JTAG signal.
For more information about hardware breakpoints and watchpoints, see Hardware Breakpoints and Watchpoints
for C28x in CCS.
For more information about JTAG emulation, see the XDS Target Connection Guide.
TMS
TDI
TDO
PD
RTCK
TCK
EMU0
TRST
TDIS
GND
KEY
GND
GND
EMU1
GND
TCK
TDO
TDI
TMS
TRST GND
12
3 4
5 6
7 8
9 10
11 12
1413 3.3 V
3.3 V
100 W
2.2 kW
4.7 kW4.7 kW
3.3 V
Distance between the header and the target
should be less than 6 inches (15.24 cm).
MCU
Figure 7-9. Connecting to the 14-Pin JTAG Header
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I TEXAS INSTRUMENTS Dwstance between the header and the target ’I " should be \esslhan a mches (15.24 cm). W» i J _‘M\— _ 7 9 —qw~— M— v GND GND
TMS
TDI
TDO
PD
RTCK
TCK
EMU0
TRST
TDIS
GND
KEY
GND
GND
EMU1
GND
GND
TCK
TDO
TDI
TMS
TRST
RESET
EMU2
EMU4
EMU3
GND
GND
open
drain
A low pulse from the JTAG debug probe
can be tied with other reset sources
to reset the board.
12
3 4
5 6
7 8
9 10
11 12
1413
1615
1817
2019
3.3 V3.3 V
3.3V
100 W
2.2 kW
4.7 kW4.7 kW
GND
GND
MCU
Distance between the header and the target
should be less than 6 inches (15.24 cm).
Figure 7-10. Connecting to the 20-Pin JTAG Header
TMS320F28379S, TMS320F28378S, TMS320F28377S, TMS320F28377S-Q1
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7.9.5.1 JTAG Electrical Data and Timing
Section 7.9.5.1.1 lists the JTAG timing requirements. Section 7.9.5.1.2 lists the JTAG switching characteristics.
Figure 7-11 shows the JTAG timing.
7.9.5.1.1 JTAG Timing Requirements
NO. MIN MAX UNIT
1 tc(TCK) Cycle time, TCK 66.66 ns
1a tw(TCKH) Pulse duration, TCK high (40% of tc) 26.66 ns
1b tw(TCKL) Pulse duration, TCK low (40% of tc) 26.66 ns
3tsu(TDI-TCKH) Input setup time, TDI valid to TCK high 13 ns
tsu(TMS-TCKH) Input setup time, TMS valid to TCK high 13 ns
4th(TCKH-TDI) Input hold time, TDI valid from TCK high 7 ns
th(TCKH-TMS) Input hold time, TMS valid from TCK high 7 ns
7.9.5.1.2 JTAG Switching Characteristics
over recommended operating conditions (unless otherwise noted)
NO. PARAMETER MIN MAX UNIT
2 td(TCKL-TDO) Delay time, TCK low to TDO valid 6 25 ns
3
TCK
TDO
TDI/TMS
2
4
1
1a 1b
Figure 7-11. JTAG Timing
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7.9.6 GPIO Electrical Data and Timing
The peripheral signals are multiplexed with general-purpose input/output (GPIO) signals. On reset, GPIO pins
are configured as inputs. For specific inputs, the user can also select the number of input qualification cycles to
filter unwanted noise glitches.
The GPIO module contains an Output X-BAR which allows an assortment of internal signals to be routed to a
GPIO in the GPIO mux positions denoted as OUTPUTXBARx. The GPIO module also contains an Input X-BAR
which is used to route signals from any GPIO input to different IP blocks such as the ADC(s), eCAP(s),
ePWM(s), and external interrupts. For more details, see the X-BAR chapter in the TMS320F2837xS
Microcontrollers Technical Reference Manual .
7.9.6.1 GPIO - Output Timing
Section 7.9.6.1.1 shows the general-purpose output switching characteristics. Figure 7-12 shows the general-
purpose output timing.
7.9.6.1.1 General-Purpose Output Switching Characteristics
over recommended operating conditions (unless otherwise noted)
PARAMETER MIN MAX UNIT
tr(GPO) Rise time, GPIO switching low to high All GPIOs 8(1) ns
tf(GPO) Fall time, GPIO switching high to low All GPIOs 8(1) ns
tfGPO Toggling frequency, GPO pins 25 MHz
(1) Rise time and fall time vary with load. These values assume a 40-pF load.
GPIO
tf(GPO)
tr(GPO)
Figure 7-12. General-Purpose Output Timing
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{5‘ TEXAS INSTRUMENTS [N MMMMMMMMMMM
7.9.6.2 GPIO - Input Timing
Section 7.9.6.2.1 shows the general-purpose input timing requirements. Figure 7-13 shows the sampling mode.
7.9.6.2.1 General-Purpose Input Timing Requirements
MIN MAX UNIT
tw(SP) Sampling period QUALPRD = 0 1tc(SYSCLK) cycles
QUALPRD ≠ 0 2tc(SYSCLK) * QUALPRD cycles
tw(IQSW) Input qualifier sampling window tw(SP) * (n(1) – 1) cycles
tw(GPI) (2) Pulse duration, GPIO low/high Synchronous mode 2tc(SYSCLK) cycles
With input qualifier tw(IQSW) + tw(SP) + 1tc(SYSCLK) cycles
(1) "n" represents the number of qualification samples as defined by GPxQSELn register.
(2) For tw(GPI), pulse width is measured from VIL to VIL for an active low signal and VIH to VIH for an active high signal.
GPIO Signal
1
Sampling Window
1 1 1111111110000000 000
SYSCLK
(A)
GPxQSELn = 1,0 (6 samples)
(D)
Output From
Qualifier
QUALPRD = 1
(SYSCLK/2)
tw(IQSW)
tw(SP)
(SYSCLK cycle * 2 * QUALPRD) * 5(C)
Sampling Period determined
by GPxCTRL[QUALPRD](B)
A. This glitch will be ignored by the input qualifier. The QUALPRD bit field specifies the qualification sampling period. It can vary from 00 to
0xFF. If QUALPRD = 00, then the sampling period is 1 SYSCLK cycle. For any other value "n", the qualification sampling period in 2n
SYSCLK cycles (that is, at every 2n SYSCLK cycles, the GPIO pin will be sampled).
B. The qualification period selected through the GPxCTRL register applies to groups of 8 GPIO pins.
C. The qualification block can take either three or six samples. The GPxQSELn Register selects which sample mode is used.
D. In the example shown, for the qualifier to detect the change, the input should be stable for 10 SYSCLK cycles or greater. In other words,
the inputs should be stable for (5 x QUALPRD x 2) SYSCLK cycles. This would ensure 5 sampling periods for detection to occur.
Because external signals are driven asynchronously, an 13-SYSCLK-wide pulse ensures reliable recognition.
Figure 7-13. Sampling Mode
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I TEXAS INSTRUMENTS Sampling frequency = SYSCLK/(2 >< qualprd),="" if="" qualprd="" ¢="" 0="" sampling="" frequency="SYSCLK," ifqualprd="" :="" 0="" sampling="" penod="SYSCLK" cyc‘e="" x="" 2="" x="" qualprd,="" if="" qualprd="" ¢="" 0="" s="" _/\_/\_/\+/\_/\_/\_="" x="" x="">
7.9.6.3 Sampling Window Width for Input Signals
The following section summarizes the sampling window width for input signals for various input qualifier
configurations.
Sampling frequency denotes how often a signal is sampled with respect to SYSCLK.
Sampling frequency = SYSCLK/(2 QUALPRD), if QUALPRD 0´ ¹
(1)
Sampling frequency = SYSCLK, if QUALPRD 0=
(2)
Sampling period = SYSCLK cycle 2 QUALPRD, if QUALPRD 0´ ¹´
(3)
In Equation 1, Equation 2, and Equation 3, SYSCLK cycle indicates the time period of SYSCLK.
Sampling period = SYSCLK cycle, if QUALPRD = 0
In a given sampling window, either 3 or 6 samples of the input signal are taken to determine the validity of the
signal. This is determined by the value written to GPxQSELn register.
Case 1:
Qualification using 3 samples
Sampling window width = (SYSCLK cycle × 2 × QUALPRD) × 2, if QUALPRD ≠ 0
Sampling window width = (SYSCLK cycle) × 2, if QUALPRD = 0
Case 2:
Qualification using 6 samples
Sampling window width = (SYSCLK cycle × 2 × QUALPRD) × 5, if QUALPRD ≠ 0
Sampling window width = (SYSCLK cycle) × 5, if QUALPRD = 0
Figure 7-14 shows the general-purpose input timing.
GPIOxn
SYSCLK
tw(GPI)
Figure 7-14. General-Purpose Input Timing
TMS320F28379S, TMS320F28378S, TMS320F28377S, TMS320F28377S-Q1
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I TEXAS INSTRUMENTS CPU‘LFM‘NT chwAKExNT |:|—> 2 4“ e V
7.9.7 Interrupts
Figure 7-15 provides a high-level view of the interrupt architecture.
As shown in Figure 7-15, the devices support five external interrupts (XINT1 to XINT5) that can be mapped onto
any of the GPIO pins.
In this device, 16 ePIE block interrupts are grouped into 1 CPU interrupt. In total, there are 12 CPU interrupt
groups, with 16 interrupts per group.
INPUTXBAR4
CPU 1.W DINT
CPU1.LPMINT CPU1.WAKEINT
CPU1.TINT0
CPU1.
ePIE
INPUTXBAR13
INPUTXBAR5
INPUTXBAR6
INPUTXBAR14
GPIO0
GPIO1
...
...
GPIOx
CPU1.TIMER0
CPU1.XINT1 Control
CPU1.XINT5 Control
CPU1.XINT3 Control
CPU1.XINT4 Control
CPU1.XINT2 Control
Input
X-BAR
LPM Logic
CPU1.WD
INT13
INT14
NM I
CPU1
INT1
to
INT12
CPU1.TINT1
CPU1.TIMER1
CPU1.TINT2
CPU1.TIMER2
CPU1.TINT2
CPU1.NMIWD
Peripherals
Figure 7-15. External and ePIE Interrupt Sources
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7.9.7.1 External Interrupt (XINT) Electrical Data and Timing
Section 7.9.7.1.1 lists the external interrupt timing requirements. Section 7.9.7.1.2 lists the external interrupt
switching characteristics. Figure 7-16 shows the external interrupt timing.
7.9.7.1.1 External Interrupt Timing Requirements
MIN MAX UNIT(1)
tw(INT) Pulse duration, INT input low/high Synchronous 2tc(SYSCLK) cycles
With qualifier tw(IQSW) + tw(SP) + 1tc(SYSCLK) cycles
(1) For an explanation of the input qualifier parameters, see Section 7.9.6.2.1.
7.9.7.1.2 External Interrupt Switching Characteristics
over recommended operating conditions (unless otherwise noted)(1)
PARAMETER MIN MAX UNIT
td(INT) Delay time, INT low/high to interrupt-vector fetch(2) tw(IQSW) + 14tc(SYSCLK) tw(IQSW) + tw(SP) + 14tc(SYSCLK) cycles
(1) For an explanation of the input qualifier parameters, see Section 7.9.6.2.1.
(2) This assumes that the ISR is in a single-cycle memory.
Interrupt Vector
XINT1, XINT2, XINT3,
XINT4, XINT5
Address bus
(internal)
tw(INT)
td(INT)
Figure 7-16. External Interrupt Timing
TMS320F28379S, TMS320F28378S, TMS320F28377S, TMS320F28377S-Q1
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7.9.8 Low-Power Modes
This device has three clock-gating low-power modes and a special power-gating mode.
Further details, as well as the entry and exit procedure, for all of the low-power modes can be found in the Low
Power Modes section of the TMS320F2837xS Microcontrollers Technical Reference Manual .
7.9.8.1 Clock-Gating Low-Power Modes
IDLE, STANDBY, and HALT modes on this device are similar to those on other C28x devices. Table 7-5
describes the effect on the system when any of the clock-gating low-power modes are entered.
Table 7-5. Effect of Clock-Gating Low-Power Modes on the Device
MODULES/
CLOCK DOMAIN CPU1 IDLE CPU1 STANDBY HALT
CPU1.CLKIN Active Gated Gated
CPU1.SYSCLK Active Gated Gated
CPU1.CPUCLK Gated Gated Gated
Clock to modules Connected to
PERx.SYSCLK
Active Gated Gated
CPU1.WDCLK Active Active Gated if CLKSRCCTL1.WDHALTI = 0
AUXPLLCLK Active Active Gated
PLL Powered Powered Software must power down PLL before entering
HALT
INTOSC1 Powered Powered Powered down if CLKSRCCTL1.WDHALTI = 0
INTOSC2 Powered Powered Powered down if CLKSRCCTL1.WDHALTI = 0
Flash Powered Powered Software-Controlled
X1/X2 Crystal Oscillator Powered Powered Powered-Down
7.9.8.2 Power-Gating Low-Power Modes
HIBERNATE mode is the lowest power mode on this device. It is a global low-power mode that gates the supply
voltages to most of the system. HIBERNATE is essentially a controlled power-down with remote wakeup
capability, and can be used to save power during long periods of inactivity. Table 7-6 describes the effects on the
system when the HIBERNATE mode is entered.
Table 7-6. Effect of Power-Gating Low-Power Mode on the Device
MODULES/POWER DOMAINS HIBERNATE
M0 and M1 memories ● Remain on with memory retention if LPMCR.M0M1MODE = 0x00
● Are off when LPMCR.M0M1MODE = 0x01
CPU1 digital peripherals Powered down
Dx, LSx, GSx memories Power down, memory contents are lost
I/Os On with output state preserved
Oscillators, PLL, analog
peripherals, Flash
Enters Low-Power Mode
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7.9.8.3 Low-Power Mode Wakeup Timing
Section 7.9.8.3.1 shows the IDLE mode timing requirements, Section 7.9.8.3.2 shows the switching
characteristics, and Figure 7-17 shows the timing diagram for IDLE mode.
7.9.8.3.1 IDLE Mode Timing Requirements
MIN MAX UNIT(1)
tw(WAKE) Pulse duration, external wake-up signal Without input qualifier 2tc(SYSCLK) cycles
With input qualifier 2tc(SYSCLK) + tw(IQSW)
(1) For an explanation of the input qualifier parameters, see Section 7.9.6.2.1.
7.9.8.3.2 IDLE Mode Switching Characteristics
over recommended operating conditions (unless otherwise noted)(1)
PARAMETER TEST CONDITIONS MIN MAX UNIT
td(WAKE-IDLE)
Delay time, external wake signal to program execution resume (2)
cycles
• Wakeup from Flash
– Flash module in active state
Without input qualifier 40tc(SYSCLK)
With input qualifier 40tc(SYSCLK) + tw(WAKE)
• Wakeup from Flash
– Flash module in sleep state
Without input qualifier 6700tc(SYSCLK) (3)
With input qualifier 6700tc(SYSCLK) (3) + tw(WAKE)
• Wakeup from RAM Without input qualifier 25tc(SYSCLK)
With input qualifier 25tc(SYSCLK) + tw(WAKE)
(1) For an explanation of the input qualifier parameters, see Section 7.9.6.2.1.
(2) This is the time taken to begin execution of the instruction that immediately follows the IDLE instruction. Execution of an ISR (triggered
by the wake-up signal) involves additional latency.
(3) This value is based on the flash power-up time, which is a function of the SYSCLK frequency, flash wait states (RWAIT), and
FPAC1[PSLEEP]. For more information, see the Flash and OTP Power-Down Modes and Wakeup section of the TMS320F2837xS
Microcontrollers Technical Reference Manual . This value can be realized when SYSCLK is 200 MHz, RWAIT is 3, and
FPAC1[PSLEEP] is 0x860.
WAKE(A)
XCLKOUT
Address/Data
(internal)
tw(WAKE)
td(WAKE-IDLE)
A. WAKE can be any enabled interrupt, WDINT or XRS. After the IDLE instruction is executed, a delay of five OSCCLK cycles (minimum) is
needed before the wake-up signal could be asserted.
Figure 7-17. IDLE Entry and Exit Timing Diagram
TMS320F28379S, TMS320F28378S, TMS320F28377S, TMS320F28377S-Q1
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Section 7.9.8.3.3 shows the STANDBY mode timing requirements, Section 7.9.8.3.4 shows the switching
characteristics, and Figure 7-18 shows the timing diagram for STANDBY mode.
7.9.8.3.3 STANDBY Mode Timing Requirements
MIN MAX UNIT
tw(WAKE-INT) Pulse duration, external
wake-up signal
QUALSTDBY = 0 | 2tc(OSCCLK) 3tc(OSCCLK)
cycles
QUALSTDBY > 0 |
(2 + QUALSTDBY)tc(OSCCLK) (1) (2 + QUALSTDBY) * tc(OSCCLK)
(1) QUALSTDBY is a 6-bit field in the LPMCR register.
7.9.8.3.4 STANDBY Mode Switching Characteristics
over recommended operating conditions (unless otherwise noted)
PARAMETER TEST CONDITIONS MIN MAX UNIT
td(IDLE-XCOS) Delay time, IDLE instruction executed to
XCLKOUT stop 16tc(INTOSC1) cycles
td(WAKE-STBY)
Delay time, external wake signal to
program execution resume(1)
cycles
• Wakeup from flash
– Flash module in active state 175tc(SYSCLK) + tw(WAKE-INT)
• Wakeup from flash
– Flash module in sleep state 6700tc(SYSCLK) (2) + tw(WAKE-
INT)
• Wakeup from RAM 3tc(OSC) + 15tc(SYSCLK) +
tw(WAKE-INT)
(1) This is the time taken to begin execution of the instruction that immediately follows the IDLE instruction. Execution of an ISR (triggered
by the wake-up signal) involves additional latency.
(2) This value is based on the flash power-up time, which is a function of the SYSCLK frequency, flash wait states (RWAIT), and
FPAC1[PSLEEP]. For more information, see the Flash and OTP Power-Down Modes and Wakeup section of the TMS320F2837xS
Microcontrollers Technical Reference Manual . This value can be realized when SYSCLK is 200 MHz, RWAIT is 3, and
FPAC1[PSLEEP] is 0x860.
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Wake-up
Signal
OSCCLK
XCLKOUT
Flushing Pipeline
(A)
Device
Status STANDBY Normal ExecutionSTANDBY
(G)(B)
(C)
(D)(E)
(F)
td(IDLE-XCOS)
tw(WAKE-INT)
td(WAKE-STBY)
A. IDLE instruction is executed to put the device into STANDBY mode.
B. The LPM block responds to the STANDBY signal, SYSCLK is held for a maximum 16 INTOSC1 clock cycles before being turned off.
This delay enables the CPU pipeline and any other pending operations to flush properly.
C. Clock to the peripherals are turned off. However, the PLL and watchdog are not shut down. The device is now in STANDBY mode. After
the IDLE instruction is executed, a delay of five OSCCLK cycles (minimum) is needed before the wake-up signal could be asserted.
D. The external wake-up signal is driven active.
E. The wake-up signal fed to a GPIO pin to wake up the device must meet the minimum pulse width requirement. Furthermore, this signal
must be free of glitches. If a noisy signal is fed to a GPIO pin, the wakeup behavior of the device will not be deterministic and the device
may not exit low-power mode for subsequent wakeup pulses.
F. After a latency period, the STANDBY mode is exited.
G. Normal execution resumes. The device will respond to the interrupt (if enabled).
Figure 7-18. STANDBY Entry and Exit Timing Diagram
TMS320F28379S, TMS320F28378S, TMS320F28377S, TMS320F28377S-Q1
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Section 7.9.8.3.5 shows the HALT mode timing requirements, Section 7.9.8.3.6 shows the switching
characteristics, and Figure 7-19 shows the timing diagram for HALT mode.
7.9.8.3.5 HALT Mode Timing Requirements
MIN MAX UNIT
tw(WAKE-GPIO) Pulse duration, GPIO wake-up signal(1) toscst + 2tc(OSCCLK) cycles
tw(WAKE-XRS) Pulse duration, XRS wake-up signal(1) toscst + 8tc(OSCCLK) cycles
(1) For applications using X1/X2 for OSCCLK, the user must characterize their specific oscillator start-up time as it is dependent on circuit/
layout external to the device. See Section 7.9.3.4.2 for more information. For applications using INTOSC1 or INTOSC2 for OSCCLK,
see Section 7.9.3.5 for toscst. Oscillator start-up time does not apply to applications using a single-ended crystal on the X1 pin, as it is
powered externally to the device.
7.9.8.3.6 HALT Mode Switching Characteristics
over recommended operating conditions (unless otherwise noted)
PARAMETER MIN MAX UNIT
td(IDLE-XCOS) Delay time, IDLE instruction executed to XCLKOUT stop 16tc(INTOSC1) cycles
td(WAKE-HALT)
Delay time, external wake signal end to CPU1 program
execution resume
cycles
• Wakeup from flash
– Flash module in active state 75tc(OSCCLK)
• Wakeup from flash
– Flash module in sleep state 17500tc(OSCCLK) (1)
• Wakeup from RAM 75tc(OSCCLK)
(1) This value is based on the flash power-up time, which is a function of the SYSCLK frequency, flash wait states (RWAIT), and
FPAC1[PSLEEP]. For more information, see the Flash and OTP Power-Down Modes and Wakeup section of the TMS320F2837xS
Microcontrollers Technical Reference Manual . This value can be realized when SYSCLK is 200 MHz, RWAIT is 3, and
FPAC1[PSLEEP] is 0x860.
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fl TEXAS INSTRUMENTS mm
OSCCLK
XCLKOUT
HALT HALT
Flushing Pipeline
Device
Status
Normal
Execution
GPIOn
(A) (C)
(D)(E)
(F)
(B) (G)
td(IDLE-XCOS)
tw(WAKE-GPIO)
td(WAKE-HALT)
Oscillator Start-up Time
A. IDLE instruction is executed to put the device into HALT mode.
B. The LPM block responds to the HALT signal, SYSCLK is held for a maximum 16 INTOSC1 clock cycles before being turned off. This
delay enables the CPU pipeline and any other pending operations to flush properly.
C. Clocks to the peripherals are turned off and the PLL is shut down. If a quartz crystal or ceramic resonator is used as the clock source,
the internal oscillator is shut down as well. The device is now in HALT mode and consumes very little power. It is possible to keep the
zero-pin internal oscillators (INTOSC1 and INTOSC2) and the watchdog alive in HALT MODE. This is done by writing a 1 to
CLKSRCCTL1.WDHALTI. After the IDLE instruction is executed, a delay of five OSCCLK cycles (minimum) is needed before the wake-
up signal could be asserted.
D. When the GPIOn pin (used to bring the device out of HALT) is driven low, the oscillator is turned on and the oscillator wakeup sequence
is initiated. The GPIO pin should be driven high only after the oscillator has stabilized. This enables the provision of a clean clock signal
during the PLL lock sequence. Because the falling edge of the GPIO pin asynchronously begins the wakeup procedure, care should be
taken to maintain a low noise environment prior to entering and during HALT mode.
E. The wake-up signal fed to a GPIO pin to wake up the device must meet the minimum pulse width requirement. Furthermore, this signal
must be free of glitches. If a noisy signal is fed to a GPIO pin, the wakeup behavior of the device will not be deterministic and the device
may not exit low-power mode for subsequent wakeup pulses.
F. When CLKIN to the core is enabled, the device will respond to the interrupt (if enabled), after some latency. The HALT mode is now
exited.
G. Normal operation resumes.
H. The user must relock the PLL upon HALT wakeup to ensure a stable PLL lock.
Figure 7-19. HALT Entry and Exit Timing Diagram
TMS320F28379S, TMS320F28378S, TMS320F28377S, TMS320F28377S-Q1
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Section 7.9.8.3.7 shows the HIBERNATE mode timing requirements, Section 7.9.8.3.8 shows the switching
characteristics, and Figure 7-20 shows the timing diagram for HIBERNATE mode.
7.9.8.3.7 HIBERNATE Mode Timing Requirements
MIN MAX UNIT
tw(HIBWAKE) Pulse duration, HIBWAKE signal 40 µs
tw(WAKEXRS) Pulse duration, XRS wake-up signal 40 µs
7.9.8.3.8 HIBERNATE Mode Switching Characteristics
over recommended operating conditions (unless otherwise noted)
PARAMETER MIN MAX UNIT
td(IDLE-XCOS) Delay time, IDLE instruction executed to XCLKOUT stop 30tc(SYSCLK) cycles
td(WAKE-HIB) Delay time, external wake signal to lORestore function start 1.5 ms
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w TEXAS INSTRUMENTS 4|
Inactive
Device Active CPU1 IDLE
Instruction
Enabled Bypassed &
Powered -Down
On Powered Down Powering up On
HIBERNATE CPU1 Boot ROM
Device Status
INTOSC1,INTOSC2,
X1/X2
GPIOHIBWAKEn,
XRSn
PLLs
I/O Isolation
IoRestore() or Application Specific Operation
CPU1 HIB
config
(A) (B) (C) (D)
tw(HIBWAKEn),
tw(XRSn)
(F) (G)(H) (I)(J)
XCLKCOUT Application Specific Operation
Application SpecificOperation
(E)
td(IDLE-XCOS)
Td(WAKE-HIB)
A. CPU1 does necessary application-specific context save to M0/M1 memories if required. This includes GPIO state if using I/O Isolation.
Configures the LPMCR register of CPU1 for HIBERNATE mode. Powers down Flash Pump/Bank, USB-PHY, CMPSS, DAC, and ADC
using their register configurations. The application should also power down the PLL and peripheral clocks before entering HIBERNATE.
B. IDLE instruction is executed to put the device into HIBERNATE mode.
C. The device is now in HIBERNATE mode. If configured, I/O isolation is turned on, M0 and M1 memories are retained. CPU1 is powered
down. Digital peripherals are powered down. The oscillators, PLLs, analog peripherals, and Flash are in their software-controlled Low-
Power modes. Dx, LSx, and GSx memories are also powered down, and their memory contents lost.
D. A falling edge on the GPIOHIBWAKEn pin will drive the wakeup of the devices clock sources INTOSC1, INTOSC2, and X1/X2 OSC. The
wakeup source must keep the GPIOHIBWAKEn pin low long enough to ensure full power-up of these clock sources.
E. After the clock sources are powered up, the GPIOHIBWAKEn must be driven high to trigger the wakeup sequence of the remainder of
the device.
F. The BootROM will then begin to execute. The BootROM can distinguish a HIBERNATE wakeup by reading the CPU1.REC.HIBRESETn
bit. After the TI OTP trims are loaded, the BootROM code will branch to the user-defined IoRestore function if it has been configured.
G. At this point, the device is out of HIBERNATE mode, and the application may continue.
H. The IoRestore function is a user-defined function where the application may reconfigure GPIO states, disable I/O isolation, reconfigure
the PLL, restore peripheral configurations, or branch to application code. This is up to the application requirements.
I. If the application has not branched to application code, the BootROM will continue after completing IoRestore. It will disable I/O isolation
automatically if it was not taken care of inside of IoRestore.
J. BootROM will then boot as determined by the HIBBOOTMODE register. Refer to the ROM Code and Peripheral Booting chapter of the
TMS320F2837xS Microcontrollers Technical Reference Manual for more information.
Figure 7-20. HIBERNATE Entry and Exit Timing Diagram
Note
1. If the IORESTOREADDR is configured as the default value, the BootROM will continue its
execution to boot as determined by the HIBBOOTMODE register. Refer to the ROM Code and
Peripheral Booting chapter of the TMS320F2837xS Microcontrollers Technical Reference Manual
for more information.
2. The user may choose to disable I/O Isolation at any point in the IoRestore function. Regardless if
the user has disabled Isolation in the IoRestore function or if IoRestore is not defined, the
BootROM will automatically disable isolation before booting as determined by the HIBBOOTMODE
register.
7.9.9 External Memory Interface (EMIF)
The EMIF provides a means of connecting the CPU to various external storage devices like asynchronous
memories (SRAM, NOR flash) or synchronous memory (SDRAM).
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7.9.9.1 Asynchronous Memory Support
The EMIF supports asynchronous memories:
• SRAMs
• NOR Flash memories
There is an external wait input that allows slower asynchronous memories to extend the memory access. The
EMIF module supports up to three chip selects ( EMIF_CS[4:2]). Each chip select has the following individually
programmable attributes:
• Data bus width
• Read cycle timings: setup, hold, strobe
• Write cycle timings: setup, hold, strobe
• Bus turnaround time
• Extended wait option with programmable time-out
• Select strobe option
7.9.9.2 Synchronous DRAM Support
The EMIF memory controller is compliant with the JESD21-C SDR SDRAMs that use a 32-bit or 16-bit data bus.
The EMIF has a single SDRAM chip select ( EMIF_CS[0]).
The address space of the EMIF, for the synchronous memory (SDRAM), lies beyond the 22-bit range of the
program address bus and can only be accessed through the data bus, which places a restriction on the C
compiler being able to work effectively on data in this space. Therefore, when using SDRAM, the user is advised
to copy data (using the DMA) from external memory to RAM before working on it. See the examples in
C2000Ware (C2000Ware for C2000 MCUs ) and the TMS320F2837xS Microcontrollers Technical Reference
Manual .
SDRAM configurations supported are:
• One-bank, two-bank, and four-bank SDRAM devices
• Devices with 8-, 9-, 10-, and 11-column addresses
• CAS latency of two or three clock cycles
• 16-bit/32-bit data bus width
• 3.3-V LVCMOS interface
Additionally, the EMIF supports placing the SDRAM in self-refresh and power-down modes. Self-refresh mode
allows the SDRAM to be put in a low-power state while still retaining memory contents because the SDRAM will
continue to refresh itself even without clocks from the microcontroller. Power-down mode achieves even lower
power, except the microcontroller must periodically wake up and issue refreshes if data retention is required. The
EMIF module does not support mobile SDRAM devices.
On this device, the EMIF does not support burst access for SDRAM configurations. This means every access to
an external SDRAM device will have CAS latency.
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I TEXAS INSTRUMENTS
7.9.9.3 EMIF Electrical Data and Timing
7.9.9.3.1 Asynchronous RAM
Section 7.9.9.3.1.1 shows the EMIF asynchronous memory timing requirements. Section 7.9.9.3.1.2 shows the
EMIF asynchronous memory switching characteristics. Figure 7-21 through Figure 7-24 show the EMIF
asynchronous memory timing diagrams.
7.9.9.3.1.1 EMIF Asynchronous Memory Timing Requirements
NO.(1) MIN MAX UNIT
Reads and Writes
E EMIF clock period tc(SYSCLK) ns
2 tw(EM_WAIT) Pulse duration, EMxWAIT assertion and
deassertion 2E ns
Reads
12 tsu(EMDV-EMOEH) Setup time, EMxD[y:0] valid before EMxOE high 15 ns
13 th(EMOEH-EMDIV) Hold time, EMxD[y:0] valid after EMxOE high 0 ns
14 tsu(EMOEL-EMWAIT) Setup Time, EMxWAIT asserted before end of
Strobe Phase(2) 4E+20 ns
Writes
28 tsu(EMWEL-EMWAIT) Setup Time, EMxWAIT asserted before end of
Strobe Phase(2) 4E+20 ns
(1) E = EMxCLK period in ns.
(2) Setup before end of STROBE phase (if no extended wait states are inserted) by which EMxWAIT must be asserted to add extended
wait states. Figure 7-22 and Figure 7-24 describe EMIF transactions that include extended wait states inserted during the STROBE
phase. However, cycles inserted as part of this extended wait period should not be counted; the 4E requirement is to the start of where
the HOLD phase would begin if there were no extended wait cycles.
7.9.9.3.1.2 EMIF Asynchronous Memory Switching Characteristics
NO.(1)
(2) (3) PARAMETER MIN MAX UNIT
Reads and Writes
1 td(TURNAROUND) Turn around time (TA)*E–3 (TA)*E+2 ns
Reads
3 tc(EMRCYCLE)
EMIF read cycle time (EW = 0) (RS+RST+RH)*E–3 (RS+RST+RH)*E+2 ns
EMIF read cycle time (EW = 1) (RS+RST+RH+
(EWC*16))*E–3
(RS+RST+RH+
(EWC*16))*E+2 ns
4 tsu(EMCEL-EMOEL)
Output setup time, EMxCS[y:2] low
to EMxOE low (SS = 0) (RS)*E–3 (RS)*E+2 ns
Output setup time, EMxCS[y:2] low
to EMxOE low (SS = 1) –3 2 ns
5 th(EMOEH-EMCEH)
Output hold time, EMxOE high to
EMxCS[y:2] high (SS = 0) (RH)*E–3 (RH)*E ns
Output hold time, EMxOE high to
EMxCS[y:2] high (SS = 1) –3 0 ns
6 tsu(EMBAV-EMOEL) Output setup time, EMxBA[y:0]
valid to EMxOE low (RS)*E–3 (RS)*E+2 ns
7 th(EMOEH-EMBAIV) Output hold time, EMxOE high to
EMxBA[y:0] invalid (RH)*E–3 (RH)*E ns
8 tsu(EMAV-EMOEL) Output setup time, EMxA[y:0] valid
to EMxOE low (RS)*E–3 (RS)*E+2 ns
9 th(EMOEH-EMAIV) Output hold time, EMxOE high to
EMxA[y:0] invalid (RH)*E–3 (RH)*E ns
TMS320F28379S, TMS320F28378S, TMS320F28377S, TMS320F28377S-Q1
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TEXAS INSTRUMENTS
NO.(1)
(2) (3) PARAMETER MIN MAX UNIT
10 tw(EMOEL)
EMxOE active low width (EW = 0) (RST)*E–1 (RST)*E+1 ns
EMxOE active low width (EW = 1) (RST+(EWC*16))*E–1 (RST+(EWC*16))*E+1 ns
11 td(EMWAITH-EMOEH) Delay time from EMxWAIT
deasserted to EMxOE high 4E+10 5E+15 ns
29 tsu(EMDQMV-EMOEL) Output setup time, EMxDQM[y:0]
valid to EMxOE low (RS)*E–3 (RS)*E+2 ns
30 th(EMOEH-EMDQMIV) Output hold time, EMxOE high to
EMxDQM[y:0] invalid (RH)*E–3 (RH)*E ns
Writes
15 tc(EMWCYCLE)
EMIF write cycle time (EW = 0) (WS+WST+WH)*E–3 (WS+WST+WH)*E+1 ns
EMIF write cycle time (EW = 1) (WS+WST+WH+
(EWC*16))*E–3
(WS+WST+WH+
(EWC*16))*E+1 ns
16 tsu(EMCEL-EMWEL)
Output setup time, EMxCS[y:2] low
to EMxWE low (SS = 0) (WS)*E–3 (WS)*E+1 ns
Output setup time, EMxCS[y:2] low
to EMxWE low (SS = 1) –3 1 ns
17 th(EMWEH-EMCEH)
Output hold time, EMxWE high to
EMxCS[y:2] high (SS = 0) (WH)*E–3 (WH)*E ns
Output hold time, EMxWE high to
EMxCS[y:2] high (SS = 1) –3 0 ns
18 tsu(EMDQMV-EMWEL) Output setup time, EMxDQM[y:0]
valid to EMxWE low (WS)*E–3 (WS)*E+1 ns
19 th(EMWEH-EMDQMIV) Output hold time, EMxWE high to
EMxDQM[y:0] invalid (WH)*E–3 (WH)*E ns
20 tsu(EMBAV-EMWEL) Output setup time, EMxBA[y:0]
valid to EMxWE low (WS)*E–3 (WS)*E+1 ns
21 th(EMWEH-EMBAIV) Output hold time, EMxWE high to
EMxBA[y:0] invalid (WH)*E–3 (WH)*E ns
22 tsu(EMAV-EMWEL) Output setup time, EMxA[y:0] valid
to EMxWE low (WS)*E–3 (WS)*E+1 ns
23 th(EMWEH-EMAIV) Output hold time, EMxWE high to
EMxA[y:0] invalid (WH)*E–3 (WH)*E ns
24 tw(EMWEL)
EMxWE active low width
(EW = 0) (WST)*E–1 (WST)*E+1 ns
EMxWE active low width
(EW = 1) (WST+(EWC*16))*E–1 (WST+(EWC*16))*E+1 ns
25 td(EMWAITH-EMWEH) Delay time from EMxWAIT
deasserted to EMxWE high 4E+10 5E+15 ns
26 tsu(EMDV-EMWEL) Output setup time, EMxD[y:0] valid
to EMxWE low (WS)*E–3 (WS)*E+1 ns
27 th(EMWEH-EMDIV) Output hold time, EMxWE high to
EMxD[y:0] invalid (WH)*E–3 (WH)*E ns
(1) TA = Turn around, RS = Read setup, RST = Read strobe, RH = Read hold, WS = Write setup, WST = Write strobe, WH = Write hold,
MEWC = Maximum external wait cycles. These parameters are programmed through the Asynchronous Bank and Asynchronous Wait
Cycle Configuration Registers. These support the following ranges of values: TA[4–1], RS[16–1], RST[64–4], RH[8–1], WS[16–1],
WST[64–1], WH[8–1], and MEWC[1–256]. See the TMS320F2837xS Microcontrollers Technical Reference Manual for more
information.
(2) E = EMxCLK period in ns.
(3) EWC = external wait cycles determined by EMxWAIT input signal. EWC supports the following range of values. EWC[256–1]. The
maximum wait time before time-out is specified by bit field MEWC in the Asynchronous Wait Cycle Configuration Register. See the
TMS320F2837xS Microcontrollers Technical Reference Manual for more information.
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fl TEXAS INSTRUMENTS #1311: 1 1 1:1: EMxWE
EMxCS[y:2]
EMxBA[y:0]
13
12
EMxA[y:0]
EMxOE
EMxD[y:0]
EMxWE
10
5
9
7
4
8
6
3
1
EMxDQM[y:0]
30
29
Figure 7-21. Asynchronous Memory Read Timing
11
Asserted Deasserted
2
2
EMxWAIT
SETUP Extended Due to EMxWAIT STROBE HOLD
14
STROBE
EMxCS[y:2]
EMxBA[y:0]
EMxA[y:0]
EMxOE
EMxD[y:0]
Figure 7-22. EMxWAIT Read Timing Requirements
TMS320F28379S, TMS320F28378S, TMS320F28377S, TMS320F28377S-Q1
TMS320F28376S, TMS320F28375S, TMS320F28375S-Q1, TMS320F28374S
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{5‘ TEXAS INSTRUMENTS
15
1
16
18
20
22 24
17
19
21
23
26
27
EMxCS[y:2]
EMxBA[y:0]
EMxA[y:0]
EMxOE
EMxD[y:0]
EMxWE
EMxDQM[y:0]
Figure 7-23. Asynchronous Memory Write Timing
25
Asserted
2
2
EMxWAIT
SETUP Extended Due to EMxWAIT
28
Deasserted
STROBE STROBE HOLD
EMxCS[y:2]
EMxBA[y:0]
EMxA[y:0]
EMxD[y:0]
EMxWE
Figure 7-24. EMxWAIT Write Timing Requirements
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TEXAS INSTRUMENTS
7.9.9.3.2 Synchronous RAM
Section 7.9.9.3.2.1 shows the EMIF synchronous memory timing requirements. Section 7.9.9.3.2.2 shows the
EMIF synchronous memory switching characteristics. Figure 7-25 and Figure 7-26 show the synchronous
memory timing diagrams.
7.9.9.3.2.1 EMIF Synchronous Memory Timing Requirements
NO. MIN MAX UNIT
19 tsu(EMIFDV-EM_CLKH) Input setup time, read data valid on EMxD[y:0] before EMxCLK rising 2 ns
20 th(CLKH-DIV) Input hold time, read data valid on EMxD[y:0] after EMxCLK rising 1.5 ns
7.9.9.3.2.2 EMIF Synchronous Memory Switching Characteristics
NO. PARAMETER MIN MAX UNIT
1 tc(CLK) Cycle time, EMIF clock EMxCLK 10 ns
2 tw(CLK) Pulse width, EMIF clock EMxCLK high or low 3 ns
3 td(CLKH-CSV) Delay time, EMxCLK rising to EMxCS[y:2] valid 8 ns
4 toh(CLKH-CSIV) Output hold time, EMxCLK rising to EMxCS[y:2] invalid 1 ns
5 td(CLKH-DQMV) Delay time, EMxCLK rising to EMxDQM[y:0] valid 8 ns
6 toh(CLKH-DQMIV) Output hold time, EMxCLK rising to EMxDQM[y:0] invalid 1 ns
7 td(CLKH-AV) Delay time, EMxCLK rising to EMxA[y:0] and EMxBA[y:0] valid 8 ns
8 toh(CLKH-AIV) Output hold time, EMxCLK rising to EMxA[y:0] and EMxBA[y:0] invalid 1 ns
9 td(CLKH-DV) Delay time, EMxCLK rising to EMxD[y:0] valid 8 ns
10 toh(CLKH-DIV) Output hold time, EMxCLK rising to EMxD[y:0] invalid 1 ns
11 td(CLKH-RASV) Delay time, EMxCLK rising to EMxRAS valid 8 ns
12 toh(CLKH-RASIV) Output hold time, EMxCLK rising to EMxRAS invalid 1 ns
13 td(CLKH-CASV) Delay time, EMxCLK rising to EMxCAS valid 8 ns
14 toh(CLKH-CASIV) Output hold time, EMxCLK rising to EMxCAS invalid 1 ns
15 td(CLKH-WEV) Delay time, EMxCLK rising to EMxWE valid 8 ns
16 toh(CLKH-WEIV) Output hold time, EMxCLK rising to EMxWE invalid 1 ns
17 td(CLKH-DHZ) Delay time, EMxCLK rising to EMxD[y:0] tri-stated 8 ns
18 toh(CLKH-DLZ) Output hold time, EMxCLK rising to EMxD[y:0] driving 1 ns
TMS320F28379S, TMS320F28378S, TMS320F28377S, TMS320F28377S-Q1
TMS320F28376S, TMS320F28375S, TMS320F28375S-Q1, TMS320F28374S
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{a} TEXAS INSTRUMENTS
EMxCLK
1
2 2
4
6
8
8
12
14
19
20
3
5
7
7
11
13
17 18
2 EM_CLK Delay
BASIC SDRAM
READ OPERATION
EMxRAS
EMxCAS
EMxCS[y:2]
EMxBA[y:0]
EMxA[y:0]
EMxD[y:0]
EMxWE
EMxDQM[y:0]
Figure 7-25. Basic SDRAM Read Operation
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{j TEXAS INSTRUMENTS
EMxCLK
1
2 2
4
6
8
8
12
10
16
3
5
7
7
11
13
15
9
BASIC SDRAM
WRITE OPERATION
EMxRAS
EMxCAS
EMxCS[y:2]
EMxBA[y:0]
EMxA[y:0]
EMxD[y:0]
EMxWE
EMxDQM[y:0]
Figure 7-26. Basic SDRAM Write Operation
TMS320F28379S, TMS320F28378S, TMS320F28377S, TMS320F28377S-Q1
TMS320F28376S, TMS320F28375S, TMS320F28375S-Q1, TMS320F28374S
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I TEXAS INSTRUMENTS
7.10 Analog Peripherals
The analog subsystem module is described in this section.
The analog modules on this device include the ADC, temperature sensor, buffered DAC, and CMPSS.
The analog subsystem has the following features:
• Flexible voltage references
– The ADCs are referenced to VREFHIx and VREFLOx pins.
• VREFHIx pin voltage must be driven in externally.
• The buffered DACs are referenced to VREFHIx and VSSA.
– Alternately, these DACs can be referenced to the VDAC pin and VSSA.
• The comparator DACs are referenced to VDDA and VSSA.
– Alternately, these DACs can be referenced to the VDAC pin and VSSA.
• Flexible pin usage
– Buffered DAC and comparator subsystem functions multiplexed with ADC inputs
• Internal connection to VREFLO on all ADCs for offset self-calibration
Figure 7-27 shows the Analog Subsystem Block Diagram for the 337-ball ZWT package. Figure 7-28 shows the
Analog Subsystem Block Diagram for the 176-pin PTP package. Figure 7-29 shows the Analog Subsystem
Block Diagram for the 100-pin PZP package.
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ADC-A
16-bits
or
12-bits
(selectable)
0
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
ADC-B
16-bits
or
12-bits
(selectable)
ADC-C
16-bits
or
12-bits
(selectable)
ADC-D
16-bits
or
12-bits
(selectable)
DACOUTA/ADCINA0
DACOUTB/ADCINA1
CMPIN1P/ADCINA2
CMPIN1N/ADCINA3
CMPIN4N/ADCIN15
TEMP SENSOR
VDAC/ADCINB0
DACOUTC/ADCINB1
CMPIN3P/ADCINB2
CMPIN3N/ADCINB3
CMPIN6P/ADCINC2
CMPIN6N/ADCINC3
CMPIN7P/ADCIND0
CMPIN7N/ADCIND1
CMPIN8P/ADCIND2
CMPIN8N/ADCIND3
12-bit
Buffered
DAC
CMPIN2P/ADCINA4
CMPIN2N/ADCINA5
ADCINB4
ADCINB5
CMPIN5P/ADCINC4
CMPIN5N/ADCINC5
ADCIND4
ADCIND5
VREFHIA
VREFLOB
REFHI VREFHIA
DACOUTADACOUTB
VREFLOC
VREFLOD
VREFLOB
VREFLOB
VDAC
0
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
0
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
0
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
VREFLOD
VREFLOD
VREFLOC
VREFLOC
VREFLOA
VREFLOA
CMPIN4P/ADCIN14
CMPIN1P
CMPIN3P
CMPIN2P
CMPIN4P
Comparator Subsystem 1
VDDA or VDAC
CMPIN1N
CTRIPOUT1H
Digital
Filter
CTRIP1H
CTRIP1L
CMPIN2N
CTRIP2L
CTRIP2H
CMPIN3N
CTRIPOUT3H
CTRIP3H
CTRIP3L
CMPIN4N
CTRIPOUT4H
CTRIP4H
CTRIP4L
Digital
Filter CTRIPOUT1L
CTRIPOUT2H
CTRIPOUT2L
CTRIPOUT3L
CTRIPOUT4L
CMPIN5P
CMPIN6P
CMPIN5N
CTRIPOUT5H
CTRIP5H
CTRIP5L
CMPIN6N
CTRIPOUT6H
CTRIP6H
CTRIP6L
CTRIPOUT5L
CTRIPOUT6L
CMPIN7P
CMPIN8P
CMPIN7N
CTRIPOUT7H
CTRIP7H
CTRIP7L
CMPIN8N
CTRIPOUT8H
CTRIP8H
CTRIP8L
CTRIPOUT7L
CTRIPOUT8L
12-bit
Buffered
DAC
VREFHIA VDAC
12-bit
Buffered
DAC
VREFHIB
DACOUTC
VDAC
REFHI
DAC12
DAC12
Comparator Subsystem 2
VDDA or VDAC
Digital
Filter
Digital
Filter
DAC12
DAC12
Comparator Subsystem 3
VDDA or VDAC
Digital
Filter
Digital
Filter
DAC12
DAC12
Comparator Subsystem 4
VDDA or VDAC
Digital
Filter
Digital
Filter
DAC12
DAC12
Comparator Subsystem 5
VDDA or VDAC
Digital
Filter
Digital
Filter
DAC12
DAC12
Comparator Subsystem 6
VDDA or VDAC
Digital
Filter
Digital
Filter
DAC12
DAC12
Comparator Subsystem 7
VDDA or VDAC
Digital
Filter
Digital
Filter
DAC12
DAC12
Comparator Subsystem 8
VDDA or VDAC
Digital
Filter
Digital
Filter
DAC12
DAC12
REFLO
VREFLOA
VREFHIB
REFLO
VREFHIC
VREFHID
REFHI
REFLO
REFHI
REFLO
VSSA
VSSA
VSSA
DACREFSEL
DACREFSEL
DACREFSEL
Figure 7-27. Analog Subsystem Block Diagram (337-Ball ZWT)
TMS320F28379S, TMS320F28378S, TMS320F28377S, TMS320F28377S-Q1
TMS320F28376S, TMS320F28375S, TMS320F28375S-Q1, TMS320F28374S
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l TEXAS INSTRUMENTS
ADC-A
16-bits
or
12-bits
(selectable)
0
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
ADC-B
16-bits
or
12-bits
(selectable)
ADC-D
16-bits
or
12-bits
(selectable)
DACOUTA/ADCINA0
DACOUTB/ADCINA1
CMPIN1P/ADCINA2
CMPIN1N/ADCINA3
CMPIN4N/ADCIN15
TEMP SENSOR
VDAC/ADCINB0
DACOUTC/ADCINB1
CMPIN3P/ADCINB2
CMPIN3N/ADCINB3
CMPIN7P/ADCIND0
CMPIN7N/ADCIND1
CMPIN8P/ADCIND2
CMPIN8N/ADCIND3
12-bit
Buffered
DAC
CMPIN2P/ADCINA4
CMPIN2N/ADCINA5
ADCIND4
VREFHIA
VREFLOB
REFHI VREFHIA
DACOUTA
DACOUTB
VREFLOD
VREFLOB
VREFLOB
VDAC
0
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
0
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
VREFLOD
VREFLOD
VREFLOA
VREFLOA
CMPIN4P/ADCIN14
CMPIN1P
CMPIN3P
CMPIN2P
CMPIN4P
Comparator Subsystem 1
VDDA or VDAC
CMPIN1N
CTRIPOUT1H
Digital
Filter
CTRIP1H
CTRIP1L
CMPIN2N
CTRIP2L
CTRIP2H
CMPIN3N
CTRIPOUT3H
CTRIP3H
CTRIP3L
CMPIN4N
CTRIPOUT4H
CTRIP4H
CTRIP4L
Digital
Filter CTRIPOUT1L
CTRIPOUT2H
CTRIPOUT2L
CTRIPOUT3L
CTRIPOUT4L
CMPIN5P
CMPIN6P
CTRIPOUT5H
CTRIP5H
CTRIP5L
CMPIN6N
CTRIPOUT6H
CTRIP6H
CTRIP6L
CTRIPOUT5L
CTRIPOUT6L
CMPIN7P
CMPIN8P
CMPIN7N
CTRIPOUT7H
CTRIP7H
CTRIP7L
CMPIN8N
CTRIPOUT8H
CTRIP8H
CTRIP8L
CTRIPOUT7L
CTRIPOUT8L
12-bit
Buffered
DAC
VREFHIA VDAC
12-bit
Buffered
DAC
VREFHIB
DACOUTC
VDAC
REFHI
DAC12
DAC12
Comparator Subsystem 2
VDDA or VDAC
Digital
Filter
Digital
Filter
DAC12
DAC12
Comparator Subsystem 3
VDDA or VDAC
Digital
Filter
Digital
Filter
DAC12
DAC12
Comparator Subsystem 4
VDDA or VDAC
Digital
Filter
Digital
Filter
DAC12
DAC12
Comparator Subsystem 5
VDDA or VDAC
Digital
Filter
Digital
Filter
DAC12
DAC12
Comparator Subsystem 6
VDDA or VDAC
Digital
Filter
Digital
Filter
DAC12
DAC12
Comparator Subsystem 7
VDDA or VDAC
Digital
Filter
Digital
Filter
DAC12
DAC12
Comparator Subsystem 8
VDDA or VDAC
Digital
Filter
Digital
Filter
DAC12
DAC12
REFLO
VREFLOA
VREFHIB
REFLO
VREFHID
REFHI
REFLO
VSSA
VSSA
VSSA
DACREFSEL
DACREFSEL
DACREFSEL
ADC-C
16-bits
or
12-bits
(selectable)
CMPIN6P/ADCINC2
CMPIN6N/ADCINC3
CMPIN5P/ADCINC4
VREFLOC
0
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
VREFLOC
VREFLOC
VREFHIC
REFHI
REFLO
Figure 7-28. Analog Subsystem Block Diagram (176-Pin PTP)
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{j TEXAS INSTRUMENTS BEE
ADC-A
12-bits
0
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
ADC-B
12-bits
DACOUTA/ADCINA0
DACOUTB/ADCINA1
CMPIN1P/ADCINA2
CMPIN1N/ADCINA3
CMPIN4N/ADCIN15
TEMP SENSOR
VDAC/ADCINB0
DACOUTC/ADCINB1
CMPIN3P/ADCINB2
CMPIN3N/ADCINB3
12-bit
Buffered
DAC
CMPIN2P/ADCINA4
CMPIN2N/ADCINA5
ADCINB4
ADCINB5
VREFHIA
VREFLOB
REFHI VREFHIA
DACOUTA
DACOUTB
VREFLOB
VREFLOB
VDAC
0
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
VREFLOA
VREFLOA
CMPIN4P/ADCIN14
CMPIN1P
CMPIN3P
CMPIN2P
CMPIN4P
Comparator Subsystem 1
VDDA or VDAC
CMPIN1N
CTRIPOUT1H
Digital
Filter
CTRIP1H
CTRIP1L
CMPIN2N
CTRIP2L
CTRIP2H
CMPIN3N
CTRIPOUT3H
CTRIP3H
CTRIP3L
CMPIN4N
CTRIPOUT4H
CTRIP4H
CTRIP4L
Digital
Filter CTRIPOUT1L
CTRIPOUT2H
CTRIPOUT2L
CTRIPOUT3L
CTRIPOUT4L
12-bit
Buffered
DAC
VREFHIA VDAC
12-bit
Buffered
DAC
VREFHIB
DACOUTC
VDAC
REFHI
DAC12
DAC12
Comparator Subsystem 2
VDDA or VDAC
Digital
Filter
Digital
Filter
DAC12
DAC12
Comparator Subsystem 3
VDDA or VDAC
Digital
Filter
Digital
Filter
DAC12
DAC12
Comparator Subsystem 4
VDDA or VDAC
Digital
Filter
Digital
Filter
DAC12
DAC12
REFLO
VREFLOA
VREFHIB
REFLO
VSSA
DACREFSEL
DACREFSEL
DACREFSEL
VSSA
VSSA
Figure 7-29. Analog Subsystem Block Diagram (100-Pin PZP)
TMS320F28379S, TMS320F28378S, TMS320F28377S, TMS320F28377S-Q1
TMS320F28376S, TMS320F28375S, TMS320F28375S-Q1, TMS320F28374S
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7.10.1 Analog-to-Digital Converter (ADC)
The ADCs on this device are successive approximation (SAR) style ADCs with selectable resolution of either
16 bits or 12 bits. There are multiple ADC modules which allow simultaneous sampling. The ADC wrapper is
start-of-conversion (SOC) based [see the SOC Principle of Operation section of the TMS320F2837xS
Microcontrollers Technical Reference Manual .
Each ADC has the following features:
• Selectable resolution of 16 bits or 12 bits
• Ratiometric external reference set by VREFHI and VREFLO
• Differential signal conversions (16-bit mode only)
• Single-ended signal conversions (12-bit mode only)
• Input multiplexer with up to 16 channels (single-ended) or 8 channels (differential)
• 16 configurable SOCs
• 16 individually addressable result registers
• Multiple trigger sources
– Software immediate start
– All ePWMs
– GPIO XINT2
– CPU timers
– ADCINT1 or 2
• Four flexible PIE interrupts
• Burst mode
• Four post-processing blocks, each with:
– Saturating offset calibration
– Error from setpoint calculation
– High, low, and zero-crossing compare, with interrupt and ePWM trip capability
– Trigger-to-sample delay capture
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Figure 7-30 shows the ADC module block diagram.
Analog to Digital Wrapper LogicAnalog to Digital Core
Input Circuit
Reference Voltage Levels
SOC
Arbitration
& Control
SOCx (0-15)
ADCIN0
Converter
ADCIN1
ADCIN2
ADCIN3
ADCIN4
ADCIN5
ADCIN6
ADCIN7
Interrupt Block (1-4)
Triggers
ADCIN8
ADCIN9
ADCIN10
ADCIN11
0
1
2
3
4
5
6
7
8
9
10
11
VREFLO
VREFHI
CHSEL
ADCSOC
[15:0]
ADCINT1-4
14
15
12
13
ADCIN12
ADCIN13
ADCIN14
ADCIN15
TRIGSEL
ACQPS
CHSEL
RESOLUTION
SIGNALMODE
Post Processing Block (1-4)
[15:0]
SIGNALMODE
RESOLUTION
RESULT
ADCRESULT
0–15 Regs
ADCPPBxRESULT
Event
Logic ADCEVTINT
[15:0]
...
...
ADCEVT
TRIGGER[15:0]
Trigger
Timestamp
SOC Delay
Timestamp
ADCCOUNTER
ADCPPBxOFFCAL
ADCPPBxOFFREF
S
+-
saturate
S
+-
SOCxSTART[15:0]
EOCx[15:0]
CONFIG
u1
x2
x1
S/H Circuit
VIN+
VIN-
DOUT
Figure 7-30. ADC Module Block Diagram
7.10.1.1 ADC Configurability
Some ADC configurations are individually controlled by the SOCs, while others are controlled by each ADC
module. Table 7-7 summarizes the basic ADC options and their level of configurability.
Table 7-7. ADC Options and Configuration Levels
OPTIONS CONFIGURABILITY
Clock By the module(1)
Resolution By the module(1)
Signal mode By the module
Reference voltage source Not configurable (external reference only)
Trigger source By the SOC(1)
Converted channel By the SOC
Acquisition window duration By the SOC(1)
EOC location By the module
Burst mode By the module(1)
(1) Writing these values differently to different ADC modules could cause the ADCs to operate
asynchronously. For guidance on when the ADCs are operating synchronously or asynchronously,
see the Ensuring Synchronous Operation section of the Analog-to-Digital Converter (ADC) chapter
in the TMS320F2837xS Microcontrollers Technical Reference Manual .
TMS320F28379S, TMS320F28378S, TMS320F28377S, TMS320F28377S-Q1
TMS320F28376S, TMS320F28375S, TMS320F28375S-Q1, TMS320F28374S
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7.10.1.1.1 Signal Mode
The ADC supports two signal modes: single-ended and differential. In single-ended mode, the input voltage to
the converter is sampled through a single pin (ADCINx), referenced to VREFLO. In differential signaling mode,
the input voltage to the converter is sampled through a pair of input pins, one of which is the positive input
(ADCINxP) and the other is the negative input (ADCINxN). The actual input voltage is the difference between the
two (ADCINxP – ADCINxN). Figure 7-31 shows the differential signaling mode. Figure 7-32 shows the single-
ended signaling mode.
VREFHI
VREFLO
(VSSA)
VREFHI/2
Pin Voltages
ADCINxP
ADCINxN
ADC
ADCINxN
ADCINxP
VREFLO
VREFHI
VREFHI
VREFLO
(VSSA)
Input Common Mode
VREFHI/2 ± 50mVVin Common Mode
+VREFHI
-VREFHI
0
Effective Input Voltage
ADC Vin
2n - 1
0
Digital Output
ADC Vin
Figure 7-31. Differential Signaling Mode
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VREFHI
VREFLO
(VSSA)
VREFHI/2
Pin Voltage
ADCINx
ADC
ADCINx
VREFLO
VREFHI
2n - 1
0
Digital Output
ADC Vin
Figure 7-32. Single-ended Signaling Mode
TMS320F28379S, TMS320F28378S, TMS320F28377S, TMS320F28377S-Q1
TMS320F28376S, TMS320F28375S, TMS320F28375S-Q1, TMS320F28374S
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I TEXAS INSTRUMENTS
7.10.1.2 ADC Electrical Data and Timing
Section 7.10.1.2.1 shows the ADC operating conditions for 16-bit differential mode. Section 7.10.1.2.2 shows the
ADC characteristics for 16-bit differential mode. Section 7.10.1.2.3 shows the ADC operating conditions for 12-
bit single-ended mode. Section 7.10.1.2.4 shows the ADC characteristics for 12-bit single-ended mode. Section
7.10.1.2.5 shows the ADCEXTSOC timing requirements.
7.10.1.2.1 ADC Operating Conditions (16-Bit Differential Mode)
over recommended operating conditions (unless otherwise noted)
MIN TYP MAX UNIT
ADCCLK (derived from PERx.SYSCLK) 5 50 MHz
Sample window duration (set by ACQPS and PERx.SYSCLK)(1) 320 ns
VREFHI 2.4 2.5 or 3.0 VDDA V
VREFLO VSSA 0 VSSA V
VREFHI – VREFLO 2.4 VDDA V
ADC input conversion range VREFLO VREFHI V
ADC input signal common mode voltage(2) (3) VREFCM – 50 VREFCM VREFCM + 50 mV
(1) The sample window must also be at least as long as 1 ADCCLK cycle for correct ADC operation.
(2) VREFCM = (VREFHI + VREFLO)/2
(3) The VREFCM requirements will not be met if the negative ADC input pin is connected to VSSA or VREFLO.
Note
The ADC inputs should be kept below VDDA + 0.3 V during operation. If an ADC input exceeds this
level, the VREF internal to the device may be disturbed, which can impact results for other ADC or
DAC inputs using the same VREF.
Note
The VREFHI pin must be kept below VDDA + 0.3 V to ensure proper functional operation. If the VREFHI
pin exceeds this level, a blocking circuit may activate, and the internal value of VREFHI may float to 0 V
internally, giving improper ADC conversion or DAC output.
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I TEXAS INSTRUMENTS
7.10.1.2.2 ADC Characteristics (16-Bit Differential Mode)
over recommended operating conditions (unless otherwise noted)(6)
PARAMETER TEST CONDITIONS MIN TYP MAX UNIT
ADC conversion cycles(1) 29.6 31 ADCCLKs
Power-up time (after setting
ADCPWDNZ to first conversion) 500 µs
Gain error –64 ±9 64 LSBs
Offset error(2) –16 ±9 16 LSBs
Channel-to-channel gain error ±6 LSBs
Channel-to-channel offset error ±3 LSBs
ADC-to-ADC gain error Identical VREFHI and VREFLO for all ADCs ±6 LSBs
ADC-to-ADC offset error Identical VREFHI and VREFLO for all ADCs ±3 LSBs
DNL(3) > –1 ±0.5 1 LSBs
INL –3 ±1.5 3 LSBs
SNR(4) (11) VREFHI = 2.5 V, fin = 10 kHz 87.6 dB
THD(4) (11) VREFHI = 2.5 V, fin = 10 kHz –93.5 dB
SFDR(4) (11) VREFHI = 2.5 V, fin = 10 kHz 95.4 dB
SINAD(4) (11) VREFHI = 2.5 V, fin = 10 kHz 86.6 dB
ENOB(4) (11)
VREFHI = 2.5 V, fin = 10 kHz,
single ADC(7) 14.1
bits
VREFHI = 2.5 V, fin = 10 kHz,
synchronous ADCs(8) 14.1
VREFHI = 2.5 V, fin = 10 kHz,
asynchronous ADCs(9) Not
supported
PSRR VDDA = 3.3-V DC + 200 mV
DC up to Sine at 1 kHz 77 dB
PSRR VDDA = 3.3-V DC + 200 mV
Sine at 800 kHz 74 dB
CMRR DC to 1 MHz 60 dB
VREFHI input current 190 µA
ADC-to-ADC isolation(11) (5) (10)
VREFHI = 2.5 V, synchronous ADCs(8) –2 2
LSBs
VREFHI = 2.5 V, asynchronous ADCs(9) Not
supported
(1) See Section 7.10.1.2.7.
(2) Difference from conversion result 32768 when ADCINp = ADCINn = VREFCM.
(3) No missing codes.
(4) AC parameters will be impacted by clock source accuracy and jitter, this should be taken into account when selecting the clock source
for the system. The clock source used for these parameters was a high-accuracy external clock fed through the PLL. The on-chip
Internal Oscillator has higher jitter than an external crystal and these parameters will degrade if it is used as a clock source.
(5) Maximum DC code deviation due to operation of multiple ADCs simultaneously.
(6) Typical values are measured with VREFHI = 2.5 V and VREFLO = 0 V. Minimum and Maximum values are tested or characterized with
VREFHI = 2.5 V and VREFLO = 0 V.
(7) One ADC operating while all other ADCs are idle.
(8) All ADCs operating with identical ADCCLK, S+H durations, triggers, and resolution.
(9) Any ADCs operating with heterogeneous ADCCLK, S+H durations, triggers, or resolution.
(10) Value based on characterization.
(11) I/O activity is minimized on pins adjacent to ADC input and VREFHI pins as part of best practices to reduce capacitive coupling and
crosstalk.
TMS320F28379S, TMS320F28378S, TMS320F28377S, TMS320F28377S-Q1
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7.10.1.2.3 ADC Operating Conditions (12-Bit Single-Ended Mode)
over recommended operating conditions (unless otherwise noted)
MIN TYP MAX UNIT
ADCCLK (derived from PERx.SYSCLK) 5 50 MHz
Sample window duration (set by ACQPS and PERx.SYSCLK)(1) 75 ns
VREFHI 2.4 2.5 or 3.0 VDDA V
VREFLO VSSA 0 VSSA V
VREFHI – VREFLO 2.4 VDDA V
ADC input conversion range VREFLO VREFHI V
(1) The sample window must also be at least as long as 1 ADCCLK cycle for correct ADC operation.
Note
The ADC inputs should be kept below VDDA + 0.3 V during operation. If an ADC input exceeds this
level, the VREF internal to the device may be disturbed, which can impact results for other ADC or
DAC inputs using the same VREF.
Note
The VREFHI pin must be kept below VDDA + 0.3 V to ensure proper functional operation. If the VREFHI
pin exceeds this level, a blocking circuit may activate, and the internal value of VREFHI may float to 0 V
internally, giving improper ADC conversion or DAC output.
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7.10.1.2.4 ADC Characteristics (12-Bit Single-Ended Mode)
over recommended operating conditions (unless otherwise noted)(5)
PARAMETER TEST CONDITIONS MIN TYP MAX UNIT
ADC conversion cycles(1) 10.1 11 ADCCLKs
Power-up time 500 µs
Gain error –5 ±3 5 LSBs
Offset error –4 ±2 4 LSBs
Channel-to-channel gain error ±4 LSBs
Channel-to-channel offset error ±2 LSBs
ADC-to-ADC gain error Identical VREFHI and VREFLO for all ADCs ±4 LSBs
ADC-to-ADC offset error Identical VREFHI and VREFLO for all ADCs ±2 LSBs
DNL(2) > –1 ±0.5 1 LSBs
INL –2 ±1.0 2 LSBs
SNR(3) (10) VREFHI = 2.5 V, fin = 100 kHz 68.8 dB
THD(3) (10) VREFHI = 2.5 V, fin = 100 kHz –78.4 dB
SFDR(3) (10) VREFHI = 2.5 V, fin = 100 kHz 79.2 dB
SINAD(3) (10) VREFHI = 2.5 V, fin = 100 kHz 68.4 dB
ENOB(3) (10)
VREFHI = 2.5 V, fin = 100 kHz,
single ADC(6), all packages 11.1
bits
VREFHI = 2.5 V, fin = 100 kHz,
synchronous ADCs(7), all packages 11.1
VREFHI = 2.5 V, fin = 100 kHz,
asynchronous ADCs(8),
100-pin PZP package
Not
supported
VREFHI = 2.5 V, fin = 100 kHz,
asynchronous ADCs(8),
176-pin PTP package
9.7
VREFHI = 2.5 V, fin = 100 kHz,
asynchronous ADCs(8),
337-ball ZWT package
10.9
PSRR VDDA = 3.3-V DC + 200 mV
DC up to Sine at 1 kHz 60 dB
PSRR VDDA = 3.3-V DC + 200 mV
Sine at 800 kHz 57 dB
ADC-to-ADC isolation(10) (4) (9)
VREFHI = 2.5 V, synchronous ADCs(7), all
packages –1 1
LSBs
VREFHI = 2.5 V, asynchronous ADCs(8),
100-pin PZP package
Not
supported
VREFHI = 2.5 V, asynchronous ADCs(8),
176-pin PTP package –9 9
VREFHI = 2.5 V, asynchronous ADCs(8),
337-ball ZWT package –2 2
VREFHI input current 130 µA
(1) See Section 7.10.1.2.7.
(2) No missing codes.
(3) AC parameters will be impacted by clock source accuracy and jitter, this should be taken into account when selecting the clock source
for the system. The clock source used for these parameters was a high-accuracy external clock fed through the PLL. The on-chip
Internal Oscillator has higher jitter than an external crystal and these parameters will degrade if it is used as a clock source.
(4) Maximum DC code deviation due to operation of multiple ADCs simultaneously.
(5) Typical values are measured with VREFHI = 2.5 V and VREFLO = 0 V. Minimum and Maximum values are tested or characterized with
VREFHI = 2.5 V and VREFLO = 0 V.
(6) One ADC operating while all other ADCs are idle.
(7) All ADCs operating with identical ADCCLK, S+H durations, triggers, and resolution.
TMS320F28379S, TMS320F28378S, TMS320F28377S, TMS320F28377S-Q1
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I TEXAS INSTRUMENTS
(8) Any ADCs operating with heterogeneous ADCCLK, S+H durations, triggers, or resolution.
(9) Value based on characterization.
(10) I/O activity is minimized on pins adjacent to ADC input and VREFHI pins as part of best practices to reduce capacitive coupling and
crosstalk.
7.10.1.2.5 ADCEXTSOC Timing Requirements
MIN(1) MAX UNIT
tw(INT) Pulse duration, INT input low/high Synchronous 2tc(SYSCLK) cycles
With qualifier tw(IQSW) + tw(SP) + 1tc(SYSCLK) cycles
(1) For an explanation of the input qualifier parameters, see Section 7.9.6.2.1.
7.10.1.2.6 ADC Input Models
Note
ADC channels ADCINA0, ADCINA1, and ADCINB1 have a 50-kΩ pulldown resistor to VSSA.
For differential operation, the ADC input characteristics are given by Section 7.10.1.2.6.1 and Figure 7-33.
7.10.1.2.6.1 Differential Input Model Parameters
DESCRIPTION VALUE (16-BIT MODE)
CpParasitic input capacitance See Table 7-8
Ron Sampling switch resistance 700 Ω
ChSampling capacitor 16.5 pF
RsNominal source impedance 50 Ω
ADC
Ron
Switch
ADCINxN
Ch
Cp
ADCINxP
AC
Rs
Ron
Switch
Rs
Cp
VSSA
Figure 7-33. Differential Input Model
For single-ended operation, the ADC input characteristics are given by Section 7.10.1.2.6.2 Figure 7-34and .
7.10.1.2.6.2 Single-Ended Input Model Parameters
DESCRIPTION VALUE (12-BIT MODE)
CpParasitic input capacitance See Table 7-8
Ron Sampling switch resistance 425 Ω
ChSampling capacitor 14.5 pF
RsNominal source impedance 50 Ω
ADC
Ron
Switch
VREFLO
Ch
Cp
ADCINx
AC
Rs
Figure 7-34. Single-Ended Input Model
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Table 7-8shows the parasitic capacitance on each channel. Also, enabling a comparator adds approximately
1.4 pF of capacitance on positive comparator inputs and 2.5 pF of capacitance on negative comparator inputs.
Table 7-8. Per-Channel Parasitic Capacitance
ADC CHANNEL Cp (pF)
COMPARATOR DISABLED COMPARATOR ENABLED
ADCINA0 12.9 N/A
ADCINA1 10.3 N/A
ADCINA2 5.9 7.3
ADCINA3 6.3 8.8
ADCINA4 5.9 7.3
ADCINA5 6.3 8.8
ADCINB01117.0 N/A
ADCINB1 10.6 N/A
ADCINB2 5.9 7.3
ADCINB3 6.2 8.7
ADCINB4 5.2 N/A
ADCINB5 5.1 N/A
ADCINC2 5.5 6.9
ADCINC3 5.8 8.3
ADCINC4 5.0 6.4
ADCINC5 5.3 7.8
ADCIND0 5.3 6.7
ADCIND1 5.7 8.2
ADCIND2 5.3 6.7
ADCIND3 5.6 8.1
ADCIND4 4.3 N/A
ADCIND5 4.3 N/A
ADCIN14 8.6 10.0
ADCIN15 9.0 11.5
1. The increased capacitance is due to VDAC functionality.
These input models should be used along with actual signal source impedance to determine the acquisition
window duration. See the Choosing an Acquisition Window Duration section of the TMS320F2837xS
Microcontrollers Technical Reference Manual for more information.
The user should analyze the ADC input setting assuming worst-case initial conditions on Ch. This will require
assuming that Ch could start the S+H window completely charged to VREFHI or completely discharged to VREFLO.
When the ADC transitions from an odd-numbered channel to an even-numbered channel, or vice-versa, the
actual initial voltage on Ch will be close to being completely discharged to VREFLO. For even-to-even or odd-to-
odd channel transitions, the initial voltage on Ch will be close to the voltage of the previously converted channel.
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7.10.1.2.7 ADC Timing Diagrams
Section 7.10.1.2.7.1 lists the ADC timings in 12-bit mode (SYSCLK cycles). Section 7.10.1.2.7.2 lists the ADC
timings in 16-bit mode. Figure 7-35 and Figure 7-36 show the ADC conversion timings for two SOCs given the
following assumptions:
• SOC0 and SOC1 are configured to use the same trigger.
• No other SOCs are converting or pending when the trigger occurs.
• The round robin pointer is in a state that causes SOC0 to convert first.
• ADCINTSEL is configured to set an ADCINT flag upon end of conversion for SOC0 (whether this flag
propagates through to the CPU to cause an interrupt is determined by the configurations in the PIE module).
Table 7-9 lists the descriptions of the ADC timing parameters that are in Figure 7-35 and Figure 7-36 .
Table 7-9. ADC Timing Parameters
PARAMETER DESCRIPTION
tSH
The duration of the S+H window.
At the end of this window, the value on the S+H capacitor becomes the voltage to be converted into a digital
value. The duration is given by (ACQPS + 1) SYSCLK cycles. ACQPS can be configured individually for each
SOC, so tSH will not necessarily be the same for different SOCs.
Note: The value on the S+H capacitor will be captured approximately 5 ns before the end of the S+H window
regardless of device clock settings.
tLAT
The time from the end of the S+H window until the ADC conversion results latch in the ADCRESULTx register.
If the ADCRESULTx register is read before this time, the previous conversion results will be returned.
tEOC The time from the end of the S+H window until the next ADC conversion S+H window can begin. The
subsequent sample can start before the conversion results are latched.
tINT
The time from the end of the S+H window until an ADCINT flag is set (if configured).
If the INTPULSEPOS bit in the ADCCTL1 register is set, tINT will coincide with the conversion results being
latched into the result register.
If the INTPULSEPOS bit is 0, tINT will coincide with the end of the S+H window. If tINT triggers a read of the
ADC result register (directly through DMA or indirectly by triggering an ISR that reads the result), care must be
taken to ensure the read occurs after the results latch (otherwise, the previous results will be read).
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7.10.1.2.7.1 ADC Timings in 12-Bit Mode (SYSCLK Cycles)
ADCCLK PRESCALE SYSCLK CYCLES ADCCLK
CYCLES
ADCCTL2
[PRESCALE]
RATIO
ADCCLK:SYSCLK tEOC tLAT (1) tINT(EARLY) tINT(LATE) tEOC
0 1 11 13 1 11 11.0
1 1.5 Invalid
2 2 21 23 1 21 10.5
3 2.5 26 28 1 26 10.4
4 3 31 34 1 31 10.3
5 3.5 36 39 1 36 10.3
6 4 41 44 1 41 10.3
7 4.5 46 49 1 46 10.2
8 5 51 55 1 51 10.2
9 5.5 56 60 1 56 10.2
10 6 61 65 1 61 10.2
11 6.5 66 70 1 66 10.2
12 7 71 76 1 71 10.1
13 7.5 76 81 1 76 10.1
14 8 81 86 1 81 10.1
15 8.5 86 91 1 86 10.1
(1) Refer to the "ADC: DMA Read of Stale Result" advisory in the TMS320F2837xS MCUs Silicon Errata .
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SYSCLK
ADCTRIG
ADCSOCFLG.SOC0
ADCSOCFLG.SOC1
ADC S+H
ADCCLK
SOC0
Input on SOC0.CHSEL
Input on SOC1.CHSEL
ADCRESULT0
ADCRESULT1
ADCINTFLG.ADCINTx
SOC1
(old data)
(old data)
Sample n
Sample n+1
Sample n
Sample n+1
tSH tLAT
tEOC
tINT
Figure 7-35. ADC Timings for 12-Bit Mode
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7.10.1.2.7.2 ADC Timings in 16-Bit Mode
ADCCLK PRESCALE SYSCLK CYCLES ADCCLK
CYCLES
ADCCTL2
[PRESCALE]
RATIO
ADCCLK:SYSCLK tEOC tLAT (1) tINT(EARLY) tINT(LATE) tEOC
0 1 31 32 1 31 31.0
1 1.5 Invalid
2 2 60 61 1 60 30.0
3 2.5 75 75 1 75 30.0
4 3 90 91 1 90 30.0
5 3.5 104 106 1 104 29.7
6 4 119 120 1 119 29.8
7 4.5 134 134 1 134 29.8
8 5 149 150 1 149 29.8
9 5.5 163 165 1 163 29.6
10 6 178 179 1 178 29.7
11 6.5 193 193 1 193 29.7
12 7 208 209 1 208 29.7
13 7.5 222 224 1 222 29.6
14 8 237 238 1 237 29.6
15 8.5 252 252 1 252 29.6
(1) Refer to the "ADC: DMA Read of Stale Result" advisory in the TMS320F2837xS MCUs Silicon Errata .
TMS320F28379S, TMS320F28378S, TMS320F28377S, TMS320F28377S-Q1
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SYSCLK
ADCTRIG
ADCSOCFLG.SOC0
ADCSOCFLG.SOC1
ADC S+H
ADCCLK
SOC0
Input on SOC0.CHSEL
Input on SOC1.CHSEL
ADCRESULT0
ADCRESULT1
ADCINTFLG.ADCINTx
SOC1
(old data)
(old data)
Sample n
Sample n+1
Sample n
Sample n+1
tSH tLAT
tEOC
tINT
Figure 7-36. ADC Timings for 16-Bit Mode
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7.10.1.3 Temperature Sensor Electrical Data and Timing
The temperature sensor can be used to measure the device junction temperature. The temperature sensor is
sampled through an internal connection to the ADC and translated into a temperature through TI-provided
software. When sampling the temperature sensor, the ADC must meet the acquisition time in Section 7.10.1.3.1.
7.10.1.3.1 Temperature Sensor Electrical Characteristics
over recommended operating conditions (unless otherwise noted)
PARAMETER MIN TYP MAX UNIT
Temperature accuracy ±15 °C
Start-up time (TSNSCTL[ENABLE] to sampling temperature sensor) 500 µs
ADC acquisition time 700 ns
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l TEXAS INSTRUMENTS CTRIP1 H cTRIPolm H CTRIP1 L cTRIPolm L CTRIPZH CTRIPOUTZH CTRIPZL CTRIPOUTZL CTRIPBH cTRIPouTaH CTRIPBL CTRIPOUTEL u.
7.10.2 Comparator Subsystem (CMPSS)
Each CMPSS module includes two comparators, two internal voltage reference DACs (CMPSS DACs), two
digital glitch filters, and one ramp generator. There are two inputs, CMPINxP and CMPINxN. Each of these
inputs will be internally connected to an ADCIN pin. The CMPINxP pin is always connected to the positive input
of the CMPSS comparators. CMPINxN can be used instead of the DAC output to drive the negative comparator
inputs. There are two comparators, and therefore two outputs from the CMPSS module, which are connected to
the input of a digital filter module before being passed on to the Comparator TRIP crossbar and either PWM
modules or directly to a GPIO pin. Figure 7-37 shows the CMPSS connectivity on the 337-ball ZWT and 176-pin
PTP packages. Figure 7-38 shows CMPSS connectivity on the 100-pin PZP package.
CTRIPOUT1H
CTRIP1H
CTRIP1L
CTRIP2L
CTRIPOUT2H
CTRIP2H
CTRIPOUT8H
CTRIP8H
CTRIP8L
ePWMs
ePWM X-BAR
CTRIPOUT2L
CTRIPOUT8L
CTRIP1H
CTRIP1L
CTRIP2H
CTRIP2L
CTRIP8H
CTRIP8L
GPIO Mux
Output X-BAR
CTRIPOUT1H
CTRIPOUT1L
CTRIPOUT2H
CTRIPOUT2L
CTRIPOUT8H
CTRIPOUT8L
Comparator Subsystem 1
VDDA or VDAC
Digital
Filter
Digital
Filter
DAC12
DAC12
CTRIPOUT1L
Comparator Subsystem 2
VDDA or VDAC
Digital
Filter
Digital
Filter
DAC12
DAC12
Comparator Subsystem 8
VDDA or VDAC
Digital
Filter
Digital
Filter
DAC12
DAC12
CMPIN1P Pin
CMPIN1N Pin
CMPIN2N Pin
CMPIN8N Pin
CMPIN2P Pin
CMPIN8P Pin
Figure 7-37. CMPSS Connectivity (337-Ball ZWT and 176-Pin PTP)
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I TEXAS INSTRUMENTS CTRIP1 H cTRIPoun H CTRIP1 L cTRIPoun L CTRIPZH CTRIPOUTZH CTRIPZL CTRIPOUTZL CTR‘PSH CTR‘POUTSH CTR‘PSL CTR‘POUTSL CTRIPAH CTR‘POUTAH CTRIPAL CTR‘POUTAL
CTRIPOUT1H
CTRIP1H
CTRIP1L
CTRIP2L
CTRIPOUT2H
CTRIP2H
CTRIPOUT4H
CTRIP4H
CTRIP4L
ePWMsePWM X-BAR
CTRIPOUT2L
CTRIPOUT4L
GPIO Mux
Output X-BAR
Comparator Subsystem 1
VDDA or VDAC
Digital
Filter
Digital
Filter
DAC12
DAC12
CTRIPOUT1L
Comparator Subsystem 2
VDDA or VDAC
Digital
Filter
Digital
Filter
DAC12
DAC12
Comparator Subsystem 4
VDDA or VDAC
Digital
Filter
Digital
Filter
DAC12
DAC12
CTRIPOUT3H
CTRIP3H
CTRIP3L
CTRIPOUT3L
Comparator Subsystem 3
VDDA or VDAC
Digital
Filter
Digital
Filter
DAC12
DAC12
CTRIP1H
CTRIP1L
CTRIP2H
CTRIP2L
CTRIP4H
CTRIP4L
CTRIP3H
CTRIP3L
CTRIPOUT1H
CTRIPOUT1L
CTRIPOUT2H
CTRIPOUT2L
CTRIPOUT4H
CTRIPOUT4L
CTRIPOUT3H
CTRIPOUT3L
CMPIN1P Pin
CMPIN2P Pin
CMPIN3P Pin
CMPIN4P Pin
CMPIN1N Pin
CMPIN2N Pin
CMPIN3N Pin
CMPIN4N Pin
Figure 7-38. CMPSS Connectivity (100-Pin PZP)
TMS320F28379S, TMS320F28378S, TMS320F28377S, TMS320F28377S-Q1
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b TEXAS INSTRUMENTS DACxVAL
7.10.2.1 CMPSS Electrical Data and Timing
Section 7.10.2.1.1 shows the comparator electrical characteristics. Figure 7-39 shows the CMPSS comparator
input referred offset. Figure 7-40 shows the CMPSS comparator hysteresis.
7.10.2.1.1 Comparator Electrical Characteristics
over recommended operating conditions (unless otherwise noted)
PARAMETER TEST CONDITIONS MIN TYP MAX UNIT
Power-up time 500(2) µs
Comparator input (CMPINxx) range 0 VDDA V
Input referred offset error Low common mode, inverting input set
to 50 mV –20 20 mV
Hysteresis(1)
1x 12
CMPSS
DAC LSB
2x 24
3x 36
4x 48
Response time (delay from CMPINx input change
to output on ePWM X-BAR or Output X-BAR)
Step response 21 60
ns
Ramp response (1.65 V/µs) 26
Ramp response (8.25 mV/µs) 30
Common Mode Rejection Ratio (CMRR) 40 dB
(1) The CMPSS DAC is used as the reference to determine how much hysteresis to apply. Therefore, hysteresis will scale with the
CMPSS DAC reference voltage. Hysteresis is available for all comparator input source configurations.
(2) See the "Analog Bandgap References" advisory of the TMS320F2837xS MCUs Silicon Errata .
Note
The CMPSS inputs must be kept below VDDA + 0.3 V to ensure proper functional operation. If a
CMPSS input exceeds this level, an internal blocking circuit will isolate the internal comparator from
the external pin until the external pin voltage returns below VDDA + 0.3 V. During this time, the internal
comparator input will be floating and can decay below VDDA within approximately 0.5 µs. After this
time, the comparator could begin to output an incorrect result depending on the value of the other
comparator input.
CTRIPx = 0
0CMPINxN or
DACxVAL
CTRIPx = 1
Input Referred Offset
COMPINxP
Voltage
CTRIPx
Logic Level
Figure 7-39. CMPSS Comparator Input Referred Offset
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TEXAS INSTRUMENTS DACXVAL
CTRIPx = 0
0CMPINxN or
DACxVAL
CTRIPx = 1
Hysteresis
COMPINxP
Voltage
CTRIPx
Logic Level
Figure 7-40. CMPSS Comparator Hysteresis
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TEXAS INSTRUMENTS 7 mun woman m m mum i W i m: Ompm LLSEA pram“; WM (L55)
Section 7.10.2.1.2 shows the CMPSS DAC static electrical characteristics. Figure 7-41 shows the CMPSS DAC
static offset. Figure 7-42 shows the CMPSS DAC static gain. Figure 7-43 shows the CMPSS DAC static linearity.
7.10.2.1.2 CMPSS DAC Static Electrical Characteristics
over recommended operating conditions (unless otherwise noted)
PARAMETER TEST CONDITIONS MIN TYP MAX UNIT
CMPSS DAC output range Internal reference 0 VDDA (1)
V
External reference 0 VDAC
Static offset error(2) –25 25 mV
Static gain error(2) –2 2 % of FSR
Static DNL Endpoint corrected >–1 4 LSB
Static INL Endpoint corrected –16 16 LSB
Settling time Settling to 1 LSB after full-scale output
change 1 µs
Resolution 12 bits
CMPSS DAC output disturbance(3) Error induced by comparator trip or
CMPSS DAC code change within the
same CMPSS module
–100 100 LSB
CMPSS DAC disturbance time(3) 200 ns
VDAC reference voltage When VDAC is reference 2.4 2.5 or 3.0 VDDA V
VDAC load(4) When VDAC is reference 6 kΩ
(1) The maximum output voltage is VDDA when VDAC > VDDA.
(2) Includes comparator input referred errors.
(3) Disturbance error may be present on the CMPSS DAC output for a certain amount of time after a comparator trip.
(4) Per active CMPSS module.
Offset Error
Figure 7-41. CMPSS DAC Static Offset
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TEXAS INSTRUMENTS 7 mm mm mm \mnmiflwt W I m: Ompm LLSEA MEN owl/figs; "“ m “m “" mm m mum , Emmi umdm mu mum, law m oulwl ? ? m Ompm may ‘ ‘ magma—1 maul (Lsa)
Actual Linear Range
Ideal Gain
Actual Gain
Figure 7-42. CMPSS DAC Static Gain
Linearity Error
Figure 7-43. CMPSS DAC Static Linearity
TMS320F28379S, TMS320F28378S, TMS320F28377S, TMS320F28377S-Q1
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I TEXAS INSTRUMENTS .— VREFHI ‘[ _ ACO EPWMlSYNCPER
7.10.3 Buffered Digital-to-Analog Converter (DAC)
The buffered DAC module consists of an internal 12-bit DAC and an analog output buffer that is capable of
driving an external load. An integrated pulldown resistor on the DAC output helps to provide a known pin voltage
when the output buffer is disabled. This pulldown resistor cannot be disabled and remains as a passive
component on the pin, even for other shared pin mux functions. Software writes to the DAC value register can
take effect immediately or can be synchronized with EPWMSYNCPER events.
Each buffered DAC has the following features:
• 12-bit programmable internal DAC
• Selectable reference voltage
• Pulldown resistor on output
• Ability to synchronize with EPWMSYNCPER
The block diagram for the buffered DAC is shown in Figure 7-44.
EPWM1SYNCPER
VREFHI
VDDA
VSSA
VDAC
DACCTL[DACREFSEL]
DACCTL[LOADMODE]
SYSCLK
DACCTL[SYNCSEL]
EPWM2SYNCPER
EPWM3SYNCPER
EPWMnSYNCPER
...
0
1
DQ
>
DQ
DACVALS
0
1
2
Y
n-1
0
1
DACVALA Buffer
12-bit
DAC
VSSA
DACOUT
DACREF
RPD
EN
Figure 7-44. DAC Module Block Diagram
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7.10.3.1 Buffered DAC Electrical Data and Timing
Section 7.10.3.1.1 shows the buffered DAC electrical characteristics. Figure 7-45 shows the buffered DAC offset.
Figure 7-46 shows the buffered DAC gain. Figure 7-47 shows the buffered DAC linearity.
7.10.3.1.1 Buffered DAC Electrical Characteristics
over recommended operating conditions (unless otherwise noted)(1)
PARAMETER TEST CONDITIONS MIN TYP MAX UNIT
Power-up time 500(8) µs
Offset error Midpoint –10 10 mV
Gain error(2) –2.5 2.5 % of FSR
DNL(3) Endpoint corrected > –1 ±0.4 1 LSB
INL Endpoint corrected –5 ±2 5 LSB
DACOUTx settling time Settling to 2 LSBs after 0.3V-to-3V
transition 2 µs
Resolution 12 bits
Voltage output range(4) 0.3 VDDA – 0.3 V
Capacitive load Output drive capability 100 pF
Resistive load Output drive capability 5 kΩ
RPD pulldown resistor 50 kΩ
Reference voltage(5) VDAC or VREFHI 2.4 2.5 or 3.0 VDDA V
Reference input resistance(6) VDAC or VREFHI 170 kΩ
Output noise Integrated noise from 100 Hz to 100 kHz 500 µVrms
Noise density at 10 kHz 711 nVrms/√Hz
Glitch energy 1.5 V-ns
PSRR(7) DC up to 1 kHz 70 dB
100 kHz 30
SNR 1020 Hz 67 dB
THD 1020 Hz –63 dB
SFDR 1020 Hz, including harmonics and spurs 66 dBc
1020 Hz, including only spurs 104
(1) Typical values are measured with VREFHI = 3.3 V unless otherwise noted. Minimum and Maximum values are tested or characterized
with VREFHI = 2.5 V.
(2) Gain error is calculated for linear output range.
(3) The DAC output is monotonic.
(4) This is the linear output range of the DAC. The DAC can generate voltages outside this range, but the output voltage will not be linear
due to the buffer.
(5) For best PSRR performance, VDAC or VREFHI should be less than VDDA.
(6) Per active Buffered DAC module.
(7) VREFHI = 3.2 V, VDDA = 3.3 V DC + 100 mV Sine.
(8) See the "Analog Bandgap References" advisory of the TMS320F2837xS MCUs Silicon Errata .
Note
The VDAC pin must be kept below VDDA + 0.3 V to ensure proper functional operation. If the VDAC
pin exceeds this level, a blocking circuit may activate, and the internal value of VDAC may float to 0 V
internally, giving improper DAC output.
TMS320F28379S, TMS320F28378S, TMS320F28377S, TMS320F28377S-Q1
TMS320F28376S, TMS320F28375S, TMS320F28375S-Q1, TMS320F28374S
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b TEXAS INSTRUMENTS .m m m m m m m m m ‘m mm mm .w E unmmmgm“. ”m3 525 93 7 am: we mm: mm m amp: Pvugvzlmmd mu nssa am; 523 93
Note
The VREFHI pin must be kept below VDDA + 0.3 V to ensure proper functional operation. If the VREFHI
pin exceeds this level, a blocking circuit may activate, and the internal value of VREFHI may float to 0 V
internally, giving improper ADC conversion or DAC output.
Offset Error
Code 2048
Figure 7-45. Buffered DAC Offset
Code 3722
Code 373
Actual Gain
Ideal Gain
Linear Range
(3.3-V Reference)
Figure 7-46. Buffered DAC Gain
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TMS320F28379S, TMS320F28378S, TMS320F28377S, TMS320F28377S-Q1
TMS320F28376S, TMS320F28375S, TMS320F28375S-Q1, TMS320F28374S
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TEXAS INSTRUMENTS mu: mum (LEE) ngzmlmd mam «say 7 Am: m cm rrrrr mm. Camden ma lmeanly ‘ Ideal BM) mlwl ‘ m _ ‘ ‘ ‘ ‘ m _ ‘ ‘ ‘ ‘ ‘ 7,. 7 ‘ ‘ ‘ ‘ ‘ A _ ‘ ‘ 1 L ‘7 ‘ ‘ L x I . . I I I I ‘ ' L ,. m 1m m m m m. ‘ m ‘ ‘ ‘ ‘ ‘ ‘ ‘
Linearity Error
Code 3722
Code 373
Linear Range
(3.3-V Reference)
Figure 7-47. Buffered DAC Linearity
TMS320F28379S, TMS320F28378S, TMS320F28377S, TMS320F28377S-Q1
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7.11 Control Peripherals
Note
For the actual number of each peripheral on a specific device, see Table 5-1.
7.11.1 Enhanced Capture (eCAP)
The eCAP module can be used in systems where accurate timing of external events is important.
Applications for eCAP include:
• Speed measurements of rotating machinery (for example, toothed sprockets sensed through Hall sensors)
• Elapsed time measurements between position sensor pulses
• Period and duty cycle measurements of pulse train signals
• Decoding current or voltage amplitude derived from duty cycle encoded current/voltage sensors
The eCAP module includes the following features:
• 4-event time-stamp registers (each 32 bits)
• Edge-polarity selection for up to four sequenced time-stamp capture events
• Interrupt on either of the four events
• Single shot capture of up to four event timestamps
• Continuous mode capture of timestamps in a four-deep circular buffer
• Absolute time-stamp capture
• Difference (Delta) mode time-stamp capture
• All of the above resources dedicated to a single input pin
• When not used in capture mode, the eCAP module can be configured as a single-channel PWM output
(APWM).
The eCAP inputs connect to any GPIO input through the Input X-BAR. The APWM outputs connect to GPIO pins
through the Output X-BAR to OUTPUTx positions in the GPIO mux. See Section 6.4.2 and Section 6.4.3.
Figure 7-48 shows the block diagram of an eCAP module.
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TMS320F28379S, TMS320F28378S, TMS320F28377S, TMS320F28377S-Q1
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TEXAS INSTRUMENTS Pmanly \ntermm and
TSCTR
(counter−32 bit)
RST
CAP1
(APRD active) LD
CAP2
(ACMP active) LD
CAP3
(APRD shadow) LD
CAP4
(ACMP shadow) LD
Continuous /
Oneshot
Capture Control
LD1
LD2
LD3
LD4
32
32
PRD [0−31]
CMP [0−31]
CTR [0−31]
eCAPx
Interrupt
Trigger
and
Flag
control
to PIE
CTR=CMP
32
32
32
32
32
ACMP
shadow
Event
Prescale
CTRPHS
(phase register−32 bit)
SYNCOut
SYNCIn
Event
qualifier
Polarity
select
Polarity
select
Polarity
select
Polarity
select
CTR=PRD
CTR_OVF
4
PWM
compare
logic
CTR [0−31]
PRD [0−31]
CMP [0−31]
CTR=CMP
CTR=PRD
CTR_OVF
OVF
APWM mode
Delta−mode
SYNC
4
Capture events
CEVT[1:4]
APRD
shadow
32
32
MODE SELECT
Figure 7-48. eCAP Block Diagram
The eCAP module is clocked by PERx.SYSCLK.
The clock enable bits (ECAP1–ECAP6) in the PCLKCR3 register turn off the eCAP module individually (for low-
power operation). Upon reset, ECAP1ENCLK is set to low, indicating that the peripheral clock is off.
TMS320F28379S, TMS320F28378S, TMS320F28377S, TMS320F28377S-Q1
TMS320F28376S, TMS320F28375S, TMS320F28375S-Q1, TMS320F28374S
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7.11.1.1 eCAP Electrical Data and Timing
Section 7.11.1.1.1 shows the eCAP timing requirement and Section 7.11.1.1.2 shows the eCAP switching
characteristics.
7.11.1.1.1 eCAP Timing Requirement
MIN(1) MAX UNIT
tw(CAP) Capture input pulse width
Asynchronous 2tc(SYSCLK) cycles
Synchronous 2tc(SYSCLK) cycles
With input qualifier 1tc(SYSCLK) + tw(IQSW) cycles
(1) For an explanation of the input qualifier parameters, see Section 7.9.6.2.1.
7.11.1.1.2 eCAP Switching Characteristics
over recommended operating conditions (unless otherwise noted)
PARAMETER MIN MAX UNIT
tw(APWM) Pulse duration, APWMx output high/low 20 ns
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7.11.2 Enhanced Pulse Width Modulator (ePWM)
The ePWM peripheral is a key element in controlling many of the power electronic systems found in both
commercial and industrial equipment. The ePWM type-4 module is able to generate complex pulse width
waveforms with minimal CPU overhead by building the peripheral up from smaller modules with separate
resources that can operate together to form a system. Some of the highlights of the ePWM type-4 module
include complex waveform generation, dead-band generation, a flexible synchronization scheme, advanced trip-
zone functionality, and global register reload capabilities.
Figure 7-49 shows the signal interconnections with the ePWM. Figure 7-50 shows the ePWM trip input
connectivity.
TMS320F28379S, TMS320F28378S, TMS320F28377S, TMS320F28377S-Q1
TMS320F28376S, TMS320F28375S, TMS320F28375S-Q1, TMS320F28374S
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I TEXAS INSTRUMENTS TR:ZERO o TR:CMP WstvNcl V a a a a 4 a a _+ H a Cupyngmo 2017‘ Texas msuumems \ncurpmanzd
TBPRD Shadow (24)
TBPRD Active (24)
Counter
Up/Down
(16 Bit)
TBCTR
Active (16)
TBCTL[PHSEN]
CTR=PRD
16
Phase
Control
8
CTR=ZERO
CTR_Dir
TBPHSHR (8)
TBPRDHR (8)
8
Time-Base (TB)
TBPHS Active (24)
CTR=PRD
CTR=ZERO
CTR_Dir
DCAEVT1.soc(A)
DCBEVT1.soc(A)
Event
Trigger
and
Interrupt
(ET)
EPWMx_INT
ADCSOCAO
ADCSOCBO
EPWMxSOCA
On-chip
ADC
Action
Qualifier
(AQ)
EPWMA
EPWMB
Dead
Band
(DB)
PWM
Chopper
(PC)
Trip
Zone
(TZ)
ePWMxA
ePWMxB
CTR=ZERO
EPWMx_TZ_INT
TZ1 TZ3to
EMUSTOP
CLOCKFAIL
EQEPxERR
DCAEVT1.force(A)
DCAEVT2.force(A)
DCBEVT1.force(A)
DCBEVT2.force(A)
CTR=CMPA
16
CMPAHR (8)
CTR=CMPB
16
CMPB Active (24)
CMPB Shadow (24)
HiRes PWM (HRPWM)
CTR=PRD or ZERO
DCAEVT1.inter
DCBEVT1.inter
DCAEVT2.inter
DCBEVT2.inter
CMPA Active (24)
CMPA Shadow (24)
CTR=CMPB
CTR=CMPC
CTR=CMPA
CTR=CMPD
CMPBHR (8)
CMPAHR (8)
CMPBHR (8)
CTR=CMPC
16
TBCNT(16)
CMPC[15-0]
CTR=CMPD
16
TBCNT(16)
CMPD[15-0]
Counter Compare (CC)
CMPD Active (16)
CMPD Shadow (16)
CMPC Active (16)
CMPC Shadow (16)
Sync
Out
Select
CTR=ZERO
CTR=CMPB
EPWMxSYNCO
EPWMxSYNCI
TBCTL[SWFSYNC]
TBCTL[SYNCOSEL]
00
01
10
11
TBCTL2[SYNCOSELX]
Disable
CTR=CMPC
CTR=CMPD
Rsvd
EPWMxSOCB
DCBEVT1.sync(A)
DCAEVT1.sync(A)
Select and pulse stretch
for external ADC
ADCSOCOUTSELECT
Copyright © 2017, Texas Instruments Incorporated
A. These events are generated by the ePWM digital compare (DC) submodule based on the levels of the TRIPIN inputs.
Figure 7-49. ePWM Submodules and Critical Internal Signal Interconnects
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TMS320F28379S, TMS320F28378S, TMS320F28377S, TMS320F28377S-Q1
TMS320F28376S, TMS320F28375S, TMS320F28375S-Q1, TMS320F28374S
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v TEXAS INSTRUMENTS ‘Eiz ‘EEZ ‘Enuz a a 3.
Async/
Sync/
Sync+Filter
Input X-Bar XINT4
XINT5
INPUT14
INPUT13
PIE(s),
CLA(s)
eCAP6
eCAP5
eCAP4
eCAP3
eCAP2
eCAP1
INPUT1
INPUT2
INPUT3
INPUT4
INPUT5
INPUT6
INPUT7
INPUT8
INPUT9
INPUT10
INPUT11
INPUT12
TZ1
TZ2
TZ3
TRIP1
TRIP2
TRIP3
TRIP6
XINT1
XINT2
XINT3
PIE(s),
CLA(s)
ADC
Wrapper(s)
TRIP4
TRIP5
TRIP7
TRIP8
TRIP9
TRIP10
TRIP11
TRIP12
Reserved
ECCERR
EQEPERR
CLKFAIL
EPWMn.EMUSTOP
TRIP13
TRIP14
TRIP15
TZ4
TZ5
TZ6
ePWM
X-Bar All
ePWM
Modules
EPWMINT
TZINT
SOCA
SOCB
PWM11.CMPC
PWM11.CMPD
PWM12.CMPC
PWM12.CMPD
PIE(s),
CLA(s)
EPWMx.EPWMCLK
EPWMENCLK
TBCLKSYNC
ADCSOCAO Select Ckt
ADCSOCBO Select Ckt
ADC
Wrapper(s)
ePWM and eCAP
Sync Chain
FLT1
FLT1
FLT1
FLT1
FLT1
FLT1
FLT1
FLT1
Filter-Reset
Filter-Reset
Filter-Reset
Filter-Reset
SD1
SD2
GPIO0
GPIOx
EXTSYNCIN1
EXTSYNCIN2
CPU1.PIEVECTERROR
CPU1.EMUSTOP
EPWMSYNCPER CMPSS
DAC
Figure 7-50. ePWM Trip Input Connectivity
TMS320F28379S, TMS320F28378S, TMS320F28377S, TMS320F28377S-Q1
TMS320F28376S, TMS320F28375S, TMS320F28375S-Q1, TMS320F28374S
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MENTS EJ— & E: "E
7.11.2.1 Control Peripherals Synchronization
The ePWM and eCAP synchronization chain allows synchronization between multiple modules for the system.
Figure 7-51 shows the synchronization chain architecture.
EPWM1
EPWM2
EPWM3 EPWM4
EPWM5
EPWM6 EPWM7
EPWM8
EPWM9 EPWM10
EPWM11
EPWM12 ECAP1
EXTSYNCIN1
EXTSYNCOUT
Pulse-Stretched
(8 PLLSYSCLK
Cycles)
SYNCSEL.EPWM4SYNCIN
EXTSYNCIN2
SYNCSEL.SYNCOUT
SYNCSEL.EPWM7SYNCIN
SYNCSEL.ECAP4SYNCIN
SYNCSEL.ECAP1SYNCIN
SYNCSEL.EPWM10SYNCIN
EPWM1SYNCOUT
EPWM4SYNCOUT
EPWM7SYNCOUT
EPWM10SYNCOUT
ECAP1SYNCOUT
ECAP2
ECAP3 ECAP4
ECAP5
ECAP6
Figure 7-51. Synchronization Chain Architecture
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TMS320F28379S, TMS320F28378S, TMS320F28377S, TMS320F28377S-Q1
TMS320F28376S, TMS320F28375S, TMS320F28375S-Q1, TMS320F28374S
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I TEXAS INSTRUMENTS
7.11.2.2 ePWM Electrical Data and Timing
Section 7.11.2.2.1 shows the PWM timing requirements and Section 7.11.2.2.2 shows the PWM switching
characteristics.
7.11.2.2.1 ePWM Timing Requirements
MIN(1) MAX UNIT
f(EPWM) Frequency, EPWMCLK(2) 100 MHz
tw(SYNCIN) Sync input pulse width
Asynchronous 2tc(EPWMCLK) cycles
Synchronous 2tc(EPWMCLK) cycles
With input qualifier 1tc(EPWMCLK) + tw(IQSW) cycles
(1) For an explanation of the input qualifier parameters, see Section 7.9.6.2.1.
(2) For SYSCLK above 100 MHz, the EPWMCLK must be half of SYSCLK.
7.11.2.2.2 ePWM Switching Characteristics
over recommended operating conditions (unless otherwise noted)
PARAMETER MIN MAX UNIT
tw(PWM) Pulse duration, PWMx output high/low 20 ns
tw(SYNCOUT) Sync output pulse width 8tc(SYSCLK) cycles
td(TZ-PWM)
Delay time, trip input active to PWM forced high
Delay time, trip input active to PWM forced low
Delay time, trip input active to PWM Hi-Z
25 ns
7.11.2.2.3 Trip-Zone Input Timing
Section 7.11.2.2.3.1 shows the trip-zone input timing requirements. Figure 7-52 shows the PWM Hi-Z
characteristics.
7.11.2.2.3.1 Trip-Zone Input Timing Requirements
MIN(1) MAX UNIT
tw(TZ) Pulse duration, TZx input low
Asynchronous 1tc(EPWMCLK) cycles
Synchronous 2tc(EPWMCLK) cycles
With input qualifier 1tc(EPWMCLK) + tw(IQSW) cycles
(1) For an explanation of the input qualifier parameters, see Section 7.9.6.2.1.
PWM(B)
TZ(A)
EPWMCLK
tw(TZ)
td(TZ-PWM)
A. TZ: TZ1, TZ2, TZ3, TRIP1–TRIP12
B. PWM refers to all the PWM pins in the device. The state of the PWM pins after TZ is taken high depends on the PWM recovery software.
Figure 7-52. PWM Hi-Z Characteristics
TMS320F28379S, TMS320F28378S, TMS320F28377S, TMS320F28377S-Q1
TMS320F28376S, TMS320F28375S, TMS320F28375S-Q1, TMS320F28374S
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l TEXAS INSTRUMENTS AD E
7.11.2.3 External ADC Start-of-Conversion Electrical Data and Timing
Section 7.11.2.3.1 shows the external ADC start-of-conversion switching characteristics. Figure 7-53 shows the
ADCSOCAO or ADCSOCBO timing.
7.11.2.3.1 External ADC Start-of-Conversion Switching Characteristics
over recommended operating conditions (unless otherwise noted)
PARAMETER MIN MAX UNIT
tw(ADCSOCL) Pulse duration, ADCSOCxO low 32tc(SYSCLK) cycles
ADCSOCAO
ADCSOCBO
or
tw(ADCSOCL)
Figure 7-53. ADCSOCAO or ADCSOCBO Timing
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TMS320F28379S, TMS320F28378S, TMS320F28377S, TMS320F28377S-Q1
TMS320F28376S, TMS320F28375S, TMS320F28375S-Q1, TMS320F28374S
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7.11.3 Enhanced Quadrature Encoder Pulse (eQEP)
The eQEP module interfaces directly with linear or rotary incremental encoders to obtain position, direction, and
speed information from rotating machines used in high-performance motion and position-control systems.
Each eQEP peripheral comprises five major functional blocks:
• Quadrature Capture Unit (QCAP)
• Position Counter/Control Unit (PCCU)
• Quadrature Decoder Unit (QDU)
• Unit Time Base for speed and frequency measurement (UTIME)
• Watchdog timer for detecting stalls (QWDOG)
The eQEP peripherals are clocked by PERx.SYSCLK. Figure 7-54 shows the eQEP block diagram.
TMS320F28379S, TMS320F28378S, TMS320F28377S, TMS320F28377S-Q1
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I TEXAS INSTRUMENTS _A
QWDTMR
QWDPRD
16
QWDOG
UTIME
QUPRD
QUTMR
32
UTOUT
WDTOUT
Quadrature
Capture
Unit
(QCAP)
QCPRDLAT
QCTMRLAT
16
QFLG
QEPSTS
QEPCTL
Registers
Used by
Multiple Units
QCLK
QDIR
QI
QS
PHE
PCSOUT
Quadrature
Decoder
(QDU)
QDECCTL
16
Position Counter/
Control Unit
(PCCU)
QPOSLAT
QPOSSLAT
16
QPOSILAT
EQEPxAIN
EQEPxBIN
EQEPxIIN
EQEPxIOUT
EQEPxIOE
EQEPxSIN
EQEPxSOUT
EQEPxSOE
GPIO
MUX
EQEPxA/XCLK
EQEPxB/XDIR
EQEPxS
EQEPxI
QPOSCMP QEINT
QFRC
32
QCLR
QPOSCTL
1632
QPOSCNT
QPOSMAX
QPOSINIT
PIE EQEPxINT
eQEP Peripheral
System Control
Registers
QCTMR
QCPRD
1616
QCAPCTL
EQEPxENCLK
SYSCLK
To CPU
Data Bus
Figure 7-54. eQEP Block Diagram
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TMS320F28376S, TMS320F28375S, TMS320F28375S-Q1, TMS320F28374S
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7.11.3.1 eQEP Electrical Data and Timing
Section 7.11.3.1.1 lists the eQEP timing requirement and Section 7.11.3.1.2 lists the eQEP switching
characteristics.
7.11.3.1.1 eQEP Timing Requirements
MIN(1) MAX UNIT
tw(QEPP) QEP input period Asynchronous(2)/Synchronous 2tc(SYSCLK) cycles
With input qualifier 2[1tc(SYSCLK) + tw(IQSW)] cycles
tw(INDEXH) QEP Index Input High time Asynchronous(2)/Synchronous 2tc(SYSCLK) cycles
With input qualifier 2tc(SYSCLK) + tw(IQSW) cycles
tw(INDEXL) QEP Index Input Low time Asynchronous(2)/Synchronous 2tc(SYSCLK) cycles
With input qualifier 2tc(SYSCLK) + tw(IQSW) cycles
tw(STROBH) QEP Strobe High time Asynchronous(2)/Synchronous 2tc(SYSCLK) cycles
With input qualifier 2tc(SYSCLK) + tw(IQSW) cycles
tw(STROBL) QEP Strobe Input Low time Asynchronous(2)/Synchronous 2tc(SYSCLK) cycles
With input qualifier 2tc(SYSCLK) + tw(IQSW) cycles
(1) For an explanation of the input qualifier parameters, see Section 7.9.6.2.1.
(2) See the TMS320F2837xS MCUs Silicon Errata for limitations in the asynchronous mode.
7.11.3.1.2 eQEP Switching Characteristics
over recommended operating conditions (unless otherwise noted)
PARAMETER MIN MAX UNIT
td(CNTR)xin Delay time, external clock to counter increment 4tc(SYSCLK) cycles
td(PCS-OUT)QEP Delay time, QEP input edge to position compare sync output 6tc(SYSCLK) cycles
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7.11.4 High-Resolution Pulse Width Modulator (HRPWM)
The HRPWM combines multiple delay lines in a single module and a simplified calibration system by using a
dedicated calibration delay line. For each ePWM module, there are two HR outputs:
• HR Duty and Deadband control on Channel A
• HR Duty and Deadband control on Channel B
The HRPWM module offers PWM resolution (time granularity) that is significantly better than what can be
achieved using conventionally derived digital PWM methods. The key points for the HRPWM module are:
• Significantly extends the time resolution capabilities of conventionally derived digital PWM
• This capability can be used in both single edge (duty cycle and phase-shift control) as well as dual edge
control for frequency/period modulation.
• Finer time granularity control or edge positioning is controlled through extensions to the Compare A, B,
phase, period and deadband registers of the ePWM module.
Note
The minimum HRPWMCLK frequency allowed for HRPWM is 60 MHz.
7.11.4.1 HRPWM Electrical Data and Timing
Section 7.11.4.1.1 lists the high-resolution PWM timing requirements. Section 7.11.4.1.2 lists the high-resolution
PWM switching characteristics.
7.11.4.1.1 High-Resolution PWM Timing Requirements
MIN MAX UNIT
f(EPWM) Frequency, EPWMCLK(1) 100 MHz
f(HRPWM) Frequency, HRPWMCLK 60 100 MHz
(1) For SYSCLK above 100 MHz, the EPWMCLK must be half of SYSCLK.
7.11.4.1.2 High-Resolution PWM Characteristics
PARAMETER MIN TYP MAX UNIT
Micro Edge Positioning (MEP) step size(1) 150 310 ps
(1) The MEP step size will be largest at high temperature and minimum voltage on VDD. MEP step size will increase with higher
temperature and lower voltage and decrease with lower temperature and higher voltage.
Applications that use the HRPWM feature should use MEP Scale Factor Optimizer (SFO) estimation software functions. See the TI
software libraries for details of using SFO functions in end applications. SFO functions help to estimate the number of MEP steps per
SYSCLK period dynamically while the HRPWM is in operation.
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7.11.5 Sigma-Delta Filter Module (SDFM)
The SDFM is a four-channel digital filter designed specifically for current measurement and resolver position
decoding in motor control applications. Each channel can receive an independent sigma-delta (ΣΔ) modulated
bit stream. The bit streams are processed by four individually programmable digital decimation filters. The filter
set includes a fast comparator for immediate digital threshold comparisons for overcurrent and undercurrent
monitoring. Figure 7-55 shows a block diagram of the SDFMs.
SDFM features include:
• Eight external pins per SDFM module:
– Four sigma-delta data input pins per SDFM module (SDx_Dy, where x = 1 to 2 and y = 1 to 4)
– Four sigma-delta clock input pins per SDFM module (SDx_Cy, where x = 1 to 2 and y = 1 to 4)
• Four different configurable modulator clock modes:
– Modulator clock rate equals modulator data rate
– Modulator clock rate running at half the modulator data rate
– Modulator data is Manchester encoded. Modulator clock not required.
– Modulator clock rate is double that of modulator data rate
• Four independent configurable comparator units:
– Four different filter type selection (Sinc1/Sinc2/Sincfast/Sinc3) options available
– Ability to detect over-value and under-value conditions
– Comparator Over-Sampling Ratio (COSR) value for comparator programmable from 1 to 32
• Four independent configurable data filter units:
– Four different filter type selection (Sinc1/Sinc2/Sincfast/Sinc3) options available
– Data filter Over-Sampling Ratio (DOSR) value for data filter unit programmable from 1 to 256
– Ability to enable or disable individual filter module
– Ability to synchronize all four independent filters of a SDFM module using the Master Filter Enable (MFE)
bit or the PWM signals.
• Filter data can be 16-bit or 32-bit representation
• PWMs can be used to generate modulator clock for sigma-delta modulators
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Filter Channel 1
SDFM- Sigma Delta Filter Module
Input
Ctrl
G4
Streams
Data bus
Register
Map
R
R
Comparator filter
Data filter
FILRES
Filter Channel 4
Filter Channel 3
Filter Channel 2
PIE
Interrupt
Unit
IEL
IEH
SD1INT
Filter Channel 1
SDFM- Sigma Delta Filter Module
Input
Ctrl
G4
Streams
Data bus
Register
Map
R
R
Comparator filter
Data filter
Filter Channel 4
Filter Channel 3
Filter Channel 2
Interrupt
Unit
IEL
IEH
SD2INT
Output
XBar
SD1FLT1.IEH
SD1FLT1.IEL
SD1FLT2.IEH
SD1FLT2.IEL
SD1FLT3.IEH
SD1FLT3.IEL
SD1FLT4.IEH
SD1FLT4.IEL
SD2FLT1.IEH
SD2FLT1.IEL
SD2FLT2.IEH
SD2FLT2.IEL
SD2FLT3.IEH
SD2FLT3.IEL
SD2FLT4.IEH
SD2FLT4.IEL
PWM11.CMPC
PWM11.CMPD
FILRES
FILRES
FILRES
PWM12.CMPC
FILRES
PWM12.CMPD FILRES
FILRES
Data filter
FILRES
GPIO
MUX
SD2_D1
SD2_C1
SD2_D2
SD2_C2
SD2_D3
SD2_C3
SD2_D4
SD2_C4
SD1_D4
SD1_C4
SD1_D3
SD1_C3
SD1_D2
SD1_C2
SD1_D1
SD1_C1
Figure 7-55. SDFM Block Diagram
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7.11.5.1 SDFM Electrical Data and Timing (Using ASYNC)
SDFM operation with asynchronous GPIO is defined by setting GPyQSELn = 0b11. Section 7.11.5.1.1 lists the
SDFM timing requirements when using the asynchronous GPIO (ASYNC) option. Figure 7-56 through Figure
7-59 show the SDFM timing diagrams.
7.11.5.1.1 SDFM Timing Requirements When Using Asynchronous GPIO (ASYNC) Option
MIN MAX UNIT
Mode 0
tc(SDC)M0 Cycle time, SDx_Cy 40 256 * SYSCLK period ns
tw(SDCH)M0 Pulse duration, SDx_Cy high 10 tc(SDC)M0 – 10 ns
tsu(SDDV-SDCH)M0 Setup time, SDx_Dy valid before SDx_Cy goes
high 5 ns
th(SDCH-SDD)M0 Hold time, SDx_Dy wait after SDx_Cy goes high 5 ns
Mode 1
tc(SDC)M1 Cycle time, SDx_Cy 80 256 * SYSCLK period ns
tw(SDCH)M1 Pulse duration, SDx_Cy high 10 tc(SDC)M1 – 10 ns
tsu(SDDV-SDCL)M1 Setup time, SDx_Dy valid before SDx_Cy goes
low 5 ns
tsu(SDDV-SDCH)M1 Setup time, SDx_Dy valid before SDx_Cy goes
high 5 ns
th(SDCL-SDD)M1 Hold time, SDx_Dy wait after SDx_Cy goes low 5 ns
th(SDCH-SDD)M1 Hold time, SDx_Dy wait after SDx_Cy goes high 5 ns
Mode 2
tc(SDD)M2 Cycle time, SDx_Dy 8 * tc(SYSCLK) 20 * tc(SYSCLK) ns
tw(SDDH)M2 Pulse duration, SDx_Dy high 10 ns
tw(SDD_LONG_KEEPOUT)M2
SDx_Dy long pulse duration keepout, where the
long pulse must not fall within the MIN or MAX
values listed.
Long pulse is defined as the high or low pulse
which is the full width of the Manchester bit-clock
period.
This requirement must be satisfied for any integer
between 8 and 20.
(N * tc(SYSCLK)) – 0.5 (N * tc(SYSCLK)) + 0.5 ns
tw(SDD_SHORT)M2
SDx_Dy Short pulse duration for a high or low
pulse (SDD_SHORT_H or SDD_SHORT_L).
Short pulse is defined as the high or low pulse
which is half the width of the Manchester bit-clock
period.
tw(SDD_LONG) / 2 –
tc(SYSCLK)
tw(SDD_LONG) / 2 +
tc(SYSCLK) ns
tw(SDD_LONG_DUTY)M2 SDx_Dy Long pulse variation (SDD_LONG_H –
SDD_LONG_L) – tc(SYSCLK) tc(SYSCLK) ns
tw(SDD_SHORT_DUTY)M2 SDx_Dy Short pulse variation (SDD_SHORT_H –
SDD_SHORT_L) – tc(SYSCLK) tc(SYSCLK) ns
Mode 3
tc(SDC)M3 Cycle time, SDx_Cy 40 256 * SYSCLK period ns
tw(SDCH)M3 Pulse duration, SDx_Cy high 10 tc(SDC)M3 – 5 ns
tsu(SDDV-SDCH)M3 Setup time, SDx_Dy valid before SDx_Cy goes
high 5 ns
th(SDCH-SDD)M3 Hold time, SDx_Dy wait after SDx_Cy goes high 5 ns
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TEXAS INSTRUMENTS
WARNING
The SDFM clock inputs (SDx_Cy pins) directly clock the SDFM module when there is no GPIO input
synchronization. Any glitches or ringing noise on these inputs can corrupt the SDFM module
operation. Special precautions should be taken on these signals to ensure a clean and noise-free
signal that meets SDFM timing requirements. Precautions such as series termination for ringing due
to any impedance mismatch of the clock driver and spacing of traces from other noisy signals are
recommended.
WARNING
Mode 2 (Manchester Mode) is not recommended for new applications. See the "SDFM: Manchester
Mode (Mode 2) Does Not Produce Correct Filter Results Under Several Conditions" advisory in the
TMS320F2837xS MCUs Silicon Errata .
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fl TEXAS INSTRUMENTS Made a Mode 1 Mode 2 _ _ ;L K / _ _ 1%}: _ _ ‘ TL _ Tr? TL “\‘W‘ _ _ _ _ ‘Iufi ‘ wm _ _ x r\_ / _\/_ _ _ _ _ ‘rufll rL‘ _ _ _ _ ‘TL‘ “““ ‘ _ _ ‘wlfilvvx‘ LVN} ‘ _ (CLKx .s dnven ex|emaHy) V‘A‘
Mode 0 tw(SDCH)M0 tc(SDC)M0
th(SDCH-SDD)M0
tsu(SDDV-SDCH)M0
SDx_Cy
SDx_Dy
Figure 7-56. SDFM Timing Diagram – Mode 0
tw(SDCH)M1 tc(SDC)M1
th(SDCL-SDD)M1 th(SDCH-SDD)M1
tsu(SDDV-SDCL)M1 tsu(SDDV-SDCH)M1
SDx_Cy
SDx_Dy
Mode 1
Figure 7-57. SDFM Timing Diagram – Mode 1
Modulator
Internal data
tc(SDD)M2
tw(SDDH)M2
Modulator
Internal clock
tw(SDD_LONG_KEEPOUT)
SDx-Dy
N x tc(SYSCLK) + 0.5
N x tc(SYSCLK) ±0.5
tw(SDD_LONG_L)
tw(SDD_SHORT_H) tw(SDD_SHORT_L)
tw(SDD_LONG_H)
N x SYSCLK
SYSCLK
Mode 2
(Manchester-encoded-bit stream)
1 1 0 1 01 0 1 1
±
Figure 7-58. SDFM Timing Diagram – Mode 2
Mode 3
SDx_Cy
SDx_Dy
(CLKx is driven externally)
tc(SDC)M3 tw(SDCH)M3
tsu(SDDV-SDCH)M3
th(SDCH-SDD)M3
Figure 7-59. SDFM Timing Diagram – Mode 3
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7.11.5.2 SDFM Electrical Data and Timing (Using 3-Sample GPIO Input Qualification)
SDFM operation with qualified GPIO (3-sample window) is defined by setting GPyQSELn = 0b01. When using
this qualified GPIO (3-sample window) mode, the timing requirement for the tw(GPI) pulse duration of 2tc(SYSCLK)
must be met. It is important for both SD-Cx and SD-Dx pairs to be configured with the same GPIO qualification
option. Section 7.11.5.2.1 lists the SDFM timing requirements when using the GPIO input qualification (3-sample
window) option. Figure 7-56 through Figure 7-59 show the SDFM timing diagrams.
7.11.5.2.1 SDFM Timing Requirements When Using GPIO Input Qualification (3-Sample Window) Option
MIN(1) MAX UNIT
Mode 0
tc(SDC)M0 Cycle time, SDx_Cy 10 * SYSCLK period 256 * SYSCLK period ns
tw(SDCHL)M0 Pulse duration, SDx_Cy high/low 4 * SYSCLK period 6 * SYSCLK period ns
tw(SDDHL)M0 Pulse duration, SDx_Dy high/low 4 * SYSCLK period ns
tsu(SDDV-SDCH)M0 Setup time, SDx_Dy valid before SDx_Cy goes
high 2 * SYSCLK period ns
th(SDCH-SDD)M0 Hold time, SDx_Dy wait after SDx_Cy goes high 2 * SYSCLK period ns
Mode 1
tc(SDC)M1 Cycle time, SDx_Cy 20 * SYSCLK period 256 * SYSCLK period ns
tw(SDCH)M1 Pulse duration, SDx_Cy high 4 * SYSCLK period 6 * SYSCLK period ns
tw(SDDHL)M1 Pulse duration, SDx_Dy high/low 4 * SYSCLK period ns
tsu(SDDV-SDCL)M1 Setup time, SDx_Dy valid before SDx_Cy goes
low 2 * SYSCLK period ns
tsu(SDDV-SDCH)M1 Setup time, SDx_Dy valid before SDx_Cy goes
high 2 * SYSCLK period ns
th(SDCL-SDD)M1 Hold time, SDx_Dy wait after SDx_Cy goes low 2 * SYSCLK period ns
th(SDCH-SDD)M1 Hold time, SDx_Dy wait after SDx_Cy goes high 2 * SYSCLK period ns
Mode 2
tc(SDD)M2 Cycle time, SDx_Dy Option unavailable
tw(SDDH)M2 Pulse duration, SDx_Dy high
Mode 3
tc(SDC)M3 Cycle time, SDx_Cy 10 * SYSCLK period 256 * SYSCLK period ns
tw(SDCHL)M3 Pulse duration, SDx_Cy high 4 * SYSCLK period 6 * SYSCLK period ns
tw(SDDHL)M3 Pulse duration, SDx_Dy high/low 4 * SYSCLK period ns
tsu(SDDV-SDCH)M3 Setup time, SDx_Dy valid before SDx_Cy goes
high 2 * SYSCLK period ns
th(SDCH-SDD)M3 Hold time, SDx_Dy wait after SDx_Cy goes high 2 * SYSCLK period ns
(1) SDFM timing requirements apply only when the GPIO input qualification type is the 3-sample window (GPyQSELx = 1; QUALPRD = 0)
option. It is important that both the SD-Cx and SD-Dx pairs be configured with the 3-sample window option.
Note
The SDFM Qualified GPIO (3-sample) mode provides protection against SDFM module corruption due
to occasional random noise glitches on the SDx_Cy pin that may result in a false comparator trip and
filter output. For more details, refer to the "SDFM: Use Caution While Using SDFM Under Noisy
Conditions" usage note in the TMS320F2837xS MCUs Silicon Errata .
The SDFM Qualified GPIO (3-sample) mode does not provide protection against persistent violations
of the above timing requirements. Timing violations will result in data corruption proportional to the
number of bits which violate the requirements.
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7.12 Communications Peripherals
Note
For the actual number of each peripheral on a specific device, see Table 5-1.
7.12.1 Controller Area Network (CAN)
The CAN module performs CAN protocol communication according to ISO 11898-1 (identical to Bosch® CAN
protocol specification 2.0 A, B). The bit rate can be programmed to values up to 1 Mbps. A CAN transceiver chip
is required for the connection to the physical layer (CAN bus).
For communication on a CAN network, individual message objects can be configured. The message objects and
identifier masks are stored in the Message RAM.
All functions concerning the handling of messages are implemented in the message handler. These functions
are: acceptance filtering; the transfer of messages between the CAN Core and the Message RAM; and the
handling of transmission requests.
The register set of the CAN may be accessed directly by the CPU through the module interface. These registers
are used to control and configure the CAN core and the message handler, and to access the message RAM.
The CAN module implements the following features:
• Complies with ISO11898-1 (Bosch® CAN protocol specification 2.0 A and B)
• Bit rates up to 1 Mbps
• Multiple clock sources
• 32 message objects (“message objects” are also referred to as “mailboxes” in this document; the two terms
are used interchangeably), each with the following properties:
– Configurable as receive or transmit
– Configurable with standard (11-bit) or extended (29-bit) identifier
– Supports programmable identifier receive mask
– Supports data and remote frames
– Holds 0 to 8 bytes of data
– Parity-checked configuration and data RAM
• Individual identifier mask for each message object
• Programmable FIFO mode for message objects
• Programmable loop-back modes for self-test operation
• Suspend mode for debug support
• Software module reset
• Automatic bus-on, after bus-off state by a programmable 32-bit timer
• Message-RAM parity-check mechanism
• Two interrupt lines
Note
For a CAN bit clock of 200 MHz, the smallest bit rate possible is 7.8125 kbps.
Note
Depending on the timing settings used, the accuracy of the on-chip zero-pin oscillator (specified in the
data manual) may not meet the requirements of the CAN protocol. In this situation, an external clock
source must be used.
Figure 7-60 shows the CAN block diagram.
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Wmm
CAN Core
Message
RAM
Interface
Message Handler
Register and Message
Object Access (IFx)
Module Interface
Message RAM
32
Message
Objects
(Mailboxes)
CAN
Test Modes
Only
3.3V CAN Transceiver
CANx RX pin CANx TX pin
CAN_H
CAN_L
CAN Bus
CANINT0 CANINT1 CPU Bus
External connections
Device
(to ePIE)
Figure 7-60. CAN Block Diagram
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7.12.2 Inter-Integrated Circuit (I2C)
The I2C module has the following features:
• Compliance with the Philips Semiconductors I2C-bus specification (version 2.1):
– Support for 1-bit to 8-bit format transfers
– 7-bit and 10-bit addressing modes
– General call
– START byte mode
– Support for multiple master-transmitters and slave-receivers
– Support for multiple slave-transmitters and master-receivers
– Combined master transmit/receive and receive/transmit mode
– Data transfer rate of from 10 kbps up to 400 kbps (I2C Fast-mode rate)
• One 16-byte receive FIFO and one 16-byte transmit FIFO
• One interrupt that can be used by the CPU. This interrupt can be generated as a result of one of the following
conditions:
– Transmit-data ready
– Receive-data ready
– Register-access ready
– No-acknowledgment received
– Arbitration lost
– Stop condition detected
– Addressed as slave
• An additional interrupt that can be used by the CPU when in FIFO mode
• Module enable/disable capability
• Free data format mode
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Figure 7-61 shows how the I2C peripheral module interfaces within the device.
I2CXSR I2CDXR
I2CRSR I2CDRR
Clock
Synchronizer
Prescaler
Noise Filters
Arbitrator
I2C INT
Peripheral Bus
Interrupt to
CPU/PIE
SDA
SCL
Control/Status
Registers CPU
I C Module
2
TX FIFO
RX FIFO
FIFO Interrupt to
CPU/PIE
Figure 7-61. I2C Peripheral Module Interfaces
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7.12.2.1 I2C Electrical Data and Timing
Section 7.12.2.1.1 lists the I2C timing requirements. Section 7.12.2.1.2 lists the I2C switching characteristics.
Figure 7-62 shows the I2C timing diagram.
7.12.2.1.1 I2C Timing Requirements
NO. MIN MAX UNIT
Standard mode
T0 fmod I2C module frequency 7 12 MHz
T1 th(SDA-SCL)START Hold time, START condition, SCL fall delay after
SDA fall 4.0 µs
T2 tsu(SCL-SDA)START Setup time, Repeated START, SCL rise before SDA
fall delay 4.7 µs
T3 th(SCL-DAT) Hold time, data after SCL fall 0 µs
T4 tsu(DAT-SCL) Setup time, data before SCL rise 250 ns
T5 tr(SDA) Rise time, SDA 1000 ns
T6 tr(SCL) Rise time, SCL 1000 ns
T7 tf(SDA) Fall time, SDA 300 ns
T8 tf(SCL) Fall time, SCL 300 ns
T9 tsu(SCL-SDA)STOP Setup time, STOP condition, SCL rise before SDA
rise delay 4.0 µs
T10 tw(SP) Pulse duration of spikes that will be suppressed by
filter 0 50 ns
T11 Cbcapacitance load on each bus line 400 pF
Fast mode
T0 fmod I2C module frequency 7 12 MHz
T1 th(SDA-SCL)START Hold time, START condition, SCL fall delay after
SDA fall 0.6 µs
T2 tsu(SCL-SDA)START Setup time, Repeated START, SCL rise before SDA
fall delay 0.6 µs
T3 th(SCL-DAT) Hold time, data after SCL fall 0 µs
T4 tsu(DAT-SCL) Setup time, data before SCL rise 100 ns
T5 tr(SDA) Rise time, SDA 20 300 ns
T6 tr(SCL) Rise time, SCL 20 300 ns
T7 tf(SDA) Fall time, SDA 11.4 300 ns
T8 tf(SCL) Fall time, SCL 11.4 300 ns
T9 tsu(SCL-SDA)STOP Setup time, STOP condition, SCL rise before SDA
rise delay 0.6 µs
T10 tw(SP) Pulse duration of spikes that will be suppressed by
filter 0 50 ns
T11 Cbcapacitance load on each bus line 400 pF
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7.12.2.1.2 I2C Switching Characteristics
over recommended operating conditions (unless otherwise noted)
NO. PARAMETER TEST CONDITIONS MIN MAX UNIT
Standard mode
S1 fSCL SCL clock frequency 0 100 kHz
S2 TSCL SCL clock period 10 µs
S3 tw(SCLL) Pulse duration, SCL clock low 4.7 µs
S4 tw(SCLH) Pulse duration, SCL clock high 4.0 µs
S5 tBUF Bus free time between STOP and START
conditions 4.7 µs
S6 tv(SCL-DAT) Valid time, data after SCL fall 3.45 µs
S7 tv(SCL-ACK) Valid time, Acknowledge after SCL fall 3.45 µs
S8 IIInput current on pins 0.1 Vbus < Vi < 0.9 Vbus –10 10 µA
Fast mode
S1 fSCL SCL clock frequency 0 400 kHz
S2 TSCL SCL clock period 2.5 µs
S3 tw(SCLL) Pulse duration, SCL clock low 1.3 µs
S4 tw(SCLH) Pulse duration, SCL clock high 0.6 µs
S5 tBUF Bus free time between STOP and START
conditions 1.3 µs
S6 tv(SCL-DAT) Valid time, data after SCL fall 0.9 µs
S7 tv(SCL-ACK) Valid time, Acknowledge after SCL fall 0.9 µs
S8 IIInput current on pins 0.1 Vbus < Vi < 0.9 Vbus –10 10 µA
7.12.2.1.3
Note
To meet all of the I2C protocol timing specifications, the I2C module clock (Fmod) must be configured
from 7 MHz to 12 MHz.
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S5
T6 T8
T5 T7 S3
S4
S2
START
STOP
SDA
SCL
SDA
SCL
T10S6
9th
clock
S7
Contd...
Contd...
T2
T1
Repeated
START
9th
clock
T9
STOP
ACK
ACK
Figure 7-62. I2C Timing Diagram
TMS320F28379S, TMS320F28378S, TMS320F28377S, TMS320F28377S-Q1
TMS320F28376S, TMS320F28375S, TMS320F28375S-Q1, TMS320F28374S
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I TEXAS INSTRUMENTS
7.12.3 Multichannel Buffered Serial Port (McBSP)
The McBSP module has the following features:
• Compatible with McBSP in TMS320C28x and TMS320F28x DSP devices
• Full-duplex communication
• Double-buffered data registers that allow a continuous data stream
• Independent framing and clocking for receive and transmit
• External shift clock generation or an internal programmable frequency shift clock
• 8-bit data transfer mode can be configured to transmit with LSB or MSB first
• Programmable polarity for both frame synchronization and data clocks
• Highly programmable internal clock and frame generation
• Direct interface to industry-standard CODECs, Analog Interface Chips (AICs), and other serially connected
A/D and D/A devices
• Supports AC97, I2S, and SPI protocols
• McBSP clock rate,
( )
CLKSRG
CLKG =
1 + CLKGDV
where CLKSRG source could be LSPCLK, CLKX, or CLKR.
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Ifimg INsnunngTs 47 Perlphera‘ Wma Bus | | , + F__J‘L__1 L_______J I:|+l: mm |___———I MFSRx |
Figure 7-63 shows the block diagram of the McBSP module.
MDXx
MDRx
Expand Logic
DRR1 Receive Buffer
RX
Interrupt
RBR1 RegisterRBR2 Register
MCLKXx
MFSXx
MCLKRx
MFSRx
16
Compand Logic
DXR2 Transmit Buffer
RSR1
XSR2 XSR1
Peripheral Read Bus
16
16
16
16
16
RSR2
DXR1 Transmit Buffer
PERx.LSPCLK
MRINT
To CPU
RX Interrupt Logic
TX
Interrupt
MXINT
To CPU TX Interrupt Logic
1616
16 16
Peripheral Bus
DRR2 Receive Buffer
Peripheral Write Bus
Bridge
DMA Bus
CPU
CPU
CPU
McBSP Transmit
Interrupt Select Logic
McBSP Receive
Interrupt Select Logic
Figure 7-63. McBSP Block Diagram
TMS320F28379S, TMS320F28378S, TMS320F28377S, TMS320F28377S-Q1
TMS320F28376S, TMS320F28375S, TMS320F28375S-Q1, TMS320F28374S
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7.12.3.1 McBSP Electrical Data and Timing
7.12.3.1.1 McBSP Transmit and Receive Timing
Section 7.12.3.1.1.1 shows the McBSP timing requirements. Section 7.12.3.1.1.2 shows the McBSP switching
characteristics. Figure 7-64 and Figure 7-65 show the McBSP timing diagrams.
7.12.3.1.1.1 McBSP Timing Requirements
NO.(1)
(2) MIN MAX UNIT
McBSP module clock (CLKG, CLKX, CLKR) range 1 kHz
25 MHz
McBSP module cycle time (CLKG, CLKX, CLKR) range 40 ns
1 ms
M11 tc(CKRX) Cycle time, CLKR/X CLKR/X ext 2P ns
M12 tw(CKRX) Pulse duration, CLKR/X high or CLKR/X low CLKR/X ext P – 7 ns
M13 tr(CKRX) Rise time, CLKR/X CLKR/X ext 7 ns
M14 tf(CKRX) Fall time, CLKR/X CLKR/X ext 7 ns
M15 tsu(FRH-CKRL) Setup time, external FSR high before CLKR low CLKR int 18 ns
CLKR ext 2
M16 th(CKRL-FRH) Hold time, external FSR high after CLKR low CLKR int 0 ns
CLKR ext 6
M17 tsu(DRV-CKRL) Setup time, DR valid before CLKR low CLKR int 18 ns
CLKR ext 5
M18 th(CKRL-DRV) Hold time, DR valid after CLKR low CLKR int 0 ns
CLKR ext 3
M19 tsu(FXH-CKXL) Setup time, external FSX high before CLKX low CLKX int 18 ns
CLKX ext 2
M20 th(CKXL-FXH) Hold time, external FSX high after CLKX low CLKX int 0 ns
CLKX ext 6
(1) Polarity bits CLKRP = CLKXP = FSRP = FSXP = 0. If the polarity of any of the signals is inverted, then the timing references of that
signal are also inverted.
(2) 2P = 1/CLKG in ns. CLKG is the output of sample rate generator mux. CLKG = CLKSRG / (1 + CLKGDV). CLKSRG can be LSPCLK,
CLKX, CLKR as source. CLKSRG ≤ (SYSCLK/2).
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7.12.3.1.1.2 McBSP Switching Characteristics
over recommended operating conditions (unless otherwise noted)
NO.(1)
(2) PARAMETER MIN MAX UNIT
M1 tc(CKRX) Cycle time, CLKR/X CLKR/X int 2P ns
M2 tw(CKRXH) Pulse duration, CLKR/X high CLKR/X int D – 5 (3) D + 5 (3) ns
M3 tw(CKRXL) Pulse duration, CLKR/X low CLKR/X int C – 5 (3) C + 5 (3) ns
M4 td(CKRH-FRV) Delay time, CLKR high to internal FSR valid CLKR int -7 7.5 ns
CLKR ext 3 27
M5 td(CKXH-FXV) Delay time, CLKX high to internal FSX valid CLKX int -5 6 ns
CLKX ext 3 27
M6 tdis(CKXH-DXHZ) Disable time, CLKX high to DX high impedance
following last data bit
CLKX int –8 8 ns
CLKX ext 3 15
M7 td(CKXH-DXV)
Delay time, CLKX high to DX valid. CLKX int –3 9
ns
This applies to all bits except the first bit
transmitted. CLKX ext 5 25
Delay time, CLKX high to DX
valid DXENA = 0 CLKX int –3 8
CLKX ext 5 20
Only applies to first bit
transmitted when in Data
Delay 1 or 2 (XDATDLY=01b
or 10b) modes
DXENA = 1
CLKX int P – 3 P + 8
CLKX ext P + 5 P + 20
M8 ten(CKXH-DX)
Enable time, CLKX high to
DX driven DXENA = 0 CLKX int -6
ns
CLKX ext 4
Only applies to first bit
transmitted when in Data
Delay 1 or 2 (XDATDLY=01b
or 10b) modes
DXENA = 1
CLKX int P - 6
CLKX ext P + 4
M9 td(FXH-DXV)
Delay time, FSX high to DX
valid DXENA = 0 FSX int 8
ns
FSX ext 17
Only applies to first bit
transmitted when in Data
Delay 0 (XDATDLY=00b)
mode.
DXENA = 1
FSX int P + 8
FSX ext P + 17
M10 ten(FXH-DX)
Enable time, FSX high to DX
driven DXENA = 0 FSX int -3
ns
FSX ext 6
Only applies to first bit
transmitted when in Data
Delay 0 (XDATDLY=00b)
mode
DXENA = 1
FSX int P - 3
FSX ext P + 6
(1) Polarity bits CLKRP = CLKXP = FSRP = FSXP = 0. If the polarity of any of the signals is inverted, then the timing references of that
signal are also inverted.
(2) 2P = 1/CLKG in ns.
(3) C = CLKRX low pulse width = P
D = CLKRX high pulse width = P
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{5‘ TEXAS INSTRUMENTS F‘
(n−2)Bit (n−1)
(n−3)(n−2)Bit (n−1)
(n−4)(n−3)(n−2)Bit (n−1)
M18
M17
M18
M17
M17
M18
M16
M15
M4
M4 M14
M13
M3, M12
M1, M11
M2, M12
(RDATDLY=10b)
DR
(RDATDLY=01b)
DR
(RDATDLY=00b)
DR
FSR (ext)
FSR (int)
CLKR
Figure 7-64. McBSP Receive Timing
M8
M7
M7
M8
M6
M7
M9
M10
(XDATDLY=10b)
DX
(XDATDLY=01b)
DX
(XDATDLY=00b)
DX
Bit (n−1)Bit 0
Bit (n−1) (n−3)(n−2)Bit 0
(n−2)Bit (n−1)
Bit 0
M20
M13
M3, M12
M1, M11
M2, M12
FSX (ext)
FSX (int)
CLKX
M5
M5
M19
Figure 7-65. McBSP Transmit Timing
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7.12.3.1.2 McBSP as SPI Master or Slave Timing
Section 7.12.3.1.2.1 lists the McBSP as SPI master timing requirements. Section 7.12.3.1.2.2 lists the McBSP as
SPI master switching characteristics. Section 7.12.3.1.2.3 lists the McBSP as SPI slave timing requirements.
Section 7.12.3.1.2.4 lists the McBSP as SPI slave switching characteristics.
Figure 7-66 through Figure 7-69 show the McBSP as SPI master or slave timing diagrams.
7.12.3.1.2.1 McBSP as SPI Master Timing Requirements
NO. MIN MAX UNIT
CLOCK
tc(CLKG) Cycle time, CLKG(1) 2 * tc(LSPCLK) ns
P Cycle time, LSPCLK(1) tc(LSPCLK) ns
M33,
M42,
M52,
M61
tc(CKX) Cycle time, CLKX 2P ns
CLKSTP = 10b, CLKXP = 0
M30 tsu(DRV-CKXL) Setup time, DR valid before CLKX low 30 ns
M31 th(CKXL-DRV) Hold time, DR valid after CLKX low 1 ns
CLKSTP = 11b, CLKXP = 0
M39 tsu(DRV-CKXH) Setup time, DR valid before CLKX high 30 ns
M40 th(CKXH-DRV) Hold time, DR valid after CLKX high 1 ns
CLKSTP = 10b, CLKXP = 1
M49 tsu(DRV-CKXH) Setup time, DR valid before CLKX high 30 ns
M50 th(CKXH-DRV) Hold time, DR valid after CLKX high 1 ns
CLKSTP = 11b, CLKXP = 1
M58 tsu(DRV-CKXL) Setup time, DR valid before CLKX low 30 ns
M59 th(CKXL-DRV) Hold time, DR valid after CLKX low 1 ns
(1) CLKG should be configured to LSPCLK/2 by setting CLKSM = 1 and CLKGDV = 1
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TEXAS INSTRUMENTS
7.12.3.1.2.2 McBSP as SPI Master Switching Characteristics
over operating free-air temperature range (unless otherwise noted)
NO. PARAMETER MIN TYP MAX UNIT
CLOCK
M33 tc(CLKG) Cycle time, CLKG(1) (n * tc(LSPCLK)) 40 ns
P Half CLKG cycle; 0.5 * tc(CLKG) 20 ns
n LSPCLK to CLKG divider 2 ns
CLKSTP = 10b, CLKXP = 0
M24 th(CKXL-FXL) Hold time, FSX high after CLKX low 2P – 6 ns
M25 td(FXL-CKXH) Delay time, FSX low to CLKX high P – 6 ns
M26 td(CLKXH-DXV) Delay time, CLKX high to DX valid –4 6 ns
M28 tdis(FXH-DXHZ) Disable time, DX high impedance following last data bit from
CLKX low P – 8 ns
M29 td(FXL-DXV) Delay time, FSX low to DX valid P – 3 P + 6 ns
CLKSTP = 11b, CLKXP = 0
M34 th(CKXL-FXH) Hold time, FSX high after CLKX low P – 6 ns
M35 td(FXL-CKXH) Delay time, FSX low to CLKX high P – 6 ns
M36 td(CLKXL-DXV) Delay time, CLKX low to DX valid –4 6 ns
M37 tdis(CKXL-DXHZ) Disable time, DX high impedance following last data bit from
CLKX low P – 6 ns
M38 td(FXL-DXV) Delay time, FSX low to DX valid –2 1 ns
CLKSTP = 10b, CLKXP = 1
M43 th(CKXH-FXH) Hold time, FSX high after CLKX high 2P – 6 ns
M44 td(FXL-CKXL) Delay time, FSX low to CLKX low P – 6 ns
M45 td(CLKXL-DXV) Delay time, CLKX low to DX valid –4 6 ns
M47 tdis(FXH-DXHZ) Disable time, DX high impedance following last data bit from
CLKX low P – 6 ns
M48 td(FXL-DXV) Delay time, FSX low to DX valid –2 1 ns
CLKSTP = 11b, CLKXP = 1
M53 th(CKXH-FXH) Hold time, FSX high after CLKX high P – 6 ns
M54 td(FXL-CKXL) Delay time, FSX low to CLKX low 2P – 6 ns
M55 td(CLKXH-DXV) Delay time, CLKX high to DX valid –4 6 ns
M56 tdis(CKXH-DXHZ) Disable time, DX high impedance following last data bit from
CLKX high P – 8 ns
M57 td(FXL-DXV) Delay time, FSX low to DX valid –2 1 ns
(1) CLKG should be configured to LSPCLK/2 by setting CLKSM = 1 and CLKGDV = 1.
7.12.3.1.2.3 McBSP as SPI Slave Timing Requirements
NO. MIN MAX UNIT
CLOCK
tc(CLKG) Cycle time, CLKG(1) 2 * tc(LSPCLK) ns
P Cycle time, LSPCLK(1) tc(LSPCLK) ns
M33,
M42,
M52,
M61
tc(CKX) Cycle time, CLKX(2) 16P ns
CLKSTP = 10b, CLKXP = 0
M30 tsu(DRV-CKXL) Setup time, DR valid before CLKX low 8P – 10 ns
M31 th(CKXL-DRV) Hold time, DR valid after CLKX low 8P – 10 ns
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TEXAS INSTRUMENTS
NO. MIN MAX UNIT
M32 tsu(BFXL-CKXH) Setup time, FSX low before CLKX high 8P+10 ns
CLKSTP = 11b, CLKXP = 0
M39 tsu(DRV-CKXH) Setup time, DR valid before CLKX high 8P – 10 ns
M40 th(CKXH-DRV) Hold time, DR valid after CLKX high 8P – 10 ns
M41 tsu(FXL-CKXH) Setup time, FSX low before CLKX high 16P+10 ns
CLKSTP = 10b, CLKXP = 1
M49 tsu(DRV-CKXH) Setup time, DR valid before CLKX high 8P – 10 ns
M50 th(CKXH-DRV) Hold time, DR valid after CLKX high 8P – 10 ns
M51 tsu(FXL-CKXL) Setup time, FSX low before CLKX low 8P+10 ns
CLKSTP = 11b, CLKXP = 1
M58 tsu(DRV-CKXL) Setup time, DR valid before CLKX low 8P – 10 ns
M59 th(CKXL-DRV) Hold time, DR valid after CLKX low 8P – 10 ns
M60 tsu(FXL-CKXL) Setup time, FSX low before CLKX low 16P+10 ns
(1) CLKG should be configured to LSPCLK/2 by setting CLKSM = 1 and CLKGDV = 1
(2) For SPI slave modes CLKX must be a minimum of 8 CLKG cycles
7.12.3.1.2.4 McBSP as SPI Slave Switching Characteristics
over operating free-air temperature range (unless otherwise noted)
NO. PARAMETER MIN TYP MAX UNIT
CLOCK
2P Cycle time, CLKG ns
CLKSTP = 10b, CLKXP = 0
M26 td(CLKXH-DXV) Delay time, CLKX high to DX valid 3P + 6 5P + 20 ns
M28 tdis(FXH-DXHZ) Disable time, DX high impedance following last data bit from
FSX high 6P + 6 ns
M29 td(FXL-DXV) Delay time, FSX low to DX valid 4P + 6 ns
CLKSTP = 11b, CLKXP = 0
M36 td(CLKXL-DXV) Delay time, CLKX low to DX valid 3P + 6 5P + 20 ns
M37 tdis(CKXL-DXHZ) Disable time, DX high impedance following last data bit from
CLKX low 7P + 6 ns
M38 td(FXL-DXV) Delay time, FSX low to DX valid 4P + 6 ns
CLKSTP = 10b, CLKXP = 1
M45 td(CLKXL-DXV) Delay time, CLKX low to DX valid 3P + 6 5P + 20 ns
M47 tdis(FXH-DXHZ) Disable time, DX high impedance following last data bit from
FSX high 6P + 6 ns
M48 td(FXL-DXV) Delay time, FSX low to DX valid 4P + 6 ns
CLKSTP = 11b, CLKXP = 1
M55 td(CLKXH-DXV) Delay time, CLKX high to DX valid 3P + 6 5P + 20 ns
M56 tdis(CKXH-DXHZ) Disable time, DX high impedance following last data bit from
CLKX high 7P + 6 ns
M57 td(FXL-DXV) Delay time, FSX low to DX valid 4P + 6 ns
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Bit 0 Bit(n-1) (n-2) (n-3) (n-4)
Bit 0 Bit(n-1) (n-2) (n-3) (n-4)
CLKX
FSX
DX
M30 M31
DR
M24
M29
M25
LSB MSB
M32 M33
M28 M26
Figure 7-66. McBSP Timing as SPI Master or Slave: CLKSTP = 10b, CLKXP = 0
Bit 0 Bit(n-1) (n-2) (n-3) (n-4)
Bit 0 Bit(n-1) (n-2) (n-3) (n-4)
CLKX
FSX
DX
DR
M35
M37
M40
M39
M38
M34
LSB MSB
M41 M42
M36
Figure 7-67. McBSP Timing as SPI Master or Slave: CLKSTP = 11b, CLKXP = 0
M51
M50
Bit 0 Bit(n-1) (n-2) (n-3) (n-4)
Bit 0 Bit(n-1) (n-2) (n-3) (n-4)
CLKX
FSX
DX
DR
M44
M48
M49
M43
LSB MSB M52
M47 M45
Figure 7-68. McBSP Timing as SPI Master or Slave: CLKSTP = 10b, CLKXP = 1
Bit 0 Bit(n-1) (n-2) (n-3) (n-4)
Bit 0 Bit(n-1) (n-2) (n-3) (n-4)
CLKX
FSX
DX
DR
M54
M58
M56
M53
M55
M59
M57
LSB MSB
M60 M61
Figure 7-69. McBSP Timing as SPI Master or Slave: CLKSTP = 11b, CLKXP = 1
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7.12.4 Serial Communications Interface (SCI)
The SCI is a 2-wire asynchronous serial port, commonly known as a UART. The SCI module supports digital
communications between the CPU and other asynchronous peripherals that use the standard non-return-to-zero
(NRZ) format
The SCI receiver and transmitter each have a 16-level-deep FIFO for reducing servicing overhead, and each has
its own separate enable and interrupt bits. Both can be operated independently for half-duplex communication,
or simultaneously for full-duplex communication. To specify data integrity, the SCI checks received data for break
detection, parity, overrun, and framing errors. The bit rate is programmable to different speeds through a 16-bit
baud-select register. Figure 7-70 shows the SCI block diagram.
Features of the SCI module include:
• Two external pins:
– SCITXD: SCI transmit-output pin
– SCIRXD: SCI receive-input pin
Note
NOTE: Both pins can be used as GPIO if not used for SCI.
– Baud rate programmable to 64K different rates
• Data-word format
– One start bit
– Data-word length programmable from 1 to 8 bits
– Optional even/odd/no parity bit
– 1 or 2 stop bits
• Four error-detection flags: parity, overrun, framing, and break detection
• Two wakeup multiprocessor modes: idle-line and address bit
• Half- or full-duplex operation
• Double-buffered receive and transmit functions
• Transmitter and receiver operations can be accomplished through interrupt-driven or polled algorithms with
status flags.
– Transmitter: TXRDY flag (transmitter-buffer register is ready to receive another character) and TX EMPTY
flag (transmitter-shift register is empty)
– Receiver: RXRDY flag (receiver-buffer register is ready to receive another character), BRKDT flag (break
condition occurred), and RX ERROR flag (monitoring four interrupt conditions)
• Separate enable bits for transmitter and receiver interrupts (except BRKDT)
• NRZ format
• Auto baud-detect hardware logic
• 16-level transmit and receive FIFO
Note
All registers in this module are 8-bit registers. When a register is accessed, the register data is in the
lower byte (bits 7–0), and the upper byte (bits 15–8) is read as zeros. Writing to the upper byte has no
effect.
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TXSHF
Register
TX FIFO_0
TX FIFO_1
TX FIFO_N
8
8
Transmit Data
Buffer Register
SCITXBUF.7-0
RXSHF
Register
RX FIFO_0
RX FIFO_1
RX FIFO_N
8
Receive Data
Buffer Register
SCIRXBUF.7-0
RXENA
SCICTL1.0
8
TX FIFO Interrupts
RX FIFO Interrupts
Baud Rate
MSB/LSB
Registers
SCIHBAUD.15-8
SCILBAUD.7-0
LSPCLK
Frame
Format and Mode
Parity
SCICCR.6
SCICCR.5
Even/Odd
Enable
SCICTL1.3
TXWAKE
WUT
SCICTL1.1
TXENA
RXENA
SCICTL2.6
TXEMPTY
RXFFOVF
SCICTL2.7
TXRDY SCICTL2.0
TXINTENA
SCIRXST.6
RXRDY
SCIRXST.5
BRKDT
SCICTL2.1
RXBKINTENA
TX Interrupt
Logic
RX Interrupt
Logic
SCIRXST.7
RXERROR
SCICTL1.6
RXERRINTENA
SCI RX Interrupt Select Logic
8
8
8
8
8
8
01
01
01
01
SCIFFENA
SCIFFTX.14
RXWAKE
SCIRXST.1
Auto Baud Detect Logic
TXINT
To CPU
RXINT
To CPU
SCITXD
SCIRXD
BRKDT FE OE PE
SCIRXST.5-2
8
SCICTL1.0
SCIFFRX.15
SCI TX Interrupt Select Logic
Figure 7-70. SCI Block Diagram
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The major elements used in full-duplex operation include:
• A transmitter (TX) and its major registers:
– SCITXBUF register – Transmitter Data Buffer register. Contains data (loaded by the CPU) to be
transmitted
– TXSHF register – Transmitter Shift register. Accepts data from the SCITXBUF register and shifts data onto
the SCITXD pin, 1 bit at a time
• A receiver (RX) and its major registers:
– RXSHF register – Receiver Shift register. Shifts data in from the SCIRXD pin, 1 bit at a time
– SCIRXBUF register – Receiver Data Buffer register. Contains data to be read by the CPU. Data from a
remote processor is loaded into the RXSHF register and then into the SCIRXBUF and SCIRXEMU
registers
• A programmable baud generator
• Data-memory-mapped control and status registers enable the CPU to access the I2C module registers and
FIFOs.
The SCI receiver and transmitter operate independently.
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7.12.5 Serial Peripheral Interface (SPI)
The SPI is a high-speed synchronous serial input/output (I/O) port that allows a serial bit stream of programmed
length (1 to 16 bits) to be shifted into and out of the device at a programmed bit-transfer rate. The SPI is
normally used for communications between the microcontroller and external peripherals or another controller.
Typical applications include external I/O or peripheral expansion through devices such as shift registers, display
drivers, and ADCs. Multidevice communications are supported by the master/slave operation of the SPI. The
port supports 16-level receive and transmit FIFOs for reducing CPU servicing overhead.
The SPI module features include:
• SPISOMI: SPI slave-output/master-input pin
• SPISIMO: SPI slave-input/master-output pin
• SPISTE: SPI slave transmit-enable pin
• SPICLK: SPI serial-clock pin
• Two operational modes: master and slave
• Baud rate: 125 different programmable rates
• Data word length: 1 to 16 data bits
• Four clocking schemes (controlled by clock polarity and clock phase bits) include:
– Falling edge without phase delay: SPICLK active-high. SPI transmits data on the falling edge of the
SPICLK signal and receives data on the rising edge of the SPICLK signal.
– Falling edge with phase delay: SPICLK active-high. SPI transmits data one half-cycle ahead of the falling
edge of the SPICLK signal and receives data on the falling edge of the SPICLK signal.
– Rising edge without phase delay: SPICLK inactive-low. SPI transmits data on the rising edge of the
SPICLK signal and receives data on the falling edge of the SPICLK signal.
– Rising edge with phase delay: SPICLK inactive-low. SPI transmits data one half-cycle ahead of the rising
edge of the SPICLK signal and receives data on the rising edge of the SPICLK signal.
• Simultaneous receive-and-transmit operation (transmit function can be disabled in software)
• Transmitter and receiver operations are accomplished through either interrupt-driven or polled algorithms.
• 16-level transmit and receive FIFO
• Delayed transmit control
• 3-wire SPI mode
• SPISTE inversion for digital audio interface receive mode on devices with two SPI modules
• DMA support
• High-speed mode for up to 50-MHz full-duplex communication
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The SPI operates in master or slave mode. The master initiates data transfer by sending the SPICLK signal. For
both the slave and the master, data is shifted out of the shift registers on one edge of the SPICLK and latched
into the shift register on the opposite SPICLK clock edge. If the CLOCK PHASE bit (SPICTL.3) is high, data is
transmitted and received a half-cycle before the SPICLK transition. As a result, both controllers send and receive
data simultaneously. The application software determines whether the data is meaningful or dummy data. There
are three possible methods for data transmission:
• Master sends data; slave sends dummy data
• Master sends data; slave sends data
• Master sends dummy data; slave sends data
The master can initiate a data transfer at any time because it controls the SPICLK signal. The software,
however, determines how the master detects when the slave is ready to broadcast data.
Figure 7-71 shows the SPI CPU Interface.
SPISIMO
SPISOMI
SPICLK
SPISTE
SPI
Low-Speed
Prescaler
DMA
PIE
LSPCLK SYSCLK
SYSRS
SPIINT
SPITXINT
SPIRXDMA
SPITXDMA
Peripheral Bus
CPU
PCLKCR8
GPIO
MUX
Bit
Clock
Figure 7-71. SPI CPU Interface
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7.12.5.1 SPI Electrical Data and Timing
Note
All timing parameters for SPI High-Speed Mode assume a load capacitance of 5 pF on SPICLK,
SPISIMO, and SPISOMI.
For more information about the SPI in High-Speed mode, see the Serial Peripheral Interface (SPI) chapter of the
TMS320F2837xS Microcontrollers Technical Reference Manual .
To use the SPI in High-Speed mode, the application must use the high-speed enabled GPIOs (see Section
6.4.5).
7.12.5.1.1 SPI Master Mode Timings
Section 7.12.5.1.1.1 lists the SPI master mode timing requirements. Section 7.12.5.1.1.2 lists the SPI master
mode switching characteristics (clock phase = 0). Section 7.12.5.1.1.3 lists the SPI master mode switching
characteristics (clock phase = 1). Figure 7-72 shows the SPI master mode external timing where the clock phase
= 0. Figure 7-73 shows the SPI master mode external timing where the clock phase = 1.
7.12.5.1.1.1 SPI Master Mode Timing Requirements
NO. (BRR + 1)
CONDITION(1) MIN MAX UNIT
High Speed Mode
8 tsu(SOMI)M Setup time, SPISOMI valid before
SPICLK Even, Odd 1 ns
9 th(SOMI)M Hold time, SPISOMI valid after
SPICLK Even, Odd 5 ns
Normal Mode
8 tsu(SOMI)M Setup time, SPISOMI valid before
SPICLK Even, Odd 20 ns
9 th(SOMI)M Hold time, SPISOMI valid after
SPICLK Even, Odd 0 ns
(1) The (BRR + 1) condition is Even when (SPIBRR + 1) is even or SPIBRR is 0 or 2. It is Odd when (SPIBRR + 1) is odd and SPIBRR is
greater than 3.
7.12.5.1.1.2 SPI Master Mode Switching Characteristics (Clock Phase = 0)
over recommended operating conditions (unless otherwise noted)
NO. PARAMETER (BRR + 1)
CONDITION(1) MIN MAX UNIT
General
1 tc(SPC)M Cycle time, SPICLK Even 4tc(LSPCLK) 128tc(LSPCLK) ns
Odd 5tc(LSPCLK) 127tc(LSPCLK)
2 tw(SPC1)M Pulse duration, SPICLK, first pulse
Even 0.5tc(SPC)M – 1 0.5tc(SPC)M + 1
ns
Odd 0.5tc(SPC)M +0.5tc(LSPCLK)
– 1
0.5tc(SPC)M +0.5tc(LSPCLK)
+ 1
3 tw(SPC2)M Pulse duration, SPICLK, second
pulse
Even 0.5tc(SPC)M – 1 0.5tc(SPC)M + 1
ns
Odd 0.5tc(SPC)M –0.5tc(LSPCLK) –
1
0.5tc(SPC)M –0.5tc(LSPCLK)
+ 1
23 td(SPC)M Delay time, SPISTE active to SPICLK
Even 1.5tc(SPC)M - 3tc(SYSCLK) –
7
1.5tc(SPC)M - 3tc(SYSCLK) +
5ns
Odd 1.5tc(SPC)M - 4tc(SYSCLK) –
7
1.5tc(SPC)M - 4tc(SYSCLK) +
5
24 tv(STE)M Valid time, SPICLK to SPISTE
inactive
Even 0.5tc(SPC)M – 7 0.5tc(SPC)M + 5
ns
Odd 0.5tc(SPC)M –0.5tc(LSPCLK) –
7
0.5tc(SPC)M –0.5tc(LSPCLK)
+ 5
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over recommended operating conditions (unless otherwise noted)
NO. PARAMETER (BRR + 1)
CONDITION(1) MIN MAX UNIT
High Speed Mode
4 td(SIMO)M Delay time, SPICLK to SPISIMO valid Even, Odd 1 ns
5 tv(SIMO)M Valid time, SPISIMO valid after
SPICLK
Even 0.5tc(SPC)M – 2
ns
Odd 0.5tc(SPC)M –0.5tc(LSPCLK) –
2
Normal Mode
4 td(SIMO)M Delay time, SPICLK to SPISIMO valid Even, Odd 6 ns
5 tv(SIMO)M Valid time, SPISIMO valid after
SPICLK
Even 0.5tc(SPC)M – 5
ns
Odd 0.5tc(SPC)M –0.5tc(LSPCLK) –
5
(1) The (BRR + 1) condition is Even when (SPIBRR + 1) is even or SPIBRR is 0 or 2. It is Odd when (SPIBRR + 1) is odd and SPIBRR is
greater than 3.
7.12.5.1.1.3 SPI Master Mode Switching Characteristics (Clock Phase = 1)
over recommended operating conditions (unless otherwise noted)
NO. PARAMETER (BRR + 1)
CONDITION(1) MIN MAX UNIT
General
1 tc(SPC)M Cycle time, SPICLK Even 4tc(LSPCLK) 128tc(LSPCLK) ns
Odd 5tc(LSPCLK) 127tc(LSPCLK)
2 tw(SPCH)M Pulse duration, SPICLK, first
pulse
Even 0.5tc(SPC)M – 1 0.5tc(SPC)M + 1
ns
Odd 0.5tc(SPC)M – 0.5tc(LSPCLK) – 1 0.5tc(SPC)M –
0.5tc(LSPCLK) + 1
3 tw(SPC2)M Pulse duration, SPICLK,
second pulse
Even 0.5tc(SPC)M – 1 0.5tc(SPC)M + 1
ns
Odd 0.5tc(SPC)M + 0.5tc(LSPCLK) – 1 0.5tc(SPC)M +
0.5tc(LSPCLK) + 1
23 td(SPC)M Delay time, SPISTE valid to
SPICLK Even, Odd 2tc(SPC)M – 3tc(SYSCLK) – 7 2tc(SPC)M –
3tc(SYSCLK) + 5 ns
24 tv(STE)M Valid time, SPICLK to SPISTE
invalid
Even – 7 +5 ns
Odd – 7 +5
High Speed Mode
4 td(SIMO)M Delay time, SPISIMO valid to
SPICLK
Even 0.5tc(SPC)M – 1 ns
Odd 0.5tc(SPC)M + 0.5tc(LSPCLK) – 1
5 tv(SIMO)M Valid time, SPISIMO valid after
SPICLK
Even 0.5tc(SPC)M – 2 ns
Odd 0.5tc(SPC)M – 0.5tc(LSPCLK) – 2
Normal Mode
4 td(SIMO)M Delay time, SPISIMO valid to
SPICLK
Even 0.5tc(SPC)M – 5 ns
Odd 0.5tc(SPC)M + 0.5tc(LSPCLK) – 5
5 tv(SIMO)M Valid time, SPISIMO valid after
SPICLK
Even 0.5tc(SPC)M – 5 ns
Odd 0.5tc(SPC)M – 0.5tc(LSPCLK) – 5
(1) The (BRR + 1) condition is Even when (SPIBRR + 1) is even or SPIBRR is 0 or 2. It is Odd when (SPIBRR + 1) is odd and SPIBRR is
greater than 3.
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I TEXAS INSTRUMENTS H——N 4 if: 4 ¥ \ \ \ :1 k4 \ » \ wowwo — owwwo' wowwwowow 2o2o22¢2¢2o22o2 %2o%2o2o22o2o202o2o2o2o2¢2o2222.22.222.32 ‘ ‘ W 1 ‘ \ 1 1 \ H , WWW... ,",."ww“wwwww mmzmw mama:t:2222.2.2222.2.2.22. 4F w‘P y_ Q 9 ‘ 2o2o2¢2o2¢2¢2¢2¢2¢2¢2o2 2229292929202o2¢2o2¢2¢2¢2¢2¢2o2o2¢2§2¢2¢2¢2¢2¢2¢2220202229292 ,F OVVVVVVVV'O'O'OVVVVVVVV 2§$202.2.2.2¢2¢2¢2¢”0292929292922 “on 4 i f i Vvovwv vow. 222.202.2929. 29292.20‘
9
4
SPISOMI
SPISIMO
SPICLK
(clock polarity = 1)
SPICLK
(clock polarity = 0)
Master In Data
Must Be Valid
8
Master Out Data Is Valid
3
2
1
SPISTE(A)
5
23 24
A. On the trailing end of the word, SPISTE will go inactive except between back-to-back transmit words in both FIFO and non-FIFO modes.
Figure 7-72. SPI Master Mode External Timing (Clock Phase = 0)
9
SPISOMI
SPISIMO
SPICLK
(clock polarity = 1)
SPICLK
(clock polarity = 0)
Master In Data Must
Be Valid
Master Out Data Is Valid
1
5
4
8
3
2
23 24
SPISTE(A)
A. On the trailing end of the word, SPISTE will go inactive except between back-to-back transmit words in both FIFO and non-FIFO modes.
Figure 7-73. SPI Master Mode External Timing (Clock Phase = 1)
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7.12.5.1.2 SPI Slave Mode Timings
Section 7.12.5.1.2.1 lists the SPI slave mode timing requirements. Section 7.12.5.1.2.2 lists the SPI slave mode
switching characteristics. Figure 7-74 shows the SPI slave mode external timing where the clock phase = 0.
Figure 7-75 shows the SPI slave mode external timing where the clock phase = 1.
7.12.5.1.2.1 SPI Slave Mode Timing Requirements
NO. MIN MAX UNIT
12 tc(SPC)S Cycle time, SPICLK 4tc(SYSCLK) ns
13 tw(SPC1)S Pulse duration, SPICLK, first pulse 2tc(SYSCLK) – 1 ns
14 tw(SPC2)S Pulse duration, SPICLK, second pulse 2tc(SYSCLK) – 1 ns
19 tsu(SIMO)S Setup time, SPISIMO valid before SPICLK 1.5tc(SYSCLK) ns
20 th(SIMO)S Hold time, SPISIMO valid after SPICLK 1.5tc(SYSCLK) ns
25 tsu(STE)S
Setup time, SPISTE valid before
SPICLK (Clock Phase = 0) 2tc(SYSCLK) + 4 ns
Setup time, SPISTE valid before
SPICLK (Clock Phase = 1) 2tc(SYSCLK) + 14 ns
26 th(STE)S Hold time, SPISTE invalid after SPICLK 1.5tc(SYSCLK) ns
7.12.5.1.2.2 SPI Slave Mode Switching Characteristics
over recommended operating conditions (unless otherwise noted)
NO. PARAMETER MIN MAX UNIT
High Speed Mode
15 td(SOMI)S Delay time, SPICLK to SPISOMI valid 9 ns
16 tv(SOMI)S Valid time, SPISOMI valid after SPICLK 0 ns
Normal Mode
15 td(SOMI)S Delay time, SPICLK to SPISOMI valid 20 ns
16 tv(SOMI)S Valid time, SPISOMI valid after SPICLK 0 ns
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I TEXAS INSTRUMENTS H— —>1 1% fi1 1 1 1 1 1 11P fl‘ 1 1 1 W141 H 1 1 1 1 1 4V1 f 1 1 5C1 1 1 w *1 ‘ 1 1 1 H 1 VO'OV'O'O'O'OV‘O'W O'O'O'O'OV'O'O'O'W'OVWW'W'O'OV'W‘O'O‘W‘O' 2.2.2.2.2.22.2.2.2.2¢ '¢.2¢.2.2¢.2a2.2¢.2¢2¢222.222222. 41 w 4 w {I 1 1 X X 1 H 4’1 1‘7 1 1 1—1 1 W W
20
15
SPISIMO
SPISOMI
SPICLK
(clock polarity = 1)
SPICLK
(clock polarity = 0)
SPISIMO Data
Must Be Valid
SPISOMI Data Is Valid
19
25
16
14
12
SPISTE
26
13
Figure 7-74. SPI Slave Mode External Timing (Clock Phase = 0)
20
SPISIMO
SPISOMI
SPICLK
(clock polarity = 1)
SPICLK
(clock polarity = 0)
SPISIMO Data
Must Be Valid
SPISOMI Data Is Valid
19 16
15
SPISTE
Data ValidData Valid
14
13
12
25 26
Figure 7-75. SPI Slave Mode External Timing (Clock Phase = 1)
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TMS320F28379S, TMS320F28378S, TMS320F28377S, TMS320F28377S-Q1
TMS320F28376S, TMS320F28375S, TMS320F28375S-Q1, TMS320F28374S
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I TEXAS INSTRUMENTS 4» Cull oller ‘—' |:| |:| l | l—l |—l |—l m andD-
7.12.6 Universal Serial Bus (USB) Controller
The USB controller operates as a full-speed or low-speed function controller during point-to-point
communications with USB host or device functions.
The USB module has the following features:
• USB 2.0 full-speed and low-speed operation
• Integrated PHY
• Three transfer types: control, interrupt, and bulk
• 32 endpoints
– One dedicated control IN endpoint and one dedicated control OUT endpoint
– 15 configurable IN endpoints and 15 configurable OUT endpoints
• 4KB of dedicated endpoint memory
Figure 7-76 shows the USB block diagram.
Packet
Encode/Decode
Endpoint Control
EP0 –31
Control
Transmit
Receive
Combine
Endpoints
Host
Transaction
Scheduler
Packet Encode
Packet Decode
CRC Gen/Check
FIFO RAM
Controller
Cycle Control
Rx
Buff
Rx
Buff
Tx
Buff
Tx
Buff
CPU Interface
Interrupt
Control
EP Reg.
Decoder
Common
Regs
Cycle
Control
FIFO
Decoder
Interrupts
CPU Bus
UTM
Synchronization
Data Sync
HNP/SRP
Timers
USB FS/LS
PHY
USB DataLines
D+ andD-
Figure 7-76. USB Block Diagram
Note
The accuracy of the on-chip zero-pin oscillator (Section 7.9.3.5.1, Internal Oscillator Electrical
Characteristics) will not meet the accuracy requirements of the USB protocol. An external clock source
must be used for applications using USB. For applications using the USB boot mode, see Section 8.9
(Boot ROM and Peripheral Booting) for clock frequency requirements.
TMS320F28379S, TMS320F28378S, TMS320F28377S, TMS320F28377S-Q1
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I TEXAS INSTRUMENTS
7.12.6.1 USB Electrical Data and Timing
Section 7.12.6.1.1 shows the USB input ports DP and DM timing requirements. Section 7.12.6.1.2 shows the
USB output ports DP and DM switching characteristics.
7.12.6.1.1 USB Input Ports DP and DM Timing Requirements
MIN MAX UNIT
V(CM) Differential input common mode range 0.8 2.5 V
Z(IN) Input impedance 300 kΩ
VCRS Crossover voltage 1.3 2.0 V
VIL Static SE input logic-low level 0.8 V
VIH Static SE input logic-high level 2.0 V
VDI Differential input voltage 0.2 V
7.12.6.1.2 USB Output Ports DP and DM Switching Characteristics
over recommended operating conditions (unless otherwise noted)
PARAMETER TEST CONDITIONS MIN MAX UNIT
VOH D+, D– single-ended USB 2.0 load conditions 2.8 3.6 V
VOL D+, D– single-ended USB 2.0 load conditions 0 0.3 V
Z(DRV) D+, D– impedance 28 44 Ω
trRise time Full speed, differential, CL = 50 pF, 10%/90%,
Rpu on D+ 4 20 ns
tfFall time Full speed, differential, CL = 50 pF, 10%/90%,
Rpu on D+ 4 20 ns
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TEXAS INSTRUMENTS Hm TNT
7.12.7 Universal Parallel Port (uPP) Interface
The uPP interface is a high-speed parallel interface with dedicated data lines and minimal control signals. The
uPP interface is designed to interface cleanly with high-speed ADCs or DACs with 8-bit data width. It can also be
interconnected with field-programmable gate arrays (FPGAs) or other uPP devices to achieve high-speed digital
data transfer. It can operate in receive mode or transmit mode (simplex mode).
The uPP interface includes an internal DMA controller to maximize throughput and minimize CPU overhead
during high-speed data transmission. All uPP transactions use internal DMA to feed data to or retrieve data from
the I/O channels. Even though there is only one I/O channel, the DMA controller includes two DMA channels to
support data interleave mode, in which all DMA resources service a single I/O channel.
On this device, the uPP interface is the dedicated resource for the CPU1 subsystem. CPU1, CPU1.CLA1, and
CPU1.DMA have access to this module. Two dedicated 512-byte data RAMs (also known as MSG RAMs) are
tightly coupled with the uPP module (one for each, TX and RX). These data RAMs are used to store the bulk of
data to avoid frequent interruptions to the CPU. Only CPU1 and CPU1.CLA1 have access to these data RAMs.
Figure 7-77 shows the integration of the uPP on this device.
CPU1.CLA1
CPU1.DMA
Arbi
t
Arbiter X
SECMSEL.PF2SEL
uPP
(Universal
Parallel Port)
RX-DATARAM
512 Byte
(Dual Port
Memory)
TX-DATARAM
512 Byte
(Dual Port
Memory)
Arbi
t
CPU1
Arbiter Y
0
1
Arbi
t
Arbiter Y
CPU1
CPU1.CLA1
CPU1
CPU1.CLA1
WRITE
READ
I/O Interface
uPP DMA READ
uPP DMA WRITE
Figure 7-77. uPP Integration
Note
On some TI devices, the uPP module is also called the Radio Peripheral Interface (RPI) module.
TMS320F28379S, TMS320F28378S, TMS320F28377S, TMS320F28377S-Q1
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The uPP interface supports the following:
• Mainstream high-speed data converters with parallel conversion interface.
• Mainstream high-speed streaming interface with frame START indication.
• Mainstream high-speed streaming interface with data ENABLE indication.
• Mainstream high-speed streaming interface with synchronization WAIT signal.
• SDR (single-data-rate) or DDR (double-data-rate, interleaved) interface.
• Multiplexing of interleaved data in SDR transmit case.
• Demultiplexing and multiplexing of interleaved data in DDR case.
• I/O interface clock frequency up to 50 MHz for SDR, and 25 MHz for DDR.
• Single-channel 8-bit input receive or output transmit mode.
• Max throughput is 50MB/s for pure read or pure write.
• Available as a DSP to FPGA general-purpose streaming interface.
Figure 7-78 shows the uPP functional block diagram.
Arbit
Internal
DMA
Arbi
t
I-FIFO
Arbi
Q-FIFO
Data Interleaving
(TX/RX)
64 Bit
MEM WR I/F
64 Bit
MEM RD I/F
Transmit Timing
and Control
CLKDIVIDER
CPU1.SYSCLK
Receive Timing
and Control
Interrupt/Trigger
Configuration
I/F
G
P
I
O
M
U
X
and
I/O
C
O
N
T
R
O
L
ENABLE OUT
START OUT
WAIT IN
ENABLE IN
START IN
WAIT OUT
ENABLE/GPIOx
START/GPIOx
WAIT/GPIOx
CLK OUT
CLK IN
CLK/GPIOx
DATA OUT
DATA IN
DATA[7:0]/GPIOx
uPP
Control Mux
MMR
Figure 7-78. uPP Functional Block Diagram
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TEXAS INSTRUMENTS
7.12.7.1 uPP Electrical Data and Timing
Section 7.12.7.1.1 shows the uPP timing requirements. Section 7.12.7.1.2 shows the uPP switching
characteristics. Figure 7-79 through Figure 7-82 show the uPP timing diagrams.
7.12.7.1.1 uPP Timing Requirements
NO. MIN MAX UNIT
1 tc(CLK) Cycle time, CLK SDR mode 20 ns
DDR mode 40
2 tw(CLKH) Pulse width, CLK high SDR mode 8 ns
DDR mode 18
3 tw(CLKL) Pulse width, CLK low SDR mode 8 ns
DDR mode 18
4 tsu(STV-CLKH) Setup time, START valid before CLK high 4 ns
5 th(CLKH-STV) Hold time, START valid after CLK high 0.8 ns
6 tsu(ENV-CLKH) Setup time, ENABLE valid before CLK high 4 ns
7 th(CLKH-ENV) Hold time, ENABLE valid after CLK high 0.8 ns
8 tsu(DV-CLKH) Setup time, DATA valid before CLK high 4 ns
9 th(CLKH-DV) Hold time, DATA valid after CLK high 0.8 ns
10 tsu(DV-CLKL) Setup time, DATA valid before CLK low 4 ns
11 th(CLKL-DV) Hold time, DATA valid after CLK low 0.8 ns
19 tsu(WTV-CLKH) Setup time, WAIT valid before CLK high SDR mode 20 ns
20 th(CLKH-WTV) Hold time, WAIT valid after CLK high SDR mode 0 ns
21 tsu(WTV-CLKL) Setup time, WAIT valid before CLK low DDR mode 20 ns
22 th(CLKL-WTV) Hold time, WAIT valid after CLK low DDR mode 0 ns
7.12.7.1.2 uPP Switching Characteristics
over recommended operating conditions (unless otherwise noted)
NO. PARAMETER MIN MAX UNIT
12 tc(CLK) Cycle time, CLK SDR mode 20 ns
DDR mode 40
13 tw(CLKH) Pulse width, CLK high SDR mode 8 ns
DDR mode 18
14 tw(CLKL) Pulse width, CLK low SDR mode 8 ns
DDR mode 18
15 td(CLKH-STV) Delay time, START valid after CLK high 3 12 ns
16 td(CLKH-ENV) Delay time, ENABLE valid after CLK high 3 12 ns
17 td(CLKH-DV) Delay time, DATA valid after CLK high 3 12 ns
18 td(CLKL-DV) Delay time, DATA valid after CLK low 3 12 ns
TMS320F28379S, TMS320F28378S, TMS320F28377S, TMS320F28377S-Q1
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I TEXAS INSTRUMENTS ‘ ‘ ‘ ‘ ‘ ‘ W \ \ H—Hi‘ ‘ \ W i 1 ‘H—W’ _/ \_)' } \_/ \ i “—47 \ ‘ w ‘ i ‘ W “4% i i ‘ 1 1 ‘ W 1 i 1 mm mm .GIHDGDDGB .GD .GB.€B.€D-®.®
CLK
START
ENABLE
DATA[n:0] Data2Data1 Data3 Data4
2
WAIT
Data5 Data6
1
Data7 Data8 Data9
3
5
4
7
6
9
8
Figure 7-79. uPP Single Data Rate (SDR) Receive Timing
I1
21 3
5
4
7
6
9
Q1 I2 I3 I4 I5 I6 I7 I8 I9Q2 Q3 Q4 Q5 Q6 Q7 Q8 Q9
8
CLK
START
ENABLE
DATA[n:0]
WAIT
11
10
Figure 7-80. uPP Double Data Rate (DDR) Receive Timing
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TMS320F28379S, TMS320F28378S, TMS320F28377S, TMS320F28377S-Q1
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w TEXAS INSTRUMENTS
Data2Data1 Data3 Data4
15
13
17
16
Data5 Data6
12
Data7 Data8 Data9
14
2019
CLK
START
ENABLE
DATA[n:0]
WAIT
Figure 7-81. uPP Single Data Rate (SDR) Transmit Timing
I1
15
13
17
16
12 14
22
21
Q1 I2 I3 I4 I5 I6 I7 I8 I9Q2 Q3 Q4 Q5 Q6 Q7 Q8 Q9
18
CLK
START
ENABLE
DATA[n:0]
WAIT
Figure 7-82. uPP Double Data Rate (DDR) Transmit Timing
TMS320F28379S, TMS320F28378S, TMS320F28377S, TMS320F28377S-Q1
TMS320F28376S, TMS320F28375S, TMS320F28375S-Q1, TMS320F28374S
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8 Detailed Description
8.1 Overview
The TMS320F2837xS is a powerful 32-bit floating-point microcontroller unit (MCU) designed for advanced
closed-loop control applications such as industrial motor drives; solar inverters and digital power; electrical
vehicles and transportation; and sensing and signal processing. Complete development packages for digital
power and industrial drives are available as part of the powerSUITE and DesignDRIVE initiatives.
The real-time control subsystem is based on TI’s 32-bit C28x floating-point CPU, which provides 200 MHz of
signal processing performance. The C28x CPU is further boosted by the new TMU accelerator, which enables
fast execution of algorithms with trigonometric operations common in transforms and torque loop calculations;
and the VCU accelerator, which reduces the time for complex math operations common in encoded applications.
The F2837xS microcontroller family features a CLA real-time control coprocessor. The CLA is an independent
32-bit floating-point processor that runs at the same speed as the main CPU. The CLA responds to peripheral
triggers and executes code concurrently with the main C28x CPU. This parallel processing capability can
effectively double the computational performance of a real-time control system. By using the CLA to service
time-critical functions, the main C28x CPU is free to perform other tasks, such as communications and
diagnostics.
The TMS320F2837xS supports up to 1MB (512KW) of onboard flash memory with error correction code (ECC)
and up to 164KB (82KW) of SRAM. Two 128-bit secure zones are also available on the CPU for code protection.
Performance analog and control peripherals are also integrated on the F2837xS MCU to further enable system
consolidation. Four independent 16-bit ADCs provide precise and efficient management of multiple analog
signals, which ultimately boosts system throughput. The new sigma-delta filter module (SDFM) works in
conjunction with the sigma-delta modulator to enable isolated current shunt measurements. The Comparator
Subsystem (CMPSS) with windowed comparators allows for protection of power stages when current limit
conditions are exceeded or not met. Other analog and control peripherals include DACs, PWMs, eCAPs,
eQEPs, and other peripherals.
Peripherals such as EMIFs, CAN modules (ISO 11898-1/CAN 2.0B-compliant), and a new uPP interface extend
the connectivity of the F2837xS. The uPP interface is a new feature of the C2000 MCUs and supports high-
speed parallel connection to FPGAs or other processors with similar uPP interfaces. Lastly, a USB 2.0 port with
MAC and PHY lets users easily add universal serial bus (USB) connectivity to their application.
8.2 Functional Block Diagram
Figure 8-1 shows the CPU system and associated peripherals.
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i TEXAS INSTRUMENTS |:|‘—l: llII $?S%fl%é THT'HWH lTH H I mmmww w w m‘umm MU H ‘1 MHMHHLH m m 1
16-/12-bit ADC
x4
ADC
Result
Regs
Peripheral Frame 1
GPIO MUX, Input X-BAR, Output X-BAR
Secure Memories
shown in Red
CPU1 Buses
Comparator
Subsystem
(CMPSS)
DAC
x3
Config
Data Bus
Bridge
ePWM-1/../12 eCAP-
1/../6 eQEP-1/2/3
HRPWM-1/../8
SDFM-1/2
EXTSYNCIN
EXTSYNCOUT
TZ1-TZ6
ECAPx
EQEPxA
EQEPxB
EPWMxA
EPWMxB
EQEPxI
EQEPxS
SDx_Dy
SDx_Cy
SCI-
A/B/C/D
(16L FIFO)
I2C-A/B
(16L FIFO)
Data Bus Bridge
SCITXDx
SCIRXDx
SDAx
SCLx
CAN-
A/B
(32-MBOX)
Data Bus
Bridge
CANRXx
CANTXx
Data Bus
Bridge
USBDP
USBDM
USB
Ctrl /
PHY
GPIO
Data Bus
Bridge
GPIOn
EMIF1
Data Bus
Bridge
EM1Dx
EM1Ax
EM1CTLx
EMIF2
Data Bus
Bridge
EM2Dx
EM2Ax
EM2CTLx
A
D
B
C
JTAG
AUXCLKIN
External Crystal or
Oscillator
Watchdog
Main PLL
Aux PLL
INTOSC1
INTOSC2
Low-Power
Mode Control GPIO MUX
TRST
TCK
TDI
TMS
TDO
MEMCPU1
Global Shared
16x 4Kx16
GS0-GS15 RAMs
CPU1.CLA1 Bus
C28 CPU-1
CPU Timer 0
CPU Timer 1
CPU Timer 2
ePIE
(up to 192
interrupts)
WD Timer
NMI-WDT
CPU1.CLA1 Data ROM
(4Kx16)
CPU1.CLA1 to CPU1
128x16 MSG RAM
CPU1 to CPU1.CLA1
128x16 MSG RAM
Boot-ROM 32Kx16
Nonsecure
Secure-ROM 32Kx16
Secure
CPU1.M0 RAM 1Kx16
CPU1.M1 RAM 1Kx16
CPU1.D0 RAM 2Kx16
CPU1.D1 RAM 2Kx16
CPU1 Local Shared
6x 2Kx16
LS0-LS5 RAMs
CPU1.CLA1
CPU1.DMA
PSWD
Dual
Code
Security
Module
+
Emulation
Code
Security
Logic
(ECSL)
PUMP
Flash Bank 0
256K x 16
Secure
Flash Bank 1
256K x 16
Secure
User-Configurable
DCSM
OTP
1K x 16
Flash Wrapper for
Bank 1
Flash Wrapper for
Bank 0
FPU
VCU-II
TMU
Analog
MUX
A5:0
B5:0
C5:2
ADCIN14
ADCIN15
D5:0
Peripheral Frame 2
SPI-
A/B/C
(16L FIFO)
SPISIMOx
SPISOMIx
SPICLKx
SPISTEx
McBSP-A/B
MDXx
MDRx
MCLKXx
MCLKRx
MFSXx
MFSRx
UPPAD[7:0]
UPPACLK
UPPAEN
UPPAWT
UPPAST
uPP RAM
Figure 8-1. Functional Block Diagram
TMS320F28379S, TMS320F28378S, TMS320F28377S, TMS320F28377S-Q1
TMS320F28376S, TMS320F28375S, TMS320F28375S-Q1, TMS320F28374S
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TEXAS INSTRUMENTS
8.3 Memory
8.3.1 C28x Memory Map
The C28x memory map is described in Table 8-1. Memories accessible by the CLA or DMA (direct memory
access) are noted as well.
Table 8-1. C28x Memory Map
MEMORY SIZE START ADDRESS END ADDRESS CLA ACCESS DMA ACCESS
M0 RAM 1K × 16 0x0000 0000 0x0000 03FF
M1 RAM 1K × 16 0x0000 0400 0x0000 07FF
PieVectTable 512 × 16 0x0000 0D00 0x0000 0EFF
CLA to CPU MSGRAM 128 × 16 0x0000 1480 0x0000 14FF Yes
CPU to CLA MSGRAM 128 × 16 0x0000 1500 0x0000 157F Yes
UPP TX MSG RAM 512 × 16 0x0000 6C00 0x0000 6DFF Yes
UPP RX MSG RAM 512 × 16 0x0000 6E00 0x0000 6FFF Yes
LS0 RAM 2K × 16 0x0000 8000 0x0000 87FF Yes
LS1 RAM 2K × 16 0x0000 8800 0x0000 8FFF Yes
LS2 RAM 2K × 16 0x0000 9000 0x0000 97FF Yes
LS3 RAM 2K × 16 0x0000 9800 0x0000 9FFF Yes
LS4 RAM 2K × 16 0x0000 A000 0x0000 A7FF Yes
LS5 RAM 2K × 16 0x0000 A800 0x0000 AFFF Yes
D0 RAM 2K × 16 0x0000 B000 0x0000 B7FF
D1 RAM 2K × 16 0x0000 B800 0x0000 BFFF
GS0 RAM 4K × 16 0x0000 C000 0x0000 CFFF Yes
GS1 RAM 4K × 16 0x0000 D000 0x0000 DFFF Yes
GS2 RAM 4K × 16 0x0000 E000 0x0000 EFFF Yes
GS3 RAM 4K × 16 0x0000 F000 0x0000 FFFF Yes
GS4 RAM 4K × 16 0x0001 0000 0x0001 0FFF Yes
GS5 RAM 4K × 16 0x0001 1000 0x0001 1FFF Yes
GS6 RAM 4K × 16 0x0001 2000 0x0001 2FFF Yes
GS7 RAM 4K × 16 0x0001 3000 0x0001 3FFF Yes
GS8 RAM 4K × 16 0x0001 4000 0x0001 4FFF Yes
GS9 RAM 4K × 16 0x0001 5000 0x0001 5FFF Yes
GS10 RAM 4K × 16 0x0001 6000 0x0001 6FFF Yes
GS11 RAM 4K × 16 0x0001 7000 0x0001 7FFF Yes
GS12 RAM(1) 4K × 16 0x0001 8000 0x0001 8FFF Yes
GS13 RAM(1) 4K × 16 0x0001 9000 0x0001 9FFF Yes
GS14 RAM(1) 4K × 16 0x0001 A000 0x0001 AFFF Yes
GS15 RAM(1) 4K × 16 0x0001 B000 0x0001 BFFF Yes
CAN A Message RAM 2K × 16 0x0004 9000 0x0004 97FF
CAN B Message RAM 2K × 16 0x0004 B000 0x0004 B7FF
Flash Bank 0 256K × 16 0x0008 0000 0x000B FFFF
Flash Bank 1 256K × 16 0x000C 0000 0x000F FFFF
Secure ROM 32K × 16 0x003F 0000 0x003F 7FFF
Boot ROM 32K × 16 0x003F 8000 0x003F FFBF
Vectors 64 × 16 0x003F FFC0 0x003F FFFF
(1) Available only on F28379S, F28378S, F28377S, and F28375S.
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TMS320F28379S, TMS320F28378S, TMS320F28377S, TMS320F28377S-Q1
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TEXAS INSTRUMENTS
8.3.2 Flash Memory Map
The F28379S, F28378S, F28377S, and F28375S devices have two flash banks [512KB (256KW) each] for a
total of 1MB (512KW). Only one bank can be programmed or erased at a time. The Flash API can be executed
from RAM, or since there are two Flash banks for one CPU, the Flash API code can be executed from one bank
to erase/program the other bank. Note that an extra wait state is automatically added when code is fetched or
data is read from Bank 1 (compared to that of Bank 0), even for prefetched data. See Section 7.9.4 for details on
flash wait states. Table 1-1 shows the addresses of flash sectors on F28379S, F28378S, F28377S, and
F28375S.
Table 8-2. Addresses of Flash Sectors on F28379S, F28378S, F28377S, and F28375S
SECTOR SIZE START ADDRESS END ADDRESS
OTP Sectors
TI OTP 1K x 16 0x0007 0000 0x0007 03FF
Reserved(1) 1K x 16 0x0007 0800 0x0007 0BFF
User configurable DCSM OTP
Bank 0 1K x 16 0x0007 8000 0x0007 83FF
Reserved 1K x 16 0x0007 8800 0x0007 8BFF
Bank 0 Sectors
Sector 0 8K x 16 0x0008 0000 0x0008 1FFF
Sector 1 8K x 16 0x0008 2000 0x0008 3FFF
Sector 2 8K x 16 0x0008 4000 0x0008 5FFF
Sector 3 8K x 16 0x0008 6000 0x0008 7FFF
Sector 4 32K x 16 0x0008 8000 0x0008 FFFF
Sector 5 32K x 16 0x0009 0000 0x0009 7FFF
Sector 6 32K x 16 0x0009 8000 0x0009 FFFF
Sector 7 32K x 16 0x000A 0000 0x000A 7FFF
Sector 8 32K x 16 0x000A 8000 0x000A FFFF
Sector 9 32K x 16 0x000B 0000 0x000B 7FFF
Sector 10 8K x 16 0x000B 8000 0x000B 9FFF
Sector 11 8K x 16 0x000B A000 0x000B BFFF
Sector 12 8K x 16 0x000B C000 0x000B DFFF
Sector 13 8K x 16 0x000B E000 0x000B FFFF
Bank 1 Sectors
Sector 14 8K x 16 0x000C 0000 0x000C 1FFF
Sector 15 8K x 16 0x000C 2000 0x000C 3FFF
Sector 16 8K x 16 0x000C 4000 0x000C 5FFF
Sector 17 8K x 16 0x000C 6000 0x000C 7FFF
Sector 18 32K x 16 0x000C 8000 0x000C FFFF
Sector 19 32K x 16 0x000D 0000 0x000D 7FFF
Sector 20 32K x 16 0x000D 8000 0x000D FFFF
Sector 21 32K x 16 0x000E 0000 0x000E 7FFF
Sector 22 32K x 16 0x000E 8000 0x000E FFFF
Sector 23 32K x 16 0x000F 0000 0x000F 7FFF
Sector 24 8K x 16 0x000F 8000 0x000F 9FFF
Sector 25 8K x 16 0x000F A000 0x000F BFFF
Sector 26 8K x 16 0x000F C000 0x000F DFFF
Sector 27 8K x 16 0x000F E000 0x000F FFFF
Flash ECC Locations
TI OTP ECC 128 x 16 0x0107 0000 0x0107 007F
TMS320F28379S, TMS320F28378S, TMS320F28377S, TMS320F28377S-Q1
TMS320F28376S, TMS320F28375S, TMS320F28375S-Q1, TMS320F28374S
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I TEXAS INSTRUMENTS
Table 8-2. Addresses of Flash Sectors on F28379S, F28378S, F28377S, and F28375S (continued)
SECTOR SIZE START ADDRESS END ADDRESS
Reserved 128 x 16 0x0107 0200 0x0107 027F
User-configurable DCSM OTP
ECC Bank 0 128 x 16 0x0107 1000 0x0107 107F
Reserved 128 x 16 0x0107 1200 0x0107 127F
Flash ECC (Sector 0) 1K x 16 0x0108 0000 0x0108 03FF
Flash ECC (Sector 1) 1K x 16 0x0108 0400 0x0108 07FF
Flash ECC (Sector 2) 1K x 16 0x0108 0800 0x0108 0BFF
Flash ECC (Sector 3) 1K x 16 0x0108 0C00 0x0108 0FFF
Flash ECC (Sector 4) 4K x 16 0x0108 1000 0x0108 1FFF
Flash ECC (Sector 5) 4K x 16 0x0108 2000 0x0108 2FFF
Flash ECC (Sector 6) 4K x 16 0x0108 3000 0x0108 3FFF
Flash ECC (Sector 7) 4K x 16 0x0108 4000 0x0108 4FFF
Flash ECC (Sector 8) 4K x 16 0x0108 5000 0x0108 5FFF
Flash ECC (Sector 9) 4K x 16 0x0108 6000 0x0108 6FFF
Flash ECC (Sector 10) 1K x 16 0x0108 7000 0x0108 73FF
Flash ECC (Sector 11) 1K x 16 0x0108 7400 0x0108 77FF
Flash ECC (Sector 12) 1K x 16 0x0108 7800 0x0108 7BFF
Flash ECC (Sector 13) 1K x 16 0x0108 7C00 0x0108 7FFF
Flash ECC (Sector 14) 1K x 16 0x0108 8000 0x0108 83FF
Flash ECC (Sector 15) 1K x 16 0x0108 8400 0x0108 87FF
Flash ECC (Sector 16) 1K x 16 0x0108 8800 0x0108 8BFF
Flash ECC (Sector 17) 1K x 16 0x0108 8C00 0x0108 8FFF
Flash ECC (Sector 18) 4K x 16 0x0108 9000 0x0108 9FFF
Flash ECC (Sector 19) 4K x 16 0x0108 A000 0x0108 AFFF
Flash ECC (Sector 20) 4K x 16 0x0108 B000 0x0108 BFFF
Flash ECC (Sector 21) 4K x 16 0x0108 C000 0x0108 CFFF
Flash ECC (Sector 22) 4K x 16 0x0108 D000 0x0108 DFFF
Flash ECC (Sector 23) 4K x 16 0x0108 E000 0x0108 EFFF
Flash ECC (Sector 24) 1K x 16 0x0108 F000 0x0108 F3FF
Flash ECC (Sector 25) 1K x 16 0x0108 F400 0x0108 F7FF
Flash ECC (Sector 26) 1K x 16 0x0108 F800 0x0108 FBFF
Flash ECC (Sector 27) 1K x 16 0x0108 FC00 0x0108 FFFF
(1) Any kind of access to this region may result in a spurious ECC error event.
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TMS320F28379S, TMS320F28378S, TMS320F28377S, TMS320F28377S-Q1
TMS320F28376S, TMS320F28375S, TMS320F28375S-Q1, TMS320F28374S
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TEXAS INSTRUMENTS
The F28376S and F28374S devices have one flash bank of 512KB (256KW) and the code to program the flash
should be executed out of RAM. See Section 7.9.4 for details on flash wait states. Table 1-1 shows the
addresses of flash sectors on F28376S and F28374S.
Table 8-3. Addresses of Flash Sectors on F28376S and F28374S
SECTOR SIZE START ADDRESS END ADDRESS
OTP Sectors
TI OTP Bank 0 1K x 16 0x0007 0000 0x0007 03FF
User configurable DCSM OTP
Bank 0 1K x 16 0x0007 8000 0x0007 83FF
Sectors
Sector 0 8K x 16 0x0008 0000 0x0008 1FFF
Sector 1 8K x 16 0x0008 2000 0x0008 3FFF
Sector 2 8K x 16 0x0008 4000 0x0008 5FFF
Sector 3 8K x 16 0x0008 6000 0x0008 7FFF
Sector 4 32K x 16 0x0008 8000 0x0008 FFFF
Sector 5 32K x 16 0x0009 0000 0x0009 7FFF
Sector 6 32K x 16 0x0009 8000 0x0009 FFFF
Sector 7 32K x 16 0x000A 0000 0x000A 7FFF
Sector 8 32K x 16 0x000A 8000 0x000A FFFF
Sector 9 32K x 16 0x000B 0000 0x000B 7FFF
Sector 10 8K x 16 0x000B 8000 0x000B 9FFF
Sector 11 8K x 16 0x000B A000 0x000B BFFF
Sector 12 8K x 16 0x000B C000 0x000B DFFF
Sector 13 8K x 16 0x000B E000 0x000B FFFF
Flash ECC Locations
TI OTP ECC Bank 0 128 x 16 0x0107 0000 0x0107 007F
User-configurable DCSM OTP
ECC Bank 0 128 x 16 0x0107 1000 0x0107 107F
Flash ECC (Sector 0) 1K x 16 0x0108 0000 0x0108 03FF
Flash ECC (Sector 1) 1K x 16 0x0108 0400 0x0108 07FF
Flash ECC (Sector 2) 1K x 16 0x0108 0800 0x0108 0BFF
Flash ECC (Sector 3) 1K x 16 0x0108 0C00 0x0108 0FFF
Flash ECC (Sector 4) 4K x 16 0x0108 1000 0x0108 1FFF
Flash ECC (Sector 5) 4K x 16 0x0108 2000 0x0108 2FFF
Flash ECC (Sector 6) 4K x 16 0x0108 3000 0x0108 3FFF
Flash ECC (Sector 7) 4K x 16 0x0108 4000 0x0108 4FFF
Flash ECC (Sector 8) 4K x 16 0x0108 5000 0x0108 5FFF
Flash ECC (Sector 9) 4K x 16 0x0108 6000 0x0108 6FFF
Flash ECC (Sector 10) 1K x 16 0x0108 7000 0x0108 73FF
Flash ECC (Sector 11) 1K x 16 0x0108 7400 0x0108 77FF
Flash ECC (Sector 12) 1K x 16 0x0108 7800 0x0108 7BFF
Flash ECC (Sector 13) 1K x 16 0x0108 7C00 0x0108 7FFF
TMS320F28379S, TMS320F28378S, TMS320F28377S, TMS320F28377S-Q1
TMS320F28376S, TMS320F28375S, TMS320F28375S-Q1, TMS320F28374S
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TEXAS INSTRUMENTS
8.3.3 EMIF Chip Select Memory Map
The EMIF memory map is shown in Table 8-4.
Table 8-4. EMIF Chip Select Memory Map
EMIF CHIP SELECT SIZE(1) START ADDRESS END ADDRESS CLA ACCESS DMA ACCESS
EMIF1_CS0n - Data 256M × 16 0x8000 0000 0x8FFF FFFF Yes
EMIF1_CS2n - Program + Data(2) 2M × 16 0x0010 0000 0x002F FFFF Yes
EMIF1_CS3n - Program + Data 512K × 16 0x0030 0000 0x0037 FFFF Yes
EMIF1_CS4n - Program + Data 393K × 16 0x0038 0000 0x003D FFFF Yes
EMIF2_CS0n - Data 3M × 16 0x9000 0000 0x91FF FFFF
EMIF2_CS2n - Program + Data 4K × 16 0x0000 2000 0x0000 2FFF Yes (Data only)
(1) Available memory size listed in this table is the maximum possible size assuming 32-bit memory. This may not apply to other memory
sizes because of pin mux setting. See Section 6.4.1 to find the available address lines for your use case.
(2) The 2M × 16 size is for a 32-bit interface with the assumption that 16-bit accesses are not performed; hence, byte enables are not
used (tied to active value on board). If byte enables are used, then the maximum size is smaller because byte enables are muxed with
address pins (see Section 6.4.1) . If 16-bit memory is used, then the maximum size is 1M × 16.
8.3.4 Peripheral Registers Memory Map
The peripheral registers memory map can be found in Table 8-5. Registers in the peripheral frames share a
secondary master (CLA or DMA) selection with all other registers within the same peripheral frame. See the
TMS320F2837xS Microcontrollers Technical Reference Manual for details on the CPU subsystem and
secondary master selection.
Table 8-5. Peripheral Registers Memory Map
REGISTERS STRUCTURE NAME START
ADDRESS
END
ADDRESS PROTECTED(1) CLA
ACCESS
DMA
ACCESS
AdcaResultRegs ADC_RESULT_REGS 0x0000 0B00 0x0000 0B1F Yes Yes
AdcbResultRegs ADC_RESULT_REGS 0x0000 0B20 0x0000 0B3F Yes Yes
AdccResultRegs ADC_RESULT_REGS 0x0000 0B40 0x0000 0B5F Yes Yes
AdcdResultRegs ADC_RESULT_REGS 0x0000 0B60 0x0000 0B7F Yes Yes
CpuTimer0Regs CPUTIMER_REGS 0x0000 0C00 0x0000 0C07
CpuTimer1Regs CPUTIMER_REGS 0x0000 0C08 0x0000 0C0F
CpuTimer2Regs CPUTIMER_REGS 0x0000 0C10 0x0000 0C17
PieCtrlRegs (2) PIE_CTRL_REGS 0x0000 0CE0 0x0000 0CFF
Cla1SoftIntRegs(2) CLA_SOFTINT_REGS 0x0000 0CE0 0x0000 0CFF
Yes – CLA
only, no
CPU
access
DmaRegs DMA_REGS 0x0000 1000 0x0000 11FF
Cla1Regs CLA_REGS 0x0000 1400 0x0000 147F
Peripheral Frame 1
EPwm1Regs EPWM_REGS 0x0000 4000 0x0000 40FF Yes Yes Yes
EPwm2Regs EPWM_REGS 0x0000 4100 0x0000 41FF Yes Yes Yes
EPwm3Regs EPWM_REGS 0x0000 4200 0x0000 42FF Yes Yes Yes
EPwm4Regs EPWM_REGS 0x0000 4300 0x0000 43FF Yes Yes Yes
EPwm5Regs EPWM_REGS 0x0000 4400 0x0000 44FF Yes Yes Yes
EPwm6Regs EPWM_REGS 0x0000 4500 0x0000 45FF Yes Yes Yes
EPwm7Regs EPWM_REGS 0x0000 4600 0x0000 46FF Yes Yes Yes
EPwm8Regs EPWM_REGS 0x0000 4700 0x0000 47FF Yes Yes Yes
EPwm9Regs EPWM_REGS 0x0000 4800 0x0000 48FF Yes Yes Yes
EPwm10Regs EPWM_REGS 0x0000 4900 0x0000 49FF Yes Yes Yes
EPwm11Regs EPWM_REGS 0x0000 4A00 0x0000 4AFF Yes Yes Yes
EPwm12Regs EPWM_REGS 0x0000 4B00 0x0000 4BFF Yes Yes Yes
ECap1Regs ECAP_REGS 0x0000 5000 0x0000 501F Yes Yes Yes
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TMS320F28379S, TMS320F28378S, TMS320F28377S, TMS320F28377S-Q1
TMS320F28376S, TMS320F28375S, TMS320F28375S-Q1, TMS320F28374S
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TMS320F28376S TMS320F28375S TMS320F28375S-Q1 TMS320F28374S
TEXAS INSTRUMENTS
Table 8-5. Peripheral Registers Memory Map (continued)
REGISTERS STRUCTURE NAME START
ADDRESS
END
ADDRESS PROTECTED(1) CLA
ACCESS
DMA
ACCESS
ECap2Regs ECAP_REGS 0x0000 5020 0x0000 503F Yes Yes Yes
ECap3Regs ECAP_REGS 0x0000 5040 0x0000 505F Yes Yes Yes
ECap4Regs ECAP_REGS 0x0000 5060 0x0000 507F Yes Yes Yes
ECap5Regs ECAP_REGS 0x0000 5080 0x0000 509F Yes Yes Yes
ECap6Regs ECAP_REGS 0x0000 50A0 0x0000 50BF Yes Yes Yes
EQep1Regs EQEP_REGS 0x0000 5100 0x0000 513F Yes Yes Yes
EQep2Regs EQEP_REGS 0x0000 5140 0x0000 517F Yes Yes Yes
EQep3Regs EQEP_REGS 0x0000 5180 0x0000 51BF Yes Yes Yes
DacaRegs DAC_REGS 0x0000 5C00 0x0000 5C0F Yes Yes Yes
DacbRegs DAC_REGS 0x0000 5C10 0x0000 5C1F Yes Yes Yes
DaccRegs DAC_REGS 0x0000 5C20 0x0000 5C2F Yes Yes Yes
Cmpss1Regs CMPSS_REGS 0x0000 5C80 0x0000 5C9F Yes Yes Yes
Cmpss2Regs CMPSS_REGS 0x0000 5CA0 0x0000 5CBF Yes Yes Yes
Cmpss3Regs CMPSS_REGS 0x0000 5CC0 0x0000 5CDF Yes Yes Yes
Cmpss4Regs CMPSS_REGS 0x0000 5CE0 0x0000 5CFF Yes Yes Yes
Cmpss5Regs CMPSS_REGS 0x0000 5D00 0x0000 5D1F Yes Yes Yes
Cmpss6Regs CMPSS_REGS 0x0000 5D20 0x0000 5D3F Yes Yes Yes
Cmpss7Regs CMPSS_REGS 0x0000 5D40 0x0000 5D5F Yes Yes Yes
Cmpss8Regs CMPSS_REGS 0x0000 5D60 0x0000 5D7F Yes Yes Yes
Sdfm1Regs SDFM_REGS 0x0000 5E00 0x0000 5E7F Yes Yes Yes
Sdfm2Regs SDFM_REGS 0x0000 5E80 0x0000 5EFF Yes Yes Yes
Peripheral Frame 2
McbspaRegs MCBSP_REGS 0x0000 6000 0x0000 603F Yes Yes Yes
McbspbRegs MCBSP_REGS 0x0000 6040 0x0000 607F Yes Yes Yes
SpiaRegs SPI_REGS 0x0000 6100 0x0000 610F Yes Yes Yes
SpibRegs SPI_REGS 0x0000 6110 0x0000 611F Yes Yes Yes
SpicRegs SPI_REGS 0x0000 6120 0x0000 612F Yes Yes Yes
UppRegs UPP_REGS 0x0000 6200 0x0000 62FF Yes Yes Yes
WdRegs WD_REGS 0x0000 7000 0x0000 703F Yes
NmiIntruptRegs NMI_INTRUPT_REGS 0x0000 7060 0x0000 706F Yes
XintRegs XINT_REGS 0x0000 7070 0x0000 707F Yes
SciaRegs SCI_REGS 0x0000 7200 0x0000 720F Yes
ScibRegs SCI_REGS 0x0000 7210 0x0000 721F Yes
ScicRegs SCI_REGS 0x0000 7220 0x0000 722F Yes
ScidRegs SCI_REGS 0x0000 7230 0x0000 723F Yes
I2caRegs I2C_REGS 0x0000 7300 0x0000 733F Yes
I2cbRegs I2C_REGS 0x0000 7340 0x0000 737F Yes
AdcaRegs ADC_REGS 0x0000 7400 0x0000 747F Yes Yes
AdcbRegs ADC_REGS 0x0000 7480 0x0000 74FF Yes Yes
AdccRegs ADC_REGS 0x0000 7500 0x0000 757F Yes Yes
AdcdRegs ADC_REGS 0x0000 7580 0x0000 75FF Yes Yes
InputXbarRegs INPUT_XBAR_REGS 0x0000 7900 0x0000 791F Yes
XbarRegs XBAR_REGS 0x0000 7920 0x0000 793F Yes
TrigRegs TRIG_REGS 0x0000 7940 0x0000 794F Yes
DmaClaSrcSelRegs DMA_CLA_SRC_SEL_REGS 0x0000 7980 0x0000 798F Yes
EPwmXbarRegs EPWM_XBAR_REGS 0x0000 7A00 0x0000 7A3F Yes
OutputXbarRegs OUTPUT_XBAR_REGS 0x0000 7A80 0x0000 7ABF Yes
GpioCtrlRegs GPIO_CTRL_REGS 0x0000 7C00 0x0000 7D7F Yes
TMS320F28379S, TMS320F28378S, TMS320F28377S, TMS320F28377S-Q1
TMS320F28376S, TMS320F28375S, TMS320F28375S-Q1, TMS320F28374S
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TEXAS INSTRUMENTS
Table 8-5. Peripheral Registers Memory Map (continued)
REGISTERS STRUCTURE NAME START
ADDRESS
END
ADDRESS PROTECTED(1) CLA
ACCESS
DMA
ACCESS
GpioDataRegs GPIO_DATA_REGS 0x0000 7F00 0x0000 7F2F Yes Yes
UsbaRegs USB_REGS 0x0004 0000 0x0004 0FFF Yes
Emif1Regs EMIF_REGS 0x0004 7000 0x0004 77FF Yes
Emif2Regs EMIF_REGS 0x0004 7800 0x0004 7FFF Yes
CanaRegs CAN_REGS 0x0004 8000 0x0004 87FF Yes
CanbRegs CAN_REGS 0x0004 A000 0x0004 A7FF Yes
FlashPumpSemaphoreRegs FLASH_PUMP_SEMAPHORE_REGS 0x0005 0024 0x0005 0025 Yes
DevCfgRegs DEV_CFG_REGS 0x0005 D000 0x0005 D17F Yes
AnalogSubsysRegs ANALOG_SUBSYS_REGS 0x0005 D180 0x0005 D1FF Yes
ClkCfgRegs CLK_CFG_REGS 0x0005 D200 0x0005 D2FF Yes
CpuSysRegs CPU_SYS_REGS 0x0005 D300 0x0005 D3FF Yes
RomPrefetchRegs ROM_PREFETCH_REGS 0x0005 E608 0x0005 E60B Yes
DcsmZ1Regs DCSM_Z1_REGS 0x0005 F000 0x0005 F02F Yes
DcsmZ2Regs DCSM_Z2_REGS 0x0005 F040 0x0005 F05F Yes
DcsmCommonRegs DCSM_COMMON_REGS 0x0005 F070 0x0005 F07F Yes
MemCfgRegs MEM_CFG_REGS 0x0005 F400 0x0005 F47F Yes
Emif1ConfigRegs EMIF1_CONFIG_REGS 0x0005 F480 0x0005 F49F Yes
Emif2ConfigRegs EMIF2_CONFIG_REGS 0x0005 F4A0 0x0005 F4BF Yes
AccessProtectionRegs ACCESS_PROTECTION_REGS 0x0005 F4C0 0x0005 F4FF Yes
MemoryErrorRegs MEMORY_ERROR_REGS 0x0005 F500 0x0005 F53F Yes
RomWaitStateRegs ROM_WAIT_STATE_REGS 0x0005 F540 0x0005 F541 Yes
Flash0CtrlRegs FLASH_CTRL_REGS 0x0005 F800 0x0005 FAFF Yes
Flash0EccRegs FLASH_ECC_REGS 0x0005 FB00 0x0005 FB3F Yes
Flash1CtrlRegs FLASH_CTRL_REGS 0x0005 FC00 0x0005 FEFF Yes
Flash1EccRegs FLASH_ECC_REGS 0x0005 FF00 0x0005 FF3F Yes
(1) The CPU (not applicable for CLA or DMA) contains a write followed by read protection mode to ensure that any read operation that
follows a write operation within a protected address range is executed as written by delaying the read operation until the write is
initiated.
(2) The address overlap of PieCtrlRegs and Cla1SoftIntRegs is correct. Each CPU, C28x and CLA, only has access to one of the register
sets.
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TMS320F28379S, TMS320F28378S, TMS320F28377S, TMS320F28377S-Q1
TMS320F28376S, TMS320F28375S, TMS320F28375S-Q1, TMS320F28374S
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I TEXAS INSTRUMENTS
8.3.5 Memory Types
Table 8-6 provides more information about each memory type.
Table 8-6. Memory Types
MEMORY TYPE ECC-CAPABLE PARITY SECURITY HIBERNATE
RETENTION
ACCESS
PROTECTION
M0, M1 Yes – – Yes –
D0, D1 Yes – Yes – Yes
LSx – Yes Yes – Yes
GSx – Yes – – Yes
CPU/CLA MSGRAM – Yes Yes – Yes
Boot ROM – – – N/A –
Secure ROM – – Yes N/A –
Flash Yes – Yes N/A N/A
User-configurable DCSM OTP Yes – Yes N/A N/A
8.3.5.1 Dedicated RAM (Mx and Dx RAM)
The CPU subsystem has four dedicated ECC-capable RAM blocks: M0, M1, D0, and D1. M0/M1 memories are
small nonsecure blocks that are tightly coupled with the CPU (that is, only the CPU has access to them). D0/D1
memories are secure blocks and also have the access-protection feature (CPU write/CPU fetch protection).
8.3.5.2 Local Shared RAM (LSx RAM)
RAM blocks which are dedicated to each subsystem and are accessible to its CPU and CLA only, are called
local shared RAMs (LSx RAMs).
All LSx RAM blocks have parity. These memories are secure and have the access protection (CPU write/CPU
fetch) feature.
By default, these memories are dedicated to the CPU only, and the user could choose to share these memories
with the CLA by configuring the MSEL_LSx bit field in the LSxMSEL registers appropriately.
Table 8-7 shows the master access for the LSx RAM.
Table 8-7. Master Access for LSx RAM
(With Assumption That all Other Access Protections are Disabled)
MSEL_LSx CLAPGM_LSx CPU ALLOWED ACCESS CLA ALLOWED ACCESS COMMENT
00 X All – LSx memory is configured
as CPU dedicated RAM.
01 0 All Data Read
Data Write
LSx memory is shared
between CPU and CLA1.
01 1 Emulation Read
Emulation Write Fetch Only LSx memory is CLA1
program memory.
TMS320F28379S, TMS320F28378S, TMS320F28377S, TMS320F28377S-Q1
TMS320F28376S, TMS320F28375S, TMS320F28375S-Q1, TMS320F28374S
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I TEXAS INSTRUMENTS
8.3.5.3 Global Shared RAM (GSx RAM)
RAM blocks which are accessible from both the CPU and DMA are called global shared RAMs (GSx RAMs).
Both the CPU and DMA have full read and write access to these memories.
All GSx RAM blocks have parity.
The GSx RAMs have access protection (CPU write/CPU fetch/DMA write).
8.3.5.4 CLA Message RAM (CLA MSGRAM)
These RAM blocks can be used to share data between the CPU and CLA. The CLA has read and write access
to the "CLA to CPU MSGRAM." The CPU has read and write access to the "CPU to CLA MSGRAM." The CPU
and CLA both have read access to both MSGRAMs.
This RAM has parity.
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TMS320F28379S, TMS320F28378S, TMS320F28377S, TMS320F28377S-Q1
TMS320F28376S, TMS320F28375S, TMS320F28375S-Q1, TMS320F28374S
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I TEXAS INSTRUMENTS
8.4 Identification
Table 8-8 shows the Device Identification Registers.
Table 8-8. Device Identification Registers
NAME ADDRESS SIZE (x16) DESCRIPTION
PARTIDH 0x0005 D00A 2
Device part identification number(1)
TMS320F28379S 0x**F9 0400
TMS320F28378S 0x**FA 0400
TMS320F28377S 0x**FF 0400
TMS320F28376S 0x**FE 0400
TMS320F28375S 0x**FD 0400
TMS320F28374S 0x**FC 0400
REVID 0x0005 D00C 2
Silicon revision number
Revision B 0x0000 0002
Revision C 0x0000 0003
UID_UNIQUE 0x0007 03CC 2
Unique identification number. This number is different on each
individual device with the same PARTIDH. This can be used as
a serial number in the application. This number is present only
on TMS Revision C devices.
JTAG ID N/A N/A JTAG Device ID 0x0B99 C02F
(1) PARTIDH may have one of two values for each part number, with the eight most significant bits identified with '**' above being 0x00 or
0x02.
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8.5 Bus Architecture – Peripheral Connectivity
Table 8-9 shows a broad view of the peripheral and configuration register accessibility from each bus master.
Peripherals within peripheral frames 1 or 2 will all be mapped to the respective secondary master as a group (if
SPI is assigned to CPU1.DMA, then McBSP is also assigned to CPU1.DMA).
Table 8-9. Bus Master Peripheral Access
PERIPHERALS
(BY BUS ACCESS TYPE) CPU1.DMA CPU1.CLA1 CPU1
Peripheral Frame 1:
• ePWM/HRPWM
• SDFM
• eCAP(1)
• eQEP(1)
• CMPSS(1)
• DAC(1)
YYY
Peripheral Frame 2:
• SPI
• McBSP
• uPP(1)
YYY
SCI Y
I2C Y
CAN Y
ADC Configuration Y Y
EMIF1 Y Y
EMIF2 Y Y
USB Y
Device Capability, Peripheral Reset, Peripheral CPU Select Y
GPIO Pin Mapping and Configuration Y
Analog System Control Y
uPP Message RAMs Y Y
Reset Configuration Y
Clock and PLL Configuration Y
System Configuration
(WD, NMIWD, LPM, Peripheral Clock Gating) Y
Flash Configuration Y
CPU Timers Y
DMA and CLA Trigger Source Select Y
GPIO Data(2) Y Y
ADC Results Y Y Y
(1) These modules are on a Peripheral Frame with DMA access; however, they cannot trigger a DMA transfer.
(2) The GPIO Data Registers are unique for each CPU1 and CPU1.CLAx. When the GPIO Pin Mapping Register is configured to assign a
GPIO to a particular master, the respective GPIO Data Register will control the GPIO. See the General-Purpose Input/Output (GPIO)
chapter of the TMS320F2837xS Microcontrollers Technical Reference Manual for more details.
8.6 C28x Processor
The CPU is a 32-bit fixed-point processor. This device draws from the best features of digital signal processing;
reduced instruction set computing (RISC); and microcontroller architectures, firmware, and tool sets.
The CPU features include a modified Harvard architecture and circular addressing. The RISC features are
single-cycle instruction execution, register-to-register operations, and modified Harvard architecture. The
microcontroller features include ease of use through an intuitive instruction set, byte packing and unpacking, and
bit manipulation. The modified Harvard architecture of the CPU enables instruction and data fetches to be
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performed in parallel. The CPU can read instructions and data while it writes data simultaneously to maintain the
single-cycle instruction operation across the pipeline. The CPU does this over six separate address/data buses.
For more information on CPU architecture and instruction set, see the TMS320C28x CPU and Instruction Set
Reference Guide.
8.6.1 Floating-Point Unit
The C28x plus floating-point (C28x+FPU) processor extends the capabilities of the C28x fixed-point CPU by
adding registers and instructions to support IEEE single-precision floating-point operations.
Devices with the C28x+FPU include the standard C28x register set plus an additional set of floating-point unit
registers. The additional floating-point unit registers are the following:
• Eight floating-point result registers, RnH (where n = 0–7)
• Floating-point Status Register (STF)
• Repeat Block Register (RB)
All of the floating-point registers, except the repeat block register, are shadowed. This shadowing can be used in
high-priority interrupts for fast context save and restore of the floating-point registers.
For more information, see the TMS320C28x Extended Instruction Sets Technical Reference Manual.
8.6.2 Trigonometric Math Unit
The TMU extends the capabilities of a C28x+FPU by adding instructions and leveraging existing FPU
instructions to speed up the execution of common trigonometric and arithmetic operations listed in Table 8-10.
Table 8-10. TMU Supported Instructions
INSTRUCTIONS C EQUIVALENT OPERATION PIPELINE CYCLES
MPY2PIF32 RaH,RbH a = b * 2pi 2/3
DIV2PIF32 RaH,RbH a = b / 2pi 2/3
DIVF32 RaH,RbH,RcH a = b/c 5
SQRTF32 RaH,RbH a = sqrt(b) 5
SINPUF32 RaH,RbH a = sin(b*2pi) 4
COSPUF32 RaH,RbH a = cos(b*2pi) 4
ATANPUF32 RaH,RbH a = atan(b)/2pi 4
QUADF32 RaH,RbH,RcH,RdH Operation to assist in calculating ATANPU2 5
No changes have been made to existing instructions, pipeline or memory bus architecture. All TMU instructions
use the existing FPU register set (R0H to R7H) to carry out their operations. A detailed explanation of the
workings of the FPU can be found in the TMS320C28x Extended Instruction Sets Technical Reference Manual.
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8.6.3 Viterbi, Complex Math, and CRC Unit II
The VCU-II is the second-generation Viterbi, Complex Math, and CRC extension to the C28x CPU. The VCU-II
extends the capabilities of the C28x CPU by adding registers and instructions to accelerate the performance of
Fast Fourier Transforms (FFTs) and communications-based algorithms. The C28x+VCU-II supports the following
algorithm types:
•Viterbi Decoding
Viterbi decoding is commonly used in baseband communications applications. The Viterbi decode algorithm
consists of three main parts: branch metric calculations, compare-select (Viterbi butterfly), and a traceback
operation. Table 8-11 shows a summary of the VCU performance for each of these operations.
Table 8-11. Viterbi Decode Performance
VITERBI OPERATION VCU CYCLES
Branch Metric Calculation (code rate = 1/2) 1
Branch Metric Calculation (code rate = 1/3) 2p
Viterbi Butterfly (add-compare-select) 2(1)
Traceback per Stage 3(2)
(1) C28x CPU takes 15 cycles per butterfly.
(2) C28x CPU takes 22 cycles per stage.
•Cyclic Redundancy Check
Cyclic redundancy check (CRC) algorithms provide a straightforward method for verifying data integrity over
large data blocks, communication packets, or code sections. The C28x+VCU can perform 8-bit, 16-bit, 24-bit,
and 32-bit CRCs. For example, the VCU can compute the CRC for a block length of 10 bytes in 10 cycles. A
CRC result register contains the current CRC, which is updated whenever a CRC instruction is executed.
•Complex Math
Complex math is used in many applications, a few of which are:
– Fast Fourier Transform
The complex FFT is used in spread spectrum communications, as well as in many signal processing
algorithms.
– Complex filters
Complex filters improve data reliability, transmission distance, and power efficiency. The C28x+VCU can
perform a complex I and Q multiply with coefficients (four multiplies) in a single cycle. In addition, the C28x
+VCU can read/write the real and imaginary parts of 16-bit complex data to memory in a single cycle.
Table 8-12 shows a summary of the VCU operations enabled by the VCU.
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Table 8-12. Complex Math Performance
COMPLEX MATH OPERATION VCU CYCLES NOTES
Add or Subtract 1 32 +/- 32 = 32-bit (Useful for filters)
Add or Subtract 1 16 +/- 32 = 15-bit (Useful for FFT)
Multiply 2p 16 x 16 = 32-bit
Multiply and Accumulate (MAC) 2p 32 + 32 = 32-bit, 16 x 16 = 32-bit
RPT MAC 2p+N Repeat MAC. Single cycle after the first operation.
For more information, see the TMS320C28x Extended Instruction Sets Technical Reference Manual.
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l TEXAS INSTRUMENTS 1 1-} SYSCLK 45 ll H 7 ClockEn » 7 4»
8.7 Control Law Accelerator
The CLA is an independent single-precision (32-bit) FPU processor with its own bus structure, fetch mechanism,
and pipeline. Eight individual CLA tasks can be specified. Each task is started by software or a peripheral such
as the ADC, ePWM, eCAP, eQEP, or CPU Timer 0. The CLA executes one task at a time to completion. When a
task completes, the main CPU is notified by an interrupt to the PIE and the CLA automatically begins the next
highest-priority pending task. The CLA can directly access the ADC Result registers, ePWM, eCAP, eQEP,
Comparator and DAC registers. Dedicated message RAMs provide a method to pass additional data between
the main CPU and the CLA.
Figure 8-2 shows the CLA block diagram.
CPU Read Data Bus
MR0(32)
MVECT1(16)
MIFR(16)
MPC(16)
MIER(16)
MIFRC(16)
MIRUN(16)
MR1(32)
MR3(32)
MAR0(16)
CPU Read/Write Data Bus
CLA Execution
Register Set
CLA Control
Register Set
MSTF(32)
PIE
CLA Program
Memory (LSx)
CLA Data
Memory (LSx)
SYSCLK
CLA Clock Enable
SYSRSn
MR2(32)
MAR1(16)
MIOVF(16)
MICLR(16)
MCTL(16)
MICLROVF(16)
LUF
CLA Message
RAMs
Shared
Peripherals
MEALLOW
CLA Data Bus
C28x
CPU
INT11
INT12
MVECT2(16)
MVECT3(16)
MVECT4(16)
MVECT5(16)
MVECT6(16)
MVECT7(16)
MVECT8(16)
CPU Data Bus
LSxMSEL[MSEL_LSx]
LSxCLAPGM[CLAPGM_LSx]
CLA Program Bus
MPERINT1
to
MPERINT8
CLA_INT1
to
CLA_INT8
LVF
From
Shared
Peripherals
Figure 8-2. CLA Block Diagram
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8.8 Direct Memory Access
The CPU has its own 6-channel DMA module. The DMA module provides a hardware method of transferring
data between peripherals and/or memory without intervention from the CPU, thereby freeing up bandwidth for
other system functions. Additionally, the DMA has the capability to orthogonally rearrange the data as it is
transferred as well as “ping-pong” data between buffers. These features are useful for structuring data into
blocks for optimal CPU processing.
The DMA module is an event-based machine, meaning it requires a peripheral or software trigger to start a DMA
transfer. Although it can be made into a periodic time-driven machine by configuring a timer as the interrupt
trigger source, there is no mechanism within the module itself to start memory transfers periodically. The
interrupt trigger source for each of the six DMA channels can be configured separately and each channel
contains its own independent PIE interrupt to let the CPU know when a DMA transfer has either started or
completed. Five of the six channels are exactly the same, while Channel 1 has the ability to be configured at a
higher priority than the others.
DMA features include:
• Six channels with independent PIE interrupts
• Peripheral interrupt trigger sources
– ADC interrupts and EVT signals
– Multichannel buffered serial port transmit and receive
– External interrupts
– CPU timers
– EPWMxSOC signals
– SPIx transmit and receive
– SDFM
– Software trigger
• Data sources and destinations:
– GSx RAM
– ADC result registers
– ePWMx
– SPI
– McBSP
– EMIF
• Word Size: 16-bit or 32-bit (SPI and McBSP limited to 16-bit)
• Throughput: four cycles/word (without arbitration)
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Figure 8-3 shows a device-level block diagram of the DMA.
DMA_CHx (1-6)
Global Shared
16x 4Kx16
GS0-15 RAMs
SDFM
(8)
EPWM
(12)
McBSP
(2)
SPI
(3) EMIF1
PIE
C28x Bus
DMA Bus
DMA C28x
XINT (1-5)
TINT (0-2)
SOCA (1-12), SOCB (1-12)
MXEVT (A-B), MREVT (A-B)
SPITX (A-C), SPIRX (A-C)
ADC INT (A-D) (1-4), EVT (A-D)
SDxFLTy (x = 1 to 2, y = 1 to 4)
ADC
RESULTS
(4)
ADC
WRAPPER
(4)
XINT
(5)
TIMER
(3)
DMA Trigger
Source Selection
DMACHSRCSEL1.CHx
DMACHSRCSEL2.CHx
CHx.MODE.PERINTSEL
(x = 1 to 6)
DMA Trigger Source
CPU and DMA Data Path
eQEP
eCAP
CMPSS
DAC
Figure 8-3. DMA Block Diagram
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8.9 Boot ROM and Peripheral Booting
The device boot ROM contains bootloading software. The device boot ROM is executed each time the device
comes out of reset. Users can configure the device to boot to flash (using GET mode) or choose to boot the
device through one of the bootable peripherals by configuring the boot mode GPIO pins.
Table 8-13 shows the possible boot modes supported on the device. The default boot mode pins are GPIO72
(boot mode pin 1) and GPIO 84 (boot mode pin 0). Users may choose to have weak pullups for boot mode pins if
they use a peripheral on these pins as well, so the pullups can be overdriven. On this device, customers can
change the factory default boot mode pins by programming user-configurable Dual Code Security Module
(DCSM) OTP locations. This is recommended only for cases in which the factory default boot mode pins do not
fit into the customer design. More details on the locations to be programmed is available in the TMS320F2837xS
Microcontrollers Technical Reference Manual .
Table 8-13. Device Boot Mode
MODE NO. CPU1 BOOT MODE TRST
GPIO72
(BOOT
MODE
PIN 1)
GPIO84
(BOOT
MODE
PIN 0)
0 Parallel I/O 0 0 0
1 SCI Mode 0 0 1
2 Wait Boot Mode 0 1 0
3 Get Mode 0 1 1
4-7 EMU Boot Mode (JTAG debug probe connected) 1 X X
Note
The default behavior of Get mode is boot-to-flash. On unprogrammed devices, using Get mode will
result in repeated watchdog resets, which may prevent proper JTAG connection and device
initialization. Use Wait mode or another boot mode for unprogrammed devices.
CAUTION
Some reset sources are internally driven by the device. The user must ensure the pins used for boot
mode are not actively driven by other devices in the system for these cases. The boot configuration
has a provision for changing the boot pins in OTP. For more details, see the TMS320F2837xS
Microcontrollers Technical Reference Manual .
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8.9.1 EMU Boot or Emulation Boot
The CPU enters this boot when it detects that TRST is HIGH (that is, when a JTAG debug probe/debugger is
connected). In this mode, the user can program the EMU_BOOTCTRL control-word (at location 0xD00) to
instruct the device on how to boot. If the contents of the EMU_BOOTCTRL location are invalid, then the device
would default to WAIT Boot mode. The emulation boot allows users to verify the device boot before
programming the boot mode into OTP. Note that EMU_BOOTCTRL is not actually a register, but refers to a
location in RAM (PIE RAM). PIE RAM starts at 0xD00, but the first few locations are reserved (when initializing
the PIE vector table in application code) for these boot ROM variables.
8.9.2 WAIT Boot Mode
The device in this boot mode loops in the boot ROM. This mode is useful if users want to connect a debugger on
a secure device or if users do not want the device to execute an application in flash yet.
8.9.3 Get Mode
The default behavior of Get mode is boot-to-flash. This behavior can be changed by programming the Zx-
OTPBOOTCTRL locations in user configurable DCSM OTP. The user configurable DCSM OTP on this device is
divided in to two secure zones: Z1 and Z2. The Get mode function in boot ROM first checks if a valid
OTPBOOTCTRL value is programmed in Z1. If the answer is yes, then the device boots as per the Z1-
OTPBOOTCTRL location. The Z2-OTPBOOTCTRL location is read and decodes only if Z1-OTPBOOTCTRL is
invalid or not programmed. If either Zx-OTPBOOTCTRL location is not programmed, then the device defaults to
factory default operation, which is to use factory default boot mode pins to boot to flash if the boot mode pins are
set to GET MODE. Users can choose the device through which to boot—SPI, I2C, CAN, and USB—by
programming proper values into the user configurable DCSM OTP. More details on this can be found in the
TMS320F2837xS Microcontrollers Technical Reference Manual .
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8.9.4 Peripheral Pins Used by Bootloaders
Table 8-14 shows the GPIO pins used by each peripheral bootloader. This device supports two sets of GPIOs for
each mode, as shown in Table 8-14.
Table 8-14. GPIO Pins Used by Each Peripheral Bootloader
BOOTLOADER GPIO PINS NOTES
SCI-Boot0 SCITXDA: GPIO84
SCIRXDA: GPIO85
SCIA Boot I/O option 1 (default SCI option
when chosen through Boot Mode GPIOs)
SCI-Boot1 SCIRXDA: GPIO28
SCITXDA: GPIO29 SCIA Boot option 2 – with alternate I/Os.
Parallel Boot
D0 – GPIO65
D1 – GPIO64
D2 – GPIO58
D3 – GPIO59
D4 – GPIO60
D5 – GPIO61
D6 – GPIO62
D7 – GPIO63
HOST_CTRL – GPIO70
DSP_CTRL – GPIO69
CAN-Boot0 CANRXA: GPIO70
CANTXA: GPIO71 CAN-A Boot – I/O option 1
CAN-Boot1 CANRXA: GPIO62
CANTXA: GPIO63 CAN-A Boot – I/O option 2
I2C-Boot0 SDAA: GPIO91
SCLA: GPIO92 I2CA Boot – I/O option 1
I2C-Boot1 SDAA: GPIO32
SCLA: GPIO33 I2CA Boot – I/O option 2
SPI-Boot0
SPISIMOA - GPIO58
SPISOMIA - GPIO59
SPICLKA - GPIO60
SPISTEA - GPIO61
SPIA Boot – I/O option 1
SPI-Boot1
SPISIMOA – GPIO16
SPISOMIA – GPIO17
SPICLKA – GPIO18
SPISTEA – GPIO19
SPIA Boot – I/O option 2
USB Boot USB0DM - GPIO42
USB0DP - GPIO43
The USB Bootloader will switch the clock
source to the external crystal oscillator (X1
and X2 pins). A 20-MHz crystal should be
present on the board if this boot mode is
selected.
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8.10 Dual Code Security Module
The dual code security module (DCSM) prevents access to on-chip secure memories. The term “secure” means
access to secure memories and resources is blocked. The term “unsecure” means access is allowed; for
example, through a debugging tool such as Code Composer Studio™ (CSS).
The code security mechanism offers protection for two zones, Zone 1 (Z1) and Zone 2 (Z2). The security
implementation for both the zones is identical. Each zone has its own dedicated secure resource (OTP memory
and secure ROM) and allocated secure resource (CLA, LSx RAM, and flash sectors).
The security of each zone is ensured by its own 128-bit password (CSM password). The password for each zone
is stored in an OTP memory location based on a zone-specific link pointer. The link pointer value can be
changed to program a different set of security settings (including passwords) in OTP.
Note
THE CODE SECURITY MODULE (CSM) INCLUDED ON THIS DEVICE WAS DESIGNED TO
PASSWORD PROTECT THE DATA STORED IN THE ASSOCIATED MEMORY AND IS
WARRANTED BY TEXAS INSTRUMENTS (TI), IN ACCORDANCE WITH ITS STANDARD TERMS
AND CONDITIONS, TO CONFORM TO TI'S PUBLISHED SPECIFICATIONS FOR THE WARRANTY
PERIOD APPLICABLE FOR THIS DEVICE.
TI DOES NOT, HOWEVER, WARRANT OR REPRESENT THAT THE CSM CANNOT BE
COMPROMISED OR BREACHED OR THAT THE DATA STORED IN THE ASSOCIATED MEMORY
CANNOT BE ACCESSED THROUGH OTHER MEANS. MOREOVER, EXCEPT AS SET FORTH
ABOVE, TI MAKES NO WARRANTIES OR REPRESENTATIONS CONCERNING THE CSM OR
OPERATION OF THIS DEVICE, INCLUDING ANY IMPLIED WARRANTIES OF MERCHANTABILITY
OR FITNESS FOR A PARTICULAR PURPOSE.
IN NO EVENT SHALL TI BE LIABLE FOR ANY CONSEQUENTIAL, SPECIAL, INDIRECT,
INCIDENTAL, OR PUNITIVE DAMAGES, HOWEVER CAUSED, ARISING IN ANY WAY OUT OF
YOUR USE OF THE CSM OR THIS DEVICE, WHETHER OR NOT TI HAS BEEN ADVISED OF THE
POSSIBILITY OF SUCH DAMAGES. EXCLUDED DAMAGES INCLUDE, BUT ARE NOT LIMITED
TO LOSS OF DATA, LOSS OF GOODWILL, LOSS OF USE OR INTERRUPTION OF BUSINESS OR
OTHER ECONOMIC LOSS.
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8.11 Timers
CPU-Timers 0, 1, and 2 are identical 32-bit timers with presettable periods and with 16-bit clock prescaling. The
timers have a 32-bit count-down register that generates an interrupt when the counter reaches zero. The counter
is decremented at the CPU clock speed divided by the prescale value setting. When the counter reaches zero, it
is automatically reloaded with a 32-bit period value.
CPU-Timer 0 is for general use and is connected to the PIE block. CPU-Timer 1 is also for general use and is
connected to INT13 of the CPU. CPU-Timer 2 is reserved for TI-RTOS. It is connected to INT14 of the CPU. If
TI-RTOS is not being used, CPU-Timer 2 is available for general use.
CPU-Timer 2 can be clocked by any one of the following:
• SYSCLK (default)
• Internal zero-pin oscillator 1 (INTOSC1)
• Internal zero-pin oscillator 2 (INTOSC2)
• X1 (XTAL)
• AUXPLLCLK
8.12 Nonmaskable Interrupt With Watchdog Timer (NMIWD)
The NMIWD module is used to handle system-level errors. The conditions monitored are:
• Missing system clock due to oscillator failure
• Uncorrectable ECC error on CPU access to flash memory
• Uncorrectable ECC error on CPU, CLA, or DMA access to RAM
If the CPU does not respond to the latched error condition, then the NMI watchdog will trigger a reset after a
programmable time interval. The default time is 65536 SYSCLK cycles.
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8.13 Watchdog
The watchdog module is the same as the one on previous TMS320C2000™ MCUs, but with an optional lower
limit on the time between software resets of the counter. This windowed countdown is disabled by default, so the
watchdog is fully backwards-compatible.
The watchdog generates either a reset or an interrupt. It is clocked from the internal oscillator with a selectable
frequency divider.
Figure 8-4 shows the various functional blocks within the watchdog module.
/512
WDCLK
(INTOSC1)
Watchdog
Prescaler
WDCR(WDPS(2:0)) WDCR(WDDIS)
SCSR(WDENINT)
1-count
delay
Overflow
SYSRSn Clear
8-bit
Watchdog
Counter
WDCNTR(7:0)
WDKEY(7:0)
Watchdog
Key Detector
55 + AA
WDWCR(MIN(7:0))
Watchdog
Window
Detector
Count
Good Key
Bad Key
Out of Window
Generate
512-WDCLK
Output Pulse Watchdog Time-out
WDRSTn
WDINTn
Figure 8-4. Windowed Watchdog
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8.14 Configurable Logic Block (CLB)
The C2000 configurable logic block (CLB) is a collection of blocks that can be interconnected using software to
implement custom digital logic functions or enhance existing on-chip peripherals. The CLB is able to enhance
existing peripherals through a set of crossbar interconnections, which provide a high level of connectivity to
existing control peripherals such as enhanced pulse width modulators (ePWM), enhanced capture modules
(eCAP), and enhanced quadrature encoder pulse modules (eQEP). The crossbars also allow the CLB to be
connected to external GPIO pins. In this way, the CLB can be configured to interact with device peripherals to
perform small logical functions such as comparators, or to implement custom serial data exchange protocols.
Through the CLB, functions that would otherwise be accomplished using external logic devices can now be
implemented inside the MCU.
The CLB peripheral is configured through the CLB tool. For more information on the CLB tool, available
examples, application reports and users guide, please refer to the following location in your C2000Ware package
(C2000Ware_2_00_00_03 and higher):
C2000WARE_INSTALL_LOCATION\utilities\clb_tool\clb_syscfg\doc
CLB Tool User Guide
How to Design with the C2000™ CLB Application Report
How to Migrate Custom Logic From an FPGA/CPLD to C2000™ CLB Application Report
The CLB module and its interconnects are shown in Figure 8-5.
TMS320F28379S, TMS320F28378S, TMS320F28377S, TMS320F28377S-Q1
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I TEXAS INSTRUMENTS GPIOO Asynchronous to Synchronous Input XVBAR GPIOX Sync.+(1ual IN PUT1 Other ID Perlpherals INPUTS TRM Table: Global Signals and Mux Selecllon I cu; we Outputs CLBX TILE CLB X*BAR 0UT4/5 AUXSIGD la AUXS|G7 CLB TllEl (18 Global GPREG —> Signals Local ’ Signals CLB TILEX GPREG '—> Local —’ Si nals CLB g— lnlersecl nlhar Peripherals OUTPUT XVBAR EPWM XVBAR
Figure 8-5. CLB Overview
Absolute encoder protocol interfaces are now provided as Position Manager solutions in the C2000Ware
MotorControl SDK. Configuration files, application programmer interface (API), and use examples for such
solutions are provided with C2000Ware MotorControl SDK. In some solutions, the TI-configured CLB is used
with other on-chip resources, such as the SPI port or the C28x CPU, to perform more complex functionality. See
Table 5-1 for the devices that support the CLB feature.
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8.15 Functional Safety
TMS320C2000™ MCUs are equipped with a TI release validation-based C28x and CLA Compiler Qualification
Kit (CQ-Kit), which is available for free and may be requested at the Compiler Qualification Kit web page.
Additionally, C2000™ MCUs are supported by the TI C2000 Support from Embedded Coder from MathWorks® to
generate C2000-optimized code from a Simulink® model. Simulink® enables Model-Based Design to ease the
systematic compliance process with certified tools, including Embedded Coder®, Simulink® model verification
tools, Polyspace® code verification tools, and the IEC Certification Kit for ISO 26262 and IEC 61508 compliance.
For more information, see the How to Use Simulink for ISO 26262 Projects article.
The Error Detection in SRAM Application Report provides technical information about the nature of the SRAM bit
cell and bit array, as well as the sources of SRAM failures. It then presents methods for managing memory
failures in electronic systems. This discussion is intended for electronic system developers or integrators who
are interested in improving the robustness of the embedded SRAM.
Functional Safety-Compliant products are developed using an ISO 26262/IEC 61508-compliant hardware
development process that is independently assessed and certified to meet ASIL D/SIL 3 systematic capability
(see certificate). The TMS320F2837D, TMS320F2837xS, and TMS320F2807x MCUs have been certified to
meet a component-level random hardware capability of ASIL B/SIL 2 (see certificate).
The Functional Safety-Compliant enablers include:
• A Functional Safety Manual
• A detailed, tunable, quantitative Failure Modes, Effects, and Diagnostics Analysis (FMEDA)
• A software diagnostic library that will help shorten the time to implement various software safety mechanisms
• A collection of application reports to help in the development of functionally safe systems.
A functional safety manual that describes all of the hardware and software functional safety mechanisms is
available. See the Safety Manual for TMS320F2837xD, TMS320F2837xS, and TMS320F2807x.
A detailed, tunable, fault-injected, quantitative FMEDA that enables the calculation of random hardware metrics
—as outlined in the International Organization for Standardization ISO 26262 and the International
Electrotechnical Commission IEC 61508 for automotive and industrial applications, respectively—is also
available. This tunable FMEDA must be requested; see the C2000™ Package for Automotive and Industrial
MCUs User's Guide.
• A white paper outlining the value (or benefit) of a tunable FMEDA is available. See the Functional Safety: A
tunable FMEDA for C2000™ MCUs publication.
• Parts 1 and 2 of a five-part FMEDA tuning training are available. See the C2000™ Tunable FMEDA Training
page.
Parts 3, 4, and 5 are packaged with the tunable FMEDA, and must be requested.
The C2000 Diagnostic Software Library is a collection of different safety mechanisms designed to detect faults.
These safety mechanisms target different device components, including the C28x core, the control law
accelerator (CLA), system control, static random access memory (SRAM), flash, and communications and
control peripherals. The software safety mechanisms leverage available hardware safety features such as the
C28x hardware built-in self-test (HWBIST); error detection and correction functionality on memories; parallel
signature analysis circuitry; missing clock detection logic; watchdog counters; and hardware redundancy.
Also included are software functional safety manual, user guides, example projects, and source code to help
users shorten system integration time. The library package includes a compliance support package (CSP), a
series of documents that TI used to develop and test the diagnostic software library. The CSP provides the
necessary documentation and reports to assist users with compliance to functional safety standards: software
safety requirements specifications; a software architecture document; software module design documents;
software module unit test plans; software module unit test documents; static analysis reports; unit test reports;
dynamic analysis reports; functional test reports; and traceability documents. Users can use these documents to
comply with route 1s (as described in IEC 61508-3, section 7.4.2.12) to reuse a preexisting software element to
implement all or part of a safety function. The contents of the CSP could also help users make important
decisions for overall system safety compliance.
TMS320F28379S, TMS320F28378S, TMS320F28377S, TMS320F28377S-Q1
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Two application reports offer details about how to develop functionally safe systems with C2000 real-time control
devices:
•C2000™ Hardware Built-In Self-Test discusses the HWBIST safety mechanism, along with its functions and
features, in the F2807x/F2837xS/F2837xD series of C2000 devices. The report also addresses some
system-level considerations when using the HWBIST feature and explains how customers can use the
diagnostic library on their system.
•C2000™ CPU Memory Built-In Self-Test describes embedded memory validation using the C28x central
processing unit (CPU) during an active control loop. It discusses system challenges to memory validation as
well as the different solutions provided by C2000 devices and software. Finally, it presents the Diagnostic
Library implementations for memory testing.
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9 Applications, Implementation, and Layout
Note
Information in the following applications sections is not part of the TI component specification, and TI
does not warrant its accuracy or completeness. TI’s customers are responsible for determining
suitability of components for their purposes, as well as validating and testing their design
implementation to confirm system functionality.
9.1 TI Reference Design
The TI Reference Design Library is a robust reference design library spanning analog, embedded processor,
and connectivity. Created by TI experts to help you jump start your system design, all reference designs include
schematic or block diagrams, BOMs, and design files to speed your time to market. Search and download
designs at the Select TI reference designs page.
Industrial Servo Drive and AC Inverter Drive Reference Design
The DesignDRIVE Development Kit is a reference design for a complete industrial drive directly connecting to a
three-phase ACI or PMSM motor. Many drive topologies can be created from the combined control, power, and
communications technologies included on this single platform. This platform includes multiple position sensor
interfaces, diverse current sensing techniques, hot-side partitioning options, and expansion for safety and
industrial Ethernet.
Differential Signal Conditioning Circuit for Current and Voltage Measurement Using Fluxgate Sensors
This design provides a 4-channel signal conditioning solution for differential ADCs integrated into a
microcontroller measuring motor current using fluxgate sensors. Also provided is an alternative measurement
circuit with external differential SAR ADCs as well as circuits for high-speed overcurrent and earth fault
detection. Proper differential signal conditioning improves noise immunity on critical current measurements in
motor drives. This reference design can help increase the effective resolution of the analog-to-digital conversion,
improving motor drive efficiency.
TMS320F28379S, TMS320F28378S, TMS320F28377S, TMS320F28377S-Q1
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10 Device and Documentation Support
10.1 Device and Development Support Tool Nomenclature
To designate the stages in the product development cycle, TI assigns prefixes to the part numbers of all
TMS320™ MCU devices and support tools. Each TMS320 MCU commercial family member has one of three
prefixes: TMX, TMP, or TMS (for example, TMS320F28379S). Texas Instruments recommends two of three
possible prefix designators for its support tools: TMDX and TMDS. These prefixes represent evolutionary stages
of product development from engineering prototypes (with TMX for devices and TMDX for tools) through fully
qualified production devices and tools (with TMS for devices and TMDS for tools).
Device development evolutionary flow:
TMX Experimental device that is not necessarily representative of the final device's electrical specifications
TMP Final silicon die that conforms to the device's electrical specifications but has not completed quality and reliability
verification
TMS Fully qualified production device
Support tool development evolutionary flow:
TMDX Development-support product that has not yet completed Texas Instruments internal qualification testing
TMDS Fully qualified development-support product
TMX and TMP devices and TMDX development-support tools are shipped against the following disclaimer:
"Developmental product is intended for internal evaluation purposes."
TMS devices and TMDS development-support tools have been characterized fully, and the quality and reliability
of the device have been demonstrated fully. TI's standard warranty applies.
Predictions show that prototype devices (TMX or TMP) have a greater failure rate than the standard production
devices. Texas Instruments recommends that these devices not be used in any production system because their
expected end-use failure rate still is undefined. Only qualified production devices are to be used.
TI device nomenclature also includes a suffix with the device family name. This suffix indicates the package type
(for example, PTP) and temperature range (for example, T). Figure 10-1 provides a legend for reading the
complete device name for any family member.
For device part numbers and further ordering information, see the TI website (www.ti.com) or contact your TI
sales representative.
For additional description of the device nomenclature markings on the die, see the TMS320F2837xS MCUs
Silicon Errata .
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ITEXAs INSTRUMENTS Genetic Part Number: TMS 32D F 233795 4.11 Orderable Part Number TMS 320 F 283755 PTP T PREFIX; - - TMX : expenmwa‘ device i QUALIFICATION [m Generlc Pan Number) 1MP : praIaIype devIce BIank : NanrAmomahve TMS = quaImed devIce ,m : ()1 refers m Aqumone AEc 0100 Grade 1 qualIfIcalIon i TEMPERATURE RANGE (in Orderable Pan Number) AO‘C Io IOS‘C (T) we Io 125% (Ti) 40 c In 125C (TA) DEVICE FAMILY 326 : TMSSZO MCU Fam-Iy PACKAGE TVPE 337-aaII ZWT New Fme Pitch BaII GrId Array (nFBGA) I767PIrI PTP PowerPAD ThermaHy Enhanced LDwVProfIle Quad FIaIpack (HLQFP) 100er PZP PowerPAD ThermaHy Enhanced TIrm Quad FIaIpack (HTQFPI DEVICE 283795 283785 283773 283755 283755 2337As TECHNOLOGY F = Flash ‘- Fin 1
Figure 10-1. Device Nomenclature
10.2 Markings
Figure 10-2 provides an example of the 2837xS device markings and defines each of the markings. The device
revision can be determined by the symbols marked on the top of the package as shown in Figure 10-2. Some
prototype devices may have markings different from those illustrated.
YMLLLLS
YM
LLLL
S
$$
#
G4
Lot Trace Code
2-Digit Year/Month Code
Assembly Lot
Assembly Site Code
Wafer Fab Code as applicable
Silicon Revision Code
Green (Low Halogen and RoHS-compliant)
=
=
=
=
=
=
=
$$#-YMLLLLS
G4
F28379SPTPT
TMS320
Package
Pin 1
Figure 10-2. Example of Device Markings
Table 10-1. Determining Silicon Revision From Lot Trace Code
SILICON REVISION CODE SILICON REVISION REVID(1)
Address: 0x5D00C COMMENTS
B B 0x0002 This silicon revision is available as TMX.
C C 0x0003 This silicon revision is available as TMS.
(1) Silicon Revision ID
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10.3 Tools and Software
TI offers an extensive line of development tools. Some of the tools and software to evaluate the performance of
the device, generate code, and develop solutions are listed below. To view all available tools and software for
C2000™ real-time control MCUs, visit the C2000 real-time control MCUs – Design & development page.
Development Tools
F28379D controlCARD for C2000 Real time control development kits
The F28379D controlCARD from Texas Instruments is Position Manager-ready and an ideal product for initial
software development and short run builds for system prototypes, test stands, and many other projects that
require easy access to high-performance controllers. All C2000 controlCARDs are complete board-level modules
that utilize a HSEC180 or DIMM100 form factor to provide a low-profile single-board controller solution. The host
system needs to provide only a single 5V power rail to the controlCARD for it to be fully functional.
F28379D Experimenter Kit
C2000™ MCU Experimenter Kits provide a robust hardware prototyping platform for real-time, closed loop
control development with Texas Instruments C2000 32-bit microcontroller family. This platform is a great tool to
customize and prove-out solutions for many common power electronics applications, including motor control,
digital power supplies, solar inverters, digital LED lighting, precision sensing, and more.
Software Tools
C2000Ware for C2000 MCUs
C2000Ware for C2000 microcontrollers is a cohesive set of development software and documentation designed
to minimize software development time. From device-specific drivers and libraries to device peripheral examples,
C2000Ware provides a solid foundation to begin development and evaluation. C2000Ware is now the
recommended content delivery tool versus controlSUITE™.
Code Composer Studio™ (CCS) Integrated Development Environment (IDE) for C2000 Microcontrollers
Code Composer Studio is an integrated development environment (IDE) that supports TI's Microcontroller and
Embedded Processors portfolio. Code Composer Studio comprises a suite of tools used to develop and debug
embedded applications. It includes an optimizing C/C++ compiler, source code editor, project build environment,
debugger, profiler, and many other features. The intuitive IDE provides a single user interface taking the user
through each step of the application development flow. Familiar tools and interfaces allow users to get started
faster than ever before. Code Composer Studio combines the advantages of the Eclipse software framework
with advanced embedded debug capabilities from TI resulting in a compelling feature-rich development
environment for embedded developers.
Pin Mux Tool
The Pin Mux Utility is a software tool which provides a Graphical User Interface for configuring pin multiplexing
settings, resolving conflicts and specifying I/O cell characteristics for TI MPUs.
F021 Flash Application Programming Interface (API)
The F021 Flash Application Programming Interface (API) provides a software library of functions to program,
erase, and verify F021 on-chip Flash memory.
UniFlash Standalone Flash Tool
UniFlash is a standalone tool used to program on-chip flash memory through a GUI, command line, or scripting
interface.
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Models
Various models are available for download from the product Tools & Software pages. These include I/O Buffer
Information Specification (IBIS) Models and Boundary-Scan Description Language (BSDL) Models. To view all
available models, visit the Models section of the Tools & Software page for each device.
Training
To help assist design engineers in taking full advantage of the C2000 microcontroller features and performance,
TI has developed a variety of training resources. Utilizing the online training materials and downloadable hands-
on workshops provides an easy means for gaining a complete working knowledge of the C2000 microcontroller
family. These training resources have been designed to decrease the learning curve, while reducing
development time, and accelerating product time to market. For more information on the various training
resources, visit the C2000™ real-time control MCUs – Support & training site.
Specific F2837xD/F2837xS/F2807x hands-on training resources can be found at C2000™ MCU Device
Workshops.
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10.4 Documentation Support
To receive notification of documentation updates, navigate to the device product folder on ti.com. In the upper
right corner, click on Alert me to register and receive a weekly digest of any product information that has
changed. For change details, review the revision history included in any revised document.
The current documentation that describes the processor, related peripherals, and other technical collateral is
listed below.
Errata
TMS320F2837xS MCUs Silicon Errata describes known advisories on silicon and provides workarounds.
Technical Reference Manual
TMS320F2837xS Microcontrollers Technical Reference Manual details the integration, the environment, the
functional description, and the programming models for each peripheral and subsystem in the 2837xS
microcontrollers.
CPU User's Guides
TMS320C28x CPU and Instruction Set Reference Guide describes the central processing unit (CPU) and the
assembly language instructions of the TMS320C28x fixed-point digital signal processors (DSPs). This Reference
Guide also describes emulation features available on these DSPs.
TMS320C28x Extended Instruction Sets Technical Reference Manual describes the architecture, pipeline, and
instruction set of the TMU, VCU-II, and FPU accelerators.
Peripheral Guides
C2000 Real-Time Control Peripherals Reference Guide describes the peripheral reference guides of the 28x
DSPs.
Tools Guides
TMS320C28x Assembly Language Tools v20.2.0.LTS User's Guide describes the assembly language tools
(assembler and other tools used to develop assembly language code), assembler directives, macros, common
object file format, and symbolic debugging directives for the TMS320C28x device.
TMS320C28x Optimizing C/C++ Compiler v20.2.0.LTS User's Guide describes the TMS320C28x C/C++
compiler. This compiler accepts ANSI standard C/C++ source code and produces TMS320 DSP assembly
language source code for the TMS320C28x device.
Application Reports
Semiconductor Packing Methodology describes the packing methodologies employed to prepare semiconductor
devices for shipment to end users.
Calculating Useful Lifetimes of Embedded Processors provides a methodology for calculating the useful lifetime
of TI embedded processors (EPs) under power when used in electronic systems. It is aimed at general
engineers who wish to determine if the reliability of the TI EP meets the end system reliability requirement.
An Introduction to IBIS (I/O Buffer Information Specification) Modeling discusses various aspects of IBIS
including its history, advantages, compatibility, model generation flow, data requirements in modeling the input/
output structures and future trends.
Serial Flash Programming of C2000™ Microcontrollers discusses using a flash kernel and ROM loaders for
serial programming a device.
10.5 Support Resources
TI E2E™ support forums are an engineer's go-to source for fast, verified answers and design help — straight
from the experts. Search existing answers or ask your own question to get the quick design help you need.
Linked content is provided "AS IS" by the respective contributors. They do not constitute TI specifications and do
not necessarily reflect TI's views; see TI's Terms of Use.
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10.6 Trademarks
PowerPAD™, C2000™, Code Composer Studio™, TMS320C2000™, TMS320™, controlSUITE™, TI E2E™ are
trademarks of Texas Instruments.
Bosch® is a registered trademark of Robert Bosch GmbH Corporation.
MathWorks®, Simulink®, Embedded Coder®, Polyspace® are registered trademarks of The MathWorks, Inc.
All trademarks are the property of their respective owners.
10.7 Electrostatic Discharge Caution
This integrated circuit can be damaged by ESD. Texas Instruments recommends that all integrated circuits be handled
with appropriate precautions. Failure to observe proper handling and installation procedures can cause damage.
ESD damage can range from subtle performance degradation to complete device failure. Precision integrated circuits may
be more susceptible to damage because very small parametric changes could cause the device not to meet its published
specifications.
10.8 Glossary
TI Glossary This glossary lists and explains terms, acronyms, and definitions.
TMS320F28379S, TMS320F28378S, TMS320F28377S, TMS320F28377S-Q1
TMS320F28376S, TMS320F28375S, TMS320F28375S-Q1, TMS320F28374S
SPRS881J – AUGUST 2014 – REVISED FEBRUARY 2021 www.ti.com
210 Submit Document Feedback Copyright © 2021 Texas Instruments Incorporated
Product Folder Links: TMS320F28379S TMS320F28378S TMS320F28377S TMS320F28377S-Q1
TMS320F28376S TMS320F28375S TMS320F28375S-Q1 TMS320F28374S
I TEXAS INSTRUMENTS
11 Mechanical, Packaging, and Orderable Information
11.1 Packaging Information
The following pages include mechanical, packaging, and orderable information. This information is the most
current data available for the designated devices. This data is subject to change without notice and revision of
this document. For browser-based versions of this data sheet, refer to the left-hand navigation.
www.ti.com
TMS320F28379S, TMS320F28378S, TMS320F28377S, TMS320F28377S-Q1
TMS320F28376S, TMS320F28375S, TMS320F28375S-Q1, TMS320F28374S
SPRS881J – AUGUST 2014 – REVISED FEBRUARY 2021
Copyright © 2021 Texas Instruments Incorporated Submit Document Feedback 211
Product Folder Links: TMS320F28379S TMS320F28378S TMS320F28377S TMS320F28377S-Q1
TMS320F28376S TMS320F28375S TMS320F28375S-Q1 TMS320F28374S
I TEXAS INSTRUMENTS O mflflflflflHHHHHHHHHHHHHHHHHHHH HHHHHHHHH HHHHHHHHHHHHHH ) Pfi— HHHH HHHHHHHHHHHHHHH HHHH wwwu com
www.ti.com
PACKAGE OUTLINE
C
100X 0.27
0.17
96X 0.5
PIN 1 ID
(0.127)
TYP
0.15
0.05
0 -7
4X 12
TYP
16.2
15.8
8.64
7.45
B
NOTE 3
14.2
13.8
A
NOTE 3
14.2
13.8
0.75
0.45
0.25
GAGE PLANE
1.2 MAX
(1)
4X (0.3)
NOTE 4 4X (0.3)
NOTE 4
PLASTIC QUAD FLATPACK
PowerPAD TQFP - 1.2 mm max height
PZP0100N
4223383/A 04/2017
NOTES:
1. All linear dimensions are in millimeters. Any dimensions in parenthesis are for reference only. Dimensioning and tolerancing
per ASME Y14.5M.
2. This drawing is subject to change without notice.
3. This dimension does not include mold flash, protrusions, or gate burrs.
4. Strap features may not be present.
5. Reference JEDEC registration MS-026.
PowerPAD is a trademark of Texas Instruments.
TM
1
25
26 50
51
75
76
100
0.08 C A B
SEE DETAIL A
SEATING PLANE
DETAILA
SCALE: 14
DETAIL A
TYPICAL
0.08 C
1
SCALE 1.000
25
26 50
51
75
76
100
101
TMS320F28379S, TMS320F28378S, TMS320F28377S, TMS320F28377S-Q1
TMS320F28376S, TMS320F28375S, TMS320F28375S-Q1, TMS320F28374S
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212 Submit Document Feedback Copyright © 2021 Texas Instruments Incorporated
Product Folder Links: TMS320F28379S TMS320F28378S TMS320F28377S TMS320F28377S-Q1
TMS320F28376S TMS320F28375S TMS320F28375S-Q1 TMS320F28374S
I TEXAS INSTRUMENTS EXAMPLE BOARD LAYOUT wwwu com
www.ti.com
EXAMPLE BOARD LAYOUT
0.05 MAX
ALL AROUND 0.05 MIN
ALL AROUND
(15.4)
(15.4)
96X (0.5)
100X (1.5)
100X (0.3)
( 0.2) TYP
VIA
( 8.64)
( 12)
NOTE 10
(R0.05) TYP
(1) TYP
(1) TYP
PowerPAD TQFP - 1.2 mm max heightPZP0100N
PLASTIC QUAD FLATPACK
4223383/A 04/2017
TM
NOTES: (continued)
6. Publication IPC-7351 may have alternate designs.
7. Solder mask tolerances between and around signal pads can vary based on board fabrication site.
8. This package is designed to be soldered to a thermal pad on the board. See technical brief, Powerpad thermally enhanced package,
Texas Instruments Literature No. SLMA002 (www.ti.com/lit/slma002) and SLMA004 (www.ti.com/lit/slma004).
9. Vias are optional depending on application, refer to device data sheet. It is recommended that vias under paste be filled,
plugged or tented.
10. Size of metal pad may vary due to creepage requirement.
EXPOSED METAL SHOWN
LAND PATTERN EXAMPLE
SCALE:5X
SYMM
SYMM
100 76
26 50
51
75
1
25
SOLDER MASK
DEFINED PAD
METAL COVERED
BY SOLDER MASK
101
SEE DETAILS
METAL
SOLDER MASK
OPENING
NON SOLDER MASK
DEFINED SOLDER MASK DETAILS
EXPOSED METAL
SOLDER MASK
OPENING
METAL UNDER
SOLDER MASK
SOLDER MASK
DEFINED
EXPOSED METAL
www.ti.com
TMS320F28379S, TMS320F28378S, TMS320F28377S, TMS320F28377S-Q1
TMS320F28376S, TMS320F28375S, TMS320F28375S-Q1, TMS320F28374S
SPRS881J – AUGUST 2014 – REVISED FEBRUARY 2021
Copyright © 2021 Texas Instruments Incorporated Submit Document Feedback 213
Product Folder Links: TMS320F28379S TMS320F28378S TMS320F28377S TMS320F28377S-Q1
TMS320F28376S TMS320F28375S TMS320F28375S-Q1 TMS320F28374S
EXAMPLE STENCIL DESIGN WE; EEEEE %% L: 1r
www.ti.com
EXAMPLE STENCIL DESIGN
(8.64)
96X (0.5)
100X (1.5)
100X (0.3)
(R0.05) TYP
(15.4)
(15.4)
7.3 X 7.30.175
7.89 X 7.890.150
8.64 X 8.64 (SHOWN)0.125
9.66 X 9.660.1
SOLDER STENCIL
OPENING
STENCIL
THICKNESS
PowerPAD TQFP - 1.2 mm max height
PZP0100N
PLASTIC QUAD FLATPACK
4223383/A 04/2017
NOTES: (continued)
11. Laser cutting apertures with trapezoidal walls and rounded corners may offer better paste release. IPC-7525 may have alternate
design recommendations.
12. Board assembly site may have different recommendations for stencil design.
TM
SOLDER PASTE EXAMPLE
EXPOSED PAD
100% PRINTED SOLDER COVERAGE BY AREA
SCALE:6X
SEE TABLE FOR
DIFFERENT OPENINGS
FOR OTHER STENCIL
THICKNESSES
BASED ON
0.125 THICK STENCIL
SYMM
SYMM
100 76
26 50
51
75
1
25
BY SOLDER MASK
METAL COVERED
101
TMS320F28379S, TMS320F28378S, TMS320F28377S, TMS320F28377S-Q1
TMS320F28376S, TMS320F28375S, TMS320F28375S-Q1, TMS320F28374S
SPRS881J – AUGUST 2014 – REVISED FEBRUARY 2021 www.ti.com
214 Submit Document Feedback Copyright © 2021 Texas Instruments Incorporated
Product Folder Links: TMS320F28379S TMS320F28378S TMS320F28377S TMS320F28377S-Q1
TMS320F28376S TMS320F28375S TMS320F28375S-Q1 TMS320F28374S
TEXAS INSTRUMENTS O 17 HHHHHHHHHHHHHHHHHHHHHMHHHHWHHHHWHHHHHM WWMHHHHHWHHHHWHHHHM ) 71 I L NOTEA Ax\ 02 MAX uuuuuuwwuuuu wuuuwwuuuw UUUWWUUUUW LILILIHHHUUUUUHHHUUUUWUUUUW
www.ti.com
PACKAGE OUTLINE
C
176X 0.27
0.17
172X 0.5
PIN 1 ID
(0.13)
TYP
0.15
0.05
0 -7
4X 21.5
TYP
26.2
25.8
7.33
6.78
8.07
7.53
4X 0.78 MAX
NOTE 4
4X
0.54 MAX
NOTE 4
4X
0.2 MAX
NOTE 4
BNOTE 3
24.2
23.8
A
NOTE 3
24.2
23.8
0.75
0.45
0.25
GAGE PLANE
1.6 MAX
(1.4)
PowerPAD HLQFP - 1.6 mm max height
PTP0176F
PLASTIC QUAD FLATPACK
4223382/A 03/2017
NOTES:
1. All linear dimensions are in millimeters. Any dimensions in parenthesis are for reference only. Dimensioning and tolerancing
per ASME Y14.5M.
2. This drawing is subject to change without notice.
3. This dimension does not include mold flash, protrusions, or gate burrs.
4. Strap features my not present.
5. Reference JEDEC registration MS-026.
TM
PowerPAD is a trademark of Texas Instruments.
1
44
45 88
89
132
133
176
0.08 C A B
SEE DETAIL A
SEATING PLANE
DETAILA
SCALE: 12
DETAIL A
TYPICAL
0.08 C
1
SCALE 0.550
44
45 88
89
132
133
176
177
EXPOSED
THERMAL PAD
www.ti.com
TMS320F28379S, TMS320F28378S, TMS320F28377S, TMS320F28377S-Q1
TMS320F28376S, TMS320F28375S, TMS320F28375S-Q1, TMS320F28374S
SPRS881J – AUGUST 2014 – REVISED FEBRUARY 2021
Copyright © 2021 Texas Instruments Incorporated Submit Document Feedback 215
Product Folder Links: TMS320F28379S TMS320F28378S TMS320F28377S TMS320F28377S-Q1
TMS320F28376S TMS320F28375S TMS320F28375S-Q1 TMS320F28374S
fl TEXAS INSTRUMENTS EEEEEEE MC 10 Size 0! ms|a\ pad may vary due to creenge requiremem
EXAMPLE BOARD LAYOUT
0.05 MAX
ALL AROUND 0.05 MIN
ALL AROUND
(25.5)
172X (0.5)
176X (1.45)
176X (0.3)
( 0.2) TYP
VIA
(8.07)
( 22)
NOTE 10
(R0.05) TYP
(1.5 TYP)
(1.5 TYP)
(7.33) (25.5)
PowerPAD HLQFP - 1.6 mm max heightPTP0176F
PLASTIC QUAD FLATPACK
4223382/A 03/2017
NOTES: (continued)
6. Publication IPC-7351 may have alternate designs.
7. Solder mask tolerances between and around signal pads can vary based on board fabrication site.
8. This package is designed to be soldered to a thermal pad on the board. See technical brief, Powerpad thermally enhanced package,
Texas Instruments Literature No. SLMA002 (www.ti.com/lit/slma002) and SLMA004 (www.ti.com/lit/slma004).
9. Vias are optional depending on application, refer to device data sheet. It is recommended that vias under paste be filled, plugged
or tented.
10. Size of metal pad may vary due to creepage requirement.
TM
LAND PATTERN EXAMPLE
EXPOSED METAL SHOWN
SCALE:4X
SYMM
SYMM
176 133
45 88
89
132
1
44
SOLDER MASK
DEFINED PAD
METAL COVERED
BY SOLDER MASK
177
SEE DETAILS
METAL
SOLDER MASK
OPENING
NON SOLDER MASK
DEFINED SOLDER MASK DETAILS
EXPOSED METAL
SOLDER MASK
OPENING
METAL UNDER
SOLDER MASK
SOLDER MASK
DEFINED
EXPOSED METAL
TMS320F28379S, TMS320F28378S, TMS320F28377S, TMS320F28377S-Q1
TMS320F28376S, TMS320F28375S, TMS320F28375S-Q1, TMS320F28374S
SPRS881J – AUGUST 2014 – REVISED FEBRUARY 2021 www.ti.com
216 Submit Document Feedback Copyright © 2021 Texas Instruments Incorporated
Product Folder Links: TMS320F28379S TMS320F28378S TMS320F28377S TMS320F28377S-Q1
TMS320F28376S TMS320F28375S TMS320F28375S-Q1 TMS320F28374S
WEEEEEEEEE EEEEEEEEEE EEEEEEEEEEE LT LI E vi EEEEEEEEEE + {5‘ TEXAS INSTRUMENTS TEXAS Insmmmls www li Com
www.ti.com
EXAMPLE STENCIL DESIGN
(8.07)
BASED ON
0.125 THICK STENCIL
172X (0.5)
176X (1.45)
176X (0.3)
(R0.05) TYP
(25.5)
(25.5)
(7.33)
BASED ON
0.125 THICK
STENCIL
6.82 X 6.20.175
7.37 X 6.690.150
8.07 X 7.33 (SHOWN)0.125
9.02 X 8.20.1
SOLDER STENCIL
OPENING
STENCIL
THICKNESS
PowerPAD HLQFP - 1.6 mm max height
PTP0176F
PLASTIC QUAD FLATPACK
4223382/A 03/2017
NOTES: (continued)
11. Laser cutting apertures with trapezoidal walls and rounded corners may offer better paste release. IPC-7525 may have alternate
design recommendations.
12. Board assembly site may have different recommendations for stencil design.
TM
SOLDER PASTE EXAMPLE
EXPOSED PAD
100% PRINTED SOLDER COVERAGE BY AREA
SCALE:4X
THICKNESSES
FOR OTHER STENCIL
DIFFERENT OPENINGS
SEE TABLE FOR
SYMM
SYMM
176 133
45 88
89
132
1
44
BY SOLDER MASK
METAL COVERED
177
www.ti.com
TMS320F28379S, TMS320F28378S, TMS320F28377S, TMS320F28377S-Q1
TMS320F28376S, TMS320F28375S, TMS320F28375S-Q1, TMS320F28374S
SPRS881J – AUGUST 2014 – REVISED FEBRUARY 2021
Copyright © 2021 Texas Instruments Incorporated Submit Document Feedback 217
Product Folder Links: TMS320F28379S TMS320F28378S TMS320F28377S TMS320F28377S-Q1
TMS320F28376S TMS320F28375S TMS320F28375S-Q1 TMS320F28374S
I TEXAS INSTRUMENTS Samples Samples Samples Samples Samples Samples Samples Samples Samples Samples Samples Samples Samples Samples Samples Samples Samples
PACKAGE OPTION ADDENDUM
www.ti.com 29-Jan-2021
Addendum-Page 1
PACKAGING INFORMATION
Orderable Device Status
(1)
Package Type Package
Drawing Pins Package
Qty Eco Plan
(2)
Lead finish/
Ball material
(6)
MSL Peak Temp
(3)
Op Temp (°C) Device Marking
(4/5)
Samples
TMS320F28374SPTPS ACTIVE HLQFP PTP 176 40 RoHS & Green NIPDAU Level-3-260C-168 HR -40 to 125 TMS320
F28374SPTPS
TMS320F28374SPTPSR ACTIVE HLQFP PTP 176 200 RoHS & Green NIPDAU Level-3-260C-168 HR -40 to 125 TMS320
F28374SPTPS
TMS320F28374SPTPT ACTIVE HLQFP PTP 176 40 RoHS & Green NIPDAU Level-3-260C-168 HR -40 to 105 TMS320
F28374SPTPT
TMS320F28374SPZPS ACTIVE HTQFP PZP 100 90 RoHS & Green NIPDAU Level-3-260C-168 HR -40 to 125 TMS320
F28374SPZPS
TMS320F28374SPZPT ACTIVE HTQFP PZP 100 90 RoHS & Green NIPDAU Level-3-260C-168 HR -40 to 105 TMS320
F28374SPZPT
TMS320F28374SZWTS ACTIVE NFBGA ZWT 337 90 RoHS & Green SNAGCU Level-3-260C-168 HR -40 to 125 TMS320
F28374SZWTS
TMS320F28374SZWTT ACTIVE NFBGA ZWT 337 90 RoHS & Green SNAGCU Level-3-260C-168 HR -40 to 105 TMS320
F28374SZWTT
TMS320F28374SZWTTR ACTIVE NFBGA ZWT 337 1000 RoHS & Green SNAGCU Level-3-260C-168 HR -40 to 105 TMS320
F28374SZWTT
TMS320F28375SPTPS ACTIVE HLQFP PTP 176 40 RoHS & Green NIPDAU Level-3-260C-168 HR -40 to 125 TMS320
F28375SPTPS
TMS320F28375SPTPT ACTIVE HLQFP PTP 176 40 RoHS & Green NIPDAU Level-3-260C-168 HR -40 to 105 TMS320
F28375SPTPT
TMS320F28375SPZPQ ACTIVE HTQFP PZP 100 90 RoHS & Green NIPDAU Level-3-260C-168 HR -40 to 125 TMS320
F28375SPZPQ
TMS320F28375SPZPQR ACTIVE HTQFP PZP 100 1000 RoHS & Green NIPDAU Level-3-260C-168 HR -40 to 125 TMS320
F28375SPZPQ
TMS320F28375SPZPS ACTIVE HTQFP PZP 100 90 RoHS & Green NIPDAU Level-3-260C-168 HR -40 to 125 TMS320
F28375SPZPS
TMS320F28375SPZPT ACTIVE HTQFP PZP 100 90 RoHS & Green NIPDAU Level-3-260C-168 HR -40 to 105 TMS320
F28375SPZPT
TMS320F28375SZWTS ACTIVE NFBGA ZWT 337 90 RoHS & Green SNAGCU Level-3-260C-168 HR -40 to 125 TMS320
F28375SZWTS
TMS320F28375SZWTT ACTIVE NFBGA ZWT 337 90 RoHS & Green SNAGCU Level-3-260C-168 HR -40 to 105 TMS320
F28375SZWTT
TMS320F28376SPTPS ACTIVE HLQFP PTP 176 40 RoHS & Green NIPDAU Level-3-260C-168 HR -40 to 125 TMS320
I TEXAS INSTRUMENTS Samples Samples Samples Samples Samples Samples Samples Samples Samples Samples Samples Samples Samples Samples Samples Samples Samples
PACKAGE OPTION ADDENDUM
www.ti.com 29-Jan-2021
Addendum-Page 2
Orderable Device Status
(1)
Package Type Package
Drawing Pins Package
Qty Eco Plan
(2)
Lead finish/
Ball material
(6)
MSL Peak Temp
(3)
Op Temp (°C) Device Marking
(4/5)
Samples
F28376SPTPS
TMS320F28376SPTPT ACTIVE HLQFP PTP 176 40 RoHS & Green NIPDAU Level-3-260C-168 HR -40 to 105 TMS320
F28376SPTPT
TMS320F28376SPZPS ACTIVE HTQFP PZP 100 90 RoHS & Green NIPDAU Level-3-260C-168 HR -40 to 125 TMS320
F28376SPZPS
TMS320F28376SPZPT ACTIVE HTQFP PZP 100 90 RoHS & Green NIPDAU Level-3-260C-168 HR -40 to 105 TMS320
F28376SPZPT
TMS320F28376SZWTS ACTIVE NFBGA ZWT 337 90 RoHS & Green SNAGCU Level-3-260C-168 HR -40 to 125 TMS320
F28376SZWTS
TMS320F28376SZWTT ACTIVE NFBGA ZWT 337 90 RoHS & Green SNAGCU Level-3-260C-168 HR -40 to 105 TMS320
F28376SZWTT
TMS320F28377SPTPQ ACTIVE HLQFP PTP 176 40 RoHS & Green NIPDAU Level-3-260C-168 HR -40 to 125 TMS320
F28377SPTPQ
TMS320F28377SPTPS ACTIVE HLQFP PTP 176 40 RoHS & Green NIPDAU Level-3-260C-168 HR -40 to 125 TMS320
F28377SPTPS
TMS320F28377SPTPT ACTIVE HLQFP PTP 176 40 RoHS & Green NIPDAU Level-3-260C-168 HR -40 to 105 TMS320
F28377SPTPT
TMS320F28377SPZPQ ACTIVE HTQFP PZP 100 90 RoHS & Green NIPDAU Level-3-260C-168 HR -40 to 125 TMS320
F28377SPZPQ
TMS320F28377SPZPS ACTIVE HTQFP PZP 100 90 RoHS & Green NIPDAU Level-3-260C-168 HR -40 to 125 TMS320
F28377SPZPS
TMS320F28377SPZPT ACTIVE HTQFP PZP 100 90 RoHS & Green NIPDAU Level-3-260C-168 HR -40 to 105 TMS320
F28377SPZPT
TMS320F28377SZWTQ ACTIVE NFBGA ZWT 337 90 RoHS & Green SNAGCU Level-3-260C-168 HR -40 to 125 TMS320
F28377SZWTQ
TMS320F28377SZWTS ACTIVE NFBGA ZWT 337 90 RoHS & Green SNAGCU Level-3-260C-168 HR -40 to 125 TMS320
F28377SZWTS
TMS320F28377SZWTT ACTIVE NFBGA ZWT 337 90 RoHS & Green SNAGCU Level-3-260C-168 HR -40 to 105 TMS320
F28377SZWTT
TMS320F28378SPTPS ACTIVE HLQFP PTP 176 40 RoHS & Green NIPDAU Level-3-260C-168 HR -40 to 125 TMS320
F28378SPTPS
TMS320F28378SPZPS ACTIVE HTQFP PZP 100 90 RoHS & Green NIPDAU Level-3-260C-168 HR -40 to 125 TMS320
F28378SPZPS
TMS320F28379SPTPS ACTIVE HLQFP PTP 176 40 RoHS & Green NIPDAU Level-3-260C-168 HR -40 to 125 TMS320
F28379SPTPS
I TEXAS INSTRUMENTS Samples Samples Samples Samples Samples
PACKAGE OPTION ADDENDUM
www.ti.com 29-Jan-2021
Addendum-Page 3
Orderable Device Status
(1)
Package Type Package
Drawing Pins Package
Qty Eco Plan
(2)
Lead finish/
Ball material
(6)
MSL Peak Temp
(3)
Op Temp (°C) Device Marking
(4/5)
Samples
TMS320F28379SPTPT ACTIVE HLQFP PTP 176 40 RoHS & Green NIPDAU Level-3-260C-168 HR -40 to 105 TMS320
F28379SPTPT
TMS320F28379SPZPS ACTIVE HTQFP PZP 100 90 RoHS & Green NIPDAU Level-3-260C-168 HR -40 to 125 TMS320
F28379SPZPS
TMS320F28379SPZPT ACTIVE HTQFP PZP 100 90 RoHS & Green NIPDAU Level-3-260C-168 HR -40 to 105 TMS320
F28379SPZPT
TMS320F28379SZWTS ACTIVE NFBGA ZWT 337 90 RoHS & Green SNAGCU Level-3-260C-168 HR -40 to 125 TMS320
F28379SZWTS
TMS320F28379SZWTT ACTIVE NFBGA ZWT 337 90 RoHS & Green SNAGCU Level-3-260C-168 HR -40 to 105 TMS320
F28379SZWTT
(1) The marketing status values are defined as follows:
ACTIVE: Product device recommended for new designs.
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design.
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.
OBSOLETE: TI has discontinued the production of the device.
(2) RoHS: TI defines "RoHS" to mean semiconductor products that are compliant with the current EU RoHS requirements for all 10 RoHS substances, including the requirement that RoHS substance
do not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, "RoHS" products are suitable for use in specified lead-free processes. TI may
reference these types of products as "Pb-Free".
RoHS Exempt: TI defines "RoHS Exempt" to mean products that contain lead but are compliant with EU RoHS pursuant to a specific EU RoHS exemption.
Green: TI defines "Green" to mean the content of Chlorine (Cl) and Bromine (Br) based flame retardants meet JS709B low halogen requirements of <=1000ppm threshold. Antimony trioxide based
flame retardants must also meet the <=1000ppm threshold requirement.
(3) MSL, Peak Temp. - The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature.
(4) There may be additional marking, which relates to the logo, the lot trace code information, or the environmental category on the device.
(5) Multiple Device Markings will be inside parentheses. Only one Device Marking contained in parentheses and separated by a "~" will appear on a device. If a line is indented then it is a continuation
of the previous line and the two combined represent the entire Device Marking for that device.
(6) Lead finish/Ball material - Orderable Devices may have multiple material finish options. Finish options are separated by a vertical ruled line. Lead finish/Ball material values may wrap to two
lines if the finish value exceeds the maximum column width.
I TEXAS INSTRUMENTS
PACKAGE OPTION ADDENDUM
www.ti.com 29-Jan-2021
Addendum-Page 4
Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information
provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and
continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals.
TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited information may not be available for release.
In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI to Customer on an annual basis.
I TEXAS INSTRUMENTS ‘3‘ V.'
PACKAGE MATERIALS INFORMATION
www.ti.com 2-May-2022
TAPE AND REEL INFORMATION
Reel Width (W1)
REEL DIMENSIONS
A0
B0
K0
W
Dimension designed to accommodate the component length
Dimension designed to accommodate the component thickness
Overall width of the carrier tape
Pitch between successive cavity centers
Dimension designed to accommodate the component width
TAPE DIMENSIONS
K0 P1
B0 W
A0
Cavity
QUADRANT ASSIGNMENTS FOR PIN 1 ORIENTATION IN TAPE
Pocket Quadrants
Sprocket Holes
Q1 Q1Q2 Q2
Q3 Q3Q4 Q4 User Direction of Feed
P1
Reel
Diameter
*All dimensions are nominal
Device Package
Type Package
Drawing Pins SPQ Reel
Diameter
(mm)
Reel
Width
W1 (mm)
A0
(mm) B0
(mm) K0
(mm) P1
(mm) W
(mm) Pin1
Quadrant
TMS320F28375SPZPQR HTQFP PZP 100 1000 330.0 24.4 17.0 17.0 1.5 20.0 24.0 Q2
Pack Materials-Page 1
PACKAGE MATERIALS INFORMATION
www.ti.com 2-May-2022
TAPE AND REEL BOX DIMENSIONS
Width (mm)
W
L
H
*All dimensions are nominal
Device Package Type Package Drawing Pins SPQ Length (mm) Width (mm) Height (mm)
TMS320F28375SPZPQR HTQFP PZP 100 1000 367.0 367.0 55.0
Pack Materials-Page 2
{if TEXAS INSTRUMENTS E 1 +++++J;T;L+++++++ +++++++++++++++ +++++++++++++++ +++++++++++++++ +++++++++++++++ +++++++++++++++ t-
PACKAGE MATERIALS INFORMATION
www.ti.com 2-May-2022
TRAY
L - Outer tray length without tabs KO -
Outer
tray
height
W -
Outer
tray
width
P1 - Tray unit pocket pitch
CW - Measurement for tray edge (Y direction) to corner pocket center
CL - Measurement for tray edge (X direction) to corner pocket center
Text
Chamfer on Tray corner indicates Pin 1 orientation of packed units.
*All dimensions are nominal
Device Package
Name Package
Type Pins SPQ Unit array
matrix Max
temperature
(°C)
L (mm) W
(mm) K0
(µm) P1
(mm) CL
(mm) CW
(mm)
TMS320F28374SPTPT PTP HLQFP 176 40 4x10 150 315 135.9 7620 20.7 30.4 20.7
TMS320F28374SPZPT PZP HTQFP 100 90 6 X 15 150 315 135.9 7620 15.4 20.3 21
TMS320F28374SZWTT ZWT NFBGA 337 90 6 X 15 150 315 135.9 7620 20 17.5 15.45
TMS320F28375SPTPS PTP HLQFP 176 40 4x10 150 315 135.9 7620 20.7 30.4 20.7
TMS320F28375SPTPT PTP HLQFP 176 40 4x10 150 315 135.9 7620 20.7 30.4 20.7
TMS320F28375SPZPQ PZP HTQFP 100 90 6 X 15 150 315 135.9 7620 15.4 20.3 21
TMS320F28375SPZPT PZP HTQFP 100 90 6 X 15 150 315 135.9 7620 15.4 20.3 21
TMS320F28375SZWTT ZWT NFBGA 337 90 6 X 15 150 315 135.9 7620 20 17.5 15.45
TMS320F28376SPTPT PTP HLQFP 176 40 4x10 150 315 135.9 7620 20.7 30.4 20.7
TMS320F28376SZWTT ZWT NFBGA 337 90 6 X 15 150 315 135.9 7620 20 17.5 15.45
TMS320F28377SPTPQ PTP HLQFP 176 40 4x10 150 315 135.9 7620 20.7 30.4 20.7
TMS320F28377SPTPS PTP HLQFP 176 40 4x10 150 315 135.9 7620 20.7 30.4 20.7
TMS320F28377SPTPT PTP HLQFP 176 40 4x10 150 315 135.9 7620 20.7 30.4 20.7
TMS320F28377SPZPQ PZP HTQFP 100 90 6 X 15 150 315 135.9 7620 15.4 20.3 21
TMS320F28377SPZPS PZP HTQFP 100 90 6 X 15 150 315 135.9 7620 15.4 20.3 21
TMS320F28377SPZPT PZP HTQFP 100 90 6 X 15 150 315 135.9 7620 15.4 20.3 21
TMS320F28377SZWTQ ZWT NFBGA 337 90 6 X 15 150 315 135.9 7620 20 17.5 15.45
Pack Materials-Page 3
I TEXAS INSTRUMENTS
PACKAGE MATERIALS INFORMATION
www.ti.com 2-May-2022
Device Package
Name Package
Type Pins SPQ Unit array
matrix Max
temperature
(°C)
L (mm) W
(mm) K0
(µm) P1
(mm) CL
(mm) CW
(mm)
TMS320F28377SZWTS ZWT NFBGA 337 90 6 X 15 150 315 135.9 7620 20 17.5 15.45
TMS320F28377SZWTT ZWT NFBGA 337 90 6 X 15 150 315 135.9 7620 20 17.5 15.45
TMS320F28378SPTPS PTP HLQFP 176 40 4x10 150 315 135.9 7620 20.7 30.4 20.7
TMS320F28378SPZPS PZP HTQFP 100 90 6 X 15 150 315 135.9 7620 15.4 20.3 21
TMS320F28379SPTPS PTP HLQFP 176 40 4x10 150 315 135.9 7620 20.7 30.4 20.7
TMS320F28379SPTPT PTP HLQFP 176 40 4x10 150 315 135.9 7620 20.7 30.4 20.7
TMS320F28379SPZPS PZP HTQFP 100 90 6 X 15 150 315 135.9 7620 15.4 20.3 21
TMS320F28379SPZPT PZP HTQFP 100 90 6 X 15 150 315 135.9 7620 15.4 20.3 21
TMS320F28379SZWTS ZWT NFBGA 337 90 6 X 15 150 315 135.9 7620 20 17.5 15.45
TMS320F28379SZWTT ZWT NFBGA 337 90 6 X 15 150 315 135.9 7620 20 17.5 15.45
Pack Materials-Page 4
5@ @ @¢¢ aw T Y% X , ‘000000000 0Qd000000 000000000 000000000 000000000 000000000 000000000 000000000 0000000000000000000 000000000 000000000 000000 000000 000000 00 00 000000 000000 00 00 000000 000000100000‘00¢00¢ 000000 00 00 000000 000000 00 00 000000 000000 , 000000 000000000 000000000 000000000 000000000 000000000 000000000 000000000 000000000 000000000000000000®w ‘000000000 000000000\ , w , f E
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PACKAGE OUTLINE
C
1.4 MAX
TYP
0.45
0.35
14.4
TYP
14.4 TYP
0.8 TYP
0.8 TYP
337X 0.55
0.45
B16.1
15.9 A
16.1
15.9
(0.8) TYP
(0.8) TYP
NFBGA - 1.4 mm max heightZWT0337A
PLASTIC BALL GRID ARRAY
4223381/A 02/2017
NOTES:
1. All linear dimensions are in millimeters. Any dimensions in parenthesis are for reference only. Dimensioning and tolerancing
per ASME Y14.5M.
2. This drawing is subject to change without notice.
13 14 15 16 17 18 19
BALL A1 CORNER
SEATING PLANE
BALL TYP 0.12 C
0.15 C A B
0.05 C
SYMM
SYMM
BALL A1 CORNER
W
C
D
E
F
G
H
J
K
L
M
N
P
R
T
U
V
12 3 45678910 11
A
B
12
SCALE 0.950
«D \ a 7 @OOOOOOO‘QJOOOOOOOOO fi®OOOOOOOO$OOOOOOOOO ’ 000000000 000000000 OOOOOOOOO¢OOOOOOOOO OOOOOOOOO®OOOOOOOOO OOOOOOOOO?OOOOOOOOO OOOOOO ‘ 000000 000000 OOCDOO 000000 000000 OO¢OO OOOOOO v 60—66790776{%®€*@7676—990—07¢ OOOOOO OOQEOO 000000 000000 OOQDOO 000000 000000 ‘ OOOOOO OOOOOOOOOIEOOOOOOOOO OOOOOOOOOCDOOOOOOOOO OOOOOOOOOfiOOOOOOOOO 000000000 000000000 OOOOOOOOO®OOOOOOOOO OOOOOOOOO¢OOOOOOOOO E “a V WF/ E ‘ L "nzxns
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EXAMPLE BOARD LAYOUT
337X ( 0.4) (0.8) TYP
(0.8) TYP
( 0.4)
METAL
0.05 MAX
SOLDER MASK
OPENING
METAL UNDER
SOLDER MASK
( 0.4)
SOLDER MASK
OPENING
0.05 MIN
NFBGA - 1.4 mm max heightZWT0337A
PLASTIC BALL GRID ARRAY
4223381/A 02/2017
NOTES: (continued)
3. Final dimensions may vary due to manufacturing tolerance considerations and also routing constraints.
For information, see Texas Instruments literature number SPRAA99 (www.ti.com/lit/spraa99).
SYMM
SYMM
LAND PATTERN EXAMPLE
EXPOSED METAL SHOWN
SCALE:7X
1234567 8 910 11
B
A
W
V
U
T
R
P
N
M
L
K
J
H
G
F
E
D
C
12 13 14 15 16 17 18 19
NON-SOLDER MASK
DEFINED
(PREFERRED)
SOLDER MASK DETAILS
NOT TO SCALE
EXPOSED METAL
SOLDER MASK
DEFINED
EXPOSED METAL
1 (<2) oooogdooooooooo="" 6%="" o="" 0="" ill="" 000000000="" 000000000="" 3="" 000000000="" *iqoooooooo="" 00="" 00="" oo="" 00="" oo="" 00="" oo="" 00="" b‘nwr="" 00="" oo="" 00="" oo="" 00="" oo="" 00="" oo="" 00="" 000000000="" 000000000="" 000000="" 000000="" 000000="" go—gfi*@©**9{}®fi*€k*fi*©—ggo—oi="" 00500="" ooqoo="" v="" i="" 000000="" 000000="" 000000="" 00600="" 000000="" oo¢oo="" 000000="" 000000="" 000000="" 000000="" 000000="" (5000000000="" oooooooooqooooooooo="" 000000000="" 000000000="" 000000000="" ooooooooocdooooooooo="" ooooooooo$ooooooooo="" 000000000="" 000000000="">
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EXAMPLE STENCIL DESIGN
(0.8) TYP
(0.8) TYP ( 0.4) TYP
NFBGA - 1.4 mm max heightZWT0337A
PLASTIC BALL GRID ARRAY
4223381/A 02/2017
NOTES: (continued)
4. Laser cutting apertures with trapezoidal walls and rounded corners may offer better paste release.
SOLDER PASTE EXAMPLE
BASED ON 0.15 mm THICK STENCIL
SCALE:7X
SYMM
SYMM
1234567 8 910 11
B
A
W
V
U
T
R
P
N
M
L
K
J
H
G
F
E
D
C
12 13 14 15 16 17 18 19
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