Datenblatt für TC8220 von Microchip Technology

I N? M? |___ an T080
Supertex inc.
Supertex inc.
www.supertex.com
Doc.# DSFP-TC8220
B080713
TC8220
Features
►High voltage Vertical DMOS technology
►Integrated gate-to-source resistor
►Integrated gate-to-source Zener diode
►Low threshold, Low on-resistance
►Low input & output capacitance
►Fast switching speeds
►Electrically isolated N- and P-MOSFET pairs
Applications
►High voltage pulsers
►Amplifiers
►Buffers
►Piezoelectric transducer drivers
►General purpose line drivers
►Logic level interfaces
Two Pair, N- and P-Channel
Enhancement-Mode MOSFET
General Description
The Supertex TC8220 consists of two pairs of high voltage, low
threshold N-channel and P-channel MOSFETs in a 12-Lead DFN
package. All MOSFETs have integrated the gate-to-source resistors
and gate-to-source Zener diode clamps which are desired for high
voltage pulser applications. The complimentary, high-speed, high
voltage, gate-clamped N and P-channel MOSFET pairs utilize an
advanced vertical DMOS structure and Supertex’s well-proven
silicon-gate manufacturing process. This combination produces a
device with the power handling capabilities of bipolar transistors
and with the high input impedance and positive temperature
coefficient inherent in MOS devices.
Characteristic of all MOS structures, these devices are free from
thermal runaway and thermally induced secondary breakdown.
Supertex’s vertical DMOS FETs are ideally suited to a wide range
of switching and amplifying applications where very low threshold
voltage, high breakdown voltage, high input impedance, low input
and output capacitance, and fast switching speeds are desired.
Typical Application Circuit
1.8 to 5.0V
Logic Imputs OUTB
VDD VH
INA
INB
OE
0.1µF
+10V
Supertex
TC
8
22
0
DAMP
VL
GND
INC
IND
VSS
+PULSE
-PULSE
ENAB
V
PP
+100V
10nF
Supertex
MD1822
0.47µF
OUTA
OUTD
OUTC 1.0µF
1.0µF
V
NN
-100V
1 Absolute Maximum Ratings Typical Thermal Resistance 1 Note: 8220 YWLL
2
Supertex inc.
www.supertex.com
Doc.# DSFP-TC8220
B080713
TC8220
Absolute Maximum Ratings
Parameter Value
Drain-to-source voltage BVDSS
Drain-to-gate voltage BVDGS
Operating and storage temperature -55°C to +150°C
Absolute Maximum Ratings are those values beyond which damage to
the device may occur. Functional operation under these conditions is not
implied. Continuous operation of the device at the absolute rating level
may affect device reliability. All voltages are referenced to device ground.
Pin Configuration
12-Lead DFN
(top view)
12-Lead DFN
Package Marking
Package may or may not include the following marks: Si or
8220
YWLL
Y = Last Digit of Year Sealed
W = Code for Week Sealed
L = Lot Number
= “Green” Packaging
1
2
3
4
5
6
12
11
10
9
8
7
SN1
DN1
DP1
SP1
DN2
DP2
GN1
GP1
GN2
SN2
GP2
SP2
Thermal
Pad
Ordering Information
Part Number Package Option Packing
TC8220K6-G 12-Lead DFN (4x4) 3000/Reel
Product Summary
BVDSS/BVDGS RDS(ON) (max)
N-Channel P-Channel N-Channel P-Channel
200V -200V 5.3Ω6.5Ω
Note:
1.0oz, 4-layer, 3”x4” PCB.
Typical Thermal Resistance
Package θja
12-Lead DFN 42OC/W
-G denotes a lead (Pb)-free / RoHS compliant package
N-Channel Electrical Characteristics *90% 10% g 90%
3
Supertex inc.
www.supertex.com
Doc.# DSFP-TC8220
B080713
TC8220
N-Channel Switching Waveforms and Test Circuit
10%
90%
90%
10%
90%
10%
R
GEN
INPUT
Pulse
Generator
V
DD
R
L
D.U.T
OUTPUT
tr tf
td(ON)
t(ON)
td(OFF)
t(OFF)
10V
INPUT
0V
VDD
OUTPUT
0V
N-Channel Electrical Characteristics (TA = 25°C unless otherwise specified)
Sym Parameter Min Typ Max Units Conditions
BVDSS Drain-to-source breakdown voltage 200 - - V VGS = 0V, ID = 2.0mA
VGS(th) Gate threshold voltage 1.0 - 2.4 V VGS = VDS, ID = 1.0mA
ΔVGS(th) Change in VGS(th) with temperature - - -4.5 mV/OC VGS = VDS, ID = 1.0mA
RGS Gate-to-source shunt resistor 10 - 50 KΩ IGS = 100µA
VZGS Gate-to-source Zener voltage 13.2 - 25 V IGS = 2.0mA
IDSS Zero gate voltage drain current
- - 10.0 µA VDS = Max rating, VGS = 0V
- - 1.0 mA VDS = 0.8 Max Rating,
VGS = 0V, TA = 125OC
ID(ON) On-state drain current 1.3 - - AVGS = 5.0V, VDS = 25V
2.3 - - VGS = 10V, VDS = 50V
RDS(ON) Static drain-to-source on-state resistance - - 6.5 ΩVGS = 5.0V, ID = 150mA
- - 6.0 VGS = 10V, ID = 1.0A
ΔRDS(ON) Change in RDS(ON) with temperature - - 1.0 %/OC VGS = 10V, ID =1.0A
GFS Forward transconductance 400 - - mmho VDS = 25V, ID = 500mA
CISS Input capacitance - 56 -
pF
VGS = 0V,
VDS = 25V,
f = 1.0MHz
COSS Common source output capacitance - 13 -
CRSS Reverse transfer capacitance - 2.0 -
td(ON) Turn-on delay time - - 10
ns
VDD =25V,
ID = 1.0A,
RGEN = 25Ω
trRise time - - 15
td(OFF) Turn-off delay time - - 20
tfFall time - - 15
VSD Diode forward voltage drop - - 1.8 V VGS = 0V, ISD = 500mA
trr Reverse recovery time - 300 - ns VGS = 0V, ISD = 500mA
Notes:
1. All D.C. parameters 100% tested at 25OC unless otherwise stated. (Pulse test: 300µs pulse, 2% duty cycle.)
2. All A.C. parameters sample tested.
P-Channel Electrical Characteristics
4
Supertex inc.
www.supertex.com
Doc.# DSFP-TC8220
B080713
TC8220
P-Channel Electrical Characteristics (TA = 25°C unless otherwise specified)
Sym Parameter Min Typ Max Units Conditions
BVDSS Drain-to-source breakdown voltage -200 - - V VGS = 0V, ID = -2.0mA
VGS(th) Gate threshold voltage -1.0 - -2.4 V VGS = VDS, ID = -1.0mA
ΔVGS(th) Change in VGS(th) with temperature - - 4.5 mV/OC VGS = VDS, ID = -1.0mA
RGS Gate-to-source shunt resistor 10 - 50 KΩIGS = 100µA
VZGS Gate-to-source Zener voltage 13.2 - 25 V IGS = -2.0mA
IDSS Zero gate voltage drain current
- - -10 µA VDS = Max rating, VGS = 0V
- - -1.0 mA VDS = 0.8 Max Rating,
VGS = 0V, TA = 125OC
ID(ON) On-state drain current -1.2 - - AVGS = -5.0V, VDS = -25V
-2.3 - - VGS = -10V, VDS = -50V
RDS(ON) Static drain-to-source on-state resistance - - 8.5 ΩVGS = -5.0V, ID = -150mA
- - 7.0 VGS = -10V, ID = -1.0A
ΔRDS(ON) Change in RDS(ON) with temperature - - 1.0 %/OC VGS = -10V, ID = -1.0A
GFS Forward transconductance 400 - - mmho VDS = -25V, ID = -500mA
CISS Input capacitance - 75 -
pF
VGS = 0V,
VDS = -25V,
f = 1.0MHz
COSS Common source output capacitance - 21 -
CRSS Reverse transfer capacitance - 6.5 -
td(ON) Turn-on delay time - - 10
ns
VDD = -25V,
ID = -1.0A,
RGEN = 25Ω
trRise time - - 15
td(OFF) Turn-off delay time - - 20
tfFall time - - 15
VSD Diode forward voltage drop - - -1.8 V VGS = 0V, ISD = -500mA
trr Reverse recovery time - 300 - ns VGS = 0V, ISD = -500mA
Notes:
1. All D.C. parameters 100% tested at 25OC unless otherwise stated. (Pulse test: 300µs pulse, 2% duty cycle.)
2. All A.C. parameters sample tested.
P-Channel Switching Waveforms and Test Circuit
R
GEN
INPUT
Pulse
Generator
V
DD
R
L
D.U.T
OUTPUT
0V
INPUT
-10V
tr tf
td(ON)
t(ON)
90%
10%
90%
10%
10%
90%
td(OFF)
t(OFF)
0V
OUTPUT
VDD
5
Supertex inc.
www.supertex.com
Doc.# DSFP-TC8220
B080713
TC8220
Pin Description
Pin # Function Description Pin # Function Description
1 GN1 Gate of N-MOSFET 1 7 DP2 Drain of P-MOSFET 2
2 GP1 Gate of P-MOSFET 1 8 DN2 Drain of N-MOSFET 2
3 GN2 Gate of N-MOSFET 2 9 SP1 Source of P-MOSFET 1
4 SN2 Source of N-MOSFET 2 10 DP1 Drain of P-MOSFET 1
5 GP2 Gate of P-MOSFET 2 11 DN1 Drain of N-MOSFET 1
6 SP2 Source of P-MOSFET 2 12 SN1 Source of N-MOSFET 1
Thermal Pad Die attachment substrate, must be grounded externally
Note:
Thermal Pad must be grounded.
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Supertex inc. does not recommend the use of its products in life support applications, and will not knowingly sell them for use in such applications unless it receives
an adequate “product liability indemnification insurance agreement.” Supertex inc. does not assume responsibility for use of devices described, and limits its liability
to the replacement of the devices determined defective due to workmanship. No responsibility is assumed for possible omissions and inaccuracies. Circuitry and
specifications are subject to change without notice. For the latest product specifications refer to the Supertex inc. (website: http//www.supertex.com)
©2013 Supertex inc. All rights reserved. Unauthorized use or reproduction is prohibited. Supertex inc.
1235 Bordeaux Drive, Sunnyvale, CA 94089
Tel: 408-222-8888
www.supertex.com
6
TC8220
(The package drawing(s) in this data sheet may not reflect the most current specifications. For the latest package outline
information go to http://www.supertex.com/packaging.html.)
Doc.# DSFP-TC8220
B080713
12-Lead DFN Package Outline (K6)
4.00x4.00mm body, 1.00mm height (max), 0.50mm pitch
Symbol A A1 A3 b D D2 E E2 e L L1 θ
Dimension
(mm)
MIN 0.80 0.00
0.20
REF
0.18 3.85 3.19 3.85 2.29
0.50
BSC
0.30 0.00 0O
NOM 0.90 0.02 0.25 4.00 3.34 4.00 2.44 0.40 - -
MAX 1.00 0.05 0.30 4.15 3.44 4.15 2.54 0.50 0.15 14O
Drawings not to scale.
Supertex Doc.#: DSPD-12DFNK64X4P050, Version A030210.
Seating
Plane
θ
Top View
Side View
Bottom View
A
A1
D
E
D2
e
b
E2
A3 L
L1
View B
View B
Note 1
(Index Area
D/2 x E/2)
Note 3
Note 2
Note 1
(Index Area
D/2 x E/2)
12
1
12
1
Notes:
1. A Pin 1 identifier must be located in the index area indicated. The Pin 1 identifier can be: a molded mark/identifier; an embedded metal marker; or
a printed indicator.
2. Depending on the method of manufacturing, a maximum of 0.15mm pullback (L1) may be present.
3. The inner tip of the lead may be either rounded or square.