Datenblatt für TCA9544A von Texas Instruments

V'.‘ 1!. B X E I TEXAS INSTRUMENTS
TCA9544A
Slaves A , A ...A0 1 N
Slaves B , B ...B0 1 N
I2C or SMBus
Master
(e.g. Processor)
SDA
SCL
INT
SD0
SC0
INT0
Channel 0
Channel 1
SD1
SC1
INT1
VCC
A0
A1
GND
A2
Slaves C , C ...C0 1 N
Channel 2
SD2
SC2
INT1
Slaves D , D ...D0 1 N
Channel 3
SD3
SC3
INT3
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An IMPORTANT NOTICE at the end of this data sheet addresses availability, warranty, changes, use in safety-critical applications,
intellectual property matters and other important disclaimers. PRODUCTION DATA.
TCA9544A
SCPS209C –MAY 2014–REVISED NOVEMBER 2019
TCA9544A Low Voltage 4-Channel I
2
C and SMBus Multiplexer With Interrupt Logic
1
1 Features
1• 1-of-4 Bidirectional Translating Switches
• I2C Bus and SMBus Compatible
• Four Active-Low Interrupt Inputs
• Active-Low Interrupt Output
• Three Address Pins, Allowing up to Eight
TCA9544A Devices on the I2C Bus
• Channel Selection Via I2C Bus
• Power-Up With All Switch Channels Deselected
• Low RON Switches
• Allows Voltage-Level Translation Between 1.8-V,
2.5-V, 3.3-V, and 5-V Buses
• No Glitch on Power-Up
• Supports Hot Insertion
• Low Standby Current
• Operating Power Supply Voltage Range of
1.65 V to 5.5 V
• 5.5-V Tolerant Inputs
• 0 to 400-kHz Clock Frequency
• Latch-Up Performance Exceeds 100 mA Per
JESD 78
• ESD Protection Exceeds JESD 22
– 4000-V Human-Body Model (A114-A)
– 1500-V Charged-Device Model (C101)
2 Applications
• Servers
• Routers (Telecom Switching Equipment)
•Factory Automation
• Products With I2C Slave Address Conflicts (For
Example, Multiple, Identical Temp Sensors)
3 Description
The TCA9544A is a 4-channel, bidirectional
translating I2C Muliplexer. The master SCL/SDA
signal pair is directed to one of the four channels of
slave devices, SC0/SD0-SC3/SD3. Four interrupt
inputs (INT3–INT0), one for each of the downstream
pairs, are provided. One interrupt output (INT) acts as
an AND of the four interrupt inputs.
A power-on reset function returns the registers to
their default state and initializes the I2C state
machine, with all channels deselected.
The pass gates of the switches are constructed such
that the VCC pin can be used to limit the maximum
high voltage which will be passed by the TCA9544A.
This allows the use of different bus voltages on each
pair, so that 1.8-V, 2.5-V, or 3.3-V parts can
communicate with 5-V parts without any additional
protection. External pull-up resistors pull the bus up
to the desired voltage level for each channel. All I/O
pins are 5.5 V tolerant.
Device Information(1)
PART NUMBER PACKAGE BODY SIZE (NOM)
TCA9544A TSSOP (20) 6.50 mm × 4.40 mm
(1) For all available packages, see the orderable addendum at
the end of the data sheet.
Simplified Schematic
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Table of Contents
1 Features.................................................................. 1
2 Applications ........................................................... 1
3 Description ............................................................. 1
4 Revision History..................................................... 2
5 Pin Configuration and Functions......................... 3
6 Specifications......................................................... 4
6.1 Absolute Maximum Ratings ...................................... 4
6.2 ESD Ratings.............................................................. 4
6.3 Recommended Operating Conditions ...................... 4
6.4 Thermal Information.................................................. 4
6.5 Electrical Characteristics........................................... 5
6.6 I2C Interface Timing Requirements........................... 6
6.7 Switching Characteristics.......................................... 6
6.8 Interrupt Timing Requirements ................................. 7
6.9 Typical Characteristics.............................................. 7
7 Parameter Measurement Information .................. 8
8 Detailed Description............................................ 10
8.1 Overview ................................................................. 10
8.2 Functional Block Diagram....................................... 10
8.3 Feature Description................................................. 11
8.4 Device Functional Modes........................................ 11
8.5 Programming .......................................................... 11
8.6 Control Register ...................................................... 13
9 Application and Implementation ........................ 16
9.1 Application Information............................................ 16
9.2 Typical Application .................................................. 16
10 Power Supply Recommendations ..................... 19
10.1 Power-On Reset Requirements ........................... 19
11 Layout................................................................... 21
11.1 Layout Guidelines ................................................. 21
11.2 Layout Example .................................................... 21
12 Device and Documentation Support ................. 22
12.1 Receiving Notification of Documentation Updates 22
12.2 Support Resources ............................................... 22
12.3 Trademarks........................................................... 22
12.4 Electrostatic Discharge Caution............................ 22
12.5 Glossary................................................................ 22
13 Mechanical, Packaging, and Orderable
Information ........................................................... 22
4 Revision History
Changes from Revision B (May 2018) to Revision C Page
• Changed VCC = 1.65 V to 5.5 V To: VCC = 2.5 V in Figure 15 ............................................................................................. 16
Changes from Revision A (May 2014) to Revision B Page
• Changed the first paragraph of the Description...................................................................................................................... 1
• Added Tstg to the Absolute Maximum Ratings table............................................................................................................... 4
• Changed the first paragraph of the Overview section.......................................................................................................... 10
• Changed "switch" to "multiplexer" in the Feature Description section.................................................................................. 11
• Changed text in the Control Register Definition section From: "One or several SCn/SDn downstream pairs, or
channels, are selected..." To: "One SCn/SDn downstream pair, or channel, is selected..."................................................ 14
Changes from Original (May 2014) to Revision A Page
• Updated document from PREVIEW to PRODUCTION DATA. ............................................................................................. 1
*9 TEXAS INSTRUMENTS
1A0 20 VCC
2A1 19 SDA
3A2 18 SCL
4INT0 17 INT
5SD0 16 SC3
6SC0 15 SD3
7INT1 14 INT3
8SD1 13 SC2
9SC1 12 SD2
10GND 11 INT2
Not to scale
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5 Pin Configuration and Functions
PW Package
Top View
(1) VDPUX is the pull-up reference voltage for the associated data line. VDPUM is the master I2C reference voltage while VDPU0 — VDPU3 are
the slave channel reference voltages.
Pin Functions
PIN DESCRIPTION
NAME NO.
A0 1 Address input 0. Connect directly to VCC or ground.
A1 2 Address input 1. Connect directly to VCC or ground.
A2 3 Address input 2. Connect directly to VCC or ground.
INT0 4 Active-low interrupt input 0. Connect to VDPU0(1) through a pull-up resistor.
SD0 5 Serial data 0. Connect to VDPU0(1) through a pull-up resistor.
SC0 6 Serial clock 0. Connect to VDPU0(1) through a pull-up resistor.
INT1 7 Active-low interrupt input 1. Connect to VDPU1(1) through a pull-up resistor.
SD1 8 Serial data 1. Connect to VDPU1(1) through a pull-up resistor.
SC1 9 Serial clock 1. Connect to VDPU1(1) through a pull-up resistor.
GND 10 Ground
INT2 11 Active-low interrupt input 2. Connect to VDPU2(1) through a pull-up resistor.
SD2 12 Serial data 2. Connect to VDPU2(1) through a pull-up resistor.
SC2 13 Serial clock 2. Connect to VDPU2(1) through a pull-up resistor.
INT3 14 Active-low interrupt input 3. Connect to VDPU3(1) through a pull-up resistor.
SD3 15 Serial data 3. Connect to VDPU3(1) through a pull-up resistor.
SC3 16 Serial clock 3. Connect to VDPU3(1) through a pull-up resistor.
INT 17 Active-low interrupt output. Connect to VDPUM(1) through a pull-up resistor.
SCL 18 Serial clock line. Connect to VDPUM(1) through a pull-up resistor.
SDA 19 Serial data line. Connect to VDPUM(1) through a pull-up resistor.
VCC 20 Supply power
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(1) Stresses beyond those listed under "absolute maximum ratings" may cause permanent damage to the device. These are stress ratings
only, and functional operation of the device at these or any other conditions beyond those indicated under "recommended operating
conditions" is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
(2) The input negative-voltage and output voltage ratings may be exceeded if the input and output current ratings are observed.
6 Specifications
6.1 Absolute Maximum Ratings(1)
over operating free-air temperature (unless otherwise noted)
MIN MAX UNIT
VCC Supply voltage –0.5 7 V
VIInput voltage(2) –0.5 7 V
IIInput current ±20 mA
IOOutput current ±25 mA
Continuous current through VCC ±100 mA
Continuous current through GND ±100 mA
Ptot Total power dissipation 400 mW
TAOperating free-air temperature range –40 85 °C
Tstg Storage temperature range –65 150 °C
(1) JEDEC document JEP155 states that 500-V HBM allows safe manufacturing with a standard ESD control process.
(2) JEDEC document JEP157 states that 250-V CDM allows safe manufacturing with a standard ESD control process.
6.2 ESD Ratings
MIN MAX UNIT
V(ESD) Electrostatic discharge
Human body model (HBM), per ANSI/ESDA/JEDEC JS-001, all pins(1) –4000 4000 V
Charged device model (CDM), per JEDEC specification JESD22-C101,
all pins(2) –1500 1500 V
(1) All unused inputs of the device must be held at VCC or GND to ensure proper device operation. Refer to the TI application report,
Implications of Slow or Floating CMOS Inputs, literature number SCBA004.
6.3 Recommended Operating Conditions(1)
MIN MAX UNIT
VCC Supply voltage 1.65 5.5 V
VIH High-level input voltage SCL, SDA 0.7 × VCC 6V
A2–A0, INT3–INT0 0.7 × VCC VCC + 0.5
VIL Low-level input voltage SCL, SDA –0.5 0.3 × VCC V
A2–A0, INT3–INT0 –0.5 0.3 × VCC
TAOperating free-air temperature –40 85 °C
(1) For more information about traditional and new thermal metrics, see the Semiconductor and IC Package Thermal Metrics application
report.
6.4 Thermal Information(1)
over operating free-air temperature range (unless otherwise noted)
THERMAL METRIC(1)
TCA9544A
UNITPW
20 PIN
RθJA Junction-to-ambient thermal resistance 118.2 °C/W
RθJCtop Junction-to-case (top) thermal resistance 51.4 °C/W
RθJB Junction-to-board thermal resistance 69.3 °C/W
ψJT Junction-to-top characterization parameter 7.7 °C/W
ψJB Junction-to-board characterization parameter 68.8 v
l TEXAS INSTRUMENTS
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(1) For operation between specified voltage ranges, refer to the worst-case parameter in both applicable ranges.
(2) All typical values are at nominal supply voltage (1.8-V, 2.5-V, 3.3-V, or 5-V VCC), TA= 25°C.
(3) The power-on reset circuit resets the I2C bus logic when VCC < VPORF.
6.5 Electrical Characteristics(1)
over recommended operating free-air temperature range (unless otherwise noted)
PARAMETER TEST CONDITIONS VCC MIN TYP(2) MAX UNIT
VPORR Power-on reset voltage, VCC
rising No load: VI= VCC or GND 1.2 1.5 V
VPORF Power-on reset voltage, VCC
falling(3) No load: VI= VCC or GND 0.8 1 V
Vpass Switch output voltage VSWin = VCC ISWout = –100 μA
5 V 3.6
V
4.5 to 5.5 V 2.6 4.5
3.3 V 1.9
3 to 3.6 V 1.6 2.8
2.5 V 1.4
2.3 to 2.7 V 1.0 1.8
1.8 V 0.8
1.65 to 1.95 V 0.5 1.1
IOH INT VO= VCC 1.65 to 5.5 V 10 μA
IOL SDA VOL = 0.4 V
1.65 to 5.5 V
3 7
mAVOL = 0.6 V 6 10
INT VOL = 0.4 V 3
II
SCL, SDA
VI= VCC or GND 1.65 to 5.5 V
±1
μA
SC3–SC0, SD3–SD0 ±1
A2–A0 ±1
INT3–INT0 ±1
ICC
Operating
mode
fSCL = 400 kHz VI= VCC or GND
IO= 0
tr,max = 300 ns
5.5 V 50
μA
3.6 V 20
2.7 V 11
1.65 V 6
fSCL = 100 kHz VI= VCC or GND
IO= 0
tr,max = 1 µs
5.5 V 35
3.6 V 14
2.7 V 5
1.65 V 2
Standby mode
Low inputs VI= GND IO= 0
5.5 V 1.6 2
3.6 V 1.0 1.3
2.7 V 0.7 1.1
1.65 V 0.4 0.55
High inputs VI= VCC IO= 0
5.5 V 1.6 2
3.6 V 1.0 1.3
2.7 V 0.7 1.1
1.65 V 0.4 0.55
ΔICC Supply-current
change
INT3–INT0
One INT3–INT0 input at 0.6 V,
Other inputs at VCC or GND
1.65 to 5.5 V
3 20
μA
One INT3–INT0 input at VCC – 0.6 V,
Other inputs at VCC or GND 3 20
SCL, SDA
SCL or SDA input at 0.6 V,
Other inputs at VCC or GND 2 15
SCL or SDA inputs at VCC – 0.6 V,
Other inputs at VCC or GND 2 15
CiA2–A0 VI= VCC or GND 1.65 to 5.5 V 4.5 6 pF
INT3–INT0 4.5 6
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Electrical Characteristics(1) (continued)
over recommended operating free-air temperature range (unless otherwise noted)
PARAMETER TEST CONDITIONS VCC MIN TYP(2) MAX UNIT
(4) Cio(ON) depends on device capacitance and load that is downstream from the device.
Cio(OFF) (4) SCL, SDA VI= VCC or GND Switch OFF 1.65 to 5.5 V 15 19 pF
SC3–SC0, SD3–SD0 6 8
RON Switch-on resistance
VO= 0.4 V IO= 15 mA 4.5 to 5.5 V 10 16
Ω
3 to 3.6 V 13 20
VO= 0.4 V IO= 10 mA 2.3 to 2.7 V 16 45
1.65 to 1.95 V 25 70
(1) A device internally must provide a hold time of at least 300 ns for the SDA signal (referred to as the VIH min of the SCL signal), in order
to bridge the undefined region of the falling edge of SCL.
(2) Cb= total bus capacitance of one bus line in pF
(3) Data taken using a 1-kΩpullup resistor and 50-pF load (see Figure 5).
6.6 I2C Interface Timing Requirements
over recommended operating free-air temperature range (unless otherwise noted)
STANDARD-MODE
I2C BUS FAST-MODE
I2C BUS UNIT
MIN MAX MIN MAX
fscl I2C clock frequency 0 100 0 400 kHz
tsch I2C clock high time 4 0.6 μs
tscl I2C clock low time 4.7 1.3 μs
tsp I2C spike time 50 50 ns
tsds I2C serial-data setup time 250 100 ns
tsdh I2C serial-data hold time 0(1) 0(1) μs
ticr I2C input rise time 1000 20 + 0.1Cb(2) 300 ns
ticf I2C input fall time 300 20 + 0.1Cb(2) 300 ns
tocf I2C output fall time (10-pF to 400-pF bus) 300 20 + 0.1Cb(2) 300 ns
tbuf I2C bus free time between stop and start 4.7 1.3 μs
tsts I2C start or repeated start condition setup 4.7 0.6 μs
tsth I2C start or repeated start condition hold 4 0.6 μs
tsps I2C stop condition setup 4 0.6 μs
tvdL(Data) Valid-data time (high to low)(3) SCL low to SDA output low valid 1 1 μs
tvdH(Data) Valid-data time (low to high)(3) SCL low to SDA output high valid 0.6 0.6 μs
tvd(ack) Valid-data time of ACK condition ACK signal from SCL low
to SDA output low 1 1 μs
CbI2C bus capacitive load 400 400 pF
(1) The propagation delay is the calculated RC time constant of the typical ON-state resistance of the switch and the specified load
capacitance, when driven by an ideal voltage source (zero output impedance).
(2) Data taken using a 4.7-kΩpullup resistor and 100-pF load (see Figure 6).
6.7 Switching Characteristics
over recommended operating free-air temperature range, CL≤100 pF (unless otherwise noted) (see Figure 5)
PARAMETER FROM
(INPUT) TO
(OUTPUT) MIN MAX UNIT
tpd (1) Propagation delay time RON = 20 Ω, CL= 15 pF SDA or SCL SDn or SCn 0.3 ns
RON = 20 Ω, CL= 50 pF 1
tiv Interrupt valid time(2) INTn INT 4 μs
tir Interrupt reset delay time(2) INTn INT 2 μs
l TEXAS INSTRUMENTS sou an //
VCC (V)
CIO(OFF) (pF)
0 0.5 1 1.5 2 2.5 3 3.5 4 4.5 5 5.5
4
4.2
4.4
4.6
4.8
5
5.2
5.4
5.6
5.8
6
D006
25ºC (Room Temperature)
85ºC
-40º
VCC (V)
RON (Ohm)
0 0.5 1 1.5 2 2.5 3 3.5 4 4.5 5 5.5
0
5
10
15
20
25
30
D001
25ºC (Room Temperature)
85ºC
-40ºC
VCC (V)
ICC, Standby Mode (µA)
1.5 2 2.5 3 3.5 4 4.5 5 5.5
0.2
0.4
0.6
0.8
1
1.2
1.4
1.6
1.8
D004
25ºC (Room Temperature)
85ºC
-40ºC
7
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(1) Data taken using a 4.7-kΩpullup resistor and 100-pF load (see Figure 6).
6.8 Interrupt Timing Requirements
over recommended operating free-air temperature range (unless otherwise noted)
PARAMETER MIN MAX UNIT
tPWRL Low-level pulse duration rejection of INTn inputs(1) 1μs
tPWRH High-level pulse duration rejection of INTn inputs(1) 0.5 μs
6.9 Typical Characteristics
Figure 1. SDA Output Low Voltage (VOL) vs Load Current
(IOL) at Three VCC Levels Figure 2. Standby Current (ICC) vs Supply Voltage (VCC) at
Three Temperature Points
Figure 3. Slave channel (SCn/SDn) capacitance (Cio(OFF)) vs.
Supply Voltage (VCC) at Three Temperature Points Figure 4. ON-Resistance (RON) vs Supply Voltage (VCC) at
Three Temperatures
l TEXAS INSTRUMENTS DUT IZC-PORT LOAD co Two Bytes ‘ DeviceF ‘ Slop sun Address ’ Condition Condition Bil7 AEIZSS 000 “We“ aim ACK Bin 0 o (P) (S) (MSB) 3'” (LSB) (A) (MSB) ‘scl ‘ ‘ ‘ ‘ ‘scn SCL \ \ \ ‘ ‘ ‘ 1 1 ‘va ‘ 71777 0.3 xvcc ‘ "E" W ‘ x x \ x \i for” ‘ 1 “ “WT—hf 1 mi r ‘ ‘ 'Spfl f ‘ , 1 ‘w 1 \ x ‘ \ ‘ ‘ r- 7 cJ7>
RL = 1 kΩ
VCC
CL = 50 pF
(See Note A)
tbuf
ticr
tsth tsds
tsdh
ticf
ticr
tscl tsch
tsts
tvd(ACK)
or tvdL
tvdH
0.3 × VCC
Stop
Condition
tsps
Repeat
Start
Condition
Start or Repeat
Start Condition
SCL
SDA
Start
Condition
(S)
Address
Bit 7
(MSB)
Data
Bit 0
(LSB)
Stop
Condition
(P)
Two Bytes for Complete
Device Programming
I2C-PORT LOAD CONFIGURATION
VOLTAGE WAVEFORMS
ticf
Stop
Condition
(P)
tsp
DUT SDn, SCn
0.7 × VCC
0.3 × VCC
0.7 × VCC
R/W
Bit 0
(LSB)
ACK
(A)
Data
Bit 7
(MSB)
Address
Bit 1
Address
Bit 6
ACK
(A)
BYTE DESCRIPTION
I2C address + R/W
Control register data
1
2
NOTES: A. CL includes probe and jig capacitance.
B. All input pulses are supplied by generators having the following characteristics: PRR ≤ 10 MHz, ZO = 50 Ω, tr/tf ≤ 30 ns.
C. The outputs are measured one at a time, with one transition per measurement.
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7 Parameter Measurement Information
Figure 5. I2C Interface Load Circuit, Byte Descriptions, and Voltage Waveforms
l TEXAS INSTRUMENTS DUT I INTERRUPT LOAD 0 AH mpm pu‘ses are supphed by generators havmg me couowmg charactenshcs PRR 510 MHZ Zo : so a «,1,
RL = 4.7 kΩ
VCC
CL = 100 pF
(See Note A)
INTERRUPT LOAD CONFIGURATION
DUT INT
0.5 × VCC
INTn
(input)
VOLTAGE WAVEFORMS (tiv)
tiv
VOLTAGE WAVEFORMS (tir)
INT
(output) 0.5 × VCC
INTn
(input)
INT
(output)
0.5 × VCC
0.5 × VCC
tir
NOTES: A. CL includes probe and jig capacitance.
B. All input pulses are supplied by generators having the following characteristics: PRR ≤ 10 MHz, ZO = 50 Ω, tr/tf ≤ 30 ns.
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Parameter Measurement Information (continued)
Figure 6. Interrupt Load Circuit and Voltage Waveforms
l TEXAS INSTRUMENTS
Switch Control Logic
I2C Bus Control
Interrupt Logic
Input Filter
Power-on Reset
TCA9544A
SC0
A1
A0
INT
INT0
SDA
SCL
GND
SD3
SD2
SD1
SD0
SC3
SC2
SC1
VCC
A2
6
9
13
16
5
8
12
15
10
20
18
19
1
2
3
17
INT1
INT2
INT3
4
7
11
14
Output
Filter
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8 Detailed Description
8.1 Overview
The TCA9544A is a 4-channel, bidirectional translating I2C Muliplexer. The master SCL/SDA signal pair is
directed to one of the four channels of slave devices, SC0/SD0-SC3/SD3. Four interrupt inputs (INT3–INT0), one
for each of the downstream pairs, are provided. One interrupt output (INT) acts as an AND of the four interrupt
inputs.
The device can be reset by cycling the power supply, VCC, also known as a power-on reset (POR), which resets
the state machine and allows the TCA9544A to recover should one of the downstream I2C buses get stuck in a
low state. A POR event will cause all channels to be deselected.
The connections of the I2C data path are controlled by the same I2C master device that is switched to
communicate with multiple I2C slaves. After the successful acknowledgment of the slave address (hardware
selectable by A0-A2 pins), a single 8-bit control register is written to or read from to determine the selected
channels and state of the interrupts.
The TCA9544A may also be used for voltage translation, allowing the use of different bus voltages on each
SCn/SDn pair such that 1.8-V, 2.5-V, or 3.3-V parts can communicate with 5-V parts. This is achieved by using
external pull-up resistors to pull the bus up to the desired voltage for the master and each slave channel.
8.2 Functional Block Diagram
‘5‘ TEXAS INSTRUMENTS \ Allowed Data Valid
SDA
SCL
Start Condition
S
Stop Condition
P
SDA
SCL
Data Line
Stable;
Data Valid
Change
of Data
Allowed
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8.3 Feature Description
The TCA9544A is a 4-channel, bidirectional translating multiplexer for I2C buses that supports Standard-Mode
(100 kHz) and Fast-Mode (400 kHz) operation. The TCA9544A features I2C control using a single 8-bit control
register in which the three least significant bits control the enabling and disabling of the 4 switch channels of I2C
data flow. The TCA9544A also supports interrupt signals for each slave channel and this data is held in the four
most significant bits of the control register. Depending on the application, voltage translation of the I2C bus can
also be achieved using the TCA9544A to allow 1.8-V, 2.5-V, or 3.3-V parts to communicate with 5-V parts.
Additionally, in the event that communication on the I2C bus enters a fault state, the TCA9544A can be reset to
resume normal operation by means of a power-on reset which results from cycling power to the device.
8.4 Device Functional Modes
8.4.1 Power-On Reset
When power is applied to VCC, an internal power-on reset holds the TCA9544A in a reset condition until VCC has
reached VPORR. At this point, the reset condition is released, and the TCA9544A registers and I2C state machine
are initialized to their default states, all zeroes, causing all the channels to be deselected. Thereafter, VCC must
be lowered below VPORF to reset the device.
8.5 Programming
8.5.1 I2C Interface
The I2C bus is for two-way two-line communication between different ICs or modules. The two lines are a serial
data line (SDA) and a serial clock line (SCL). Both lines must be connected to a positive supply via a pull-up
resistor when connected to the output stages of a device. Data transfer can be initiated only when the bus is not
busy.
One data bit is transferred during each clock pulse. The data on the SDA line must remain stable during the high
period of the clock pulse, as changes in the data line at this time are interpreted as control signals (see Figure 7).
Figure 7. Bit Transfer
Both data and clock lines remain high when the bus is not busy. A high-to-low transition of the data line while the
clock is high is defined as the start condition (S). A low-to-high transition of the data line while the clock is high is
defined as the stop condition (P) (see Figure 8).
Figure 8. Definition of Start and Stop Conditions
‘5‘ TEXAS INSTRUMENTS XIX
Data Output
by Transmitter
SCL From
Master
Start
Condition
S
1 2 8 9
Data Output
by Receiver
Clock Pulse for ACK
NACK
ACK
SDA
SCL
Master
Transmitter/
Receiver
Slave
Receiver
Slave
Transmitter/
Receiver
Master
Transmitter
Master
Transmitter/
Receiver
I2C
Multiplexer
Slave
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Programming (continued)
A device generating a message is a transmitter; a device receiving a message is the receiver. The device that
controls the message is the master, and the devices that are controlled by the master are the slaves (see
Figure 9).
Figure 9. System Configuration
The number of data bytes transferred between the start and the stop conditions from transmitter to receiver is not
limited. Each byte of eight bits is followed by one ACK bit. The transmitter must release the SDA line before the
receiver can send an ACK bit.
When a slave receiver is addressed, it must generate an acknowledge (ACK) after the reception of each byte.
Also, a master must generate an ACK after the reception of each byte that has been clocked out of the slave
transmitter. The device that acknowledges must pull down the SDA line during the ACK clock pulse so that the
SDA line is stable low during the high pulse of the ACK-related clock period (see Figure 10). Setup and hold
times must be taken into account.
Figure 10. Acknowledgment on the I2C Bus
A master receiver must signal an end of data to the transmitter by not generating an acknowledge (NACK) after
the last byte has been clocked out of the slave. This is done by the master receiver by holding the SDA line high.
In this event, the transmitter must release the data line to enable the master to generate a stop condition.
Data is transmitted to the TCA9544A control register using the write mode shown in Figure 11.
l TEXAS INSTRUMENTS f ff ff Slop Condition
1 1 1 0A1A2 A0
Slave Address
R/W
Fixed Hardware
Selectable
ANA
S 1 1 1 0 A2 A1 A0 1SDA INT0
INT3 INT2 INT1 P
0B2 B1 B0
Start Condition R/W ACK From Slave NACK From Master Stop Condition
Slave Address Control Register
A AS 1 1 1 0 A2 A1 A0 0
Start Condition
SDA
R/W ACK From Slave ACK From Slave
P
B0B1B2XXXXX
Stop Condition
Slave Address Control Register
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Programming (continued)
Figure 11. Write Control Register
Data is read from the TCA9544A control register using the read mode shown in Figure 12.
Figure 12. Read Control Register
8.6 Control Register
8.6.1 Device Address
Following a start condition, the bus master must output the address of the slave it is accessing. The address of
the TCA9544A is shown in Figure 13. To conserve power, no internal pullup resistors are incorporated on the
hardware-selectable address pins, and they must be pulled high or low.
Figure 13. TCA9544A Address
The last bit of the slave address defines the operation to be performed. When set to a logic 1, a read is selected,
while a logic 0 selects a write operation.
l TEXAS INSTRUMENTS
Interrupt Bits
(Read Only)
Channel-Selection Bits
(Read/Write)
Enable Bit
INT3 INT2 INT1 INT0 B2 B1 B0
7 6 54 3 2 1 0
X
INT1
INT3
INT2
INT0
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Control Register (continued)
(1) Only one channel may be selected at a time.
8.6.2 Control Register Description
Following the successful acknowledgment of the slave address, the bus master sends a byte to the TCA9544A,
which is stored in the control register. If multiple bytes are received by the TCA9544A, it saves the last byte
received. This register can be written and read via the I2C bus.
Figure 14. Control Register
8.6.3 Control Register Definition
Only one SCn/SDn downstream pair, or channel, can be selected by the contents of the control register (see
Table 1). This register is written after the TCA9544A has been addressed. The three LSBs of the control byte are
used to determine which channel (or channels) is to be selected. When a channel is selected, the channel
becomes active after a stop condition has been placed on the I2C bus. This ensures that all SCn/SDn lines are in
a high state when the channel is made active, so that no false conditions are generated at the time of
connection. A stop condition always must occur right after the acknowledge cycle.
Table 1. Control Register Write (Channel Selection), Control Register Read (Channel Status)(1)
INT3 INT2 INT1 INT0 D3 B2 B1 B0 COMMAND
X X X X X 0 X X No channel selected
X X X X X 1 0 0 Channel 0 enabled
X X X X X 1 0 1 Channel 1 enabled
X X X X X 1 1 0 Channel 2 enabled
X X X X X 1 1 1 Channel 3 enabled
00000000No channel selected,
power-up default state
l TEXAS INSTRUMENTS
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(1) Several interrupts can be active at the same time. For example, INT3 = 0, INT2 = 1, INT1 = 1, INT0 = 0 means that there is no interrupt
on channels 0 and 3, and there is interrupt on channels 1 and 2.
8.6.4 Interrupt Handling
The TCA9544A provides four interrupt inputs (one for each channel) and one open-drain interrupt output. When
an interrupt is generated by any device, it is detected by the TCA9544A, and the interrupt output is driven low.
The channel does not need to be active for detection of the interrupt. A bit also is set in the control register (see
Table 2).
Bits 4–7 of the control register correspond to channels 0–3 of the TCA9544A, respectively. Therefore, if an
interrupt is generated by any device connected to channel 1, the state of the interrupt inputs is loaded into the
control register when a read is accomplished. Likewise, an interrupt on any device connected to channel 0
causes bit 4 of the control register to be set on the read. The master then can address the TCA9544A and read
the contents of the control register to determine which channel contains the device generating the interrupt. The
master can reconfigure the TCA9544A to select this channel and locate the device generating the interrupt and
clear it. Once the device responsible for the interrupt clears, the interrupt clears.
It should be noted that more than one device can provide an interrupt on a channel, so it is up to the master to
ensure that all devices on a channel are interrogated for an interrupt.
The interrupt inputs can be used as general-purpose inputs if the interrupt function is not required.
If unused, interrupt input(s) must be connected to VCC.
Table 2. Control Register Read (Interrupt)(1)
INT3 INT2 INT1 INT0 D3 B2 B1 B0 COMMAND
XXX0XXXXNo interrupt on channel 0
1 Interrupt on channel 0
X X 0XXXXXNo interrupt on channel 1
1 Interrupt on channel 1
X0XXXXXXNo interrupt on channel 2
1 Interrupt on channel 2
0XXXXXXXNo interrupt on channel 3
1 Interrupt on channel 3
MENTS it"
TCA9544A
SD1
SDA Channel 0
Channel 1
Channel 2
Channel 3
I2C/SMBus
Master SCL
INT
INT1
SC1
SD2
SC2
SD3
SC3
INT2
INT3
SD0
INT0
SC0
V = 1.65 V to 5.5 V
DPUM VCC = 2.5 V
V = 1.65 V to 5.5 V
DPU0
V = 1.65 V to 5.5 V
DPU1
V = 1.65 V to 5.5 V
DPU2
V = 1.65 V to 5.5 V
DPU3
SDA
SCL
GND
A0
A1
A2
5
6
4
8
9
7
12
13
11
15
16
14
19
18
17
2
3
1
10
20
VCC
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9 Application and Implementation
NOTE
Information in the following applications sections is not part of the TI component
specification, and TI does not warrant its accuracy or completeness. TI’s customers are
responsible for determining suitability of components for their purposes. Customers should
validate and test their design implementation to confirm system functionality.
9.1 Application Information
Applications of the TCA9544A will contain an I2C (or SMBus) master device and up to four I2C slave devices.
The downstream channels are ideally used to resolve I2C slave address conflicts. For example, if four identical
digital temperature sensors are needed in the application, one sensor can be connected at each channel: 0, 1, 2,
and 3. When the temperature at a specific location needs to be read, the appropriate channel can be enabled
and all other channels switched off, the data can be retrieved, and the I2C master can move on and read the next
channel.
In an application where the I2C bus will contain many additional slave devices that do not result in I2C slave
address conflicts, these slave devices can be connected to any desired channel to distribute the total bus
capacitance across multiple channels. If multiple switches will be enabled simultaneously, additional design
requirements must be considered (See Design Requirements and Detailed Design Procedure).
9.2 Typical Application
A typical application of the TCA9544A contains anywhere from 1 to 5 separate data pull-up voltages, VDPUX , one
for the master device (VDPUM) and one for each of the selectable slave channels (VDPU0 – VDPU3). In the event
where the master device and all slave devices operate at the same voltage, then the supply voltage can be VCC
= VDPUX. In an application where voltage translation is necessary, additional design requirements must be
considered (See Design Requirements).
Figure 15 shows an application in which the TCA9544A can be used.
Figure 15. Typical Application Schematic
TEXAS INSTRUMENTS R V”
r
p(max)
b
t
R0.8473 C
=
´
DPUX OL(max)
p(min)
OL
V V
RI
-
=
17
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Typical Application (continued)
9.2.1 Design Requirements
The pull-up resistors on the INT3-INT0 pins in the application schematic are not required in all applications. If the
device generating the interrupt has an open-drain output structure or can be tri-stated, a pull-up resistor is
required. If the device generating the interrupt has a push-pull output structure and cannot be tri-stated, a pull-up
resistor is not required. The interrupt inputs should not be left floating in the application.
The A0 and A1 pins are hardware selectable to control the slave address of the TCA9544A. These pins may be
tied directly to GND or VCC in the application.
If multiple slave channels will be activated simultaneously in the application, then the total IOL from SCL/SDA to
GND on the master side will be the sum of the currents through all pull-up resistors, Rp.
The pass-gate transistors of the TCA9544A are constructed such that the VCC voltage can be used to limit the
maximum voltage that is passed from one I2C bus to another.
Figure 16 shows the voltage characteristics of the pass-gate transistors (note that the graph was generated using
data specified in the Electrical Characteristics section of this data sheet). In order for the TCA9544A to act as a
voltage translator, the Vpass voltage must be equal to or lower than the lowest bus voltage. For example, if the
main bus is running at 5 V and the downstream buses are 3.3 V and 2.7 V, Vpass must be equal to or below 2.7 V
to effectively clamp the downstream bus voltages. As shown in Figure 16, Vpass(max) is 2.7 V when the TCA9544A
supply voltage is 4 V or lower, so the TCA9544A supply voltage could be set to 3.3 V. Pull-up resistors then can
be used to bring the bus voltages to their appropriate levels (see Figure 15).
9.2.2 Detailed Design Procedure
Once all the slaves are assigned to the appropriate slave channels and bus voltages are identified, the pull-up
resistors, Rp, for each of the buses need to be selected appropriately. The minimum pull-up resistance is a
function of VDPUX, VOL,(max), and IOL:
(1)
The maximum pull-up resistance is a function of the maximum rise time, tr(300 ns for fast-mode operation, fSCL =
400 kHz) and bus capacitance, Cb:
(2)
The maximum bus capacitance for an I2C bus must not exceed 400 pF for fast-mode operation. The bus
capacitance can be approximated by adding the capacitance of the TCA9544A, Cio(OFF), the capacitance of
wires/connections/traces, and the capacitance of each individual slave on a given channel. If multiple channels
will be activated simultaneously, each of the slaves on all channels will contribute to total bus capacitance.
l TEXAS INSTRUMENTS
VDPUX (V)
Rp(min) (kOhm)
0 0.5 1 1.5 2 2.5 3 3.5 4 4.5 5 5.5
0
0.2
0.4
0.6
0.8
1
1.2
1.4
1.6
1.8
D009
VDPUX > 2V
VDPUX <= 2
VCC (V)
Vpass (V)
0 0.5 1 1.5 2 2.5 3 3.5 4 4.5 5 5.5
0
1
2
3
4
5
D007
25ºC (Room Temperature)
85ºC
-40ºC
Cb (pF)
Rp(max) (kOhm)
0 50 100 150 200 250 300 350 400 450
0
5
10
15
20
25
D008
Standard-mode
Fast-mode
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Typical Application (continued)
9.2.3 TCA9544A Application Curves
Space
spacespace
Space
spacespace
Figure 16. Pass-Gate Voltage (Vpass) vs Supply Voltage
(VCC) at Three Temperature Points
Standard-mode
(fSCL= 100 kHz, tr= 1 µs) Fast-mode
(fSCL= 400 kHz, tr= 300 ns)
Figure 17. Maximum Pull-up resistance (Rp(max)) vs Bus
Capacitance (Cb)
VOL = 0.2*VDPUX, IOL = 2 mA when VDPUX ≤2 V
VOL = 0.4 V, IOL = 3 mA when VDPUX > 2 V
Figure 18. Minimum Pull-up Resistance (Rp(min)) vs Pull-up Reference Voltage (VDPUX)
b TEXAS INSTRUMENTS
VCC
Ramp-Up
Time to Re-Ramp
Time
Ramp-Down
VCC drops below V 50 mV
PORF –
VCC_RT
VCC_FT
VCC_TRR
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(1) All supply sequencing and ramp rate values are measured at TA= 25°C
10 Power Supply Recommendations
The operating power-supply voltage range of the TCA9544A is 1.65 V to 5.5 V applied at the VCC pin. When the
TCA9544A is powered on for the first time or anytime the device needs to be reset by cycling the power supply,
the power-on reset requirements must be followed to ensure the I2C bus logic is initialized properly.
10.1 Power-On Reset Requirements
In the event of a glitch or data corruption, TCA9544A can be reset to its default conditions by using the power-on
reset feature. Power-on reset requires that the device go through a power cycle to be completely reset. This
reset also happens when the device is powered on for the first time in an application.
A power-on reset is shown in Figure 19.
Figure 19. VCC is Lowered Below the POR Threshold, Then Ramped Back Up to VCC
Table 3 specifies the performance of the power-on reset feature for TCA9544A for both types of power-on reset.
Table 3. Recommended Supply Sequencing And Ramp Rates(1)
PARAMETER MIN TYP MAX UNIT
VCC_FT Fall time See Figure 19 1 ms
VCC_RT Rise time See Figure 19 0.1 ms
VCC_TRR Time to re-ramp (when VCC drops below VPORF(min) – 50 mV or
when VCC drops to GND) See Figure 19 40 μs
VCC_GH Level that VCC can glitch down to, but not cause a functional
disruption when VCC_GW = 1 μsSee Figure 20 1.2 V
VCC_GW Glitch width that will not cause a functional disruption when
VCC_GH = 0.5 × VCC See Figure 20 10 μs
VPORF Voltage trip point of POR on falling VCC See Figure 21 0.8 1.25 V
VPORR Voltage trip point of POR on rising VCC See Figure 21 1.05 1.5 V
‘5‘ TEXAS INSTRUMENTS
VCC
VPORR
VPORF
Time
POR
Time
VCC
Time
VCC_GH
VCC_GW
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Glitches in the power supply can also affect the power-on reset performance of this device. The glitch width
(VCC_GW) and height (VCC_GH) are dependent on each other. The bypass capacitance, source impedance, and
device impedance are factors that affect power-on reset performance. Figure 20 and Table 3 provide more
information on how to measure these specifications.
Figure 20. Glitch Width and Glitch Height
VPOR is critical to the power-on reset. VPOR is the voltage level at which the reset condition is released and all the
registers and the I2C/SMBus state machine are initialized to their default states. The value of VPOR differs based
on the VCC being lowered to or from 0. Figure 21 and Table 3 provide more details on this specification.
Figure 21. VPOR
l TEXAS INSTRUMENTS LEGEND
A0
A1
A2
INT0
SD0
SC0
INT1
SD1
SC1
GND
VCC
SDA
SCL
INT
SC3
SD3
INT3
SC2
SD2
INT2
VDPU1
VDPU0
VIA to Power Plane
Partial Power Plane
VDPU3
VDPUM
VIA to GND Plane (Inner Layer)
Polygonal
Copper Pour
VCC
GND
Bypass/Decoupling
Capacitors
TCA9544A
GND
VDPU2
To I2C Master
To Slave Channel 3 To Slave Channel 2
To Slave Channel 1 To Slave Channel 1
LEGEND
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11 Layout
11.1 Layout Guidelines
For PCB layout of the TCA9544A, common PCB layout practices should be followed but additional concerns
related to high-speed data transfer such as matched impedances and differential pairs are not a concern for I2C
signal speeds. It is common to have a dedicated ground plane on an inner layer of the board and pins that are
connected to ground should have a low-impedance path to the ground plane in the form of wide polygon pours
and multiple vias. By-pass and de-coupling capacitors are commonly used to control the voltage on the VCC pin,
using a larger capacitor to provide additional power in the event of a short power supply glitch and a smaller
capacitor to filter out high-frequency ripple.
In an application where voltage translation is not required, all VDPUX voltages and VCC could be at the same
potential and a single copper plane could connect all of pull-up resistors to the appropriate reference voltage. In
an application where voltage translation is required, VDPUM, VDPU0, VDPU1, VDPU2, and VDPU3 may all be on the
same layer of the board with split planes to isolate different voltage potentials.
To reduce the total I2C bus capacitance added by PCB parasitics, data lines (SCn, SDn and INTn) should be a
short as possible and the widths of the traces should also be minimized (e.g. 5-10 mils depending on copper
weight).
11.2 Layout Example
l TEXAS INSTRUMENTS
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12 Device and Documentation Support
12.1 Receiving Notification of Documentation Updates
To receive notification of documentation updates, navigate to the device product folder on ti.com. In the upper
right corner, click on Alert me to register and receive a weekly digest of any product information that has
changed. For change details, review the revision history included in any revised document.
12.2 Support Resources
TI E2E™ support forums are an engineer's go-to source for fast, verified answers and design help — straight
from the experts. Search existing answers or ask your own question to get the quick design help you need.
Linked content is provided "AS IS" by the respective contributors. They do not constitute TI specifications and do
not necessarily reflect TI's views; see TI's Terms of Use.
12.3 Trademarks
E2E is a trademark of Texas Instruments.
All other trademarks are the property of their respective owners.
12.4 Electrostatic Discharge Caution
These devices have limited built-in ESD protection. The leads should be shorted together or the device placed in conductive foam
during storage or handling to prevent electrostatic damage to the MOS gates.
12.5 Glossary
SLYZ022 —TI Glossary.
This glossary lists and explains terms, acronyms, and definitions.
13 Mechanical, Packaging, and Orderable Information
The following pages include mechanical, packaging, and orderable information. This information is the most
current data available for the designated devices. This data is subject to change without notice and revision of
this document. For browser-based versions of this data sheet, refer to the left-hand navigation.
I TEXAS INSTRUMENTS Samples
PACKAGE OPTION ADDENDUM
www.ti.com 10-Dec-2020
Addendum-Page 1
PACKAGING INFORMATION
Orderable Device Status
(1)
Package Type Package
Drawing Pins Package
Qty Eco Plan
(2)
Lead finish/
Ball material
(6)
MSL Peak Temp
(3)
Op Temp (°C) Device Marking
(4/5)
Samples
TCA9544APWR ACTIVE TSSOP PW 20 2000 RoHS & Green NIPDAU Level-1-260C-UNLIM -40 to 85 PW544A
(1) The marketing status values are defined as follows:
ACTIVE: Product device recommended for new designs.
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design.
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.
OBSOLETE: TI has discontinued the production of the device.
(2) RoHS: TI defines "RoHS" to mean semiconductor products that are compliant with the current EU RoHS requirements for all 10 RoHS substances, including the requirement that RoHS substance
do not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, "RoHS" products are suitable for use in specified lead-free processes. TI may
reference these types of products as "Pb-Free".
RoHS Exempt: TI defines "RoHS Exempt" to mean products that contain lead but are compliant with EU RoHS pursuant to a specific EU RoHS exemption.
Green: TI defines "Green" to mean the content of Chlorine (Cl) and Bromine (Br) based flame retardants meet JS709B low halogen requirements of <=1000ppm threshold. Antimony trioxide based
flame retardants must also meet the <=1000ppm threshold requirement.
(3) MSL, Peak Temp. - The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature.
(4) There may be additional marking, which relates to the logo, the lot trace code information, or the environmental category on the device.
(5) Multiple Device Markings will be inside parentheses. Only one Device Marking contained in parentheses and separated by a "~" will appear on a device. If a line is indented then it is a continuation
of the previous line and the two combined represent the entire Device Marking for that device.
(6) Lead finish/Ball material - Orderable Devices may have multiple material finish options. Finish options are separated by a vertical ruled line. Lead finish/Ball material values may wrap to two
lines if the finish value exceeds the maximum column width.
Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information
provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and
continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals.
TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited information may not be available for release.
In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI to Customer on an annual basis.
I TEXAS INSTRUMENTS ‘3‘ V.'
PACKAGE MATERIALS INFORMATION
www.ti.com 3-Jun-2022
TAPE AND REEL INFORMATION
Reel Width (W1)
REEL DIMENSIONS
A0
B0
K0
W
Dimension designed to accommodate the component length
Dimension designed to accommodate the component thickness
Overall width of the carrier tape
Pitch between successive cavity centers
Dimension designed to accommodate the component width
TAPE DIMENSIONS
K0 P1
B0 W
A0
Cavity
QUADRANT ASSIGNMENTS FOR PIN 1 ORIENTATION IN TAPE
Pocket Quadrants
Sprocket Holes
Q1 Q1Q2 Q2
Q3 Q3Q4 Q4 User Direction of Feed
P1
Reel
Diameter
*All dimensions are nominal
Device Package
Type Package
Drawing Pins SPQ Reel
Diameter
(mm)
Reel
Width
W1 (mm)
A0
(mm) B0
(mm) K0
(mm) P1
(mm) W
(mm) Pin1
Quadrant
TCA9544APWR TSSOP PW 20 2000 330.0 16.4 6.95 7.0 1.4 8.0 16.0 Q1
Pack Materials-Page 1
PACKAGE MATERIALS INFORMATION
www.ti.com 3-Jun-2022
TAPE AND REEL BOX DIMENSIONS
Width (mm)
W
L
H
*All dimensions are nominal
Device Package Type Package Drawing Pins SPQ Length (mm) Width (mm) Height (mm)
TCA9544APWR TSSOP PW 20 2000 356.0 356.0 35.0
Pack Materials-Page 2
--I L J f T , g T Q f fl g
www.ti.com
PACKAGE OUTLINE
C
18X 0.65
2X
5.85
20X 0.30
0.19
TYP
6.6
6.2
1.2 MAX
0.15
0.05
0.25
GAGE PLANE
-80
B
NOTE 4
4.5
4.3
A
NOTE 3
6.6
6.4
0.75
0.50
(0.15) TYP
TSSOP - 1.2 mm max heightPW0020A
SMALL OUTLINE PACKAGE
4220206/A 02/2017
1
10 11
20
0.1 C A B
PIN 1 INDEX AREA
SEE DETAIL A
0.1 C
NOTES:
1. All linear dimensions are in millimeters. Any dimensions in parenthesis are for reference only. Dimensioning and tolerancing
per ASME Y14.5M.
2. This drawing is subject to change without notice.
3. This dimension does not include mold flash, protrusions, or gate burrs. Mold flash, protrusions, or gate burrs shall not
exceed 0.15 mm per side.
4. This dimension does not include interlead flash. Interlead flash shall not exceed 0.25 mm per side.
5. Reference JEDEC registration MO-153.
SEATING
PLANE
A 20
DETAIL A
TYPICAL
SCALE 2.500
““‘w‘+‘w““‘
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EXAMPLE BOARD LAYOUT
0.05 MAX
ALL AROUND 0.05 MIN
ALL AROUND
20X (1.5)
20X (0.45)
18X (0.65)
(5.8)
(R0.05) TYP
TSSOP - 1.2 mm max heightPW0020A
SMALL OUTLINE PACKAGE
4220206/A 02/2017
NOTES: (continued)
6. Publication IPC-7351 may have alternate designs.
7. Solder mask tolerances between and around signal pads can vary based on board fabrication site.
LAND PATTERN EXAMPLE
EXPOSED METAL SHOWN
SCALE: 10X
SYMM
SYMM
1
10 11
20
15.000
METAL
SOLDER MASK
OPENING METAL UNDER
SOLDER MASK SOLDER MASK
OPENING
EXPOSED METAL
EXPOSED METAL
SOLDER MASK DETAILS
NON-SOLDER MASK
DEFINED
(PREFERRED)
SOLDER MASK
DEFINED
gmgmmj r Egg;
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EXAMPLE STENCIL DESIGN
20X (1.5)
20X (0.45)
18X (0.65)
(5.8)
(R0.05) TYP
TSSOP - 1.2 mm max heightPW0020A
SMALL OUTLINE PACKAGE
4220206/A 02/2017
NOTES: (continued)
8. Laser cutting apertures with trapezoidal walls and rounded corners may offer better paste release. IPC-7525 may have alternate
design recommendations.
9. Board assembly site may have different recommendations for stencil design.
SOLDER PASTE EXAMPLE
BASED ON 0.125 mm THICK STENCIL
SCALE: 10X
SYMM
SYMM
1
10 11
20
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