Datenblatt für 74HC(T)4075-Q100 von Nexperia USA Inc.

Table 1. Ordering information nexpefla
74HC4075-Q100;
74HCT4075-Q100
Triple 3-input OR gate
Rev. 2 — 4 February 2019 Product data sheet
1. General description
The 74HC4075-Q100; 74HCT4075-Q100 is a triple 3-input OR gate. Inputs include clamp diodes.
This enables the use of current limiting resistors to interface inputs to voltages in excess of VCC.
This product has been qualified to the Automotive Electronics Council (AEC) standard Q100
(Grade 1) and is suitable for use in automotive applications.
2. Features and benefits
Automotive product qualification in accordance with AEC-Q100 (Grade 1)
Specified from -40 °C to +85 °C and from -40 °C to +125 °C
Complies with JEDEC standard JESD7A
Input levels:
For 74HC4075-Q100: CMOS level
For 74HCT4075-Q100: TTL level
ESD protection:
MIL-STD-883, method 3015 exceeds 2000 V
HBM JESD22-A114F exceeds 2000 V
MM JESD22-A115-A exceeds 200 V (C = 200 pF, R = 0 Ω)
3. Ordering information
Table 1. Ordering information
PackageType number
Temperature range Name Description Version
74HC4075D-Q100
74HCT4075D-Q100
-40 °C to +125 °C SO14 plastic small outline package; 14 leads;
body width 3.9 mm
SOT108-1
74HC4075PW-Q100 -40 °C to +125 °C TSSOP14 plastic thin shrink small outline package; 14 leads;
body width 4.4 mm
SOT402-1
Nexperia 74HC4075-Q100; 74HCT4075-Q100 H 12 ass-024793 11 12 m Ens-024794 ass-024795 74HC4075-Q100 o o UUFTWFTUU UHLJULJUU ass-007523 74HC4075-0100 flflflflflflfl O n o UUUUUUU “3007624 Table 2. Pin description
Nexperia 74HC4075-Q100; 74HCT4075-Q100
Triple 3-input OR gate
4. Functional diagram
aaa-024793
2A
2B 2Y
2
1
9
2C
8
3A
3B 3Y
12
11
10
3C
13
1A
1B 1Y
4
3
6
1C
5
Fig. 1. Logic symbol
aaa-024794
6
≥1
4
3
≥1
≥1
9
2
1
1012
11
5
8
13
Fig. 2. IEC logic symbol
aaa-024795
A
C
BY
Fig. 3. Logic diagram (one gate)
5. Pinning information
5.1. Pinning
aaa-007623
2A
2B
1A
1B
1C
1Y
GND
VCC
3C
3B
3A
3Y
2Y
2C
74HC4075-Q100
74HCT4075-Q100
1
2
3
4
5
6
7 8
10
9
12
11
14
13
Fig. 4. Pin configuration SOT108-1 (SO14)
aaa-007624
2A
2B
1A
1B
1C
1Y
GND
VCC
3C
3B
3A
3Y
2Y
2C
1
2
3
4
5
6
78
10
9
12
11
14
13
74HC4075-Q100
Fig. 5. Pin configuration SOT402-1 (TSSOP14)
5.2. Pin description
Table 2. Pin description
Symbol Pin Description
1A, 2A, 3A 3, 1, 11 data input
1B, 2B, 3B 4, 2, 12 data input
1C, 2C, 3C 5, 8, 13 data input
1Y, 2Y, 3Y 6, 9, 10 data output
GND 7 ground (0 V)
VCC 14 supply voltage
74HC_HCT4075_Q100 All information provided in this document is subject to legal disclaimers. © Nexperia B.V. 2019. All rights reserved
Product data sheet Rev. 2 — 4 February 2019 2 / 12
Nexperia 74HC4075-Q100; 74HCT4075-Q100
Nexperia 74HC4075-Q100; 74HCT4075-Q100
Triple 3-input OR gate
6. Functional description
Table 3. Function table
H = HIGH voltage level; L = LOW voltage level; X = don’t care.
Inputs Outputs
nA nB nC nY
LLLL
X X H H
X H X H
H X X H
7. Limiting values
Table 4. Limiting values
In accordance with the Absolute Maximum Rating System (IEC 60134). Voltages are referenced to GND (ground = 0 V).
Symbol Parameter Conditions Min Max Unit
VCC supply voltage -0.5 +7 V
IIK input clamping current VI < -0.5 V or VI > VCC + 0.5 V [1] - ±20 mA
IOK output clamping current VO < -0.5 V or VO > VCC + 0.5 V [1] - ±20 mA
IOoutput current -0.5 V < VO < VCC + 0.5 V - ±25 mA
ICC supply current - 50 mA
IGND ground current -50 - mA
Tstg storage temperature -65 +150 °C
Ptot total power dissipation [2] - 500 mW
[1] The input and output voltage ratings may be exceeded if the input and output current ratings are observed.
[2] For SO14 package: Ptot derates linearly with 8 mW/K above 70 °C.
For TSSOP14 packages: Ptot derates linearly with 5.5 mW/K above 60 °C.
8. Recommended operating conditions
Table 5. Recommended operating conditions
Voltages are referenced to GND (ground = 0 V)
74HC4075-Q100 74HCT4075-Q100Symbol Parameter Conditions
Min Typ Max Min Typ Max
Unit
VCC supply voltage 2.0 5.0 6.0 4.5 5.0 5.5 V
VIinput voltage 0 - VCC 0 - VCC V
VOoutput voltage 0 - VCC 0 - VCC V
Tamb ambient temperature -40 +25 +125 -40 +25 +125 °C
VCC = 2.0 V - - 625 - - - ns/V
VCC = 4.5 V - 1.67 139 - 1.67 139 ns/V
Δt/ΔV input transition rise and fall rate
VCC = 6.0 V - - 83 - - - ns/V
74HC_HCT4075_Q100 All information provided in this document is subject to legal disclaimers. © Nexperia B.V. 2019. All rights reserved
Product data sheet Rev. 2 — 4 February 2019 3 / 12
Nexperia 74HC4075-Q100; 74HCT4075-Q100
Nexperia 74HC4075-Q100; 74HCT4075-Q100
Triple 3-input OR gate
9. Static characteristics
Table 6. Static characteristics
At recommended operating conditions; voltages are referenced to GND (ground = 0 V).
25 °C -40 °C to
+85 °C
-40 °C to
+125 °C
Symbol Parameter Conditions
Min Typ Max Min Max Min Max
Unit
74HC4075-Q100
VCC = 2.0 V 1.5 1.2 - 1.5 - 1.5 - V
VCC = 4.5 V 3.15 2.4 - 3.15 - 3.15 - V
VIH HIGH-level
input voltage
VCC = 6.0 V 4.2 3.2 - 4.2 - 4.2 - V
VCC = 2.0 V - 0.8 0.5 - 0.5 - 0.5 V
VCC = 4.5 V - 2.1 1.35 - 1.35 - 1.35 V
VIL LOW-level input
voltage
VCC = 6.0 V - 2.8 1.8 - 1.8 - 1.8 V
VI = VIH or VIL
IO = -20 μA; VCC = 2.0 V 1.9 2.0 - 1.9 - 1.9 - V
IO = -20 μA; VCC = 4.5 V 4.4 4.5 - 4.4 - 4.4 - V
IO = -20 μA; VCC = 6.0 V 5.9 6.0 - 5.9 - 5.9 - V
IO = -4.0 mA; VCC = 4.5 V 3.98 4.32 - 3.84 - 3.7 - V
VOH HIGH-level
output voltage
IO = -5.2 mA; VCC = 6.0 V 5.48 5.81 - 5.34 - 5.2 - V
VI = VIH or VIL
IO = 20 μA; VCC = 2.0 V - 0 0.1 - 0.1 - 0.1 V
IO = 20 μA; VCC = 4.5 V - 0 0.1 - 0.1 - 0.1 V
IO = 20 μA; VCC = 6.0 V - 0 0.1 - 0.1 - 0.1 V
IO = 4.0 mA; VCC = 4.5 V - 0.15 0.26 - 0.33 - 0.4 V
VOL LOW-level
output voltage
IO = 5.2 mA; VCC = 6.0 V - 0.16 0.26 - 0.33 - 0.4 V
IIinput leakage
current
VI = VCC or GND; VCC = 6.0 V - - ±0.1 - ±1.0 - ±1.0 μA
ICC supply current VI = VCC or GND; IO = 0 A;
VCC = 6.0 V
- - 2.0 - 20 - 40 μA
CIinput
capacitance
- 3.5 - - - - - pF
74HCT4075-Q100
VIH HIGH-level
input voltage
VCC = 4.5 V to 5.5 V 2.0 1.6 - 2.0 - 2.0 - V
VIL LOW-level input
voltage
VCC = 4.5 V to 5.5 V - 1.2 0.8 - 0.8 - 0.8 V
VI = VIH or VIL; VCC = 4.5 V
IO = -20 μA 4.4 4.5 - 4.4 - 4.4 - V
VOH HIGH-level
output voltage
IO = -4.0 mA 3.98 4.32 - 3.84 - 3.7 - V
VI = VIH or VIL; VCC = 4.5 V
IO = 20 μA - 0 0.1 - 0.1 - 0.1 V
VOL LOW-level
output voltage
IO = 4.0 mA - 0.15 0.26 - 0.33 - 0.4 V
IIinput leakage
current
VI = VCC or GND; VCC = 5.5 V - - ±0.1 - ±1.0 - ±1.0 μA
ICC supply current VI = VCC or GND; VCC = 5.5 V;
IO = 0 A
- - 2.0 - 20 - 40 μA
74HC_HCT4075_Q100 All information provided in this document is subject to legal disclaimers. © Nexperia B.V. 2019. All rights reserved
Product data sheet Rev. 2 — 4 February 2019 4 / 12
Nexperia 74HC4075-Q100; 74HCT4075-Q100 as Fig. 7
Nexperia 74HC4075-Q100; 74HCT4075-Q100
Triple 3-input OR gate
25 °C -40 °C to
+85 °C
-40 °C to
+125 °C
Symbol Parameter Conditions
Min Typ Max Min Max Min Max
Unit
per input pin; VI = VCC - 2.1 V;
other inputs at VCC or GND;
VCC = 4.5 V to 5.5 V; IO = 0 A
ΔICC additional
supply current
nA, nB, nC inputs - 150 540 - 675 - 735 μA
CIinput
capacitance
- 3.5 - - - - - pF
10. Dynamic characteristics
Table 7. Dynamic characteristics
Voltages are referenced to GND (ground = 0 V); CL = 50 pF unless otherwise specified; for test circuit see Fig. 7.
25 °C -40 °C to +125 °CSymbol Parameter Conditions
Min Typ Max Min Max
(85 °C)
Max
(125 °C)
Unit
74HC4075-Q100
nA, nB, nC to nY; see Fig. 6 [1]
VCC = 2.0 V - 28 100 - 125 150 ns
VCC = 4.5 V - 10 20 - 25 30 ns
VCC = 5.0 V; CL = 15 pF - 8 - - - - ns
tpd propagation
delay
VCC = 6.0 V - 8 17 - 21 26 ns
see Fig. 6 [2]
VCC = 2.0 V - 19 75 - 95 110 ns
VCC = 4.5 V - 7 15 - 19 22 ns
tttransition time
VCC = 6.0 V - 6 13 - 16 19 ns
CPD power
dissipation
capacitance
per package; VI = GND to VCC [3] - 28 - - - - pF
74HCT4075-Q100
nA, nB, nC to nY; see Fig. 6 [1]
VCC = 4.5 V - 12 24 - 30 36 ns
tpd propagation
delay
VCC = 5.0 V; CL = 15 pF - 10 - - - - ns
tttransition time VCC = 4.5 V; see Fig. 6 [2] - 7 15 - 19 22 ns
CPD power
dissipation
capacitance
per package;
VI = GND to VCC - 1.5 V
[3] - 32 - - - - pF
[1] tpd is the same as tPHL and tPLH.
[2] tt is the same as tTHL and tTLH.
[3] CPD is used to determine the dynamic power dissipation (PD in μW):
PD = CPD × VCC
2 × fi × N + ∑ (CL × VCC
2 × fo) where:
fi = input frequency in MHz;
fo = output frequency in MHz;
CL = output load capacitance in pF;
VCC = supply voltage in V;
N = number of inputs switching;
∑ (CL × VCC
2 × fo) = sum of outputs.
74HC_HCT4075_Q100 All information provided in this document is subject to legal disclaimers. © Nexperia B.V. 2019. All rights reserved
Product data sheet Rev. 2 — 4 February 2019 5 / 12
Nexperia 74HC4075-Q100; 74HCT4075-Q100 5334724798 Table 3 Table 8. Measurement points
Nexperia 74HC4075-Q100; 74HCT4075-Q100
Triple 3-input OR gate
10.1. Waveforms and test circuit
aaa-024798
nA, nB, nC input
VI
GND
VOH
VOL
nY output
tTHL tTLH
VM
VM
VX
VY
tPHL tPLH
Measurement points are given in Table 8.
VOL and VOH are typical voltage output levels that occur with the output load.
Fig. 6. Input (nA, nB, nC) to output (nY) propagation delays and output transition times
Table 8. Measurement points
Input OutputType
VMVMVXVY
74HC4075-Q100 0.5VCC 0.5VCC 0.1VCC 0.9VCC
74HCT4075-Q100 1.3 V 1.3 V 0.1VCC 0.9VCC
74HC_HCT4075_Q100 All information provided in this document is subject to legal disclaimers. © Nexperia B.V. 2019. All rights reserved
Product data sheet Rev. 2 — 4 February 2019 6 / 12
Nexperia 74HC4075-Q100; 74HCT4075-Q100 gamma Table 9. Test data
Nexperia 74HC4075-Q100; 74HCT4075-Q100
Triple 3-input OR gate
VMVM
tW
tW
10 %
90 %
0 V
VI
VI
negative
pulse
positive
pulse
0 V
VMVM
90 %
10 %
tf
tr
tr
tf
001aad983
DUT
VCC VCC
VIVO
RT
RLS1
CL
open
G
Test data is given in Table 9.
Definitions test circuit:
RT = Termination resistance should be equal to output impedance Zo of the pulse generator.
CL = Load capacitance including jig and probe capacitance.
RL = Load resistance.
S1 = Test selection switch
Fig. 7. Test circuit for measuring switching times
Table 9. Test data
Input Load S1 positionType
VItr, tfCLRLtPHL, tPLH
74HC4075-Q100 VCC 6 ns 15 pF, 50 pF 1 kΩ open
74HCT4075-Q100 3 V 6 ns 15 pF, 50 pF 1 kΩ open
74HC_HCT4075_Q100 All information provided in this document is subject to legal disclaimers. © Nexperia B.V. 2019. All rights reserved
Product data sheet Rev. 2 — 4 February 2019 7 / 12
Nexperia 74HC4075-Q100; 74HCT4075-Q100 SO14: plastic small outline package; 14 leads; body width 3.9 mm SOT108-1 .-
Nexperia 74HC4075-Q100; 74HCT4075-Q100
Triple 3-input OR gate
11. Package outline
Fig. 8. Package outline SOT108-1 (SO14)
74HC_HCT4075_Q100 All information provided in this document is subject to legal disclaimers. © Nexperia B.V. 2019. All rights reserved
Product data sheet Rev. 2 — 4 February 2019 8 / 12
Nexperia 74HC4075-Q100; 74HCT4075-Q100 TSSOP14: plastic lhin shrink small outline package; 14 leads; body width 44 mm SOT402-1 W, l H\\/H:‘ m ;::f ; l ; II ‘ L7 \‘ '// an]. 7‘4 l ‘ HHHHH H l 7 l l l ‘ fifi l ‘ H A , l l; "l l O l l + + + N H HH H H H “L” *D * Er© 9“” “
Nexperia 74HC4075-Q100; 74HCT4075-Q100
Triple 3-input OR gate
UNIT A
1 A
2 A
3 b
p c D
(1) E (2) (1)
e H
E L L
p Q Z y w v θ
REFERENCES
OUTLINE
VERSION
EUROPEAN
PROJECTION ISSUE DATE
IEC JEDEC JEITA
mm 0.15
0.05
0.95
0.80
0.30
0.19
0.2
0.1
5.1
4.9
4.5
4.3 0.65 6.6
6.2
0.4
0.3
0.72
0.38
8
0
o
o
0.13 0.1 0.2 1
DIMENSIONS (mm are the original dimensions)
Notes
1. Plastic or metal protrusions of 0.15 mm maximum per side are not included.
2. Plastic interlead protrusions of 0.25 mm maximum per side are not included.
0.75
0.50
SOT402-1 MO-153 99-12-27
03-02-18
w M
b
p
D
Z
e
0.25
1 7
14 8
θ
A
A
1
A
2
L
p
Q
detail X
L
(A )
3
H
E
E
c
v M A
X
A
y
0 2.5 5 mm
scale
TSSOP14: plastic thin shrink small outline package; 14 leads; body width 4.4 mm SOT402-1
A
max.
1.1
pin 1 index
Fig. 9. Package outline SOT402-1 (TSSOP14)
74HC_HCT4075_Q100 All information provided in this document is subject to legal disclaimers. © Nexperia B.V. 2019. All rights reserved
Product data sheet Rev. 2 — 4 February 2019 9 / 12
Nexperia 74HC4075-Q100; 74HCT4075-Q100 Table 10. Abbreviations Table 11. Revision history 0100; a Table 6
Nexperia 74HC4075-Q100; 74HCT4075-Q100
Triple 3-input OR gate
12. Abbreviations
Table 10. Abbreviations
Acronym Description
CMOS Complementary Metal-Oxide Semiconductor
DUT Device Under Test
ESD ElectroStatic Discharge
HBM Human Body Model
MIL Military
MM Machine Model
TTL Transistor-Transistor Logic
13. Revision history
Table 11. Revision history
Document ID Release date Data sheet status Change notice Supersedes
74HC_HCT4075_Q100 v.2 20190204 Product data sheet - 74HC_HCT4075_Q100 v.1
Modifications: The format of this data sheet has been redesigned to comply with the identity guidelines
of Nexperia.
Legal texts have been adapted to the new company name where appropriate.
Type number 74HCT4075PW-Q100 (SOT402-1) removed.
74HCT4075-Q100; added value for VOL at IO = 4 mA (inline with Non-Automotive
version), see Table 6.
74HC_HCT4075_Q100 v.1 20130522 Product data sheet - -
74HC_HCT4075_Q100 All information provided in this document is subject to legal disclaimers. © Nexperia B.V. 2019. All rights reserved
Product data sheet Rev. 2 — 4 February 2019 10 / 12
Nexperia same In a deswgn on new sheaf .s exp‘amed in status of demoem described e «we neeumem was publish es. The latest produd slam hugs waw nexge mm 74HC4075-Q100; 74HCT4075-Q100 oundilions at commercial sale 7 Max m me genera‘ ierms and mnd ans of m llwww nex er
Nexperia 74HC4075-Q100; 74HCT4075-Q100
Triple 3-input OR gate
14. Legal information
Data sheet status
Document status
[1][2]
Product
status [3]
Definition
Objective [short]
data sheet
Development This document contains data from
the objective specification for
product development.
Preliminary [short]
data sheet
Qualification This document contains data from
the preliminary specification.
Product [short]
data sheet
Production This document contains the product
specification.
[1] Please consult the most recently issued document before initiating or
completing a design.
[2] The term 'short data sheet' is explained in section "Definitions".
[3] The product status of device(s) described in this document may have
changed since this document was published and may differ in case of
multiple devices. The latest product status information is available on
the internet at https://www.nexperia.com.
Definitions
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detailed and full information. For detailed and full information see the relevant
full data sheet, which is available on request via the local Nexperia sales
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data sheet shall define the specification of the product as agreed between
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has been qualified for use in automotive applications. Unless otherwise
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Limiting values — Stress above one or more limiting values (as defined in
the Absolute Maximum Ratings System of IEC 60134) will cause permanent
damage to the device. Limiting values are stress ratings only and (proper)
operation of the device at these or any other conditions above those
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Trademarks
Notice: All referenced brands, product names, service names and
trademarks are the property of their respective owners.
74HC_HCT4075_Q100 All information provided in this document is subject to legal disclaimers. © Nexperia B.V. 2019. All rights reserved
Product data sheet Rev. 2 — 4 February 2019 11 / 12
Nexperia 74HC4075-Q100; 74HCT4075-Q100
Nexperia 74HC4075-Q100; 74HCT4075-Q100
Triple 3-input OR gate
Contents
1. General description......................................................1
2. Features and benefits.................................................. 1
3. Ordering information....................................................1
4. Functional diagram.......................................................2
5. Pinning information......................................................2
5.1. Pinning.........................................................................2
5.2. Pin description............................................................. 2
6. Functional description................................................. 3
7. Limiting values............................................................. 3
8. Recommended operating conditions..........................3
9. Static characteristics....................................................4
10. Dynamic characteristics............................................ 5
10.1. Waveforms and test circuit........................................ 6
11. Package outline.......................................................... 8
12. Abbreviations............................................................ 10
13. Revision history........................................................10
14. Legal information......................................................11
© Nexperia B.V. 2019. All rights reserved
For more information, please visit: http://www.nexperia.com
For sales office addresses, please send an email to: salesaddresses@nexperia.com
Date of release: 4 February 2019
74HC_HCT4075_Q100 All information provided in this document is subject to legal disclaimers. © Nexperia B.V. 2019. All rights reserved
Product data sheet Rev. 2 — 4 February 2019 12 / 12