Datenblatt für IR3891 von Infineon Technologies

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Dual output, 4A/Phase, Highly Integrated SupIRBuck®

Single-Input Voltage, Synchronous Buck Regulator IR3891

FEATURES

• Single 5V to 21V application

• Wide Input Voltage Range from 1V to 21V with

external Vcc

• Output Voltage Range: 0.5V to 0.86*PVin

• Dual output, 4A/Phase

• Enhanced Line/Load Regulation with Feed-

Forward

• Programmable Switching Frequency up to 1.5MHz

• Internal Digital Soft-Start

• Enable input with Voltage Monitoring Capability

• Thermally compensated current limit and Hiccup

Mode Over Current Protection

• External synchronization with Smooth Clocking

• Precision Reference Voltage (0.5V +/-1%)

• Seq pin for Sequencing Applications

• Integrated MOSFETs, drivers and Bootstrap diode

• Thermal Shut Down

• Open Feedback Line Protection

• Over Voltage Protection

• Interleaved Phases to reduce Input Capacitors

• Monotonic Start-Up

• Operating Junction Temp: -40oC<Tj<125oC

• Small Size 5mm x 6mm PQFN

• Lead-free, Halogen-free, and RoHS Compliant

DESCRIPTION

The IR3891 SupIRBuck® is an easy-to-use, fully

integrated and highly efficient DC/DC regulator. The

onboard PWM controller and MOSFETs make IR3891

a space-efficient solution, providing accurate power

delivery for low output voltage.

IR3891 is a versatile regulator which offers

programmability of switching frequency and a fixed

current limit while operating in wide input and output

voltage range.

The switching frequency is programmable from

300kHz to 1.5MHz for an optimum solution.

It also features important protection functions, such as

Over Voltage Protection (OVP), Pre-Bias startup,

hiccup current limit and thermal shutdown to give

required system level security in the event of fault

conditions.

APPLICATIONS

• Sever Applications

• Netcom Applications

• Set Top Box Applications

• Storage Applications

• Embedded telecom Systems

• Distributed Point of Load Power Architectures

• Computing Peripheral Voltage regulators

• General DC-DC Converters

ORDERING INFORMATION

Base Part

Number

Package Type

Standard Pack

Orderable Part

Number

Form

Quantity

IR3891

PQFN 5mm x 6mm

Tape and Reel

4000

IR3891MTRPBF

IR3891

PBF

TR

M

Lead Free

Tape and Reel

Package Type

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IR3891

BASIC APPLICATION

Boot1

Vcc

Fb1

Comp1

Gnd PGnd1/2

SW1

Vo1

PG1

Seq Vin

PG2

Fb2

Comp2

Vo

2

Rt/

Sync

Boot2

SW2

Vsns2 Vsns1

PVin1/2

EN1

EN2

5V < Vin < 21V

Figure 1: IR3891 Basic Application Circuit

73

75

77

79

81

83

85

87

89

91

93

0.5 11.5 22.5 33.5 4

Efficiency [%]

Load Current[A]

1.2V 1.8V

Figure 2: Efficiency [Vin=12V, Fsw=600kHz]

PIN DIAGRAM

5mm X 6mm POWER QFN

Top View

25PGnd1

1 2 3 4 5 6 7 8 9

13

12

11

10

17

16

15

14

18

Boot2

PGood2

Comp2

FB2

PGnd2

PVin2

PGnd2

Vsns2

EN2

RT/Sync

Seq

GND

VCC/LDO_out

Vin

EN1

Vsns1

19

SW2

20

21

SW1

22

24PGnd1

23PGnd1

28Boot1

27

PVin1

26PVin1

31FB1

30Comp1

29PGood1

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IR3891

FUNCTIONAL BLOCK DIAGRAM

GATE

DRIVE

LOGIC

Gnd

Comp

Seq*

fb

EN

VREF

E/A

Intl_SS

FB

FAULT

CONTROL

LOGIC

Rff

Vin

SOFT

START SSOK

FAULT

POR

VREF

+

-

PGood

Rt/Sync

Vsns

UVEN UVEN

POR POR

UVLO

VREF UV/

OV/OLFP

FB UV/

OV/OLFP

HDin

LDin

OC OVER CURRENT

PROTECTION

THERMAL

SHUTDOWN

POR

TSD

OV/OFLP

OC

+

-

VLDO_REF

+

-LDO

VCC

LDrv

HDrv

FAULT

CONTROL

FAULT

PGnd

SW

PVin

Boot

Vin VCC/LDO_out

UVLO UVLO

+

-

VCC

*The Seq pin is only available for channel 2

Figure 3: IR3891 Simplified Block Diagram (one phase)

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IR3891

PIN DESCRIPTIONS

PIN # PIN NAME PIN DESCRIPTION

1, 9 Vsns 1/2

Sense pins for over-voltage protection and PGood. A resistor divider

with the same ratio as the respective feedback resistor divider should be

connected between each Vsns pin and its respective Vout.

2, 8 EN 1/2

Enable pins for turning on and off the regulator.

3 Vin

Input voltage for Internal LDO. A 1.0µF capacitor should be connected

between this pin and PGnd. If external supply is connected to VCC pin,

this pin should be shorted to VCC pin.

4 VCC/LDO_out

Input Bias Voltage, output of the internal LDO. Place a minimum 2.2µF

cap from this pin to PGnd.

5 GND Signal ground for internal reference and control circuitry.

6 Seq

Input to error amplifier for sequencing purposes. Can be left floating for

non-sequencing applications. It is only connected to the Error-Amplifier

of channel 2.

7 Rt/Sync

Multi-function pin to set switching frequency. Use an external resistor

from this pin to Gnd to set the free-running switching frequency. Or use

an external clock signal to connect to this pin through a diode, the

device’s switching frequency is synchronized with the external clock.

10, 31 FB 2/1

Inverting inputs to the error amplifiers. These pins are connected directly

to the outputs of the regulator via resistor dividers to set the output

voltages and provide feedback to the error amplifiers.

11, 30 Comp 2/1

Output of the error amplifiers. External resistor and capacitor networks

are typically connected from these pins to its respective Fb pin to provide

loop compensation.

12, 29 PGood 2/1

Power Good status pins are open drain outputs. The pins are typically

connected to VCC via pull up resistors.

13, 28 Boot 2/1

Supply voltages for high side drivers, 100nF capacitors should be

connected between these pins and their respective SW pin.

14, 15, 26,

27 PVin 2/1 Input voltage for power stage.

16, 17, 18,

23, 24, 25 PGnd 2/1

Power Ground. These pins serve as a separated ground for the

MOSFET drivers and should be connected to the system’s power ground

plane.

19, 20, 21,

22 SW 2/1 Switch nodes. These pins are connected to the output inductors.

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IR3891

ABSOLUTE MAXIMUM RATINGS

Stresses beyond those listed under “Absolute Maximum Ratings” may cause permanent damage to the device. These are

stress ratings only and functional operation of the device at these or any other conditions beyond those indicated in the

operational sections of the specifications are not implied.

PVin

-0.3V to 25V

Vin

-0.3V to 25V

VCC

-0.3V to 8V (Note 1)

SW

-0.3V to 25V (DC), -4V to 25V (AC, 100ns)

BOOT

-0.3V to 33V

BOOT to SW

-0.3V to VCC + 0.3V (Note 2)

EN, PGood

-0.3V to VCC + 0.3V (Note 2)

Other Input/Output pins

-0.3V to 3.9V

PGnd to GND

-0.3V to + 0.3V

Junction Temperature Range

-40°C to 150°C

Storage Temperature Range

-55°C to 150°C

ESD

Machine Model

Class A

Human Body Model

Class 1C

Charged Device Model

Class III

Moisture Sensitivity level

JEDEC Level 2 @ 260°C

RoHS Compliant

Yes

Note:

1. VCC must not exceed 7.5V for Junction Temperature between -10°C and -40°C.

2. Must not exceed 8V.

THERMAL INFORMATION

Thermal Resistance, Junction to Case Top (θJC_TOP) 36 °C/W

Thermal Resistance, Junction to PCB (θJB)

3.6 °C/W

Thermal Resistance, Junction to Ambient (θ

JA

) (Note 3) 24.7 °C/W

Note:

3. Thermal resistance (θJA) is measured with components mounted on a high effective thermal conductivity

test board in free air.

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IR3891

ELECTRICAL SPECIFICATIONS

RECOMMENDED OPERATING CONDITIONS

SYMBOL

DEFINITION

MIN

MAX

UNIT

PVin

Input Bus Voltage *

1.0

21

V

Vin

Supply Voltage

5.0

21

VCC

Supply Voltage **

4.5

7.5

Boot to SW

Supply Voltage

4.5

7.5

VO

Output Voltage

0.5

0.86 * PVin

IO

Output Current

0

4

A / Phase

Fs

Switching Frequency

300

1500

kHz

TJ

Junction Temperature

-40

125

°C

* SW1/2 node must not exceed 25V

** When VCC is connected to an externally regulated supply, also connect Vin.

ELECTRICAL CHARACTERISTICS

Unless otherwise specified, these specifications apply over, 6.8V < Vin=PVin < 21V in 0°C < TJ < 125°C.

Typical values are specified at Ta = 25°C.

PARAMETER SYMBOL CONDITIONS MIN TYP MAX UNIT

Power Stage

Power Losses PLOSS

Vin

= 12V, Vout

1

= 1.8V,

Vout2 = 1.2V, IO =

4A/phase, Fs = 600kHz,

L1 =2.2uH, L2=1.5uH,

Note 4

1.38 W

Top Switch Rds(on)_Top

VBoot - Vsw= 5.3V, I

O

=

4A, Tj = 25°C

27.5 36.4

mΩ

Bottom Switch Rds(on)_Bot

Vcc = 5.3V, I

O

= 4A, Tj =

25°C

19.5 24.2

Bootstrap Diode

Forward Voltage

I(Boot) = 10mA 300 450 mV

SW Leakage Current ISW SW = 0V, Enable = 0V 1 µA

SW = 0V, Enable = high,

VSeq = 0V

2 µA

Dead Band Time

Tdb

Note 4

10

20

30

ns

Supply Current

VIN Supply Current

(standby) Iin(Standby) EN = Low, No Switching 100 175 µA

VIN Supply Current

(dynamic) Iin(Dyn) EN = High, Fs = 600kHz,

12.0 17 mA

VCC LDO Output

Output Voltage Vcc Vin(min) = 6.8V, Io = 0-

60mA, Cload = 2.2uF 5 5.3 5.6 V

VCC Dropout Vcc_drop Icc = 60mA, Cload =

2.2uF 0.75 V

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IR3891

PARAMETER SYMBOL CONDITIONS MIN TYP MAX UNIT

Short Circuit Current Ishort 120 mA

Oscillator

Rt Voltage Vrt 1.0 V

Frequency Range Fs

Rt = 80.6K 270 300 330

kHz Rt = 39.2K 540 600 660

Rt = 15K 1350 1500 1650

Ramp Amplitude Vramp

Vin = 6.8V, Vin slew rate

max = 1V/μs, Note 4 1.02

Vp-p

Vin = 12V, Vin slew rate

max = 1V/μs, Note 4 1.80

Vin = 21V, Vin slew rate

max = 1V/μs, Note 4 3.15

Vcc=Vin = 5V, For

external Vcc operation,

Note 4

0.75

Min Pulse Width Tmin(ctrl) Note 4 60 ns

Max Duty Cycle Dmax Fs = 300kHz,

Vin=Pvin=12V 86 %

Fixed Off Time Toff Note 4 200 250 ns

Sync Frequency Range Fsync 270 1650 kHz

Sync Pulse Duration Tsync 100 200 ns

Sync Level Threshold High 3 V

Low 0.6

Error Amplifier

Seq Input Offset

Voltage Vos_VSeq VSeq – Vfb;

VSeq=250mV -3 +3 %

Input Bias Current IFb(E/A) -200 +200 nA

Seq Input impedance Rin_Seq(E/A) Internal Seq pull-up

resistor 300 kΩ

Sink Current Isink(E/A) 0.4 0.85 1.2 mA

Source Current Isource(E/A) 3 4 7 mA

Slew Rate SR Note 4 7 12 20 V/µs

Gain-Bandwidth

Product GBWP Note 4 20 30 40 MHz

DC Gain Gain Note 4 80 90 110 dB

Maximum Voltage Vmax(E/A) 1.7 2 2.3 V

Minimum Voltage Vmin(E/A) 120 220 mV

Vseq Common Mode

Voltage 0 0.77 V

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IR3891

PARAMETER SYMBOL CONDITIONS MIN TYP MAX UNIT

Reference Voltage

Feedback Voltage Vfb VSeq=3.3V 0.5 V

Accuracy

0°C < Tj < 85°C -1 +1

%

-40°C < Tj < 125°C,

Note 5 -1.5 +1.5

Soft Start

Soft Start Ramp Rate Ramp (SS_start) 0.14 0.18 0.22 mV /

µs

Fault Protection

Current Limit ICC Vcc=5.3V, Tj = 25°C 4.8 6.0 7.2

A /

Phase

Hiccup blanking time

Tblk_Hiccup

Note 4

20.48

ms

OFLP Trip Threshold

OFLP(threshold)

Fb Falling

65

70

75

%Vref

OFLP Fault Prop Delay

OFLP(delay)

0.1

0.3

0.5

µs

OVP Trip Threshold

OVP(threshold)

Vsns Rising

115

120

125

%Vref

OVP Trip Threshold

Hysteresis OVP_Hys

Vsns falling from above

120% of Vref, Sync_FET

turns off afterwards

25 mV

OVP Comparator Delay

OVP(delay)

2

µs

Thermal Shutdown

Note 4

140

°C

Thermal Hysteresis

Note 4

20

°C

VCC-Start-Threshold

VCC_UVLO_Start

VCC Rising Trip Level

4.0

4.2

4.4

V

VCC-Stop-Threshold

VCC_UVLO_Stop

VCC Falling Trip Level

3.7

3.9

4.1

Input / Output Signals

Enable-Start-Threshold

EN_UVLO_Start

Supply ramping up

1.14

1.2

1.26

V

Enable-Stop-Threshold

EN_UVLO_Stop

Supply ramping down

0.95

1

1.05

Enable leakage current

Ien

Enable=3.3V

3

4.5

µA

Power Good upper

Threshold

VPG(upper) Vsns Rising 80 85 90 %Vref

Power Good lower

Threshold

VPG(lower) Vsns Falling 75 80 85 %Vref

Lower Threshold Delay

VPG(lower)_Dly

Vsns Rising

1

1.3

1.6

ms

PGood Voltage Low

PG(voltage)

IPgood= -5mA

0.5

V

Note:

4. Guaranteed by design but not tested in production.

5. Cold temperature performance is guaranteed via correlation using statistical quality control. Not tested in

production.

I‘ZR Efﬁciency [‘56] 0.4 0.8 1.2 1.6 2.0 2.4 2.8 3.2 3.6 4.0 Load Current [A] —1.UV 1.2V —1.8V —3.3V —5.0V E 0.7 m 0.6 as _. Power 0.4 0.8 1.2 1 6 2.0 2.4 2.8 3.2 3.6 4.0 Load Current [A] —1.0V 1.2V —1.8V —3.3V —5.0V - www.\rl.com Submxl Dalasheel Feedback

IR3891

TYPICAL EFFICIENCY AND POWER LOSS CURVES

PVin = 12V, Vcc = Internal LDO, Io=0-4A, Fs= 600kHz, Room Temperature, No Air Flow. Note that the losses of

the inductor, input and output capacitors are also considered in the efficiency and power loss curves. The table

below shows the indicator used for each of the output voltages in the efficiency measurement while running a

single channel and disabling the other.

VOUT (V)

LOUT (uH)

P/N

DCR (mΩ)

1.0

1.5

7443340150 (Wurth Elektronik)

4.4

1.2

1.5

7443340150 (Wurth Elektronik)

4.4

1.8

2.2

7443340220 (Wurth Elektronik)

4.4

3.3

7443340330 (Wurth Elektronik)

6.5

5.0

3.3

7443340330 (Wurth Elektronik)

6.5

I‘ZR Efficiency [‘56] 0.4 0.6 0.8 1.0 1.2 14 1.6 1.8 2.0 2.2 2.4 2.6 2.8 3.0 3.2 3.4 36 3.8 4.0 Load Current [A] —1,0V 1,2V —1,8V —33V —E,DV Power Loss [W] 99.09.09.099 Hwammeo .0 z: 0.0 0.4 0.8 1.2 1.6 2.0 2.4 2.8 3.2 3.6 4.0 Load Current [A] —1,0V 1,2V —1,8V —33V —E,DV - www.\rl.com Submil Dalasheel Feedback

IR3891

TYPICAL EFFICIENCY AND POWER LOSS CURVES

PVin = 12V, Vin = Vcc = 5V, Io=0-4A, Fs= 600kHz, Room Temperature, No Air Flow. Note that the losses of the

inductor, input and output capacitors are also considered in the efficiency and power loss curves. The table

below shows the indicator used for each of the output voltages in the efficiency measurement while running a

single channel and disabling the other.

VOUT (V)

LOUT (uH)

P/N

DCR (mΩ)

1.0

1.5

PCMB065T-1R5MS (Cyntec)

6.7

1.2

1.5

PCMB065T-1R5MS (Cyntec)

6.7

1.8

2.2

7443340220 (Wurth Elektronik)

4.4

3.3

7443340330 (Wurth Elektronik)

6.5

5.0

3.3

7443340330 (Wurth Elektronik)

6.5

I‘ZR Efficiency [‘56] 0.4 0.8 1 2 1.6 2.0 2.4 2.8 3.2 3.6 4.0 Load Current [A] —1.0V 1.2V —1.8V —3.3V Power Loss [W] 0 4 0.8 1.2 1.6 2.0 2.4 2.8 3.2 3.6 4.0 Load Current [A] —10V 12V —18V —33V - www.\rl.com Submxl Dalasheel Feedback

IR3891

TYPICAL EFFICIENCY AND POWER LOSS CURVES

PVin = 5V, Vcc = 5V, Io=0-4A, Fs = 600kHz, Room Temperature, No Air Flow. Note that the losses of the

inductor, input and output capacitors are also considered in the efficiency and power loss curves. The table

below shows the indicator used for each of the output voltages in the efficiency measurement while running a

single channel and disabling the other.

VOUT (V)

LOUT (uH)

P/N

DCR (mΩ)

1.0

PCMB065T-1R0MS (Cyntec)

5.6

1.2

1.5

PCMB065T-1R5MS (Cyntec)

6.7

1.8

1.5

PCMB065T-1R5MS (Cyntec)

6.7

3.3

1.5

PCMB065T-1R5MS (Cyntec)

6.7

m - Channel 1 : Rds(on) at Vcc = 5.3V -4O -2O 0 20 40 60 80 100 120 140 Temperature [°C] —CtrI-FET —Sync-FET Channel 2: Rds(on) at Vcc=5.3V -40 -20 O 20 40 60 80 100 120 140 Temperature [°C] —Sync-FET —CtrI-FET - www.\rl.com Submit Dalasheel Feedback

IR3891

MOSFET RDSON VARIATION OVER TEMPERATURE

I‘ZR IIN (STANDBY) IIN(DYNAMIC) @ Fs=sookHz 170 13 0 150 12 5 — 13° , 12.0 < 110="" fr/="">< =="" e="" 11.5="" 90="" '="" 70="" 11.0="" 50="" 10.5="" 30="" 10.0="" ~40="" -20="" 0="" 20="" 40="" 60="" 80="" 100120140="" ~40="" ~20="" 0="" 20="" 40="" 60="" 80="" 100120140="" temperature="" ['c]="" temperarure="" [“c]="" frequency="" [rt="39.2kﬂl" vcc="" 620="" 5.5="" 615="" 610="" 5'5="" 605="" ’11'="" 5.4="" n="" g="" 600="" i=""> 5.3 595 5 2 590 585 5.1 580 50 ~40 -20 0 20 40 60 80 100120140 ~40 ~20 0 20 40 60 80 100120140 Temperature ['0] Temperature [“C] VCC7UVL075TART VCC,UVLO,STOF 4.40 4.10 4.35 4.05 4 30 4 00 4.25 3.95 > 4.20 > 3,90 7 W 4.15 3.85 4,10 3,80 4,05 3,75 4.00 1 3.70 ~40 ~20 0 20 40 60 80 100120140 ~40 ~20 0 20 40 60 80 100120140 Temperarure [“C] Temperarure [“C] SS,START1 SS,START2 0.24 0.24 0.23 0.23 0 22 0 22 0:] 0.21 0:] 0.21 5 0,20 5 0.20 E 0.19 E 0.19 0,10 \ ‘7 0,10 _ 0,17 ‘ 0,17 0.16 0.16 ~40 ~20 0 20 40 60 80 100120140 ~40 ~20 0 20 40 60 80 100120140 Tem peraluve ["C] Temperarure [“C] - www.mcom Submit Dalasheel Feedback

IR3891

TYPICAL OPERATING CHARACTERISTICS (-40°C TO +125°C)

I‘ZR EN_UVLD_START1 1.20 1 24 1.22 > 1,20 1 ,18 1,15 1,14 ~40 ~20 0 20 4O 60 80100120140 Temperamre [“C] EN,UVLO,STOP1 1 .05 1.03 101 0,99 0.97 0.95 ~40 ~20 0 20 4O 60 80100120140 Temperamre [“C] VPG (UPPERH 0.45 0.44 ‘ 0 43 ‘ > 0,42 T 0.41 ‘ 0.40 1 ~40 ~20 0 20 4O 60 80 100120 140 Temperamre [“C] VPG (LOWER) 1 0 .43 0.42 040 1 041 0.39 1 0.38 1 ~40 ~20 0 20 4O 60 80100120140 Tempera‘ure [“C] EN,UVLO,START2 1 .26 124 122 >120 1,18 1,15 1.14 ~40 ~20 0 20 4O 60 80100120140 Temperamre [“C] EN,UVLO,STOP2 1 .05 1.03 101 0,99 0.97 0.95 ~40 ~20 0 20 4O 60 80100120140 Temperamre [“C] VPG (UPPER)2 0.45 0 .44 D43 0,42 0.41 0.40 ~40 ~20 0 20 4O 60 80100120140 Temperamre [“C] VPG (LOWER) 2 0.43 0.42 U 41 0 40 0.39 0.38 ~40 ~20 0 20 4O 60 80100120140 Tempera‘ure [“C] - www.mcom Submit Dalasheel Feedback

IR3891

I‘ZR OVF7V1h1 0.625 0,620 0.615 0,610 0505 > 0.600 A 0 595 0 590 0.505 0.530 0.575 -40 -20 0 20 40 60 80100120140 Temperamre [°c1 VFB1 503 506 504 502 2500 m 493 496 494 492 40 -20 0 20 40 50 so 100120140 Temperature ['C] IOCP1 [vcc=5.a] 7.30 5,90 6.50 (6.10 f 5.70 5 30 4.90 ~40 -20 0 20 40 60 80100120140 Temperature [“C] OVFivch 0.625 0,620 0.615 0,610 0505 > 0.600 a 0 595 0 590 0.505 0.530 0.575 -40 -20 0 20 40 60 80100120140 Temperamre [°c1 VFBZ 503 506 504 502 2500 ,II—‘A 493 496 494 492 40 -20 0 20 40 50 so 100120140 Temperature ['6] loop: [vcc=5.av1 7.30 5,90 6.50 < 6.10="" \="" 5.70="" 5="" 30="" 4.90="" ~40="" -20="" 0="" 20="" 40="" 60="" 80100120140="" temperature="" [“c]="" -="" www.1rl.com="" submil="" dalasheel="" feedback="">

IR3891

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IR3891

THEORY OF OPERATION

DESCRIPTION

The IR3891 uses a PWM voltage mode control

scheme with external compensation to provide good

noise immunity and maximum flexibility in selecting

inductor values and capacitor types.

The switching frequency is programmable from

300KHz to 1.5MHz and provides the capability of

optimizing the design in terms of size and

performance.

IR3891 provides precisely regulated output voltage

programmed via two external resistors from 0.5V to

0.86*PVin.

The IR3891 operates with an internal low drop out

regulator (LDO) which is connected to the VCC pin.

This allows operation with a single supply. When

using the internal LDO supply, the Vin pin should be

connected the PVin pin. If an external bias is used, it

should be connected to the VCC pin and the Vin pin

should be shorted to the VCC pin.

The device utilizes the on-resistance of the low side

MOSFET (sync FET) as a current sense element.

This method enhances the converter’s efficiency and

reduces cost by eliminating the need for an external

current sense resistor.

IR3891 includes two low Rds(on) MOSFETs using

IR’s HEXFET technology. These are specifically

designed for high efficiency applications.

UNDER-VOLTAGE LOCKOUT AND POR

The under-voltage lockout circuits monitor the voltage

on the VCC pin and the EN1/2 pins. They ensure that

the MOSFET driver outputs remain in the off state

whenever either of these signals drops below the set

thresholds. Normal operation resumes once VCC and

EN rise above their thresholds.

The POR (Power On Ready) signal is high when all

these signals reach the valid logic level (see system

block diagram).

ENABLE

The EN pin offers another level of flexibility for startup.

Each channel of the IR3891 is controlled by a

separate EN pin. When the voltage at an EN pin

voltage exceeds its precise threshold

(EN_UVLO_START), the respective channel turns on.

The precise threshold allows the user to implement an

Under-Voltage Lockout (UVLO) function. By deriving

the EN pin voltage from the bus voltage (PVin)

through a suitable resistor divider, the user can set a

PVin threshold voltage. The resistor divider scales the

PVin voltage for the EN pin. Only after the bus

voltage reaches or exceeds this level will the voltage

at the Enable pin exceeds its threshold and enable the

respective IR3891 channel. By connecting IR3891 in

this configuration, the user can enable the part by

applying PVin and ensures the IR3891 does not turn

on until the bus voltage reaches the desired level

(Figure 4). Therefore, in addition to being a logic input

pin that enables channels on IR3891, the EN pin also

offers UVLO functionality. UVLO functionality is

particularly desirable for high output voltage

applications, where it is beneficial to disable the

IR3891 until PVin exceeds the desired output voltage

level.

Vcc

PVin

Intl_SS

EN

> 1.2V

1.2V

EN_UVLO_START

10.2V

12V

Figure 4: Normal Startup: IR3891 Channel starts when

PVin reaches 10.2V by connecting EN to PVin using a

resistor divider.

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IR3891

Vcc

PVin=Vin

Intl_SS 1/2

EN1/2 > 1.2V

Vo 1/2

Figure 5: Recommended startup for Normal operation

Vcc

PVin=Vin

Intl_SS 2

EN2

> 1.2V

Intl_SS 1

EN1

> 1.2V

Vo1

Vo2

Figure 6: Recommended startup for sequencing

operation (ratiometric or simultaneous)

Figure 5 shows the recommended start-up sequence

for the normal (non-sequencing) operation of IR3891,

when EN pins are used as a logic input. Figure 6

shows the recommended startup sequence for

sequenced operation of IR3891.

PRE-BIAS STARTUP

IR3891 begins each start up by pre-charging the

output to prevent oscillation and disturbances to the

output voltage. The buck converter starts in an

asynchronous fashion and keeps the synchronous

MOSFET (Sync FET) off until the first gate signal for

control MOSFET (Ctrl FET) is generated. Figure 7

shows a typical pre-bias sequence. The sync FET

always starts with a narrow pulse width (12.5% of the

switching period). The pulse width increase after 16

pulses by 12.5% until the output reaches steady state

value. There are 16 pulses for each step. Figure 8

shows the series of 16 x 8 startup pulses.

[V]

[Time]

Pre-Bias

Voltage

Vo

Figure 7: Pre-bias Start Up

... ... ...

HDRv

... ... ...

16 End of

PB

LDRv

12.5% 25% 87.5%

16

...

Figure 8: Pre-bias startup pulses

SOFT-START

IR3891 has an internal digital soft-start to control the

output voltage rise and to limit the current surge

during start-up. To ensure the correct start-up, the

soft-start sequence initiates when the EN and VCC

rise above their UVLO thresholds and generates

Power On Ready (POR) signal. The internal soft-start

rises with the typical rate of 0.2mV/µS from 0V to

1.5V. Figure 9 shows the waveforms during soft-start.

The normal Vout start-up time is fixed, and is equal to:

()

mS

SmV

VV

Tstart 5

.2

/

2.0

15.

065.0 =

−

=

µ

(1)

During the soft-start the over-current protection (OCP)

and the over-voltage protection (OVP) is enabled to

protect the device from short circuit or over voltage

events.

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IR3891

Vout

Intl_SS

POR

0.15V

t

1

t

2

0.65V

t

3

1.5V

3.0V

Figure 9: Theoretical operation waveforms during soft-

start (non-sequencing)

OPERATING FREQUENCY

The switching frequency can be programmed between

300KHz-1.5MHz by connecting an external resistor

from Rt/Sync pin to GND. Table 1 tabulates the

oscillator frequency versus Rt.

Table 1: Switching Frequency (Fs) vs. External

Resistor (Rt)

Rt (KΩ)

Freq

(KHz)

80.6

300

60.4

400

48.7

500

39.2

600

34

700

29.4

800

26.1

900

23.2

1000

21

1100

19.1

1200

17.4

1300

16.2

1400

15

1500

EXTERNAL SYNCHRONIZATION

IR3891 incorporates an internal phase lock loop (PLL)

circuit which enables synchronization of the internal

oscillator to an external clock. This function is

important to avoid sub-harmonic oscillations due to

beat frequency for embedded systems when multiple

point-of-load (POL) regulators are used. A multiple-

function pin, Rt/Sync, is used to connect the external

clock. If the external clock is present before the

converter turns on, Rt/Sync pin can be connected to

the external clock solely and no resistor is required. If

the external clock is applied after the converter turns

on, or the converter switching frequency needs to

toggle between the external clock frequency and the

internal free-running frequency, an external resistor

from Rt/Sync pin to GND is required to set the free

running frequency.

When an external clock is applied to Rt/Sync pin after

the converter runs in steady state with its free-running

frequency, a transition from the free-running frequency

to the external clock frequency will happen. The

switching frequency gradually synchronizes to the

external clock frequency regardless of which one is

faster. On the contrary, when the external clock signal

is removed from Rt/Sync pin, the switching frequency

gradually returns to the free-running frequency. In

order to minimize the impact from these transitions to

output voltage, a diode is recommended to add

between the external clock and Rt/Sync pin. Figure 10

shows the timing diagram of these transitions.

SW

SYNC

...

Gradually change

Fs1

Fs2

Fs1

Free Running

Frequency Synchronize to the

external clock Return to free-

running freq

Gradually change

Figure 10: Timing diagram for synchronization to an

external clock (Fs1>Fs2 or Fs1<Fs2)

An internal compensation circuit is used to change the

PWM ramp slope according to the clock frequency

applied on Rt/Sync pin. Thus, the effective amplitude

of the PWM ramp (Vramp), which is used in

compensation loop calculation, has minor impact from

the variation of the external synchronization signal.

Vin variation also affects the ramp amplitude, which is

discussed separately in Feed-Forward section.

SHUTDOWN

IR3891 shutdown occurs when VCC drops below its

threshold or a fault occurs. When VCC falls below

VCC_UVLO_STOP, the part detects an UVLO event

and the part turns off. Over-Voltage Protection, Over-

Current Protection and Thermal Shutdown also cause

the IR3891 shutdown. Faults are discussed in more

detail below.

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IR3891

Each channel of the IR3891 can be shutdown

separately by pulling the channel EN pin below its low

threshold. Each EN pin controls only one channel to

allow the user to operate each independently.

OVER CURRENT PROTECTION (CURRENT LIMIT

AND HICCUP MODE)

The over-current protection is performed by sensing

current through the RDS(on) of the Sync FET. This

method enhances the converter’s efficiency and

reduces cost by eliminating a current sense resistor.

The current limit is pre-set internally and compensated

to maintain an almost constant limit over temperature.

IR3891 determines over-current events when the

Synchronous FET is on. OCP circuit samples this

current for 40 nsec typically after the rising edge of the

PWM set pulse which has a width of 12.5% of the

switching period. The PWM pulse starts at the falling

edge of the PWM set pulse. This makes valley

current sense more robust as current is sensed close

to the bottom of the inductor downward slope where

transient and switching noise are lower and helps to

prevent false tripping due to noise and transient. An

OC condition is detected if the load current exceeds

the threshold, the converter enters into hiccup mode.

PGood will go low and the internal soft start signal will

be pulled low.

2

i

II

LIMITOCP

∆

+=

(2)

IOCP = DC current limit hiccup point

ILIMIT = Current Limit Valley Point

Δi = Inductor ripple current

Hiccup mode is when the converter stops and waits

before restarting. The channel waits for Tblk_Hiccup,

2.48 ms typical, before the OC signal resets and

restarts. In normal application, the converter restarts

with a pre-bias sequence and soft-start. Figure 11

shows the timing diagram of the above OC protection.

If another OC event is detected, the part repeats

hiccup mode.

0

IL

0

HDrv

Current Limit

0

LDrv

...

0

PGood

Hiccup

Tblk_Hiccup

20.48 mS*

*typical filter delay

Figure 11: Timing diagram for pulse-by-pulse current

limit and Hiccup mode

THERMAL SHUTDOWN

IR3891 provides thermal protection. A thermal fault is

detected, when the temperature of the part reaches

the Thermal Shutdown Threshold, 145°C typical. A

thermal fault results in both channels turning off. The

power MOSFETs are disabled during thermal

shutdown. IR3891 automatically restarts when the

temperature of the part drops back below the lower

thermal limit, typically 20°C below the Thermal

Shutdown Threshold.

FEED-FORWARD

Feed-Forward is an important feature which helps with

stability and preserves load transient performance

during PVin changes. In IR3891, Feed-Forward (F.F.)

function is enabled when Vin pin is connected to PVin

pin and Vin>5.0V. The PWM ramp amplitude (Vramp)

is proportionally changed with respect to Vin to

maintain PVin/Vramp ratio. The ratio is almost

constant throughout the Vin range (as shown in Figure

12). By maintaining a constant PVin/Vramp, the

control loop bandwidth and phase margin are more

constant. F.F. function also helps minimize the effect

of PVin changes on the output voltage.

Feed-Forward is based on the Vin voltage and needs

to be accounted for when calculating IR3891

compensation. The PVin/Vramp ratio is not

maintained when Vin and PVin are not equal. This is

the case when an external bias voltage for VCC.

When using an external VCC voltage, Vin pin should

be connected to the VCC pin instead of the PVin pin.

Compensation for the configuration should reflect the

separation.

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IR3891

0

Vin

PWM Ramp

12V

Ramp Offset

16V

6.8V

12V

PWM Ramp

Amplitude = 1.8V

PWM Ramp

Amplitude = 2.4V

PWM Ramp

Amplitude = 1.02V

Figure 12: Timing diagram for Feed Forward (F.F.)

Function

LOW DROPOUT REGULATOR (LDO)

IR3891 has an integrated low dropout (LDO) regulator

which can provide gate drive voltage for both drivers.

When using an internally biased configuration, the

LDO draws from the Vin pin and provides a 5.3V

(typ.), as shown in Figure 13. Vin and PVin can be

connected together as shown in the internally biased

single rail configuration, Figure 14.

An external bias configuration can provide gate drive

voltage for the drivers instead of the internal LDO. To

use an external bias, connected to Vin and VCC to the

external bias, as shown in Figure 15. PVin can also

be connected or a different rail can be used.

When using multiple rail configurations, calculate the

compensation Vramp associated with Vin. Vramp is

derived from Vin which can be different from PVin,

refer to Feed-Forward section.

IR3891

Vin PVin

PGND

Vin

VCC

PVin

Figure 13: Internally Biased Configuration

IR3891

Vin PVin

PGND

Vin

VCC

Figure 14: Internally Biased Single Rail Configuration

IR3891

Vin PVin

PGND

PVin

Ext VCC

VCC

Figure 15: Externally Biased Configuration

OUTPUT VOLTAGE SEQUENCING

IR3891 can accommodate user sequencing options

using Seq, EN1/2, and PGood1/2 pins. In the block

diagram presented on page 3, the error-amplifier (E/A)

has been depicted with three positive inputs. Ideally,

the input with the lowest voltage is used for regulating

the output voltage and the other two inputs are

ignored. In practice the voltages of the other two

inputs should be at least 200mV greater than the

referenced voltage input so that their effects can

completely be ignored.

In normal operating condition, the IR3891 channels

initially follow their internal soft-starts (Intl_SS) and

then references VREF. After Enable goes high,

Intl_SS begins to ramp up from 0V. The FB pin

follows the Intl_SS until it approaches VREF where

the E/A starts to reference the VREF instead of the

Intl_SS (refer to Figure 16). VREF and Seq are not

referenced initially because they are higher than

Intl_SS. VREF is 0.5V, typical. Seq is internally pulled

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IR3891

up to approximately 3.3V when left floating in normal

operation and only used by channel 2.

In sequencing mode of operation, Vout2 is initially

regulated with the Seq pin. Vout2 ramps up similar to

the normal operation, but Intl_SS is replaced with Seq.

Seq is kept to ground level until Intl_SS signal reaches

its final value. FB2 follows Seq, until Seq approaches

VREF where the E/A switches reference to the VREF.

Vout2 is then regulated with respect to internal VREF

(refer to Figure 17). The final Seq voltage should

between 0.7V and 3.3V.

FB/Vsns

1.3 mS*

PGood

OVP

Is Activated

0.65V

* typical filter delay

Intl_SS

VPG(Upper)

VPG(Lower)

OVP(Threshold) OVP(Hys)

1.3 mS*

LDrv

turned off

Figure 16: Timing Diagram for Output Sequence

Intl_SS

FB/Vsns

VPG(Lower)

Threshold

1.3 mS*

PGood

VPG(Upper)

Threshold

(>0.7V)

Seq

VREF

*typical filter delay

2uS*

OVP(Threshold)

Figure 17: Timing Diagram for Sequence Startup (Seq

ramping up/down)

IR3891 can perform simultaneous or ratiometric

sequencing operations. Simultaneous sequencing is

when the both outputs rise at the same rate. During

Ratiometric sequencing, the ratio of the two outputs is

held constant during power-up. Figure 19 shows

examples of the two sequencing modes.

IR3891 uses a single configuration to implement both

mode of sequencing operations. Figure 18 shows the

typical circuit configuration for both modes of

sequencing operation. The sequencing mode is

determined by the RA/RB, RE/RF, and RC/RD ratios. If

RE/RF = RC/RD, simultaneous startup is achieved.

Vout2 follows Vout1 until the voltage at the Seq pin

reaches VREF. After the voltage at the Seq pin

exceeds VREF, VREF dictates Vout2. In ratiometric

startup, Vout2 rises at a slower rate than Vout1. The

resistor values are set up in the following way, RA/RB >

RE/RF > RC/RD.

Table 2 summarizes the required conditions to

achieve simultaneous or ratiometric sequencing

operations.

Table 2: Required Conditions for Simultaneous /

Ratiometric Tracking and Sequencing

Operating Mode Seq

Required

Condition

Normal

(Non-sequencing,

Non-tracking)

Floating ―

Simultaneous

Sequencing

Ramp up

from 0V

R

A

/R

B

>R

E

/R

F

=R

C

/R

D

Ratiometric

Sequencing

Ramp up

from 0V

R

A

/R

B

>R

E

/R

F

>R

C

/R

D

PVin

Vin

Vcc/LDO_out

En1

En2

SW2

FB2

Comp2

Vsns2

PGood2

Boot2

R

C

R

D

Rt/Sync

R

A

SW1

Comp1

Vsns1

PGood1

Seq

R

B

R

E

R

F

Vo1 Vo2

Vo1

PGND1

PGND2

GND

Vin

FB1

Figure 18: Application Circuit for Simultaneous

and Ratiometric Sequencing

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IR3891

Vcc

Vo1 (master)

Vo2 (slave)

(a)

Vo1 (master)

Vo2 (slave)

(b)

Intl_SS2

EN1

EN2

Figure 19: Typical waveforms for sequencing mode of

operation: (a) simultaneous, (b) ratiometric

OVER-VOLTAGE PROTECTION (OVP)

Over-Voltage protection (OVP) disables the channel

when the output voltage exceeds the over-voltage

threshold. IR3891 achieves OVP by comparing Vsns

pin to the internal over-voltage threshold set at

OVP(threshold), 1.2*VREF typical. Vsns voltage is

determined by an external voltage divider resistor

network connected to the output in typical application.

When Vsns exceeds the over-voltage threshold, an

over-voltage is detected and OV signal asserts after

OVP(delay). The high side drive signal HDrv is turned

off immediately and PGood flags low. The low side

drive signal is kept on until the Vsns voltage drops

below the lower threshold. After that, HDrv is latched

off until a reset is performed by cycling either VCC or

the respective EN.

Vsns

HDrv

LDrv

PGood

OVP(Threshold) OVP(Hys)

2uS *

*typical filter delay

Figure 20: Timing diagram for OVP

OPEN FEEDBACK-LOOP PROTECTION

Open Feedback Loop protection (OFLP) is devised to

shutdown the channel in case the feedback is broken.

OFLP is activated when the Vsns is above the

VPG(upper) threshold, 0.85*VREF typical, and

remains active while Vsns is above the VPG(lower)

threshold, 0.80*VREF. When FB drop below

OFLP(threshold) threshold, 0.70*VREF, OFLP

disables switching and pulls down on PGood. The

part remains disabled until FB rises above

OFLP(threshold) plus OFLP(Hys), 0.75*VREF. This

function does not latch the part off nor does it require

an EN or a VCC toggle to re-enable the part.

Vsns

FB

PGood

VREF

VPG(Lower)

Threshold

OFLP Trip Threshold

Figure 21: Timing Diagram for Open Feedback Line

Protection (OFLP)

POWER GOOD OUTPUT

PGood is an open drain pin that monitors the UV,

FAULT and the POR signals. PGood signal asserts

approximately 1.3mS, after Vsns rises above

VGP(Upper) threshold, 0.85*VREF typical, while

FAULT is low and POR is high. It remains asserted

while FAULT is low and POR is high and Vsns stays

above VGP(Lower) threshold, 0.80*VREF typical.

When Vsns falls below VGP(Lower) threshold there is

a typical 2µS delay before PGood goes low. The two

PGood signals are independent of each other and are

set according to their respective channel.

SWITCH NODE PHASE SHIFT

The two converters on the IR3891 run interleaving

phases by 180° to reduce input filter requirements.

The two converters are synchronized to the user

programmable oscillator. Channel 1 runs in phase with

the oscillator while channel 2 runs out of phase.

Staggering the switching cycles reduces the time the

converters draw current from the supply

simultaneously. The pulses of current drawn from the

input induce voltage ripples across the input capacitor.

The voltage ripple shapes are dependent on the

different loading and output voltages of the two

converters. By switching the converters at different

times, the magnitude of voltage ripples reduces and

input filter requirements become less stringent.

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IR3891

MINIMUM ON-TIME CONSIDERATIONS

The minimum on-time is the shortest amount of time

which the Control FET may be reliably turned on.

Internal delays and gate drive make up a large portion

of the minimum on-time. IR3891 has a minimum on-

time of 60nS.

Any design or application using IR3891 should

operation with a pulse width greater than minimum on-

time. This is necessary for the circuit to operate

without jitter and pulse-skipping, which can cause high

inductor current ripple and high output voltage ripple.

s

out

s

on F

PVin

V

F

D

t×

=

(3)

In any application that uses IR3891, the following

condition must be satisfied:

onon tt ≤

(min)

(4)

sin

out

on

FPV

V

t×

≤

(min)

(5)

(min)on

out

sin

t

V

FPV ≤×∴

(6)

The minimum output voltage is limited by the

reference voltage and hence Vout(min) = 0.5V. For

Vout(min) = 0.5V,

(min)on

out

sin

t

V

FPV ≤×∴

(7)

SV

nS

V

FPV sin

µ

/33

.8

60

5.0 =

≤×∴

Therefore, with an input voltage 16V and minimum

output voltage, the converter should be designed for

switching frequency not to exceed 520kHz.

Conversely, the input voltage (PVin) should not

exceed 5.55V for operation at the maximum

recommended operating frequency (1.5MHz) and

minimum output voltage (0.5V). Increasing the PVin

greater than 5.55V will cause pulse skipping.

MAXIMUM DUTY RATIO

Maximum duty ratio is lower at higher frequencies and

higher Vin voltages. A maximum off-time of 250nS is

specified for IR3891. This provides an upper limit on

the operating duty ratio at any given switching

frequency. The off-time becomes a larger percentage

of the switching period when high switching

frequencies are used. Thus, a lower the maximum

duty ratio can be achieved when frequencies increase.

Feed-Forward from the Vin voltage placed a limitation

on the maximum duty cycle by saturating the

compensation ramp. By maintaining a constant

Vin/Vramp, the effective Vramp voltage is increased

while the maximum range is remains the same. The

ramp reaches the maximum limit before reaching the

expected level. Reaching the maximum limit ends the

switching cycle prematurely and results in a lower

maximum duty cycle.

Maximum duty cycle is dependent on the Vin and

switching frequency. Figure 22 is a theoretical plot of

the maximum duty cycle vs. the switching frequency

using typical parameter values. It shows how the

maximum duty cycle is influenced by the Vin and the

switching frequency.

Figure 22: Maximum Duty Cycle vs. Switching

Frequency

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IR3891

DESIGN EXAMPLE

The following example is a typical application for

IR3891. The application circuit is shown in

Vin = PVin = 12V (21V Max)

Fs = 600kHz

Channel 1:

Vo = 1.8V

Io = 4A

Ripple Voltage = ± 1% * Vo

ΔVo = ± 5% * Vo (for 50% load transient)

Channel 2:

Vo = 1.2V

Io = 4A

Ripple Voltage = ± 1% * Vo

ΔVo = ± 5% * Vo (for 50% load transient)

Enabling the IR3891

As explained earlier, the precise threshold of the

Enable lends itself well to implementation of a UVLO

for the Bus Voltage as shown in Figure 23.

R1

R2

Enable

IR3891

PVin

Figure 23: Using Enable pin for UVLO implementation

For a typical Enable threshold of VEN = 1.2 V

2.1

21

2

(min)

==

+

×

ENin

V

RR

R

PV

(8)

ENin

EN

VPV

V

RR −

=

(min)

12

(9)

For PVin (min)=9.2V, R1=49.9K and R2=7.5K ohm is a

good choice.

Programming the frequency

For Fs = 600 kHz, select Rt = 39.2 KΩ, using Table 1.

Output Voltage Programming

Output voltage is programmed by reference voltage

and external voltage divider. The FB pin is the

inverting input of the error amplifier, which is internally

referenced to VREF. The divider ratio is set to equal

VREF at the FB pin when the output is at its desired

value. When an external resistor divider is connected

to the output as shown in Figure 24, the output

voltage is defined by using the following equation:











+×=

6

5

1R

R

VV refo

(10)













−

×=

ref

o

ref

VV

V

RR 56

(11)

For the calculated values of R5 and R6, see feedback

compensation section.

R5

R6

FB

IR3891

Vout

Figure 24: Typical application of the IR3891

for programming the output voltage

Bootstrap Capacitor Selection

To drive the Control FET, it is necessary to supply a

gate voltage at least 4V greater than the voltage at the

SW pin, which is connected to the source of the

Control FET. This is achieved by using a bootstrap

configuration, which comprises the internal bootstrap

diode and an external bootstrap capacitor (C1). The

operation of the circuit is as follows: When the sync

FET is turned on, the capacitor node connected to SW

is pulled down to ground. The capacitor charges

towards Vcc through the internal bootstrap diode

(Figure 25), which has a forward voltage drop VD. The

voltage Vc across the bootstrap capacitor C1 is

approximately given as:

DcccVVV −≅

(12)

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IR3891

When the control FET turns on in the next cycle, the

capacitor node connected to SW rises to the bus

voltage Vin. However, if the value of C1 is

appropriately chosen, the voltage Vc across C1

remains approximately unchanged and the voltage at

the Boot pin becomes:

DccinBoot

VVVV −+≅

(13)

L

Vc

C1

V

IN

V

cc

SW

+

-

Boot

PGnd

+ V

D

-

IR3891

Cvin

Figure 25: Bootstrap circuit to generate Vc voltage

A bootstrap capacitor of value 0.1uF is suitable for

most applications.

Input Capacitor Selection

The ripple currents generated during the on time of

the control FETs should be provided by the input

capacitor. The RMS value of this ripple for each

channel is expressed by:

( )

DDII

oRMS

−××= 1

(14)

in

o

V

D=

(15)

Where:

D is the Duty Cycle

IRMS is the RMS value of the input capacitor

current.

Io is the output current.

For channel 1, Io=4A and D = 0.15, the IRMS =

1.43A.

For channel 2, Io=4A and D = 0.1, the IRMS = 1.2A.

Ceramic capacitors are recommended due to their

peak current capabilities. They also feature low ESR

and ESL at higher frequency which enables better

efficiency. For this application, it is advisable to have

4x10uF, 25V ceramic capacitors, C3216X5R1E106K

from TDK. In addition to these, although not

mandatory, a 1x330uF, 25V SMD capacitor EEV-

FK1E331P from Panasonic may also be used as a

bulk capacitor and is recommended if the input power

supply is not located close to the converter.

Inductor Selection

Inductors are selected based on output power,

operating frequency and efficiency requirements. A

low inductor value causes large ripple current,

resulting in the smaller size, faster response to a load

transient but may reduce efficiency and cause higher

output noise. Generally, the selection of the inductor

value can be reduced to the desired maximum ripple

current in the inductor (Δi). The optimum point is

usually found between 20% and 50% ripple of the

output current. For the buck converter, the inductor

value for the desired operating ripple current can be

determined using the following relation:

s

oin

F

D

t

i

LVV 1

;×=∆

∆

×=−

( )

sin

o

oin FiV

V

VVL ×∆×

×−=

(16)

Where:

Vin = Maximum input voltage

V0 = Output Voltage

Δi = Inductor Peak-to-Peak Ripple Current

Fs = Switching Frequency

Δt = On time for Control FET

D = Duty Cycle

If Δi ≈ 20%*Io, then the channel 1 output inductor is

calculated to be 3.2μH. Select L=2.2μH, PCMB065T-

2R2MS, from Cyntec which provides a compact, low

profile inductor suitable for this application. For

channel 2, the output inductor is calculated to be

2.25μH. Select L=1.5μH, PCMB065T-1R5MS, from

Cyntec.

Output Capacitor Selection

The voltage ripple and transient requirements

determine the output capacitors type and values. The

criterion is normally based on the value of the

IEZR AK, : AV“ +AV +AV em: - www.\rl.com Submxl Dalasheel Feedback

IR3891

Effective Series Resistance (ESR). However the

actual capacitance value and the Equivalent Series

Inductance (ESL) are other contributing components.

These components can be described as:

( ) ( )

)(CoESLoESRoo

VVVV ∆+∆+∆=∆

ESRI

VLESR ×∆

=∆ )

(0

ESL

L

VV

V

o

in

ESL

×











−

=

∆

)(

0

so

L

CFC

I

V××

∆

=∆ 8

)(0

(17)

Where:

ΔV0 = Output Voltage Ripple

ΔIL = Inductor Ripple Current

Since the output capacitor has a major role in the

overall performance of the converter and determines

the result of transient response, selection of the

capacitor is critical. The IR3891 can perform well with

all types of capacitors.

As a rule, the capacitor must have low enough ESR to

meet output ripple and load transient requirements.

The goal for this design is to meet the voltage ripple

requirement in the smallest possible capacitor size.

Therefore it is advisable to select ceramic capacitors

due to their low ESR and ESL and small size. Four of

TDK C2012X5R0J226M (22uF/0805/X5R/6.3V)

capacitors is a good choice for channel 1 and channel

2.

It is also recommended to use a 0.1µF ceramic

capacitor at the output for high frequency filtering.

Feedback Compensation

The IR3891 is a voltage mode controller. The control

loop is a single voltage feedback path including error

amplifier and error comparator. To achieve fast

transient response and accurate output regulation, a

compensation circuit is necessary. The goal of the

compensation network is to have a stable closed-loop

transfer function with a high crossover frequency and

phase margin greater than 45o.

The output LC filter introduces a double pole, -

40dB/decade gain slope above its corner resonant

frequency, and a total phase lag of 180o. The resonant

frequency of the LC filter is expressed as follows:

o

LC C

L

F×

×

=

π

2

1

(18)

Figure 26 shows gain and phase of the LC filter. Since

we already have 180o phase shift from the output filter

alone, the system runs the risk of being unstable.

Phase

0

F

LC

0

Frequency

F

LC

Frequency

0

-180

0

0dB

-40dB/Decade

-90

Gain

Figure 26: Gain and Phase of LC filter

The IR3891 uses a voltage-type error amplifier with

high-gain and high-bandwidth. The output of the

amplifier is available for DC gain control and AC

phase compensation.

The error amplifier can be compensated either in type

II or type III compensation.

Local feedback with Type II compensation is shown in

Figure 27.

This method requires that the output capacitor should

have enough ESR to satisfy stability requirements. If

the output capacitor’s ESR generates a zero at 5kHz

to 50kHz, the zero generates acceptable phase

margin and the Type II compensator can be used.

The ESR zero of the output capacitor is expressed as

follows:

o

ESR

CESR

F×××

=

π

2

1

(19)

I‘ER <7 submxl="" dalasheel="" feedback="" www.\rl.com="">

IR3891

VOUT

VREF

R6

R5

CPOLE

C3

R3

Ve

F

Z

F

POLE

E/A

Z

f

Frequency

Gain(dB)

H(s) dB

Fb

Comp

ZIN

Figure 27: Type II compensation network

and its asymptotic gain plot

The transfer function (Ve/Vout) is given by:

35

3

1

)( CsR

CsR

Z

sH

V

IN

f

out

e

+

−=−==

(20)

The (s) indicates that the transfer function varies as a

function of frequency. This configuration introduces a

gain and zero, expressed by:

5

3

)( R

R

sH =

(21)

33

2

1

CR

F

z

×××

=

π

(22)

First select the desired zero-crossover frequency (Fo):

ESRo FF >

and

so FF ×≤ )10/1~5/1(

(23)

Use the following equation to calculate R3:

2

5

3

LCin

ESRoramp

FV

RFFV

R×

×××

=

(24)

Where:

Vin = Maximum Input Voltage

Vramp = Amplitude of the oscillator Ramp Voltage

Fo = Crossover Frequency

FESR = Zero Frequency of the Output Capacitor

FLC = Resonant Frequency of the Output Filter

R5 = Feedback Resistor

To cancel one of the LC filter poles, place the zero

before the LC filter resonant frequency pole:

LCZ

FF ×= %75

oo

ZCL

F××

×=

π

2

1

75.0

(25)

Use equation (22), (23) and (24) to calculate C3.

One more capacitor is sometimes added in parallel

with C3 and R3. This introduces one more pole which

is mainly used to suppress the switching noise.

The additional pole is given by:

POLE

p

C

F

+

×

=

3

2

1

π

(26)

The pole sets to one half of the switching frequency

which results in the capacitor CPOLE:

S

POLE FR

C

FR

C××

≅

−××

=

3

1

π

(27)

For an unconditional stability general solution using

any type of output capacitors with a wide range of

ESR values, use local feedback with type III

compensation network. Type III compensation

network is typically used for voltage-mode controller

as shown in Figure 28.

IEZR Fs <7 submxl="" dalasheel="" feedback="" www.\rl.com="">

IR3891

V

OUT

V

REF

R6

R5

R4

C4

C2

C3

R3

Ve

F

Z

1

F

Z

2

F

P

2

F

P

3

E/A

Z

f

Z

IN

Frequency

Gain (dB)

|H(s)| dB

Fb

Comp

Figure 28: Type III Compensation network

and its asymptotic gain plot

Again, the transfer function is given by:

IN

f

out

e

Z

sH

V

V−== )

(

By replacing Zin and Zf, according to Figure 28, the

transfer function can be expressed as:

( ) ( )

[ ]

( ) ( )

44

32

3325

54433

11

)(

CsR

CC

sRCCsR

RRsCCsR

sH

+

























+

×

++

+++

−=

(28)

The compensation network has three poles and two

zeros and they are expressed as follows:

0

1

=

P

F

(29)

44

22

1

CR

FP××

=

π

(30)

23

32

3

32

1

2

1

CR

CC

R

FP××

≅













+

×

=

π

(31)

3

12

1

C

R

FZ×

×

=

π

(32)

( )

54544

2

1

2

1

RCRRC

F

Z

××

≅

×××

=

ππ

(33)

Cross over frequency is expressed as:

o

oramp

in

o

CL

V

C

RF ××

×

××

=

π

2

1

43

(34)

Based on the frequency of the zero generated by the

output capacitor and its ESR, relative to the crossover

frequency, the compensation type can be different.

Table 3 shows the compensation types for relative

locations of the crossover frequency.

Table 3: Different types of compensators

Compensator

Type

FESR vs FO

Typical Output

Capacitor

Type II

F

LC

< F

ESR

< F

O

<

FS/2

Electrolytic

Type III FLC < FO < FESR

SP Cap,

Ceramic

The higher the crossover frequency is, the potentially

faster the load transient response will be. However,

the crossover frequency should be low enough to

allow attenuation of switching noise. Typically, the

control loop bandwidth or crossover frequency (Fo) is

selected such that:

( )

so F F * 1/10~1/5≤

The DC gain should be large enough to provide high

DC-regulation accuracy. The phase margin should be

greater than 45o for overall stability.

The specifications for designing channel 1:

Vin = 12V

Vo = 1.8V

Vramp

= 1.8V (This is a function of Vin, pls. see

Feed-Forward section)

Vref = 0.5V

Lo = 2.2uH

Co = 4x22uF, ESR≈3mΩ each

It must be noted here that the value of the

capacitance used in the compensator design must be

I‘ER H X H ><7r>< x="" x="" x="" -="" www.\rl.com="" submxl="" dalasheel="" feedback="">

IR3891

the small signal value. For instance, the small signal

capacitance of the 22uF capacitor used in this design

is 9.5uF at 1.8 V DC bias and 600 kHz frequency. It is

this value that must be used for all computations

related to the compensation. The small signal value

may be obtained from the manufacturer’s datasheets,

design tools or SPICE models. Alternatively, they may

also be inferred from measuring the power stage

transfer function of the converter and measuring the

double pole frequency FLC and using equation (18) to

compute the small signal Co.

These result to:

FLC = 17.4 kHz

FESR = 5.6 MHz

Fs/2 = 300 kHz

Select crossover frequency F0=100 kHz

Since FLC<F0<Fs/2<FESR, Type III is selected to place

the pole and zeros.

Detailed calculation of compensation Type III:

Desired Phase Margin Θ = 70°

=

Θ+

Θ−

=sin1

sin1

2oZ FF

17.6 kHz

=

Θ−

Θ+

=sin1

sin1

2oP

FF

567.1 kHz

Select:

=×= 21 5.0 ZZ FF

8.8 kHz and

=

×=

sP

FF 5.0

3

300 kHz

Select C4 = 2.2nF.

Calculate R3, C3 and C2:

in

rampooo

VC

VCLF

R×

×××××

=

4

3

2

π

; R3 = 3.6 kΩ,

Select: R3 = 3.24 kΩ

31

32

1

RF

C

Z×××

=

π

; C3 = 5 nF,

Select: C3 = 10 nF

33

2

1

RF

C

P

×××

=

π

; C2 = 148 pF,

Select: C2 = 150 pF

Calculate R4, R5 and R6:

24

4

2

1

P

FC

R×××

=

π

; R4 = 127.6 Ω,

Select R4 = 130 Ω

2

4

52

1

Z

FC

R×

×

=

π

; R5 = 3.98 kΩ,

Select R5 = 4.02 kΩ

56

R

VV

V

R

refo

ref

×

−

=

; R6 = 1.53 kΩ,

Select R6 = 1.54 kΩ

Setting the Power Good Threshold

In this design IR3891, the PGood outer limits are set

at 85% and 120% of VREF. PGood signal is asserted

1.3ms after Vsns voltage reaches 0.85*0.5V=0.425V.

As long as the Vsns voltage is between the threshold

range, Enable is high, and no fault happens, the

PGood remains high.

The following formula can be used to set the PGood

threshold. Vout (PGood_TH) can be taken as 85% of Vout.

Choose Rsns11=1.54 KΩ.

111

85.0

12

)_(

Rsns

VREF

V

Rsns

THPGoodout

×











−

×

=

(35)

Rsns12 = 4.00 kΩ, Select 4.02 kΩ,

OVP comparator also uses Vsns signal for Over-

Voltage detection. With above values for Rsns22 and

Rsns21, OVP trip point (Vout_OVP) is

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IR3891

()

11

1211

2

.1

_Rsns

RsnsRsns

VREFVout OVP

+

××

=

(36)

Vout_OVP = 2.17 V

Selecting Power Good Pull-Up Resistor

The PGood1 and PGood2 are open drain outputs and

require pull up resistors to VCC. The value of the pull-

up resistors should limit the current flowing into the

each PGood pin to be less than 5mA. A typical value

used is 49.9kΩ.

The specifications for the channel 2 design:

Vin=12V

Vo=1.2V

Vramp=1.8V (This is a function of Vin, pls. see feed

forward section)

Vref=0.5V

Lo=1.5uH

Co=4x22uF, ESR≈3mΩ each

In the calculations, 10uF is used for the 22uF Co

capacitors due to the 1.2V bias and 600 kHz

frequency.

These result to:

FLC = 20.5 kHz

FESR = 5.3 MHz

Fs/2 = 300 kHz

Select crossover frequency F0=100 kHz

Since FLC<F0<Fs/2<FESR, Type III is selected to place

the pole and zeros.

Detailed calculation of compensation Type III:

Desired Phase Margin Θ = 70°

=

Θ+

Θ−

=sin

1

sin1

2oZ FF

17.6 kHz

=

Θ−

Θ+

=sin1

sin1

2oP FF

567.1 kHz

Select:

=×=

21

5.0

ZZ

F

8.8 kHz and

=×= sP FF 5.0

3

300 kHz

Select C4 = 2.2nF.

Calculate R3, C3 and C2:

in

rampooo

VC

VCLF

R×

×××××

=

4

3

2

π

; R3 = 2.57 kΩ,

Select: R3 = 2.87 kΩ

31

32

1

RF

C

Z×××

=

π

; C3 = 7 nF,

Select: C3 = 10 nF

33

22

1

RF

C

P×××

=

π

;

C2 = 206 pF,

Select: C2 = 150 pF

Calculate R4, R5 and R6:

24

42

1

P

F

C

R×××

=

π

; R4 = 127.6 Ω,

Select R4 = 130 Ω

24

5

2

1

Z

F

C

R×

××

=

π

; R5 = 3.98 kΩ,

Select R5 = 4.02 kΩ

56

R

VV

V

R

refo

ref

×

−

=

; R6 = 2.84 kΩ,

Select R6 = 2.87 kΩ

Setting the Power Good Threshold

Equation (35) shows how to set values for Rsns12

and Rsns11. Use the same equation to determine

Rsns21 and Rsns22 values, but substitute Rsns22 for

Rsns12 and Rsns21 for Rsns11.

Choose Rsns21=2.87 KΩ.

I‘ER Rsm 22 - www.\rl.com Submxl Dalasheel Feedback

IR3891

211

85

.0

22

)

_(

Rsns

VREF

V

Rsns

TH

PGood

out

×











−

×

=

(37)

Rsns22 = 4.02 kΩ

The typical over-voltage threshold is calculated below

for channel 2. With above values for Rsns22 and

Rsns21, OVP trip point (Vout_OVP) is

( )

22

2221

2.1

_

Rsns

RsnsRsns

VREFVout

OVP

+

××=

(38)

Vout_OVP = 1.44 V

IEZR

IR3891

APPLICATION DIAGRAM

INTERNALLY BIASED SINGLE RAIL

U1

IR3891

L0

GND

PGND1/2

Rt/Sync

Seq

SW1

Comp1

FB1

Vsns1

Boot1

EN1

PGood1

Ren12

Ren11

PGood2

EN2

Boot2

SW2

Comp2

FB2

L1

Vsns2

Ren22

Ren21

PVin1/2

Vin

Vcc

Cpvin1

Cvcc

Cpvin2 Cpvin3

Cvin

Rfb12

Rc12

Cc13

Cc12

Cc11

Rc22

Rfb22 Rc21

Cc21

Cc22

Cc23

Cboot1 Cboot2

0.1 uF0.1 uF

49.9 K

Rpg2

2.2 uF 1 uF

49.9 K

Rpg1

2 x 0.1 uF

49.9 K

7.5 K

49.9 K

7.5 K

330 uF 4 x 10 uF

4.02 K

Rsns12

1.54 K

Rsns11

4 x 22 uF

10 nF

150 pF

3.24 K

130

2200 pF

4.02 K

1.54 K

Rfb11

Rc11

39.2 K

Rt

Vo1

Vin

PG2

PG1

2.2 uH 1.5 uH

4.02 K

2.87 K

Rfb21

4 x 22 uF

Vo2

Rsns22

4.02 K

Rbd2

20

Rsns21

2.87 K

130

2200 pF

150 pF

10 nF

2.87 K

Rbd1

20

Cout1

0.1 uF

Co1 Cout2

0.1 uF

Co2

Figure 29: Application circuit for 12V to 1.8V and 1.2V, 4A Point of Load Converter Using the Internal LDO

SMD 7.05x6.6x4.8mm,11.2mﬂ .05x6.6x 6.0m!) - www \rl com Submxl Dalasheel Feedback

IR3891

Suggested Bill of Material for application circuit 12V to 1.8V and 1.2V

Part Reference

Qty

Value

Description

Manufacturer

Part Number

Cpvin1

1

330uF

SMD, electrolytic, 25V, 20%

Panasonic

EEV-FK1E331P

Cpvin2

4

10uF

1206, 25V, X5R, 10%

TDK

C3216X5R1E106M

Cvin

1

1.0uF

0603, 25V, X5R, 10%

Murata

GRM188R61E105KA12D

Cvcc

1

2.2uF

0603, 16V, X5R, 20%

TDK

C1608X5R1C225M

Co1 Co2

Cboot1

Cboot2 Cpvin3

6 0.1uF 0603, 25V, X7R, 10% Murata GRM188R71E104KA01D

Cc12 Cc22

2

10nF

0603, 50V, X7R, 10%

Murata

GRM188R71H103KA01D

Cc13 Cc23

2

150pF

0603, 50V, NPO, 5%

Murata

GRM1885C1H151JA01D

Cc11 Cc21

2

2200pF

0603, 50V, X7R, 10%

Murata

GRM188R71H222KA01D

Cpvin2

4

10uF

1206, 25V, X5R, 20%

TDK

C3216X5R1E106M

Cout1 Cout2

8

22uF

0805, 6.3V X5R, 20%

TDK

C2012X5R0J226M

L0 1 2.2uH

SMD

7.05x6.6x4.8mm,11.2mΩ

Cyntec PCMB065T-2R2MS

L1 1 1.5uH

SMD 7.05x6.6x4.8mm,

6.0mΩ

Cyntec PCMB065T-1R5MS

Rbd1 Rbd2

2

20

Thick Film, 0603, 1/10W, 1%

Panasonic

ERJ-3EKF20R0V

Ren12 Ren22

Rpg1 Rpg2

4 49.9K Thick Film, 0603, 1/10W, 1% Panasonic ERJ-3EKF4992V

Ren11 Ren21

2

7.5K

Thick Film, 0603, 1/10W, 1%

Panasonic

ERJ-3EKF7501V

Rc11 Rc21

2

130

Thick Film, 0603, 1/10W, 1%

Panasonic

ERJ-3EKF1300V

Rc12

1

3.24K

Thick Film, 0603, 1/10W, 1%

Panasonic

ERJ-3EKF3241V

Rc22

1

2.87K

Thick Film, 0603, 1/10W, 1%

Panasonic

ERJ-3EKF2871V

Rfb11 Rsns11

2

1.54K

Thick Film, 0603, 1/10W, 1%

Panasonic

ERJ-3EKF1541V

Rfb12 Rsns12

Rfb22 Rsns22

2 4.02K Thick Film, 0603, 1/10W, 1% Panasonic ERJ-3EKF4021V

Rfb21 Rsns21

2

2.87K

Thick Film, 0603, 1/10W, 1%

Panasonic

ERJ-3EKF2871V

Rt

1

39.2K

Thick Film, 0603, 1/10W, 1%

Panasonic

ERJ-3EKF3922V

U1 1 IR3891 PQFN 5x6mm

International

Rectifier

IR3891MPBF

IEZR

IR3891

EXTERNALLY BIASED DUAL RAIL

U1

IR3891

L0

GND

PGND1/2

Rt/Sync

Seq

SW1

Comp1

FB1

Vsns1

Boot1

EN1

PGood1

Ren12

Ren11

PGood2

EN2

Boot2

SW2

Comp2

FB2

L1

Vsns2

Ren22

Ren21

PVin1/2

Vin

Vcc

Cpvin1

Cvcc

Cpvin2 Cpvin3

Cvin

Rfb12

Rc12

Cc13

Cc12

Cc11

Rc22

Rfb22 Rc21

Cc21

Cc22

Cc23

Cboot1 Cboot2

0.1 uF0.1 uF

49.9 K

Rpg2

2.2 uF 1 uF

49.9 K

Rpg1

2 x 0.1 uF

49.9 K

7.5 K

49.9 K

7.5 K

330 uF 4 x 10 uF

16.5 K

Rsns12

6.34 K

Rsns11

4 x 22 uF

5.6 nF

100 pF

5.9 K

127

1000 pF

16.5 K

6.34 K

Rfb11

Rc11

39.2 K

Rt

Vo1

PVin

PG2

PG1

2.2 uH 1.5 uH

18.2 K

13 K

Rfb21

4 x 22 uF

Vo2

Rsns22

18.2 K

Rbd2

20

Rsns21

13 K

140

1000 pF

100 pF

5.6 nF

3.74 K

Rbd1

20

Cout1

0.1 uF

Co1 Cout2

0.1 uF

Co2

Vin

Figure 30: Application circuit for a 12V to 1.8V and 1.2V, 4A Point of Load Converter using external 5V VCC

.05x6.6x4 1 1 .2mQ .05x6.6x 6.0mﬂ - www \rl com Submxl Dalasheel Feedback

IR3891

Suggested Bill of Material for application circuit 12V to 1.8V and 1.2V using external 5V VCC

Part Reference

Qty

Value

Description

Manufacturer

Part Number

Cpvin1

1

330uF

SMD, electrolytic, 25V, 20%

Panasonic

EEV-FK1E331P

Cpvin2

4

10uF

1206, 25V, X5R, 10%

TDK

C3216X5R1E106M

Cvin

1

1.0uF

0603, 25V, X5R, 10%

Murata

GRM188R61E105KA12D

Cvcc

1

2.2uF

0603, 16V, X5R, 20%

TDK

C1608X5R1C225M

Cpvin3 Cboot1

Cboot2 Co1

Co2

6 0.1uF 0603, 25V, X7R, 10% Murata GRM188R71E104KA01D

Cc11 Cc21

2

1000pF

0603, 50V, X7R, 10%

Murata

GRM188R71H102KA01D

Cc12 Cc22

2

5.6nF

0603, 50V, X7R, 10%

Murata

GRM188R71H562KA01D

Cc13 Cc23

2

100pF

0603, 50V, NPO, 5%

Murata

GRM1885C1H101JA01D

Cout1 Cout2

8

22uF

0805, 6.3V X5R, 20%

TDK

C2012X5R0J226M

L0 1 2.2uH

SMD 7.05x6.6x4.8mm,

11.2mΩ

Cyntec PCMB065T-2R2MS

L1 1 1.5uH

SMD 7.05x6.6x4.8mm,

6.0mΩ

Cyntec PCMB065T-1R5MS

Rbd1 Rbd2

2

20

Thick Film, 0603, 1/10W, 1%

Panasonic

ERJ-3EKF20R0V

Rc11

1

127

Thick Film, 0603, 1/10W, 1%

Panasonic

ERJ-3EKF1270V

Rc12

1

5.9K

Thick Film, 0603, 1/10W, 1%

Panasonic

ERJ-3EKF5901V

Rc21

1

140

Thick Film, 0603, 1/10W, 1%

Panasonic

ERJ-3EKF1400V

Rc22

1

3.74K

Thick Film, 0603, 1/10W, 1%

Panasonic

ERJ-3EKF3741V

Ren11 Ren21

2

7.5K

Thick Film, 0603, 1/10W, 1%

Panasonic

ERJ-3EKF7501V

Ren12 Ren22

Rpg1 Rpg2

4 49.9K Thick Film, 0603, 1/10W, 1% Panasonic ERJ-3EKF4992V

Rfb11 Rsns11

2

6.34K

Thick Film, 0603, 1/10W, 1%

Panasonic

ERJ-3EKF6341V

Rfb12 Rsns12

2

16.5K

Thick Film, 0603, 1/10W, 1%

Panasonic

ERJ-3EKF1652V

Rfb21 Rsns21

2

13K

Thick Film, 0603, 1/10W, 1%

Panasonic

ERJ-3EKF1302V

Rfb22 Rsns22

2

18.2K

Thick Film, 0603, 1/10W, 1%

Panasonic

ERJ-3EKF1822V

Rt

1

39.2K

Thick Film, 0603, 1/10W, 1%

Panasonic

ERJ-3EKF3922V

U1 1 IR3891 PQFN 5x6mm

International

Rectifier

IR3891MPBF

m I

IR3891

EXTERNALLY BIASED SINGLE RAIL

U1

IR3891

L0

GND

PGND1/2

Rt/Sync

Seq

SW1

Comp1

FB1

Vsns1

Boot1

EN1

PGood1

Ren12

Ren11

PGood2

EN2

Boot2

SW2

Comp2

FB2

L1

Vsns2

Ren22

Ren21

PVin1/2

Vin

Vcc

Cpvin1

Cvcc

Cpvin2 Cpvin3

Cvin

Rfb12

Rc12

Cc13

Cc12

Cc11

Rc22

Rfb22 Rc21

Cc21

Cc22

Cc23

Cboot1 Cboot2

0.1 uF0.1 uF

49.9 K

Rpg2

2.2 uF 1 uF

49.9 K

Rpg1

2 x 0.1 uF

41.2 K

21 K

41.2 K

21 K

330 uF 8 x 10 uF

6.81 K

Rsns12

2.61 K

Rsns11

4 x 22 uF

5.6 nF

100 pF

3.74 K

52.3

2200 pF

6.81 K

2.61 K

Rfb11

Rc11

39.2 K

Rt

Vo1

Vin

PG2

PG1

1.5 uH 1.5 uH

6.81 K

4.87 K

Rfb21

4 x 22 uF

Vo2

Rsns22

6.81 K

Rbd2

20

Rsns21

4.87 K

52.3

2200 pF

100 pF

5.6 nF

4.02 K

Rbd1

20

Cout1

0.1 uF

Co1 Cout2

0.1 uF

Co2

Figure 31: Application circuit for a 5V to 1.8V and 1.2V, 4A Point of Load Converter

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IR3891

Suggested bill of material for application circuit 5V to 1.8V and 1.2V

Part Reference

Qty

Value

Description

Manufacturer

Part Number

Cpvin1

1

330uF

SMD, electrolytic, 25V, 20%

Panasonic

EEV-FK1E331P

Cpvin2

8

10uF

1206, 25V, X5R, 10%

TDK

C3216X5R1E106M

Cvin

1

1.0uF

0603, 25V, X5R, 10%

Murata

GRM188R61E105KA12D

Cvcc

1

2.2uF

0603, 16V, X5R, 20%

TDK

C1608X5R1C225M

Cpvin3 Cboot1

Cboot2 Co1

Co2

6 0.1uF 0603, 25V, X7R, 10% Murata GRM188R71E104KA01D

Cc12 Cc22

2

5.6nF

0603, 50V, X7R, 10%

Murata

GRM188R71H562KA01D

Cc13 Cc23

2

100pF

0603, 50V, NPO, 5%

Murata

GRM1885C1H101JA01D

Cc11 Cc21

2

2200pF

0603, 50V, X7R, 10%

Murata

GRM188R71H222KA01D

Cout1 Cout2

8

22uF

0805, 6.3V X5R, 20%

TDK

C2012X5R0J226M

L0 L1 2 1.5uH

SMD 7.05x6.6x4.8mm,

6.0mΩ

Cyntec PCMB065T-1R5MS

Rbd1 Rbd2

2

20

Thick Film, 0603, 1/10W, 1%

Panasonic

ERJ-3EKF20R0V

Rc11 Rc21

2

52.3

Thick Film, 0603, 1/10W, 1%

Panasonic

ERJ-3EKF52R3V

Rc12

1

6.81K

Thick Film, 0603, 1/10W, 1%

Panasonic

ERJ-3EKF6811V

Rc22

1

4.02K

Thick Film, 0603, 1/10W, 1%

Panasonic

ERJ-3EKF4021V

Ren11 Ren21

2

21K

Thick Film, 0603, 1/10W, 1%

Panasonic

ERJ-3EKF2102V

Ren12 Ren22

2

41.2K

Thick Film, 0603, 1/10W, 1%

Panasonic

ERJ-3EKF4122V

Rfb11 Rsns11

2

2.61K

Thick Film, 0603, 1/10W, 1%

Panasonic

ERJ-3EKF2611V

Rfb12 Rsns12

Rfb22 Rsns22

4 6.81K Thick Film, 0603, 1/10W, 1% Panasonic ERJ-3EKF6811V

Rfb21 Rsns21

2

4.87K

Thick Film, 0603, 1/10W, 1%

Panasonic

ERJ-3EKF4871V

Rpg1 Rpg2

2

49.9K

Thick Film, 0603, 1/10W, 1%

Panasonic

ERJ-3EKF4992V

Rt

1

39.2K

Thick Film, 0603, 1/10W, 1%

Panasonic

ERJ-3EKF3922V

U1 1 IR3891 PQFN 5x6mm

International

Rectifier

IR3891MPBF

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IR3891

TYPICAL OPERATING WAVEFORMS

Vin=PVin=12V, Vo1=1.8V, Iout1=0-4A, Vo2=1.2V, Iout1=0-4A, Fs=600kHz, Room Temperature, No air flow

Figure 32: Startup with full load

CH1:Vout1, Ch2:Vout2, Ch3:Vin, CH4:Vcc

Figure 33: PGood signals at Startup with full load

CH1:Vout1, Ch2:Vout2, Ch3:PGood1, CH4:PGood2

Figure 34: Channel 1 Startup with Pre-Bias, 1.52V

CH1:Enable1, Ch2:Vout1, Ch4:PGood1

Figure 35: Channel 2 Startup with Pre-Bias, 1.05V

CH1:Enable2, Ch2:Vout2, Ch4:PGood2

Figure 36: Inductor Switch Nodes at full load

CH1:SW1, Ch2:SW2

Figure 37: Output Voltage Ripples at full load

CH1:Vout1, Ch2:Vout2

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IR3891

TYPICAL OPERATING WAVEFORMS

Vin=PVin=12V, Vo1=1.8V, Iout1=0-4A, Vo2=1.2V, Iout1=0-4A, Fs=600kHz, Room Temperature, No air flow

Figure 38: Vout1 Transient Response, 0A to 1.6A step at 2.5A/µSec

CH1:Vout1, CH2=Vout2, CH4:Iout1

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IR3891

TYPICAL OPERATING WAVEFORMS

Vin=PVin=12V, Vo1=1.8V, Iout1=0-4A, Vo2=1.2V, Iout1=0-4A, Fs=600kHz, Room Temperature, No air flow

Figure 39: Vout2 Transient Response, 0A to 1.6A step at 2.5A/µSec

CH1:Vout1, CH2=Vout2, CH4:Iout2

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IR3891

TYPICAL OPERATING WAVEFORMS

Vin=PVin=12V, Vo1=1.8V, Iout1=0-4A, Vo2=1.2V, Iout1=0-4A, Fs=600kHz, Room Temperature, No air flow

Figure 40: CH1 Bode Plot with 4A load, CH2 disabled.

Fo = 84.9 kHz, Phase Margin = 51.9 Degrees

Figure 41: CH2 Bode Plot with 4A load, CH1 disabled.

Fo = 113.1 kHz, Phase Margin = 48.2 Degrees

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IR3891

LAYOUT RECOMMENDATIONS

The layout is very important when designing high

frequency switching converters. Layout will affect

noise pickup and can cause a good design to perform

with less than expected results.

Make the connections for the power components on

the top layer with wide, copper filled areas or

polygons. In general, it is desirable to make proper

use of power planes and polygons for power

distribution and heat dissipation.

The inductor, input capacitors, output capacitors and

the IR3891 should be as close to each other as

possible. This helps to reduce the EMI radiated by the

power traces due to the high switching currents

through them. Place the input capacitor directly at the

PVin pin of IR3891.

The feedback part of the system should be kept away

from the inductor and other noise sources.

The critical bypass components such as capacitors for

PVin and VCC should be close to their respective

pins. It is important to place the feedback components

including feedback resistors and compensation

components close to Fb and Comp pins.

In a multilayer PCB use one layer as a power ground

plane and have a control circuit ground (analog

ground), to which all signals are referenced. The goal

is to localize the high current path to a separate loop

that does not interfere with the more sensitive analog

control function. These two grounds must be

connected together on the PC board layout at a single

point. It is recommended to place all the

compensation parts over the analog ground plane on

top layer.

The Power QFN is a thermally enhanced package.

Based on thermal performance it is recommended to

use at least a 4-layers PCB. To effectively remove

heat from the device the exposed pad should be

connected to the ground plane using vias. Figure

42a-d illustrates the implementation of the layout

guidelines outlined above, on the IRDC3891 4-layer

demo board.

Figure 42a: IRDC3891 Demo board Layout Considerations – Top Layer

- Compensation parts

should be placed

as close as possible

t

o the Comp pins

- SW node copper is

kept on

ly at the top

layer to

minimize the

switching noise

- Single point connection

between AGND &

PGND, should be placed

near the part and kept

away from noise sources

PGND

PVin

Vout1

Vout2

AGND

- Ground path length

between VIN

- and VOUT1-

should be minimized with

maximum copper

- Ground path length

between VIN

- and

VOUT2

- should be

minimized with

maximum copper

- Bypass caps should

be placed as close as

possible to their

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IR3891

Figure 42b: IRDC3891 Demo board Layout Considerations – Bottom Layer

Figure 42c: IRDC3891 Demo board Layout Considerations – Mid Layer 1

Figure 42d: IRDC3891 Demo board Layout Considerations – Mid Layer 2

Feedback and Vsns trace

routing should be kept

away from noise sources

Vin

PGND

AGND

PGND

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IR3891

PCB METAL AND COMPONENT PLACEMENT

Evaluations have shown that the best overall

performance is achieved using the substrate/PCB

layout as shown in following figures. PQFN devices

should be placed to an accuracy of 0.050mm on

both X and Y axes. Self-centering behavior is highly

dependent on solders and processes, and

experiments should be run to confirm the limits of

self-centering on specific processes. For further

information, please refer to “SupIRBuck® Multi-Chip

Module (MCM) Power Quad Flat No-Lead (PQFN)

Board Mounting Application Note.” (AN1132)

Figure 43: PCB Pad Sizes Detail 1

(Dimensions in mm)

Figure 44: PCB Pad Sizes Detail 2

(Dimensions in mm)

Figure 45: PCB Metal Pad Spacing (Dimensions in mm)

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IR3891

SOLDER RESIST

• IR recommends that the larger Power or Land

Area pads are Solder Mask Defined (SMD).

This allows the underlying Copper traces to be

as large as possible, which helps in terms of

current carrying capability and device cooling

capability.

• When using SMD pads, the underlying copper

traces should be at least 0.05mm larger (on

each edge) than the Solder Mask window, in

order to accommodate any layer to layer

misalignment. (i.e. 0.1mm in X & Y).

• However, for the smaller Signal type leads

around the edge of the device, IR recommends

that these are Non Solder Mask Defined or

Copper Defined.

• When using NSMD pads, the Solder Resist

Window should be larger than the Copper Pad

by at least 0.025mm on each edge, (i.e.

0.05mm in X & Y), in order to accommodate any

layer to layer misalignment.

• Ensure that the solder resist in-between the

smaller signal lead areas are at least 0.15mm

wide, due to the high x/y aspect ratio of the

solder mask strip.

Figure 46: SMD Pad Sizes Detail 1 (Dimensions in mm)

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IR3891

Figure 47: SMD Pad Sizes Detail 2 (Dimensions in mm)

Figure 48: SMD Pad Spacing (Dimensions in mm)

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IR3891

STENCIL DESIGN

• Stencils for PQFN can be used with thicknesses of

0.100-0.250mm (0.004-0.010"). Stencils thinner

than 0.100mm are unsuitable because they

deposit insufficient solder paste to make good

solder joints with the ground pad; high

reductions sometimes create similar problems.

Stencils in the range of 0.125mm-0.200mm

(0.005-0.008"), with suitable reductions, give the

best results.

• Evaluations have shown that the best overall

performance is achieved using the stencil design

shown in following figure. This design is for a

stencil thickness of 0.127mm (0.005"). The

reduction should be adjusted for stencils of other

thicknesses.

Figure 49: Stencil Pad Sizes (Dimensions in mm)

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IR3891

Figure 50: Stencil Pad Spacing Detail 1 (Dimensions in mm)

Figure 51: Stencil Pad Spacing Detail 2 (Dimensions in mm)

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IR3891

MARKING INFORMATION

Figure 52: Marking Information

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IR3891

IEER \nTernorionol IE: Rectiﬁer www.irl.com - www.\rl.com Submxl Dalasheel Feedback

IR3891

ENVIRONMENTAL QUALIFICATIONS

Qualification Level

Industrial

Moisture Sensitivity Level 5mm x 6mm PQFN MSL2

ESD

Machine Model

(JESD22-A115A)

Class A

<200V

Human Body Model

(JESD22-A114F)

Class 1C

≥1000V to <2000V

Charged Device Model

(JESD22-C101D)

Class III

≥500V to ≤1000V

RoHS Compliant

Yes

Data and specifications subject to change without notice.

Qualification Standards can be found on IR’s Web site.

IR WORLD HEADQUARTERS: 233 Kansas St., El Segundo, California 90245, USA Tel: (310) 252-7105

TAC Fax: (310) 252-7903

Visit us at www.irf.com for sales contact information.

www.irf.com

Datenblatt für IR3891 von Infineon Technologies

INFORMATION

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