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SILIEEIN LABS
Voltage
Comparator
Brown-Out
Belem, Powers" Reset
Backup Damam
EFM32WG Reference Manual
The EFM32 Wonder Gecko MCUs are the world’s most energy-
friendly microcontrollers.
The EFM32WG offers unmatched performance and ultra low power consumption in both
active and sleep modes. EFM32WG devices consume as little as 0.65 μA in Stop mode
and 225 μA/MHz in Run mode. It also features autonomous peripherals, high overall chip
and analog integration, and the performance of the industry standard 32-bit ARM Cortex-
M4 processor, making it perfect for battery-powered systems and systems with high-per-
formance, low-energy requirements.
EFM32WG applications include the following:
KEY FEATURES
• ARM Cortex-M4 at 48 MHz
• Ultra low power operation
• 0.65 μA current in Stop (EM3), with
CRYOTIMER and RAM retention
• 63 μA/MHz in EM1
• 225 μA/MHz in Run mode (EM0)
• Fast wake-up time of 2 us
• Hardware cryptography (AES)
• Up to 256 kB of Flash and 32 kB of RAM
• Smart metering
• Water metering
• Gas metering
• Industrial and home automation
• Alarm and security systems
• Health and fitness applications
32-bit bus
Lowest power mode with peripheral operational:
EM2 – Deep Sleep
EM1 - Sleep EM4S - Shutoff
EM0 - Active EM3 - Stop
Core / Memory
Flash Program
Memory
RAM Memory
ARM CortexTM
M4 processor
with FPU and
MPU
Debug Interface
with ETM
DMA Controller
Memory
Protection Unit
Other
Hardware AES
Energy Management
Brown-Out
Detector
Voltage
Regulator
Voltage
Comparator
Power-On Reset
Clock Management
High Frequency
RC Oscillator
Ultra Low Freq.
RC Oscillator
Low Frequency
Crystal Oscillator
Low Frequency
RC Oscillator
Auxiliary High
Freq. RC Osc.
High Frequency
Crystal Oscillator
Analog Interfaces
LCD Controller
Operational
Amplifier
ADC
DAC
Analog
Comparator
Backup Domain
Peripheral Reflex System
Serial Interfaces
UART
I2C
USB
I/O Ports Timers and Triggers
LESENSE
Timer/Counter
Low Energy Timer
Watchdog Timer
Back-Up RTC
External
Interrupts
Pin Reset
External Bus
Interface
General
Purpose I/O
Pin Wakeup
TFT Driver
Pulse Counter
Real Time Counter
USART
Low Energy
UARTTM
silabs.com | Building a more connected world. Rev. 1.1
Table of Contents
1. Energy Friendly Microcontrollers .......................24
1.1 Typical Applications ............................24
1.2 EFM32WG Development ..........................24
2. About This Document ...........................25
2.1 Conventions ..............................25
2.2 Related Documentation ..........................26
3. System Overview .............................27
3.1 Introduction...............................27
3.2 Features................................28
3.3 Block Diagram..............................30
3.4 Energy Modes..............................30
3.5 Product Overview ............................32
3.6 Device Revision .............................35
4. System Processor ............................36
4.1 Introduction...............................36
4.2 Features................................37
4.3 Functional Description ...........................37
4.3.1 Interrupt Operation ..........................38
5. Memory and Bus System ..........................40
5.1 Introduction...............................41
5.2 Functional Description ...........................42
5.2.1 Bit-Banding.............................43
5.2.2 Peripherals .............................45
5.2.3 Bus Matrix .............................47
5.2.4 Access to Low Energy Peripherals (Asynchronous Registers)............48
5.2.5 Flash ...............................50
5.2.6 SRAM ..............................51
5.2.7 Device Information (DI) Page.......................52
6. DBG - Debug Interface ...........................54
6.1 Introduction...............................54
6.2 Features................................54
6.3 Functional Description ...........................54
6.3.1 Debug Pins.............................55
6.3.2 Embedded Trace Macrocell v3.5 (ETM) ...................55
6.3.3 Debug and EM2/EM3 .........................55
6.3.4 Debug Lock and Device Erase ......................56
6.4 Register Map ..............................57
6.5 Register Description ............................58
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6.5.1 AAP_CMD - Command Register .....................58
6.5.2 AAP_CMDKEY - Command Key Register ..................58
6.5.3 AAP_STATUS - Status Register .....................59
6.5.4 AAP_IDR - AAP Identification Register ...................59
7. MSC - Memory System Controller....................... 60
7.1 Introduction...............................60
7.2 Features................................61
7.3 Functional Description ...........................61
7.3.1 User Data (UD) Page Description .....................62
7.3.2 Lock Bits (LB) Page Description......................62
7.3.3 Device Information (DI) Page.......................62
7.3.4 Post-Reset Behavior .........................62
7.3.5 Erase and Write Operations .......................65
7.4 Register Map ..............................66
7.5 Register Description ............................67
7.5.1 MSC_CTRL - Memory System Control Register ................67
7.5.2 MSC_READCTRL - Read Control Register .................68
7.5.3 MSC_WRITECTRL - Write Control Register .................69
7.5.4 MSC_WRITECMD - Write Command Register ................70
7.5.5 MSC_ADDRB - Page Erase/Write Address Buffer ...............71
7.5.6 MSC_WDATA - Write Data Register ....................71
7.5.7 MSC_STATUS - Status Register .....................72
7.5.8 MSC_IF - Interrupt Flag Register .....................73
7.5.9 MSC_IFS - Interrupt Flag Set Register ...................73
7.5.10 MSC_IFC - Interrupt Flag Clear Register ..................74
7.5.11 MSC_IEN - Interrupt Enable Register ...................74
7.5.12 MSC_LOCK - Configuration Lock Register .................75
7.5.13 MSC_CMD - Command Register ....................76
7.5.14 MSC_CACHEHITS - Cache Hits Performance Counter .............76
7.5.15 MSC_CACHEMISSES - Cache Misses Performance Counter ...........77
7.5.16 MSC_TIMEBASE - Flash Write and Erase Timebase ..............77
7.5.17 MSC_MASSLOCK - Mass Erase Lock Register ...............78
8. DMA - DMA Controller ...........................79
8.1 Introduction...............................79
8.2 Features................................80
8.3 Block Diagram..............................81
8.4 Functional Description ...........................82
8.4.1 Channel Select Configuration ......................82
8.4.2 DMA Control ............................83
8.4.3 Channel Control Data Structure ......................96
8.4.4 Looped Transfers .........................106
8.4.5 2D Copy.............................107
8.4.6 Interaction with the EMU .......................107
8.4.7 Interrupts ............................108
8.4.8 Examples ............................108
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8.5 Register Map .............................109
8.6 Register Description ...........................110
8.6.1 DMA_STATUS - DMA Status Registers ..................110
8.6.2 DMA_CONFIG - DMA Configuration Register ................111
8.6.3 DMA_CTRLBASE - Channel Control Data Base Pointer Register .........111
8.6.4 DMA_ALTCTRLBASE - Channel Alternate Control Data Base Pointer Register ....112
8.6.5 DMA_CHWAITSTATUS - Channel Wait on Request Status Register ........113
8.6.6 DMA_CHSWREQ - Channel Software Request Register ............114
8.6.7 DMA_CHUSEBURSTS - Channel Useburst Set Register ............115
8.6.8 DMA_CHUSEBURSTC - Channel Useburst Clear Register ...........117
8.6.9 DMA_CHREQMASKS - Channel Request Mask Set Register ..........118
8.6.10 DMA_CHREQMASKC - Channel Request Mask Clear Register .........119
8.6.11 DMA_CHENS - Channel Enable Set Register ...............120
8.6.12 DMA_CHENC - Channel Enable Clear Register ..............121
8.6.13 DMA_CHALTS - Channel Alternate Set Register ..............122
8.6.14 DMA_CHALTC - Channel Alternate Clear Register .............123
8.6.15 DMA_CHPRIS - Channel Priority Set Register ...............124
8.6.16 DMA_CHPRIC - Channel Priority Clear Register ..............125
8.6.17 DMA_ERRORC - Bus Error Clear Register ................126
8.6.18 DMA_CHREQSTATUS - Channel Request Status ..............127
8.6.19 DMA_CHSREQSTATUS - Channel Single Request Status ...........129
8.6.20 DMA_IF - Interrupt Flag Register ...................131
8.6.21 DMA_IFS - Interrupt Flag Set Register ..................133
8.6.22 DMA_IFC - Interrupt Flag Clear Register .................134
8.6.23 DMA_IEN - Interrupt Enable register ..................135
8.6.24 DMA_CTRL - DMA Control Register ..................136
8.6.25 DMA_RDS - DMA Retain Descriptor State ................137
8.6.26 DMA_LOOP0 - Channel 0 Loop Register .................138
8.6.27 DMA_LOOP1 - Channel 1 Loop Register .................139
8.6.28 DMA_RECT0 - Channel 0 Rectangle Register ...............139
8.6.29 DMA_CHx_CTRL - Channel Control Register ...............140
9. RMU - Reset Management Unit ........................144
9.1 Introduction..............................144
9.2 Features...............................144
9.3 Functional Description ..........................145
9.3.1 RMU_RSTCAUSE Register ......................146
9.3.2 Power-On Reset (POR) .......................147
9.3.3 Brown-Out Detector Reset (BOD) ....................147
9.3.4 RESETn Pin Reset .........................147
9.3.5 Watchdog Reset ..........................148
9.3.6 Lockup Reset ...........................148
9.3.7 System Reset Request ........................148
9.3.8 EM4 Reset ............................148
9.3.9 EM4 Wakeup Reset .........................148
9.4 Register Map .............................148
9.5 Register Description ...........................149
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9.5.1 RMU_CTRL - Control Register .....................149
9.5.2 RMU_RSTCAUSE - Reset Cause Register ................150
9.5.3 RMU_CMD - Command Register ....................151
10. EMU - Energy Management Unit .......................152
10.1 Introduction .............................152
10.2 Features ..............................152
10.3 Functional Description .........................153
10.3.1 Energy Modes ..........................154
10.3.2 Entering a Low Energy Mode .....................157
10.3.3 Leaving a Low Energy Mode .....................158
10.3.4 Backup Power Domain .......................159
10.4 Register Map.............................163
10.5 Register Description ..........................164
10.5.1 EMU_CTRL - Control Register ....................164
10.5.2 EMU_LOCK - Configuration Lock Register ................165
10.5.3 EMU_AUXCTRL - Auxiliary Control Register ...............165
10.5.4 EMU_EM4CONF - Energy Mode 4 Configuration Register ...........166
10.5.5 EMU_BUCTRL - Backup Power configuration register ............167
10.5.6 EMU_PWRCONF - Power Connection Configuration Register ..........168
10.5.7 EMU_BUINACT - Backup Mode Inactive Configuration Register .........169
10.5.8 EMU_BUACT - Backup mode active configuration register ...........170
10.5.9 EMU_STATUS - Status register ....................171
10.5.10 EMU_ROUTE - I/O Routing Register ..................171
10.5.11 EMU_IF - Interrupt Flag Register ...................172
10.5.12 EMU_IFS - Interrupt Flag Set Register .................172
10.5.13 EMU_IFC - Interrupt Flag Clear Register ................173
10.5.14 EMU_IEN - Interrupt Enable Register .................173
10.5.15 EMU_BUBODBUVINCAL - BU_VIN Backup BOD calibration ..........174
10.5.16 EMU_BUBODUNREGCAL - Unregulated power Backup BOD calibration .....174
11. CMU - Clock Management Unit .......................175
11.1 Introduction .............................175
11.2 Features ..............................175
11.3 Functional Description .........................176
11.3.1 System Clocks ..........................177
11.3.2 Oscillator Selection ........................179
11.3.3 Oscillator Configuration .......................181
11.3.4 Configuration For Operating Frequencies .................185
11.3.5 Output Clock on a Pin ........................185
11.3.6 Protection ............................185
11.4 Register Map.............................186
11.5 Register Description ..........................187
11.5.1 CMU_CTRL - CMU Control Register ..................187
11.5.2 CMU_HFCORECLKDIV - High Frequency Core Clock Division Register ......190
11.5.3 CMU_HFPERCLKDIV - High Frequency Peripheral Clock Division Register .....191
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11.5.4 CMU_HFRCOCTRL - HFRCO Control Register ..............192
11.5.5 CMU_LFRCOCTRL - LFRCO Control Register ...............193
11.5.6 CMU_AUXHFRCOCTRL - AUXHFRCO Control Register ...........194
11.5.7 CMU_CALCTRL - Calibration Control Register ...............195
11.5.8 CMU_CALCNT - Calibration Counter Register ...............196
11.5.9 CMU_OSCENCMD - Oscillator Enable/Disable Command Register ........197
11.5.10 CMU_CMD - Command Register ...................198
11.5.11 CMU_LFCLKSEL - Low Frequency Clock Select Register ...........199
11.5.12 CMU_STATUS - Status Register ...................201
11.5.13 CMU_IF - Interrupt Flag Register ...................203
11.5.14 CMU_IFS - Interrupt Flag Set Register .................204
11.5.15 CMU_IFC - Interrupt Flag Clear Register ................205
11.5.16 CMU_IEN - Interrupt Enable Register .................206
11.5.17 CMU_HFCORECLKEN0 - High Frequency Core Clock Enable Register 0 .....207
11.5.18 CMU_HFPERCLKEN0 - High Frequency Peripheral Clock Enable Register 0 ....208
11.5.19 CMU_SYNCBUSY - Synchronization Busy Register .............210
11.5.20 CMU_FREEZE - Freeze Register ...................211
11.5.21 CMU_LFACLKEN0 - Low Frequency A Clock Enable Register 0 (Async Reg) ....212
11.5.22 CMU_LFBCLKEN0 - Low Frequency B Clock Enable Register 0 (Async Reg) ....212
11.5.23 CMU_LFAPRESC0 - Low Frequency A Prescaler Register 0 (Async Reg) .....213
11.5.24 CMU_LFBPRESC0 - Low Frequency B Prescaler Register 0 (Async Reg) .....215
11.5.25 CMU_PCNTCTRL - PCNT Control Register ...............216
11.5.26 CMU_LCDCTRL - LCD Control Register ................217
11.5.27 CMU_ROUTE - I/O Routing Register ..................218
11.5.28 CMU_LOCK - Configuration Lock Register ................219
12. WDOG - Watchdog Timer .........................220
12.1 Introduction .............................220
12.2 Features ..............................220
12.3 Functional Description .........................220
12.3.1 Clock Source ..........................221
12.3.2 Debug Functionality ........................221
12.3.3 Energy Mode Handling .......................221
12.3.4 Register Access..........................221
12.4 Register Map.............................221
12.5 Register Description ..........................222
12.5.1 WDOG_CTRL - Control Register (Async Reg) ...............222
12.5.2 WDOG_CMD - Command Register (Async Reg) ..............224
12.5.3 WDOG_SYNCBUSY - Synchronization Busy Register ............225
13. PRS - Peripheral Reflex System .......................226
13.1 Introduction .............................226
13.2 Features ..............................226
13.3 Functional Description .........................226
13.3.1 Asynchronous Mode ........................227
13.3.2 Channel Functions .........................227
13.3.3 Producers ............................228
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13.3.4 Consumers ...........................230
13.3.5 Example ............................231
13.4 Register Map.............................231
13.5 Register Description ..........................232
13.5.1 PRS_SWPULSE - Software Pulse Register ................232
13.5.2 PRS_SWLEVEL - Software Level Register ................233
13.5.3 PRS_ROUTE - I/O Routing Register ..................234
13.5.4 PRS_CHx_CTRL - Channel Control Register ...............235
14. EBI - External Bus Interface ........................240
14.1 Introduction .............................240
14.2 Features ..............................240
14.3 Functional Description .........................241
14.3.1 Non-Multiplexed 8-Bit Data, 8-Bit Address Mode ...............243
14.3.2 Multiplexed 16-bit Data, 16-bit Address Mode ................244
14.3.3 Multiplexed 8-Bit Data, 24-Bit Address Mode ................245
14.3.4 Non-Multiplexed 16-Bit Data, N-Bit Address Mode ..............246
14.3.5 Page Mode Read Operation .....................247
14.3.6 Extended Addressing ........................250
14.3.7 Prefetch Unit and Write Buffer .....................251
14.3.8 Strobe Length ..........................252
14.3.9 Bus Turn-Around and Idle Cycles ....................253
14.3.10 Timing ............................254
14.3.11 Data Access Width ........................255
14.3.12 Bank Access ..........................256
14.3.13 WAIT/ARDY ..........................257
14.3.14 NAND Flash Support .......................258
14.3.15 Error Correction Code .......................264
14.3.16 TFT Direct Drive .........................267
14.3.17 Alpha Blending and Masking .....................271
14.3.18 Direct Drive Timing ........................274
14.3.19 Control Signal Polarity .......................276
14.3.20 Pin Configuration .........................276
14.3.21 Interrupts ...........................277
14.3.22 DMA Request ..........................277
14.4 Register Map.............................278
14.5 Register Description ..........................280
14.5.1 EBI_CTRL - Control Register .....................280
14.5.2 EBI_ADDRTIMING - Address Timing Register ...............283
14.5.3 EBI_RDTIMING - Read Timing Register .................284
14.5.4 EBI_WRTIMING - Write Timing Register .................285
14.5.5 EBI_POLARITY - Polarity Register ...................286
14.5.6 EBI_ROUTE - I/O Routing Register ...................288
14.5.7 EBI_ADDRTIMING1 - Address Timing Register 1 ..............290
14.5.8 EBI_RDTIMING1 - Read Timing Register 1 ................291
14.5.9 EBI_WRTIMING1 - Write Timing Register 1 ................292
14.5.10 EBI_POLARITY1 - Polarity Register 1 .................293
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14.5.11 EBI_ADDRTIMING2 - Address Timing Register 2 .............294
14.5.12 EBI_RDTIMING2 - Read Timing Register 2 ...............295
14.5.13 EBI_WRTIMING2 - Write Timing Register 2 ...............296
14.5.14 EBI_POLARITY2 - Polarity Register 2 .................297
14.5.15 EBI_ADDRTIMING3 - Address Timing Register 3 .............298
14.5.16 EBI_RDTIMING3 - Read Timing Register 3 ...............299
14.5.17 EBI_WRTIMING3 - Write Timing Register 3 ...............300
14.5.18 EBI_POLARITY3 - Polarity Register 3 .................301
14.5.19 EBI_PAGECTRL - Page Control Register ................303
14.5.20 EBI_NANDCTRL - NAND Control Register ................304
14.5.21 EBI_CMD - Command Register ...................305
14.5.22 EBI_STATUS - Status Register ....................306
14.5.23 EBI_ECCPARITY - ECC Parity register .................307
14.5.24 EBI_TFTCTRL - TFT Control Register .................308
14.5.25 EBI_TFTSTATUS - TFT Status Register ................310
14.5.26 EBI_TFTFRAMEBASE - TFT Frame Base Register .............310
14.5.27 EBI_TFTSTRIDE - TFT Stride Register .................311
14.5.28 EBI_TFTSIZE - TFT Size Register ..................311
14.5.29 EBI_TFTHPORCH - TFT Horizontal Porch Register .............312
14.5.30 EBI_TFTVPORCH - TFT Vertical Porch Register ..............313
14.5.31 EBI_TFTTIMING - TFT Timing Register .................314
14.5.32 EBI_TFTPOLARITY - TFT Polarity Register ...............315
14.5.33 EBI_TFTDD - TFT Direct Drive Data Register ...............316
14.5.34 EBI_TFTALPHA - TFT Alpha Blending Register ..............316
14.5.35 EBI_TFTPIXEL0 - TFT Pixel 0 Register .................317
14.5.36 EBI_TFTPIXEL1 - TFT Pixel 1 Register .................317
14.5.37 EBI_TFTPIXEL - TFT Alpha Blending Result Pixel Register ..........318
14.5.38 EBI_TFTMASK - TFT Masking Register .................318
14.5.39 EBI_IF - Interrupt Flag Register ...................319
14.5.40 EBI_IFS - Interrupt Flag Set Register ..................320
14.5.41 EBI_IFC - Interrupt Flag Clear Register .................321
14.5.42 EBI_IEN - Interrupt Enable Register ..................322
15. USB - Universal Serial Bus Controller.....................323
15.1 Introduction .............................323
15.2 Features ..............................324
15.3 USB System Description .........................325
15.3.1 USB Initialization .........................325
15.3.2 Configurations ..........................326
15.3.3 PHY..............................331
15.3.4 Voltage Regulator .........................331
15.3.5 Interrupts and PRS.........................331
15.3.6 USB in EM2 ...........................331
15.4 USB Core Description ..........................332
15.4.1 Overview: Programming the Core ....................332
15.4.2 Modes of Operation ........................336
15.4.3 Host Programming Model ......................340
15.4.4 Device Programming Model......................372
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15.4.5 OTG Revision 1.3 Programming Model ..................410
15.4.6 OTG Revision 2.0 Programming Model ..................413
15.4.7 FIFO RAM Allocation ........................420
15.4.8 Suspend/Resume and SRP ......................429
15.4.9 Register Usage ..........................438
15.5 Register Map.............................439
15.6 Register Description ..........................443
15.6.1 USB_CTRL - System Control Register ..................443
15.6.2 USB_STATUS - System Status Register .................444
15.6.3 USB_IF - Interrupt Flag Register ....................444
15.6.4 USB_IFS - Interrupt Flag Set Register ..................445
15.6.5 USB_IFC - Interrupt Flag Clear Register .................445
15.6.6 USB_IEN - Interrupt Enable Register ..................446
15.6.7 USB_ROUTE - I/O Routing Register ..................446
15.6.8 USB_GOTGCTL - OTG Control and Status Register .............447
15.6.9 USB_GOTGINT - OTG Interrupt Register .................449
15.6.10 USB_GAHBCFG - AHB Configuration Register ..............451
15.6.11 USB_GUSBCFG - USB Configuration Register ..............453
15.6.12 USB_GRSTCTL - Reset Register ...................455
15.6.13 USB_GINTSTS - Interrupt Register ..................457
15.6.14 USB_GINTMSK - Interrupt Mask Register ................461
15.6.15 USB_GRXSTSR - Receive Status Debug Read Register ...........463
15.6.16 USB_GRXSTSP - Receive Status Read and Pop Register ..........465
15.6.17 USB_GRXFSIZ - Receive FIFO Size Register ...............467
15.6.18 USB_GNPTXFSIZ - Non-periodic Transmit FIFO Size Register .........467
15.6.19 USB_GNPTXSTS - Non-periodic Transmit FIFO/Queue Status Register ......468
15.6.20 USB_GDFIFOCFG - Global DFIFO Configuration Register ..........469
15.6.21 USB_HPTXFSIZ - Host Periodic Transmit FIFO Size Register .........469
15.6.22 USB_DIEPTXF1 - Device IN Endpoint Transmit FIFO 1 Size Register ......470
15.6.23 USB_DIEPTXF2 - Device IN Endpoint Transmit FIFO 2 Size Register ......471
15.6.24 USB_DIEPTXF3 - Device IN Endpoint Transmit FIFO 3 Size Register ......472
15.6.25 USB_DIEPTXF4 - Device IN Endpoint Transmit FIFO 4 Size Register ......473
15.6.26 USB_DIEPTXF5 - Device IN Endpoint Transmit FIFO 5 Size Register ......474
15.6.27 USB_DIEPTXF6 - Device IN Endpoint Transmit FIFO 6 Size Register ......475
15.6.28 USB_HCFG - Host Configuration Register ................476
15.6.29 USB_HFIR - Host Frame Interval Register ................477
15.6.30 USB_HFNUM - Host Frame Number/Frame Time Remaining Register ......478
15.6.31 USB_HPTXSTS - Host Periodic Transmit FIFO/Queue Status Register ......479
15.6.32 USB_HAINT - Host All Channels Interrupt Register .............480
15.6.33 USB_HAINTMSK - Host All Channels Interrupt Mask Register .........480
15.6.34 USB_HPRT - Host Port Control and Status Register ............481
15.6.35 USB_HCx_CHAR - Host Channel x Characteristics Register ..........484
15.6.36 USB_HCx_INT - Host Channel x Interrupt Register .............486
15.6.37 USB_HCx_INTMSK - Host Channel x Interrupt Mask Register .........488
15.6.38 USB_HCx_TSIZ - Host Channel x Transfer Size Register ...........489
15.6.39 USB_HCx_DMAADDR - Host Channel x DMA Address Register ........490
15.6.40 USB_DCFG - Device Configuration Register ...............491
15.6.41 USB_DCTL - Device Control Register .................493
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15.6.42 USB_DSTS - Device Status Register ..................495
15.6.43 USB_DIEPMSK - Device IN Endpoint Common Interrupt Mask Register ......496
15.6.44 USB_DOEPMSK - Device OUT Endpoint Common Interrupt Mask Register ....497
15.6.45 USB_DAINT - Device All Endpoints Interrupt Register ............498
15.6.46 USB_DAINTMSK - Device All Endpoints Interrupt Mask Register ........500
15.6.47 USB_DVBUSDIS - Device VBUS Discharge Time Register ..........501
15.6.48 USB_DVBUSPULSE - Device VBUS Pulsing Time Register ..........502
15.6.49 USB_DIEPEMPMSK - Device IN Endpoint FIFO Empty Interrupt Mask Register ...502
15.6.50 USB_DIEP0CTL - Device IN Endpoint 0 Control Register ...........503
15.6.51 USB_DIEP0INT - Device IN Endpoint 0 Interrupt Register ...........505
15.6.52 USB_DIEP0TSIZ - Device IN Endpoint 0 Transfer Size Register ........507
15.6.53 USB_DIEP0DMAADDR - Device IN Endpoint 0 DMA Address Register ......508
15.6.54 USB_DIEP0TXFSTS - Device IN Endpoint 0 Transmit FIFO Status Register ....508
15.6.55 USB_DIEPx_CTL - Device IN Endpoint x+1 Control Register .........509
15.6.56 USB_DIEPx_INT - Device IN Endpoint x+1 Interrupt Register .........511
15.6.57 USB_DIEPx_TSIZ - Device IN Endpoint x+1 Transfer Size Register .......513
15.6.58 USB_DIEPx_DMAADDR - Device IN Endpoint x+1 DMA Address Register .....514
15.6.59 USB_DIEPx_TXFSTS - Device IN Endpoint x+1 Transmit FIFO Status Register ...514
15.6.60 USB_DOEP0CTL - Device OUT Endpoint 0 Control Register .........515
15.6.61 USB_DOEP0INT - Device OUT Endpoint 0 Interrupt Register .........517
15.6.62 USB_DOEP0TSIZ - Device OUT Endpoint 0 Transfer Size Register .......519
15.6.63 USB_DOEP0DMAADDR - Device OUT Endpoint 0 DMA Address Register .....520
15.6.64 USB_DOEPx_CTL - Device OUT Endpoint x+1 Control Register ........521
15.6.65 USB_DOEPx_INT - Device OUT Endpoint x+1 Interrupt Register ........523
15.6.66 USB_DOEPx_TSIZ - Device OUT Endpoint x+1 Transfer Size Register ......525
15.6.67 USB_DOEPx_DMAADDR - Device OUT Endpoint x+1 DMA Address Register ...526
15.6.68 USB_PCGCCTL - Power and Clock Gating Control Register ..........527
15.6.69 USB_FIFO0Dx - Device EP 0/Host Channel 0 FIFO .............528
15.6.70 USB_FIFO1Dx - Device EP 1/Host Channel 1 FIFO .............528
15.6.71 USB_FIFO2Dx - Device EP 2/Host Channel 2 FIFO .............529
15.6.72 USB_FIFO3Dx - Device EP 3/Host Channel 3 FIFO .............529
15.6.73 USB_FIFO4Dx - Device EP 4/Host Channel 4 FIFO .............530
15.6.74 USB_FIFO5Dx - Device EP 5/Host Channel 5 FIFO .............530
15.6.75 USB_FIFO6Dx - Device EP 6/Host Channel 6 FIFO .............531
15.6.76 USB_FIFO7Dx - Host Channel 7 FIFO .................531
15.6.77 USB_FIFO8Dx - Host Channel 8 FIFO .................532
15.6.78 USB_FIFO9Dx - Host Channel 9 FIFO .................532
15.6.79 USB_FIFO10Dx - Host Channel 10 FIFO ................533
15.6.80 USB_FIFO11Dx - Host Channel 11 FIFO ................533
15.6.81 USB_FIFO12Dx - Host Channel 12 FIFO ................534
15.6.82 USB_FIFO13Dx - Host Channel 13 FIFO ................534
15.6.83 USB_FIFORAMx - Direct Access to Data FIFO RAM for Debugging (2 KB) .....535
16. I2C - Inter-Integrated Circuit Interface .....................536
16.1 Introduction .............................536
16.2 Features ..............................536
16.3 Functional Description .........................537
16.3.1 I2C-Bus Overview .........................538
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16.3.2 Enable and Reset .........................542
16.3.3 Safely Disabling and Changing Slave Configuration..............542
16.3.4 Clock Generation .........................543
16.3.5 Arbitration ............................544
16.3.6 Buffers .............................545
16.3.7 Master Operation .........................545
16.3.8 Bus States ...........................553
16.3.9 Slave Operation ..........................553
16.3.10 Transfer Automation ........................557
16.3.11 Using 10-Bit Addresses .......................558
16.3.12 Error Handling ..........................558
16.3.13 DMA Support ..........................560
16.3.14 Interrupts ...........................560
16.3.15 Wake-Up ...........................560
16.4 Register Map.............................560
16.5 Register Description ..........................561
16.5.1 I2Cn_CTRL - Control Register ....................561
16.5.2 I2Cn_CMD - Command Register ...................564
16.5.3 I2Cn_STATE - State Register .....................565
16.5.4 I2Cn_STATUS - Status Register ....................566
16.5.5 I2Cn_CLKDIV - Clock Division Register .................567
16.5.6 I2Cn_SADDR - Slave Address Register .................567
16.5.7 I2Cn_SADDRMASK - Slave Address Mask Register .............568
16.5.8 I2Cn_RXDATA - Receive Buffer Data Register (Actionable Reads) ........568
16.5.9 I2Cn_RXDATAP - Receive Buffer Data Peek Register ............569
16.5.10 I2Cn_TXDATA - Transmit Buffer Data Register ..............569
16.5.11 I2Cn_IF - Interrupt Flag Register ...................570
16.5.12 I2Cn_IFS - Interrupt Flag Set Register .................572
16.5.13 I2Cn_IFC - Interrupt Flag Clear Register ................574
16.5.14 I2Cn_IEN - Interrupt Enable Register ..................576
16.5.15 I2Cn_ROUTE - I/O Routing Register ..................577
17. USART - Universal Synchronous Asynchronous Receiver/Transmitter ........578
17.1 Introduction .............................578
17.2 Features ..............................579
17.3 Functional Description .........................580
17.3.1 Modes of Operation ........................581
17.3.2 Asynchronous Operation .......................582
17.3.3 Synchronous Operation .......................597
17.3.4 PRS-Triggered Transmissions .....................603
17.3.5 PRS RX Input ..........................604
17.3.6 DMA Support ..........................604
17.3.7 Transmission Delay ........................604
17.3.8 Interrupts ............................605
17.3.9 IrDA Modulator/Demodulator .....................606
17.4 Register Map.............................607
17.5 Register Description ..........................608
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17.5.1 USARTn_CTRL - Control Register ...................608
17.5.2 USARTn_FRAME - USART Frame Format Register .............613
17.5.3 USARTn_TRIGCTRL - USART Trigger Control register ............615
17.5.4 USARTn_CMD - Command Register ..................616
17.5.5 USARTn_STATUS - USART Status Register ...............617
17.5.6 USARTn_CLKDIV - Clock Control Register ................618
17.5.7 USARTn_RXDATAX - RX Buffer Data Extended Register (Actionable Reads) ....619
17.5.8 USARTn_RXDATA - RX Buffer Data Register (Actionable Reads) ........619
17.5.9 USARTn_RXDOUBLEX - RX Buffer Double Data Extended Register (Actionable Reads) 620
17.5.10 USARTn_RXDOUBLE - RX FIFO Double Data Register (Actionable Reads) ....621
17.5.11 USARTn_RXDATAXP - RX Buffer Data Extended Peek Register ........621
17.5.12 USARTn_RXDOUBLEXP - RX Buffer Double Data Extended Peek Register ....622
17.5.13 USARTn_TXDATAX - TX Buffer Data Extended Register ...........623
17.5.14 USARTn_TXDATA - TX Buffer Data Register ...............624
17.5.15 USARTn_TXDOUBLEX - TX Buffer Double Data Extended Register .......625
17.5.16 USARTn_TXDOUBLE - TX Buffer Double Data Register ...........626
17.5.17 USARTn_IF - Interrupt Flag Register ..................627
17.5.18 USARTn_IFS - Interrupt Flag Set Register ................628
17.5.19 USARTn_IFC - Interrupt Flag Clear Register ...............629
17.5.20 USARTn_IEN - Interrupt Enable Register ................630
17.5.21 USARTn_IRCTRL - IrDA Control Register ................631
17.5.22 USARTn_ROUTE - I/O Routing Register ................633
17.5.23 USARTn_INPUT - USART Input Register ................634
17.5.24 USARTn_I2SCTRL - I2S Control Register ................635
18. UART - Universal Asynchronous Receiver/ Transmitter ..............637
18.1 Introduction .............................637
18.2 Features ..............................638
18.3 Functional Description .........................638
18.4 Register Description ..........................638
18.5 Register Map.............................638
19. LEUART - Low Energy Universal Asynchronous Receiver/Transmitter ........639
19.1 Introduction .............................639
19.2 Features ..............................640
19.3 Functional Description .........................641
19.3.1 Frame Format ..........................642
19.3.2 Clock Source ..........................642
19.3.3 Clock Generation .........................643
19.3.4 Data Transmission .........................643
19.3.5 Data Reception ..........................645
19.3.6 Loopback ............................648
19.3.7 Half Duplex Communication .....................648
19.3.8 Transmission Delay ........................649
19.3.9 PRS RX Input ..........................649
19.3.10 DMA Support ..........................649
19.3.11 Pulse Generator / Pulse Extender ...................650
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19.3.12 Register Access .........................650
19.4 Register Map.............................651
19.5 Register Description ..........................652
19.5.1 LEUARTn_CTRL - Control Register (Async Reg) ..............652
19.5.2 LEUARTn_CMD - Command Register (Async Reg) .............655
19.5.3 LEUARTn_STATUS - Status Register ..................656
19.5.4 LEUARTn_CLKDIV - Clock Control Register (Async Reg) ...........657
19.5.5 LEUARTn_STARTFRAME - Start Frame Register (Async Reg) .........657
19.5.6 LEUARTn_SIGFRAME - Signal Frame Register (Async Reg) ..........658
19.5.7 LEUARTn_RXDATAX - Receive Buffer Data Extended Register (Actionable Reads) ..658
19.5.8 LEUARTn_RXDATA - Receive Buffer Data Register (Actionable Reads) ......659
19.5.9 LEUARTn_RXDATAXP - Receive Buffer Data Extended Peek Register ......659
19.5.10 LEUARTn_TXDATAX - Transmit Buffer Data Extended Register (Async Reg) ....660
19.5.11 LEUARTn_TXDATA - Transmit Buffer Data Register (Async Reg) ........661
19.5.12 LEUARTn_IF - Interrupt Flag Register .................662
19.5.13 LEUARTn_IFS - Interrupt Flag Set Register ...............663
19.5.14 LEUARTn_IFC - Interrupt Flag Clear Register ...............664
19.5.15 LEUARTn_IEN - Interrupt Enable Register ................665
19.5.16 LEUARTn_PULSECTRL - Pulse Control Register (Async Reg) .........666
19.5.17 LEUARTn_FREEZE - Freeze Register .................667
19.5.18 LEUARTn_SYNCBUSY - Synchronization Busy Register ...........668
19.5.19 LEUARTn_ROUTE - I/O Routing Register ................669
19.5.20 LEUARTn_INPUT - LEUART Input Register ...............670
20. TIMER - Timer/Counter ..........................671
20.1 Introduction .............................671
20.2 Features ..............................672
20.3 Functional Description .........................673
20.3.1 Counter Modes ..........................673
20.3.2 Compare/Capture Channels .....................679
20.3.3 Dead-Time Insertion Unit (TIMER0 only) .................687
20.3.4 Debug Mode ...........................690
20.3.5 Interrupts, DMA and PRS Output ....................691
20.3.6 GPIO Input/Output .........................691
20.4 Register Map.............................692
20.5 Register Description ..........................693
20.5.1 TIMERn_CTRL - Control Register ...................693
20.5.2 TIMERn_CMD - Command Register ..................695
20.5.3 TIMERn_STATUS - Status Register ..................696
20.5.4 TIMERn_IEN - Interrupt Enable Register .................699
20.5.5 TIMERn_IF - Interrupt Flag Register ..................700
20.5.6 TIMERn_IFS - Interrupt Flag Set Register ................701
20.5.7 TIMERn_IFC - Interrupt Flag Clear Register ................702
20.5.8 TIMERn_TOP - Counter Top Value Register ...............703
20.5.9 TIMERn_TOPB - Counter Top Value Buffer Register .............703
20.5.10 TIMERn_CNT - Counter Value Register .................704
20.5.11 TIMERn_ROUTE - I/O Routing Register .................705
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20.5.12 TIMERn_CCx_CTRL - CC Channel Control Register ............706
20.5.13 TIMERn_CCx_CCV - CC Channel Value Register .............709
20.5.14 TIMERn_CCx_CCVP - CC Channel Value Peek Register ...........709
20.5.15 TIMERn_CCx_CCVB - CC Channel Buffer Register .............710
20.5.16 TIMERn_DTCTRL - DTI Control Register ................711
20.5.17 TIMERn_DTTIME - DTI Time Control Register ..............713
20.5.18 TIMERn_DTFC - DTI Fault Configuration Register .............715
20.5.19 TIMERn_DTOGEN - DTI Output Generation Enable Register .........717
20.5.20 TIMERn_DTFAULT - DTI Fault Register ................718
20.5.21 TIMERn_DTFAULTC - DTI Fault Clear Register ..............719
20.5.22 TIMERn_DTLOCK - DTI Configuration Lock Register ............720
21. RTC - Real Time Counter .........................721
21.1 Introduction .............................721
21.2 Features ..............................721
21.3 Functional Description .........................722
21.3.1 Counter ............................722
21.3.2 Compare Channels ........................723
21.3.3 Interrupts ............................724
21.3.4 DEBUGRUN ...........................724
21.3.5 Using the RTC in EM3 .......................724
21.3.6 Register Access..........................724
21.4 Register Map.............................724
21.5 Register Description ..........................725
21.5.1 RTC_CTRL - Control Register (Async Reg) ................725
21.5.2 RTC_CNT - Counter Value Register ..................726
21.5.3 RTC_COMP0 - Compare Value Register 0 (Async Reg) ............726
21.5.4 RTC_COMP1 - Compare Value Register 1 (Async Reg) ............727
21.5.5 RTC_IF - Interrupt Flag Register ....................727
21.5.6 RTC_IFS - Interrupt Flag Set Register ..................728
21.5.7 RTC_IFC - Interrupt Flag Clear Register .................728
21.5.8 RTC_IEN - Interrupt Enable Register ..................729
21.5.9 RTC_FREEZE - Freeze Register ...................729
21.5.10 RTC_SYNCBUSY - Synchronization Busy Register .............730
22. BURTC - Backup Real Time Counter .....................731
22.1 Introduction .............................731
22.2 Features ..............................731
22.3 Functional Description .........................732
22.3.1 Counter ............................732
22.3.2 Clock Source ..........................732
22.3.3 Compare Channel .........................732
22.3.4 PRS Sources ..........................732
22.3.5 Debug Run ...........................733
22.3.6 Low Power Mode .........................733
22.3.7 Retention Registers ........................733
22.3.8 Backup Operation .........................733
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22.3.9 Backup Mode Timestamp ......................734
22.3.10 LFXO Failure Detection .......................734
22.3.11 Register Access .........................734
22.4 Register Map.............................735
22.5 Register Description ..........................736
22.5.1 BURTC_CTRL - Control Register ...................736
22.5.2 BURTC_LPMODE - Low power mode configuration (Async Reg) .........738
22.5.3 BURTC_CNT - Counter Value Register .................738
22.5.4 BURTC_COMP0 - Counter Compare Value (Async Reg) ...........739
22.5.5 BURTC_TIMESTAMP - Backup mode timestamp ..............739
22.5.6 BURTC_LFXOFDET - LFXO .....................740
22.5.7 BURTC_STATUS - Status Register ...................741
22.5.8 BURTC_CMD - Command Register ..................741
22.5.9 BURTC_POWERDOWN - Retention RAM power-down Register .........742
22.5.10 BURTC_LOCK - Configuration Lock Register ...............742
22.5.11 BURTC_IF - Interrupt Flag Register ..................743
22.5.12 BURTC_IFS - Interrupt Flag Set Register ................743
22.5.13 BURTC_IFC - Interrupt Flag Clear Register ...............744
22.5.14 BURTC_IEN - Interrupt Enable Register .................744
22.5.15 BURTC_FREEZE - Freeze Register ..................745
22.5.16 BURTC_SYNCBUSY - Synchronization Busy Register ............745
22.5.17 RETx_REG - Retention Register ...................746
23. LETIMER - Low Energy Timer ........................747
23.1 Introduction .............................747
23.2 Features ..............................747
23.3 Functional Description .........................748
23.3.1 Timer .............................748
23.3.2 Compare Registers ........................748
23.3.3 Top Value ............................748
23.3.4 Underflow Output Action .......................754
23.3.5 PRS Output ...........................756
23.3.6 Examples ............................756
23.3.7 Using the LETIMER in EM3 ......................758
23.3.8 Register Access..........................758
23.4 Register Map.............................759
23.5 Register Description ..........................760
23.5.1 LETIMERn_CTRL - Control Register (Async Reg) ..............760
23.5.2 LETIMERn_CMD - Command Register .................762
23.5.3 LETIMERn_STATUS - Status Register .................762
23.5.4 LETIMERn_CNT - Counter Value Register ................763
23.5.5 LETIMERn_COMP0 - Compare Value Register 0 (Async Reg) .........763
23.5.6 LETIMERn_COMP1 - Compare Value Register 1 (Async Reg) .........764
23.5.7 LETIMERn_REP0 - Repeat Counter Register 0 (Async Reg) ..........764
23.5.8 LETIMERn_REP1 - Repeat Counter Register 1 (Async Reg) ..........765
23.5.9 LETIMERn_IF - Interrupt Flag Register .................765
23.5.10 LETIMERn_IFS - Interrupt Flag Set Register ...............766
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23.5.11 LETIMERn_IFC - Interrupt Flag Clear Register ..............767
23.5.12 LETIMERn_IEN - Interrupt Enable Register ...............768
23.5.13 LETIMERn_FREEZE - Freeze Register .................769
23.5.14 LETIMERn_SYNCBUSY - Synchronization Busy Register ..........770
23.5.15 LETIMERn_ROUTE - I/O Routing Register ................771
24. PCNT - Pulse Counter ..........................772
24.1 Introduction .............................772
24.2 Features ..............................772
24.3 Functional Description .........................773
24.3.1 Pulse Counter Modes ........................773
24.3.2 Hysteresis ...........................775
24.3.3 Auxiliary Counter .........................775
24.3.4 Register Access..........................776
24.3.5 Clock Sources ..........................776
24.3.6 Input Filter ...........................776
24.3.7 Edge Polarity ..........................776
24.3.8 PRS S0IN and S1IN Input ......................776
24.3.9 Interrupts ............................776
24.4 Register Map.............................778
24.5 Register Description ..........................779
24.5.1 PCNTn_CTRL - Control Register (Async Reg) ...............779
24.5.2 PCNTn_CMD - Command Register (Async Reg) ..............781
24.5.3 PCNTn_STATUS - Status Register ...................781
24.5.4 PCNTn_CNT - Counter Value Register .................782
24.5.5 PCNTn_TOP - Top Value Register ...................782
24.5.6 PCNTn_TOPB - Top Value Buffer Register (Async Reg) ...........783
24.5.7 PCNTn_IF - Interrupt Flag Register ...................783
24.5.8 PCNTn_IFS - Interrupt Flag Set Register .................784
24.5.9 PCNTn_IFC - Interrupt Flag Clear Register ................785
24.5.10 PCNTn_IEN - Interrupt Enable Register .................786
24.5.11 PCNTn_ROUTE - I/O Routing Register .................787
24.5.12 PCNTn_FREEZE - Freeze Register ..................788
24.5.13 PCNTn_SYNCBUSY - Synchronization Busy Register ............788
24.5.14 PCNTn_AUXCNT - Auxiliary Counter Value Register ............789
24.5.15 PCNTn_INPUT - PCNT Input Register .................790
25. LESENSE - Low Energy Sensor Interface ...................792
25.1 Introduction .............................792
25.2 Features ..............................792
25.3 Functional Description .........................793
25.3.1 Channel Configuration .......................794
25.3.2 Scan Sequence ..........................795
25.3.3 Sensor Timing ..........................796
25.3.4 Sensor Interaction .........................797
25.3.5 Sensor Evaluation .........................799
25.3.6 Decoder ............................800
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25.3.7 Measurement Results ........................803
25.3.8 DAC Interface ..........................804
25.3.9 ACMP Interface ..........................804
25.3.10 ACMP and DAC Duty Cycling.....................804
25.3.11 DMA Requests .........................804
25.3.12 PRS Output...........................804
25.3.13 RAM .............................805
25.3.14 Application Examples .......................805
25.4 Register Map.............................810
25.5 Register Description ..........................812
25.5.1 LESENSE_CTRL - Control Register (Async Reg) ..............812
25.5.2 LESENSE_TIMCTRL - Timing Control Register (Async Reg) ..........815
25.5.3 LESENSE_PERCTRL - Peripheral Control Register (Async Reg) .........817
25.5.4 LESENSE_DECCTRL - Decoder control Register (Async Reg) .........820
25.5.5 LESENSE_BIASCTRL - Bias Control Register (Async Reg) ..........823
25.5.6 LESENSE_CMD - Command Register ..................824
25.5.7 LESENSE_CHEN - Channel enable Register (Async Reg) ...........824
25.5.8 LESENSE_SCANRES - Scan result register (Async Reg) ...........825
25.5.9 LESENSE_STATUS - Status Register (Async Reg) .............826
25.5.10 LESENSE_PTR - Result buffer pointers (Async Reg) ............827
25.5.11 LESENSE_BUFDATA - Result buffer data register (Async Reg) (Actionable Reads) ..827
25.5.12 LESENSE_CURCH - Current channel index (Async Reg) ...........828
25.5.13 LESENSE_DECSTATE - Current decoder state (Async Reg) .........828
25.5.14 LESENSE_SENSORSTATE - Decoder input register (Async Reg) ........829
25.5.15 LESENSE_IDLECONF - GPIO Idle phase configuration (Async Reg) .......830
25.5.16 LESENSE_ALTEXCONF - Alternative excite pin configuration (Async Reg) .....834
25.5.17 LESENSE_IF - Interrupt Flag Register .................837
25.5.18 LESENSE_IFC - Interrupt Flag Clear Register ...............839
25.5.19 LESENSE_IFS - Interrupt Flag Set Register ...............841
25.5.20 LESENSE_IEN - Interrupt Enable Register ................843
25.5.21 LESENSE_SYNCBUSY - Synchronization Busy Register ...........845
25.5.22 LESENSE_ROUTE - I/O Routing Register (Async Reg) ...........847
25.5.23 LESENSE_POWERDOWN - LESENSE RAM power-down register (Async Reg) ...848
25.5.24 LESENSE_STx_TCONFA - State transition configuration A (Async Reg) .....849
25.5.25 LESENSE_STx_TCONFB - State transition configuration B (Async Reg) .....851
25.5.26 LESENSE_BUFx_DATA - Scan results (Async Reg) ............852
25.5.27 LESENSE_CHx_TIMING - Scan configuration (Async Reg) ..........853
25.5.28 LESENSE_CHx_INTERACT - Scan configuration (Async Reg) .........854
25.5.29 LESENSE_CHx_EVAL - Scan configuration (Async Reg) ...........856
26. ACMP - Analog Comparator ........................857
26.1 Introduction .............................857
26.2 Features ..............................857
26.3 Functional Description .........................858
26.3.1 Warm-up Time ..........................858
26.3.2 Response Time ..........................859
26.3.3 Hysteresis ...........................860
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26.3.4 Input Selection ..........................860
26.3.5 Capacitive Sense Mode .......................861
26.3.6 Interrupts and PRS Output ......................861
26.3.7 Output to GPIO ..........................861
26.4 Register Map.............................862
26.5 Register Description ..........................863
26.5.1 ACMPn_CTRL - Control Register ...................863
26.5.2 ACMPn_INPUTSEL - Input Selection Register ...............865
26.5.3 ACMPn_STATUS - Status Register ...................867
26.5.4 ACMPn_IEN - Interrupt Enable Register .................867
26.5.5 ACMPn_IF - Interrupt Flag Register ..................868
26.5.6 ACMPn_IFS - Interrupt Flag Set Register .................868
26.5.7 ACMPn_IFC - Interrupt Flag Clear Register ................869
26.5.8 ACMPn_ROUTE - I/O Routing Register .................869
27. VCMP - Voltage Comparator ........................870
27.1 Introduction .............................870
27.2 Features ..............................870
27.3 Functional Description .........................871
27.3.1 Warm-Up Time ..........................871
27.3.2 Response Time ..........................872
27.3.3 Hysteresis ...........................873
27.3.4 Input Selection ..........................873
27.3.5 Interrupts and PRS Output ......................873
27.4 Register Map.............................874
27.5 Register Description ..........................875
27.5.1 VCMP_CTRL - Control Register ....................875
27.5.2 VCMP_INPUTSEL - Input Selection Register ...............876
27.5.3 VCMP_STATUS - Status Register ...................877
27.5.4 VCMP_IEN - Interrupt Enable Register .................877
27.5.5 VCMP_IF - Interrupt Flag Register ...................878
27.5.6 VCMP_IFS - Interrupt Flag Set Register .................878
27.5.7 VCMP_IFC - Interrupt Flag Clear Register ................879
28. ADC - Analog to Digital Converter ......................880
28.1 Introduction .............................880
28.2 Features ..............................881
28.3 Functional Description .........................882
28.3.1 Clock Selection ..........................882
28.3.2 Conversions ...........................883
28.3.3 Warm-Up Time ..........................884
28.3.4 Input Selection ..........................885
28.3.5 Reference Selection ........................886
28.3.6 Programming of Bias Current .....................886
28.3.7 ADC Modes ...........................886
28.3.8 Interrupts, PRS Output .......................890
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28.3.9 DMA Request ..........................890
28.3.10 Calibration ...........................891
28.4 Register Map.............................892
28.5 Register Description ..........................893
28.5.1 ADCn_CTRL - Control Register ....................893
28.5.2 ADCn_CMD - Command Register ...................895
28.5.3 ADCn_STATUS - Status Register ...................896
28.5.4 ADCn_SINGLECTRL - Single Sample Control Register ............898
28.5.5 ADCn_SCANCTRL - Scan Control Register ................902
28.5.6 ADCn_IEN - Interrupt Enable Register ..................905
28.5.7 ADCn_IF - Interrupt Flag Register ...................906
28.5.8 ADCn_IFS - Interrupt Flag Set Register .................907
28.5.9 ADCn_IFC - Interrupt Flag Clear Register ................908
28.5.10 ADCn_SINGLEDATA - Single Conversion Result Data (Actionable Reads) .....908
28.5.11 ADCn_SCANDATA - Scan Conversion Result Data (Actionable Reads) ......909
28.5.12 ADCn_SINGLEDATAP - Single Conversion Result Data Peek Register ......909
28.5.13 ADCn_SCANDATAP - Scan Sequence Result Data Peek Register .......910
28.5.14 ADCn_CAL - Calibration Register ...................911
28.5.15 ADCn_BIASPROG - Bias Programming Register ..............912
29. DAC - Digital to Analog Converter ......................913
29.1 Introduction .............................913
29.2 Features ..............................913
29.3 Functional Description .........................914
29.3.1 Conversions ...........................914
29.3.2 Reference Selection ........................915
29.3.3 Programming of Bias Current .....................915
29.3.4 Mode .............................916
29.3.5 Sine Generation Mode .......................916
29.3.6 Interrupts and PRS Output ......................917
29.3.7 DMA Request ..........................917
29.3.8 Analog Output ..........................917
29.3.9 Calibration ...........................917
29.3.10 Opamps ............................917
29.4 Register Map.............................918
29.5 Register Description ..........................919
29.5.1 DACn_CTRL - Control Register ....................919
29.5.2 DACn_STATUS - Status Register ...................921
29.5.3 DACn_CH0CTRL - Channel 0 Control Register ...............922
29.5.4 DACn_CH1CTRL - Channel 1 Control Register ...............924
29.5.5 DACn_IEN - Interrupt Enable Register ..................925
29.5.6 DACn_IF - Interrupt Flag Register ...................926
29.5.7 DACn_IFS - Interrupt Flag Set Register .................927
29.5.8 DACn_IFC - Interrupt Flag Clear Register ................928
29.5.9 DACn_CH0DATA - Channel 0 Data Register ...............928
29.5.10 DACn_CH1DATA - Channel 1 Data Register ...............929
29.5.11 DACn_COMBDATA - Combined Data Register ..............929
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29.5.12 DACn_CAL - Calibration Register ...................930
29.5.13 DACn_BIASPROG - Bias Programming Register ..............931
29.5.14 DACn_OPACTRL - Operational Amplifier Control Register ..........932
29.5.15 DACn_OPAOFFSET - Operational Amplifier Offset Register ..........933
29.5.16 DACn_OPA0MUX - Operational Amplifier Mux Configuration Register ......934
29.5.17 DACn_OPA1MUX - Operational Amplifier Mux Configuration Register ......937
29.5.18 DACn_OPA2MUX - Operational Amplifier Mux Configuration Register ......940
30. OPAMP - Operational Amplifier .......................942
30.1 Introduction .............................942
30.2 Features ..............................942
30.3 Functional Description .........................943
30.3.1 Opamp Configuration ........................944
30.3.2 Opamp Modes ..........................946
30.3.3 Opamp DAC Combination ......................954
30.4 Register Description ..........................954
30.5 Register Map.............................954
31. AES - Advanced Encryption Standard Accelerator ................955
31.1 Introduction .............................955
31.2 Features ..............................955
31.3 Functional Description .........................956
31.3.1 Encryption/Decryption........................956
31.3.2 Data and Key Access ........................957
31.3.3 Interrupt Request .........................958
31.3.4 DMA Request ..........................958
31.3.5 Block Chaining Example .......................959
31.4 Register Map.............................959
31.5 Register Description ..........................960
31.5.1 AES_CTRL - Control Register ....................960
31.5.2 AES_CMD - Command Register ....................961
31.5.3 AES_STATUS - Status Register ....................961
31.5.4 AES_IEN - Interrupt Enable Register ..................962
31.5.5 AES_IF - Interrupt Flag Register ....................962
31.5.6 AES_IFS - Interrupt Flag Set Register ..................962
31.5.7 AES_IFC - Interrupt Flag Clear Register .................963
31.5.8 AES_DATA - DATA Register (Actionable Reads) ..............963
31.5.9 AES_XORDATA - XORDATA Register (Actionable Reads) ...........964
31.5.10 AES_KEYLA - KEY Low Register (Actionable Reads) ............964
31.5.11 AES_KEYLB - KEY Low Register (Actionable Reads) ............965
31.5.12 AES_KEYLC - KEY Low Register (Actionable Reads) ............965
31.5.13 AES_KEYLD - KEY Low Register (Actionable Reads) ............966
31.5.14 AES_KEYHA - KEY High Register (Actionable Reads) ............966
31.5.15 AES_KEYHB - KEY High Register (Actionable Reads) ............967
31.5.16 AES_KEYHC - KEY High Register (Actionable Reads) ............967
31.5.17 AES_KEYHD - KEY High Register (Actionable Reads) ............968
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32. GPIO - General Purpose Input/Output .....................969
32.1 Introduction .............................969
32.2 Features ..............................970
32.3 Functional Description .........................971
32.3.1 Pin Configuration .........................972
32.3.2 EM4 Wake-Up ..........................975
32.3.3 EM4 Retention ..........................975
32.3.4 Alternate Functions ........................976
32.3.5 Interrupt Generation ........................977
32.3.6 Output to PRS ..........................977
32.3.7 Synchronization ..........................977
32.4 Register Map.............................978
32.5 Register Description ..........................979
32.5.1 GPIO_Px_CTRL - Port Control Register .................979
32.5.2 GPIO_Px_MODEL - Port Pin Mode Low Register ..............980
32.5.3 GPIO_Px_MODEH - Port Pin Mode High Register ..............982
32.5.4 GPIO_Px_DOUT - Port Data Out Register ................983
32.5.5 GPIO_Px_DOUTSET - Port Data Out Set Register .............983
32.5.6 GPIO_Px_DOUTCLR - Port Data Out Clear Register .............984
32.5.7 GPIO_Px_DOUTTGL - Port Data Out Toggle Register ............984
32.5.8 GPIO_Px_DIN - Port Data In Register ..................985
32.5.9 GPIO_Px_PINLOCKN - Port Unlocked Pins Register .............985
32.5.10 GPIO_EXTIPSELL - External Interrupt Port Select Low Register ........986
32.5.11 GPIO_EXTIPSELH - External Interrupt Port Select High Register ........989
32.5.12 GPIO_EXTIRISE - External Interrupt Rising Edge Trigger Register ........992
32.5.13 GPIO_EXTIFALL - External Interrupt Falling Edge Trigger Register .......992
32.5.14 GPIO_IEN - Interrupt Enable Register .................993
32.5.15 GPIO_IF - Interrupt Flag Register ...................993
32.5.16 GPIO_IFS - Interrupt Flag Set Register .................994
32.5.17 GPIO_IFC - Interrupt Flag Clear Register ................994
32.5.18 GPIO_ROUTE - I/O Routing Register .................995
32.5.19 GPIO_INSENSE - Input Sense Register .................996
32.5.20 GPIO_LOCK - Configuration Lock Register ...............997
32.5.21 GPIO_CTRL - GPIO Control Register .................997
32.5.22 GPIO_CMD - GPIO Command Register .................998
32.5.23 GPIO_EM4WUEN - EM4 Wake-up Enable Register .............998
32.5.24 GPIO_EM4WUPOL - EM4 Wake-up Polarity Register ............999
32.5.25 GPIO_EM4WUCAUSE - EM4 Wake-up Cause Register ...........1000
33. LCD - Liquid Crystal Display Driver .....................1001
33.1 Introduction .............................1001
33.2 Features ..............................1001
33.3 Functional Description .........................1002
33.3.1 LCD Driver Enable .........................1002
33.3.2 Multiplexing, Bias, and Wave Settings ..................1003
33.3.3 Waveform Examples ........................1004
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33.3.4 LCD Contrast ..........................1021
33.3.5 VLCD Selection ..........................1022
33.3.6 VBOOST Control .........................1023
33.3.7 Frame Rate ...........................1023
33.3.8 Data Update ...........................1024
33.3.9 Direct Segment Control (DSC) .....................1025
33.3.10 Frame Counter (FC) ........................1026
33.3.11 LCD Interrupt ..........................1027
33.3.12 Blink, Blank, and Animation Features ..................1027
33.3.13 LCD in Low Energy Modes .....................1030
33.3.14 Register Access .........................1030
33.4 Register Map.............................1031
33.5 Register Description ..........................1032
33.5.1 LCD_CTRL - Control Register (Async Reg) ................1032
33.5.2 LCD_DISPCTRL - Display Control Register ................1033
33.5.3 LCD_SEGEN - Segment Enable Register ................1035
33.5.4 LCD_BACTRL - Blink and Animation Control Register (Async Reg) ........1036
33.5.5 LCD_STATUS - Status Register ....................1038
33.5.6 LCD_AREGA - Animation Register A (Async Reg) ..............1038
33.5.7 LCD_AREGB - Animation Register B (Async Reg) ..............1039
33.5.8 LCD_IF - Interrupt Flag Register ....................1039
33.5.9 LCD_IFS - Interrupt Flag Set Register ..................1039
33.5.10 LCD_IFC - Interrupt Flag Clear Register .................1040
33.5.11 LCD_IEN - Interrupt Enable Register ..................1040
33.5.12 LCD_SEGD0L - Segment Data Low Register 0 (Async Reg) ..........1041
33.5.13 LCD_SEGD1L - Segment Data Low Register 1 (Async Reg) ..........1041
33.5.14 LCD_SEGD2L - Segment Data Low Register 2 (Async Reg) ..........1042
33.5.15 LCD_SEGD3L - Segment Data Low Register 3 (Async Reg) ..........1042
33.5.16 LCD_SEGD0H - Segment Data High Register 0 (Async Reg) .........1043
33.5.17 LCD_SEGD1H - Segment Data High Register 1 (Async Reg) .........1043
33.5.18 LCD_SEGD2H - Segment Data High Register 2 (Async Reg) .........1044
33.5.19 LCD_SEGD3H - Segment Data High Register 3 (Async Reg) .........1044
33.5.20 LCD_FREEZE - Freeze Register ...................1045
33.5.21 LCD_SYNCBUSY - Synchronization Busy Register .............1046
33.5.22 LCD_SEGD4H - Segment Data High Register 4 (Async Reg) .........1047
33.5.23 LCD_SEGD5H - Segment Data High Register 5 (Async Reg) .........1048
33.5.24 LCD_SEGD6H - Segment Data High Register 6 (Async Reg) .........1048
33.5.25 LCD_SEGD7H - Segment Data High Register 7 (Async Reg) .........1049
33.5.26 LCD_SEGD4L - Segment Data Low Register 4 (Async Reg) ..........1049
33.5.27 LCD_SEGD5L - Segment Data Low Register 5 (Async Reg) ..........1050
33.5.28 LCD_SEGD6L - Segment Data Low Register 6 (Async Reg) ..........1050
33.5.29 LCD_SEGD7L - Segment Data Low Register 7 (Async Reg) ..........1051
34. FPUEH - Floating Point Unit Exception Handler .................1052
34.1 Functional Description .........................1052
34.2 Register Map.............................1052
34.3 Register Description ..........................1053
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34.3.1 FPUEH_IF - Interrupt Flag Register ...................1053
34.3.2 FPUEH_IFS - Interrupt Flag Set Register .................1054
34.3.3 FPUEH_IFC - Interrupt Flag Clear Register ................1055
34.3.4 FPUEH_IEN - Interrupt Enable Register .................1056
35. Revision History.............................1057
35.1 Revision 1.10 ............................1057
35.2 Revision 1.00 ............................1057
35.3 Revision 0.60 ............................1057
35.4 Revision 0.51 ............................1058
35.5 Revision 0.50 ............................1058
36. Abbreviations..............................1059
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1. Energy Friendly Microcontrollers
1.1 Typical Applications
The EFM32WG Wonder Gecko is the ideal choice for demanding 8-, 16-, and 32-bit energy sensitive applications. These devices are
developed to minimize the energy consumption by lowering both the power and the active time, over all phases of MCU operation. This
unique combination of ultra low energy consumption and the performance of the 32-bit ARM Cortex-M4 processor helps designers get
more out of the available energy in a variety of applications.
Ultra low energy EFM32WG microcontrollers are perfect for:
• Gas metering
• Energy metering
• Water metering
• Smart metering
• Alarm and security systems
• Health and fitness applications
• Industrial and home automation
43210
1.2 EFM32WG Development
Because EFM32WG use the Cortex-M4 CPU, embedded designers benefit from the largest development ecosystem in the industry, the
ARM ecosystem. The development suite spans the whole design process and includes powerful debug tools, and some of the world’s
top brand compilers. Libraries with documentation and user examples shorten time from idea to market.
The range of EFM32WG devices ensure easy migration and feature upgrade possibilities.
EFM32WG Reference Manual
Energy Friendly Microcontrollers
silabs.com | Building a more connected world. Rev. 1.1 | 24
2. About This Document
This document contains reference material for the EFM32WG series of microcontrollers. All modules and peripherals in the EFM32WG
series devices are described in general terms. Not all modules are present in all devices, and the feature set for each device might
vary. Such differences, including pinout, are covered in the device-specific datasheet.
2.1 Conventions
Register Names
Register names are given as a module name prefix followed by the short register name:
TIMERn_CTRL - Control Register
The "n" denotes the numeric instance for modules that might have more than one instance.
Some registers are grouped which leads to a group name following the module prefix:
GPIO_Px_DOUT - Port Data Out Register,
where x denotes the port instance (A,B,...).
Bit Fields
Registers contain one or more bit fields which can be 1 to 32 bits wide. Multi-bit fields are denoted with (x:y), where x is the start bit and
y is the end bit.
Address
The address for each register can be found by adding the base address of the module (found in the Memory Map), and the offset ad-
dress for the register (found in module Register Map).
Access Type
The register access types used in the register descriptions are explained in the table below.
Table 2.1. Register Access Types
Access Type Description
R Read only. Writes are ignored.
RW Readable and writable.
RW1 Readable and writable. Only writes to 1 have effect.
RW1H Readable, writable and updated by hardware. Only writes to 1 have effect.
W1 Read value undefined. Only writes to 1 have effect.
W Write only. Read value undefined.
RWH Readable, writable and updated by hardware.
Number format
0x prefix is used for hexadecimal numbers.
0b prefix is used for binary numbers.
Numbers without prefix are in decimal representation.
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About This Document
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Reserved
Registers and bit fields marked with reserved are reserved for future use. These should be written to 0 unless otherwise stated in the
Register Description. Reserved bits might be read as 1 in future devices.
Reset Value
The reset value denotes the value after reset. Registers denoted with X have an unknown reset value and need to be initialized before
use. Note that, before these registers are initialized, read-modify-write operations might result in undefined register values.
Pin Connections
Pin connections are given as a module prefix followed by a short pin name:
USn_TX (USARTn TX pin)
The pin locations referenced in this document are given in the device-specific datasheet.
2.2 Related Documentation
Further documentation on the EFM32WG family and the ARM Cortex-M4 can be found at the Silicon Laboratories and ARM web pa-
ges:
www.silabs.com
www.arm.com
EFM32WG Reference Manual
About This Document
silabs.com | Building a more connected world. Rev. 1.1 | 26
3. System Overview
3.1 Introduction
The EFM32 MCUs are the world’s most energy friendly microcontrollers. With a unique combination of the powerful 32-bit ARM Cortex-
M4, innovative low energy techniques, short wake-up time from energy saving modes, and a wide selection of peripherals, the
EFM32WG microcontroller is well suited for any battery operated application, as well as other systems requiring high performance and
low-energy consumption. See Figure 3.1 Block Diagram of EFM32WG on page 30 for a block diagram of the EFM32WG device.
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System Overview
silabs.com | Building a more connected world. Rev. 1.1 | 27
3.2 Features
•ARM Cortex-M4 CPU platform
• High Performance 32-bit processor @ up to 48 MHz
• DSP instruction support and floating-point unit
• Memory Protection Unit
• Wake-up Interrupt Controller
•Flexible Energy Management System
• 20 nA @ 3 V Shutoff Mode
• 0.4 µA @ 3 V Shutoff Mode with RTC
• 0.65 µA @ 3 V Stop Mode, including Power-on Reset, Brown-out Detector, RAM and CPU retention
• 0.95 µA @ 3 V Deep Sleep Mode, including RTC with 32.768 kHz oscillator, Power-on Reset, Brown-out Detector, RAM and
CPU retention
• 63 µA/MHz @ 3 V Sleep Mode
• 225 µA/MHz @ 3 V Run Mode, with code executed from flash
•256/128/64 KB Flash
•32 KB RAM
•Up to 93 General Purpose I/O pins
• Configurable push-pull, open-drain, pull-up/down, input filter, drive strength
• Configurable peripheral I/O locations
• 16 asynchronous external interrupts
• Output state retention and wake-up from Shutoff Mode
•12 Channel DMA Controller
• Alternate/primary descriptors with scatter-gather/ping-pong operation
•12 Channel Peripheral Reflex System
• Autonomous inter-peripheral signaling enables smart operation in low energy modes
•External Bus Interface (EBI)
• Up to 4x256 MB of external memory mapped space
• TFT Controller supporting Direct Drive
•Universal Serial Bus (USB) with Host and OTG support
• Fully USB 2.0 compliant
• On-chip PHY and embedded 5V to 3.3V regulator
•Integrated LCD Controller for up to 8×36 Segments
• Voltage boost, adjustable contrast adjustment and autonomous animation feature
•Hardware AES with 128/256-bit Keys in 54/75 cycles
•Communication Interfaces
• 3× Universal Synchronous/Asynchronous Receiver/Transmitter
• UART/SPI/SmartCard (ISO 7816)/IrDA (USART0)/I2S (USART1+USART2)
• Triple buffered full/half-duplex operation
• 4-16 data bits
• 2× Universal Asynchronous Receiver/Transmitter
• Triple buffered full/half-duplex operation
• 8-9 data bits
• 2× Low Energy UART
• Autonomous operation with DMA in Deep Sleep Mode
•2× I2C Interface with SMBus support
• Address recognition in Stop Mode
•Timers/Counters
• 4×16-bit Timer/Counter
• 3 Compare/Capture/PWM channels
• Dead-Time Insertion on TIMER0
• 16-bit Low Energy Timer
• 1× 24-bit and 1× 32-bit Real-Time Counter
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System Overview
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• 3× 16-bit Pulse Counter
• Asynchronous pulse counting/quadrature decoding
• Watchdog Timer with dedicated RC oscillator @ 50 nA
•Backup Power Domain
• RTC and retention registers in a separate power domain, available in all energy modes
• Operation from backup battery when main power drains out
•Ultra Low Power Precision Analog Peripherals
• 12-bit 1 Msamples/s Analog to Digital Converter
• 8 input channels and on-chip temperature sensor
• Single ended or differential operation
• Conversion tailgating for predictable latency
• 12-bit 500 ksamples/s Digital to Analog Converter
• 2 single ended channels/1 differential channel
• Up to 3 Operational Amplifiers
• Supports rail-to-rail inputs and outputs
• Programmable gain
• 2× Analog Comparator
• Programmable speed/current
• Capacitive sensing with up to 8 inputs
• Supply Voltage Comparator
•Ultra Low Power Sensor Interface
• Autonomous sensor monitoring in Deep Sleep Mode
• Wide range of sensors supported, including LC sensors and capacitive buttons
•Ultra Efficient Power-on Reset and Brown-Out Detector
•Debug Interface
• 2-pin Serial Wire Debug interface
• 1-pin Serial Wire Viewer
• Embedded Trace Module v3.5 (ETM)
• Temperature range -40 - 85°C
• Single power supply 1.98 - 3.8 V
•Packages
• QFN64
• TQFP64
• LQFP100
• LFBGA112
• VFBGA120
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System Overview
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Voltage
Comparator
Brown-Out
Belem, Powers" Reset
Backup Damam
3.3 Block Diagram
Figure 3.1 Block Diagram of EFM32WG on page 30 shows the block diagram of EFM32WG. The color indicates peripheral availability
in the different energy modes, described in 3.4 Energy Modes .
32-bit bus
Lowest power mode with peripheral operational:
EM2 – Deep Sleep
EM1 - Sleep EM4S - Shutoff
EM0 - Active EM3 - Stop
Core / Memory
Flash Program
Memory
RAM Memory
ARM CortexTM
M4 processor
with FPU and
MPU
Debug Interface
with ETM
DMA Controller
Memory
Protection Unit
Other
Hardware AES
Energy Management
Brown-Out
Detector
Voltage
Regulator
Voltage
Comparator
Power-On Reset
Clock Management
High Frequency
RC Oscillator
Ultra Low Freq.
RC Oscillator
Low Frequency
Crystal Oscillator
Low Frequency
RC Oscillator
Auxiliary High
Freq. RC Osc.
High Frequency
Crystal Oscillator
Analog Interfaces
LCD Controller
Operational
Amplifier
ADC
DAC
Analog
Comparator
Backup Domain
Peripheral Reflex System
Serial Interfaces
UART
I2C
USB
I/O Ports Timers and Triggers
LESENSE
Timer/Counter
Low Energy Timer
Watchdog Timer
Back-Up RTC
External
Interrupts
Pin Reset
External Bus
Interface
General
Purpose I/O
Pin Wakeup
TFT Driver
Pulse Counter
Real Time Counter
USART
Low Energy
UARTTM
Figure 3.1. Block Diagram of EFM32WG
43210
Figure 3.2. Energy Mode Indicator
Note: In the energy mode indicator, the numbers indicates Energy Mode, i.e EM0-EM4.
3.4 Energy Modes
There are five different Energy Modes (EM0-EM4) in the EFM32WG, see Table 3.1 Energy Mode Description on page 31 . The
EFM32WG is designed to achieve a high degree of autonomous operation in low energy modes. The intelligent combination of periph-
erals, RAM with data retention, DMA, low-power oscillators, and short wake-up time, makes it attractive to remain in low energy modes
for long periods and thus saving energy consumption.
Note: Throughout this document, the first figure in every module description contains an Energy Mode Indicator showing which energy
mode(s) the module can operate.
EFM32WG Reference Manual
System Overview
silabs.com | Building a more connected world. Rev. 1.1 | 30
@@@@@
Table 3.1. Energy Mode Description
Energy Mode Name Description
43210EM0 - Energy Mode 0 (Run mode)
In EM0, the CPU is running and consuming
as little as 225 µA/MHz, when running code
from flash. All peripherals can be active.
43210 EM1 - Energy Mode 1 (Sleep Mode)
In EM1, the CPU is sleeping and the power
consumption is only 63 µA/MHz. All periph-
erals, including DMA, PRS and memory
system, are still available.
43210
EM2 - Energy Mode 2 (Deep Sleep Mode)
In EM2 the high frequency oscillator is
turned off, but with the 32.768 kHz oscilla-
tor running, selected low energy peripher-
als (LCD, RTC, LETIMER, PCNT,
LEUART, I2C, LESENSE, OPAMP, USB,
WDOG and ACMP) are still available. This
gives a high degree of autonomous opera-
tion with a current consumption as low as
0.95 µA with RTC enabled. Power-on Re-
set, Brownout Detection and full RAM and
CPU retention is also included.
43210 EM3 - Energy Mode 3 (Stop Mode)
In EM3, the low-frequency oscillator is disa-
bled, but there is still full CPU and RAM re-
tention, as well as Power-on Reset, Pin re-
set, EM4 wake-up and Brown-out Detec-
tion, with a consumption of only 0.65 µA.
The low-power ACMP, asynchronous exter-
nal interrupt, PCNT, and I2C can wake-up
the device. Even in this mode, the wake-up
time is a few microseconds.
43210 EM4 - Energy Mode 4 (Shutoff Mode)
In EM4, the current is down to 20 nA and
all chip functionality is turned off except the
pin reset, GPIO pin wake-up, GPIO pin re-
tention, Backup RTC (including retention
RAM) and the Power-On Reset. All pins are
put into their reset state.
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System Overview
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3.5 Product Overview
The following table shows a device overview of the EFM32WG Microcontroller Series, including peripheral functionality. For more infor-
mation, the reader is referred to the device specific datasheets.
Table 3.2. EFM32WG Microcontroller Series
EFM32WG Part #
Flash
RAM
GPIO(pins)
USB
LCD
USART+UART
LEUART
I2C
Timer(PWM)
LETIMER
RTC
PCNT
Watchdog
ADC(pins)
DAC(pins)
ACMP(pins)
AES
EBI
LESENSE
Op—Amps
Package
230F64 64 32 56 — — 3 2 2 4
(12)
1 1 3 1 1
(8)
2
(2)
2
(16)
Y — Y 3 QFN64
230F128 128 32 56 — — 3 2 2 4
(12)
1 1 3 1 1
(8)
2
(2)
2
(16)
Y — Y 3 QFN64
230F256 256 32 56 — — 3 2 2 4
(12)
1 1 3 1 1
(8)
2
(2)
2
(16)
Y — Y 3 QFN64
232F64 64 32 53 — — 3 2 2 4
(11)
1 1 3 1 1
(8)
2
(2)
2
(16)
Y — Y 3 QFP64
232F128 128 32 53 — — 3 2 2 4
(11)
1 1 3 1 1
(8)
2
(2)
2
(16)
Y — Y 3 QFP64
232F256 256 32 53 — — 3 2 2 4
(11)
1 1 3 1 1
(8)
2
(2)
2
(16)
Y — Y 3 QFP64
280F64 64 32 86 — — 3+2 2 2 4
(12)
1 1 3 1 1
(8)
2
(2)
2
(16)
Y Y Y 3 QFP100
280F128 128 32 86 — — 3+2 2 2 4
(12)
1 1 3 1 1
(8)
2
(2)
2
(16)
Y Y Y 3 QFP100
280F256 256 32 86 — — 3+2 2 2 4
(12)
1 1 3 1 1
(8)
2
(2)
2
(16)
Y Y Y 3 QFP100
290F64 64 32 90 — — 3+2 2 2 4
(12)
1 1 3 1 1
(8)
2
(2)
2
(16)
Y Y Y 3 BGA112
290F128 128 32 90 — — 3+2 2 2 4
(12)
1 1 3 1 1
(8)
2
(2)
2
(16)
Y Y Y 3 BGA112
290F256 256 32 90 — — 3+2 2 2 4
(12)
1 1 3 1 1
(8)
2
(2)
2
(16)
Y Y Y 3 BGA112
295F64 64 32 93 — — 3+2 2 2 4
(12)
1 1 3 1 1
(8)
2
(2)
2
(16)
Y Y Y 3 BGA120
295F128 128 32 93 — — 3+2 2 2 4
(12)
1 1 3 1 1
(8)
2
(2)
2
(16)
Y Y Y 3 BGA120
295F256 256 32 93 — — 3+2 2 2 4
(12)
1 1 3 1 1
(8)
2
(2)
2
(16)
Y Y Y 3 BGA120
330F64 64 32 53 Y — 3 2 2 4
(12)
1 1 3 1 1
(8)
2
(2)
2
(12)
Y — Y 3 QFN64
330F128 128 32 53 Y — 3 2 2 4
(12)
1 1 3 1 1
(8)
2
(2)
2
(12)
Y — Y 3 QFN64
330F256 256 32 53 Y — 3 2 2 4
(12)
1 1 3 1 1
(8)
2
(2)
2
(12)
Y — Y 3 QFN64
EFM32WG Reference Manual
System Overview
silabs.com | Building a more connected world. Rev. 1.1 | 32
EFM32WG Part #
Flash
RAM
GPIO(pins)
USB
LCD
USART+UART
LEUART
I2C
Timer(PWM)
LETIMER
RTC
PCNT
Watchdog
ADC(pins)
DAC(pins)
ACMP(pins)
AES
EBI
LESENSE
Op—Amps
Package
332F64 64 32 50 Y — 3 2 2 4
(11)
1 1 3 1 1
(8)
2
(2)
2
(12)
Y — Y 3 QFP64
332F128 128 32 50 Y — 3 2 2 4
(11)
1 1 3 1 1
(8)
2
(2)
2
(12)
Y — Y 3 QFP64
332F256 256 32 50 Y — 3 2 2 4
(11)
1 1 3 1 1
(8)
2
(2)
2
(12)
Y — Y 3 QFP64
380F64 64 32 83 Y — 3+2 2 2 4
(12)
1 1 3 1 1
(8)
2
(2)
2
(12)
Y Y Y 3 QFP100
380F128 128 32 83 Y — 3+2 2 2 4
(12)
1 1 3 1 1
(8)
2
(2)
2
(12)
Y Y Y 3 QFP100
380F256 256 32 83 Y — 3+2 2 2 4
(12)
1 1 3 1 1
(8)
2
(2)
2
(12)
Y Y Y 3 QFP100
390F64 64 32 87 Y — 3+2 2 2 4
(12)
1 1 3 1 1
(8)
2
(2)
2
(12)
Y Y Y 3 BGA112
390F128 128 32 87 Y — 3+2 2 2 4
(12)
1 1 3 1 1
(8)
2
(2)
2
(12)
Y Y Y 3 BGA112
390F256 256 32 87 Y — 3+2 2 2 4
(12)
1 1 3 1 1
(8)
2
(2)
2
(12)
Y Y Y 3 BGA112
395F64 64 32 93 Y — 3+2 2 2 4
(12)
1 1 3 1 1
(8)
2
(2)
2
(16)
Y Y Y 3 BGA120
395F128 128 32 93 Y — 3+2 2 2 4
(12)
1 1 3 1 1
(8)
2
(2)
2
(16)
Y Y Y 3 BGA120
395F256 256 32 93 Y — 3+2 2 2 4
(12)
1 1 3 1 1
(8)
2
(2)
2
(16)
Y Y Y 3 BGA120
840F64 64 32 56 — 8x20 3 2 2 4
(12)
1 1 3 1 1
(8)
2
(2)
2
(8)
Y — Y 3 QFN64
840F128 128 32 56 — 8x20 3 2 2 4
(12)
1 1 3 1 1
(8)
2
(2)
2
(8)
Y — Y 3 QFN64
840F256 256 32 56 — 8x20 3 2 2 4
(12)
1 1 3 1 1
(8)
2
(2)
2
(8)
Y — Y 3 QFN64
842F64 64 32 53 — 8x18 3 2 2 4
(11)
1 1 3 1 1
(8)
2
(2)
2
(8)
Y — Y 3 QFP64
842F128 128 32 53 — 8x18 3 2 2 4
(11)
1 1 3 1 1
(8)
2
(2)
2
(8)
Y — Y 3 QFP64
842F256 256 32 53 — 8x18 3 2 2 4
(11)
1 1 3 1 1
(8)
2
(2)
2
(8)
Y — Y 3 QFP64
880F64 64 32 86 — 8x36 3+2 2 2 4
(12)
1 1 3 1 1
(8)
2
(2)
2
(16)
YY1Y 3 QFP100
880F128 128 32 86 — 8x36 3+2 2 2 4
(12)
1 1 3 1 1
(8)
2
(2)
2
(16)
YY1Y 3 QFP100
880F256 256 32 86 — 8x36 3+2 2 2 4
(12)
1 1 3 1 1
(8)
2
(2)
2
(16)
YY1Y 3 QFP100
EFM32WG Reference Manual
System Overview
silabs.com | Building a more connected world. Rev. 1.1 | 33
EFM32WG Part #
Flash
RAM
GPIO(pins)
USB
LCD
USART+UART
LEUART
I2C
Timer(PWM)
LETIMER
RTC
PCNT
Watchdog
ADC(pins)
DAC(pins)
ACMP(pins)
AES
EBI
LESENSE
Op—Amps
Package
890F64 64 32 90 — 8x36 3+2 2 2 4
(12)
1 1 3 1 1
(8)
2
(2)
2
(16)
YY1Y 3 BGA112
890F128 128 32 90 — 8x36 3+2 2 2 4
(12)
1 1 3 1 1
(8)
2
(2)
2
(16)
YY1Y 3 BGA112
890F256 256 32 90 — 8x36 3+2 2 2 4
(12)
1 1 3 1 1
(8)
2
(2)
2
(16)
YY1Y 3 BGA112
895F64 64 32 93 — 8x36 3+2 2 2 4
(12)
1 1 3 1 1
(8)
2
(2)
2
(16)
YY1Y 3 BGA120
895F128 128 32 93 — 8x36 3+2 2 2 4
(12)
1 1 3 1 1
(8)
2
(2)
2
(16)
YY1Y 3 BGA120
895F256 256 32 93 — 8x36 3+2 2 2 4
(12)
1 1 3 1 1
(8)
2
(2)
2
(16)
YY1Y 3 BGA120
940F64 64 32 53 Y 8x18 3 2 2 4
(12)
1 1 3 1 1
(8)
2
(2)
1
(4)
Y — Y 3 QFN64
940F128 128 32 53 Y 8x18 3 2 2 4
(12)
1 1 3 1 1
(8)
2
(2)
1
(4)
Y — Y 3 QFN64
940F256 256 32 53 Y 8x18 3 2 2 4
(12)
1 1 3 1 1
(8)
2
(2)
1
(4)
Y — Y 3 QFN64
942F64 64 32 50 Y 8x16 3 2 2 4
(11)
1 1 3 1 1
(8)
2
(2)
1
(4)
Y — Y 3 QFP64
942F128 128 32 50 Y 8x16 3 2 2 4
(11)
1 1 3 1 1
(8)
2
(2)
1
(4)
Y — Y 3 QFP64
942F256 256 32 50 Y 8x16 3 2 2 4
(11)
1 1 3 1 1
(8)
2
(2)
1
(4)
Y — Y 3 QFP64
980F64 64 32 83 Y 8x34 3+2 2 2 4
(12)
1 1 3 1 1
(8)
2
(2)
2
(12)
YY1Y 3 LQFP100
980F128 128 32 83 Y 8x34 3+2 2 2 4
(12)
1 1 3 1 1
(8)
2
(2)
2
(12)
YY1Y 3 LQFP100
980F256 256 32 83 Y 8x34 3+2 2 2 4
(12)
1 1 3 1 1
(8)
2
(2)
2
(12)
YY1Y 3 LQFP100
990F64 64 32 87 Y 8x34 3+2 2 2 4
(12)
1 1 3 1 1
(8)
2
(2)
2
(12)
YY1Y 3 LFBGA112
990F128 128 32 87 Y 8x34 3+2 2 2 4
(12)
1 1 3 1 1
(8)
2
(2)
2
(12)
YY1Y 3 LFBGA112
990F256 256 32 87 Y 8x34 3+2 2 2 4
(12)
1 1 3 1 1
(8)
2
(2)
2
(12)
YY1Y 3 LFBGA112
995F64 64 32 93 Y 8x36 3+2 2 2 4
(12)
1 1 3 1 1
(8)
2
(2)
2
(16)
YY1Y 3 VFBGA120
995F128 128 32 93 Y 8x36 3+2 2 2 4
(12)
1 1 3 1 1
(8)
2
(2)
2
(16)
YY1Y 3 VFBGA120
995F256 256 32 93 Y 8x36 3+2 2 2 4
(12)
1 1 3 1 1
(8)
2
(2)
2
(16)
YY1Y 3 VFBGA120
EFM32WG Reference Manual
System Overview
silabs.com | Building a more connected world. Rev. 1.1 | 34
EFM32WG Part #
Flash
RAM
GPIO(pins)
USB
LCD
USART+UART
LEUART
I2C
Timer(PWM)
LETIMER
RTC
PCNT
Watchdog
ADC(pins)
DAC(pins)
ACMP(pins)
AES
EBI
LESENSE
Op—Amps
Package
Note:
1. EBI and LCD share pins in the part. Only a reduced pin count LCD driver can be used simultaneously with the EBI.
3.6 Device Revision
The device revision number is read from the ROM Table. The major revision number and the chip family number is read from PID0 and
PID1 registers. The minor revision number is extracted from the PID2 and PID3 registers, as illustrated in Figure 3.3 Revision Number
Extraction on page 35. The Fam[5:2] and Fam[1:0] must be combined to complete the chip family number, while the Minor Rev[7:4]
and Minor Rev[3:0] must be combined to form the complete revision number.
PID3 (0xE00FFFEC)
Minor Rev[3:0]
31:8 7:4 3:0
PID2 (0xE00FFFE8)
Minor Rev[7:4]
31:8 7:4 3:0
PID1 (0xE00FFFE4)
31:4
PID0 (0xE00FFFE0)
Fam[1:0]
31:8 7:6 5:0
Major Rev[5:0] Fam[5:2]
3:0
Figure 3.3. Revision Number Extraction
For the latest revision of the Wonder Gecko family, the chip family number is 0x03 and the major revision number is 0x01. The minor
revision number is to be interpreted according to the table below.
Table 3.3. Minor Revision Number Interpretation
Minor Rev[7:0] Revision
0x00 A
EFM32WG Reference Manual
System Overview
silabs.com | Building a more connected world. Rev. 1.1 | 35
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4. System Processor
43210
CM4 Core
32-bit ALU
Control Logic DSP extensions
Instruction
Interface Data Interface
NVIC Interface
Single cycle
32-bit multiplier
Hardware divider
Memory Protection Unit
Floating-Point Unit Thumb & Thumb-2
Decode
Quick Facts
What?
The industry leading Cortex-M4 processor from
ARM is the CPU in the EFM32WG microcontrollers.
Why?
The ARM Cortex-M4 is designed for exceptional
short response time, high code density, and high 32-
bit throughput while maintaining a strict cost and
power consumption budget.
How?
Combined with the ultra low energy peripherals
available, the Cortex-M4 with Floating-Point Unit
(FPU) makes the EFM32WG devices perfect for 8-
to 32- bit applications. The processor is featuring a
Harvard architecture, 3 stage pipeline, single cycle
instructions, extended Thumb-2 instruction set sup-
port, and fast interrupt handling.
4.1 Introduction
The ARM Cortex-M4 32-bit RISC processor provides outstanding computational performance and exceptional system response to inter-
rupts while meeting low cost requirements and low power consumption.
The ARM Cortex-M4 implemented is revision r0p1.
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System Processor
silabs.com | Building a more connected world. Rev. 1.1 | 36
4.2 Features
• Digital Signal Processor
• Enhances speed and reduces the active time with dedicated DSP instructions
• Harvard Architecture
• Separate data and program memory buses (No memory bottleneck as for a single-bus system)
• 3-stage pipeline
• Thumb-2 instruction set
• Enhanced levels of performance, energy efficiency, and code density
• Single-Precision Floating-Point Unit
• Enables embedded system designers to take full advantage of floating-points
• Extends the instruction set with 28 floating-point instructions
• Single-cycle multiply and efficient divide instructions
• 32-bit multiplication in a single cycle
• Signed and unsigned divide operations between 2 and 12 cycles
• Atomic bit manipulation with bit banding
• Direct access to single bits of data
• Two 1MB bit banding regions for memory and peripherals mapping to 32MB alias regions
• Atomic operation which cannot be interrupted by other bus activities
• 1.25 DMIPS/MHz
• Memory Protection Unit
• Up to 8 protected memory regions
• 24-bit System Tick Timer for Real-Time Operating System (RTOS)
• Excellent 32-bit migration choice for 8/16 bit architecture based designs
• Simplified stack-based programmer's model is compatible with traditional ARM architecture and retains the programming simplici-
ty of legacy 8- and 16-bit architectures
• Unaligned data storage and access
• Continuous storage of data requiring different byte lengths
• Data access in a single core clock cycle
• Integrated power modes
• Sleep Now mode for immediate transfer to low power state
• Sleep on Exit mode for entry into low power state after the servicing of an interrupt
• Ability to extend power savings to other system components
• Optimized for low latency, nested interrupts
4.3 Functional Description
For a full functional description of the ARM Cortex-M4 (r0p1) implementation in the EFM32WG family, the reader is referred to the ARM
Cortex-M4 Devices Generic User Guide.
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System Processor
silabs.com | Building a more connected world. Rev. 1.1 | 37
4.3.1 Interrupt Operation
Module Cortex-M4 NVIC
IEN[n]
IF[n]
set clear
IFS[n] IFC[n]
Interrupt
condition
IRQ
SETENA[n]/CLRENA[n]
Interrupt
request
SETPEND[n]/CLRPEND[n]
set clear
Active interrupt
Software generated interrupt
Figure 4.1. Interrupt Operation
The EFM32WG devices have up to 40 interrupt request lines (IRQ) which are connected to the Cortex-M4. Each of these lines are
connected to one or more interrupt flags in one or more modules. The interrupt flags are set by hardware on an interrupt condition. It is
also possible to set/clear the interrupt flags through the IFS/IFC registers. Each interrupt flag is then qualified with its own interrupt ena-
ble bit (IEN register), before being OR'ed with the other interrupt flags to generate the IRQ. A high IRQ line will set the corresponding
pending bit (can also be set/cleared with the SETPEND/CLRPEND bits in ISPR0/ICPR0) in the Cortex-M4 NVIC. The pending bit is
then qualified with an enable bit (set/cleared with SETENA/CLRENA bits in ISER0/ICER0) before generating an interrupt request to the
core. The previous figure illustrates the interrupt system. For more information on how the interrupts are handled inside the Cortex-M4,
the reader is referred to the ARM Cortex-M4 Devices Generic User Guide.
Table 4.1. Interrupt Request Lines (IRQ)
IRQ# Source
0 DMA
1 GPIO_EVEN
2 TIMER0
3 USART0_RX
4 USART0_TX
5 USB
6 ACMP0/ACMP1
7 ADC0
8 DAC0
9 I2C0
10 I2C1
11 GPIO_ODD
12 TIMER1
13 TIMER2
14 TIMER3
15 USART1_RX
16 USART1_TX
17 LESENSE
18 USART2_RX
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IRQ# Source
19 USART2_TX
20 UART0_RX
21 UART0_TX
22 UART1_RX
23 UART1_TX
24 LEUART0
25 LEUART1
26 LETIMER0
27 PCNT0
28 PCNT1
29 PCNT2
30 RTC
31 BURTC
32 CMU
33 VCMP
34 LCD
35 MSC
36 AES
37 EBI
38 EMU
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System Processor
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5. Memory and Bus System
43210
ARM Cortex-M4
DMA Controller
RAM
Peripherals
Flash
EBI
Quick Facts
What?
A low latency memory system, including low energy
flash and RAM with data retention, makes extended
use of low-power energy-modes possible.
Why?
RAM retention reduces the need for storing data in
flash and enables frequent use of the ultra low ener-
gy modes EM2 and EM3 with as little as 0.65 µA
current consumption.
How?
Low energy and non-volatile flash memory stores
program and application data in all energy modes
and can easily be reprogrammed in system. Low
leakage RAM, with data retention in EM0 to EM3, re-
moves the data restore time penalty, and the DMA
ensures fast autonomous transfers with predictable
response time.
EFM32WG Reference Manual
Memory and Bus System
silabs.com | Building a more connected world. Rev. 1.1 | 40
5.1 Introduction
The EFM32WG contains an AMBA AHB Bus system allowing bus masters to access the memory mapped address space. A multilayer
AHB bus matrix, using a Round-robin arbitration scheme, connects the master bus interfaces to the AHB slaves (refer to the following
figure). The bus matrix allows several AHB slaves to be accessed simultaneously. An AMBA APB interface is used for the peripherals,
which are accessed through an AHB-to-APB bridge connected to the AHB bus matrix. The AHB bus masters are:
•Cortex-M4 ICode: Used for instruction fetches from Code memory (0x00000000 - 0x1FFFFFFF).
•Cortex-M4 DCode: Used for debug and data access to Code memory (0x00000000 - 0x1FFFFFFF).
•Cortex-M4 System: Used for instruction fetches, data and debug access to system space (0x20000000 - 0xDFFFFFFF).
•DMA: Can access EBI, SRAM, Flash and peripherals (0x00000000 - 0xDFFFFFFF).
•USB DMA: Can access EBI, SRAM and Flash (0x80000000 - 0xDFFFFFFF, 0x00000000 - 0x3FFFFFFF), and the AHB-peripherals:
USB and AES.
Cortex
AHB Multilayer
Bus Matrix
DCode
System
USB DMA
Flash
RAM
EBI
AHB/APB
Bridge
ICode
AES
Peripheral 0
Peripheral n
DMA
USB
Figure 5.1. EFM32WG Bus System
EFM32WG Reference Manual
Memory and Bus System
silabs.com | Building a more connected world. Rev. 1.1 | 41
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5.2 Functional Description
The memory segments are mapped together with the internal segments of the Cortex-M4 into the system memory map shown by the
following figures.
Figure 5.2. System Address Space with Core and Code Space Listing
EFM32WG Reference Manual
Memory and Bus System
silabs.com | Building a more connected world. Rev. 1.1 | 42
0x40020400
0x40020000
0x400(:400
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0x4009<000 axavaoaaoo="" axauaoaaao="" 0x40003000="" uxanauaana="" oononeaoa="" ox400u7000="" oxadousodg="" 0x40004400="" nxauauaana="" 0x40002400="" uxananzunu="" 0x40002300="" oxaoouxaoo="" oxadodjooo="" 0x40000400="" nxauauunua="" nxfffffffe="" uxnuluuuuu="" exeeevvvtv="" cw="" permhera‘s="" uxcuuuuuuu="" exavvvvvvv="" uxauuuuuuu="" exavvvvvvv="" em="" regmn="" z="" uxscuuuuuu="" oxsuvvvvvv="" te‘="" regmn="" 2="" uxssuuuuuu="" oxsvvvvvvv="" hm="" ramon="" 1="" uxsduuuuuu="" oxssvvvvvv="" em="" rfigmn="" o="" uxeuuuuuuu="" 9x7vvvvvvv="" axoouuuuuu="" 9x43777777="" vermherd‘s="" (hxlrhand)="" uxdzuuuuuu="" exalvvvvvv="" uxoluuuuuu="" 0x40777777="" penunerax,="" uxduuuuuuu="" exavvvvvvv="" uxzzouuuuu="" exzzavvvvv="" sum="" (hxtrhand)="" uxzzuuuuuu="" axznvvvvvv="" 0x20005000="" exzeee7vvv="" sum="" (32="" kb)="" (dam="" swam="" uxzuuuuuuu="" 9x111!!!”="" uxuuuuuuuu="">Figure 5.3. System Address Space with Peripheral Listing
The embedded SRAM is located at address 0x20000000 in the memory map of the EFM32WG. When running code located in SRAM
starting at this address, the Cortex-M4 uses the System bus to fetch instructions. This results in reduced performance as the Cortex-M4
accesses stack, other data in SRAM and peripherals using the System bus. To be able to run code from SRAM efficiently, the SRAM is
also mapped in the code space at address 0x10000000. When running code from this space, the Cortex-M4 fetches instructions
through the I/D-Code bus interface, leaving the System bus for data access. The SRAM mapped into the code space can however only
be accessed by the CPU, i.e. not the DMA.
5.2.1 Bit-Banding
The SRAM bit-band alias and peripheral bit-band alias regions are located at 0x22000000 and 0x42000000 respectively. Read and
write operations to these regions are converted into masked single-bit reads and atomic single-bit writes to the embedded SRAM and
peripherals of the EFM32WG.
The standard approach to modify a single register or SRAM bit in the aliased regions, requires software to read the value of the byte,
half-word or word containing the bit, modify the bit, and then write the byte, half-word or word back to the register or SRAM address.
Using bit-banding, this read-modify-write can be done in a single atomic operation. As read-writeback, bit-masking and bit-shift opera-
tions are not necessary in software, code size is reduced and execution speed improved.
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To set or clear a memory SRAM bit:
bit_address = 0x22000000 + (address – 0x20000000) × 32 + bit × 4
where address is the address of the 32-bit word containing the bit to modify, and bit is the index of the bit in the 32-bit word.
To modify a bit in the Peripheral area, use the following address:
bit_address = 0x42000000 + (address – 0x40000000) × 32 + bit × 4
where address and bit are defined as above.
Note that the AHB-peripherals USB and AES does not support bit-banding.
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5.2.2 Peripherals
The peripherals are mapped into the peripheral memory segment, each with a fixed size address range.
Table 5.1. Memory System Core Peripherals
Core Peripherals
Address Range Peripheral
0x400E0400 – 0x41FFFFFF Reserved
0x400E0000 – 0x400E03FF AES
0x400CC400 – 0x400DFFFF Reserved
0x400CC000 – 0x400CC3FF PRS
0x400CA400 – 0x400CBFFF Reserved
0x400CA000 – 0x400CA3FF RMU
0x400C8400 – 0x400C9FFF Reserved
0x400C8000 – 0x400C83FF CMU
0x400C6400 – 0x400C7FFF Reserved
0x400C6000 – 0x400C63FF EMU
0x400C4400 – 0x400C5FFF Reserved
0x400C4000 – 0x400C43FF USB
0x400C2000 – 0x400C3FFF DMA
0x400C1C00 – 0x400C1FFF FPUEH
0x400C0400 – 0x400C1BFF Reserved
0x400C0000 – 0x400C03FF MSC
Table 5.2. Memory System Low Energy Peripherals
Low Energy Peripherals
Address Range Peripheral
0x4008C400 – 0x400BFFFF Reserved
0x4008C000 – 0x4008C3FF LESENSE
0x4008A400 – 0x4008BFFF Reserved
0x4008A000 – 0x4008A3FF LCD
0x40088400 – 0x40089FFF Reserved
0x40088000 – 0x400883FF WDOG
0x40086C00 – 0x40087FFF Reserved
0x40086800 – 0x40086BFF PCNT2
0x40086400 – 0x400867FF PCNT1
0x40086000 – 0x400863FF PCNT0
0x40084800 – 0x40085FFF Reserved
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Memory and Bus System
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Low Energy Peripherals
Address Range Peripheral
0x40084400 – 0x400847FF LEUART1
0x40084000 – 0x400843FF LEUART0
0x40082400 – 0x40083FFF Reserved
0x40082000 – 0x400823FF LETIMER0
0x40081400 – 0x40081FFF Reserved
0x40081000 – 0x400813FF BCKRTC
0x40080400 – 0x40080FFF Reserved
0x40080000 – 0x400803FF RTC
Table 5.3. Memory System Peripherals
Peripherals
Address Range Peripheral
0x40011000 – 0x4007FFFF Reserved
0x40010C00 – 0x40010FFF TIMER3
0x40010800 – 0x40010BFF TIMER2
0x40010400 – 0x400107FF TIMER1
0x40010000 – 0x400103FF TIMER0
0x4000E800 – 0x4000FFFF Reserved
0x4000E400 – 0x4000E7FF UART1
0x4000E000 – 0x4000E3FF UART0
0x4000CC00 – 0x4000DFFF Reserved
0x4000C800 – 0x4000CBFF USART2
0x4000C400 – 0x4000C7FF USART1
0x4000C000 – 0x4000C3FF USART0
0x4000A800 – 0x4000BFFF Reserved
0x4000A400 – 0x4000A7FF I2C1
0x4000A000 – 0x4000A3FF I2C0
0x40008400 – 0x40009FFF Reserved
0x40008000 – 0x400083FF EBI
0x40007000 – 0x40007FFF Reserved
0x40006000 – 0x40006FFF GPIO
0x40004400 – 0x40005FFF Reserved
0x40004000 – 0x400043FF DAC0
0x40002400 – 0x40003FFF Reserved
0x40002000 – 0x400023FF ADC0
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Peripherals
Address Range Peripheral
0x40001800 – 0x40001FFF Reserved
0x40001400 – 0x400017FF ACMP1
0x40001000 – 0x400013FF ACMP0
0x40000400 – 0x40000FFF Reserved
0x40000000 - 0x400003FF VCMP
5.2.3 Bus Matrix
The Bus Matrix connects the memory segments to the bus masters:
• Code—CPU instruction or data fetches from the code space
• System—CPU read and write to the SRAM, EBI and peripherals
• DMA—Access to EBI, SRAM, Flash and peripherals
• USB DMA—Access to EBI, SRAM and Flash
5.2.3.1 Arbitration
The Bus Matrix uses a round-robin arbitration algorithm which enables high throughput and low latency while starvation of simultaneous
accesses to the same bus slave are eliminated. Round-robin does not assign a fixed priority to each bus master. The arbiter does not
insert any bus wait-states.
5.2.3.2 Access Performance
The Bus Matrix is a multi-layer energy optimized AMBA AHB compliant bus with an internal bandwidth equal to 4 times a single AHB-
bus.
The Bus Matrix accepts new transfers initiated by each master in every clock cycle without inserting any wait-states. The slaves, how-
ever, may insert wait-states depending on their internal throughput and the clock frequency.
The Cortex-M4, the DMA Controller, and the peripherals run on clocks that can be prescaled separately. When accessing a peripheral
which runs on a frequency equal to or faster than the HFCORECLK, the number of wait cycles per access, in addition to master arbitra-
tion, is given by:
Ncycles = 2 + Nslave cycles
where Nslave cycles is the wait cycles introduced by the slave.
When accessing a peripheral running on a clock slower than the HFCORECLK, wait-cycles are introduced to allow the transfer to com-
plete on the peripheral clock. The number of wait cycles per access, in addition to master arbitration, is given by:
Ncycles =
(
2 + Nslave cycles
)
×
fHFCORECLK
fHFPERCLK
where Nslave cycles is the number of wait cycles introduced by the slave.
For general register access, Nslave cycles = 1.
More details on clocks and prescaling can be found in 11. CMU - Clock Management Unit.
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5.2.4 Access to Low Energy Peripherals (Asynchronous Registers)
5.2.4.1 Introduction
The Low Energy Peripherals are capable of running when the high frequency oscillator and core system is powered off, i.e. in energy
mode EM2 and in some cases also EM3. This enables the peripherals to perform tasks while the system energy consumption is mini-
mal.
The Low Energy Peripherals are:
• Liquid Crystal Display driver - LCD
• Low Energy Timer - LETIMER
• Low Energy UART - LEUART
• Pulse Counter - PCNT
• Real Time Counter - RTC
• Watchdog - WDOG
• Low Energy Sensor Interface - LESENSE
• Backup RTC - BURTC
All Low Energy Peripherals are memory mapped, with automatic data synchronization. Because the Low Energy Peripherals are run-
ning on clocks asynchronous to the core clock, there are some constraints on how register accesses can be done, as described in the
following sections.
5.2.4.1.1 Writing
Every Low Energy Peripheral has one or more registers with data that needs to be synchronized into the Low Energy clock domain to
maintain data consistency and predictable operation. There are two different synchronization mechanisms on the Wonder Gecko; im-
mediate synchronization, and delayed synchronization. Immediate synchronization is available for the RTC, LETIMER and LESENSE,
and results in an immediate update of the target registers. Delayed synchronization is used for the other Low Energy Peripherals, and
for these peripherals, a write operation requires 3 positive edges on the clock of the Low Energy Peripheral being accessed. Registers
requiring synchronization are marked "Asynchronous" in their description header.
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5.2.4.1.1.1 Delayed Synchronization
After writing data to a register which value is to be synchronized into the Low Energy Peripheral using delayed synchronization, a corre-
sponding busy flag in the <module_name>_SYNCBUSY register (e.g. LEUART_SYNCBUSY) is set. This flag is set as long as synchro-
nization is in progress and is cleared upon completion.
Note:
Subsequent writes to the same register before the corresponding busy flag is cleared is not supported. Write before the busy flag is
cleared may result in undefined behavior.
In general, the SYNCBUSY register only needs to be observed if there is a risk of multiple write access to a register (which must be
prevented). It is not required to wait until the relevant flag in the SYNCBUSY register is cleared after writing a register. E.g EM2 can be
entered immediately after writing a register.
See the following figure for a more detailed overview of the write operation.
Register 0
Register 1
.
.
.
Register n
Synchronizer 0
Synchronizer 1
.
.
.
Synchronizer n
Register 0 Sync
Register 1 Sync
.
.
.
Register n Sync
Write[0:n]
Syncbusy Register 0
Syncbusy Register 1
.
.
.
Syncbusy Register n
Set 0
Set 1
Set n
Freeze
Synchronization Done
Clear 0
Clear 1
Clear n
Core Clock Low Frequency Clock Low Frequency Clock
Core Clock Domain Low Frequency Clock Domain
Figure 5.4. Write Operation to Low Energy Peripherals
5.2.4.1.1.2 Immediate Synchronization
Contrary to the peripherals with delayed synchronization, data written to peripherals with immediate synchronization, takes effect in the
peripheral immediately. They are updated immediately on the peripheral write access. If a write is set up close to a peripheral clock
edge, the write is delayed to after the clock edge. This will introduce wait-states on peripheral access. In the worst case, there can be
three wait-state cycles of the HFCORECLK_LE and an additional wait-state equivalent of up to 315 ns.
For peripherals with immediate synchronization, the SYNCBUSY registers are still present and serve two purposes: (1) commands writ-
ten to a peripheral with immediate synchronization are not executed before the first peripheral clock after the write. During this period,
the SYNCBUSY flag in the command register is set, indicating that the command has not yet been executed; (2) to maintain backwards
compatibility with the EFM32G series, SYNCBUSY registers are also present for other registers. These are however, always 0, indicat-
ing that register writes are always safe.
Note: If the application must be compatible with the EFM32G series, all Low Energy Peripherals should be accessed as if they only had
delayed synchronization, i.e. using SYNCBUSY.
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5.2.4.1.2 Reading
When reading from Low Energy Peripherals, the data is synchronized regardless of the originating clock domain. Registers updated/
maintained by the Low Energy Peripheral are read directly from the Low Energy clock domain. Registers residing in the core clock do-
main, are read from the core clock domain. See the following figure for a more detailed overview of the read operation.
Note: Writing a register and then immediately reading back the value of the register may give the impression that the write operation is
complete. This is not necessarily the case. Please refer to the SYNCBUSY register for correct status of the write operation to the Low
Energy Peripheral.
Register 0
Register 1
.
.
.
Register n
Synchronizer 0
Synchronizer 1
.
.
.
Synchronizer n
Register 0 Sync
Register 1 Sync
.
.
.
Register n Sync
Freeze
Core Clock Low Frequency Clock Low Frequency Clock
Core Clock Domain Low Frequency Clock Domain
Low Energy
Peripheral
Main
Function
HW Status Register 0
HW Status Register 1
.
.
.
HW Status Register m
Read
Synchronizer
Read Data
Figure 5.5. Read Operation from Low Energy Peripherals
5.2.4.2 FREEZE Register
For Low Energy Peripherals with delayed synchronization there is a <module_name>_FREEZE register (e.g. RTC_FREEZE), contain-
ing a bit named REGFREEZE. If precise control of the synchronization process is required, this bit may be utilized. When REGFREEZE
is set, the synchronization process is halted, allowing the software to write multiple Low Energy registers before starting the synchroni-
zation process, thus providing precise control of the module update process. The synchronization process is started by clearing the
REGFREEZE bit.
Note: The FREEZE register is also present on peripherals with immediate synchronization, but has no effect.
5.2.5 Flash
The Flash retains data in any state and typically stores the application code, special user data and security information. The Flash
memory is typically programmed through the debug interface, but can also be erased and written to from software.
• Up to 256 kB of memory
• Page size of 2048 bytes (minimum erase unit)
• Minimum 20,000 erase cycles
• More than 10 years data retention at 85 °C
• Lock-bits for memory protection
• Data retention in any state
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5.2.6 SRAM
The primary task of the SRAM memory is to store application data. Additionally, it is possible to execute instructions from SRAM, and
the DMA may used to transfer data between the SRAM, Flash and peripherals.
• Up to 32 kB memory
• Bit-band access support
• Data retention of the entire memory in EM0 to EM3
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5.2.7 Device Information (DI) Page
The DI page contains calibration values, a unique identification number and other useful data. See the table below for a complete over-
view.
Table 5.4. Device Information Page Contents
DI Address Register Description
0x0FE08020 CMU_LFRCOCTRL Register reset value.
0x0FE08028 CMU_HFRCOCTRL Register reset value.
0x0FE08030 CMU_AUXHFRCOCTRL Register reset value.
0x0FE08040 ADC0_CAL Register reset value.
0x0FE08048 ADC0_BIASPROG Register reset value.
0x0FE08050 DAC0_CAL Register reset value.
0x0FE08058 DAC0_BIASPROG Register reset value.
0x0FE08060 ACMP0_CTRL Register reset value.
0x0FE08068 ACMP1_CTRL Register reset value.
0x0FE08068 ACMP1_CTRL Register reset value.
0x0FE08078 CMU_LCDCTRL Register reset value.
0x0FE080A0 DAC0_OPACTRL Register reset value.
0x0FE080A8 DAC0_OPAOFFSET Register reset value.
0x0FE080B0 EMU_BUINACT Register reset value.
0x0FE080B8 EMU_BUACT Register reset value.
0x0FE080C0 EMU_BUBODBUVINCAL Register reset value.
0x0FE080C8 EMU_BUBODUNREGCAL Register reset value.
0x0FE081B0 DI_CRC [15:0]: DI data CRC-16.
0x0FE081B2 CAL_TEMP_0 [7:0] Calibration temperature (°C).
0x0FE081B4 ADC0_CAL_1V25 [14:8]: Gain for 1V25 reference, [6:0]: Offset for 1V25 reference.
0x0FE081B6 ADC0_CAL_2V5 14:8]: Gain for 2V5 reference, [6:0]: Offset for 2V5 reference.
0x0FE081B8 ADC0_CAL_VDD 14:8]: Gain for VDD reference, [6:0]: Offset for VDD reference.
0x0FE081BA ADC0_CAL_5VDIFF 14:8]: Gain for 5VDIFF reference, [6:0]: Offset for 5VDIFF refer-
ence.
0x0FE081BC ADC0_CAL_2XVDD [14:8]: Reserved (gain for this reference cannot be calibrated),
[6:0]: Offset for 2XVDD reference.
0x0FE081BE ADC0_TEMP_0_READ_1V25 [15:4] Temperature reading at 1V25 reference, [3:0] Reserved.
0x0FE081C8 DAC0_CAL_1V25 22:16]: Gain for 1V25 reference, [13:8]: Channel 1 offset for 1V25
reference, [5:0]: Channel 0 offset for 1V25 reference.
0x0FE081CC DAC0_CAL_2V5 22:16]: Gain for 2V5 reference, [13:8]: Channel 1 offset for 2V5
reference, [5:0]: Channel 0 offset for 2V5 reference.
0x0FE081D0 DAC0_CAL_VDD [22:16]: Reserved (gain for this reference cannot be calibrated),
[13:8]: Channel 1 offset for VDD reference, [5:0]: Channel 0 offset
for VDD reference.
0x0FE081D4 AUXHFRCO_CALIB_BAND_1 [7:0]: Tuning for the 1.2 MHZ AUXHFRCO band.
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DI Address Register Description
0x0FE081D5 AUXHFRCO_CALIB_BAND_7 [7:0]: Tuning for the 6.6 MHZ AUXHFRCO band.
0x0FE081D6 AUXHFRCO_CALIB_BAND_11 7:0]: Tuning for the 11 MHZ AUXHFRCO band.
0x0FE081D7 AUXHFRCO_CALIB_BAND_14 [7:0]: Tuning for the 14 MHZ AUXHFRCO band.
0x0FE081D8 AUXHFRCO_CALIB_BAND_21 [7:0]: Tuning for the 21 MHZ AUXHFRCO band.
0x0FE081D9 AUXHFRCO_CALIB_BAND_28 [7:0]: Tuning for the 28 MHZ AUXHFRCO band.
0x0FE081DC HFRCO_CALIB_BAND_1 [7:0]: Tuning for the 1.2 MHZ HFRCO band.
0x0FE081DD HFRCO_CALIB_BAND_7 [7:0]: Tuning for the 6.6 MHZ HFRCO band.
0x0FE081DE HFRCO_CALIB_BAND_11 [7:0]: Tuning for the 11 MHZ HFRCO band.
0x0FE081DF HFRCO_CALIB_BAND_14 [7:0]: Tuning for the 14 MHZ HFRCO band.
0x0FE081E0 HFRCO_CALIB_BAND_21 [7:0]: Tuning for the 21 MHZ HFRCO band.
0x0FE081E1 HFRCO_CALIB_BAND_28 [7:0]: Tuning for the 28 MHZ HFRCO band.
0x0FE081E7 MEM_INFO_PAGE_SIZE [7:0] Flash page size in bytes coded as 2 ^ ((MEM_IN-
FO_PAGE_SIZE + 10) & 0xFF). Ie. the value 0xFF = 512 bytes.
0x0FE081F0 UNIQUE_0 [31:0] Unique number.
0x0FE081F4 UNIQUE_1 [63:32] Unique number.
0x0FE081F8 MEM_INFO_FLASH [15:0]: Flash size, kbyte count as unsigned integer (eg. 128).
0x0FE081FA MEM_INFO_RAM [15:0]: Ram size, kbyte count as unsigned integer (eg. 16).
0x0FE081FC PART_NUMBER [15:0]: EFM32 part number as unsigned integer (eg. 230).
0x0FE081FE PART_FAMILY [7:0]: EFM32 part family number (Gecko = 71, Giant Gecko = 72,
Tiny Gecko = 73, Leopard Gecko=74, Wonder Gecko=75).
0x0FE081FF PROD_REV [7:0]: EFM32 Production ID.
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3333333333
flflflflflflflflflfl
UUUUUUUUUU
CECCCCCCCC
6. DBG - Debug Interface
43210
ARM Cortex-M4
DBG Debug Data
Quick Facts
What?
The DBG (Debug Interface) is used to program and
debug EFM32WG devices.
Why?
The Debug Interface makes it easy to reprogram
and update the system in the field, and allows de-
bugging with minimal I/O pin usage.
How?
The Cortex-M4 supports advanced debugging fea-
tures. EFM32WG devices only use two port pins for
debugging or programming. The internal and exter-
nal state of the system can be examined with debug
extensions supporting instruction or data access
break- and watch points.
6.1 Introduction
The EFM32WG devices include hardware debug support through a 2-pin serial-wire debug (SWD) interface and an Embedded Trace
Module (ETM) for data/instruction tracing. In addition, there is also a Serial Wire Viewer pin which can be used to output profiling infor-
mation, data trace, and software generated messages.
For more technical information about the debug interface the reader is referred to:
• ARM Cortex-M4 Technical Reference Manual
• ARM CoreSight Components Technical Reference Manual
• ARM Debug Interface v5 Architecture Specification
6.2 Features
• Flash Patch and Breakpoint (FPB) unit
• Implement breakpoints and code patches
• Data Watch point and Trace (DWT) unit
• Implement watch points, trigger resources and system profiling
• Instrumentation Trace Macrocell (ITM)
• Application-driven trace source that supports printf style debugging
• Embedded Trace Macrocell v3.5 (ETM)
• Real time instruction and data trace information of the processor
6.3 Functional Description
There are three debug pins and four trace pins available on the device. Operation of these pins are described in the following section.
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6.3.1 Debug Pins
The following pins are the debug connections for the device:
• Serial Wire Clock input (SWCLK): This pin is enabled after reset and has a built-in pull down.
• Serial Wire Data Input/Output (SWDIO): This pin is enabled after reset and has a built-in pull-up.
• Serial Wire Viewer (SWV): This pin is disabled after reset.
The debug pins can be enabled and disabled through GPIO_ROUTE, see 32.3.4.1 Serial Wire Debug Port Connection. Please reme-
berer that upon disabling, debug contact with the device is lost. Also note that, because the debug pins have pull-down and pull-up
enabled by default, leaving them enabled might increase the current consumption with up to 200 µA if left connected to supply or
ground.
6.3.2 Embedded Trace Macrocell v3.5 (ETM)
The ETM makes it possible to trace both instruction and data from the processor in real time. The trace can be controlled through a set
of triggering and filtering resources. The resources include 4 address comparators, 2 data value comparators, 2 counters, a context ID
comparator and a sequencer. Before enabling the ETM, the AUXHFRCO clock needs to be enabled by setting AUXHFRCOEN in
CMU_OSCENCMD. The trace can be exported through a set of trace pins, which include:
• Trace Clock (TCLK): Functions as a sample clock for the trace. This pin is disabled after reset.
• Trace Data 0 - Trace Data 3 (TD0-TD3): The data pins provide the compressed trace stream. These pins are disabled after reset.
For information on how to configure the ETM, see the ARM Embedded Trace Macrocell Architecture Specification. The Trace Clock
and Trace Data pins can be enabled through the GPIO. For more information on how to enable the ETM Trace pins, the reader is refer-
red to 32.3.4.2 ETM Trace Ports.
6.3.3 Debug and EM2/EM3
Leaving the debugger connected when issuing a WFI or WFE to enter EM2 or EM3 will make the system enter a special EM2. This
mode differs from regular EM2 and EM3 in that the high frequency clocks are still enabled, and certain core functionality is still powered
in order to maintain debug-functionality. Because of this, the current consumption in this mode is closer to EM1 and it is therefore im-
portant to disconnect the debugger before doing current consumption measurements.
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6.3.4 Debug Lock and Device Erase
The debug access to the Cortex-M4 is locked by clearing the Debug Lock Word (DLW) and resetting the device, see 7.3.2 Lock Bits
(LB) Page Description.
When debug access is locked, the debug interface remains accessible but the connection to the Cortex- M4 core and the whole bus-
system is blocked as shown in Figure 6.2 Device Unlock on page 56. This mechanism is controlled by the Authentication Access Port
(AAP) as illustrated by Figure 6.1 AAP - Authentication Access Port on page 56. The AAP is only accessible from a debugger and not
from the core.
SW-DP AHB-AP
Cortex
SerialWire
debug
interface
DEVICEERASE
Authentication
Access Port
(AAP)
ERASEBUSY
DLW[3:0] == 0xF
Figure 6.1. AAP - Authentication Access Port
The debugger can access the AAP-registers, and only these registers just after reset, for the time of the AAP-window outlined in the
following figure. If the device is locked, access to the core and bus-system is blocked even after code execution starts, and the debug-
ger can only access the AAP-registers. If the device is not locked, the AAP is no longer accessible after code execution starts, and the
debugger can access the core and bus-system normally. The AAP window can be extended by issuing the bit pattern on SWDIO/
SWCLK as shown in Figure 6.3 AAP Expansion on page 576.3.4 Debug Lock and Device Erase. This pattern should be applied just
before reset is deasserted, and will give the debugger more time to access the AAP.
Unlocked Cortex
Extended
unlocked Extended AAP
Locked No access AAP
Program
execution
Reset
150 us
47 us
No access AAP
Cortex
255 x 47 us
No access
Program
execution
Program
execution
Figure 6.2. Device Unlock
If the device is locked, it can be unlocked by writing a valid key to the AAP_CMDKEY register and then setting the DEVICEERASE bit
of the AAP_CMD register via the debug interface. The commands are not executed before AAP_CMDKEY is invalidated, so this regis-
ter should be cleared to to start the erase operation. This operation erases the main block of flash, all lock bits are reset and debug
access through the AHB-AP is enabled. The operation takes 125 ms to complete. Note that the SRAM contents will also be deleted
during a device erase, while the UD-page is not erased.
Even if the device is not locked, the device can be erased through the AAP, using the above procedure during the AAP window. This
can be useful if the device has been programmed with code that, e.g., disables the debug interface pins on start-up, or does something
else that prevents communication with a debugger.
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SWDIO
SWCLK
AAP expand
Figure 6.3. AAP Expansion
If the device is locked, the debugger may read the status from the AAP_STATUS register. When the ERASEBUSY bit is set low after
DEVICEERASE of the AAP_CMD register is set, the debugger may set the SYSRESETREQ bit in the AAP_CMD register. After reset,
the debugger may resume a normal debug session through the AHB-AP. If the device is not locked, the device erase starts when the
AAP window closes, so it is not possible to poll the status.
6.4 Register Map
The offset register address is relative to the registers base address.
Offset Name Type Description
0x000 AAP_CMD W1 Command Register
0x004 AAP_CMDKEY W1 Command Key Register
0x008 AAP_STATUS RStatus Register
0x0FC AAP_IDR RAAP Identification Register
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6.5 Register Description
6.5.1 AAP_CMD - Command Register
Offset Bit Position
0x000
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
16
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
Reset
0
0
Access
W1
W1
Name
SYSRESETREQ
DEVICEERASE
Bit Name Reset Access Description
31:2 Reserved To ensure compatibility with future devices, always write bits to 0. More information in 2.1 Conven-
tions.
1 SYSRESETREQ 0 W1 System Reset Request
A system reset request is generated when set to 1. This register is write enabled from the AAP_CMDKEY register.
0 DEVICEERASE 0 W1 Erase the Flash Main Block, SRAM and Lock Bits
When set, all data and program code in the main block is erased, the SRAM is cleared and then the Lock Bit (LB) page is
erased. This also includes the Debug Lock Word (DLW), causing debug access to be enabled after the next reset. The
information block User Data page (UD) is left unchanged, but the User data page Lock Word (ULW) is erased. This register
is write enabled from the AAP_CMDKEY register.
6.5.2 AAP_CMDKEY - Command Key Register
Offset Bit Position
0x004
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
16
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
Reset
0x00000000
Access
W1
Name
WRITEKEY
Bit Name Reset Access Description
31:0 WRITEKEY 0x00000000 W1 CMD Key Register
The key value must be written to this register to write enable the AAP_CMD register. After AAP_CMD is written, this regis-
ter should be cleared to excecute the command.
Value Mode Description
0xCFACC118 WRITEEN Enable write to AAP_CMD
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6.5.3 AAP_STATUS - Status Register
Offset Bit Position
0x008
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
16
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
Reset
0
Access
R
Name
ERASEBUSY
Bit Name Reset Access Description
31:1 Reserved To ensure compatibility with future devices, always write bits to 0. More information in 2.1 Conven-
tions.
0 ERASEBUSY 0 R Device Erase Command Status
This bit is set when a device erase is executing.
6.5.4 AAP_IDR - AAP Identification Register
Offset Bit Position
0x0FC
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
16
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
Reset
0x16E60001
Access
R
Name
ID
Bit Name Reset Access Description
31:0 ID 0x16E60001 R AAP Identification Register
Access port identification register in compliance with the ARM ADI v5 specification (JEDEC Manufacturer ID).
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7. MSC - Memory System Controller
43210
01000101011011100110010101110010
01100111011110010010000001001101
01101001011000110111001001101111
00100000011100100111010101101100
01100101011100110010000001110100
01101000011001010010000001110111
01101111011100100110110001100100
00100000011011110110011000100000
01101100011011110111011100101101
01100101011011100110010101110010
01100111011110010010000001101101
01101001011000110111001001101111
01100011011011110110111001110100
01110010011011110110110001101100
01100101011100100010000001100100
01100101011100110110100101100111
01101110001000010100010101101110
Quick Facts
What?
The user can perform Flash memory read, read con-
figuration and write operations through the Memory
System Controller (MSC).
Why?
The MSC allows the application code, user data and
flash lock bits to be stored in non-volatile Flash
memory. Certain memory system functions, such as
program memory wait-states and bus faults are also
configured from the MSC peripheral register inter-
face, giving the developer the ability to dynamically
customize the memory system performance, securi-
ty level, energy consumption and error handling ca-
pabilities to the requirements at hand.
How?
The MSC integrates a low-energy Flash IP with a
charge pump, enabling minimum energy consump-
tion while eliminating the need for external program-
ming voltage to erase the memory. An easy to use
write and erase interface is supported by an internal,
fixed-frequency oscillator and autonomous flash tim-
ing and control reduces software complexity while
not using other timer resources.
Application code may dynamically scale between
high energy optimization and high code execution
performance through advanced read modes.
A highly efficient low energy instruction cache re-
duces the number of flash reads significantly, thus
saving energy. Performance is also improved when
wait states are used, since many of the wait-states
are eliminated. Built-in performance counters can be
used to measure the efficiency of the instruction
cache.
7.1 Introduction
The Memory System Controller (MSC) is the program memory unit of the EFM32WG microcontroller. The flash memory is readable and
writable from both the Cortex-M4 and DMA. The flash memory is divided into two blocks; the main block and the information block.
Program code is normally written to the main block. Additionally, the information block is available for special user data and flash lock
bits. There is also a read-only page in the information block containing system and device calibration data. Read and write operations
are supported in the energy modes EM0 and EM1.
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7.2 Features
• AHB read interface
• Scalable access performance to optimize the Cortex-M4 code interface
• Zero wait-state access up to 16 MHz and one wait-state for up to 32 MHz and two wait-states for up to 48 MHz
• Advanced energy optimization functionality
• Conditional branch target prefetch suppression
• Cortex-M4 disfolding of if-then (IT) blocks
• Instruction Cache
• DMA read support in EM0 and EM1
• Command and status interface
• Flash write and erase
• Accessible from Cortex-M4 in EM0
• DMA write support in EM0 and EM1
• Core clock independent Flash timing
• Internal oscillator and internal timers for precise and autonomous Flash timing
• General purpose timers are not occupied during Flash erase and write operations
• Configurable interrupt erase abort
• Improved interrupt predictability
• Memory and bus fault control
• Security features
• Lockable debug access
• Page lock bits
• SW Mass erase Lock bits
• User data lock bits
• End-of-write and end-of-erase interrupts
7.3 Functional Description
The size of the main block is device dependent. The largest size available is 256 kB (128 pages). The information block has 2048 bytes
available for user data. The information block also contains chip configuration data located in a reserved area. The main block is map-
ped to address 0x00000000 and the information block is mapped to address 0x0FE00000. The table below outlines how the Flash is
mapped in the memory space. All Flash memory is organized into 2048 byte pages.
Block Page Base address Write/Erase by Software readable Purpose/Name Size
Main10 0x00000000 Software, debug Yes User code and data 64 kB – 256 kB
— Software, debug Yes
127 0x0003F800 Software, debug Yes
Reserved — 0x00040000 — — Reserved for flash expansion ~24 MB
Information 0 0x0FE00000 Software, debug Yes User Data (UD) 2 kB
— 0x0FE00800 — — Reserved —
1 0x0FE04000 Write: Software, debug Yes Lock Bits (LB) 2 kB
Erase: Debug only
— 0x0FE04800 — — Reserved —
2 0x0FE08000 — Yes Device Information (DI) 2 kB
— 0x0FE08800 — — Reserved —
Reserved — 0x0FE10000 — — Reserved for flash expansion Rest of code space
Note:
1. Block/page erased by a device erase.
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7.3.1 User Data (UD) Page Description
This is the user data page in the information block. The page can be erased and written by software. The page is erased by the ERA-
SEPAGE command of the MSC_WRITECMD register. Note that the page is not erased by a device erase operation. The device erase
operation is described in 6.3.4 Debug Lock and Device Erase.
7.3.2 Lock Bits (LB) Page Description
This page contains the following information:
• Debug Lock Word (DLW)
• User data page Lock Word (ULW)
• Mass erase Lock Word (MLW)
• Main block Page Lock Words (PLWs)
The words in this page are organized as shown in the table below:
Table 7.1. Lock Bits Page Structure
Word Index Description
127 DLW
126 ULW
125 MLW
N PLW[N]
… …
1 PLW[1]
0 PLW[0]
Word 127 is the debug lock word (DLW). The four LSBs of this word are the debug lock bits. If these bits are 0xF, then debug access is
enabled. If the bits are not 0xF, then debug access to the core is locked. See 6.3.4 Debug Lock and Device Erase for details on how to
unlock the debug access.
Word 126 is the user page lock word (ULW). Bit 0 of this word is the User Data Page lock bit. Bit 1 in this word locks the Lock Bits
Page.
Word 125 is the mass erase lock word (MLW). Bit 0 locks the entire flash. The mass erase lock bits will not have any effect on device
erases initiated from the Authentication Access Port (AAP) registers. The AAP is described in more detail in 6.3.4 Debug Lock and
Device Erase.
There are 32 page lock bits per page lock word (PLW). Bit 0 refers to the first page and bit 31 refers to the last page within a PLW.
Thus, PLW[0] contains lock bits for page 0-31 in the main block. Similarly, PLW[1] contains lock bits for page 32-63 and so on. A page
is locked when the bit is 0. A locked page cannot be erased or written.
The lock bits can be reset by a device erase operation initiated from the Authentication Access Port (AAP) registers. The AAP is descri-
bed in more detail in 6.3.4 Debug Lock and Device Erase. Note that the AAP is only accessible from the debug interface, and cannot be
accessed from the Cortex-M4 core.
7.3.3 Device Information (DI) Page
This read-only page holds the calibration data for the oscillator and other analog peripherals from the production test as well as a
unique device ID. The page is further described in 5.2.5 Flash.
7.3.4 Post-Reset Behavior
Calibration values are automatically written to registers by the MSC before application code startup. The values are also available to
read from the DI page for later reference by software. Other information such as the device ID and production date is also stored in the
DI page and is readable from software.
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7.3.4.1 One Wait-State Access
After reset, the HFCORECLK is normally 14 MHz from the HFRCO and the MODE field of the MSC_READCTRL register is set to WS1
(one wait-state). The reset value must be WS1 as an uncalibrated HFRCO may produce a frequency higher than 16 MHz. Software
must not select a zero wait-state mode unless the clock is guaranteed to be 16 MHz or below, otherwise the resulting behavior is unde-
fined. If a HFCORECLK frequency above 16 MHz is to be set by software, the MODE field of the MSC_READCTRL register must be
set to WS1 or WS1SCBTP before the core clock is switched to the higher frequency clock source.
When changing to a lower frequency, the MODE field of the MSC_READCTRL register can be set to WS0 or WS0SCBTP, but only
after the frequency transition is completed. If the HFRCO is used, wait until the oscillator is stable on the new frequency. Otherwise, the
behavior is unpredictable.
To run at a frequency higher than 32 MHz, WS2 or WS2SCBTP must be selected to insert two wait-states for every flash access.
7.3.4.2 Zero Wait-State Access
At 16 MHz and below, read operations from flash may be performed without any wait-states. Zero wait-state access greatly improves
code execution performance at frequencies from 16 MHz and below. By default, the Cortex-M4 uses speculative prefetching and If-
Then block folding to maximize code execution performance at the cost of additional flash accesses and energy consumption.
7.3.4.3 Operation Above 32 MHz
To run at frequencies higher than 32 MHz, MODE in MSC_READCTRL must be set to WS2 or WS2SCBTP.
7.3.4.4 Suppressed Conditional Branch Target Prefetch
MSC offers a special instruction fetch mode which optimizes energy consumption by cancelling Cortex- M4 conditional branch target
prefetches. Normally, the Cortex-M4 core prefetches both the next sequential instruction and the instruction at the branch target ad-
dress when a conditional branch instruction reaches the pipeline decode stage. This prefetch scheme improves performance while one
extra instruction is fetched from memory at each conditional branch, regardless of whether the branch is taken or not. To optimize for
low energy, the MSC can be configured to cancel these speculative branch target prefetches. With this configuration, energy consump-
tion is more optimal, as the branch target instruction fetch is delayed until the branch condition is evaluated.
The performance penalty with this mode enabled is source code dependent, but is normally less than 1% for core frequencies from 16
MHz and below. To enable the mode at frequencies from 16 MHz and below write WS0SCBTP to the MODE field of the
MSC_READCTRL register. For frequencies above 16 MHz, use the WS1SCBTP mode, and for frequencies above 32 MHz, use the
WS2SCBTP mode. An increased performance penalty per clock cycle must be expected compared to WS0SCBTP mode. The perform-
ance penalty in WS1SCBTP/WS2SCBTP mode depends greatly on the density and organization of conditional branch instructions in
the code.
7.3.4.5 Cortex-M4 If-Then Block Folding
The Cortex-M4 offers a mechanism known as if-then block folding. This is a form of speculative prefetching where small if-then blocks
are collapsed in the prefetch buffer if the condition evaluates to false. The instructions in the block then appear to execute in zero cy-
cles. With this scheme, performance is optimized at the cost of higher energy consumption as the processor fetches more instructions
from memory than it actually executes. To disable the mode, write a 1 to the DISFOLD bit in the NVIC Auxiliary Control Register; see
the Cortex-M4 Technical Reference Manual for details. Normally, it is expected that this feature is most efficient at core frequencies
above 16 MHz. Folding is enabled by default.
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7.3.4.6 Instruction Cache
The MSC includes an instruction cache. The instruction cache for the internal flash memory is enabled by default, but can be disabled
by setting IFCDIS in MSC_READCTRL. When enabled, the instruction cache typically reduces the number of flash reads significantly,
thus saving energy. In most cases a cache hit-rate of more than 70 % is achievable. When a 32-bit instruction fetch hits in the cache
the data is returned to the processor in one clock cycle. Thus, performance is also improved when wait-states are used (i.e. running at
frequencies above 16 MHz).
The instruction cache is connected directly to the Cortex-M4 and functions as a memory access filter between the processor and the
memory system, as illustrated in the following figure. The cache consists of an access filter, lookup logic, a 128x32 SRAM (512 bytes)
and two performance counters. The access filter checks that the address for the access is of an instruction in the code space (instruc-
tions in RAM outside the code space are not cached). If the address matches, the cache lookup logic and SRAM is enabled. Otherwise,
the cache is bypassed and the access is forwarded to the memory system. The cache is then updated when the memory access com-
pletes. The access filter also disables cache updates for interrupt context accesses if caching in interrupt context is disabled. The per-
formance counters, when enabled, keep track of the number of cache hits and misses. The cache consists of 16 8-word cachelines
organized as 4 sets with 4 ways. The cachelines are filled up continuously one word at a time as the individual words are requested by
the processor. Thus, not all words of a cacheline might be valid at a given time.
Cortex
128x32
SRAM
Access
Filter
Cache
Look-up Logic
ICODE
AHB-Lite Bus
ICODE
AHB-Lite Bus
CODE
Memory
Space
Instruction Cache
Performance Counters
DCODE
AHB-Lite Bus
IDCODE
AHB-Lite Bus
IDCODE
MUX
Figure 7.1. Instruction Cache
By default, the instruction cache is automatically invalidated when the contents of the flash is changed (i.e. written or erased). In many
cases, however, the application only makes changes to data in the flash, not code. In this case, the automatic invalidate feature can be
disabled by setting AIDIS in MSC_READCTRL. The cache can (independent of the AIDIS setting) be manually invalidated by writing 1
to INVCACHE in MSC_CMD.
In general it is highly recommended to keep the cache enabled all the time. However, for some sections of code with very low cache hit-
rate more energy-efficient execution can be achieved by disabling the cache temporarily. To measure the hit-rate of a code-section, the
built-in performance counters can be used. Before the section, start the performance counters by writing 1 to STARTPC in MSC_CMD.
This starts the performance counters, counting from 0. At the end of the section, stop the performance counters by writing 1 to
STOPPC in MSC_CMD. The number of cache hits and cache misses for that section can then be read from MSC_CACHEHITS and
MSC_CACHEMISSES respectively. The total number of 32-bit instruction fetches will be MSC_CACHEHITS + MSC_CACHEMISSES.
Thus, the cache hit-ratio can be calculated as MSC_CACHEHITS / (MSC_CACHEHITS + MSC_CACHEMISSES). When MSC_CA-
CHEHITS overflows the CHOF interrupt flag is set. When MSC_CACHEMISSES overflows the CMOF interrupt flag is set. These flags
must be cleared explicitly by software. The range of the performance counters can thus be extended by increasing a counter in the
MSC interrupt routine. The performance counters only count when a cache lookup is performed. If the lookup fails, MSC_CACHEMISS-
ES is increased. If the lookup is successful, MSC_CACHEHITS is increased. For example, a cache lookup is not performed if the cache
is disabled or the code is executed from RAM outside the code space. When caching of vector fetches and instructions in interrupt
routines is disabled (ICCDIS in MSC_READCTRL is set), the performance counters do not count when these types of fetches occur
(i.e. while in interrupt context).
By default, interrupt vector fetches and instructions in interrupt routines are also cached. Some applications may get better cache uti-
lization by not caching instructions in interrupt context. This is done by setting ICCDIS in MSC_READCTRL. You should only set this bit
based on the results from a cache hit ratio measurement. In general, it is recommended to keep the ICCDIS bit cleared. Note that look-
ups in the cache are still performed, regardless of the ICCDIS setting - but instructions are not cached when cache misses occur inside
the interrupt routine. So, for example, if a cached function is called from the interrupt routine, the instructions for that function will be
taken from the cache.
The cache content is not retained in EM2, EM3 and EM4. The cache is therefore invalidated regardless of the setting of AIDIS in
MSC_READCTRL when entering these energy modes. Applications that switch frequently between EM0 and EM2/3 and execute the
very same non-looping code almost every time will most likely benefit from putting this code in RAM. The interrupt vectors can also be
put in RAM to reduce current consumption even further.
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The cache also supports caching of instruction fetches from the external bus interface (EBI) when accessing the EBI through code
space. By default, this is enabled, but it can be disabled by setting EBICDIS in MSC_READCTRL.
7.3.5 Erase and Write Operations
The AUXHFRCO is used for timing during flash write and erase operations. To achieve correct timing, the MSC_TIMEBASE register
has to be configured according to the settings in CMU_AUXHFRCOCTRL. BASE in MSC_TIMEBASE defines how many AUXCLK cy-
cles - 1 there is in 1 us or 5 us, depending on the configuration of PERIOD. To ensure that timing of flash write and erase operations is
within the specification of the flash, the value written to BASE should give at least a 10% margin with respect to the period, i.e. for the 1
us PERIOD, the number of cycles should at least span 1.1 us, and for the 5 us period they should span at least 5.5 us. For the 1 MHz
band, PERIOD in MSC_TIMEBASE should be set to 5US, while it should be set to 1US for all other AUXHFRCO bands.
Both page erase and write operations require that the address is written into the MSC_ADDRB register. For erase operations, the ad-
dress may be any within the page to be erased. Load the address by writing 1 to the LADDRIM bit in the MSC_WRITECMD register.
The LADDRIM bit only has to be written once when loading the first address. After each word is written the internal address register
ADDR will be incremented automatically by 4. The INVADDR bit of the MSC_STATUS register is set if the loaded address is outside
the flash and the LOCKED bit of the MSC_STATUS register is set if the page addressed is locked. Any attempts to command erase of
or write to the page are ignored if INVADDR or the LOCKED bits of the MSC_STATUS register are set. To abort an ongoing erase, set
the ERASEABORT bit in the MSC_WRITECMD register.
When a word is written to the MSC_WDATA register, the WDATAREADY bit of the MSC_STATUS register is cleared. When this status
bit is set, software or DMA may write the next word.
A single word write is commanded by setting the WRITEONCE bit of the MSC_WRITECMD register. The operation is complete when
the BUSY bit of the MSC_STATUS register is cleared and control of the flash is handed back to the AHB interface, allowing application
code to resume execution.
For a DMA write the software must write the first word to the MSC_WDATA register and then set the WRITETRIG bit of the
MSC_WRITECMD register. DMA triggers when the WDATAREADY bit of the MSC_STATUS register is set.
It is possible to write words twice between each erase by keeping at 1 the bits that are not to be changed. Let us take as an example
writing two 16 bit values, 0xAAAA and 0x5555. To safely write them in the same flash word this method can be used:
• Write 0xFFFFAAAA (word in flash becomes 0xFFFFAAAA)
• Write 0x5555FFFF (word in flash becomes 0x5555AAAA)
Note: During a write or erase, flash read accesses will be stalled, effectively halting code execution from flash. Code execution contin-
ues upon write/erase completion. Code residing in RAM may be executed during a write/erase operation.
Note: The MSC_WDATA and MSC_ADDRB registers are not retained when entering EM2 or lower energy modes.
7.3.5.1 Mass Erase
A mass erase can be initiated from software using ERASEMAIN0 in MSC_WRITECMD. This command will start a mass erase of the
entire flash. Prior to initiating a mass erase, MSC_MASSLOCK must be unlocked by writing 0x631A to it. After a mass erase has been
started, this register can be locked again to prevent runaway code from accidentally triggering a mass erase.
The regular flash page lock bits will not prevent a mass erase. To prevent software from initiating mass erases, use the mass erase
lock bits in the mass erase lock word (MLW).
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7.4 Register Map
The offset register address is relative to the registers base address.
Offset Name Type Description
0x000 MSC_CTRL RW Memory System Control Register
0x004 MSC_READCTRL RW Read Control Register
0x008 MSC_WRITECTRL RW Write Control Register
0x00C MSC_WRITECMD W1 Write Command Register
0x010 MSC_ADDRB RW Page Erase/Write Address Buffer
0x018 MSC_WDATA RW Write Data Register
0x01C MSC_STATUS RStatus Register
0x02C MSC_IF RInterrupt Flag Register
0x030 MSC_IFS W1 Interrupt Flag Set Register
0x034 MSC_IFC (R)W1 Interrupt Flag Clear Register
0x038 MSC_IEN RW Interrupt Enable Register
0x03C MSC_LOCK RW Configuration Lock Register
0x040 MSC_CMD W1 Command Register
0x044 MSC_CACHEHITS RCache Hits Performance Counter
0x048 MSC_CACHEMISSES RCache Misses Performance Counter
0x050 MSC_TIMEBASE RW Flash Write and Erase Timebase
0x054 MSC_MASSLOCK RW Mass Erase Lock Register
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7.5 Register Description
7.5.1 MSC_CTRL - Memory System Control Register
Offset Bit Position
0x000
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
16
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
Reset
1
Access
RW
Name
BUSFAULT
Bit Name Reset Access Description
31:1 Reserved To ensure compatibility with future devices, always write bits to 0. More information in 2.1 Conven-
tions.
0 BUSFAULT 1 RW Bus Fault Response Enable
When this bit is set, the memory system generates bus error response.
Value Mode Description
0 GENERATE A bus fault is generated on access to unmapped code and system
space.
1 IGNORE Accesses to unmapped address space is ignored.
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7.5.2 MSC_READCTRL - Read Control Register
Offset Bit Position
0x004
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
16
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
Reset
0x0
0
0
0
0
0
0x1
Access
RW
RW
RW
RW
RW
RW
RW
Name
BUSSTRATEGY
RAMCEN
EBICDIS
ICCDIS
AIDIS
IFCDIS
MODE
Bit Name Reset Access Description
31:18 Reserved To ensure compatibility with future devices, always write bits to 0. More information in 2.1 Conven-
tions.
17:16 BUSSTRATEGY 0x0 RW Strategy for bus matrix
Specify which master has low latency to bus matrix.
Value Mode Description
0 CPU
1 DMA
2 DMAEM1
3 NONE
15:8 Reserved To ensure compatibility with future devices, always write bits to 0. More information in 2.1 Conven-
tions.
7 RAMCEN 0 RW RAM Cache Enable
Enable instruction caching for RAM in code-space.
6 EBICDIS 0 RW External Bus Interface Cache Disable
Disable instruction cache for external bus interface.
5 ICCDIS 0 RW Interrupt Context Cache Disable
Set this bit to automatically disable caching of vector fetches and instruction fetches in interrupt context. Cache lookup will
still be performed in interrupt context. When set, the performance counters will not count when these types of fetches occur.
4 AIDIS 0 RW Automatic Invalidate Disable
When this bit is set the cache is not automatically invalidated when a write or page erase is performed.
3 IFCDIS 0 RW Internal Flash Cache Disable
Disable instruction cache for internal flash memory.
2:0 MODE 0x1 RW Read Mode
If software wants to set a core clock frequency above 16 MHz, this register must be set to WS1 or WS1SCBTP before the
core clock is switched to the higher frequency. When changing to a lower frequency, this register can be set to WS0 or
WS0SCBTP after the frequency transition has been completed. After reset, the core clock is 14 MHz from the HFRCO but
the MODE field of MSC_READCTRL register is set to WS1. This is because the HFRCO may produce a frequency above
16 MHz before it is calibrated. If the HFRCO is used as clock source, wait until the oscillator is stable on the new frequency
to avoid unpredictable behavior.
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Bit Name Reset Access Description
Value Mode Description
0 WS0 Zero wait-states inserted in fetch or read transfers.
1 WS1 One wait-state inserted for each fetch or read transfer. This mode is re-
quired for a core frequency above 16 MHz.
2 WS0SCBTP Zero wait-states inserted with the Suppressed Conditional Branch Tar-
get Prefetch (SCBTP) function enabled. SCBTP saves energy by de-
laying the Cortex' conditional branch target prefetches until the condi-
tional branch instruction is in the execute stage. When the instruction
reaches this stage, the evaluation of the branch condition is completed
and the core does not perform a speculative prefetch of both the
branch target address and the next sequential address. With the
SCBTP function enabled, one instruction fetch is saved for each
branch not taken, with a negligible performance penalty.
3 WS1SCBTP One wait-state access with SCBTP enabled.
4 WS2 Two wait-states inserted for each fetch or read transfer. This mode is
required for a core frequency above 32 MHz.
5 WS2SCBTP Two wait-state access with SCBTP enabled.
7.5.3 MSC_WRITECTRL - Write Control Register
Offset Bit Position
0x008
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
16
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
Reset
0
0
Access
RW
RW
Name
IRQERASEABORT
WREN
Bit Name Reset Access Description
31:2 Reserved To ensure compatibility with future devices, always write bits to 0. More information in 2.1 Conven-
tions.
1 IRQERASEABORT 0 RW Abort Page Erase on Interrupt
When this bit is set to 1, any Cortex interrupt aborts any current page erase operation.
0 WREN 0 RW Enable Write/Erase Controller
When this bit is set, the MSC write and erase functionality is enabled.
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7.5.4 MSC_WRITECMD - Write Command Register
Offset Bit Position
0x00C
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
16
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
Reset
0
0
0
0
0
0
0
0
Access
W1
W1
W1
W1
W1
W1
W1
W1
Name
CLEARWDATA
ERASEMAIN0
ERASEABORT
WRITETRIG
WRITEONCE
WRITEEND
ERASEPAGE
LADDRIM
Bit Name Reset Access Description
31:13 Reserved To ensure compatibility with future devices, always write bits to 0. More information in 2.1 Conven-
tions.
12 CLEARWDATA 0 W1 Clear WDATA state
Will set WDATAREADY and DMA request. Should only be used when no write is active.
11:9 Reserved To ensure compatibility with future devices, always write bits to 0. More information in 2.1 Conven-
tions.
8 ERASEMAIN0 0 W1 Mass erase region 0
Initiate mass erase of region 0. For devices supporting read-while-write, this is the lower half of the flash. For other devices
it is the entire flash. Before use MSC_MASSLOCK must be unlocked. To completely prevent access from software, clear bit
0 in the mass erase lock-word (MLW).
7:6 Reserved To ensure compatibility with future devices, always write bits to 0. More information in 2.1 Conven-
tions.
5 ERASEABORT 0 W1 Abort erase sequence
Writing to this bit will abort an ongoing erase sequence.
4 WRITETRIG 0 W1 Word Write Sequence Trigger
Functions like MSC_CMD_WRITEONCE, but will set MSC_STATUS_WORDTIMEOUT if no new data is written to
MSC_WDATA within the 30 µs timeout.
3 WRITEONCE 0 W1 Word Write-Once Trigger
Start write of the first word written to MSC_WDATA, then add 4 to ADDR and write the next word if available within a 30 µs
timeout. When ADDR is incremented past the page boundary, ADDR is set to the base of the page.
2 WRITEEND 0 W1 End Write Mode
Write 1 to end write mode when using the WRITETRIG command.
1 ERASEPAGE 0 W1 Erase Page
Erase any user defined page selected by the MSC_ADDRB register. The WREN bit in the MSC_WRITECTRL register must
be set in order to use this command.
0 LADDRIM 0 W1 Load MSC_ADDRB into ADDR
Load the internal write address register ADDR from the MSC_ADDRB register. The internal address register ADDR is in-
cremented automatically by 4 after each word is written. When ADDR is incremented past the page boundary, ADDR is set
to the base of the page.
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7.5.5 MSC_ADDRB - Page Erase/Write Address Buffer
Offset Bit Position
0x010
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
16
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
Reset
0x00000000
Access
RW
Name
ADDRB
Bit Name Reset Access Description
31:0 ADDRB 0x00000000 RW Page Erase or Write Address Buffer
This register holds the page address for the erase or write operation. This register is loaded into the internal MSC_ADDR
register when the LADDRIM field in MSC_WRITECMD is set. The MSC_ADDR register is not readable. This register is not
retained when entering EM2 or lower energy modes.
7.5.6 MSC_WDATA - Write Data Register
Offset Bit Position
0x018
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
16
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
Reset
0x00000000
Access
RW
Name
WDATA
Bit Name Reset Access Description
31:0 WDATA 0x00000000 RW Write Data
The data to be written to the address in MSC_ADDR. This register must be written when the WDATAREADY bit of
MSC_STATUS is set. This register is not retained when entering EM2 or lower energy modes.
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7.5.7 MSC_STATUS - Status Register
Offset Bit Position
0x01C
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
16
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
Reset
0
0
0
1
0
0
0
Access
R
R
R
R
R
R
R
Name
PCRUNNING
ERASEABORTED
WORDTIMEOUT
WDATAREADY
INVADDR
LOCKED
BUSY
Bit Name Reset Access Description
31:7 Reserved To ensure compatibility with future devices, always write bits to 0. More information in 2.1 Conven-
tions.
6 PCRUNNING 0 R Performance Counters Running
This bit is set while the performance counters are running. When one performance counter reaches the maximum value,
this bit is cleared.
5 ERASEABORTED 0 R The Current Flash Erase Operation Aborted
When set, the current erase operation was aborted by interrupt.
4 WORDTIMEOUT 0 R Flash Write Word Timeout
When this bit is set, MSC_WDATA was not written within the timeout. The flash write operation timed out and access to the
flash is returned to the AHB interface. This bit is cleared when the ERASEPAGE, WRITETRIG or WRITEONCE commands
in MSC_WRITECMD are triggered.
3 WDATAREADY 1 R WDATA Write Ready
When this bit is set, the content of MSC_WDATA is read by MSC Flash Write Controller and the register may be updated
with the next 32-bit word to be written to flash. This bit is cleared when writing to MSC_WDATA.
2 INVADDR 0 R Invalid Write Address or Erase Page
Set when software attempts to load an invalid (unmapped) address into ADDR.
1 LOCKED 0 R Access Locked
When set, the last erase or write is aborted due to erase/write access constraints.
0 BUSY 0 R Erase/Write Busy
When set, an erase or write operation is in progress and new commands are ignored.
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7.5.8 MSC_IF - Interrupt Flag Register
Offset Bit Position
0x02C
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
16
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
Reset
0
0
0
0
Access
R
R
R
R
Name
CMOF
CHOF
WRITE
ERASE
Bit Name Reset Access Description
31:4 Reserved To ensure compatibility with future devices, always write bits to 0. More information in 2.1 Conven-
tions.
3 CMOF 0 R Cache Misses Overflow Interrupt Flag
Set when MSC_CACHEMISSES overflows.
2 CHOF 0 R Cache Hits Overflow Interrupt Flag
Set when MSC_CACHEHITS overflows.
1 WRITE 0 R Write Done Interrupt Read Flag
Set when a write is done.
0 ERASE 0 R Erase Done Interrupt Read Flag
Set when erase is done.
7.5.9 MSC_IFS - Interrupt Flag Set Register
Offset Bit Position
0x030
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
16
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
Reset
0
0
0
0
Access
W1
W1
W1
W1
Name
CMOF
CHOF
WRITE
ERASE
Bit Name Reset Access Description
31:4 Reserved To ensure compatibility with future devices, always write bits to 0. More information in 2.1 Conven-
tions.
3 CMOF 0 W1 Cache Misses Overflow Interrupt Set
Set the CMOF flag and generate interrupt.
2 CHOF 0 W1 Cache Hits Overflow Interrupt Set
Set the CHOF flag and generate interrupt.
1 WRITE 0 W1 Write Done Interrupt Set
Set the write done bit and generate interrupt.
0 ERASE 0 W1 Erase Done Interrupt Set
Set the erase done bit and generate interrupt.
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7.5.10 MSC_IFC - Interrupt Flag Clear Register
Offset Bit Position
0x034
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
16
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
Reset
0
0
0
0
Access
(R)W1
(R)W1
(R)W1
(R)W1
Name
CMOF
CHOF
WRITE
ERASE
Bit Name Reset Access Description
31:4 Reserved To ensure compatibility with future devices, always write bits to 0. More information in 2.1 Conven-
tions.
3 CMOF 0 (R)W1 Cache Misses Overflow Interrupt Clear
Clear the CMOF interrupt flag.
2 CHOF 0 (R)W1 Cache Hits Overflow Interrupt Clear
Clear the CHOF interrupt flag.
1 WRITE 0 (R)W1 Write Done Interrupt Clear
Clear the write done bit.
0 ERASE 0 (R)W1 Erase Done Interrupt Clear
Clear the erase done bit.
7.5.11 MSC_IEN - Interrupt Enable Register
Offset Bit Position
0x038
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
16
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
Reset
0
0
0
0
Access
RW
RW
RW
RW
Name
CMOF
CHOF
WRITE
ERASE
Bit Name Reset Access Description
31:4 Reserved To ensure compatibility with future devices, always write bits to 0. More information in 2.1 Conven-
tions.
3 CMOF 0 RW Cache Misses Overflow Interrupt Enable
Enable the cache misses performance counter overflow interrupt.
2 CHOF 0 RW Cache Hits Overflow Interrupt Enable
Enable the cache hits performance counter overflow interrupt.
1 WRITE 0 RW Write Done Interrupt Enable
Enable the write done interrupt.
0 ERASE 0 RW Erase Done Interrupt Enable
Enable the erase done interrupt.
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7.5.12 MSC_LOCK - Configuration Lock Register
Offset Bit Position
0x03C
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
16
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
Reset
0x0000
Access
RW
Name
LOCKKEY
Bit Name Reset Access Description
31:16 Reserved To ensure compatibility with future devices, always write bits to 0. More information in 2.1 Conven-
tions.
15:0 LOCKKEY 0x0000 RW Configuration Lock
Write any other value than the unlock code to lock access to MSC_CTRL, MSC_READCTRL, MSC_WRITECTRL and
MSC_TIMEBASE. Write the unlock code to enable access. When reading the register, bit 0 is set when the lock is enabled.
Mode Value Description
Read Operation
UNLOCKED 0 MSC registers are unlocked.
LOCKED 1 MSC registers are locked.
Write Operation
LOCK 0 Lock MSC registers.
UNLOCK 0x1B71 Unlock MSC registers.
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7.5.13 MSC_CMD - Command Register
Offset Bit Position
0x040
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
16
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
Reset
0
0
0
Access
W1
W1
W1
Name
STOPPC
STARTPC
INVCACHE
Bit Name Reset Access Description
31:3 Reserved To ensure compatibility with future devices, always write bits to 0. More information in 2.1 Conven-
tions.
2 STOPPC 0 W1 Stop Performance Counters
Use this command bit to stop the performance counters.
1 STARTPC 0 W1 Start Performance Counters
Use this command bit to start the performance counters. The performance counters always start counting from 0.
0 INVCACHE 0 W1 Invalidate Instruction Cache
Use this register to invalidate the instruction cache.
7.5.14 MSC_CACHEHITS - Cache Hits Performance Counter
Offset Bit Position
0x044
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
16
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
Reset
0x00000
Access
R
Name
CACHEHITS
Bit Name Reset Access Description
31:20 Reserved To ensure compatibility with future devices, always write bits to 0. More information in 2.1 Conven-
tions.
19:0 CACHEHITS 0x00000 R Cache hits since last performance counter start command.
Use to measure cache performance for a particular code section.
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7.5.15 MSC_CACHEMISSES - Cache Misses Performance Counter
Offset Bit Position
0x048
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
16
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
Reset
0x00000
Access
R
Name
CACHEMISSES
Bit Name Reset Access Description
31:20 Reserved To ensure compatibility with future devices, always write bits to 0. More information in 2.1 Conven-
tions.
19:0 CACHEMISSES 0x00000 R Cache misses since last performance counter start command.
Use to measure cache performance for a particular code section.
7.5.16 MSC_TIMEBASE - Flash Write and Erase Timebase
Offset Bit Position
0x050
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
16
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
Reset
0
0x10
Access
RW
RW
Name
PERIOD
BASE
Bit Name Reset Access Description
31:17 Reserved To ensure compatibility with future devices, always write bits to 0. More information in 2.1 Conven-
tions.
16 PERIOD 0 RW Sets the timebase period
Decides whether TIMEBASE specifies the number of AUX cycles in 1 us or 5 us. 5 us should only be used with 1 MHz
AUXHFRCO band.
Value Mode Description
0 1US TIMEBASE period is 1 us.
1 5US TIMEBASE period is 5 us.
15:6 Reserved To ensure compatibility with future devices, always write bits to 0. More information in 2.1 Conven-
tions.
5:0 BASE 0x10 RW Timebase used by MSC to time flash writes and erases
Should be set to the number of full AUX clock cycles in the period given by MSC_TIMEBASE_PERIOD. I.e. 1.1 us or 5.5.
us with PERIOD cleared or set, respectively. The resetvalue of the timebase matches a 14 MHz AUXHFRCO, which is the
default frequency of the AUXHFRCO.
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7.5.17 MSC_MASSLOCK - Mass Erase Lock Register
Offset Bit Position
0x054
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
16
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
Reset
0x0001
Access
RW
Name
LOCKKEY
Bit Name Reset Access Description
31:16 Reserved To ensure compatibility with future devices, always write bits to 0. More information in 2.1 Conven-
tions.
15:0 LOCKKEY 0x0001 RW Mass Erase Lock
Write any other value than the unlock code to lock access the the ERASEMAIN0 and ERASEMAIN1 commands. Write the
unlock code 631A to enable access. When reading the register, bit 0 is set when the lock is enabled. Locked by default.
Mode Value Description
Read Operation
UNLOCKED 0 Mass erase unlocked.
LOCKED 1 Mass erase locked.
Write Operation
LOCK 0 Lock mass erase.
UNLOCK 0x631A Unlock mass erase.
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“M“ g
8. DMA - DMA Controller
43210
DMA
controller
Flash
RAM
External Bus
Interface
Peripherals
Quick Facts
What?
The DMA controller can move data without CPU in-
tervention, effectively reducing the energy consump-
tion for a data transfer.
Why?
The DMA can perform data transfers more energy
efficiently than the CPU and allows autonomous op-
eration in low energy modes. The LEUART can for
instance provide full UART communication in EM2,
consuming only a few μA by using the DMA to move
data between the LEUART and RAM.
How?
The DMA controller has multiple highly configurable,
prioritized DMA channels. Advanced transfer modes
such as ping-pong and scatter-gather make it possi-
ble to tailor the controller to the specific needs of an
application.
8.1 Introduction
The Direct Memory Access (DMA) controller performs memory operations independently of the CPU. This has the benefit of reducing
the energy consumption and the workload of the CPU, and enables the system to stay in low energy modes for example when moving
data from the USART to RAM or from the External Bus Interface (EBI) to the DAC. The DMA controller uses the PL230 μDMA controller
licensed from ARM.
Note: ARM PL230 homepage [ http://infocenter.arm.com/help/index.jsp?topic=/com.arm.doc.ddi0417a/index.html ].
Each of the PL230s channels on the EFM32 can be connected to any of the EFM32 peripherals.
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8.2 Features
• The DMA controller is accessible as a memory mapped peripheral
• Possible data transfers include
• RAM/EBI/Flash to peripheral
• RAM/EBI to Flash
• Peripheral to RAM/EBI
• RAM/EBI/Flash to RAM/EBI
• The DMA controller has 12 independent channels
• Each channel has one (primary) or two (primary and alternate) descriptors
• The configuration for each channel includes
• Transfer mode
• Priority
• Word-count
• Word-size (8, 16, 32 bit)
• The transfer modes include
• Basic (using the primary or alternate DMA descriptor)
• Ping-pong (switching between the primary or alternate DMA descriptors, for continuous data flow to/from peripherals)
• Scatter-gather (using the primary descriptor to configure the alternate descriptor)
• Each channel has a programmable transfer length
• Channels 0 and 1 support looped transfers
• Channel 0 supports 2D copy
• A DMA channel can be triggered by any of several sources:
• Communication modules (USART, UART, LEUART)
• Timers (TIMER)
• Analog modules (DAC, ACMP, ADC)
• External Bus Interface (EBI)
• Software
• Programmable mapping between channel number and peripherals - any DMA channel can be triggered by any of the available sour-
ces
• Interrupts upon transfer completion
• Data transfer to/from LEUART in EM2 is supported by the DMA, providing extremely low energy consumption while performing
UART communications
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8.3 Block Diagram
An overview of the DMA and the modules it interacts with is shown in the following figure.
Interrupts
APB block AHB block
DMA control block
Cortex
AHB to
APB
bridge
AHB
Configuration
control
DMA data
transfer
Error
Channel
done
Peripheral
Peripheral
Channel
select REQ/
ACK
Configuration
APB
memory
mapped
registers
AHB-Lite
master
interface
DMA Core
Figure 8.1. DMA Block Diagram
The DMA Controller consists of four main parts:
• An APB block allowing software to configure the DMA controller
• An AHB block allowing the DMA to read and write the DMA descriptors and the source and destination data for the DMA transfers
• A DMA control block controlling the operation of the DMA, including request/acknowledge signals for the connected peripherals
• A channel select block routing the right peripheral request to each DMA channel
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8.4 Functional Description
The DMA Controller is highly flexible. It is capable of transferring data between peripherals and memory without involvement from the
processor core. This can be used to increase system performance by off-loading the processor from copying large amounts of data or
avoiding frequent interrupts to service peripherals needing more data or having available data. It can also be used to reduce the system
energy consumption by making the DMA work autonomously with the LEUART for data transfer in EM2 without having to wake up the
processor core from sleep.
The DMA Controller contains 12 independent channels. Each of these channels can be connected to any of the available peripheral
trigger sources by writing to the configuration registers, see 8.4.1 Channel Select Configuration. In addition, each channel can be trig-
gered by software (for large memory transfers or for debugging purposes).
What the DMA Controller should do (when one of its channels is triggered) is configured through channel descriptors residing in system
memory. Before enabling a channel, the software must therefore take care to write this configuration to memory. When a channel is
triggered, the DMA Controller will first read the channel descriptor from system memory, and then it will proceed to perform the memory
transfers as specified by the descriptor. The descriptor contains the memory address to read from, the memory address to write to, the
number of bytes to be transferred, etc. The channel descriptor is described in detail in 8.4.3 Channel Control Data Structure.
In addition to the basic transfer mode, the DMA Controller also supports two advanced transfer modes; ping-pong and scatter-gather.
Ping-pong transfers are ideally suited for streaming data for high-speed peripheral communication as the DMA will be ready to retrieve
the next incoming data bytes immediately while the processor core is still processing the previous ones (and similarly for outgoing com-
munication). Scatter-gather involves executing a series of tasks from memory and allows sophisticated schemes to be implemented by
software.
Using different priority levels for the channels and setting the number of bytes after which the DMA Controller re-arbitrates, it is possible
to ensure that timing-critical transfers are serviced on time.
8.4.1 Channel Select Configuration
The channel select block allows selecting which peripheral's request lines (dma_req, dma_sreq) to connect to each DMA channel.
This configuration is done by software through the control registers DMA_CH0_CTRL through DMA_ CH11_CTRL, with SOURCESEL
and SIGSEL components. SOURCESEL selects which peripheral to listen to and SIGSEL picks which output signals to use from the
selected peripheral.
All peripherals are connected to dma_req. When this signal is triggered, the DMA performs a number of transfers as specified by the
channel descriptor (2R). The USARTs are additionally connected to the dma_sreq line. When only dma_sreq is asserted but not
dma_req, then the DMA will perform exactly one transfer only (given that dma_sreq is enabled by software).
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8.4.2 DMA Control
8.4.2.1 DMA Arbitration Rate
You can configure when the controller arbitrates during a DMA transfer. This enables you to reduce the latency to service a higher
priority channel.
The controller provides four bits that configure how many AHB bus transfers occur before it re-arbitrates. These bits are known as the
R_power bits because the value you enter, R, is raised to the power of two and this determines the arbitration rate. For example, if R =
4 then the arbitration rate is 24, that is, the controller arbitrates every 16 DMA transfers.
The following table lists the arbitration rates.
Table 8.1. AHB Bus Transfer Arbitration Interval
R_power Arbitrate After x DMA Transfers
b0000 x = 1
b0001 x = 2
b0010 x = 4
b0011 x = 8
b0100 x = 16
b0101 x = 32
b0110 x = 64
b0111 x = 128
b1000 x = 256
b1001 x = 512
b1010 - b1111 x = 1024
Note: You must take care not to assign a low-priority channel with a large R_power because this prevents the controller from servicing
high-priority requests, until it re-arbitrates.
The number of dma transfers N that need to be done is specified by the user. When N > 2R and is not an integer multiple of 2R then the
controller always performs sequences of 2R transfers until N < 2R remain to be transferred. The controller performs the remaining N
transfers at the end of the DMA cycle.
You store the value of the R_power bits in the channel control data structure. See 8.4.3.3 Control Data Configuration for more informa-
tion about the location of the R_power bits in the data structure.
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8.4.2.2 Priority
When the controller arbitrates, it determines the next channel to service by using the following information:
• the channel number
• the priority level, default or high, that is assigned to the channel.
You can configure each channel to use either the default priority level or a high priority level by setting the DMA_CHPRIS register.
Channel number zero has the highest priority and as the channel number increases, the priority of a channel decreases. The following
table lists the DMA channel priority levels in descending order of priority.
Table 8.2. DMA Channel Priority
Channel Number Priority Level Setting Descending Order of Channel Priority
0 High —
1 High —
2 High —
3 High —
4 High —
5 High —
6 High —
7 High —
8 High —
9 High —
10 High —
11 High —
0 Default —
1 Default —
2 Default —
3 Default —
4 Default —
5 Default —
6 Default —
7 Default —
8 Default —
9 Default —
10 Default —
11 Default Lowest-priority DMA channel
After a DMA transfer completes, the controller polls all the DMA channels that are available. The following figure shows the process it
uses to determine which DMA transfer to perform next.
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NO
Start polling
Is there
a channel request ?
Are any
channel requests
using a high priority-
level ?
Start DMA transfer
Select channel that has the
lowest channel number and
is set to high priority-level
Select channel that has the
lowest channel number
YES
YES
NO
Figure 8.2. Polling Flowchart
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8.4.2.3 DMA Cycle Types
The cycle_ctrl bits control how the controller performs a DMA cycle. You can set the cycle_ctrl bits as the following table lists.
Table 8.3. DMA Cycle Types
cycle_ctrl Description
b000 Channel control data structure is invalid
b001 Basic DMA transfer
b010 Auto-request
b011 Ping-pong
b100 Memory scatter-gather using the primary data structure
b101 Memory scatter-gather using the alternate data structure
b110 Peripheral scatter-gather using the primary data structure
b111 Peripheral scatter-gather using the alternate data structure
Note: The cycle_ctrl bits are located in the channel_cfg memory location as described in 8.4.3.3 Control Data Configuration.
For all cycle types, the controller arbitrates after 2R DMA transfers. If you set a low-priority channel with a large 2R value then it pre-
vents all other channels from performing a DMA transfer, until the low-priority DMA transfer completes. Therefore, you must take care
when setting the R_power, that you do not significantly increase the latency for high-priority channels.
8.4.2.3.1 Invalid
After the controller completes a DMA cycle it sets the cycle type to invalid, to prevent it from repeating the same DMA cycle.
8.4.2.3.2 Basic
In this mode, you configure the controller to use either the primary or the alternate data structure. After you enable the channel C and
the controller receives a request for this channel, then the flow for this DMA cycle is as follows:
1. The controller performs 2R transfers. If the number of transfers remaining becomes zero, then the flow continues at step 3.
2. The controller arbitrates:
• if a higher-priority channel is requesting service then the controller services that channel
• if the peripheral or software signals a request to the controller, then it continues at step 1.
3. The controller sets dma_done[C] HIGH for one HFCORECLK cycle. This indicates to the host processor that the DMA cycle is
complete.
8.4.2.3.3 Auto-Request
When the controller operates in this mode, it is only necessary for it to receive a single request to enable it to complete the entire DMA
cycle. This enables a large data transfer to occur, without significantly increasing the latency for servicing higher priority requests, or
requiring multiple requests from the processor or peripheral.
You can configure the controller to use either the primary or the alternate data structure. After you enable the channel C and the con-
troller receives a request for this channel, then the flow for this DMA cycle is as follows:
1. The controller performs 2R transfers for channel C. If the number of transfers remaining is zero the flow continues at step 3.
2. The controller arbitrates. When channel C has the highest priority then the DMA cycle continues at step 1.
3. The controller sets dma_done[C] HIGH for one HFCORECLK cycle. This indicates to the host processor that the DMA cycle is
complete.
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sk
A
A
AAA
sk
sk
A A
sk
A
A
8.4.2.3.4 Ping-Pong
In ping-pong mode, the controller performs a DMA cycle using one of the data structures (primary or alternate) and it then performs a
DMA cycle using the other data structure. The controller continues to switch from primary to alternate to primary… until it reads a data
structure that is invalid, or until the host processor disables the channel.
Figure 8.3 Ping-Pong Example on page 87 shows an example of a ping-pong DMA transaction.
Task A
Task A: Primary, cycle_ctrl = b011, 2R = 4, N = 6
dma_done[C]
Task B
Task B: Alternate, cycle_ctrl = b011, 2R = 4, N = 12
dma_done[C]
Task C
Task C: Primary, cycle_ctrl = b011, 2R = 2, N = 2
dma_done[C]
Task D
Task D: Alternate, cycle_ctrl = b011, 2R = 4, N = 5
dma_done[C]
Task E
Task E: Primary, cycle_ctrl = b011, 2R = 4, N = 7
dma_done[C]
End: Alternate, cycle_ctrl = b000 Invalid
Request
Request
Request
Request
Request
Request
Request
Request
Request
Request
Figure 8.3. Ping-Pong Example
In Figure 8.3 Ping-Pong Example on page 87 :
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Task A 1. The host processor configures the primary data structure for task A.
2. The host processor configures the alternate data structure for task B. This enables the controller to immediately
switch to task B after task A completes, provided that a higher priority channel does not require servicing.
3. The controller receives a request and performs four DMA transfers.
4. The controller arbitrates. After the controller receives a request for this channel, the flow continues if the channel
has the highest priority.
5. The controller performs the remaining two DMA transfers.
6. The controller sets dma_done[C] HIGH for one HFCORECLK cycle and enters the arbitration process.
After task A completes, the host processor can configure the primary data structure for task C. This enables the controller to immediate-
ly switch to task C after task B completes, provided that a higher priority channel does not require servicing.
After the controller receives a new request for the channel and it has the highest priority then task B commences:
Task B 7. The controller performs four DMA transfers.
8. The controller arbitrates. After the controller receives a request for this channel, the flow continues if the channel
has the highest priority.
9. The controller performs four DMA transfers.
10. The controller arbitrates. After the controller receives a request for this channel, the flow continues if the channel
has the highest priority.
11. The controller performs the remaining four DMA transfers.
12. The controller sets dma_done[C] HIGH for one HFCORECLK cycle and enters the arbitration process.
After task B completes, the host processor can configure the alternate data structure for task D.
After the controller receives a new request for the channel and it has the highest priority then task C commences:
Task C 13. The controller performs two DMA transfers.
14. The controller sets dma_done[C] HIGH for one HFCORECLK cycle and enters the arbitration process.
After task C completes, the host processor can configure the primary data structure for task E.
After the controller receives a new request for the channel and it has the highest priority then task D commences:
Task D 15. The controller performs four DMA transfers.
16. The controller arbitrates. After the controller receives a request for this channel, the flow continues if the channel
has the highest priority.
17 The controller performs the remaining DMA transfer.
18. The controller sets dma_done[C] HIGH for one HFCORECLK cycle and enters the arbitration process.
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After the controller receives a new request for the channel and it has the highest priority then task E commences:
Task E 19. The controller performs four DMA transfers.
20. The controller arbitrates. After the controller receives a request for this channel, the flow continues if the channel
has the highest priority.
21. The controller performs the remaining three DMA transfers.
22. The controller sets dma_done[C] HIGH for one HFCORECLK cycle and enters the arbitration process.
If the controller receives a new request for the channel and it has the highest priority then it attempts to start the next task. However,
because the host processor has not configured the alternate data structure, and on completion of task D the controller set the cycle_ctrl
bits to b000, then the ping-pong DMA transaction completes.
Note: You can also terminate the ping-pong DMA cycle in Figure 8.3 Ping-Pong Example on page 87, if you configure task E to be a
basic DMA cycle by setting the cycle_ctrl field to 3’b001.
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8.4.2.3.5 Memory Scatter-Gather
In memory scatter-gather mode the controller receives an initial request and then performs four DMA transfers using the primary data
structure. After this transfer completes, it starts a DMA cycle using the alternate data structure. After this cycle completes, the controller
performs another four DMA transfers using the primary data structure. The controller continues to switch from primary to alternate to
primary… until either:
• the host processor configures the alternate data structure for a basic cycle
• it reads an invalid data structure.
Note: After the controller completes the N primary transfers it invalidates the primary data structure by setting the cycle_ctrl field to
b000.
The controller only asserts dma_done[C] when the scatter-gather transaction completes using an autorequest cycle.
In scatter-gather mode, the controller uses the primary data structure to program the alternate data structure. The following table lists
the fields of the channel_cfg memory location for the primary data structure, that you must program with constant values and those that
can be user defined.
Table 8.4. channel_cfg for a Primary Data Structure, in Memory Scatter-Gather Mode
Bit Field Value Description
Constant-Value Fields
[31:30] dst_inc b10 Configures the controller to use word increments for the address
[29:28] dst_size b10 Configures the controller to use word transfers
[27:26] src_inc b10 Configures the controller to use word increments for the address
[25:24] src_size b10 Configures the controller to use word transfers
[17:14] R_power b0010 Configures the controller to perform four DMA transfers
[3] next_useburst 0 For a memory scatter-gather DMA cycle, this bit must be set to zero
[2:0] cycle_ctrl b100 Configures the controller to perform a memory scatter-gather DMA cycle
User Defined Values
[23:21] dst_prot_ctrl — Configures the state of HPROT when the controller writes the destination data
[20:18] src_prot_ctrl — Configures the state of HPROT when the controller reads the source data
[13:4] n_minus_1 N1Configures the controller to perform N DMA transfers, where N is a multiple of
four
Note:
1. Because the R_power field is set to four, you must set N to be a multiple of four. The value given by N/4 is the number of times
that you must configure the alternate data structure.
See 8.4.3.3 Control Data Configuration for more information.
Figure 8.4 Memory Scatter-Gather Example on page 91 shows a memory scatter-gather example.
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Copy from A in
memory, to Alternate
Request
1. Configure primary to enable the copy A, B, C, and D operations: cycle_ctrl = b100, 2R = 4, N = 16.
Task A
Task B
Auto request
dma_done[C]
Copy from B in
memory, to Alternate
Auto request
Auto request
Auto
request
Auto
request
Auto
request
Copy from C in
memory, to Alternate
Task C
Copy from D in
memory, to Alternate
Task D
Data for Task A cycle_ctrl = b101, 2R = 4, N = 3
cycle_ctrl = b101, 2R = 2, N = 8
cycle_ctrl = b101, 2R = 8, N = 5
cycle_ctrl = b010, 2R = 4, N = 4
src_data_end_ptr dst_data_end_ptr channel_cfg Unused
0x0A000000 0x0AE00000
0x0B000000 0x0BE00000
0x0C000000 0x0CE00000
0x0D000000 0x0DE00000
0xXXXXXXXX
0xXXXXXXXX
0xXXXXXXXX
Data for Task B
Data for Task C
Data for Task D
Memory scatter-gather transaction:
Initialization:
Auto
request
Auto
request
Auto
request
Auto
request
Primary Alternate
N = 3, 2R =
4
N = 8, 2R =
2
N = 5, 2R =
8
N = 4, 2R =
4
2. Write the primary source data to memory, using the structure shown in the following table.
0xXXXXXXXX
Figure 8.4. Memory Scatter-Gather Example
In Figure 8.4 Memory Scatter-Gather Example on page 91:
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Initialization 1. The host processor configures the primary data structure to operate in memory scatter-gather mode by set-
ting cycle_ctrl to b100. Because a data structure for a single channel consists of four words then you must
set 2R to 4. In this example, there are four tasks and therefore N is set to 16.
2. The host processor writes the data structure for tasks A, B, C, and D to the memory locations that the pri-
mary src_data_end_ptr specifies.
3. The host processor enables the channel.
The memory scatter-gather transaction commences when the controller receives a request on dma_req[ ] or a manual request from the
host processor. The transaction continues as follows:
Primary, copy A 1. After receiving a request, the controller performs four DMA transfers. These transfers write the alternate
data structure for task A.
2. The controller generates an auto-request for the channel and then arbitrates.
Task A 3. The controller performs task A. After it completes the task, it generates an auto-request for the channel and
then arbitrates.
Primary, copy B 4. The controller performs four DMA transfers. These transfers write the alternate data structure for task B.
5. The controller generates an auto-request for the channel and then arbitrates.
Task B 6. The controller performs task B. After it completes the task, it generates an auto-request for the channel and
then arbitrates.
Primary, copy C 7. The controller performs four DMA transfers. These transfers write the alternate data structure for task C.
8. The controller generates an auto-request for the channel and then arbitrates.
Task C 9. The controller performs task C. After it completes the task, it generates an auto-request for the channel
and then arbitrates.
Primary, copy D 10. The controller performs four DMA transfers. These transfers write the alternate data structure for task D.
11. The controller sets the cycle_ctrl bits of the primary data structure to b000, to indicate that this data struc-
ture is now invalid.
12. The controller generates an auto-request for the channel and then arbitrates.
Task D 13. The controller performs task D using an auto-request cycle.
14. The controller sets dma_done[C] HIGH for one HFCORECLK cycle and enters the arbitration process.
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8.4.2.3.6 Peripheral Scatter-Gather
In peripheral scatter-gather mode the controller receives an initial request from a peripheral and then it performs four DMA transfers
using the primary data structure. It then immediately starts a DMA cycle using the alternate data structure, without re-arbitrating.
Note: These are the only circumstances, where the controller does not enter the arbitration process after completing a transfer using
the primary data structure.
After this cycle completes, the controller re-arbitrates and if the controller receives a request from the peripheral that has the highest
priority then it performs another four DMA transfers using the primary data structure. It then immediately starts a DMA cycle using the
alternate data structure, without rearbitrating. The controller continues to switch from primary to alternate to primary… until either:
• the host processor configures the alternate data structure for a basic cycle
• it reads an invalid data structure
Note: After the controller completes the N primary transfers it invalidates the primary data structure by setting the cycle_ctrl field to
b000.
The controller asserts dma_done[C] when the scatter-gather transaction completes using a basic cycle.
In scatter-gather mode, the controller uses the primary data structure to program the alternate data structure. The following table lists
the fields of the channel_cfg memory location for the primary data structure, that you must program with constant values and those that
can be user defined.
Table 8.5. channel_cfg for a Primary Data Structure, in Peripheral Scatter-Gather Mode
Bit Field Value Description
Constant-Value Fields
[31:30] dst_inc b10 Configures the controller to use word increments for the address
[29:28] dst_size b10 Configures the controller to use word transfers
[27:26] src_inc b10 Configures the controller to use word increments for the address
[25:24] src_size b10 Configures the controller to use word transfers
[17:14] R_power b0010 Configures the controller to perform four DMA transfers
[2:0] cycle_ctrl b110 Configures the controller to perform a peripheral scatter-gather DMA cycle
User Defined Values
[23:21] dst_prot_ctrl — Configures the state of HPROT when the controller writes the destination data
[20:18] src_prot_ctrl — Configures the state of HPROT when the controller reads the source data
[13:4] n_minus_1 N1Configures the controller to perform N DMA transfers, where N is a multiple of
four
[3] next_useburst — When set to 1, the controller sets the chnl_useburst_set [C] bit to 1 after the
alternate transfer completes
Note:
1. Because the R_power field is set to four, you must set N to be a multiple of four. The value given by N/4 is the number of times
that you must configure the alternate data structure.
See 8.4.3.3 Control Data Configuration for more information.
Figure 8.5 Peripheral Scatter-Gather Example on page 94 shows a peripheral scatter-gather example.
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Copy from A in
memory, to Alternate
Request
Task A
Task B
Request
Copy from B in
memory, to Alternate
Request
Request
Copy from C in
memory, to Alternate
Task C
Copy from D in
memory, to Alternate
Task D
Peripheral scatter-gather transaction:
For all primary to alternate transitions, the
controller does not enter the arbitration
process and immediately performs the
DMA transfer that the alternate channel
control data structure specifies.
1. Configure primary to enable the copy A, B, C, and D operations: cycle_ctrl = b110, 2R = 4, N = 16.
Initialization:
2. Write the primary source data in memory, using the structure shown in the following table.
cycle_ctrl = b111, 2R = 4, N = 3
cycle_ctrl = b111, 2R = 2, N = 8
cycle_ctrl = b111, 2R = 8, N = 5
cycle_ctrl = b001, 2R = 4, N = 4
src_data_end_ptr dst_data_end_ptr channel_cfg Unused
0x0A000000 0x0AE00000
0x0B000000 0x0BE00000
0x0C000000 0x0CE00000
0x0D000000 0x0DE00000
0xXXXXXXXX
0xXXXXXXXX
0xXXXXXXXX
0xXXXXXXXXData for Task A
Data for Task B
Data for Task C
Data for Task D
Request
Request
Request
Primary Alternate
dma_done[C]
N = 3, 2R = 4
N = 8, 2R = 2
N = 5, 2R = 8
N = 4, 2R = 4
Figure 8.5. Peripheral Scatter-Gather Example
In Figure 8.5 Peripheral Scatter-Gather Example on page 94 :
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Initialization 1. The host processor configures the primary data structure to operate in peripheral scatter-gather mode by
setting cycle_ctrl to b110. Because a data structure for a single channel consists of four words then you
must set 2R to 4. In this example, there are four tasks and therefore N is set to 16.
2. The host processor writes the data structure for tasks A, B, C, and D to the memory locations that the pri-
mary src_data_end_ptr specifies.
3. The host processor enables the channel.
The peripheral scatter-gather transaction commences when the controller receives a request on dma_req[ ]. The transaction continues
as follows:
Primary, copy A 1. After receiving a request, the controller performs four DMA transfers. These transfers write the alternate
data structure for task A.
Task A 2. The controller performs task A.
3. After the controller completes the task it enters the arbitration process.
After the peripheral issues a new request and it has the highest priority then the process continues with:
Primary, copy B 4. The controller performs four DMA transfers. These transfers write the alternate data structure for task B.
Task B 5. The controller performs task B. To enable the controller to complete the task, the peripheral must issue a
further three requests.
6. After the controller completes the task it enters the arbitration process.
After the peripheral issues a new request and it has the highest priority then the process continues with:
Primary, copy C 7. The controller performs four DMA transfers. These transfers write the alternate data structure for task C.
Task C 8. The controller performs task C.
9. After the controller completes the task it enters the arbitration process.
After the peripheral issues a new request and it has the highest priority then the process continues with:
Primary, copy D 10. The controller performs four DMA transfers. These transfers write the alternate data structure for task D.
11. The controller sets the cycle_ctrl bits of the primary data structure to b000, to indicate that this data struc-
ture is now invalid.
Task D 12. The controller performs task D using a basic cycle.
13. The controller sets dma_done[C] HIGH for one HFCORECLK cycle and enters the arbitration process.
8.4.2.4 Error Signaling
If the controller detects an ERROR response on the AHB-Lite master interface, it:
• disables the channel that corresponds to the ERROR
• sets dma_err HIGH.
After the host processor detects that dma_err is HIGH, it must check which channel was active when the ERROR occurred. It can do
this by:
1. Reading the DMA_CHENS register to create a list of disabled channels. When a channel asserts dma_done[ ] then the controller
disables the channel. The program running on the host processor must always keep a record of which channels have recently as-
serted their dma_done[ ] outputs.
2. It must compare the disabled channels list from step 1, with the record of the channels that have recently set their dma_done[ ]
outputs. The channel with no record of dma_done[C] being set is the channel that the ERROR occurred on.
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[L
0x010
0x000
8.4.3 Channel Control Data Structure
You must provide an area of system memory to contain the channel control data structure. This system memory must:
• provide a contiguous area of system memory that the controller and host processor can access
• have a base address that is an integer multiple of the total size of the channel control data structure.
Figure 8.6 Memory Map for 12 Channels, Including the Alternate Data Structure on page 96 shows the memory that the controller
requires for the channel control data structure, when all 12 channels and the optional alternate data structure are in use.
Primary_Ch_0
Primary_Ch_1
Primary_Ch_2
Primary_Ch_3
Primary_Ch_4
Primary_Ch_5
Primary_Ch_6
Primary_Ch_7
0x000
0x010
0x050
0x080
0x070
0x060
0x040
0x030
0x020
Alternate_Ch_0
Alternate_Ch_1
Alternate_Ch_2
Alternate_Ch_3
Alternate_Ch_4
Alternate_Ch_5
Alternate_Ch_6
Alternate_Ch_7
0x100
0x110
0x150
0x180
0x170
0x160
0x140
0x130
0x120 Destination End Pointer
Source End Pointer
Control
User
0x000
0x004
0x008
0x00C
Alternate Data Structure Primary Data Structure
Primary_Ch_8
Primary_Ch_9
Primary_Ch_10
Primary_Ch_11
0x090
0x0C0
0x0B0
0x0A0
Alternate_Ch_8
Alternate_Ch_9
Alternate_Ch_10
Alternate_Ch_11
0x190
0x1C0
0x1B0
0x1A0
Figure 8.6. Memory Map for 12 Channels, Including the Alternate Data Structure
This structure in Figure 8.6 Memory Map for 12 Channels, Including the Alternate Data Structure on page 96 uses 384 bytes of system
memory. The controller uses the lower 8 address bits to enable it to access all of the elements in the structure and therefore the base
address must be at 0xXXXXXX00.
You can configure the base address for the primary data structure by writing the appropriate value in the DMA_CTRLBASE register.
You do not need to set aside the full 384 bytes if all dma channels are not used or if all alternate descriptors are not used. If, for exam-
ple, only 4 channels are used and they only need the primary descriptors, then only 64 bytes need to be set aside.
The following table lists the address bits that the controller uses when it accesses the elements of the channel control data structure.
Table 8.6. Address Bit Settings for the Channel Control Data Structure
Address Bits
[8] [7] [6] [5] [4] [3:0]
A C[3] C[2] C[1] C[0] 0x0, 0x4, or 0x8
Where:
ASelects one of the channel control data structures:
A = 0 Selects the primary data structure.
A = 1 Selects the alternate data structure.
C[3:0] Selects the DMA channel.
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Address[3:0] Selects one of the control elements:
0x0 Selects the source data end pointer.
0x4 Selects the destination data end pointer.
0x8 Selects the control data configuration.
0xC The controller does not access this address location. If required, you can enable the host
processor to use this memory location as system memory.
Note: It is not necessary for you to calculate the base address of the alternate data structure because the DMA_ALTCTRLBASE regis-
ter provides this information.
Figure 8.7 Detailed Memory Map for the 12 channels, Including the Alternate Data Structure on page 98 shows a detailed memory
map of the descriptor structure.
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EEE
Unused
0x000
Source End Pointer
Destination End Pointer
Control
Unused
Source End Pointer
Destination End Pointer
Control
Unused
Source End Pointer
Destination End Pointer
Control
Unused
0x004
0x008
0x010
0x014
0x018
0x0B0
0x0B4
0x0B8
Source End Pointer
Destination End Pointer
Control
Unused
0x100
0x104
0x108
Source End Pointer
Destination End Pointer
Control
Unused
0x110
0x114
0x118
Source End Pointer
Destination End Pointer
Control
0x1B0
0x1B4
0x1B8
0x00C
0x01C
0x0BC
0x10C
0x11C
0x1BC
Alternate for
channel 11
Alternate for
channel 1
Alternate for
channel 0
Primary for
channel 11
Primary for
channel 1
Primary for
channel 0
Alternate
Data
Structure
Primary
Data
Structure
Figure 8.7. Detailed Memory Map for the 12 channels, Including the Alternate Data Structure
The controller uses the system memory to enable it to access two pointers and the control information that it requires for each channel.
The following subsections will describe these 32-bit memory locations and how the controller calculates the DMA transfer address.
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8.4.3.1 Source Data End Pointer
The src_data_end_ptr memory location contains a pointer to the end address of the source data. The following table lists the bit assign-
ments for this memory location.
Table 8.7. src_data_end_ptr Bit Assignments
Bit Name Description
[31:0] src_data_end_ptr Pointer to the end address of the source data
Before the controller can perform a DMA transfer, you must program this memory location with the end address of the source data. The
controller reads this memory location when it starts a 2R DMA transfer.
Note: The controller does not write to this memory location.
8.4.3.2 Destination Data End Pointer
The dst_data_end_ptr memory location contains a pointer to the end address of the destination data. The following table lists the bit
assignments for this memory location.
Table 8.8. dst_data_end_ptr Bit Assignments
Bit Name Description
[31:0] dst_data_end_ptr Pointer to the end address of the destination data
Before the controller can perform a DMA transfer, you must program this memory location with the end address of the destination data.
The controller reads this memory location when it starts a 2R DMA transfer.
Note: The controller does not write to this memory location.
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L
8.4.3.3 Control Data Configuration
For each DMA transfer, the channel_cfg memory location provides the control information for the controller. Figure 8.8 channel_cfg Bit
Assignments on page 100 shows the bit assignments for this memory location.
31 21 20 13 40
dst_inc
src_prot_ctrl
R_power n_minus_1
next_useburst
30 29 28 27 26 25 24 23
dst_size src_size
src_inc dst_prot_ctrl
18 17
cycle_ctrl
314 2
Figure 8.8. channel_cfg Bit Assignments
Table 8.9. channel_cfg Bit Assignments
Bit Name Description
[31:30] dst_inc Destination address increment.
Source data width =
byte
b00 = byte.
b01 = halfword.
b10 = word.
b11 = no increment. Address remains set to the value that the
dst_data_end_ptr memory location contains.
Source data width =
halfword
b00 = reserved.
b01 = halfword.
b10 = word.
b11 = no increment. Address remains set to the value that the
dst_data_end_ptr memory location contains.
Source data width =
word
b00 = reserved.
b01 = reserved.
b10 = word.
b11 = no increment. Address remains set to the value that the
dst_data_end_ptr memory location contains.
[29:28] dst_size Destination data size.
Note: You must set dst_size to contain the same value that src_size contains.
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Bit Name Description
[27:26] src_inc Set the bits to control the source address increment. The address increment depends on
the source data width as follows:
Source data width =
byte
b00 = byte.
b01 = halfword.
b10 = word.
b11 = no increment. Address remains set to the value that the
src_data_end_ptr memory location contains.
Source data width =
halfword
b00 = reserved.
b01 = halfword.
b10 = word.
b11 = no increment. Address remains set to the value that the
src_data_end_ptr memory location contains.
Source data width =
word
b00 = reserved.
b01 = reserved.
b10 = word.
b11 = no increment. Address remains set to the value that the
src_data_end_ptr memory location contains.
[25:24] src_size Set the bits to match the size of the source data:
b00 = byte
b01 = halfword
b10 = word
b11 = reserved.
[23:21] dst_prot_ctrl Set the bits to control the state of HPROT when the controller writes the destination data.
Bit [23] This bit has no effect on the DMA.
Bit [22] This bit has no effect on the DMA.
Bit [21] Controls the state of HPROT as follows:
0 = HPROT is LOW and the access is non-privileged.
1 = HPROT is HIGH and the access is privileged.
[20:18] src_prot_ctrl Set the bits to control the state of HPROT when the controller reads the source data.
Bit [20] This bit has no effect on the DMA.
Bit [19] This bit has no effect on the DMA.
Bit [18] Controls the state of HPROT as follows:
0 = HPROT is LOW and the access is non-privileged.
1 = HPROT is HIGH and the access is privileged.
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Bit Name Description
[17:14] R_power Set these bits to control how many DMA transfers can occur before the controller re-arbi-
trates. The possible arbitration rate settings are:
b0000 Arbitrates after each DMA transfer.
b0001 Arbitrates after 2 DMA transfers.
b0010 Arbitrates after 4 DMA transfers.
b0011 Arbitrates after 8 DMA transfers.
b0100 Arbitrates after 16 DMA transfers.
b0101 Arbitrates after 32 DMA transfers.
b0110 Arbitrates after 64 DMA transfers.
b0111 Arbitrates after 128 DMA transfers.
b1000 Arbitrates after 256 DMA transfers.
b1001 Arbitrates after 512 DMA transfers.
b1010 - b1111 Arbitrates after 1024 DMA transfers. This means that no arbitra-
tion occurs during the DMA transfer because the maximum trans-
fer size is 1024.
[13:4] n_minus_1 Prior to the DMA cycle commencing, these bits represent the total number of DMA trans-
fers that the DMA cycle contains. You must set these bits according to the size of DMA
cycle that you require.
The 10-bit value indicates the number of DMA transfers, minus one. The possible values
are:
b000000000 = 1 DMA transfer.
b000000001 = 2 DMA transfers.
b000000010 = 3 DMA transfers.
b000000011 = 4 DMA transfers.
b000000100 = 5 DMA transfers.
...
b111111111 = 1024 DMA transfers.
The controller updates this field immediately prior to it entering the arbitration process.
This enables the controller to store the number of outstanding DMA transfers that are
necessary to complete the DMA cycle.
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Bit Name Description
[3] next_useburst Controls if the chnl_useburst_set [C] bit is set to a 1, when the controller is performing a
peripheral scatter-gather and is completing a DMA cycle that uses the alternate data
structure.
Note: Immediately prior to completion of the DMA cycle that the alternate data structure
specifies, the controller sets the chnl_useburst_set [C] bit to 0 if the number of remaining
transfers is less than 2R. The setting of the next_useburst bit controls if the controller
performs an additional modification of the chnl_useburst_set [C] bit.
In peripheral scatter-gather DMA cycle then after the DMA cycle that uses the alternate
data structure completes, either:
0 = the controller does not change the value of the chnl_useburst_set [C] bit. If the
chnl_useburst_set [C] bit is 0 then for all the remaining DMA cycles in the peripheral
scattergather transaction, the controller responds to requests on dma_req[ ] and
dma_sreq[ ], when it performs a DMA cycle that uses an alternate data structure.
1 = the controller sets the chnl_useburst_set [C] bit to a 1. Therefore, for the remaining
DMA cycles in the peripheral scatter-gather transaction, the controller only responds to
requests on dma_req[ ], when it performs a DMA cycle that uses an alternate data struc-
ture.
[2:0] cycle_ctrl The operating mode of the DMA cycle. The modes are:
b000 Stop. Indicates that the data structure is invalid.
b001 Basic. The controller must receive a new request, prior to it enter-
ing the arbitration process, to enable the DMA cycle to complete.
b010 Auto-request. The controller automatically inserts a request for the
appropriate channel during the arbitration process. This means
that the initial request is sufficient to enable the DMA cycle to
complete.
b011 Ping-pong. The controller performs a DMA cycle using one of the
data structures. After the DMA cycle completes, it performs a
DMA cycle using the other data structure. After the DMA cycle
completes and provided that the host processor has updated the
original data structure, it performs a DMA cycle using the original
data structure. The controller continues to perform DMA cycles
until it either reads an invalid data structure or the host processor
changes the cycle_ctrl bits to b001 or b010. See 8.4.2.3.4 Ping-
Pong.
b100 Memory scatter/gather. See 8.4.2.3.5 Memory Scatter-Gather.
When the controller operates in memory scatter-gather mode, you
must only use this value in the primary data structure.
b101 Memory scatter/gather. See 8.4.2.3.5 Memory Scatter-Gather.
When the controller operates in memory scatter-gather mode, you
must only use this value in the alternate data structure.
b110 Peripheral scatter/gather. See 8.4.2.3.6 Peripheral Scatter-Gath-
er.
When the controller operates in peripheral scatter-gather mode,
you must only use this value in the primary data structure.
b111 Peripheral scatter/gather. See 8.4.2.3.6 Peripheral Scatter-Gath-
er.
When the controller operates in peripheral scatter-gather mode,
you must only use this value in the alternate data structure.
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At the start of a DMA cycle, or 2R DMA transfer, the controller fetches the channel_cfg from system memory. After it performs 2R, or N,
transfers it stores the updated channel_cfg in system memory.
The controller does not support a dst_size value that is different to the src_size value. If it detects a mismatch in these values, it uses
the src_size value for source and destination and when it next updates the n_minus_1 field, it also sets the dst_size field to the same as
the src_size field.
After the controller completes the N transfers it sets the cycle_ctrl field to b000, to indicate that the channel_cfg data is invalid. This
prevents it from repeating the same DMA transfer.
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8.4.3.4 Address Calculation
To calculate the source address of a DMA transfer, the controller performs a left shift operation on the n_minus_1 value by a shift
amount that src_inc specifies, and then subtracts the resulting value from the source data end pointer. Similarly, to calculate the desti-
nation address of a DMA transfer, it performs a left shift operation on the n_minus_1 value by a shift amount that dst_inc specifies, and
then subtracts the resulting value from the destination end pointer.
Depending on the value of src_inc and dst_inc, the source address and destination address can be calculated using the equations:
Pointer Values Equation
src_inc = b00 and dst_inc = b00 source address = src_data_end_ptr - n_minus_1
destination address = dst_data_end_ptr - n_minus_1
src_inc = b01 and dst_inc = b01 source address = src_data_end_ptr - (n_minus_1 << 1)
destination address = dst_data_end_ptr - (n_minus_1 << 1)
src_inc = b10 and dst_inc = b10 source address = src_data_end_ptr - (n_minus_1 << 2)
destination address = dst_data_end_ptr - (n_minus_1 << 2)
src_inc = b11 and dst_inc = b11 source address = src_data_end_ptr
destination address = dst_data_end_ptr
The following table lists the destination addresses for a DMA cycle of six words.
Table 8.10. DMA Cycle of Six Words Using a Word Increment
Initial values of channel_cfg, prior to the DMA cycle
src_size = b10, dst_inc = b10, n_minus_1 = b101, cycle_ctrl = 1
DMA transfers
End Pointer Count Difference1Address
0x2AC 5 0x14 0x298
0x2AC 4 0x10 0x29C
0x2AC 3 0xC 0x2A0
0x2AC 2 0x8 0x2A4
0x2AC 1 0x4 0x2A8
0x2AC 0 0x0 0x2AC
Final values of channel_cfg, after the DMA cycle
src_size = b10, dst_inc = b10, n_minus_1 = 0, cycle_ctrl = 0
Note:
1. This value is the result of count being shifted left by the value of dst_inc.
The following table lists the destination addresses for a DMA transfer of 12 bytes using a halfword increment.
Table 8.11. DMA Cycle of 12 Bytes Using a Halfword Increment
Initial values of channel_cfg, prior to the DMA cycle
src_size = b00, dst_inc = b01, n_minus_1 = b1011, cycle_ctrl = 1, R_power = b11
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DMA transfers
End Pointer Count Difference1Address
0x5E7 11 0x16 0x5D1
0x5E7 10 0x14 0x5D3
0x5E7 9 0x12 0x5D5
0x5E7 8 0x10 0x5D7
0x5E7 7 0xE 0x5D9
0x5E7 6 0xC 0x5DB
0x5E7 5 0xA 0x5DD
0x5E7 4 0x8 0x5DF
Values of channel_cfg after 2R DMA transfers
src_size = b00, dst_inc = b01, n_minus_1 = b011, cycle_ctrl = 1, R_power = b11
DMA transfers
End Pointer Count Difference Address
0x5E7 3 0x6 0x5E1
0x5E7 2 0x4 0x5E3
0x5E7 1 0x2 0x5E5
0x5E7 0 0x0 0x5E7
Final values of channel_cfg, after the DMA cycle
src_size = b00, dst_inc = b01, n_minus_1 = 0, cycle_ctrl = 0 2, R_power = b11
Note:
1. This value is the result of count being shifted left by the value of dst_inc.
2. After the controller completes the DMA cycle, it invalidates the channel_cfg memory location by clearing the cycle_ctrl field.
8.4.4 Looped Transfers
A regular DMA channel is done when it has performed the number of transfers given by the channel descriptor. If an application wants
a continuous flow of data, one option is to use ping-pong mode, alternating between two descriptors and having software update one
descriptor while the other is being used. Another way is to use looped transfers.
For DMA channels 0 and 1, looping can be enabled by setting EN in DMA_LOOP0 and DMA_LOOP1 respectively. A looping DMA
channel will on completion set the respective DONE interrupt flag, but then reload n_minus_1 in the channel descriptor with the loop
width defined by WIDTH in DMA_LOOPx and continue transmitting data.
The total length of the transfer is given by the original value of n_minus_1 in the channel descriptor and WIDTH in DMA_LOOPx times
the number of loops taken. The loop feature can for instance be used to implement a ring buffer, contiguously overwriting old data when
new data is available. To end the loop clear EN in DMA_LOOPx. The channel will then complete the last loop before stopping.
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W
8.4.5 2D Copy
In addition to looped transfers, DMA channel 0 has the ability to do rectangle transfers, or 2D copy. For an application working with
graphics, this would mean the ability to copy a rectangle of a given width and height from one picture to another. The DMA also has the
ability to copy from linear data to a rectangle, and from a rectangle to linear data.
To set up rectangle copy for DMA channel 0, configure WIDTH in DMA_LOOP0 to one less than the rectangle width, and HEIGHT in
DMA_RECT0 to one less than the rectangle height. Then set SRCSTRIDE in DMA_RECT0 to the outer rectangle width of the source,
and DSTSTRIDE in DMA_RECT0 to the outer rectangle width of the destination rectangle. Finally, the channel descriptor for channel 0
has to be configured. The source and destination end pointers should be set to the last element of the first line of the source data and
destination data respectively. The number of elements to be transferred, n_minus_1 should be set equal to WIDTH in DMA_LOOP0.
The parameters are visualized in Figure 8.9 2D Copy on page 107.
Source buffer Destination buffer
SRCSTRIDE DSTSTRIDE
WIDTH
HEIGHT
WIDTH
HEIGHT
Source end
pointer
Destination
end pointer
Figure 8.9. 2D Copy
When doing a rectangle copy, the source and destination address of the channel descriptor will be incremented line for line as the DMA
works its way through the rectangle. The operation is done when the number of lines specified by HEIGHT in DMA_RECT0 has been
copied. The source and destination addresses in the channel descriptor will then point at the last element of the source and destination
rectangles.
On completion, the DONE interrupt flag of channel 0 is set. Looping is not supported for rectangle copy.
In some cases, e.g. when performing graphics operations, it is desirable to create a list of copy operations and have them executed
automatically. This can be done using 2D copy together with the scatter gather mode of the DMA controller. Set DESCRECT in
DMA_CTRL to override SCRSTRIDE and HEIGHT in DMA_RECT0 and WIDTH in DMA_LOOP0 by the values in the user part of the
DMA descriptor as shown in the following table. In this way every copy command in the list can specify these parameters individually.
Table 8.12. User Data Assignments When DESCRECT is Set
Bit Field Description
[30:20] SRCSTRIDE Stride in source buffer
[19:10] HEIGHT Height - 1 of data to be copied
[9:0] WIDTH Width - 1 of data to be copied
With regular 2D copy, the DMA descriptor will be updated as the copy operation proceeds. To be able to reuse 2D copy scatter gather
list without rewriting source and destination end addresses, set PRDU in DMA_CTRL. This will prevent the address in the descriptor
from being updated. In this case RDSCH0 in DMA_RDS must be set and all other bits in DMA_RDS must be cleared. The bits in
DMA_RDS make individual DMA channels remember the source and destination end pointers while active, speeding up their transfers.
8.4.6 Interaction with the EMU
The DMA interacts with the Energy Management Unit (EMU) to allow transfers from , e.g., the LEUART to occur in EM2. The EMU can
wake up the DMA sufficiently long to allow data transfers to occur. See section "DMA Support" in the LEUART documentation.
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8.4.7 Interrupts
The PL230 dma_done[n:0] signals (one for each channel) as well as the dma_err signal, are available as interrupts to the Cortex-M4
core. They are combined into one interrupt vector, DMA_INT. If the interrupt for the DMA is enabled in the ARM Cortex-M4 core, an
interrupt will be made if one or more of the interrupt flags in DMA_IF and their corresponding bits in DMA_IEN are set.
8.4.8 Examples
A basic example of how to program the DMA for transferring 42 bytes from the USART1 to memory location 0x20003420. Assumes that
the channel 0 is currently disabled, and that the DMA_ALTCTRLBASE register has already been configured.
1. Configure the channel select for using USART1 with DMA channel 0
a. Write SOURCESEL=0b001101 and SIGSEL=XX to DMA_CHCTRL0
2. Configure the primary channel descriptor for DMA channel 0
a. Write XX (read address of USART1) to src_data_end_ptr
b. Write 0x20003420 + 40 to dst_data_end_ptr c
c. Write these values to channel_cfg for channel 0:
i. dst_inc=b01 (destination halfword address increment)
ii. dst_size=b01 (halfword transfer size)
iii. src_inc=b11 (no address increment for source)
iv. src_size=01 (halfword transfer size)
v. dst_prot_ctrl=000 (no cache/buffer/privilege)
vi. src_prot_ctrl=000 (no cache/buffer/privilege)
vii. R_power=b0000 (arbitrate after each DMA transfer)
viii. n_minus_1=d20 (transfer 21 halfwords)
ix. next_useburst=b0 (not applicable)
x. cycle_ctrl=b001 (basic operating mode)
3. Enable the DMA
a. Write EN=1 to DMA_CONFIG
4. Disable the single requests for channel 0 (i.e., do not react to data available, wait for buffer full)
a. Write DMA_CHUSEBURSTS[0]=1
5. Enable buffer-full requests for channel 0
a. Write DMA_CHREQMASKC[0]=1
6. Use the primary data structure for channel 0
a. Write DMA_CHALTC[0]=1
7. Enable channel 0
a. Write DMA_CHENS[0]=1
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8.5 Register Map
The offset register address is relative to the registers base address.
Offset Name Type Description
0x000 DMA_STATUS RDMA Status Registers
0x004 DMA_CONFIG WDMA Configuration Register
0x008 DMA_CTRLBASE RW Channel Control Data Base Pointer Register
0x00C DMA_ALTCTRLBASE RChannel Alternate Control Data Base Pointer Register
0x010 DMA_CHWAITSTATUS RChannel Wait on Request Status Register
0x014 DMA_CHSWREQ W1 Channel Software Request Register
0x018 DMA_CHUSEBURSTS RW1H Channel Useburst Set Register
0x01C DMA_CHUSEBURSTC W1 Channel Useburst Clear Register
0x020 DMA_CHREQMASKS RW1 Channel Request Mask Set Register
0x024 DMA_CHREQMASKC W1 Channel Request Mask Clear Register
0x028 DMA_CHENS RW1 Channel Enable Set Register
0x02C DMA_CHENC W1 Channel Enable Clear Register
0x030 DMA_CHALTS RW1 Channel Alternate Set Register
0x034 DMA_CHALTC W1 Channel Alternate Clear Register
0x038 DMA_CHPRIS RW1 Channel Priority Set Register
0x03C DMA_CHPRIC W1 Channel Priority Clear Register
0x04C DMA_ERRORC RW Bus Error Clear Register
0xE10 DMA_CHREQSTATUS RChannel Request Status
0xE18 DMA_CHSREQSTATUS RChannel Single Request Status
0x1000 DMA_IF RInterrupt Flag Register
0x1004 DMA_IFS W1 Interrupt Flag Set Register
0x1008 DMA_IFC (R)W1 Interrupt Flag Clear Register
0x100C DMA_IEN RW Interrupt Enable register
0x1010 DMA_CTRL RW DMA Control Register
0x1014 DMA_RDS RW DMA Retain Descriptor State
0x1020 DMA_LOOP0 RWH Channel 0 Loop Register
0x1024 DMA_LOOP1 RW Channel 1 Loop Register
0x1060 DMA_RECT0 RWH Channel 0 Rectangle Register
0x1100 DMA_CH0_CTRL RW Channel Control Register
... DMA_CHx_CTRL RW Channel Control Register
0x112C DMA_CH11_CTRL RW Channel Control Register
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8.6 Register Description
8.6.1 DMA_STATUS - DMA Status Registers
Offset Bit Position
0x000
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
16
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
Reset
0x0B
0x0
0
Access
R
R
R
Name
CHNUM
STATE
EN
Bit Name Reset Access Description
31:21 Reserved To ensure compatibility with future devices, always write bits to 0. More information in 2.1 Conven-
tions.
20:16 CHNUM 0x0B R Channel Number
Number of available DMA channels minus one.
15:8 Reserved To ensure compatibility with future devices, always write bits to 0. More information in 2.1 Conven-
tions.
7:4 STATE 0x0 R Control Current State
State can be one of the following. Higher values (11-15) are undefined.
Value Mode Description
0 IDLE Idle
1 RDCHCTRLDATA Reading channel controller data
2 RDSRCENDPTR Reading source data end pointer
3 RDDSTENDPTR Reading destination data end pointer
4 RDSRCDATA Reading source data
5 WRDSTDATA Writing destination data
6 WAITREQCLR Waiting for DMA request to clear
7 WRCHCTRLDATA Writing channel controller data
8 STALLED Stalled
9 DONE Done
10 PERSCATTRANS Peripheral scatter-gather transition
3:1 Reserved To ensure compatibility with future devices, always write bits to 0. More information in 2.1 Conven-
tions.
0 EN 0 R DMA Enable Status
When this bit is 1, the DMA is enabled.
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8.6.2 DMA_CONFIG - DMA Configuration Register
Offset Bit Position
0x004
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
16
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
Reset
0
0
Access
W
W
Name
CHPROT
EN
Bit Name Reset Access Description
31:6 Reserved To ensure compatibility with future devices, always write bits to 0. More information in 2.1 Conven-
tions.
5 CHPROT 0 W Channel Protection Control
Control whether accesses done by the DMA controller are privileged or not. When CHPROT = 1 then HPROT is HIGH and
the access is privileged. When CHPROT = 0 then HPROT is LOW and the access is non-privileged.
4:1 Reserved To ensure compatibility with future devices, always write bits to 0. More information in 2.1 Conven-
tions.
0 EN 0 W Enable DMA
Set this bit to enable the DMA controller.
8.6.3 DMA_CTRLBASE - Channel Control Data Base Pointer Register
Offset Bit Position
0x008
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
16
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
Reset
0x00000000
Access
RW
Name
CTRLBASE
Bit Name Reset Access Description
31:0 CTRLBASE 0x00000000 RW Channel Control Data Base Pointer
The base pointer for a location in system memory that holds the channel control data structure. This register must be writ-
ten to point to a location in system memory with the channel control data structure before the DMA can be used. Note that
ctrl_base_ptr[8:0] must be 0.
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8.6.4 DMA_ALTCTRLBASE - Channel Alternate Control Data Base Pointer Register
Offset Bit Position
0x00C
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
16
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
Reset
0x00000100
Access
R
Name
ALTCTRLBASE
Bit Name Reset Access Description
31:0 ALTCTRLBASE 0x00000100 R Channel Alternate Control Data Base Pointer
The base address of the alternate data structure. This register will read as DMA_CTRLBASE + 0x100.
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8.6.5 DMA_CHWAITSTATUS - Channel Wait on Request Status Register
Offset Bit Position
0x010
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
16
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
Reset
1
1
1
1
1
1
1
1
1
1
1
1
Access
R
R
R
R
R
R
R
R
R
R
R
R
Name
CH11WAITSTATUS
CH10WAITSTATUS
CH9WAITSTATUS
CH8WAITSTATUS
CH7WAITSTATUS
CH6WAITSTATUS
CH5WAITSTATUS
CH4WAITSTATUS
CH3WAITSTATUS
CH2WAITSTATUS
CH1WAITSTATUS
CH0WAITSTATUS
Bit Name Reset Access Description
31:12 Reserved To ensure compatibility with future devices, always write bits to 0. More information in 2.1 Conven-
tions.
11 CH11WAITSTATUS 1 R Channel 11 Wait on Request Status
Status for wait on request for channel 11.
10 CH10WAITSTATUS 1 R Channel 10 Wait on Request Status
Status for wait on request for channel 10.
9 CH9WAITSTATUS 1 R Channel 9 Wait on Request Status
Status for wait on request for channel 9.
8 CH8WAITSTATUS 1 R Channel 8 Wait on Request Status
Status for wait on request for channel 8.
7 CH7WAITSTATUS 1 R Channel 7 Wait on Request Status
Status for wait on request for channel 7.
6 CH6WAITSTATUS 1 R Channel 6 Wait on Request Status
Status for wait on request for channel 6.
5 CH5WAITSTATUS 1 R Channel 5 Wait on Request Status
Status for wait on request for channel 5.
4 CH4WAITSTATUS 1 R Channel 4 Wait on Request Status
Status for wait on request for channel 4.
3 CH3WAITSTATUS 1 R Channel 3 Wait on Request Status
Status for wait on request for channel 3.
2 CH2WAITSTATUS 1 R Channel 2 Wait on Request Status
Status for wait on request for channel 2.
1 CH1WAITSTATUS 1 R Channel 1 Wait on Request Status
Status for wait on request for channel 1.
0 CH0WAITSTATUS 1 R Channel 0 Wait on Request Status
Status for wait on request for channel 0.
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8.6.6 DMA_CHSWREQ - Channel Software Request Register
Offset Bit Position
0x014
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
16
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
Reset
0
0
0
0
0
0
0
0
0
0
0
0
Access
W1
W1
W1
W1
W1
W1
W1
W1
W1
W1
W1
W1
Name
CH11SWREQ
CH10SWREQ
CH9SWREQ
CH8SWREQ
CH7SWREQ
CH6SWREQ
CH5SWREQ
CH4SWREQ
CH3SWREQ
CH2SWREQ
CH1SWREQ
CH0SWREQ
Bit Name Reset Access Description
31:12 Reserved To ensure compatibility with future devices, always write bits to 0. More information in 2.1 Conven-
tions.
11 CH11SWREQ 0 W1 Channel 11 Software Request
Write 1 to this bit to generate a DMA request for this channel.
10 CH10SWREQ 0 W1 Channel 10 Software Request
Write 1 to this bit to generate a DMA request for this channel.
9 CH9SWREQ 0 W1 Channel 9 Software Request
Write 1 to this bit to generate a DMA request for this channel.
8 CH8SWREQ 0 W1 Channel 8 Software Request
Write 1 to this bit to generate a DMA request for this channel.
7 CH7SWREQ 0 W1 Channel 7 Software Request
Write 1 to this bit to generate a DMA request for this channel.
6 CH6SWREQ 0 W1 Channel 6 Software Request
Write 1 to this bit to generate a DMA request for this channel.
5 CH5SWREQ 0 W1 Channel 5 Software Request
Write 1 to this bit to generate a DMA request for this channel.
4 CH4SWREQ 0 W1 Channel 4 Software Request
Write 1 to this bit to generate a DMA request for this channel.
3 CH3SWREQ 0 W1 Channel 3 Software Request
Write 1 to this bit to generate a DMA request for this channel.
2 CH2SWREQ 0 W1 Channel 2 Software Request
Write 1 to this bit to generate a DMA request for this channel.
1 CH1SWREQ 0 W1 Channel 1 Software Request
Write 1 to this bit to generate a DMA request for this channel.
0 CH0SWREQ 0 W1 Channel 0 Software Request
Write 1 to this bit to generate a DMA request for this channel.
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8.6.7 DMA_CHUSEBURSTS - Channel Useburst Set Register
Offset Bit Position
0x018
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
16
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
Reset
0
0
0
0
0
0
0
0
0
0
0
0
Access
RW1H
RW1H
RW1H
RW1H
RW1H
RW1H
RW1H
RW1H
RW1H
RW1H
RW1H
RW1H
Name
CH11USEBURSTS
CH10USEBURSTS
CH9USEBURSTS
CH8USEBURSTS
CH7USEBURSTS
CH6USEBURSTS
CH5USEBURSTS
CH4USEBURSTS
CH3USEBURSTS
CH2USEBURSTS
CH1USEBURSTS
CH0USEBURSTS
Bit Name Reset Access Description
31:12 Reserved To ensure compatibility with future devices, always write bits to 0. More information in 2.1 Conven-
tions.
11 CH11USEBURSTS 0 RW1H Channel 11 Useburst Set
See description for channel 0.
10 CH10USEBURSTS 0 RW1H Channel 10 Useburst Set
See description for channel 0.
9 CH9USEBURSTS 0 RW1H Channel 9 Useburst Set
See description for channel 0.
8 CH8USEBURSTS 0 RW1H Channel 8 Useburst Set
See description for channel 0.
7 CH7USEBURSTS 0 RW1H Channel 7 Useburst Set
See description for channel 0.
6 CH6USEBURSTS 0 RW1H Channel 6 Useburst Set
See description for channel 0.
5 CH5USEBURSTS 0 RW1H Channel 5 Useburst Set
See description for channel 0.
4 CH4USEBURSTS 0 RW1H Channel 4 Useburst Set
See description for channel 0.
3 CH3USEBURSTS 0 RW1H Channel 3 Useburst Set
See description for channel 0.
2 CH2USEBURSTS 0 RW1H Channel 2 Useburst Set
See description for channel 0.
1 CH1USEBURSTS 0 RW1H Channel 1 Useburst Set
See description for channel 0.
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Bit Name Reset Access Description
0 CH0USEBURSTS 0 RW1H Channel 0 Useburst Set
Write to 1 to enable the useburst setting for this channel. Reading returns the useburst status. After the penultimate 2^R
transfer completes, if the number of remaining transfers, N, is less than 2^R then the controller resets the chnl_use-
burst_set bit to 0. This enables you to complete the remaining transfers using dma_req[] or dma_sreq[]. In peripheral scat-
ter-gather mode, if the next_useburst bit is set in channel_cfg then the controller sets the chnl_useburst_set[C] bit to a 1,
when it completes the DMA cycle that uses the alternate data structure.
Value Mode Description
0 SINGLEANDBURST Channel responds to both single and burst requests
1 BURSTONLY Channel responds to burst requests only
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8.6.8 DMA_CHUSEBURSTC - Channel Useburst Clear Register
Offset Bit Position
0x01C
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
16
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
Reset
0
0
0
0
0
0
0
0
0
0
0
0
Access
W1
W1
W1
W1
W1
W1
W1
W1
W1
W1
W1
W1
Name
CH11USEBURSTC
CH10USEBURSTC
CH9USEBURSTC
CH08USEBURSTC
CH7USEBURSTC
CH6USEBURSTC
CH5USEBURSTC
CH4USEBURSTC
CH3USEBURSTC
CH2USEBURSTC
CH1USEBURSTC
CH0USEBURSTC
Bit Name Reset Access Description
31:12 Reserved To ensure compatibility with future devices, always write bits to 0. More information in 2.1 Conven-
tions.
11 CH11USEBURSTC 0 W1 Channel 11 Useburst Clear
Write to 1 to disable useburst setting for this channel.
10 CH10USEBURSTC 0 W1 Channel 10 Useburst Clear
Write to 1 to disable useburst setting for this channel.
9 CH9USEBURSTC 0 W1 Channel 9 Useburst Clear
Write to 1 to disable useburst setting for this channel.
8 CH08USEBURSTC 0 W1 Channel 8 Useburst Clear
Write to 1 to disable useburst setting for this channel.
7 CH7USEBURSTC 0 W1 Channel 7 Useburst Clear
Write to 1 to disable useburst setting for this channel.
6 CH6USEBURSTC 0 W1 Channel 6 Useburst Clear
Write to 1 to disable useburst setting for this channel.
5 CH5USEBURSTC 0 W1 Channel 5 Useburst Clear
Write to 1 to disable useburst setting for this channel.
4 CH4USEBURSTC 0 W1 Channel 4 Useburst Clear
Write to 1 to disable useburst setting for this channel.
3 CH3USEBURSTC 0 W1 Channel 3 Useburst Clear
Write to 1 to disable useburst setting for this channel.
2 CH2USEBURSTC 0 W1 Channel 2 Useburst Clear
Write to 1 to disable useburst setting for this channel.
1 CH1USEBURSTC 0 W1 Channel 1 Useburst Clear
Write to 1 to disable useburst setting for this channel.
0 CH0USEBURSTC 0 W1 Channel 0 Useburst Clear
Write to 1 to disable useburst setting for this channel.
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8.6.9 DMA_CHREQMASKS - Channel Request Mask Set Register
Offset Bit Position
0x020
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
16
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
Reset
0
0
0
0
0
0
0
0
0
0
0
0
Access
RW1
RW1
RW1
RW1
RW1
RW1
RW1
RW1
RW1
RW1
RW1
RW1
Name
CH11REQMASKS
CH10REQMASKS
CH9REQMASKS
CH8REQMASKS
CH7REQMASKS
CH6REQMASKS
CH5REQMASKS
CH4REQMASKS
CH3REQMASKS
CH2REQMASKS
CH1REQMASKS
CH0REQMASKS
Bit Name Reset Access Description
31:12 Reserved To ensure compatibility with future devices, always write bits to 0. More information in 2.1 Conven-
tions.
11 CH11REQMASKS 0 RW1 Channel 11 Request Mask Set
Write to 1 to disable peripheral requests for this channel.
10 CH10REQMASKS 0 RW1 Channel 10 Request Mask Set
Write to 1 to disable peripheral requests for this channel.
9 CH9REQMASKS 0 RW1 Channel 9 Request Mask Set
Write to 1 to disable peripheral requests for this channel.
8 CH8REQMASKS 0 RW1 Channel 8 Request Mask Set
Write to 1 to disable peripheral requests for this channel.
7 CH7REQMASKS 0 RW1 Channel 7 Request Mask Set
Write to 1 to disable peripheral requests for this channel.
6 CH6REQMASKS 0 RW1 Channel 6 Request Mask Set
Write to 1 to disable peripheral requests for this channel.
5 CH5REQMASKS 0 RW1 Channel 5 Request Mask Set
Write to 1 to disable peripheral requests for this channel.
4 CH4REQMASKS 0 RW1 Channel 4 Request Mask Set
Write to 1 to disable peripheral requests for this channel.
3 CH3REQMASKS 0 RW1 Channel 3 Request Mask Set
Write to 1 to disable peripheral requests for this channel.
2 CH2REQMASKS 0 RW1 Channel 2 Request Mask Set
Write to 1 to disable peripheral requests for this channel.
1 CH1REQMASKS 0 RW1 Channel 1 Request Mask Set
Write to 1 to disable peripheral requests for this channel.
0 CH0REQMASKS 0 RW1 Channel 0 Request Mask Set
Write to 1 to disable peripheral requests for this channel.
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8.6.10 DMA_CHREQMASKC - Channel Request Mask Clear Register
Offset Bit Position
0x024
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
16
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
Reset
0
0
0
0
0
0
0
0
0
0
0
0
Access
W1
W1
W1
W1
W1
W1
W1
W1
W1
W1
W1
W1
Name
CH11REQMASKC
CH10REQMASKC
CH9REQMASKC
CH8REQMASKC
CH7REQMASKC
CH6REQMASKC
CH5REQMASKC
CH4REQMASKC
CH3REQMASKC
CH2REQMASKC
CH1REQMASKC
CH0REQMASKC
Bit Name Reset Access Description
31:12 Reserved To ensure compatibility with future devices, always write bits to 0. More information in 2.1 Conven-
tions.
11 CH11REQMASKC 0 W1 Channel 11 Request Mask Clear
Write to 1 to enable peripheral requests for this channel.
10 CH10REQMASKC 0 W1 Channel 10 Request Mask Clear
Write to 1 to enable peripheral requests for this channel.
9 CH9REQMASKC 0 W1 Channel 9 Request Mask Clear
Write to 1 to enable peripheral requests for this channel.
8 CH8REQMASKC 0 W1 Channel 8 Request Mask Clear
Write to 1 to enable peripheral requests for this channel.
7 CH7REQMASKC 0 W1 Channel 7 Request Mask Clear
Write to 1 to enable peripheral requests for this channel.
6 CH6REQMASKC 0 W1 Channel 6 Request Mask Clear
Write to 1 to enable peripheral requests for this channel.
5 CH5REQMASKC 0 W1 Channel 5 Request Mask Clear
Write to 1 to enable peripheral requests for this channel.
4 CH4REQMASKC 0 W1 Channel 4 Request Mask Clear
Write to 1 to enable peripheral requests for this channel.
3 CH3REQMASKC 0 W1 Channel 3 Request Mask Clear
Write to 1 to enable peripheral requests for this channel.
2 CH2REQMASKC 0 W1 Channel 2 Request Mask Clear
Write to 1 to enable peripheral requests for this channel.
1 CH1REQMASKC 0 W1 Channel 1 Request Mask Clear
Write to 1 to enable peripheral requests for this channel.
0 CH0REQMASKC 0 W1 Channel 0 Request Mask Clear
Write to 1 to enable peripheral requests for this channel.
EFM32WG Reference Manual
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8.6.11 DMA_CHENS - Channel Enable Set Register
Offset Bit Position
0x028
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
16
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
Reset
0
0
0
0
0
0
0
0
0
0
0
0
Access
RW1
RW1
RW1
RW1
RW1
RW1
RW1
RW1
RW1
RW1
RW1
RW1
Name
CH11ENS
CH10ENS
CH9ENS
CH8ENS
CH7ENS
CH6ENS
CH5ENS
CH4ENS
CH3ENS
CH2ENS
CH1ENS
CH0ENS
Bit Name Reset Access Description
31:12 Reserved To ensure compatibility with future devices, always write bits to 0. More information in 2.1 Conven-
tions.
11 CH11ENS 0 RW1 Channel 11 Enable Set
Write to 1 to enable this channel. Reading returns the enable status of the channel.
10 CH10ENS 0 RW1 Channel 10 Enable Set
Write to 1 to enable this channel. Reading returns the enable status of the channel.
9 CH9ENS 0 RW1 Channel 9 Enable Set
Write to 1 to enable this channel. Reading returns the enable status of the channel.
8 CH8ENS 0 RW1 Channel 8 Enable Set
Write to 1 to enable this channel. Reading returns the enable status of the channel.
7 CH7ENS 0 RW1 Channel 7 Enable Set
Write to 1 to enable this channel. Reading returns the enable status of the channel.
6 CH6ENS 0 RW1 Channel 6 Enable Set
Write to 1 to enable this channel. Reading returns the enable status of the channel.
5 CH5ENS 0 RW1 Channel 5 Enable Set
Write to 1 to enable this channel. Reading returns the enable status of the channel.
4 CH4ENS 0 RW1 Channel 4 Enable Set
Write to 1 to enable this channel. Reading returns the enable status of the channel.
3 CH3ENS 0 RW1 Channel 3 Enable Set
Write to 1 to enable this channel. Reading returns the enable status of the channel.
2 CH2ENS 0 RW1 Channel 2 Enable Set
Write to 1 to enable this channel. Reading returns the enable status of the channel.
1 CH1ENS 0 RW1 Channel 1 Enable Set
Write to 1 to enable this channel. Reading returns the enable status of the channel.
0 CH0ENS 0 RW1 Channel 0 Enable Set
Write to 1 to enable this channel. Reading returns the enable status of the channel.
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8.6.12 DMA_CHENC - Channel Enable Clear Register
Offset Bit Position
0x02C
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
16
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
Reset
0
0
0
0
0
0
0
0
0
0
0
0
Access
W1
W1
W1
W1
W1
W1
W1
W1
W1
W1
W1
W1
Name
CH11ENC
CH10ENC
CH9ENC
CH8ENC
CH7ENC
CH6ENC
CH5ENC
CH4ENC
CH3ENC
CH2ENC
CH1ENC
CH0ENC
Bit Name Reset Access Description
31:12 Reserved To ensure compatibility with future devices, always write bits to 0. More information in 2.1 Conven-
tions.
11 CH11ENC 0 W1 Channel 11 Enable Clear
Write to 1 to disable this channel. See also description for channel 0.
10 CH10ENC 0 W1 Channel 10 Enable Clear
Write to 1 to disable this channel. See also description for channel 0.
9 CH9ENC 0 W1 Channel 9 Enable Clear
Write to 1 to disable this channel. See also description for channel 0.
8 CH8ENC 0 W1 Channel 8 Enable Clear
Write to 1 to disable this channel. See also description for channel 0.
7 CH7ENC 0 W1 Channel 7 Enable Clear
Write to 1 to disable this channel. See also description for channel 0.
6 CH6ENC 0 W1 Channel 6 Enable Clear
Write to 1 to disable this channel. See also description for channel 0.
5 CH5ENC 0 W1 Channel 5 Enable Clear
Write to 1 to disable this channel. See also description for channel 0.
4 CH4ENC 0 W1 Channel 4 Enable Clear
Write to 1 to disable this channel. See also description for channel 0.
3 CH3ENC 0 W1 Channel 3 Enable Clear
Write to 1 to disable this channel. See also description for channel 0.
2 CH2ENC 0 W1 Channel 2 Enable Clear
Write to 1 to disable this channel. See also description for channel 0.
1 CH1ENC 0 W1 Channel 1 Enable Clear
Write to 1 to disable this channel. See also description for channel 0.
0 CH0ENC 0 W1 Channel 0 Enable Clear
Write to 1 to disable this channel. Note that the controller disables a channel, by setting the appropriate bit, when either it
completes the DMA cycle, or it reads a channel_cfg memory location which has cycle_ctrl = b000, or an ERROR occurs on
the AHB-Lite bus. A read from this field returns the value of CH0ENS from the DMA_CHENS register.
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DMA - DMA Controller
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8.6.13 DMA_CHALTS - Channel Alternate Set Register
Offset Bit Position
0x030
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
16
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
Reset
0
0
0
0
0
0
0
0
0
0
0
0
Access
RW1
RW1
RW1
RW1
RW1
RW1
RW1
RW1
RW1
RW1
RW1
RW1
Name
CH11ALTS
CH10ALTS
CH9ALTS
CH8ALTS
CH7ALTS
CH6ALTS
CH5ALTS
CH4ALTS
CH3ALTS
CH2ALTS
CH1ALTS
CH0ALTS
Bit Name Reset Access Description
31:12 Reserved To ensure compatibility with future devices, always write bits to 0. More information in 2.1 Conven-
tions.
11 CH11ALTS 0 RW1 Channel 11 Alternate Structure Set
Write to 1 to select the alternate structure for this channel.
10 CH10ALTS 0 RW1 Channel 10 Alternate Structure Set
Write to 1 to select the alternate structure for this channel.
9 CH9ALTS 0 RW1 Channel 9 Alternate Structure Set
Write to 1 to select the alternate structure for this channel.
8 CH8ALTS 0 RW1 Channel 8 Alternate Structure Set
Write to 1 to select the alternate structure for this channel.
7 CH7ALTS 0 RW1 Channel 7 Alternate Structure Set
Write to 1 to select the alternate structure for this channel.
6 CH6ALTS 0 RW1 Channel 6 Alternate Structure Set
Write to 1 to select the alternate structure for this channel.
5 CH5ALTS 0 RW1 Channel 5 Alternate Structure Set
Write to 1 to select the alternate structure for this channel.
4 CH4ALTS 0 RW1 Channel 4 Alternate Structure Set
Write to 1 to select the alternate structure for this channel.
3 CH3ALTS 0 RW1 Channel 3 Alternate Structure Set
Write to 1 to select the alternate structure for this channel.
2 CH2ALTS 0 RW1 Channel 2 Alternate Structure Set
Write to 1 to select the alternate structure for this channel.
1 CH1ALTS 0 RW1 Channel 1 Alternate Structure Set
Write to 1 to select the alternate structure for this channel.
0 CH0ALTS 0 RW1 Channel 0 Alternate Structure Set
Write to 1 to select the alternate structure for this channel.
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8.6.14 DMA_CHALTC - Channel Alternate Clear Register
Offset Bit Position
0x034
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
16
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
Reset
0
0
0
0
0
0
0
0
0
0
0
0
Access
W1
W1
W1
W1
W1
W1
W1
W1
W1
W1
W1
W1
Name
CH11ALTC
CH10ALTC
CH9ALTC
CH8ALTC
CH7ALTC
CH6ALTC
CH5ALTC
CH4ALTC
CH3ALTC
CH2ALTC
CH1ALTC
CH0ALTC
Bit Name Reset Access Description
31:12 Reserved To ensure compatibility with future devices, always write bits to 0. More information in 2.1 Conven-
tions.
11 CH11ALTC 0 W1 Channel 11 Alternate Clear
Write to 1 to select the primary structure for this channel.
10 CH10ALTC 0 W1 Channel 10 Alternate Clear
Write to 1 to select the primary structure for this channel.
9 CH9ALTC 0 W1 Channel 9 Alternate Clear
Write to 1 to select the primary structure for this channel.
8 CH8ALTC 0 W1 Channel 8 Alternate Clear
Write to 1 to select the primary structure for this channel.
7 CH7ALTC 0 W1 Channel 7 Alternate Clear
Write to 1 to select the primary structure for this channel.
6 CH6ALTC 0 W1 Channel 6 Alternate Clear
Write to 1 to select the primary structure for this channel.
5 CH5ALTC 0 W1 Channel 5 Alternate Clear
Write to 1 to select the primary structure for this channel.
4 CH4ALTC 0 W1 Channel 4 Alternate Clear
Write to 1 to select the primary structure for this channel.
3 CH3ALTC 0 W1 Channel 3 Alternate Clear
Write to 1 to select the primary structure for this channel.
2 CH2ALTC 0 W1 Channel 2 Alternate Clear
Write to 1 to select the primary structure for this channel.
1 CH1ALTC 0 W1 Channel 1 Alternate Clear
Write to 1 to select the primary structure for this channel.
0 CH0ALTC 0 W1 Channel 0 Alternate Clear
Write to 1 to select the primary structure for this channel.
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8.6.15 DMA_CHPRIS - Channel Priority Set Register
Offset Bit Position
0x038
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
16
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
Reset
0
0
0
0
0
0
0
0
0
0
0
0
Access
RW1
RW1
RW1
RW1
RW1
RW1
RW1
RW1
RW1
RW1
RW1
RW1
Name
CH11PRIS
CH10PRIS
CH9PRIS
CH8PRIS
CH7PRIS
CH6PRIS
CH5PRIS
CH4PRIS
CH3PRIS
CH2PRIS
CH1PRIS
CH0PRIS
Bit Name Reset Access Description
31:12 Reserved To ensure compatibility with future devices, always write bits to 0. More information in 2.1 Conven-
tions.
11 CH11PRIS 0 RW1 Channel 11 High Priority Set
Write to 1 to obtain high priority for this channel. Reading returns the channel priority status.
10 CH10PRIS 0 RW1 Channel 10 High Priority Set
Write to 1 to obtain high priority for this channel. Reading returns the channel priority status.
9 CH9PRIS 0 RW1 Channel 9 High Priority Set
Write to 1 to obtain high priority for this channel. Reading returns the channel priority status.
8 CH8PRIS 0 RW1 Channel 8 High Priority Set
Write to 1 to obtain high priority for this channel. Reading returns the channel priority status.
7 CH7PRIS 0 RW1 Channel 7 High Priority Set
Write to 1 to obtain high priority for this channel. Reading returns the channel priority status.
6 CH6PRIS 0 RW1 Channel 6 High Priority Set
Write to 1 to obtain high priority for this channel. Reading returns the channel priority status.
5 CH5PRIS 0 RW1 Channel 5 High Priority Set
Write to 1 to obtain high priority for this channel. Reading returns the channel priority status.
4 CH4PRIS 0 RW1 Channel 4 High Priority Set
Write to 1 to obtain high priority for this channel. Reading returns the channel priority status.
3 CH3PRIS 0 RW1 Channel 3 High Priority Set
Write to 1 to obtain high priority for this channel. Reading returns the channel priority status.
2 CH2PRIS 0 RW1 Channel 2 High Priority Set
Write to 1 to obtain high priority for this channel. Reading returns the channel priority status.
1 CH1PRIS 0 RW1 Channel 1 High Priority Set
Write to 1 to obtain high priority for this channel. Reading returns the channel priority status.
0 CH0PRIS 0 RW1 Channel 0 High Priority Set
Write to 1 to obtain high priority for this channel. Reading returns the channel priority status.
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8.6.16 DMA_CHPRIC - Channel Priority Clear Register
Offset Bit Position
0x03C
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
16
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
Reset
0
0
0
0
0
0
0
0
0
0
0
0
Access
W1
W1
W1
W1
W1
W1
W1
W1
W1
W1
W1
W1
Name
CH11PRIC
CH10PRIC
CH9PRIC
CH8PRIC
CH7PRIC
CH6PRIC
CH5PRIC
CH4PRIC
CH3PRIC
CH2PRIC
CH1PRIC
CH0PRIC
Bit Name Reset Access Description
31:12 Reserved To ensure compatibility with future devices, always write bits to 0. More information in 2.1 Conven-
tions.
11 CH11PRIC 0 W1 Channel 11 High Priority Clear
Write to 1 to clear high priority for this channel.
10 CH10PRIC 0 W1 Channel 10 High Priority Clear
Write to 1 to clear high priority for this channel.
9 CH9PRIC 0 W1 Channel 9 High Priority Clear
Write to 1 to clear high priority for this channel.
8 CH8PRIC 0 W1 Channel 8 High Priority Clear
Write to 1 to clear high priority for this channel.
7 CH7PRIC 0 W1 Channel 7 High Priority Clear
Write to 1 to clear high priority for this channel.
6 CH6PRIC 0 W1 Channel 6 High Priority Clear
Write to 1 to clear high priority for this channel.
5 CH5PRIC 0 W1 Channel 5 High Priority Clear
Write to 1 to clear high priority for this channel.
4 CH4PRIC 0 W1 Channel 4 High Priority Clear
Write to 1 to clear high priority for this channel.
3 CH3PRIC 0 W1 Channel 3 High Priority Clear
Write to 1 to clear high priority for this channel.
2 CH2PRIC 0 W1 Channel 2 High Priority Clear
Write to 1 to clear high priority for this channel.
1 CH1PRIC 0 W1 Channel 1 High Priority Clear
Write to 1 to clear high priority for this channel.
0 CH0PRIC 0 W1 Channel 0 High Priority Clear
Write to 1 to clear high priority for this channel.
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8.6.17 DMA_ERRORC - Bus Error Clear Register
Offset Bit Position
0x04C
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
16
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
Reset
0
Access
RW
Name
ERRORC
Bit Name Reset Access Description
31:1 Reserved To ensure compatibility with future devices, always write bits to 0. More information in 2.1 Conven-
tions.
0 ERRORC 0 RW Bus Error Clear
This bit is set high if an AHB bus error has occurred. Writing a 1 to this bit will clear the bit. If the error is deasserted at the
same time as an error occurs on the bus, the error condition takes precedence and ERRORC remains asserted.
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8.6.18 DMA_CHREQSTATUS - Channel Request Status
Offset Bit Position
0xE10
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
16
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
Reset
0
0
0
0
0
0
0
0
0
0
0
0
Access
R
R
R
R
R
R
R
R
R
R
R
R
Name
CH11REQSTATUS
CH10REQSTATUS
CH9REQSTATUS
CH8REQSTATUS
CH7REQSTATUS
CH6REQSTATUS
CH5REQSTATUS
CH4REQSTATUS
CH3REQSTATUS
CH2REQSTATUS
CH1REQSTATUS
CH0REQSTATUS
Bit Name Reset Access Description
31:12 Reserved To ensure compatibility with future devices, always write bits to 0. More information in 2.1 Conven-
tions.
11 CH11REQSTATUS 0 R Channel 11 Request Status
When this bit is 1, it indicates that the peripheral connected as the input to this DMA channel is requesting the controller to
service the DMA channel. The controller services the request by performing the DMA cycle using 2R DMA transfers.
10 CH10REQSTATUS 0 R Channel 10 Request Status
When this bit is 1, it indicates that the peripheral connected as the input to this DMA channel is requesting the controller to
service the DMA channel. The controller services the request by performing the DMA cycle using 2R DMA transfers.
9 CH9REQSTATUS 0 R Channel 9 Request Status
When this bit is 1, it indicates that the peripheral connected as the input to this DMA channel is requesting the controller to
service the DMA channel. The controller services the request by performing the DMA cycle using 2R DMA transfers.
8 CH8REQSTATUS 0 R Channel 8 Request Status
When this bit is 1, it indicates that the peripheral connected as the input to this DMA channel is requesting the controller to
service the DMA channel. The controller services the request by performing the DMA cycle using 2R DMA transfers.
7 CH7REQSTATUS 0 R Channel 7 Request Status
When this bit is 1, it indicates that the peripheral connected as the input to this DMA channel is requesting the controller to
service the DMA channel. The controller services the request by performing the DMA cycle using 2R DMA transfers.
6 CH6REQSTATUS 0 R Channel 6 Request Status
When this bit is 1, it indicates that the peripheral connected as the input to this DMA channel is requesting the controller to
service the DMA channel. The controller services the request by performing the DMA cycle using 2R DMA transfers.
5 CH5REQSTATUS 0 R Channel 5 Request Status
When this bit is 1, it indicates that the peripheral connected as the input to this DMA channel is requesting the controller to
service the DMA channel. The controller services the request by performing the DMA cycle using 2R DMA transfers.
4 CH4REQSTATUS 0 R Channel 4 Request Status
When this bit is 1, it indicates that the peripheral connected as the input to this DMA channel is requesting the controller to
service the DMA channel. The controller services the request by performing the DMA cycle using 2R DMA transfers.
3 CH3REQSTATUS 0 R Channel 3 Request Status
When this bit is 1, it indicates that the peripheral connected as the input to this DMA channel is requesting the controller to
service the DMA channel. The controller services the request by performing the DMA cycle using 2R DMA transfers.
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Bit Name Reset Access Description
2 CH2REQSTATUS 0 R Channel 2 Request Status
When this bit is 1, it indicates that the peripheral connected as the input to this DMA channel is requesting the controller to
service the DMA channel. The controller services the request by performing the DMA cycle using 2R DMA transfers.
1 CH1REQSTATUS 0 R Channel 1 Request Status
When this bit is 1, it indicates that the peripheral connected as the input to this DMA channel is requesting the controller to
service the DMA channel. The controller services the request by performing the DMA cycle using 2R DMA transfers.
0 CH0REQSTATUS 0 R Channel 0 Request Status
When this bit is 1, it indicates that the peripheral connected as the input to this DMA channel is requesting the controller to
service the DMA channel. The controller services the request by performing the DMA cycle using 2R DMA transfers.
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8.6.19 DMA_CHSREQSTATUS - Channel Single Request Status
Offset Bit Position
0xE18
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
16
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
Reset
0
0
0
0
0
0
0
0
0
0
0
0
Access
R
R
R
R
R
R
R
R
R
R
R
R
Name
CH11SREQSTATUS
CH10SREQSTATUS
CH9SREQSTATUS
CH8SREQSTATUS
CH7SREQSTATUS
CH6SREQSTATUS
CH5SREQSTATUS
CH4SREQSTATUS
CH3SREQSTATUS
CH2SREQSTATUS
CH1SREQSTATUS
CH0SREQSTATUS
Bit Name Reset Access Description
31:12 Reserved To ensure compatibility with future devices, always write bits to 0. More information in 2.1 Conven-
tions.
11 CH11SREQSTATUS 0 R Channel 11 Single Request Status
When this bit is 1, it indicates that the peripheral connected as the input to this DMA channel is requesting the controller to
service the DMA channel. The controller services the request by performing the DMA cycle using single DMA transfers.
10 CH10SREQSTATUS 0 R Channel 10 Single Request Status
When this bit is 1, it indicates that the peripheral connected as the input to this DMA channel is requesting the controller to
service the DMA channel. The controller services the request by performing the DMA cycle using single DMA transfers.
9 CH9SREQSTATUS 0 R Channel 9 Single Request Status
When this bit is 1, it indicates that the peripheral connected as the input to this DMA channel is requesting the controller to
service the DMA channel. The controller services the request by performing the DMA cycle using single DMA transfers.
8 CH8SREQSTATUS 0 R Channel 8 Single Request Status
When this bit is 1, it indicates that the peripheral connected as the input to this DMA channel is requesting the controller to
service the DMA channel. The controller services the request by performing the DMA cycle using single DMA transfers.
7 CH7SREQSTATUS 0 R Channel 7 Single Request Status
When this bit is 1, it indicates that the peripheral connected as the input to this DMA channel is requesting the controller to
service the DMA channel. The controller services the request by performing the DMA cycle using single DMA transfers.
6 CH6SREQSTATUS 0 R Channel 6 Single Request Status
When this bit is 1, it indicates that the peripheral connected as the input to this DMA channel is requesting the controller to
service the DMA channel. The controller services the request by performing the DMA cycle using single DMA transfers.
5 CH5SREQSTATUS 0 R Channel 5 Single Request Status
When this bit is 1, it indicates that the peripheral connected as the input to this DMA channel is requesting the controller to
service the DMA channel. The controller services the request by performing the DMA cycle using single DMA transfers.
4 CH4SREQSTATUS 0 R Channel 4 Single Request Status
When this bit is 1, it indicates that the peripheral connected as the input to this DMA channel is requesting the controller to
service the DMA channel. The controller services the request by performing the DMA cycle using single DMA transfers.
3 CH3SREQSTATUS 0 R Channel 3 Single Request Status
When this bit is 1, it indicates that the peripheral connected as the input to this DMA channel is requesting the controller to
service the DMA channel. The controller services the request by performing the DMA cycle using single DMA transfers.
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Bit Name Reset Access Description
2 CH2SREQSTATUS 0 R Channel 2 Single Request Status
When this bit is 1, it indicates that the peripheral connected as the input to this DMA channel is requesting the controller to
service the DMA channel. The controller services the request by performing the DMA cycle using single DMA transfers.
1 CH1SREQSTATUS 0 R Channel 1 Single Request Status
When this bit is 1, it indicates that the peripheral connected as the input to this DMA channel is requesting the controller to
service the DMA channel. The controller services the request by performing the DMA cycle using single DMA transfers.
0 CH0SREQSTATUS 0 R Channel 0 Single Request Status
When this bit is 1, it indicates that the peripheral connected as the input to this DMA channel is requesting the controller to
service the DMA channel. The controller services the request by performing the DMA cycle using single DMA transfers.
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8.6.20 DMA_IF - Interrupt Flag Register
Offset Bit Position
0x1000
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
16
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
Reset
0
0
0
0
0
0
0
0
0
0
0
0
0
Access
R
R
R
R
R
R
R
R
R
R
R
R
R
Name
ERR
CH11DONE
CH10DONE
CH9DONE
CH8DONE
CH7DONE
CH6DONE
CH5DONE
CH4DONE
CH3DONE
CH2DONE
CH1DONE
CH0DONE
Bit Name Reset Access Description
31 ERR 0 R DMA Error Interrupt Flag
This flag is set when an error has occurred on the AHB bus.
30:12 Reserved To ensure compatibility with future devices, always write bits to 0. More information in 2.1 Conven-
tions.
11 CH11DONE 0 R DMA Channel 11 Complete Interrupt Flag
Set when the DMA channel has completed its transfer. If the channel is disabled, the flag is set when there is a request for
the channel.
10 CH10DONE 0 R DMA Channel 10 Complete Interrupt Flag
Set when the DMA channel has completed its transfer. If the channel is disabled, the flag is set when there is a request for
the channel.
9 CH9DONE 0 R DMA Channel 9 Complete Interrupt Flag
Set when the DMA channel has completed its transfer. If the channel is disabled, the flag is set when there is a request for
the channel.
8 CH8DONE 0 R DMA Channel 8 Complete Interrupt Flag
Set when the DMA channel has completed its transfer. If the channel is disabled, the flag is set when there is a request for
the channel.
7 CH7DONE 0 R DMA Channel 7 Complete Interrupt Flag
Set when the DMA channel has completed its transfer. If the channel is disabled, the flag is set when there is a request for
the channel.
6 CH6DONE 0 R DMA Channel 6 Complete Interrupt Flag
Set when the DMA channel has completed its transfer. If the channel is disabled, the flag is set when there is a request for
the channel.
5 CH5DONE 0 R DMA Channel 5 Complete Interrupt Flag
Set when the DMA channel has completed its transfer. If the channel is disabled, the flag is set when there is a request for
the channel.
4 CH4DONE 0 R DMA Channel 4 Complete Interrupt Flag
Set when the DMA channel has completed its transfer. If the channel is disabled, the flag is set when there is a request for
the channel.
3 CH3DONE 0 R DMA Channel 3 Complete Interrupt Flag
Set when the DMA channel has completed its transfer. If the channel is disabled, the flag is set when there is a request for
the channel.
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Bit Name Reset Access Description
2 CH2DONE 0 R DMA Channel 2 Complete Interrupt Flag
Set when the DMA channel has completed its transfer. If the channel is disabled, the flag is set when there is a request for
the channel.
1 CH1DONE 0 R DMA Channel 1 Complete Interrupt Flag
Set when the DMA channel has completed its transfer. If the channel is disabled, the flag is set when there is a request for
the channel.
0 CH0DONE 0 R DMA Channel 0 Complete Interrupt Flag
Set when the DMA channel has completed its transfer. If the channel is disabled, the flag is set when there is a request for
the channel.
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8.6.21 DMA_IFS - Interrupt Flag Set Register
Offset Bit Position
0x1004
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
16
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
Reset
0
0
0
0
0
0
0
0
0
0
0
0
0
Access
W1
W1
W1
W1
W1
W1
W1
W1
W1
W1
W1
W1
W1
Name
ERR
CH11DONE
CH10DONE
CH9DONE
CH8DONE
CH7DONE
CH6DONE
CH5DONE
CH4DONE
CH3DONE
CH2DONE
CH1DONE
CH0DONE
Bit Name Reset Access Description
31 ERR 0 W1 DMA Error Interrupt Flag Set
Set to 1 to set DMA error interrupt flag.
30:12 Reserved To ensure compatibility with future devices, always write bits to 0. More information in 2.1 Conven-
tions.
11 CH11DONE 0 W1 DMA Channel 11 Complete Interrupt Flag Set
Write to 1 to set the corresponding DMA channel complete interrupt flag.
10 CH10DONE 0 W1 DMA Channel 10 Complete Interrupt Flag Set
Write to 1 to set the corresponding DMA channel complete interrupt flag.
9 CH9DONE 0 W1 DMA Channel 9 Complete Interrupt Flag Set
Write to 1 to set the corresponding DMA channel complete interrupt flag.
8 CH8DONE 0 W1 DMA Channel 8 Complete Interrupt Flag Set
Write to 1 to set the corresponding DMA channel complete interrupt flag.
7 CH7DONE 0 W1 DMA Channel 7 Complete Interrupt Flag Set
Write to 1 to set the corresponding DMA channel complete interrupt flag.
6 CH6DONE 0 W1 DMA Channel 6 Complete Interrupt Flag Set
Write to 1 to set the corresponding DMA channel complete interrupt flag.
5 CH5DONE 0 W1 DMA Channel 5 Complete Interrupt Flag Set
Write to 1 to set the corresponding DMA channel complete interrupt flag.
4 CH4DONE 0 W1 DMA Channel 4 Complete Interrupt Flag Set
Write to 1 to set the corresponding DMA channel complete interrupt flag.
3 CH3DONE 0 W1 DMA Channel 3 Complete Interrupt Flag Set
Write to 1 to set the corresponding DMA channel complete interrupt flag.
2 CH2DONE 0 W1 DMA Channel 2 Complete Interrupt Flag Set
Write to 1 to set the corresponding DMA channel complete interrupt flag.
1 CH1DONE 0 W1 DMA Channel 1 Complete Interrupt Flag Set
Write to 1 to set the corresponding DMA channel complete interrupt flag.
0 CH0DONE 0 W1 DMA Channel 0 Complete Interrupt Flag Set
Write to 1 to set the corresponding DMA channel complete interrupt flag.
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8.6.22 DMA_IFC - Interrupt Flag Clear Register
Offset Bit Position
0x1008
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
16
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
Reset
0
0
0
0
0
0
0
0
0
0
0
0
0
Access
(R)W1
(R)W1
(R)W1
(R)W1
(R)W1
(R)W1
(R)W1
(R)W1
(R)W1
(R)W1
(R)W1
(R)W1
(R)W1
Name
ERR
CH11DONE
CH10DONE
CH9DONE
CH8DONE
CH7DONE
CH6DONE
CH5DONE
CH4DONE
CH3DONE
CH2DONE
CH1DONE
CH0DONE
Bit Name Reset Access Description
31 ERR 0 (R)W1 DMA Error Interrupt Flag Clear
Set to 1 to clear DMA error interrupt flag. Note that if an error happened, the Bus Error Clear Register must be used to clear
the DMA.
30:12 Reserved To ensure compatibility with future devices, always write bits to 0. More information in 2.1 Conven-
tions.
11 CH11DONE 0 (R)W1 DMA Channel 11 Complete Interrupt Flag Clear
Write to 1 to clear the corresponding DMA channel complete interrupt flag.
10 CH10DONE 0 (R)W1 DMA Channel 10 Complete Interrupt Flag Clear
Write to 1 to clear the corresponding DMA channel complete interrupt flag.
9 CH9DONE 0 (R)W1 DMA Channel 9 Complete Interrupt Flag Clear
Write to 1 to clear the corresponding DMA channel complete interrupt flag.
8 CH8DONE 0 (R)W1 DMA Channel 8 Complete Interrupt Flag Clear
Write to 1 to clear the corresponding DMA channel complete interrupt flag.
7 CH7DONE 0 (R)W1 DMA Channel 7 Complete Interrupt Flag Clear
Write to 1 to clear the corresponding DMA channel complete interrupt flag.
6 CH6DONE 0 (R)W1 DMA Channel 6 Complete Interrupt Flag Clear
Write to 1 to clear the corresponding DMA channel complete interrupt flag.
5 CH5DONE 0 (R)W1 DMA Channel 5 Complete Interrupt Flag Clear
Write to 1 to clear the corresponding DMA channel complete interrupt flag.
4 CH4DONE 0 (R)W1 DMA Channel 4 Complete Interrupt Flag Clear
Write to 1 to clear the corresponding DMA channel complete interrupt flag.
3 CH3DONE 0 (R)W1 DMA Channel 3 Complete Interrupt Flag Clear
Write to 1 to clear the corresponding DMA channel complete interrupt flag.
2 CH2DONE 0 (R)W1 DMA Channel 2 Complete Interrupt Flag Clear
Write to 1 to clear the corresponding DMA channel complete interrupt flag.
1 CH1DONE 0 (R)W1 DMA Channel 1 Complete Interrupt Flag Clear
Write to 1 to clear the corresponding DMA channel complete interrupt flag.
0 CH0DONE 0 (R)W1 DMA Channel 0 Complete Interrupt Flag Clear
Write to 1 to clear the corresponding DMA channel complete interrupt flag.
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8.6.23 DMA_IEN - Interrupt Enable register
Offset Bit Position
0x100C
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
16
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
Reset
0
0
0
0
0
0
0
0
0
0
0
0
0
Access
RW
RW
RW
RW
RW
RW
RW
RW
RW
RW
RW
RW
RW
Name
ERR
CH11DONE
CH10DONE
CH9DONE
CH8DONE
CH7DONE
CH6DONE
CH5DONE
CH4DONE
CH3DONE
CH2DONE
CH1DONE
CH0DONE
Bit Name Reset Access Description
31 ERR 0 RW DMA Error Interrupt Flag Enable
Set this bit to enable interrupt on AHB bus error.
30:12 Reserved To ensure compatibility with future devices, always write bits to 0. More information in 2.1 Conven-
tions.
11 CH11DONE 0 RW DMA Channel 11 Complete Interrupt Enable
Write to 1 to enable complete interrupt on this DMA channel. Clear to disable the interrupt.
10 CH10DONE 0 RW DMA Channel 10 Complete Interrupt Enable
Write to 1 to enable complete interrupt on this DMA channel. Clear to disable the interrupt.
9 CH9DONE 0 RW DMA Channel 9 Complete Interrupt Enable
Write to 1 to enable complete interrupt on this DMA channel. Clear to disable the interrupt.
8 CH8DONE 0 RW DMA Channel 8 Complete Interrupt Enable
Write to 1 to enable complete interrupt on this DMA channel. Clear to disable the interrupt.
7 CH7DONE 0 RW DMA Channel 7 Complete Interrupt Enable
Write to 1 to enable complete interrupt on this DMA channel. Clear to disable the interrupt.
6 CH6DONE 0 RW DMA Channel 6 Complete Interrupt Enable
Write to 1 to enable complete interrupt on this DMA channel. Clear to disable the interrupt.
5 CH5DONE 0 RW DMA Channel 5 Complete Interrupt Enable
Write to 1 to enable complete interrupt on this DMA channel. Clear to disable the interrupt.
4 CH4DONE 0 RW DMA Channel 4 Complete Interrupt Enable
Write to 1 to enable complete interrupt on this DMA channel. Clear to disable the interrupt.
3 CH3DONE 0 RW DMA Channel 3 Complete Interrupt Enable
Write to 1 to enable complete interrupt on this DMA channel. Clear to disable the interrupt.
2 CH2DONE 0 RW DMA Channel 2 Complete Interrupt Enable
Write to 1 to enable complete interrupt on this DMA channel. Clear to disable the interrupt.
1 CH1DONE 0 RW DMA Channel 1 Complete Interrupt Enable
Write to 1 to enable complete interrupt on this DMA channel. Clear to disable the interrupt.
0 CH0DONE 0 RW DMA Channel 0 Complete Interrupt Enable
Write to 1 to enable complete interrupt on this DMA channel. Clear to disable the interrupt.
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8.6.24 DMA_CTRL - DMA Control Register
Offset Bit Position
0x1010
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
16
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
Reset
0
0
Access
RW
RW
Name
PRDU
DESCRECT
Bit Name Reset Access Description
31:2 Reserved To ensure compatibility with future devices, always write bits to 0. More information in 2.1 Conven-
tions.
1 PRDU 0 RW Prevent Rect Descriptor Update
Allows the reuse of a rect descriptor. When active CH0 and no others can have RDS set
0 DESCRECT 0 RW Descriptor Specifies Rectangle
Word 4 (user data) in dma descriptor specifies WIDTH, HEIGHT and SRCSTRIDE for rectangle copies. WIDTH is given by
bits 9:0, HEIGHT is given by bits 19:10, and SRCSTRIDE is given by bits 30:20
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8.6.25 DMA_RDS - DMA Retain Descriptor State
Offset Bit Position
0x1014
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
16
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
Reset
0
0
0
0
0
0
0
0
0
0
0
0
Access
RW
RW
RW
RW
RW
RW
RW
RW
RW
RW
RW
RW
Name
RDSCH11
RDSCH10
RDSCH9
RDSCH8
RDSCH7
RDSCH6
RDSCH5
RDSCH4
RDSCH3
RDSCH2
RDSCH1
RDSCH0
Bit Name Reset Access Description
31:12 Reserved To ensure compatibility with future devices, always write bits to 0. More information in 2.1 Conven-
tions.
11 RDSCH11 0 RW Retain Descriptor State
Speed up execution of consecutive DMA requests from the same channel by not reading descriptor at the start of every
arbitration cycle if the next channel is the same as the previous
10 RDSCH10 0 RW Retain Descriptor State
Speed up execution of consecutive DMA requests from the same channel by not reading descriptor at the start of every
arbitration cycle if the next channel is the same as the previous
9 RDSCH9 0 RW Retain Descriptor State
Speed up execution of consecutive DMA requests from the same channel by not reading descriptor at the start of every
arbitration cycle if the next channel is the same as the previous
8 RDSCH8 0 RW Retain Descriptor State
Speed up execution of consecutive DMA requests from the same channel by not reading descriptor at the start of every
arbitration cycle if the next channel is the same as the previous
7 RDSCH7 0 RW Retain Descriptor State
Speed up execution of consecutive DMA requests from the same channel by not reading descriptor at the start of every
arbitration cycle if the next channel is the same as the previous
6 RDSCH6 0 RW Retain Descriptor State
Speed up execution of consecutive DMA requests from the same channel by not reading descriptor at the start of every
arbitration cycle if the next channel is the same as the previous
5 RDSCH5 0 RW Retain Descriptor State
Speed up execution of consecutive DMA requests from the same channel by not reading descriptor at the start of every
arbitration cycle if the next channel is the same as the previous
4 RDSCH4 0 RW Retain Descriptor State
Speed up execution of consecutive DMA requests from the same channel by not reading descriptor at the start of every
arbitration cycle if the next channel is the same as the previous
3 RDSCH3 0 RW Retain Descriptor State
Speed up execution of consecutive DMA requests from the same channel by not reading descriptor at the start of every
arbitration cycle if the next channel is the same as the previous
2 RDSCH2 0 RW Retain Descriptor State
Speed up execution of consecutive DMA requests from the same channel by not reading descriptor at the start of every
arbitration cycle if the next channel is the same as the previous
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Bit Name Reset Access Description
1 RDSCH1 0 RW Retain Descriptor State
Speed up execution of consecutive DMA requests from the same channel by not reading descriptor at the start of every
arbitration cycle if the next channel is the same as the previous
0 RDSCH0 0 RW Retain Descriptor State
Speed up execution of consecutive DMA requests from the same channel by not reading descriptor at the start of every
arbitration cycle if the next channel is the same as the previous
8.6.26 DMA_LOOP0 - Channel 0 Loop Register
Offset Bit Position
0x1020
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
16
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
Reset
0
0x000
Access
RW
RWH
Name
EN
WIDTH
Bit Name Reset Access Description
31:17 Reserved To ensure compatibility with future devices, always write bits to 0. More information in 2.1 Conven-
tions.
16 EN 0 RW DMA Channel 0 Loop Enable
Loop enable for channel 0
15:10 Reserved To ensure compatibility with future devices, always write bits to 0. More information in 2.1 Conven-
tions.
9:0 WIDTH 0x000 RWH Loop Width
Reload value for N_MINUS_1 when loop is enabled
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8.6.27 DMA_LOOP1 - Channel 1 Loop Register
Offset Bit Position
0x1024
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
16
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
Reset
0
0x000
Access
RW
RW
Name
EN
WIDTH
Bit Name Reset Access Description
31:17 Reserved To ensure compatibility with future devices, always write bits to 0. More information in 2.1 Conven-
tions.
16 EN 0 RW DMA Channel 1 Loop Enable
Loop enable for channel 1
15:10 Reserved To ensure compatibility with future devices, always write bits to 0. More information in 2.1 Conven-
tions.
9:0 WIDTH 0x000 RW DMA Channel 1 Loop Width
Reload value for N_MINUS_1 when loop is enabled
8.6.28 DMA_RECT0 - Channel 0 Rectangle Register
Offset Bit Position
0x1060
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
16
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
Reset
0x000
0x000
0x000
Access
RW
RWH
RWH
Name
DSTSTRIDE
SRCSTRIDE
HEIGHT
Bit Name Reset Access Description
31:21 DSTSTRIDE 0x000 RW DMA Channel 0 Destination Stride
Space between start of lines in destination rectangle
20:10 SRCSTRIDE 0x000 RWH DMA Channel 0 Source Stride
Space between start of lines in source rectangle
9:0 HEIGHT 0x000 RWH DMA Channel 0 Rectangle Height
Number of lines when doing rectangle copy. Set to the number of lines - 1.
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8.6.29 DMA_CHx_CTRL - Channel Control Register
Offset Bit Position
0x1100
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
16
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
Reset
0x00
0x0
Access
RW
RW
Name
SOURCESEL
SIGSEL
Bit Name Reset Access Description
31:22 Reserved To ensure compatibility with future devices, always write bits to 0. More information in 2.1 Conven-
tions.
21:16 SOURCESEL 0x00 RW Source Select
Select input source to DMA channel.
Value Mode Description
0b000000 NONE No source selected
0b001000 ADC0 Analog to Digital Converter 0
0b001010 DAC0 Digital to Analog Converter 0
0b001100 USART0 Universal Synchronous/Asynchronous Receiver/Transmitter 0
0b001101 USART1 Universal Synchronous/Asynchronous Receiver/Transmitter 1
0b001110 USART2 Universal Synchronous/Asynchronous Receiver/Transmitter 2
0b010000 LEUART0 Low Energy UART 0
0b010001 LEUART1 Low Energy UART 1
0b010100 I2C0 I2C 0
0b010101 I2C1 I2C 1
0b011000 TIMER0 Timer 0
0b011001 TIMER1 Timer 1
0b011010 TIMER2 Timer 2
0b011011 TIMER3 Timer 3
0b101100 UART0 Universal Asynchronous Receiver/Transmitter 0
0b101101 UART1 Universal Asynchronous Receiver/Transmitter 1
0b110000 MSC
0b110001 AES Advanced Encryption Standard Accelerator
0b110010 LESENSE Low Energy Sensor Interface
0b110011 EBI External Bus Interface
15:4 Reserved To ensure compatibility with future devices, always write bits to 0. More information in 2.1 Conven-
tions.
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Bit Name Reset Access Description
3:0 SIGSEL 0x0 RW Signal Select
Select input signal to DMA channel.
Value Mode Description
SOURCESEL = 0b000000 (NONE)
0bxxxx OFF Channel input selection is turned off
SOURCESEL = 0b001000 (ADC0)
0b0000 ADC0SINGLE ADC0SINGLE
0b0001 ADC0SCAN ADC0SCAN
SOURCESEL = 0b001010 (DAC0)
0b0000 DAC0CH0 DAC0CH0
0b0001 DAC0CH1 DAC0CH1
SOURCESEL = 0b001100 (USART0)
0b0000 USART0RXDATAV USART0RXDATAV REQ/SREQ
0b0001 USART0TXBL USART0TXBL REQ/SREQ
0b0010 USART0TXEMPTY USART0TXEMPTY
SOURCESEL = 0b001101 (USART1)
0b0000 USART1RXDATAV USART1RXDATAV REQ/SREQ
0b0001 USART1TXBL USART1TXBL REQ/SREQ
0b0010 USART1TXEMPTY USART1TXEMPTY
0b0011 USART1RXDATAV-
RIGHT
USART1RXDATAVRIGHT REQ/SREQ
0b0100 USART1TXBLRIGHT USART1TXBLRIGHT REQ/SREQ
SOURCESEL = 0b001110 (USART2)
0b0000 USART2RXDATAV USART2RXDATAV REQ/SREQ
0b0001 USART2TXBL USART2TXBL REQ/SREQ
0b0010 USART2TXEMPTY USART2TXEMPTY
0b0011 USART2RXDATAV-
RIGHT
USART2RXDATAVRIGHT REQ/SREQ
0b0100 USART2TXBLRIGHT USART2TXBLRIGHT REQ/SREQ
SOURCESEL = 0b010000 (LEUART0)
0b0000 LEUART0RXDATAV LEUART0RXDATAV
0b0001 LEUART0TXBL LEUART0TXBL
0b0010 LEUART0TXEMPTY LEUART0TXEMPTY
SOURCESEL = 0b010001 (LEUART1)
0b0000 LEUART1RXDATAV LEUART1RXDATAV
0b0001 LEUART1TXBL LEUART1TXBL
0b0010 LEUART1TXEMPTY LEUART1TXEMPTY
SOURCESEL = 0b010100 (I2C0)
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Bit Name Reset Access Description
0b0000 I2C0RXDATAV I2C0RXDATAV
0b0001 I2C0TXBL I2C0TXBL
SOURCESEL = 0b010101 (I2C1)
0b0000 I2C1RXDATAV I2C1RXDATAV
0b0001 I2C1TXBL I2C1TXBL
SOURCESEL = 0b011000 (TIMER0)
0b0000 TIMER0UFOF TIMER0UFOF
0b0001 TIMER0CC0 TIMER0CC0
0b0010 TIMER0CC1 TIMER0CC1
0b0011 TIMER0CC2 TIMER0CC2
SOURCESEL = 0b011001 (TIMER1)
0b0000 TIMER1UFOF TIMER1UFOF
0b0001 TIMER1CC0 TIMER1CC0
0b0010 TIMER1CC1 TIMER1CC1
0b0011 TIMER1CC2 TIMER1CC2
SOURCESEL = 0b011010 (TIMER2)
0b0000 TIMER2UFOF TIMER2UFOF
0b0001 TIMER2CC0 TIMER2CC0
0b0010 TIMER2CC1 TIMER2CC1
0b0011 TIMER2CC2 TIMER2CC2
SOURCESEL = 0b011011 (TIMER3)
0b0000 TIMER3UFOF TIMER3UFOF
0b0001 TIMER3CC0 TIMER3CC0
0b0010 TIMER3CC1 TIMER3CC1
0b0011 TIMER3CC2 TIMER3CC2
SOURCESEL = 0b101100 (UART0)
0b0000 UART0RXDATAV UART0RXDATAV REQ/SREQ
0b0001 UART0TXBL UART0TXBL REQ/SREQ
0b0010 UART0TXEMPTY UART0TXEMPTY
SOURCESEL = 0b101101 (UART1)
0b0000 UART1RXDATAV UART1RXDATAV REQ/SREQ
0b0001 UART1TXBL UART1TXBL REQ/SREQ
0b0010 UART1TXEMPTY UART1TXEMPTY
SOURCESEL = 0b110000 (MSC)
0b0000 MSCWDATA MSCWDATA
SOURCESEL = 0b110001 (AES)
0b0000 AESDATAWR AESDATAWR
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Bit Name Reset Access Description
0b0001 AESXORDATAWR AESXORDATAWR
0b0010 AESDATARD AESDATARD
0b0011 AESKEYWR AESKEYWR
SOURCESEL = 0b110010 (LESENSE)
0b0000 LESENSEBUFDATAV LESENSEBUFDATAV REQ/SREQ
SOURCESEL = 0b110011 (EBI)
0b0000 EBIPXL0EMPTY EBIPXL0EMPTY
0b0001 EBIPXL1EMPTY EBIPXL1EMPTY
0b0010 EBIPXLFULL EBIPXLFULL
0b0011 EBIDDEMPTY EBIDDEMPTY
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@—
OWERON
9. RMU - Reset Management Unit
43210
Reset Management Unit
SYSRESETREQ
WATCHDOG
BROWNOUT
POWERON
RESET
LOCKUP
RESETn
Quick Facts
What?
The RMU ensures correct reset operation. It is re-
sponsible for connecting the different reset sources
to the reset lines of the EFM32WG.
Why?
A correct reset sequence is needed to ensure safe
and synchronous startup of the EFM32WG. In the
case of error situations such as power supply glitch-
es or software crash, the RMU provides proper reset
and startup of the EFM32WG.
How?
The Power-on Reset and Brown-out Detector of the
EFM32WG provides power line monitoring with ex-
ceptionally low power consumption. The cause of
the reset may be read from a register, thus providing
software with information about the cause of the re-
set.
9.1 Introduction
The RMU is responsible for handling the reset functionality of the EFM32WG.
9.2 Features
• Reset sources
• Power-on Reset (POR)
• Brown-out Detection (BOD) on the following power domains:
• Regulated domain
• Unregulated domain
• Analog Power Domain 0 (AVDD0)
• Analog Power Domain 1 (AVDD1)
• RESETn pin reset
• Watchdog reset
• EM4 wakeup reset from pin
• EM4 wakeup reset from Backup RTC interrupt
• Wakeup from Backup Mode
• Software triggered reset (SYSRESETREQ)
• Core LOCKUP condition
• EM4 Detection
• A software readable register indicates the cause of the last reset
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Du
D1
LOCKUF
SVSREQRST
9.3 Functional Description
The RMU monitors each of the reset sources of the EFM32WG. If one or more reset sources go active, the RMU applies reset to the
EFM32WG. When the reset sources go inactive the EFM32WG starts up. At startup the EFM32WG loads the stack pointer and pro-
gram entry point from memory, and starts execution.
As seen in the figure below, the Power-on Reset, Brown-out Detectors, Watchdog timeout, and RESETn pin all reset the whole system
including the Debug Interface. A Core Lockup condition or a System reset request from software resets the whole system except the
Debug Interface.
Whenever a reset source is active, the corresponding bit in the RMU_RSTCAUSE register is set. At startup the program code may
investigate this register in order to determine the cause of the reset. The register must be cleared by software.
Reset Management Unit
SYSREQRST
WDOG
PORESETn
SYSRESETn
LOCKUP
POWERONn
BROWNOUT_UNREGn
RESETn
Filter
LOCKUPRDIS
VDD
POR
BOD
Cortex
Core
Debug
Interface
Peripherals
VDD_REGULATED
RMU_RSTCAUSE
BROWNOUT_REGn
RCCLR
Edge-to-pulse
filter
BOD
AVDD0 BROWNOUT_AVDD0
BOD
AVDD1 BROWNOUT_AVDD1
BOD
EM4 wakeup
em4
Backup mode
Backup mode exit
Figure 9.1. RMU Reset Input Sources and Connections
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9.3.1 RMU_RSTCAUSE Register
The RMU_RSTCAUSE register indicates the reason for the last reset. The register should be cleared after the value has been read at
startup. Otherwise, the register may indicate multiple causes for the reset at next startup.
The following procedure must be done to clear RMU_RSTCAUSE:
1. Write a 1 to RCCLR in RMU_CMD.
2. Write a 1 to bit 0 in EMU_AUXCTRL.
3. Write a 0 to bit 0 in EMU_AUXCTRL.
RMU_RSTCAUSE should be interpreted according to the table below. X bits are don't care. Notice that it is possible to have multiple
reset causes. For example, an external reset and a watchdog reset may happen simultaneously.
Table 9.1. RMU Reset Cause Register Interpretation
Register Value Cause
0bXXXX XXXX XXXX XXX1 A Power-on Reset has been performed. X bits are don't care.
0bXXXX XXXX 0XXX XX10 A Brown-out has been detected on the unregulated power.
0bXXXX XXXX XXX0 0100 A Brown-out has been detected on the regulated power.
0bXXXX XXXX XXXX 1X00 An external reset has been applied.
0bXXXX XXXX XXX1 XX00 A watchdog reset has occurred.
0bXXXX X000 0010 0000 A lockup reset has occurred.
0bXXXX X000 01X0 0000 A system request reset has occurred.
0bXXXX X000 1XX0 0XX0 The system has woken up from EM4.
0bXXXX X001 1XX0 0XX0 The system has woken up from EM4 on an EM4 wakeup reset re-
quest from pin.
0bXXXX X01X XXX0 0000 A Brown-out has been detected on Analog Power Domain 0
(AVDD0).
0bXXXX X10X XXX0 0000 A Brown-out has been detected on Analog Power Domain 1
(AVDD1).
0bXXXX 1XXX XXXX 0XX0 A Brown-out has been detected by the Backup BOD on
VDD_DREG.
0bXXX1 XXXX XXXX 0XX0 A Brown-out has been detected by the Backup BOD on BU_VIN.
0bXX1X XXXX XXXX 0XX0 A Brown-out has been detected by the Backup BOD on unregula-
ted power
0bX1XX XXXX XXXX 0XX0 A Brown-out has been detected by the Backup BOD on regulated
power.
0b1XXX XXXX XXXX XXX0 The system has been in Backup mode.
Note: When exiting EM4 with external reset, both the BODREGRST and BODUNREGRST in RSTCAUSE might be set (i.e., are inva-
lid).
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9.3.2 Power-On Reset (POR)
The POR ensures that the EFM32WG does not start up before the supply voltage VDD has reached the threshold voltage VPORthr (see
Device Datasheet Electrical Characteristics for details). Before the threshold voltage is reached, the EFM32WG is kept in reset state.
The operation of the POR is illustrated in the figure below with the active low POWERONn reset signal. The reason for the “unknown”
region is that the corresponding supply voltage is too low for any reliable operation.
POWERONn
VDD
time
V
Unknown
VPORthr
Figure 9.2. RMU Power-on Reset Operation
9.3.3 Brown-Out Detector Reset (BOD)
The EFM32WG has 4 brownout detectors, one for the unregulated 3.0 V power, one for the regulated internal power, one for Analog
Power Domain 0 (AVDD0), and one for Analog Power Domain 1 (AVDD1). The BODs are constantly monitoring the voltages. Whenev-
er the unregulated or regulated power drops below the VBODthr value (see Electrical Characteristics for details), or if the AVDD0 or
AVDD1 drops below the voltage at the decouple pin (DEC), the corresponding active low BROWNOUTn line is held low. The BODs
also include hysteresis, which prevents instability in the corresponding BROWNOUTn line when the supply is crossing the VBODthr
limit or the AVDD bods drops below decouple pin (DEC). The operation of the BOD is illustrated in the figure below. The “unknown”
regions are handled by the POR module.
Unknown
BROWNOUTn
VDD
time
V
Unknown
VBODthr VBODhyst
VBODhyst
Figure 9.3. RMU Brown-out Detector Operation
9.3.4 RESETn Pin Reset
Forcing the RESETn pin low generates a reset of the EFM32WG. The RESETn pin includes an on-chip pull-up resistor, and can there-
fore be left unconnected if no external reset source is needed. Also connected to the RESETn line is a filter which prevents glitches
from resetting the EFM32WG.
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9.3.5 Watchdog Reset
The Watchdog circuit is a timer which (when enabled) must be cleared by software regularly. If software does not clear it, a Watchdog
reset is activated. This functionality provides recovery from a software stalemate. Refer to the Watchdog section for specifications and
description.
9.3.6 Lockup Reset
A Cortex-M4 lockup is the result of the core being locked up because of an unrecoverable exception following the activation of the pro-
cessor’s built-in system state protection hardware.
For more information about the Cortex-M4 lockup conditions, see the ARMv7-M Architecture Reference Manual. The Lockup reset does
not reset the Debug Interface. Set the LOCKUPRDIS bit in the RMU_CTRL register in order to disable this reset source.
9.3.7 System Reset Request
Software may initiate a reset (e.g. if it finds itself in a non-recoverable state). By asserting the SYSRESETREQ in the Application Inter-
rupt and Reset Control Register (write 0x05FA 0004), a reset is issued. The SYSRESETREQ does not reset the Debug Interface.
9.3.8 EM4 Reset
Whenever EM4 is entered, the EM4RST bit is set. This bit enables the user to identify that the device has been in EM4. Upon wake-up
this bit should be cleared by software.
9.3.9 EM4 Wakeup Reset
Whenever the system is woken up from EM4 on a pin wake-up request, the EM4WURST bit is set. This bit enables the user to identify
that the device was woken up from EM4 using a pin wake-up request. Upon wake-up this bit should be cleared by software.
9.4 Register Map
The offset register address is relative to the registers base address.
Offset Name Type Description
0x000 RMU_CTRL RW Control Register
0x004 RMU_RSTCAUSE RReset Cause Register
0x008 RMU_CMD W1 Command Register
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9.5 Register Description
9.5.1 RMU_CTRL - Control Register
Offset Bit Position
0x000
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
16
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
Reset
1
0
Access
RW
RW
Name
BURSTEN
LOCKUPRDIS
Bit Name Reset Access Description
31:2 Reserved To ensure compatibility with future devices, always write bits to 0. More information in 2.1 Conven-
tions.
1 BURSTEN 1 RW Backup domain reset enable
This bit has to be cleared before accessing the registers in the BURTC.
0 LOCKUPRDIS 0 RW Lockup Reset Disable
Set this bit to disable the LOCKUP signal (from the Cortex) from resetting the device.
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9.5.2 RMU_RSTCAUSE - Reset Cause Register
Offset Bit Position
0x004
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
16
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
Reset
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
Access
R
R
R
R
R
R
R
R
R
R
R
R
R
R
R
R
Name
BUMODERST
BUBODREG
BUBODUNREG
BUBODBUVIN
BUBODVDDDREG
BODAVDD1
BODAVDD0
EM4WURST
EM4RST
SYSREQRST
LOCKUPRST
WDOGRST
EXTRST
BODREGRST
BODUNREGRST
PORST
Bit Name Reset Access Description
31:16 Reserved To ensure compatibility with future devices, always write bits to 0. More information in 2.1 Conven-
tions.
15 BUMODERST 0 R Backup mode reset
Set if the system has been in Backup mode. Must be cleared by software. Please see 10.3.4 Backup Power Domain for
details on how to interpret this bit.
14 BUBODREG 0 R Backup Brown Out Detector Regulated Domain
Set if the Backup BOD sensing on regulated power triggers. Must be cleared by software. Please see 10.3.4.2 Brown Out
Detectors for details on how to interpret this bit.
13 BUBODUNREG 0 R Backup Brown Out Detector Unregulated Domain
Set if the Backup BOD sensing on unregulated power triggers. Must be cleared by software. Please see 10.3.4.2 Brown
Out Detectors for details on how to interpret this bit.
12 BUBODBUVIN 0 R Backup Brown Out Detector, BU_VIN
Set if the Backup BOD sensing on BU_VIN triggers. Must be cleared by software. Please see 10.3.4.2 Brown Out Detectors
for details on how to interpret this bit.
11 BUBODVDDDREG 0 R Backup Brown Out Detector, VDD_DREG
Set if the Backup BOD sensing on VDDD_REG triggers. Must be cleared by software. Please see 10.3.4.2 Brown Out De-
tectors for details on how to interpret this bit.
10 BODAVDD1 0 R AVDD1 Bod Reset
Set if analog power domain 1 brown out detector reset has been performed. Must be cleared by software. Please see Table
9.1 RMU Reset Cause Register Interpretation on page 146 for details on how to interpret this bit.
9 BODAVDD0 0 R AVDD0 Bod Reset
Set if analog power domain 0 brown out detector reset has been performed. Must be cleared by software. Please see Table
9.1 RMU Reset Cause Register Interpretation on page 146 for details on how to interpret this bit.
8 EM4WURST 0 R EM4 Wake-up Reset
Set if the system has been woken up from EM4 from a reset request from pin. Must be cleared by software. Please see
Table 9.1 RMU Reset Cause Register Interpretation on page 146 for details on how to interpret this bit.
7 EM4RST 0 R EM4 Reset
Set if the system has been in EM4. Must be cleared by software. Please see Table 9.1 RMU Reset Cause Register Inter-
pretation on page 146 for details on how to interpret this bit.
6 SYSREQRST 0 R System Request Reset
Set if a system request reset has been performed. Must be cleared by software. Please see Table 9.1 RMU Reset Cause
Register Interpretation on page 146 for details on how to interpret this bit.
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Bit Name Reset Access Description
5 LOCKUPRST 0 R LOCKUP Reset
Set if a LOCKUP reset has been requested. Must be cleared by software. Please see Table 9.1 RMU Reset Cause Regis-
ter Interpretation on page 146 for details on how to interpret this bit.
4 WDOGRST 0 R Watchdog Reset
Set if a watchdog reset has been performed. Must be cleared by software. Please see Table 9.1 RMU Reset Cause Regis-
ter Interpretation on page 146 for details on how to interpret this bit.
3 EXTRST 0 R External Pin Reset
Set if an external pin reset has been performed. Must be cleared by software. Please see Table 9.1 RMU Reset Cause
Register Interpretation on page 146 for details on how to interpret this bit.
2 BODREGRST 0 R Brown Out Detector Regulated Domain Reset
Set if a regulated domain brown out detector reset has been performed. Must be cleared by software. Please see Table
9.1 RMU Reset Cause Register Interpretation on page 146 for details on how to interpret this bit.
1 BODUNREGRST 0 R Brown Out Detector Unregulated Domain Reset
Set if a unregulated domain brown out detector reset has been performed. Must be cleared by software. Please see Table
9.1 RMU Reset Cause Register Interpretation on page 146 for details on how to interpret this bit.
0 PORST 0 R Power On Reset
Set if a power on reset has been performed. Must be cleared by software. Please see Table 9.1 RMU Reset Cause Regis-
ter Interpretation on page 146 for details on how to interpret this bit.
9.5.3 RMU_CMD - Command Register
Offset Bit Position
0x008
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
16
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
Reset
0
Access
W1
Name
RCCLR
Bit Name Reset Access Description
31:1 Reserved To ensure compatibility with future devices, always write bits to 0. More information in 2.1 Conven-
tions.
0 RCCLR 0 W1 Reset Cause Clear
Set this bit to clear the LOCKUPRST and SYSREQRST bits in the RMU_RSTCAUSE register. Use the HRCCLR bit in the
EMU_AUXCTRL register to clear the remaining bits.
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10. EMU - Energy Management Unit
43210
Quick Facts
What?
The EMU (Energy Management Unit) handles the
different low energy modes in the EFM32WG micro-
controllers.
Why?
The need for performance and peripheral functions
varies over time in most applications. By efficiently
scaling the available resources in real-time to match
the demands of the application, the energy con-
sumption can be kept at a minimum.
How?
With a broad selection of energy modes, a high
number of low-energy peripherals available even in
EM2, and short wakeup time (2 µs from EM2 and
EM3), applications can dynamically minimize energy
consumption during program execution.
10.1 Introduction
The Energy Management Unit (EMU) manages all the low energy modes (EM) in EFM32WG microcontrollers. Each energy mode man-
ages if the CPU and the various peripherals are available. The energy modes range from EM0 to EM4, where EM0, also called run
mode, enables the CPU and all peripherals. The lowest recoverable energy mode, EM3, disables the CPU and most peripherals while
maintaining wake-up and RAM functionality. EM4 disables everything except the POR, pin reset and optionally Backup RTC, 512 byte
data retention, GPIO state retention, and EM4 reset wakeup request.
The various energy modes differ in:
• Energy consumption
• CPU activity
• Reaction time
• Wake-up triggers
• Active peripherals
• Available clock sources
Low energy modes EM1 to EM4 are enabled through the application software. In EM1-EM3, a range of wake-up triggers return the
microcontroller back to EM0. EM4 can only return to EM0 by power on reset, external pin reset, EM4 GPIO wakeup request, or Backup
RTC interrupt.
10.2 Features
• Energy Mode control from software
• Flexible wakeup from low energy modes
• Low wakeup time
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10.3 Functional Description
The Energy Management Unit (EMU) is responsible for managing the wide range of energy modes available in EFM32WG. An over-
view of the EMU module is shown in the following figure.
Peripheral bus
Control and
status registers
Energy Management
State Machine
Cortex
Voltage
regulator
system
Oscillator
system
Reset
system
Memory
system
Interrupt
controller
Figure 10.1. EMU Overview
The EMU is available as a peripheral on the peripheral bus. The energy management state machine is triggered from the Cortex-M4
and controls the internal voltage regulators, oscillators, memories and interrupt systems in the low energy modes. Events from the inter-
rupt or reset systems can in turn cause the energy management state machine to return to its active state. This is further described in
the following sections.
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10.3.1 Energy Modes
There are five main energy modes available in EFM32WG, called Energy Mode 0 (EM0) through Energy Mode 4 (EM4). EM0, also
called the active mode, is the energy mode in which any peripheral function can be enabled and the Cortex-M4 core is executing in-
structions. EM1 through EM4, also called low energy modes, provide a selection of reduced peripheral functionality that also lead to
reduced energy consumption, as described below.
The following figure shows the transitions between different energy modes. After reset the EMU will always start in EM0. A transition
from EM0 to another energy mode is always initiated by software. EM0 is the highest activity mode, in which all functionality is availa-
ble. EM0 is therefore also the mode with highest energy consumption.
The low energy modes EM1 through EM4 result in less functionality being available, and therefore also reduced energy consumption.
The Cortex-M4 is not executing instructions in any low energy mode. Each low energy mode provides different energy consumptions
associated with it, for example because a different set of peripherals are enabled or because these peripherals are configured different-
ly.
A transition from EM0 to a low energy mode can only be triggered by software.
A transition from EM1 – EM3 to EM0 can be triggered by an enabled interrupt or event. In addition, a chip reset will return the device to
EM0. A transition from EM4 can be triggered by a pin reset, poweron reset, EM4 GPIO wakeup, or Backup RTC interrupt.
EM0
EM1
EM2
Software triggered sleep
Interrupt triggered wakeup
Reduced energy consumption
EM3
Low energy
modes
Active
mode
EM4
pin reset,
power-on reset,
EM4 wakeup,
BURTC interrupt
Figure 10.2. EMU Energy Mode Transitions
No direct transitions between EM1, EM2 or EM3 are available, as can also be seen from the previous figure. Instead, a wakeup will
transition back to EM0, in which software can enter any other low energy mode. An overview of the supported energy modes and the
functionality available in each mode is shown in the following table. Most peripheral functionality indicated as "On" in a particular energy
mode can also be turned off from software in order to save further energy.
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Table 10.1. EMU Energy Mode Overview
EM01EM12EM22EM32EM42
Wakeup time to EM0 – – 2 µs 2 µs 160 µs
MCU clock tree On – – – –
High frequency peripheral clock trees On On – – –
Core voltage regulator On On – – –
High frequency oscillator On On – – –
I2C full functionality On On – – –
Low frequency peripheral clock trees On On On – –
Low frequency oscillator On On On – –
Real Time Counter On On On On3–
LCD On On On – –
LEUART On On On – –
LETIMER On On On On3–
LESENSE On On On On3–
PCNT On On On On –
ACMP On On On On –
I2C receive address recognition On On On On –
Watchdog On On On On3–
Pin interrupts On On On On –
RAM voltage regulator/RAM retention On On On On –
Brown Out Reset On On On On –
Power On Reset On On On On On
Pin Reset On On On On On
GPIO state retention On On On On On4
EM4 Reset Wakeup Request – – – – On4
Backup RTC On On On On On
Backup retention registers On On On On On
Note:
1. Energy Mode 0/Active Mode.
2. Energy Mode 1/2/3/4.
3. When the 1 kHz ULFRCO is selected.
4. Not available in Backup mode.
The different Energy Modes are summarized in the following sections.
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10.3.1.1 EM0
• The high frequency oscillator is active
• High frequency clock trees are active
• All peripheral functionality is available
10.3.1.2 EM1
• The high frequency oscillator is active
• MCU clock tree is inactive
• High frequency peripheral clock trees are active
• All peripheral functionality is available
10.3.1.3 EM2
• The high frequency oscillator is inactive
• The high frequency peripheral and MCU clock trees are inactive
• The low frequency oscillator and clock trees are active
• Low frequency peripheral functionality is available
• Wakeup through peripheral interrupt or asynchronous pin interrupt
• RAM and register values are preserved
• DAC and OPAMPs are available
10.3.1.4 EM3
• Both high and low frequency oscillators and clock trees are inactive
•Wakeup through asynchronous pin interrupts, I2C address recognition or ACMP edge interrupt
• Watchdog and some low frequency peripherals available when ULFRCO (1 kHz clock) has been selected
• BURTC is available.
• All other peripheral functionality is disabled
• RAM and register values are preserved
• DAC and OPAMPs are available
10.3.1.5 EM4
• All oscillators and regulators are inactive, if Backup RTC is not enabled.
• RAM and register values are not preserved, except for the ones located in the Backup RTC.
• Optional GPIO state retention
• Wakeup from Backup RTC interrupt, external pin reset, or pins that support EM4 wakeup
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10.3.2 Entering a Low Energy Mode
A low energy mode is entered by first configuring the desired Energy Mode through the EMU_CTRL register and the SLEEPDEEP bit in
the Cortex-M4 System Control Register, see the following table. A Wait For Interrupt (WFI) or Wait For Event (WFE) instruction from the
Cortex-M4 triggers the transition into a low energy mode.
The transition into a low energy mode can optionally be delayed until the lowest priority Interrupt Service Routine (ISR) is exited, if the
SLEEPONEXIT bit in the Cortex-M4 System Control Register is set.
Entering the lowest energy mode, EM4, is done by writing a sequence to the EM4CTRL bitfield in the EMU_CTRL register. Writing a
zero to the EM4CTRL bitfield will restart the power sequence. EM2BLOCK prevents the EMU to enter EM2 or lower, and it will instead
enter EM1.
EM3 is equal to EM2, except that the LFACLK/LFBCLK are disabled in EM3. The LFACLK/LFBCLK must be disabled by the user be-
fore entering low energy mode.
The EMVREG bit in EMU_CTRL can be used to prevent the voltage regulator from being turned off in low energy modes. The device
will then essentially stay in EM1 when entering a low energy mode.
Table 10.2. EMU Entering a Low Energy Mode
Low Energy Mode EM4CTRL EMVREG EM2BLOCK SLEEPDEEP Cortex-M4 Instruc-
tion
EM1 0 X X 0 WFI or WFE
EM2 0 0 0 1 WFI or WFE
EM4 Write sequence:
2, 3, 2, 3, 2, 3, 2, 3,
2
X X X X
Note:
1. (‘X’ means don’t care)
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10.3.3 Leaving a Low Energy Mode
In each low energy mode a selection of peripheral units are available, and software can either enable or disable the functionality. Ena-
bled interrupts that can cause wakeup from a low energy mode are shown in the following table. The wakeup triggers always return the
EFM32 to EM0. Additionally, any reset source will return to EM0.
Table 10.3. EMU Wakeup Triggers from Low Energy Modes
Peripheral Wakeup Trigger EM01EM12EM22EM32EM42
RTC Any enabled interrupt — Yes Yes Yes3—
USART Receive / transmit — Yes — — —
UART Receive / transmit — Yes — — —
LEUART Receive / transmit — Yes Yes — —
LESENSE Any enabled interrupt — Yes Yes Yes3—
I2CAny enabled interrupt — Yes — — —
I2CReceive address recognition — Yes Yes Yes —
TIMER Any enabled interrupt — Yes — — —
LETIMER Any enabled interrupt — Yes Yes Yes3—
CMU Any enabled interrupt — Yes — — —
DMA Any enabled interrupt — Yes — — —
MSC Any enabled interrupt — Yes — — —
DAC Any enabled interrupt — Yes — — —
ADC Any enabled interrupt — Yes — — —
AES Any enabled interrupt — Yes — — —
PCNT Any enabled interrupt — Yes Yes Yes4—
LCD Any enabled interrupt — Yes Yes — —
ACMP Any enabled edge interrupt — Yes Yes Yes —
VCMP Any enabled edge interrupt — Yes Yes Yes —
Pin interrupts Asynchronous — Yes Yes Yes —
Pin Reset — Yes Yes Yes Yes
EM4 wakeup on supported pins Asynchronous — — — — Yes
Backup RTC Any enabled interrupt Yes Yes Yes Yes Yes
Power Cycle Off/On — Yes Yes Yes Yes
Note:
1. Energy Mode 0/Active Mode.
2. Energy mode 1/2/3/4.
3. When the 1 kHz ULFRCO is selected.
4. When using an external clock.
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10.3.4 Backup Power Domain
10.3.4.1 Introduction
The EFM32WG has the possibility to be partly powered by a backup battery. The backup power input, BU_VIN, is connected to a power
domain in the EFM32WG containing the Backup RTC and 512 bytes of data retention, available in all energy modes. The following
figure shows an overview of the backup powering scheme. During normal operation, the entire chip is powered by the main power sup-
ply. If the main power supply drains out and the Backup mode functionality is enabled, the system enters a low energy mode, equiva-
lent to EM4, and automatically switches over to the backup power supply.
EFM32
Main Domain
Backup Domain
BURTC
BOD WDOG
POR EXT
EM4 pin Wake-Up
BURTC
Wake-Up
reset
Wake-up
controller
SW reset
512 byte
retention
Main power OK
BU_VIN
Main power
Backup power
Main power BOD
RESETn
BU_STAT
BU_VOUT
BUCTRL_EN
PWRCONF_VOUTxxx
BUCTRL_STATEN
VDD_DREG
PWRCONF_PWRRES
BUINACT_PWRCON /
BUACT_PWRCON
+
–
+
–
Main power
supply
Backup
power
supply
STRONG
MEDIUM
WEAK
BUBODVDDDREG
BUBODBUVIN
Backup Regulator
BUBODUNREG
BUBODREG
Figure 10.3. Backup Power Domain Overview
When in backup mode, available functionality is the same as the functionality available in EM4. Refer to 10.3.4.10 EM4 with RTC and
Data Retention for further details.
10.3.4.2 Brown Out Detectors
The backup power domain functionality utilizes four brown-out detectors, BODs. One senses the main power supply, one senses the
backup power supply, one senses the unregulated selected power supply (main or backup, depending on mode), and one BOD senses
the regulated power supply. The bits BUBODVDDDREG ,BUBODBUVIN, BUBODUNREG, and BUBODREG in the RSTCAUSE regis-
ter in the RMU are set when the associated BOD triggers. The locations of the Backup BODs are indicated in Figure 10.3 Backup Pow-
er Domain Overview on page 159. A brown out on the main power supply will trigger a switch to the backup power supply if the backup
functionality is enabled and the BOD sensing on the backup power supply has not triggered. The two other BODs are used for error
indication and will only set the bits in RMU_RSTCAUSE if they are triggered.
A reset from backup mode on BUBODUNREG brown-out can also be triggered if BUMODEBODEN in EMU_BUCTRL is set. This will
cause the device to switch back to the main power supply regardless of whether this is valid or not. Set this bit to make sure the device
always asssume a known condition when the backup voltage drops below the operating limits.
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10.3.4.3 Entering Backup Mode
To be able to enter backup mode, the EN bit in EMU_BUCTRL has to be set. The BURDY interrupt flag will be set as soon as the
backup sensing module is operational. Status of the backup functionality is also available in the BURDY flag in the EMU_STATUS reg-
ister. The BU_VIN pin also needs to be enabled. This is done by setting the BUVINPEN bit in EMU_ROUTE. To enter backup mode,
the voltage on VDD_DREG has to drop below the programmable threshold of the BOD sensing on this power. This threshold is pro-
grammed using BUENRANGE and BUENTHRES in EMU_BUINACT. BUENRANGE decides the voltage range for the BOD, while
BUENTHRES is used for tuning of the BOD threshold. Refer to 10.3.4.5 Threshold Calibration for details regarding BOD calibration.
Note: BUVINPEN in EMU_ROUTE is by default set. If Backup mode is not to be used, this bit should be cleared.
Note: The voltage on BU_VIN has to be above the threshold for the BOD sensing on BU_VIN to enter backup mode.
The BU_STAT pin can be used to indicate whether or not the system is in backup mode. To enable exporting of the backup mode
status, set STATEN in EMU_BUCTRL. The BU_STAT pin is driven to BU_VIN when backup mode is active and to ground otherwise.
10.3.4.4 Leaving Backup Mode
To exit backup mode, the voltage on VDD_DREG has to be above the threshold programmed in EMU_BUACT. BUEXRANGE decides
the voltage range for backup mode exit, while BUEXTHRES is used for tuning. When leaving backup mode, a system reset is triggered,
resetting everything except the backup domain. When backup mode has been active, the BURST bit in RMU_RSTCAUSE is set.
EMU_BUACT_BUEXRANGE /
EMU_BUACT_BUEXTHRES
VDDREG
Time
Backup mode active
EMU_BUINACT_BUENRANGE /
EMU_BUINACT_BUENTHRES
Figure 10.4. Entering and Leaving Backup Mode
The previous figure illustrates how the BOD sensing on VDD_DREG can be programmed to implement hysteresis on entering and exit-
ing backup mode.
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10.3.4.5 Threshold Calibration
The thresholds for entering and exiting backup mode are configured in the EMU_BUINACT and EMU_BUACT registers, respectively.
Calibration of these thresholds is performed during production test, but may also be performed using the DAC. The calibration values
for the BODs sensing on unregulated power and BU_VIN, BUBODUNREG and BUBODBUVIN respectively, are available in EMU_BU-
BODVINCAL and EMU_BUBODUNREGCAL. These registers are written during production test and should not be modified except for
calibrating the Backup BOD sensing on VDD_DREG, as described in the following section.
Setting BODCAL in EMU_BUCTRL will enable a mode where the BOD is sensing the DAC output, as depicted in the following figure.
For the BODCAL bit to take effect, the backup power enable bit, EN in EMU_BUCTRL, has to be cleared. The procedure for BOD cali-
bration is as follows:
1. Clear EN and set BODCAL in EMU_BUCTRL.
2. Store the values in EMU_BUBODVINCAL and EMU_BUBODUNREGCAL before clearing these registers.
3. Configure the DAC to output to the maximum level and wait for 500 us before configuring the DAC output to the wanted BOD trig-
ger voltage level.
4. Step through the BOD calibration values (RANGE and THRES in EMU_BUINACT) with 500 us delay in between steps until the
BUBODVDDDREG flag in RMU_RSTCAUSE is set. The RANGE and THRES values in EMU_BUINACT can now be written to
EMU_BUINACT for configuration of threshold for entering backup mode, or EMU_BUACT for configuration of the threshold for
leaving backup mode.
5. Restore the values in EMU_BUBODVINCAL and EMU_BUBODUNREGCAL.
1.8V
+
–
BUCTRL_BODCAL
DAC alternative output
VDD_DREG
BOD trigger
0
1
EMU_BUINACT_BUENRANGE /
EMU_BUINACT_BUENTHRES
Figure 10.5. BOD Calibration Using DAC
10.3.4.6 Backup Battery Charging
The EFM32WG includes functionality for charging of the backup battery. This is done by connecting the main power and the backup
power through a resistor, and optionally a diode. The connection is configured individually for when in backup mode and when in nor-
mal mode. When in normal mode, the connection is configured in PWRCON in EMU_BUINACT. PWRCON in EMU_BUACT configures
the connection when in backup mode. The series resistance between the two power domains is configured in PWRRES in
EMU_PWRCONF, this configuration applies both to backup mode and normal mode.
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10.3.4.7 Supply Voltage Output
To be able to power external devices, the supply voltage for the backup domain is available as an output. Three switches connect the
backup supply voltage to the BU_VOUT pin. To be able to control the series resistance, the switches have different strengths: weak,
medium, and strong. The switches are controlled using the VOUTWEAK, VOUTMED, and VOUTSTRONG bits in EMU_PWRCONF.
For resistor values, refer to Device Datasheet Electrical Characteristics.
10.3.4.8 Voltage Probing
It is possible to probe the voltage levels at VDD_DREG, BU_VIN, and BU_VOUT. This is done by configuring the ADC to measure a
tristated channel, for instance a disabled DAC channel. The PROBE bitfield in EMU_BUCTRL configures which voltage to be probed.
The voltage measured by the ADC will be 1/8 of the actual probed voltage, meaning that the result needs to be multiplied by 8 for the
correct result. Voltage probing does not work when BODCAL in the EMU_BUCTRL register is set.
10.3.4.9 Configuration Lock
Configurations used in Backup mode and EM4, like BOD calibration, and Backup RTC settings need to be locked before entering EM4,
this is done by setting the LOCKCONF bit in EMU_EM4CONF. This bit should also be set before a potential entry to backup mode.
Setting this bit will lock following the configuration:
• LFXOMODE, LFXOBUFCUR, and LFXOBOOST in CMU_CTRL
• TUNING in CMU_LFRCOCTRL
• BURSTEN in RMU_CTRL
• BURTCWU and VREGEN in EMU_EM4CONF
• EMU_BUCTRL
• EMU_PWRCONF
• EMU_BUINACT
• EMU_BUACT
• EMU_ROUTE
Note: For registers residing in the CMU and EMU_AUXCTRL, the reset value will be read after exit from EM4 or Backup mode, but if
LOCKCONF in EMU_EM4CONF has been set, the locked configuration will be used until LOCKCONF is cleared. This also applies for
the LOCKCONF bit itself.
10.3.4.10 EM4 with RTC and Data Retention
The backup power domain can also be powered by the main power. This provides possibility for Backup RTC operation and data reten-
tion in EM4. Available functionality in EM4 is configured in EMU_EM4CONF. Setting the VREGEN bit will keep the voltage regulator for
the Backup domain enabled when in EM4. This allows the Backup RTC to keep running. To enable the Backup RTC to wake up the
system from EM4, BURTCWU in EMU_EM4CONF needs to be set. When BURTCWU is set, any enabled Backup RTC interrupt will
wake up the system. For further details regarding the Backup RTC and EM4 data retention, refer to 22. BURTC - Backup Real Time
Counter.
The voltage regulator can also be used to power the Backup RTC during a watchdog reset from any energy mode. Set
EMU_EM4CONF_VREGEN to enable the Backup RTC to be powered from the regulator, making sure it survives a watchdog reset.
10.3.4.10.1 Oscillators in EM4
When the system is in EM4 or backup mode with the voltage regulator enabled, the ULFRCO is by default enabled. If the LFXO or
LFRCO is used by the Backup RTC, the ULFRCO can be shut down to reduce power consumption. To do this, configure the OSC
bitfield in EMU_EM4CONF.
Note: If OSC in EMU_EM4CONF is not set to ULFRCO, PRESC and LPCOMP in BURTC_CTRL has to be configured in the following
manner:
4 < (PRESC + LPCOMP) < 8, PRESC = 0,5,6,7
Refer to 22. BURTC - Backup Real Time Counter for details on how to configure the Backup RTC.
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10.3.4.10.2 Brown Out Detector in EM4
To enable Brown-out detection in EM4, the Backup BODs have to be enabled, by setting EN in EMU_BUCTRL. When BURDY in
EMU_STATUS is set, the Brown-out detectors are ready and able to issue a reset from EM4 if a Brown-out is detected on either regula-
ted or unregulated power. The Backup BOD' ability to issue reset from EM4 can be disabled by setting BUBODRSTDIS in
EMU_EM4CONF.
Note: The Backup BODs can be enabled without allowing entrance to backup mode. This is done by setting EN in EMU_BUCTRL, and
clearing BUVINPEN in EMU_ROUTE.
10.4 Register Map
The offset register address is relative to the registers base address.
Offset Name Type Description
0x000 EMU_CTRL RW Control Register
0x008 EMU_LOCK RW Configuration Lock Register
0x024 EMU_AUXCTRL RW Auxiliary Control Register
0x02C EMU_EM4CONF RW Energy mode 4 configuration register
0x030 EMU_BUCTRL RW Backup Power configuration register
0x034 EMU_PWRCONF RW Power connection configuration register
0x038 EMU_BUINACT RW Backup mode inactive configuration register
0x03C EMU_BUACT RW Backup mode active configuration register
0x040 EMU_STATUS RStatus register
0x044 EMU_ROUTE RW I/O Routing Register
0x048 EMU_IF RInterrupt Flag Register
0x04C EMU_IFS W1 Interrupt Flag Set Register
0x050 EMU_IFC (R)W1 Interrupt Flag Clear Register
0x054 EMU_IEN RW Interrupt Enable Register
0x058 EMU_BUBODBUVINCAL RW BU_VIN Backup BOD calibration
0x05C EMU_BUBODUNREGCAL RW Unregulated power Backup BOD calibration
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10.5 Register Description
10.5.1 EMU_CTRL - Control Register
Offset Bit Position
0x000
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
16
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
Reset
0x0
0
0
Access
RW
RW
RW
Name
EM4CTRL
EM2BLOCK
EMVREG
Bit Name Reset Access Description
31:4 Reserved To ensure compatibility with future devices, always write bits to 0. More information in 2.1 Conven-
tions.
3:2 EM4CTRL 0x0 RW Energy Mode 4 Control
This register is used to enter Energy Mode 4, in which the device only wakes up from an external pin reset, from a power
cycle, Backup RTC interrupt, or EM4 wakeup reset request. Energy Mode 4 is entered when the EM4 sequence is written
to this bitfield.
1 EM2BLOCK 0 RW Energy Mode 2 Block
This bit is used to prevent the MCU to enter Energy Mode 2 or lower.
0 EMVREG 0 RW Energy Mode Voltage Regulator Control
Control the voltage regulator in low energy modes 2 and 3.
Value Mode Description
0 REDUCED Reduced voltage regulator drive strength in EM2 and EM3.
1 FULL Full voltage regulator drive strength in EM2 and EM3.
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10.5.2 EMU_LOCK - Configuration Lock Register
Offset Bit Position
0x008
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
16
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
Reset
0x0000
Access
RW
Name
LOCKKEY
Bit Name Reset Access Description
31:16 Reserved To ensure compatibility with future devices, always write bits to 0. More information in 2.1 Conven-
tions.
15:0 LOCKKEY 0x0000 RW Configuration Lock Key
Write any other value than the unlock code to lock all EMU registers, except the interrupt registers, from editing. Write the
unlock code to unlock. When reading the register, bit 0 is set when the lock is enabled.
Mode Value Description
Read Operation
UNLOCKED 0 EMU registers are unlocked.
LOCKED 1 EMU registers are locked.
Write Operation
LOCK 0 Lock EMU registers.
UNLOCK 0xADE8 Unlock EMU registers.
10.5.3 EMU_AUXCTRL - Auxiliary Control Register
Offset Bit Position
0x024
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
16
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
Reset
0
Access
RW
Name
HRCCLR
Bit Name Reset Access Description
31:1 Reserved To ensure compatibility with future devices, always write bits to 0. More information in 2.1 Conven-
tions.
0 HRCCLR 0 RW Hard Reset Cause Clear
Write to 1 and then 0 to clear the POR, BOD and WDOG reset cause register bits. See also the Reset Management Unit
(RMU).
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10.5.4 EMU_EM4CONF - Energy Mode 4 Configuration Register
Offset Bit Position
0x02C
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
16
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
Reset
0
0
0x0
0
0
Access
RW
RW
RW
RW
RW
Name
LOCKCONF
BUBODRSTDIS
OSC
BURTCWU
VREGEN
Bit Name Reset Access Description
31:17 Reserved To ensure compatibility with future devices, always write bits to 0. More information in 2.1 Conven-
tions.
16 LOCKCONF 0 RW EM4 configuration lock enable
Lock regulator, BOD and oscillator configuration. This is necessary before going to EM4 if the regulator is to be used in
EM4, and must also be done before a potential entry to backup mode.
15:5 Reserved To ensure compatibility with future devices, always write bits to 0. More information in 2.1 Conven-
tions.
4 BUBODRSTDIS 0 RW Disable reset from Backup BOD in EM4
When set, no reset will be asserted due to Brownout when in EM4.
3:2 OSC 0x0 RW Select EM4 duty oscillator
Value Mode Description
0 ULFRCO ULFRCO is available.
1 LFRCO LFRCO is available. Can only be set if LFRCO is running before EM4/
backup entry.
2 LFXO LFXO is available. Can only be set if LFXO is available before EM4/
backup entry.
1 BURTCWU 0 RW Backup RTC EM4 wakeup enable
Exit EM4 on Backup RTC interrupt.
0 VREGEN 0 RW EM4 voltage regulator enable
When set, the voltage regulator is enabled in EM4, enabling operation of the Backup RTC and retention registers.
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10.5.5 EMU_BUCTRL - Backup Power configuration register
Offset Bit Position
0x030
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
16
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
Reset
0x0
0
0
0
0
Access
RW
RW
RW
RW
RW
Name
PROBE
BUMODEBODEN
BODCAL
STATEN
EN
Bit Name Reset Access Description
31:7 Reserved To ensure compatibility with future devices, always write bits to 0. More information in 2.1 Conven-
tions.
6:5 PROBE 0x0 RW Voltage probe select
Configure which voltage to export to ADC.
Value Mode Description
0 DISABLE Disable voltage probe.
1 VDDDREG Connect probe to VDD_DREG.
2 BUIN Connect probe to BU_IN.
3 BUOUT Connect probe to BU_OUT.
4 Reserved To ensure compatibility with future devices, always write bits to 0. More information in 2.1 Conven-
tions.
3 BUMODEBODEN 0 RW Enable brown out detection on BU_VIN when in backup mode
When set, a reset (and switch back to main power) will be performed when in backup mode and the BUBODUNREG-bod
senses a brown-out on BU_VIN.
2 BODCAL 0 RW Enable BOD calibration mode
When set, the Backup BOD sensing on VDD_DREG will be sensing the DAC output.
1 STATEN 0 RW Enable backup mode status export
When enabled, BU_STAT will indicate when backup mode is active.
0 EN 0 RW Enable backup mode
Backup mode will be entered when main power browns out and backup battery is present.
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10.5.6 EMU_PWRCONF - Power Connection Configuration Register
Offset Bit Position
0x034
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
16
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
Reset
0x0
0
0
0
Access
RW
RW
RW
RW
Name
PWRRES
VOUTSTRONG
VOUTMED
VOUTWEAK
Bit Name Reset Access Description
31:5 Reserved To ensure compatibility with future devices, always write bits to 0. More information in 2.1 Conven-
tions.
4:3 PWRRES 0x0 RW Power domain resistor select
Select value of series resistor between main power domain and backup power domain.
Value Mode Description
0 RES0 Main power and backup power connected with RES0 series resistance.
1 RES1 Main power and backup power connected with RES1 series resistance.
2 RES2 Main power and backup power connected with RES2 series resistance.
3 RES3 Main power and backup power connected with RES3 series resistance.
2 VOUTSTRONG 0 RW BU_VOUT strong enable
Enable strong switch between backup domain power supply and BU_VOUT.
1 VOUTMED 0 RW BU_VOUT medium enable
Enable medium switch between backup domain power supply and BU_VOUT.
0 VOUTWEAK 0 RW BU_VOUT weak enable
Enable weak switch between backup domain power supply and BU_VOUT.
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10.5.7 EMU_BUINACT - Backup Mode Inactive Configuration Register
Offset Bit Position
0x038
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
16
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
Reset
0x0
0x1
0x3
Access
RW
RW
RW
Name
PWRCON
BUENRANGE
BUENTHRES
Bit Name Reset Access Description
31:7 Reserved To ensure compatibility with future devices, always write bits to 0. More information in 2.1 Conven-
tions.
6:5 PWRCON 0x0 RW Power connection configuration when not in Backup mode
Value Mode Description
0 NONE No connection.
1 BUMAIN Main power and backup power are connected through a diode, allow-
ing current to flow from backup power source to main power source,
but not the other way.
2 MAINBU Main power and backup power are connected through a diode, allow-
ing current to flow from main power source to backup power source,
but not the other way.
3 NODIODE Main power and backup power are connected without diode.
4:3 BUENRANGE 0x1 RW
Threshold range for Backup BOD sensing on VDD_DREG when not in backup mode. This field is set to the threshold range
calibrated during production, hence the reset value might differ from device to device.
2:0 BUENTHRES 0x3 RW
Threshold for Backup BOD sensing on VDD_DREG when not in backup mode. This field is set to the threshold value cali-
brated during production, hence the reset value might differ from device to device.
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10.5.8 EMU_BUACT - Backup mode active configuration register
Offset Bit Position
0x03C
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
16
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
Reset
0x0
0x1
0x3
Access
RW
RW
RW
Name
PWRCON
BUEXRANGE
BUEXTHRES
Bit Name Reset Access Description
31:7 Reserved To ensure compatibility with future devices, always write bits to 0. More information in 2.1 Conven-
tions.
6:5 PWRCON 0x0 RW Power connection configuration when in Backup mode
Value Mode Description
0 NONE No connection.
1 BUMAIN Main power and backup power are connected through a diode, allow-
ing current to flow from backup power source to main power source,
but not the other way.
2 MAINBU Main power and backup power are connected through a diode, allow-
ing current to flow from main power source to backup power source,
but not the other way.
3 NODIODE Main power and backup power are connected without diode.
4:3 BUEXRANGE 0x1 RW
Threshold range for Backup BOD sensing on VDD_DREG when in backup mode. This field is set to the threshold range
calibrated during production, hence the reset value might differ from device to device.
2:0 BUEXTHRES 0x3 RW
Threshold for Backup BOD sensing on VDD_DREG when in backup mode. This field is set to the threshold value calibrated
during production, hence the reset value might differ from device to device.
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10.5.9 EMU_STATUS - Status register
Offset Bit Position
0x040
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
16
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
Reset
0
Access
R
Name
BURDY
Bit Name Reset Access Description
31:1 Reserved To ensure compatibility with future devices, always write bits to 0. More information in 2.1 Conven-
tions.
0 BURDY 0 R Backup mode ready
Set when the Backup power functionality is ready.
10.5.10 EMU_ROUTE - I/O Routing Register
Offset Bit Position
0x044
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
16
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
Reset
1
Access
RW
Name
BUVINPEN
Bit Name Reset Access Description
31:1 Reserved To ensure compatibility with future devices, always write bits to 0. More information in 2.1 Conven-
tions.
0 BUVINPEN 1 RW BU_VIN Pin Enable
When set, the BU_VIN pin is enabled.
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10.5.11 EMU_IF - Interrupt Flag Register
Offset Bit Position
0x048
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
16
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
Reset
0
Access
R
Name
BURDY
Bit Name Reset Access Description
31:1 Reserved To ensure compatibility with future devices, always write bits to 0. More information in 2.1 Conven-
tions.
0 BURDY 0 R Backup functionality ready Interrupt Flag
Set when the Backup functionality is ready for use.
10.5.12 EMU_IFS - Interrupt Flag Set Register
Offset Bit Position
0x04C
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
16
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
Reset
0
Access
W1
Name
BURDY
Bit Name Reset Access Description
31:1 Reserved To ensure compatibility with future devices, always write bits to 0. More information in 2.1 Conven-
tions.
0 BURDY 0 W1 Set Backup functionality ready Interrupt Flag
Write to 1 to set the BURDY interrupt flag.
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10.5.13 EMU_IFC - Interrupt Flag Clear Register
Offset Bit Position
0x050
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
16
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
Reset
0
Access
(R)W1
Name
BURDY
Bit Name Reset Access Description
31:1 Reserved To ensure compatibility with future devices, always write bits to 0. More information in 2.1 Conven-
tions.
0 BURDY 0 (R)W1 Clear Backup functionality ready Interrupt Flag
Write to 1 to clear the BURDY interrupt flag.
10.5.14 EMU_IEN - Interrupt Enable Register
Offset Bit Position
0x054
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
16
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
Reset
0
Access
RW
Name
BURDY
Bit Name Reset Access Description
31:1 Reserved To ensure compatibility with future devices, always write bits to 0. More information in 2.1 Conven-
tions.
0 BURDY 0 RW Backup functionality ready Interrupt Enable
Enable interrupt when Backup functionality is ready.
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10.5.15 EMU_BUBODBUVINCAL - BU_VIN Backup BOD calibration
Offset Bit Position
0x058
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
16
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
Reset
0x1
0x3
Access
RW
RW
Name
RANGE
THRES
Bit Name Reset Access Description
31:5 Reserved To ensure compatibility with future devices, always write bits to 0. More information in 2.1 Conven-
tions.
4:3 RANGE 0x1 RW
Threshold range for Backup BOD sensing on BU_VIN. This field is set to the threshold range calibrated during production,
hence the reset value might differ from device to device.
2:0 THRES 0x3 RW
Threshold for Backup BOD sensing on BU_VIN. This field is set to the threshold value calibrated during production, hence
the reset value might differ from device to device.
10.5.16 EMU_BUBODUNREGCAL - Unregulated power Backup BOD calibration
Offset Bit Position
0x05C
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
16
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
Reset
0x1
0x3
Access
RW
RW
Name
RANGE
THRES
Bit Name Reset Access Description
31:5 Reserved To ensure compatibility with future devices, always write bits to 0. More information in 2.1 Conven-
tions.
4:3 RANGE 0x1 RW
Threshold range for Backup BOD sensing on unregulated power. This field is set to the threshold range calibrated during
production, hence the reset value might differ from device to device.
2:0 THRES 0x3 RW
Threshold for Backup BOD sensing on unregulated power. This field is set to the threshold value calibrated during produc-
tion, hence the reset value might differ from device to device.
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11. CMU - Clock Management Unit
43210
Oscillators CMU
WDOG clock
LETIMER clock
LCD clock
Peripheral A clock
Peripheral B clock
Peripheral C clock
Peripheral D clock
CPU clock
Quick Facts
What?
The CMU controls oscillators and clocks. EFM32WG
supports five different oscillators with minimized
power consumption and short start-up time. An addi-
tional separate RC oscillator is used for flash pro-
gramming and debug trace. The CMU also has HW
support for calibration of RC oscillators.
Why?
Oscillators and clocks contribute significantly to the
power consumption of the MCU. With the low power
oscillators combined with the flexible clock control
scheme, it is possible to minimize the energy con-
sumption in any given application.
How?
The CMU can configure different clock sources, ena-
ble/disable clocks to peripherals on an individual ba-
sis and set the prescaler for the different clocks. The
short oscillator start-up times makes duty-cycling be-
tween active mode and the different low energy
modes (EM2-EM4) very efficient. The calibration
feature ensures high accuracy RC oscillators. Sever-
al interrupts are available to avoid CPU polling of
flags.
11.1 Introduction
The Clock Management Unit (CMU) is responsible for controlling the oscillators and clocks on-board the EFM32WG. The CMU pro-
vides the capability to turn on and off the clock on an individual basis to all peripheral modules in addition to enable/disable and config-
ure the available oscillators. The high degree of flexibility enables software to minimize energy consumption in any specific application
by not wasting power on peripherals and oscillators that are inactive.
11.2 Features
• Multiple clock sources available:
• 1-28 MHz High Frequency RC Oscillator (HFRCO)
• 4-48 MHz High Frequency Crystal Oscillator (HFXO)
• 32.768 kHz Low Frequency RC Oscillator (LFRCO)
• 32.768 kHz Low Frequency Crystal Oscillator (LFXO)
• 1 kHz Ultra Low Frequency RC Oscillator (ULFRCO)
• Low power oscillators
• Low start-up times
• Separate prescaler for High Frequency Core Clocks (HFCORECLK) and Peripheral Clocks (HFPERCLK)
• Individual clock prescaler selection for each Low Energy Peripheral
• Clock Gating on an individual basis to core modules and all peripherals
• Selectable clocks can be output on two pins for use externally.
• Auxiliary 1-28 MHz RC oscillator (AUXHFRCO) for flash programming, debug trace, and LESENSE timing.
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11.3 Functional Description
An overview of the CMU is shown in the following figure. The number of peripheral modules that are connected to the different clocks
varies from device to device.
HFXO
HFRCO
LFXO
LFRCO
prescaler
CMU_HFPERCLKEN0.I2C0
HFPERCLKTIMER1
Timeout
Timeout
Timeout
Timeout
HFPERCLKI2C0
CMU_HFPERCLKEN0.TIMER0 HFPERCLKTIMER0
HFCORECLKCM4
CMU_HFPERCLKDIV.HFPERCLKEN
CMU_HFPERCLKEN0.TIMER1
HFCLK
Clock Gate
Clock Gate
EM0
HFCORECLKDMA
CMU_HFCORECLKEN0.DMA
Clock Gate
Clock Gate
Clock Gate
clock
switch
prescaler
HFCORECLKLE
CMU_HFCORECLKEN0.LE
Clock Gate
.
.
.
.
.
.
HFCORECLK
HFPERCLK .
.
.
CMU_HFPERCLKDIV.HFPERCLKDIV
CMU_HFCORECLKDIV
AUXHFRCO
Debug Trace
MSC
(Flash Programming)
Timeout AUXCLK
CMU_CMD.HFCLKSEL
.
.
.
clock
switch
CMU_CTRL_DBGCLK
LESENSE
(High frequency timing)
HFCLK
DIV
CMU_CTRL.HFCLKDIV
clock
switch
CMU_CMD.USBCCLKSEL
HFCORECLKUSBC
CMU_HFCORECLKEN0.USBC
Figure 11.1. CMU Overview - High Frequency Portion
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LFXO
LFRCO
Timeout
Timeout
CMU_LFACLKEN0.RTC
prescaler
Clock Gate LFACLKRTC
CMU_LFACLKEN0.LETIMER0
Clock Gate LFACLKLETIMER0
CMU_LFACLKEN0.LCD
Clock Gate LFACLKLCD
LFACLK
CMU_LFBCLKEN0.LEUART0
Clock Gate
LFBCLKLEUART0
Clock Gate
LFBCLKLEUART1
LFBCLK
clock
switch
clock
switch
prescaler
prescaler
prescaler
prescaler
HFCORECLKLE
CMU_HFCORECLKEN0.LE
Clock Gate
/2 or /4
HFCORECLK
Frame Rate Control
ULFRCO
PCNTnCLK
PCNTn_S0
WDOG
WDOG_CTRL.CLKSEL
CMU_LFCLKSEL.LFB / LFBE
CMU_LFCLKSEL.LFA / LFAE
CMU_LFBCLKEN0.LEUART1
CMU_LCDCTRL.FDIV
CMU_LFBPRESC0.LEUART1
CMU_LFBPRESC0.LEUART0
CMU_LFAPRESC0.LCD
CMU_LFAPRESC0.LETIMER0
CMU_LFAPRESC0.RTC
CMU_PCNTCTRL.PCNTnCLKSEL
LFACLKLCDpre
WDOGCLK
CMU_LFACLKEN0.LESENSE
Clock Gate LFACLKLESENSE
prescaler
CMU_LFAPRESC0.LESENSE
BURTC
Figure 11.2. CMU Overview - Low Frequency Portion
11.3.1 System Clocks
11.3.1.1 HFCLK - High Frequency Clock
HFCLK is the selected High Frequency Clock. This clock is used by the CMU and drives the two prescalers that generate HFCORECLK
and HFPERCLK. The HFCLK can be driven by a high-frequency oscillator (HFRCO or HFXO) or one of the low-frequency oscillators
(LFRCO or LFXO). By default the HFRCO is selected. In most applications, one of the high frequency oscillators will be the preferred
choice. To change the selected HFCLK write to HFCLKSEL in CMU_CMD. The HFCLK is running in EM0 and EM1.
HFCLK can optionally be divided down by setting HFCLKDIV in CMU_CTRL to a nonzero value. This divides down HFCLK to all high
frequency components except the USB Core and is typically used to save energy in USB applications where the system is not required
to run at 48 MHz. Combined with the HFCORECLK and HFPERCLK prescalers the HFCLK divider also allows for more flexible clock
division.
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11.3.1.2 HFCORECLK - High Frequency Core Clock
HFCORECLK is a prescaled version of HFCLK. This clock drives the Core Modules, which consists of the CPU and modules that are
tightly coupled to the CPU, e.g. MSC, DMA etc. This also includes the interface to the Low Energy Peripherals. Some of the modules
that are driven by this clock can be clock gated completely when not in use. This is done by clearing the clock enable bit for the specific
module in CMU_HFCORECLKEN0. The frequency of HFCORECLK is set using the CMU_HFCORECLKDIV register. The setting can
be changed dynamically and the new setting takes effect immediately.
The USB Core clock (USBC) is always undivided regardless of the HFCLKDIV setting. When the USB Core is active this clock must be
switched to a 32 kHz clock (LFRCO or LFXO) when entering EM2. The USB Core uses this clock for monitoring the USB bus. The
switch is done by writing USBCCLKSEL in CMU_CMD. The currently active clock can be checked by reading CMU_STATUS. The
clock switch can take up to 1.5 32 kHz cycle (45 us). To avoid polling the clock selection status when switching switching from 32 kHz
to HFCLK when coming up from EM2 the USBCHFCLKSEL interrupt can be used. EM3 is not supported when the USB is active.
Note: Note that if HFPERCLK runs faster than HFCORECLK, the number of clock cycles for each bus-access to peripheral modules
will increase with the ratio between the clocks. Please refer to 5.2.3.2 Access Performance for more details.
11.3.1.3 HFPERCLK - High Frequency Peripheral Clock
Like HFCORECLK, HFPERCLK can also be a prescaled version of HFCLK. This clock drives the High-Frequency Peripherals. All the
peripherals that are driven by this clock can be clock gated completely when not in use. This is done by clearing the clock enable bit for
the specific peripheral in CMU_HFPERCLKEN0. The frequency of HFPERCLK is set using the CMU_HFPERCLKDIV register. The set-
ting can be changed dynamically and the new setting takes effect immediately.
Note: Note that if HFPERCLK runs faster than HFCORECLK, the number of clock cycles for each bus-access to peripheral modules
will increase with the ratio between the clocks. E.g. if a bus-access normally takes three cycles, it will take 9 cycles if HFPERCLK runs
three times as fast as the HFCORECLK.
11.3.1.4 LFACLK - Low Frequency A Clock
LFACLK is the selected clock for the Low Energy A Peripherals. There are four selectable sources for LFACLK: LFRCO, LFXO,
HFCORECLK/2 and ULFRCO. In addition, the LFACLK can be disabled. From reset, the LFACLK source is set to LFRCO. However,
note that the LFRCO is disabled from reset. The selection is configured using the LFA field in CMU_LFCLKSEL. The HFCORECLK/2
setting allows the Low Energy A Peripherals to be used as high-frequency peripherals.
Note: If HFCORECLK/2 is selected as LFACLK, the clock will stop in EM2/3.
Each Low Energy Peripheral that is clocked by LFACLK has its own prescaler setting and enable bit. The prescaler settings are config-
ured using CMU_LFAPRESC0 and the clock enable bits can be found in CMU_LFACLKEN0. Notice that the LCD has an additional
high resolution prescaler for Frame Rate Control, configured by FDIV in CMU_LCDCTRL. When operating in oversampling mode, the
pulse counters are clocked by LFACLK. This is configured for each pulse counter (n) individually by setting PCNTnCLKSEL in
CMU_PCNTCTRL.
11.3.1.5 LFBCLK - Low Frequency B Clock
LFBCLK is the selected clock for the Low Energy B Peripherals. There are four selectable sources for LFBCLK: LFRCO, LFXO,
HFCORECLK/2 and ULFRCO. In addition, the LFBCLK can be disabled. From reset, the LFBCLK source is set to LFRCO. However,
note that the LFRCO is disabled from reset. The selection is configured using the LFB field in CMU_LFCLKSEL. The HFCORECLK/2
setting allows the Low Energy B Peripherals to be used as high-frequency peripherals.
Note: If HFCORECLK/2 is selected as LFBCLK, the clock will stop in EM2/3.
Each Low Energy Peripheral that is clocked by LFBCLK has its own prescaler setting and enable bit. The prescaler settings are config-
ured using CMU_LFBPRESC0 and the clock enable bits can be found in CMU_LFBCLKEN0.
11.3.1.6 PCNTnCLK - Pulse Counter n Clock
Each available pulse counter is driven by its own clock, PCNTnCLK where n is the pulse counter instance number. Each pulse counter
can be configured to use an external pin (PCNTn_S0) or LFACLK as PCNTnCLK.
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11.3.1.7 WDOGCLK - Watchdog Timer Clock
The Watchdog Timer (WDOG) can be configured to use one of three different clock sources: LFRCO, LFXO or ULFRCO. ULFRCO
(Ultra Low Frequency RC Oscillator) is a separate 1 kHz RC oscillator that also runs in EM3.
11.3.1.8 AUXCLK - Auxiliary Clock
AUXCLK is a 1-28 MHz clock driven by a separate RC oscillator, AUXHFRCO. This clock is used for flash programming, and Serial
Wire Output (SWO), and LESENSE operation. During flash programming, or if needed by LESENSE, this clock will be active. If the
AUXHFRCO has not been enabled explicitly by software, the MSC or LESENSE module will automatically start and stop it. The
AUXHFRCO is enabled by writing a 1 to AUXHFRCOEN in CMU_OSCENCMD. This explicit enabling is required when SWO is used.
11.3.2 Oscillator Selection
11.3.2.1 Start-Up Time
The different oscillators have different start-up times. For the RC oscillators, the start-up time is fixed, but both the LFXO and the HFXO
have configurable start-up time. At the end of the start-up time a ready flag is set to indicated that the start-up time has exceeded and
that the clock is available. The low start-up time values can be used for an external clock source of already high quality, while the higher
start-up times should be used when the clock signal is coming directly from a crystal. The start-up time for HFXO and LFXO can be set
by configuring the HFXOTIMEOUT and LFXOTIMEOUT bitfields, respectively. Both bitfields are located in CMU_CTRL. For HFXO it is
also possible to enable a glitch detection filter by setting HFXOGLITCHDETEN in CMU_CTRL. The glitch detector will reset the start-up
counter if a glitch is detected, making the start-up process start over again.
There are individual bits for each oscillator indicating the status of the oscillator:
• ENABLED - Indicates that the oscillator is enabled
• READY - Start-up time is exceeded
• SELECTED - Start-up time is exceeded and oscillator is chosen as clock source
These status bits are located in the CMU_STATUS register.
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WWW
WWW
11.3.2.2 Switching Clock Source
The HFRCO oscillator is a low energy oscillator with extremely short wake-up time. Therefore, this oscillator is always chosen by hard-
ware as the clock source for HFCLK when the device starts up (e.g. after reset and after waking up from EM2 and EM3). After reset,
the HFRCO frequency is 14 MHz.
Software can switch between the different clock sources at run-time. E.g., when the HFRCO is the clock source, software can switch to
HFXO by writing the field HFCLKSEL in the CMU_CMD command register. See the following figure for a description of the sequence of
events for this specific operation.
Note: It is important first to enable the HFXO since switching to a disabled oscillator will effectively stop HFCLK and only a reset can
recover the system.
During the start-up period HFCLK will stop since the oscillator driving it is not ready. This effectively stalls the Core Modules and the
High-Frequency Peripherals. It is possible to avoid this by first enabling the HFXO and then wait for the oscillator to become ready
before switching the clock source. This way, the system continues to run on the HFRCO until the HFXO has timed out and provides a
reliable clock. This sequence of events is shown in Figure 11.4 CMU Switching from HFRCO to HFXO After HFXO is Ready on page
181.
A separate flag is set when the oscillator is ready. This flag can also be configured to generate an interrupt.
HFXO
CMU_STATUS..HFXORDY
CMU_STATUS.HFXOENS
CMU_STATUS.HFXOSEL
HFRCO
HFCLK
HFXO time-out period
CMU_STATUS.HFRCORDY
CMU_STATUS.HFRCOENS
CMU_STATUS.HFRCOSEL
CMU_OSCENCMD.HFXOEN
CMU_OSCENCMD.HFXODIS
clocks
CMU_CMD.HFCLKSEL
CMU_OSCENCMD.HFRCOEN
CMU_OSCENCMD.HFRCODIS
command
status
00 02 00
Figure 11.3. CMU Switching from HFRCO to HFXO Before HFXO is Ready
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00 02 00
HFXO
CMU_STATUS.HFXORDY
CMU_STATUS.HFXOENS
CMU_STATUS.HFXOSEL
HFRCO
HFCLK
HFXO time-out period
CMU_STATUS.HFRCORDY
CMU_STATUS.HFRCOENS
CMU_STATUS.HFRCOSEL
CMU_OSCENCMD.HFXOEN
CMU_OSCENCMD.HFXODIS
clocks
CMU_CMD.HFCLKSEL
CMU_OSCENCMD.HFRCOEN
CMU_OSCENCMD.HFRCODIS
command
status
Figure 11.4. CMU Switching from HFRCO to HFXO After HFXO is Ready
Switching clock source for LFACLK and LFBCLK is done by setting the LFA and LFB fields in CMU_LFCLKSEL. To ensure no stalls in
the Low Energy Peripherals, the clock source should be ready before switching to it.
Note: To save energy, remember to turn off all oscillators not in use.
11.3.3 Oscillator Configuration
11.3.3.1 HFXO and LFXO
The crystal oscillators are by default configured to ensure safe startup and operation of the most common crystals. In order to optimize
startup margin, startup time and power consumption for a given crystal, it is possible to adjust the gain in the oscillator. HFXO gain can
be increased by setting HFXOBOOST field in CMU_CTRL, LFXO gain can be increased by setting LFXOBOOST field in CMU_CTRL. It
is important that the boost settings, along with the crystal load capacitors are matched to the crystals in use. Correct values for these
parameters can be found using Hardware Configurator in Simplicity Studio.
The HFXO crystal is connected to the HFXTAL_N/HFXTAL_P pins as shown in the following figure.
DEVICE
HFXTAL_N
HFXTAL_P
4-32 MHz
CL1 CL2
Figure 11.5. HFXO Pin Connection
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Similarly, the LFXO crystal is connected to the LFXTAL_N/LFXTAL_P pins as shown in the following figure.
Device
LFXTAL_N
LFXTAL_P
32.768kHz
CL1 CL2
Figure 11.6. LFXO Pin Connection
It is possible to connect an external clock source to HFXTAL_N/LFXTAL_N pin of the HFXO or LFXO oscillator. By configuring the
HFXOMODE/LFXOMODE fields in CMU_CTRL, the HFXO/LFXO can be bypassed.
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11.3.3.2 HFRCO, LFRCO, and AUXHFRCO
It is possible to calibrate the HFRCO, LFRCO and AUXHFRCO to achieve higher accuracy (see the device datasheets for details on
accuracy). The frequency is adjusted by changing the TUNING fields in CMU_HFRCOCTRL/CMU_LFRCOCTRL/CMU_AUXHFR-
COCTRL. Changing to a higher value will result in a higher frequency. Please refer to the datasheet for stepsize details.
The HFRCO and AUXHFRCO can be set to one of several different frequency bands from 1 MHz to 28 MHz by setting the BAND field
in CMU_HFRCOCTRL and CMU_AUXHFRCOCTRL.The HFRCO and AUXHFRCO frequency bands are calibrated during production
test, and the production tested calibration values can be read from the Device Information (DI) page. The DI page contains a separate
tuning value for each frequency band. During reset, HFRCO and AUXHFRCO tuning values are set to the production calibrated values
for the 14 MHz band, which is the default frequency band. When changing to a different HFRCO or AUXHFRCO band, make sure to
also update the tuning value.
The LFRCO and is also calibrated in production and its TUNING value is set to the correct value during reset.
The CMU has built-in HW support to efficiently calibrate the RC oscillators at run-time, see the following figure. The concept is to select
a reference and compare the RC frequency with the reference frequency. When the calibration circuit is started, one down-counter run-
ning on a selectable clock (DOWNSEL in CMU_CALCTRL) and one up-counter running on a selectable clock (UPSEL in
CMU_CALCTRL) are started simultaneously. The top value for the down-counter must be written to CMU_CALCNT before calibration is
started. The smallest value that can be written to the CMU_CALCNT is 1. The down-counter counts for CMU_CALCNT+1 cycles. When
the down-counter has reached 0, the up-counter is sampled and the CALRDY interrupt flag is set. If CONT in CMU_CALCTRL is
cleared, the counters are stopped at this point. If continuous mode is selected by setting CONT in CMU_CALCTRL the down-counter
reloads the top value and continues counting and the up-counter restarts from 0. Software can then read out the sampled up-counter
value from CMU_CALCNT. Then it is easy to find the ratio between the reference and the oscillator subject to the calibration. Overflows
of the up-counter will not occur. If the up-counter reaches its top value before the down counter reaches 0, the top counter stays at its
top value. Calibration can be stopped by writing CALSTOP in CMU_CMD. With this HW support, it is simple to write efficient calibration
algorithms in software.
CMU_CALCTRL.REFSEL
AUXHFRCO
HFRCO
LFRCO
HFXO
LFXO
20-bit up-counter
CMU_CALCTRL.DOWNSEL
AUXHFRCO
HFRCO
LFRCO
HFXO
LFXO
TOP
Write top-value using
CMU_CALCNT before
starting calibration.
DOWNCLK Domain
UPCLK Domain
HFCLK Domain
= 0 ?
SYNC
(Default) HFCLK
SYNC
20-bit up-counter
buffer
SYNC
20-bit down-counter
Set CMU_IF.CALRDY
CMU_CALCNT
DOWNCLK
UPCLK
Reload down-counter with
top value in continouous
mode.
Take snapshot of up-counter in
up-counter bufffer. If in
continouous mode, restart up-
counter from 0.
Figure 11.7. HW Support for RC Oscillator Calibration
The counter operation for single and continuous mode are shown in the following figures.
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TOP
0
Calibration Started Calibration Stopped
(counters stopped)
0
Down-counter
Up-counter
Up-counter sampled and
CALRDY interrupt flag set.
Sampled value available in
CMU_CALCNT.
Figure 11.8. Single Calibration (CONT=0)
TOP
0
Calibration Started
0
Down-counter
Up-counter
Up-counter sampled and
CALRDY interrupt flag set.
Sampled value available in
CMU_CALCNT.
Up-counter sampled and
CALRDY interrupt flag set.
Sampled value available in
CMU_CALCNT.
Figure 11.9. Continuous Calibration (CONT=1)
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11.3.4 Configuration For Operating Frequencies
The HFXO is capable of driving crystals up to 48 MHz, which allows the EFM32 to run at up to this frequency. Different frequencies
have different requirements as shown in the following table. Before going to a high frequency, make sure the registers in the table have
the correct values. When going down in frequency, make sure to keep the registers at the values required by the higher frequency until
after the switch has been done.
Table 11.1. Table 11.1. Configuration For Operating Frequencies
Maximum Fre-
quency
MODE in MSC_READCTRL HFLE in
CMU_CTRL
HFXOBUFCUR in CMU_CTRL
16 MHz WS0 / WS0SCBTP / WS1 / WS1SCBTP / WS2 /
WS2SCBTP
— BOOSTUPTO32MHZ (default value)
24 MHz WS1 / WS1SCBTP / WS2 / WS2SCBTP — BOOSTUPTO32MHZ (default value)
32 MHz WS1 / WS1SCBTP / WS2 / WS2SCBTP 1 BOOSTUPTO32MHZ (default value)
48 MHz WS2 / WS2SCBTP 1 BOOSTABOVE32MHZ
MODE in MSC_READCTRL makes sure the flash is able to operate at the given frequencies by inserting waitstates for flash accesses.
HFXOBUFCUR in CMU_CTRL should be set to BOOSTABOVE32MHZ when operating above 32 MHz. When operating at 32 MHz or
below, the default value (BOOSTUPTO32MHZ) should be used. HFLE in CMU_CTRL is only required for frequencies above 24 MHz,
and ensures correct operation of LE peripherals. The CMU_CTRL_HFLE is or'ed with HFCORECLKLEDIV in CMU_HFCORECLKDIV,
so setting either of this bits will reduce the the frequency of CMU_HFCORECLKLEDIV2.
11.3.5 Output Clock on a Pin
It is possible to configure the CMU to output clocks on two pins. This clock selection is done using CLKOUTSEL0 and CLKOUTSEL1
fields in CMU_CTRL. The output pins must be configured in the CMU_ROUTE register.
• LFRCO, LFXO, HFCLK or the qualified clock from any of the oscillators can be output on one pin (CMU_OUT1). A qualified clock
will not have any glitches or skewed duty-cycle during startup. For LFXO and HFXO you need to configure LFXOTIMEOUT and
HFXOTIMEOUT in CMU_CTRL correctly to guarantee a qualified clock.
• HFRCO, HFXO, HFCLK/2, HFCLK/4, HFCLK/8, HFCLK/16, ULFRCO or AUXHFRCO can be output on another pin (CMU_OUT0)
Note that HFXO and HFRCO clock outputs to pin can be unstable after startup and should not be output on a pin before HFXORDY/
HFRCORDY is set high in CMU_STATUS.
11.3.6 Protection
It is possible to lock the control- and command registers to prevent unintended software writes to critical clock settings. This is control-
led by the CMU_LOCK register.
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11.4 Register Map
The offset register address is relative to the registers base address.
Offset Name Type Description
0x000 CMU_CTRL RW CMU Control Register
0x004 CMU_HFCORECLKDIV RW High Frequency Core Clock Division Register
0x008 CMU_HFPERCLKDIV RW High Frequency Peripheral Clock Division Register
0x00C CMU_HFRCOCTRL RW HFRCO Control Register
0x010 CMU_LFRCOCTRL RW LFRCO Control Register
0x014 CMU_AUXHFRCOCTRL RW AUXHFRCO Control Register
0x018 CMU_CALCTRL RW Calibration Control Register
0x01C CMU_CALCNT RWH Calibration Counter Register
0x020 CMU_OSCENCMD W1 Oscillator Enable/Disable Command Register
0x024 CMU_CMD W1 Command Register
0x028 CMU_LFCLKSEL RW Low Frequency Clock Select Register
0x02C CMU_STATUS RStatus Register
0x030 CMU_IF RInterrupt Flag Register
0x034 CMU_IFS W1 Interrupt Flag Set Register
0x038 CMU_IFC (R)W1 Interrupt Flag Clear Register
0x03C CMU_IEN RW Interrupt Enable Register
0x040 CMU_HFCORECLKEN0 RW High Frequency Core Clock Enable Register 0
0x044 CMU_HFPERCLKEN0 RW High Frequency Peripheral Clock Enable Register 0
0x050 CMU_SYNCBUSY RSynchronization Busy Register
0x054 CMU_FREEZE RW Freeze Register
0x058 CMU_LFACLKEN0 RW Low Frequency A Clock Enable Register 0 (Async Reg)
0x060 CMU_LFBCLKEN0 RW Low Frequency B Clock Enable Register 0 (Async Reg)
0x068 CMU_LFAPRESC0 RW Low Frequency A Prescaler Register 0 (Async Reg)
0x070 CMU_LFBPRESC0 RW Low Frequency B Prescaler Register 0 (Async Reg)
0x078 CMU_PCNTCTRL RW PCNT Control Register
0x07C CMU_LCDCTRL RW LCD Control Register
0x080 CMU_ROUTE RW I/O Routing Register
0x084 CMU_LOCK RW Configuration Lock Register
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11.5 Register Description
11.5.1 CMU_CTRL - CMU Control Register
Offset Bit Position
0x000
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
16
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
Reset
0
0
0x0
0x0
0x3
0
0x0
1
0x0
0x3
0
0x1
0x3
0x0
Access
RW
RW
RW
RW
RW
RW
RW
RW
RW
RW
RW
RW
RW
RW
Name
HFLE
DBGCLK
CLKOUTSEL1
CLKOUTSEL0
LFXOTIMEOUT
LFXOBUFCUR
HFCLKDIV
LFXOBOOST
LFXOMODE
HFXOTIMEOUT
HFXOGLITCHDETEN
HFXOBUFCUR
HFXOBOOST
HFXOMODE
Bit Name Reset Access Description
31 Reserved To ensure compatibility with future devices, always write bits to 0. More information in 2.1 Conven-
tions.
30 HFLE 0 RW High-Frequency LE Interface
Set to allow access to LE peripherals when running at frequencies higher than 24 MHz. Or'ed with CMU_HFCORECLK-
DIV_HFCORECLKLEDIV to reduce the frequency of CMU_HFCORECLKLEDIV2.
29 Reserved To ensure compatibility with future devices, always write bits to 0. More information in 2.1 Conven-
tions.
28 DBGCLK 0 RW Debug Clock
Select clock used for the debug system.
Value Mode Description
0 AUXHFRCO AUXHFRCO is the debug clock.
1 HFCLK The system clock is the debug clock.
27 Reserved To ensure compatibility with future devices, always write bits to 0. More information in 2.1 Conven-
tions.
26:23 CLKOUTSEL1 0x0 RW Clock Output Select 1
Controls the clock output multiplexer. To actually output on the pin, set CLKOUT1PEN in CMU_ROUTE.
Value Mode Description
0 LFRCO LFRCO (directly from oscillator).
1 LFXO LFXO (directly from oscillator).
2 HFCLK HFCLK (undivided).
3 LFXOQ LFXO (qualified).
4 HFXOQ HFXO (qualified).
5 LFRCOQ LFRCO (qualified).
6 HFRCOQ HFRCO (qualified).
7 AUXHFRCOQ AUXHFRCO (qualified).
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Bit Name Reset Access Description
22:20 CLKOUTSEL0 0x0 RW Clock Output Select 0
Controls the clock output multiplexer. To actually output on the pin, set CLKOUT0PEN in CMU_ROUTE.
Value Mode Description
0 HFRCO HFRCO (directly from oscillator).
1 HFXO HFXO (directly from oscillator).
2 HFCLK2 HFCLK/2.
3 HFCLK4 HFCLK/4.
4 HFCLK8 HFCLK/8.
5 HFCLK16 HFCLK/16.
6 ULFRCO ULFRCO (directly from oscillator).
7 AUXHFRCO AUXHFRCO (directly from oscillator).
19:18 LFXOTIMEOUT 0x3 RW LFXO Timeout
Configures the start-up delay for LFXO.
Value Mode Description
0 8CYCLES Timeout period of 8 cycles.
1 1KCYCLES Timeout period of 1024 cycles.
2 16KCYCLES Timeout period of 16384 cycles.
3 32KCYCLES Timeout period of 32768 cycles.
17 LFXOBUFCUR 0 RW LFXO Boost Buffer Current
This value has been updated to the correct level during calibration and should not be changed.
16:14 HFCLKDIV 0x0 RW HFCLK Division
Use to divide HFCLK frequency by (HFCLKDIV + 1).
13 LFXOBOOST 1 RW LFXO Start-up Boost Current
Adjusts start-up boost current for LFXO.
Value Mode Description
0 70PCENT 70 %.
1 100PCENT 100 %.
12:11 LFXOMODE 0x0 RW LFXO Mode
Set this to configure the external source for the LFXO. The oscillator setting takes effect when 1 is written to LFXOEN in
CMU_OSCENCMD. The oscillator setting is reset to default when 1 is written to LFXODIS in CMU_OSCENCMD.
Value Mode Description
0 XTAL 32.768 kHz crystal oscillator.
1 BUFEXTCLK An AC coupled buffer is coupled in series with LFXTAL_N pin, suitable
for external sinus wave (32.768 kHz).
2 DIGEXTCLK Digital external clock on LFXTAL_N pin. Oscillator is effectively by-
passed.
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Bit Name Reset Access Description
10:9 HFXOTIMEOUT 0x3 RW HFXO Timeout
Configures the start-up delay for HFXO.
Value Mode Description
0 8CYCLES Timeout period of 8 cycles.
1 256CYCLES Timeout period of 256 cycles.
2 1KCYCLES Timeout period of 1024 cycles.
3 16KCYCLES Timeout period of 16384 cycles.
8 Reserved To ensure compatibility with future devices, always write bits to 0. More information in 2.1 Conven-
tions.
7 HFXOGLITCHDET-
EN
0 RW HFXO Glitch Detector Enable
This bit enables the glitch detector which is active as long as the start-up ripple-counter is counting. A detected glitch will
reset the ripple-counter effectively increasing the start-up time. Once the ripple-counter has timed-out, glitches will not be
detected.
6:5 HFXOBUFCUR 0x1 RW HFXO Boost Buffer Current
The current level in the HFXO buffer should be set to default value when operating on 32 MHz or below. When operating on
frequencies above 32 MHz, the buffer current level should be set to 3.
Value Mode Description
1 BOOSTUPTO32MHZ Boost Buffer Current level when HFXO is below or equal to 32 MHz.
3 BOOSTABOVE32MHZ Boost Buffer Current Level when HFXO is above 32 MHz.
4 Reserved To ensure compatibility with future devices, always write bits to 0. More information in 2.1 Conven-
tions.
3:2 HFXOBOOST 0x3 RW HFXO Start-up Boost Current
Used to adjust start-up boost current for HFXO.
Value Mode Description
0 50PCENT 50 %.
1 70PCENT 70 %.
2 80PCENT 80 %.
3 100PCENT 100 % (default).
1:0 HFXOMODE 0x0 RW HFXO Mode
Set this to configure the external source for the HFXO. The oscillator setting takes effect when 1 is written to HFXOEN in
CMU_OSCENCMD. The oscillator setting is reset to default when 1 is written to HFXODIS in CMU_OSCENCMD.
Value Mode Description
0 XTAL 4-48 crystal oscillator.
1 BUFEXTCLK An AC coupled buffer is coupled in series with HFXTAL_N, suitable for
external sine wave (4-48). The sine wave should have a minimum of
200 mV peak to peak.
2 DIGEXTCLK Digital external clock on HFXTAL_N pin. Oscillator is effectively by-
passed.
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11.5.2 CMU_HFCORECLKDIV - High Frequency Core Clock Division Register
Offset Bit Position
0x004
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
16
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
Reset
0
0x0
Access
RW
RW
Name
HFCORECLKLEDIV
HFCORECLKDIV
Bit Name Reset Access Description
31:9 Reserved To ensure compatibility with future devices, always write bits to 0. More information in 2.1 Conven-
tions.
8 HFCORECLKLEDIV 0 RW Additional Division Factor For HFCORECLKLE
Additional division factor for HFCORECLKLE. When running at frequencies higher than 24 MHz, this must be set to DIV4.
Value Mode Description
0 DIV2 Valid for frequencies 24 MHz and lower.
1 DIV4 Must be used when HFCORECLK may go above 24 MHz.
7:4 Reserved To ensure compatibility with future devices, always write bits to 0. More information in 2.1 Conven-
tions.
3:0 HFCORECLKDIV 0x0 RW HFCORECLK Divider
Specifies the clock divider for HFCORECLK.
Value Mode Description
0 HFCLK HFCORECLK = HFCLK.
1 HFCLK2 HFCORECLK = HFCLK/2.
2 HFCLK4 HFCORECLK = HFCLK/4.
3 HFCLK8 HFCORECLK = HFCLK/8.
4 HFCLK16 HFCORECLK = HFCLK/16.
5 HFCLK32 HFCORECLK = HFCLK/32.
6 HFCLK64 HFCORECLK = HFCLK/64.
7 HFCLK128 HFCORECLK = HFCLK/128.
8 HFCLK256 HFCORECLK = HFCLK/256.
9 HFCLK512 HFCORECLK = HFCLK/512.
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11.5.3 CMU_HFPERCLKDIV - High Frequency Peripheral Clock Division Register
Offset Bit Position
0x008
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
16
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
Reset
1
0x0
Access
RW
RW
Name
HFPERCLKEN
HFPERCLKDIV
Bit Name Reset Access Description
31:9 Reserved To ensure compatibility with future devices, always write bits to 0. More information in 2.1 Conven-
tions.
8 HFPERCLKEN 1 RW HFPERCLK Enable
Set to enable the HFPERCLK.
7:4 Reserved To ensure compatibility with future devices, always write bits to 0. More information in 2.1 Conven-
tions.
3:0 HFPERCLKDIV 0x0 RW HFPERCLK Divider
Specifies the clock divider for the HFPERCLK.
Value Mode Description
0 HFCLK HFPERCLK = HFCLK.
1 HFCLK2 HFPERCLK = HFCLK/2.
2 HFCLK4 HFPERCLK = HFCLK/4.
3 HFCLK8 HFPERCLK = HFCLK/8.
4 HFCLK16 HFPERCLK = HFCLK/16.
5 HFCLK32 HFPERCLK = HFCLK/32.
6 HFCLK64 HFPERCLK = HFCLK/64.
7 HFCLK128 HFPERCLK = HFCLK/128.
8 HFCLK256 HFPERCLK = HFCLK/256.
9 HFCLK512 HFPERCLK = HFCLK/512.
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11.5.4 CMU_HFRCOCTRL - HFRCO Control Register
Offset Bit Position
0x00C
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
16
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
Reset
0x00
0x3
0x80
Access
RW
RW
RW
Name
SUDELAY
BAND
TUNING
Bit Name Reset Access Description
31:17 Reserved To ensure compatibility with future devices, always write bits to 0. More information in 2.1 Conven-
tions.
16:12 SUDELAY 0x00 RW HFRCO Start-up Delay
Always write this field to 0.
11 Reserved To ensure compatibility with future devices, always write bits to 0. More information in 2.1 Conven-
tions.
10:8 BAND 0x3 RW HFRCO Band Select
Write this field to set the frequency band in which the HFRCO is to operate. When changing this setting there will be no
glitches on the HFRCO output, hence it is safe to change this setting even while the system is running on the HFRCO. To
ensure an accurate frequency, the HFTUNING value should also be written when changing the frequency band. The cali-
brated tuning value for the different bands can be read from the Device Information page.
Value Mode Description
0 1MHZ 1 MHz band. NOTE: Also set the TUNING value (bits 7:0) when chang-
ing band.
1 7MHZ 7 MHz band. NOTE: Also set the TUNING value (bits 7:0) when chang-
ing band.
2 11MHZ 11 MHz band. NOTE: Also set the TUNING value (bits 7:0) when
changing band.
3 14MHZ 14 MHz band. NOTE: Also set the TUNING value (bits 7:0) when
changing band.
4 21MHZ 21 MHz band. NOTE: Also set the TUNING value (bits 7:0) when
changing band.
5 28MHZ 28 MHz band. NOTE: Also set the TUNING value (bits 7:0) when
changing band.
7:0 TUNING 0x80 RW HFRCO Tuning Value
Writing this field adjusts the HFRCO frequency (the higher value, the higher frequency). This field is updated with the pro-
duction calibrated value for the 14 MHz band during reset, and the reset value might therefore vary between devices.
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11.5.5 CMU_LFRCOCTRL - LFRCO Control Register
Offset Bit Position
0x010
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
16
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
Reset
0x40
Access
RW
Name
TUNING
Bit Name Reset Access Description
31:7 Reserved To ensure compatibility with future devices, always write bits to 0. More information in 2.1 Conven-
tions.
6:0 TUNING 0x40 RW LFRCO Tuning Value
Writing this field adjusts the LFRCO frequency (the higher value, the higher frequency). This field is updated with the pro-
duction calibrated value during reset, and the reset value might therefore vary between devices.
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11.5.6 CMU_AUXHFRCOCTRL - AUXHFRCO Control Register
Offset Bit Position
0x014
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
16
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
Reset
0x0
0x80
Access
RW
RW
Name
BAND
TUNING
Bit Name Reset Access Description
31:11 Reserved To ensure compatibility with future devices, always write bits to 0. More information in 2.1 Conven-
tions.
10:8 BAND 0x0 RW AUXHFRCO Band Select
Write this field to set the frequency band in which the AUXHFRCO is to operate. When changing this setting there will be no
glitches on the AUXHFRCO output, hence it is safe to change this setting even while the system is using the AUXHFRCO.
To ensure an accurate frequency, the AUXTUNING value should also be written when changing the frequency band. The
calibrated tuning value for the different bands can be read from the Device Information page. Flash erase and write use this
clock. If it is changed to another value than the default, MSC_TIMEBASE must also be configured to ensure correct flash
erase and write operation.
Value Mode Description
0 14MHZ 14 MHz band. NOTE: Also set the TUNING value (bits 7:0) when
changing band.
1 11MHZ 11 MHz band. NOTE: Also set the TUNING value (bits 7:0) when
changing band.
2 7MHZ 7 MHz band. NOTE: Also set the TUNING value (bits 7:0) when chang-
ing band.
3 1MHZ 1 MHz band. NOTE: Also set the TUNING value (bits 7:0) when chang-
ing band.
6 28MHZ 28 MHz band. NOTE: Also set the TUNING value (bits 7:0) when
changing band.
7 21MHZ 21 MHz band. NOTE: Also set the TUNING value (bits 7:0) when
changing band.
7:0 TUNING 0x80 RW AUXHFRCO Tuning Value
Writing this field adjusts the AUXHFRCO frequency (the higher value, the higher frequency).This field is updated with the
production calibrated value during reset, and the reset value might therefore vary between devices.
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11.5.7 CMU_CALCTRL - Calibration Control Register
Offset Bit Position
0x018
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
16
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
Reset
0
0x0
0x0
Access
RW
RW
RW
Name
CONT
DOWNSEL
UPSEL
Bit Name Reset Access Description
31:7 Reserved To ensure compatibility with future devices, always write bits to 0. More information in 2.1 Conven-
tions.
6 CONT 0 RW Continuous Calibration
Set this bit to enable continuous calibration.
5:3 DOWNSEL 0x0 RW Calibration Down-counter Select
Selects clock source for the calibration down-counter.
Value Mode Description
0 HFCLK Select HFCLK for down-counter.
1 HFXO Select HFXO for down-counter.
2 LFXO Select LFXO for down-counter.
3 HFRCO Select HFRCO for down-counter.
4 LFRCO Select LFRCO for down-counter.
5 AUXHFRCO Select AUXHFRCO for down-counter.
2:0 UPSEL 0x0 RW Calibration Up-counter Select
Selects clock source for the calibration up-counter.
Value Mode Description
0 HFXO Select HFXO as up-counter.
1 LFXO Select LFXO as up-counter.
2 HFRCO Select HFRCO as up-counter.
3 LFRCO Select LFRCO as up-counter.
4 AUXHFRCO Select AUXHFRCO as up-counter.
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11.5.8 CMU_CALCNT - Calibration Counter Register
Offset Bit Position
0x01C
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
16
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
Reset
0x00000
Access
RWH
Name
CALCNT
Bit Name Reset Access Description
31:20 Reserved To ensure compatibility with future devices, always write bits to 0. More information in 2.1 Conven-
tions.
19:0 CALCNT 0x00000 RWH Calibration Counter
Write top value before calibration. Read calibration result from this register when Calibration Ready flag has been set.
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11.5.9 CMU_OSCENCMD - Oscillator Enable/Disable Command Register
Offset Bit Position
0x020
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
16
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
Reset
0
0
0
0
0
0
0
0
0
0
Access
W1
W1
W1
W1
W1
W1
W1
W1
W1
W1
Name
LFXODIS
LFXOEN
LFRCODIS
LFRCOEN
AUXHFRCODIS
AUXHFRCOEN
HFXODIS
HFXOEN
HFRCODIS
HFRCOEN
Bit Name Reset Access Description
31:10 Reserved To ensure compatibility with future devices, always write bits to 0. More information in 2.1 Conven-
tions.
9 LFXODIS 0 W1 LFXO Disable
Disables the LFXO. LFXOEN has higher priority if written simultaneously.
8 LFXOEN 0 W1 LFXO Enable
Enables the LFXO.
7 LFRCODIS 0 W1 LFRCO Disable
Disables the LFRCO. LFRCOEN has higher priority if written simultaneously.
6 LFRCOEN 0 W1 LFRCO Enable
Enables the LFRCO.
5 AUXHFRCODIS 0 W1 AUXHFRCO Disable
Disables the AUXHFRCO. AUXHFRCOEN has higher priority if written simultaneously. WARNING: Do not disable this
clock during a flash erase/write operation.
4 AUXHFRCOEN 0 W1 AUXHFRCO Enable
Enables the AUXHFRCO.
3 HFXODIS 0 W1 HFXO Disable
Disables the HFXO. HFXOEN has higher priority if written simultaneously. WARNING: Do not disable the HFRXO if this
oscillator is selected as the source for HFCLK.
2 HFXOEN 0 W1 HFXO Enable
Enables the HFXO.
1 HFRCODIS 0 W1 HFRCO Disable
Disables the HFRCO. HFRCOEN has higher priority if written simultaneously. WARNING: Do not disable the HFRCO if this
oscillator is selected as the source for HFCLK.
0 HFRCOEN 0 W1 HFRCO Enable
Enables the HFRCO.
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11.5.10 CMU_CMD - Command Register
Offset Bit Position
0x024
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
16
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
Reset
0x0
0
0
0x0
Access
W1
W1
W1
W1
Name
USBCCLKSEL
CALSTOP
CALSTART
HFCLKSEL
Bit Name Reset Access Description
31:8 Reserved To ensure compatibility with future devices, always write bits to 0. More information in 2.1 Conven-
tions.
7:5 USBCCLKSEL 0x0 W1 USB Core Clock Select
Selects the clock for HFCORECLKUSBC. The status register is updated when the clock switch has taken effect.
Value Mode Description
1 HFCLKNODIV Select HFCLK (undivided) as HFCORECLKUSBC.
2 LFXO Select LFXO as HFCORECLKUSBC.
3 LFRCO Select LFRCO as HFCORECLKUSBC.
4 CALSTOP 0 W1 Calibration Stop
Stops the calibration counters.
3 CALSTART 0 W1 Calibration Start
Starts the calibration, effectively loading the CMU_CALCNT into the down-counter and start decrementing.
2:0 HFCLKSEL 0x0 W1 HFCLK Select
Selects the clock source for HFCLK. Note that selecting an oscillator that is disabled will cause the system clock to stop.
Check the status register and confirm that oscillator is ready before switching.
Value Mode Description
1 HFRCO Select HFRCO as HFCLK.
2 HFXO Select HFXO as HFCLK.
3 LFRCO Select LFRCO as HFCLK.
4 LFXO Select LFXO as HFCLK.
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11.5.11 CMU_LFCLKSEL - Low Frequency Clock Select Register
Offset Bit Position
0x028
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
16
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
Reset
0
0
0x1
0x1
Access
RW
RW
RW
RW
Name
LFBE
LFAE
LFB
LFA
Bit Name Reset Access Description
31:21 Reserved To ensure compatibility with future devices, always write bits to 0. More information in 2.1 Conven-
tions.
20 LFBE 0 RW Clock Select for LFB Extended
This bit redefines the meaning of the LFB field.
Value Mode Description
0 DISABLED LFBCLK is disabled (when LFB = DISABLED).
1 ULFRCO ULFRCO selected as LFBCLK (when LFB = DISABLED).
19:17 Reserved To ensure compatibility with future devices, always write bits to 0. More information in 2.1 Conven-
tions.
16 LFAE 0 RW Clock Select for LFA Extended
This bit redefines the meaning of the LFA field.
Value Mode Description
0 DISABLED LFACLK is disabled (when LFA = DISABLED).
1 ULFRCO ULFRCO selected as LFACLK (when LFA = DISABLED).
15:4 Reserved To ensure compatibility with future devices, always write bits to 0. More information in 2.1 Conven-
tions.
3:2 LFB 0x1 RW Clock Select for LFB
Selects the clock source for LFBCLK.
LFB LFBE Mode
0 0 Disabled
1 0 LFRCO
2 0 LFXO
3 0 HFCORECLKLEDIV2
0 1 ULFRCO
1:0 LFA 0x1 RW Clock Select for LFA
Selects the clock source for LFACLK.
LFA LFAE Mode
0 0 Disabled
1 0 LFRCO
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Bit Name Reset Access Description
2 0 LFXO
3 0 HFCORECLKLEDIV2
0 1 ULFRCO
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11.5.12 CMU_STATUS - Status Register
Offset Bit Position
0x02C
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
16
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
Reset
0
0
0
0
0
0
0
1
0
0
0
0
0
0
0
0
1
1
Access
R
R
R
R
R
R
R
R
R
R
R
R
R
R
R
R
R
R
Name
USBCLFRCOSEL
USBCLFXOSEL
USBCHFCLKSEL
CALBSY
LFXOSEL
LFRCOSEL
HFXOSEL
HFRCOSEL
LFXORDY
LFXOENS
LFRCORDY
LFRCOENS
AUXHFRCORDY
AUXHFRCOENS
HFXORDY
HFXOENS
HFRCORDY
HFRCOENS
Bit Name Reset Access Description
31:18 Reserved To ensure compatibility with future devices, always write bits to 0. More information in 2.1 Conven-
tions.
17 USBCLFRCOSEL 0 R USBC LFRCO Selected
LFRCO is selected (and active) as HFCORECLKUSBC.
16 USBCLFXOSEL 0 R USBC LFXO Selected
LFXO is selected (and active) as HFCORECLKUSBC.
15 USBCHFCLKSEL 0 R USBC HFCLK Selected
HFCLK is selected (and active) as HFCORECLKUSBC.
14 CALBSY 0 R Calibration Busy
Calibration is on-going.
13 LFXOSEL 0 R LFXO Selected
LFXO is selected as HFCLK clock source.
12 LFRCOSEL 0 R LFRCO Selected
LFRCO is selected as HFCLK clock source.
11 HFXOSEL 0 R HFXO Selected
HFXO is selected as HFCLK clock source.
10 HFRCOSEL 1 R HFRCO Selected
HFRCO is selected as HFCLK clock source.
9 LFXORDY 0 R LFXO Ready
LFXO is enabled and start-up time has exceeded.
8 LFXOENS 0 R LFXO Enable Status
LFXO is enabled.
7 LFRCORDY 0 R LFRCO Ready
LFRCO is enabled and start-up time has exceeded.
6 LFRCOENS 0 R LFRCO Enable Status
LFRCO is enabled.
5 AUXHFRCORDY 0 R AUXHFRCO Ready
AUXHFRCO is enabled and start-up time has exceeded.
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Bit Name Reset Access Description
4 AUXHFRCOENS 0 R AUXHFRCO Enable Status
AUXHFRCO is enabled.
3 HFXORDY 0 R HFXO Ready
HFXO is enabled and start-up time has exceeded.
2 HFXOENS 0 R HFXO Enable Status
HFXO is enabled.
1 HFRCORDY 1 R HFRCO Ready
HFRCO is enabled and start-up time has exceeded.
0 HFRCOENS 1 R HFRCO Enable Status
HFRCO is enabled.
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11.5.13 CMU_IF - Interrupt Flag Register
Offset Bit Position
0x030
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
16
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
Reset
0
0
0
0
0
0
0
1
Access
R
R
R
R
R
R
R
R
Name
USBCHFCLKSEL
CALOF
CALRDY
AUXHFRCORDY
LFXORDY
LFRCORDY
HFXORDY
HFRCORDY
Bit Name Reset Access Description
31:8 Reserved To ensure compatibility with future devices, always write bits to 0. More information in 2.1 Conven-
tions.
7 USBCHFCLKSEL 0 R USBC HFCLK Selected Interrupt Flag
Set when HFCLK is selected as HFCORECLKUSBC.
6 CALOF 0 R Calibration Overflow Interrupt Flag
Set when calibration overflow has occurred
5 CALRDY 0 R Calibration Ready Interrupt Flag
Set when calibration is completed.
4 AUXHFRCORDY 0 R AUXHFRCO Ready Interrupt Flag
Set when AUXHFRCO is ready (start-up time exceeded).
3 LFXORDY 0 R LFXO Ready Interrupt Flag
Set when LFXO is ready (start-up time exceeded).
2 LFRCORDY 0 R LFRCO Ready Interrupt Flag
Set when LFRCO is ready (start-up time exceeded).
1 HFXORDY 0 R HFXO Ready Interrupt Flag
Set when HFXO is ready (start-up time exceeded).
0 HFRCORDY 1 R HFRCO Ready Interrupt Flag
Set when HFRCO is ready (start-up time exceeded).
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11.5.14 CMU_IFS - Interrupt Flag Set Register
Offset Bit Position
0x034
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
16
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
Reset
0
0
0
0
0
0
0
0
Access
W1
W1
W1
W1
W1
W1
W1
W1
Name
USBCHFCLKSEL
CALOF
CALRDY
AUXHFRCORDY
LFXORDY
LFRCORDY
HFXORDY
HFRCORDY
Bit Name Reset Access Description
31:8 Reserved To ensure compatibility with future devices, always write bits to 0. More information in 2.1 Conven-
tions.
7 USBCHFCLKSEL 0 W1 USBC HFCLK Selected Interrupt Flag Set
Write to 1 to set the USBC HFCLK Selected Interrupt Flag.
6 CALOF 0 W1 Calibration Overflow Interrupt Flag Set
Write to 1 to set the Calibration Overflow Interrupt Flag.
5 CALRDY 0 W1 Calibration Ready Interrupt Flag Set
Write to 1 to set the Calibration Ready(completed) Interrupt Flag.
4 AUXHFRCORDY 0 W1 AUXHFRCO Ready Interrupt Flag Set
Write to 1 to set the AUXHFRCO Ready Interrupt Flag.
3 LFXORDY 0 W1 LFXO Ready Interrupt Flag Set
Write to 1 to set the LFXO Ready Interrupt Flag.
2 LFRCORDY 0 W1 LFRCO Ready Interrupt Flag Set
Write to 1 to set the LFRCO Ready Interrupt Flag.
1 HFXORDY 0 W1 HFXO Ready Interrupt Flag Set
Write to 1 to set the HFXO Ready Interrupt Flag.
0 HFRCORDY 0 W1 HFRCO Ready Interrupt Flag Set
Write to 1 to set the HFRCO Ready Interrupt Flag.
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11.5.15 CMU_IFC - Interrupt Flag Clear Register
Offset Bit Position
0x038
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
16
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
Reset
0
0
0
0
0
0
0
0
Access
(R)W1
(R)W1
(R)W1
(R)W1
(R)W1
(R)W1
(R)W1
(R)W1
Name
USBCHFCLKSEL
CALOF
CALRDY
AUXHFRCORDY
LFXORDY
LFRCORDY
HFXORDY
HFRCORDY
Bit Name Reset Access Description
31:8 Reserved To ensure compatibility with future devices, always write bits to 0. More information in 2.1 Conven-
tions.
7 USBCHFCLKSEL 0 (R)W1 USBC HFCLK Selected Interrupt Flag Clear
Write to 1 to clear the USBC HFCLK Selected Interrupt Flag.
6 CALOF 0 (R)W1 Calibration Overflow Interrupt Flag Clear
Write to 1 to clear the Calibration Overflow Interrupt Flag.
5 CALRDY 0 (R)W1 Calibration Ready Interrupt Flag Clear
Write to 1 to clear the Calibration Ready Interrupt Flag.
4 AUXHFRCORDY 0 (R)W1 AUXHFRCO Ready Interrupt Flag Clear
Write to 1 to clear the AUXHFRCO Ready Interrupt Flag.
3 LFXORDY 0 (R)W1 LFXO Ready Interrupt Flag Clear
Write to 1 to clear the LFXO Ready Interrupt Flag.
2 LFRCORDY 0 (R)W1 LFRCO Ready Interrupt Flag Clear
Write to 1 to clear the LFRCO Ready Interrupt Flag.
1 HFXORDY 0 (R)W1 HFXO Ready Interrupt Flag Clear
Write to 1 to clear the HFXO Ready Interrupt Flag.
0 HFRCORDY 0 (R)W1 HFRCO Ready Interrupt Flag Clear
Write to 1 to clear the HFRCO Ready Interrupt Flag.
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11.5.16 CMU_IEN - Interrupt Enable Register
Offset Bit Position
0x03C
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
16
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
Reset
0
0
0
0
0
0
0
0
Access
RW
RW
RW
RW
RW
RW
RW
RW
Name
USBCHFCLKSEL
CALOF
CALRDY
AUXHFRCORDY
LFXORDY
LFRCORDY
HFXORDY
HFRCORDY
Bit Name Reset Access Description
31:8 Reserved To ensure compatibility with future devices, always write bits to 0. More information in 2.1 Conven-
tions.
7 USBCHFCLKSEL 0 RW USBC HFCLK Selected Interrupt Enable
Set to enable the USBC HFCLK Selected Interrupt.
6 CALOF 0 RW Calibration Overflow Interrupt Enable
Set to enable the Calibration Overflow Interrupt.
5 CALRDY 0 RW Calibration Ready Interrupt Enable
Set to enable the Calibration Ready Interrupt.
4 AUXHFRCORDY 0 RW AUXHFRCO Ready Interrupt Enable
Set to enable the AUXHFRCO Ready Interrupt.
3 LFXORDY 0 RW LFXO Ready Interrupt Enable
Set to enable the LFXO Ready Interrupt.
2 LFRCORDY 0 RW LFRCO Ready Interrupt Enable
Set to enable the LFRCO Ready Interrupt.
1 HFXORDY 0 RW HFXO Ready Interrupt Enable
Set to enable the HFXO Ready Interrupt.
0 HFRCORDY 0 RW HFRCO Ready Interrupt Enable
Set to enable the HFRCO Ready Interrupt.
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11.5.17 CMU_HFCORECLKEN0 - High Frequency Core Clock Enable Register 0
Offset Bit Position
0x040
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
16
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
Reset
0
0
0
0
0
0
Access
RW
RW
RW
RW
RW
RW
Name
EBI
LE
USB
USBC
AES
DMA
Bit Name Reset Access Description
31:6 Reserved To ensure compatibility with future devices, always write bits to 0. More information in 2.1 Conven-
tions.
5 EBI 0 RW External Bus Interface Clock Enable
Set to enable the clock for EBI.
4 LE 0 RW Low Energy Peripheral Interface Clock Enable
Set to enable the clock for LE. Interface used for bus access to Low Energy peripherals.
3 USB 0 RW Universal Serial Bus Interface Clock Enable
Set to enable the clock for USB.
2 USBC 0 RW Universal Serial Bus Interface Core Clock Enable
Set to enable the clock for USBC.
1 AES 0 RW Advanced Encryption Standard Accelerator Clock Enable
Set to enable the clock for AES.
0 DMA 0 RW Direct Memory Access Controller Clock Enable
Set to enable the clock for DMA.
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11.5.18 CMU_HFPERCLKEN0 - High Frequency Peripheral Clock Enable Register 0
Offset Bit Position
0x044
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
16
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
Reset
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
Access
RW
RW
RW
RW
RW
RW
RW
RW
RW
RW
RW
RW
RW
RW
RW
RW
RW
RW
Name
DAC0
ADC0
PRS
VCMP
GPIO
I2C1
I2C0
ACMP1
ACMP0
TIMER3
TIMER2
TIMER1
TIMER0
UART1
UART0
USART2
USART1
USART0
Bit Name Reset Access Description
31:18 Reserved To ensure compatibility with future devices, always write bits to 0. More information in 2.1 Conven-
tions.
17 DAC0 0 RW Digital to Analog Converter 0 Clock Enable
Set to enable the clock for DAC0.
16 ADC0 0 RW Analog to Digital Converter 0 Clock Enable
Set to enable the clock for ADC0.
15 PRS 0 RW Peripheral Reflex System Clock Enable
Set to enable the clock for PRS.
14 VCMP 0 RW Voltage Comparator Clock Enable
Set to enable the clock for VCMP.
13 GPIO 0 RW General purpose Input/Output Clock Enable
Set to enable the clock for GPIO.
12 I2C1 0 RW I2C 1 Clock Enable
Set to enable the clock for I2C1.
11 I2C0 0 RW I2C 0 Clock Enable
Set to enable the clock for I2C0.
10 ACMP1 0 RW Analog Comparator 1 Clock Enable
Set to enable the clock for ACMP1.
9 ACMP0 0 RW Analog Comparator 0 Clock Enable
Set to enable the clock for ACMP0.
8 TIMER3 0 RW Timer 3 Clock Enable
Set to enable the clock for TIMER3.
7 TIMER2 0 RW Timer 2 Clock Enable
Set to enable the clock for TIMER2.
6 TIMER1 0 RW Timer 1 Clock Enable
Set to enable the clock for TIMER1.
5 TIMER0 0 RW Timer 0 Clock Enable
Set to enable the clock for TIMER0.
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Bit Name Reset Access Description
4 UART1 0 RW Universal Asynchronous Receiver/Transmitter 1 Clock Enable
Set to enable the clock for UART1.
3 UART0 0 RW Universal Asynchronous Receiver/Transmitter 0 Clock Enable
Set to enable the clock for UART0.
2 USART2 0 RW Universal Synchronous/Asynchronous Receiver/Transmitter 2
Clock Enable
Set to enable the clock for USART2.
1 USART1 0 RW Universal Synchronous/Asynchronous Receiver/Transmitter 1
Clock Enable
Set to enable the clock for USART1.
0 USART0 0 RW Universal Synchronous/Asynchronous Receiver/Transmitter 0
Clock Enable
Set to enable the clock for USART0.
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11.5.19 CMU_SYNCBUSY - Synchronization Busy Register
Offset Bit Position
0x050
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
16
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
Reset
0
0
0
0
Access
R
R
R
R
Name
LFBPRESC0
LFBCLKEN0
LFAPRESC0
LFACLKEN0
Bit Name Reset Access Description
31:7 Reserved To ensure compatibility with future devices, always write bits to 0. More information in 2.1 Conven-
tions.
6 LFBPRESC0 0 R Low Frequency B Prescaler 0 Busy
Used to check the synchronization status of CMU_LFBPRESC0.
Value Description
1 CMU_LFBPRESC0 is busy synchronizing new value.
5 Reserved To ensure compatibility with future devices, always write bits to 0. More information in 2.1 Conven-
tions.
4 LFBCLKEN0 0 R Low Frequency B Clock Enable 0 Busy
Used to check the synchronization status of CMU_LFBCLKEN0.
Value Description
0 CMU_LFBCLKEN0 is ready for update.
1 CMU_LFBCLKEN0 is busy synchronizing new value.
3 Reserved To ensure compatibility with future devices, always write bits to 0. More information in 2.1 Conven-
tions.
2 LFAPRESC0 0 R Low Frequency A Prescaler 0 Busy
Used to check the synchronization status of CMU_LFAPRESC0.
Value Description
0 CMU_LFAPRESC0 is ready for update.
1 CMU_LFAPRESC0 is busy synchronizing new value.
1 Reserved To ensure compatibility with future devices, always write bits to 0. More information in 2.1 Conven-
tions.
0 LFACLKEN0 0 R Low Frequency A Clock Enable 0 Busy
Used to check the synchronization status of CMU_LFACLKEN0.
Value Description
0 CMU_LFACLKEN0 is ready for update.
1 CMU_LFACLKEN0 is busy synchronizing new value.
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11.5.20 CMU_FREEZE - Freeze Register
Offset Bit Position
0x054
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
16
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
Reset
0
Access
RW
Name
REGFREEZE
Bit Name Reset Access Description
31:1 Reserved To ensure compatibility with future devices, always write bits to 0. More information in 2.1 Conven-
tions.
0 REGFREEZE 0 RW Register Update Freeze
When set, the update of the Low Frequency clock control registers is postponed until this bit is cleared. Use this bit to up-
date several registers simultaneously.
Value Mode Description
0 UPDATE Each write access to a Low Frequency clock control register is updated
into the Low Frequency domain as soon as possible.
1 FREEZE The LE Clock Control registers are not updated with the new written
value.
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11.5.21 CMU_LFACLKEN0 - Low Frequency A Clock Enable Register 0 (Async Reg)
Offset Bit Position
0x058
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
16
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
Reset
0
0
0
0
Access
RW
RW
RW
RW
Name
LCD
LETIMER0
RTC
LESENSE
Bit Name Reset Access Description
31:4 Reserved To ensure compatibility with future devices, always write bits to 0. More information in 2.1 Conven-
tions.
3 LCD 0 RW Liquid Crystal Display Controller Clock Enable
Set to enable the clock for LCD.
2 LETIMER0 0 RW Low Energy Timer 0 Clock Enable
Set to enable the clock for LETIMER0.
1 RTC 0 RW Real-Time Counter Clock Enable
Set to enable the clock for RTC.
0 LESENSE 0 RW Low Energy Sensor Interface Clock Enable
Set to enable the clock for LESENSE.
11.5.22 CMU_LFBCLKEN0 - Low Frequency B Clock Enable Register 0 (Async Reg)
Offset Bit Position
0x060
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
16
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
Reset
0
0
Access
RW
RW
Name
LEUART1
LEUART0
Bit Name Reset Access Description
31:2 Reserved To ensure compatibility with future devices, always write bits to 0. More information in 2.1 Conven-
tions.
1 LEUART1 0 RW Low Energy UART 1 Clock Enable
Set to enable the clock for LEUART1.
0 LEUART0 0 RW Low Energy UART 0 Clock Enable
Set to enable the clock for LEUART0.
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11.5.23 CMU_LFAPRESC0 - Low Frequency A Prescaler Register 0 (Async Reg)
Offset Bit Position
0x068
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
16
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
Reset
0x0
0x0
0x0
0x0
Access
RW
RW
RW
RW
Name
LCD
LETIMER0
RTC
LESENSE
Bit Name Reset Access Description
31:14 Reserved To ensure compatibility with future devices, always write bits to 0. More information in 2.1 Conven-
tions.
13:12 LCD 0x0 RW Liquid Crystal Display Controller Prescaler
Configure Liquid Crystal Display Controller prescaler
Value Mode Description
0 DIV16 LFACLKLCD = LFACLK/16
1 DIV32 LFACLKLCD = LFACLK/32
2 DIV64 LFACLKLCD = LFACLK/64
3 DIV128 LFACLKLCD = LFACLK/128
11:8 LETIMER0 0x0 RW Low Energy Timer 0 Prescaler
Configure Low Energy Timer 0 prescaler
Value Mode Description
0 DIV1 LFACLKLETIMER0 = LFACLK
1 DIV2 LFACLKLETIMER0 = LFACLK/2
2 DIV4 LFACLKLETIMER0 = LFACLK/4
3 DIV8 LFACLKLETIMER0 = LFACLK/8
4 DIV16 LFACLKLETIMER0 = LFACLK/16
5 DIV32 LFACLKLETIMER0 = LFACLK/32
6 DIV64 LFACLKLETIMER0 = LFACLK/64
7 DIV128 LFACLKLETIMER0 = LFACLK/128
8 DIV256 LFACLKLETIMER0 = LFACLK/256
9 DIV512 LFACLKLETIMER0 = LFACLK/512
10 DIV1024 LFACLKLETIMER0 = LFACLK/1024
11 DIV2048 LFACLKLETIMER0 = LFACLK/2048
12 DIV4096 LFACLKLETIMER0 = LFACLK/4096
13 DIV8192 LFACLKLETIMER0 = LFACLK/8192
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Bit Name Reset Access Description
14 DIV16384 LFACLKLETIMER0 = LFACLK/16384
15 DIV32768 LFACLKLETIMER0 = LFACLK/32768
7:4 RTC 0x0 RW Real-Time Counter Prescaler
Configure Real-Time Counter prescaler
Value Mode Description
0 DIV1 LFACLKRTC = LFACLK
1 DIV2 LFACLKRTC = LFACLK/2
2 DIV4 LFACLKRTC = LFACLK/4
3 DIV8 LFACLKRTC = LFACLK/8
4 DIV16 LFACLKRTC = LFACLK/16
5 DIV32 LFACLKRTC = LFACLK/32
6 DIV64 LFACLKRTC = LFACLK/64
7 DIV128 LFACLKRTC = LFACLK/128
8 DIV256 LFACLKRTC = LFACLK/256
9 DIV512 LFACLKRTC = LFACLK/512
10 DIV1024 LFACLKRTC = LFACLK/1024
11 DIV2048 LFACLKRTC = LFACLK/2048
12 DIV4096 LFACLKRTC = LFACLK/4096
13 DIV8192 LFACLKRTC = LFACLK/8192
14 DIV16384 LFACLKRTC = LFACLK/16384
15 DIV32768 LFACLKRTC = LFACLK/32768
3:2 Reserved To ensure compatibility with future devices, always write bits to 0. More information in 2.1 Conven-
tions.
1:0 LESENSE 0x0 RW Low Energy Sensor Interface Prescaler
Configure Low Energy Sensor Interface prescaler
Value Mode Description
0 DIV1 LFACLKLESENSE = LFACLK
1 DIV2 LFACLKLESENSE = LFACLK/2
2 DIV4 LFACLKLESENSE = LFACLK/4
3 DIV8 LFACLKLESENSE = LFACLK/8
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11.5.24 CMU_LFBPRESC0 - Low Frequency B Prescaler Register 0 (Async Reg)
Offset Bit Position
0x070
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
16
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
Reset
0x0
0x0
Access
RW
RW
Name
LEUART1
LEUART0
Bit Name Reset Access Description
31:6 Reserved To ensure compatibility with future devices, always write bits to 0. More information in 2.1 Conven-
tions.
5:4 LEUART1 0x0 RW Low Energy UART 1 Prescaler
Configure Low Energy UART 1 prescaler
Value Mode Description
0 DIV1 LFBCLKLEUART1 = LFBCLK
1 DIV2 LFBCLKLEUART1 = LFBCLK/2
2 DIV4 LFBCLKLEUART1 = LFBCLK/4
3 DIV8 LFBCLKLEUART1 = LFBCLK/8
3:2 Reserved To ensure compatibility with future devices, always write bits to 0. More information in 2.1 Conven-
tions.
1:0 LEUART0 0x0 RW Low Energy UART 0 Prescaler
Configure Low Energy UART 0 prescaler
Value Mode Description
0 DIV1 LFBCLKLEUART0 = LFBCLK
1 DIV2 LFBCLKLEUART0 = LFBCLK/2
2 DIV4 LFBCLKLEUART0 = LFBCLK/4
3 DIV8 LFBCLKLEUART0 = LFBCLK/8
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11.5.25 CMU_PCNTCTRL - PCNT Control Register
Offset Bit Position
0x078
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
16
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
Reset
0
0
0
0
0
0
Access
RW
RW
RW
RW
RW
RW
Name
PCNT2CLKSEL
PCNT2CLKEN
PCNT1CLKSEL
PCNT1CLKEN
PCNT0CLKSEL
PCNT0CLKEN
Bit Name Reset Access Description
31:6 Reserved To ensure compatibility with future devices, always write bits to 0. More information in 2.1 Conven-
tions.
5 PCNT2CLKSEL 0 RW PCNT2 Clock Select
This bit controls which clock that is used for the PCNT.
Value Mode Description
0 LFACLK LFACLK is clocking PCNT2.
1 PCNT2S0 External pin PCNT2_S0 is clocking PCNT0.
4 PCNT2CLKEN 0 RW PCNT2 Clock Enable
This bit enables/disables the clock to the PCNT.
Value Description
0 PCNT2 is disabled.
1 PCNT2 is enabled.
3 PCNT1CLKSEL 0 RW PCNT1 Clock Select
This bit controls which clock that is used for the PCNT.
Value Mode Description
0 LFACLK LFACLK is clocking PCNT0.
1 PCNT1S0 External pin PCNT1_S0 is clocking PCNT0.
2 PCNT1CLKEN 0 RW PCNT1 Clock Enable
This bit enables/disables the clock to the PCNT.
Value Description
0 PCNT1 is disabled.
1 PCNT1 is enabled.
1 PCNT0CLKSEL 0 RW PCNT0 Clock Select
This bit controls which clock that is used for the PCNT.
Value Mode Description
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Bit Name Reset Access Description
0 LFACLK LFACLK is clocking PCNT0.
1 PCNT0S0 External pin PCNT0_S0 is clocking PCNT0.
0 PCNT0CLKEN 0 RW PCNT0 Clock Enable
This bit enables/disables the clock to the PCNT.
Value Description
0 PCNT0 is disabled.
1 PCNT0 is enabled.
11.5.26 CMU_LCDCTRL - LCD Control Register
Offset Bit Position
0x07C
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
16
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
Reset
0x2
0
0x0
Access
RW
RW
RW
Name
VBFDIV
VBOOSTEN
FDIV
Bit Name Reset Access Description
31:7 Reserved To ensure compatibility with future devices, always write bits to 0. More information in 2.1 Conven-
tions.
6:4 VBFDIV 0x2 RW Voltage Boost Frequency Division
These bits control the voltage boost update frequency division.
Value Mode Description
0 DIV1 Voltage Boost update Frequency = LFACLK.
1 DIV2 Voltage Boost update Frequency = LFACLK/2.
2 DIV4 Voltage Boost update Frequency = LFACLK/4.
3 DIV8 Voltage Boost update Frequency = LFACLK/8.
4 DIV16 Voltage Boost update Frequency = LFACLK/16.
5 DIV32 Voltage Boost update Frequency = LFACLK/32.
6 DIV64 Voltage Boost update Frequency = LFACLK/64.
7 DIV128 Voltage Boost update Frequency = LFACLK/128.
3 VBOOSTEN 0 RW Voltage Boost Enable
This bit enables/disables the VBOOST function.
2:0 FDIV 0x0 RW Frame Rate Control
These bits controls the framerate according to this formula: LFACLKLCD = LFACLKLCDpre / (1 + FDIV). Do not change this
value while the LCD bit in CMU_LFACLKEN0 is set to 1.
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11.5.27 CMU_ROUTE - I/O Routing Register
Offset Bit Position
0x080
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
16
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
Reset
0x0
0
0
Access
RW
RW
RW
Name
LOCATION
CLKOUT1PEN
CLKOUT0PEN
Bit Name Reset Access Description
31:5 Reserved To ensure compatibility with future devices, always write bits to 0. More information in 2.1 Conven-
tions.
4:2 LOCATION 0x0 RW I/O Location
Decides the location of the CMU I/O pins.
Value Mode Description
0 LOC0 Location 0
1 LOC1 Location 1
2 LOC2 Location 2
1 CLKOUT1PEN 0 RW CLKOUT1 Pin Enable
When set, the CLKOUT1 pin is enabled.
0 CLKOUT0PEN 0 RW CLKOUT0 Pin Enable
When set, the CLKOUT0 pin is enabled.
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11.5.28 CMU_LOCK - Configuration Lock Register
Offset Bit Position
0x084
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
16
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
Reset
0x0000
Access
RW
Name
LOCKKEY
Bit Name Reset Access Description
31:16 Reserved To ensure compatibility with future devices, always write bits to 0. More information in 2.1 Conven-
tions.
15:0 LOCKKEY 0x0000 RW Configuration Lock Key
Write any other value than the unlock code to lock CMU_CTRL, CMU_HFCORECLKDIV, CMU_HFPERCLKDIV,
CMU_HFRCOCTRL, CMU_LFRCOCTRL, CMU_AUXHFRCOCTRL, CMU_OSCENCMD, CMU_CMD, CMU_LFCLKSEL,
CMU_HFCORECLKEN0, CMU_HFPERCLKEN0, CMU_LFACLKEN0, CMU_LFBCLKEN0, CMU_LFAPRESC0,
CMU_LFBPRESC0, and CMU_PCNTCTRL from editing. Write the unlock code to unlock. When reading the register, bit 0
is set when the lock is enabled.
Mode Value Description
Read Operation
UNLOCKED 0 CMU registers are unlocked.
LOCKED 1 CMU registers are locked.
Write Operation
LOCK 0 Lock CMU registers.
UNLOCK 0x580E Unlock CMU registers.
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mm
wmcmag chm
,rm
12. WDOG - Watchdog Timer
43210
Timeout period
Counter value
Time
Watchdog clear System reset
Quick Facts
What?
The WDOG (Watchdog Timer) resets the system in
case of a fault condition, and can be enabled in all
energy modes as long as the low frequency clock
source is available.
Why?
If a software failure or external event renders the
MCU unresponsive, a Watchdog timeout will reset
the system to a known, safe state.
How?
An enabled Watchdog Timer implements a configu-
rable timeout period. If the CPU fails to re-start the
Watchdog Timer before it times out, a full system re-
set will be triggered. The Watchdog consumes insig-
nificant power, and allows the device to remain safe-
ly in low energy modes for up to 256 seconds at a
time.
12.1 Introduction
The purpose of the watchdog timer is to generate a reset in case of a system failure, to increase application reliability. The failure may
e.g. be caused by an external event, such as an ESD pulse, or by a software failure.
12.2 Features
• Clock input from selectable oscillators
• Internal 32.768 kHz RC oscillator
• Internal 1 kHz RC oscillator
• External 32.768 kHz XTAL oscillator
• Configurable timeout period from 9 to 256k watchdog clock cycles
• Individual selection to keep running or freeze when entering EM2 or EM3
• Selection to keep running or freeze when entering debug mode
• Selection to block the CPU from entering Energy Mode 4
• Selection to block the CMU from disabling the selected watchdog clock
12.3 Functional Description
The watchdog is enabled by setting the EN bit in WDOG_CTRL. When enabled, the watchdog counts up to the period value configured
through the PERSEL field in WDOG_CTRL. If the watchdog timer is not cleared to 0 (by writing a 1 to the CLEAR bit in WDOG_CMD)
before the period is reached, the chip is reset. If a timely clear command is issued, the timer starts counting up from 0 again. The
watchdog can optionally be locked by writing the LOCK bit in WDOG_CTRL. Once locked, it cannot be disabled or reconfigured by
software.
The watchdog counter is reset when EN is reset.
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12.3.1 Clock Source
Three clock sources are available for use with the watchdog, through the CLKSEL field in WDOG_CTRL. The corresponding clocks
must be enabled in the CMU. The SWOSCBLOCK bit in WDOG_CTRL can be written to prevent accidental disabling of the selected
clocks. Also, setting this bit will automatically start the selected oscillator source when the watchdog is enabled. The PERSEL field in
WDOG_CTRL is used to divide the selected watchdog clock, and the timeout for the watchdog timer can be calculated like this:
TTIMEOUT =23+PERSEL + 1
f
where f is the frequency of the selected clock.
It is recommended to clear the watchdog first if PERSEL is changed while the watchdog is enabled.
To use this module, the LE interface clock must be enabled in CMU_HFCORECLKEN0, in addition to the module clock.
12.3.2 Debug Functionality
The watchdog timer can either keep running or be frozen when the device is halted by a debugger. This configuration is done through
the DEBUGRUN bit in WDOG_CTRL. When code execution is resumed, the watchdog will continue counting where it left off.
12.3.3 Energy Mode Handling
The watchdog timer can be configured to either keep on running or freeze when entering EM2 or EM3. The configuration is done indi-
vidually for each energy mode in the EM2RUN and EM3RUN bits in WDOG_CTRL. When the watchdog has been frozen and is re-
entering an energy mode where it is running, the watchdog timer will continue counting where it left off. For the watchdog there is no
difference between EM0 and EM1. The watchdog does not run in EM4, and if EM4BLOCK in WDOG_CTRL is set, the CPU is preven-
ted from entering EM4.
Note: If the WDOG is clocked by the LFXO or LFRCO, writing the SWOSCBLOCK bit will effectively prevent the CPU from entering
EM3. When running from the ULFRCO, writing the SWOSCBLOCK bit will prevent the CPU from entering EM4.
12.3.4 Register Access
Since this module is a Low Energy Peripheral, and runs off a clock which is asynchronous to the HFCORECLK, special considerations
must be taken when accessing registers. Please refer to 5.2.4 Access to Low Energy Peripherals (Asynchronous Registers) for a de-
scription on how to perform register accesses to Low Energy Peripherals. note that clearing the EN bit in WDOG_CTRL will reset the
WDOG module, which will halt any ongoing register synchronization.
Note: Never write to the WDOG registers when it is disabled, except to enable it by setting the EN bitfield in WDOG_CTRL. Make sure
that the enable is registered (i.e. WDOG_SYNCBUSY_CTRL goes low), before writing other registers.
12.4 Register Map
The offset register address is relative to the registers base address.
Offset Name Type Description
0x000 WDOG_CTRL RW Control Register
0x004 WDOG_CMD W1 Command Register
0x008 WDOG_SYNCBUSY RSynchronization Busy Register
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12.5 Register Description
12.5.1 WDOG_CTRL - Control Register (Async Reg)
For more information about Asynchronous Registers, see 5.2.4 Access to Low Energy Peripherals (Asynchronous Registers).
Offset Bit Position
0x000
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
16
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
Reset
0x0
0xF
0
0
0
0
0
0
0
Access
RW
RW
RW
RW
RW
RW
RW
RW
RW
Name
CLKSEL
PERSEL
SWOSCBLOCK
EM4BLOCK
LOCK
EM3RUN
EM2RUN
DEBUGRUN
EN
Bit Name Reset Access Description
31:14 Reserved To ensure compatibility with future devices, always write bits to 0. More information in 2.1 Conven-
tions.
13:12 CLKSEL 0x0 RW Watchdog Clock Select
Selects the WDOG oscillator, i.e. the clock on which the watchdog will run.
Value Mode Description
0 ULFRCO ULFRCO
1 LFRCO LFRCO
2 LFXO LFXO
11:8 PERSEL 0xF RW Watchdog Timeout Period Select
Select watchdog timeout period.
Value Description
0 Timeout period of 9
watchdog clock cycles.
1 Timeout period of 17
watchdog clock cycles.
2 Timeout period of 33
watchdog clock cycles.
3 Timeout period of 65
watchdog clock cycles.
4 Timeout period of 129
watchdog clock cycles.
5 Timeout period of 257
watchdog clock cycles.
6 Timeout period of 513
watchdog clock cycles.
7 Timeout period of 1k
watchdog clock cycles.
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Bit Name Reset Access Description
8 Timeout period of 2k
watchdog clock cycles.
9 Timeout period of 4k
watchdog clock cycles.
10 Timeout period of 8k
watchdog clock cycles.
11 Timeout period of 16k
watchdog clock cycles.
12 Timeout period of 32k
watchdog clock cycles.
13 Timeout period of 64k
watchdog clock cycles.
14 Timeout period of 128k
watchdog clock cycles.
15 Timeout period of 256k
watchdog clock cycles.
7 Reserved To ensure compatibility with future devices, always write bits to 0. More information in 2.1 Conven-
tions.
6 SWOSCBLOCK 0 RW Software Oscillator Disable Block
Set to disallow disabling of the selected WDOG oscillator. Writing this bit to 1 will turn on the selected WDOG oscillator if it
is not already running.
Value Description
0 Software is allowed to disable the selected WDOG oscillator. See CMU
for detailed description. Note that also CMU registers are lockable.
1 Software is not allowed to disable the selected WDOG oscillator.
5 EM4BLOCK 0 RW Energy Mode 4 Block
Set to prevent the EMU from entering EM4.
Value Description
0 EM4 can be entered. See EMU for detailed description.
1 EM4 cannot be entered.
4 LOCK 0 RW Configuration lock
Set to lock the watchdog configuration. This bit can only be cleared by reset.
Value Description
0 Watchdog configuration can be changed.
1 Watchdog configuration cannot be changed.
3 EM3RUN 0 RW Energy Mode 3 Run Enable
Set to keep watchdog running in EM3.
Value Description
0 Watchdog timer is frozen in EM3.
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Bit Name Reset Access Description
1 Watchdog timer is running in EM3.
2 EM2RUN 0 RW Energy Mode 2 Run Enable
Set to keep watchdog running in EM2.
Value Description
0 Watchdog timer is frozen in EM2.
1 Watchdog timer is running in EM2.
1 DEBUGRUN 0 RW Debug Mode Run Enable
Set to keep watchdog running in debug mode.
Value Description
0 Watchdog timer is frozen in debug mode.
1 Watchdog timer is running in debug mode.
0 EN 0 RW Watchdog Timer Enable
Set to enabled watchdog timer.
12.5.2 WDOG_CMD - Command Register (Async Reg)
For more information about Asynchronous Registers, see 5.2.4 Access to Low Energy Peripherals (Asynchronous Registers).
Offset Bit Position
0x004
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
16
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
Reset
0
Access
W1
Name
CLEAR
Bit Name Reset Access Description
31:1 Reserved To ensure compatibility with future devices, always write bits to 0. More information in 2.1 Conven-
tions.
0 CLEAR 0 W1 Watchdog Timer Clear
Clear watchdog timer. The bit must be written 4 watchdog cycles before the timeout.
Value Mode Description
0 UNCHANGED Watchdog timer is unchanged.
1 CLEARED Watchdog timer is cleared to 0.
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12.5.3 WDOG_SYNCBUSY - Synchronization Busy Register
Offset Bit Position
0x008
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
16
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
Reset
0
0
Access
R
R
Name
CMD
CTRL
Bit Name Reset Access Description
31:2 Reserved To ensure compatibility with future devices, always write bits to 0. More information in 2.1 Conven-
tions.
1 CMD 0 R CMD Register Busy
Set when the value written to CMD is being synchronized.
0 CTRL 0 R CTRL Register Busy
Set when the value written to CTRL is being synchronized.
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“fl @
13. PRS - Peripheral Reflex System
43210
Timer
ADC
DMA
PRS
Ch
PRS
Ch
Quick Facts
What?
The PRS (Peripheral Reflex System) allows configu-
rable, fast and autonomous communication between
the peripherals.
Why?
Events and signals from one peripheral can be used
as input signals or triggers by other peripherals and
ensure timing-critical operation and reduced soft-
ware overhead.
How?
Without CPU intervention the peripherals can send
reflex signals (both pulses and level) to each other in
single- or chained steps. The peripherals can be set
up to perform actions based on the incoming reflex
signals. This results in improved system perform-
ance and reduced energy consumption.
13.1 Introduction
The Peripheral Reflex System (PRS) system is a network which allows the different peripheral modules to communicate directly with
each other without involving the CPU. Peripheral modules which send out reflex signals are called producers. The PRS routes these
reflex signals to consumer peripherals which apply actions depending on the reflex signals received. The format for the reflex signals is
not given, but edge triggers and other functionality can be applied by the PRS.
13.2 Features
• 12 configurable interconnect channels
• Each channel can be connected to any producing peripheral
• Consumers can choose which channel to listen to
• Selectable edge detector (rising, falling and both edges)
• Software controlled channel output
• Configurable level
• Triggered pulses
13.3 Functional Description
An overview of the PRS module is shown in Figure 13.1 PRS Overview on page 227. The PRS contains 12 interconnect channels, and
each of these can select between all the output reflex signals offered by the producers. The consumers can then choose which PRS
channel to listen to and perform actions based on the reflex signals routed through that channel. The reflex signals can be both pulse
signals and level signals. Synchronous PRS pulses are one HFPERCLK cycle long, and can either be sent out by a producer (e.g.,
ADC conversion complete) or be generated from the edge detector in the PRS channel. Level signals can have an arbitrary waveform
(e.g., Timer PWM output).
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13.3.1 Asynchronous Mode
Many reflex signals can operate in two modes, synchronous or asynchronous. A synchronous reflex is clocked on HFPERCLK, and can
be used as an input to all reflex consumers, but since they require HFPERCLK, they will not work in EM2/EM3.
Asynchronous reflexes are not clocked on HFPERCLK, and can be used even in EM2/EM3. There is a limitation to reflexes operating in
asynchronous mode though: they can only be used by a subset of the reflex consumers, the ones marked with async support in Table
13.2 Reflex Consumers on page 230. Peripherals that can produce asynchronous reflexes are marked with async support in Table
13.1 Reflex Producers on page 228. To use these reflexes asynchronously, set ASYNC in the CHCTRL register for the PRS channel
selecting the reflex signal.
Note: If a peripheral channel with ASYNC set is used in a consumer not supporting asynchronous reflexes, the behaviour is undefined.
13.3.2 Channel Functions
Different functions can be applied to a reflex signal within the PRS. Each channel includes an edge detector to enable generation of
pulse signals from level signals. It is also possible to generate output reflex signals by configuring the SWPULSE and SWLEVEL bits.
SWLEVEL is a programmable level for each channel and holds the value it is programmed to. The SWPULSE will give out a one-cycle
high pulse if it is written to 1, otherwise a 0 is asserted. The SWLEVEL and SWPULSE signals are then XOR'ed with the selected input
from the producers to form the output signal sent to the consumers listening to the channel.
Note: The edge detector controlled by EDSEL should only be used when working with synchronous reflexes, i.e., ASYNC in CHCTRL
is cleared.
APB Interface
Reg
SIGSEL[2:0]
APB bus
Signals from
producer
peripherals
Signals to
consumer
peripherals
EDSEL[1:0]
SWPULSE[n]
SOURCESEL[5:0]
SWLEVEL[n]
Figure 13.1. PRS Overview
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13.3.3 Producers
Each PRS channel can choose between signals from several producers, which is configured in SOURCESEL in PRS_CHx_CTRL.
Each of these producers outputs one or more signals which can be selected by setting the SIGSEL field in PRS_CHx_CTRL. Setting
the SOURCESEL bits to 0 (Off) leads to a constant 0 output from the input mux. An overview of the available producers is given in the
following table.
Table 13.1. Reflex Producers
Module Reflex Output Output Format Async Support
ACMP Comparator Output Level Yes
ADC Single Conversion Done Pulse —
Scan Conversion Done Pulse —
DAC Channel 0 Conversion Done Pulse —
Channel 1 Conversion Done Pulse —
GPIO Pin 0 Input Level Yes
Pin 1 Input Level Yes
Pin 2 Input Level Yes
Pin 3 Input Level Yes
Pin 4 Input Level Yes
Pin 5 Input Level Yes
Pin 6 Input Level Yes
Pin 7 Input Level Yes
Pin 8 Input Level Yes
Pin 9 Input Level Yes
Pin 10 Input Level Yes
Pin 11 Input Level Yes
Pin 12 Input Level Yes
Pin 13 Input Level Yes
Pin 14 Input Level Yes
Pin 15 Input Level Yes
RTC Overflow Pulse Yes
Compare Match 0 Pulse Yes
Compare Match 1 Pulse Yes
TIMER Underflow Pulse —
Overflow Pulse —
CC0 Output Level —
CC1 Output Level —
CC2 Output Level —
LETIMER CH0 Level Yes
CH1 Level Yes
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Module Reflex Output Output Format Async Support
UART TX Complete Pulse —
RX Data Received Pulse —
USART TX Complete Pulse —
RX Data Received Pulse —
IrDA Decoder Output Level —
VCMP Comparator Output Level Yes
LESENSE SCANRES register Level Yes
Decoder Output Level/Pulse Yes
BURTC Overflow Pulse Yes
Compare match 0 Pulse Yes
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13.3.4 Consumers
Consumer peripherals (listed in the following table) can be set to listen to a PRS channel and perform an action based on the signal
received on that channel. Most consumers expect pulse input, while some can handle level inputs as well.
Table 13.2. Reflex Consumers
Module Reflex Input Input Format Async Support
ADC Single Mode Trigger Pulse —
Scan Mode Trigger Pulse —
DAC Channel 0 Trigger Pulse —
Channel 1 Trigger Pulse —
TIMER CC0 Input Pulse/Level —
CC1 Input Pulse/Level —
CC2 Input Pulse/Level —
DTI Fault Source 0 (TIMER0
only)
Pulse —
DTI Fault Source 1 (TIMER0
only)
Pulse —
DTI Input (TIMER0 only) Pulse/Level —
UART TX/RX Enable Pulse —
RX Input Pulse/Level Yes
USART TX/RX Enable Pulse —
IrDA Encoder Input (USART0
only)
Pulse —
RX Input Pulse/Level Yes
LEUART RX Input Pulse/Level Yes
PCNT S0 input Level Yes
S1 input Level Yes
LESENSE Start scan Pulse/Level Yes
Decoder Bit 0 Level Yes
Decoder Bit 1 Level Yes
Decoder Bit 2 Level Yes
Decoder Bit 3 Level Yes
Note: It is possible to output prs channel 0 - channel 3 onto the GPIO by setting CH0PEN, CH1PEN, CH2PEN, or CH3PEN in the
PRS_ROUTE register.
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13.3.5 Example
The example below (illustrated in the following figure) shows how to set up ADC0 to start single conversions every time TIMER0 over-
flows (one HFPERCLK cycle high pulse), using PRS channel 5:
• Set SOURCESEL in PRS_CH5_CTRL to 0b011100 to select TIMER0 as input to PRS channel 5.
• Set SIGSEL in PRS_CH5_CTRL to 0b001 to select the overflow signal (from TIMER0).
• Configure ADC0 with the desired conversion set-up.
• Set SINGLEPRSEN in ADC0_SINGLECTRL to 1 to enable single conversions to be started by a high PRS input signal.
• Set SINGLEPRSSEL in ADC0_SINGLECTRL to 0x5 to select PRS channel 5 as input to start the single conversion.
• Start TIMER0 with the desired TOP value, an overflow PRS signal is output automatically on overflow.
Note that the ADC results needs to be fetched either by the CPU or DMA.
PRS
TIMER0 ADC0
ch0
ch1
ch2
ch3
ch4
ch5
ch6
ch7
Start single conv.Overflow
Figure 13.2. TIMER0 Overflow Starting ADC0 Single Conversions Through PRS Channel 5
13.4 Register Map
The offset register address is relative to the registers base address.
Offset Name Type Description
0x000 PRS_SWPULSE W1 Software Pulse Register
0x004 PRS_SWLEVEL RW Software Level Register
0x008 PRS_ROUTE RW I/O Routing Register
0x010 PRS_CH0_CTRL RW Channel Control Register
... PRS_CHx_CTRL RW Channel Control Register
0x03C PRS_CH11_CTRL RW Channel Control Register
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13.5 Register Description
13.5.1 PRS_SWPULSE - Software Pulse Register
Offset Bit Position
0x000
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
16
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
Reset
0
0
0
0
0
0
0
0
0
0
0
0
Access
W1
W1
W1
W1
W1
W1
W1
W1
W1
W1
W1
W1
Name
CH11PULSE
CH10PULSE
CH9PULSE
CH8PULSE
CH7PULSE
CH6PULSE
CH5PULSE
CH4PULSE
CH3PULSE
CH2PULSE
CH1PULSE
CH0PULSE
Bit Name Reset Access Description
31:12 Reserved To ensure compatibility with future devices, always write bits to 0. More information in 2.1 Conven-
tions.
11 CH11PULSE 0 W1 Channel 11 Pulse Generation
See bit 0.
10 CH10PULSE 0 W1 Channel 10 Pulse Generation
See bit 0.
9 CH9PULSE 0 W1 Channel 9 Pulse Generation
See bit 0.
8 CH8PULSE 0 W1 Channel 8 Pulse Generation
See bit 0.
7 CH7PULSE 0 W1 Channel 7 Pulse Generation
See bit 0.
6 CH6PULSE 0 W1 Channel 6 Pulse Generation
See bit 0.
5 CH5PULSE 0 W1 Channel 5 Pulse Generation
See bit 0.
4 CH4PULSE 0 W1 Channel 4 Pulse Generation
See bit 0.
3 CH3PULSE 0 W1 Channel 3 Pulse Generation
See bit 0.
2 CH2PULSE 0 W1 Channel 2 Pulse Generation
See bit 0.
1 CH1PULSE 0 W1 Channel 1 Pulse Generation
See bit 0.
0 CH0PULSE 0 W1 Channel 0 Pulse Generation
Write to 1 to generate one HFPERCLK cycle high pulse. This pulse is XOR'ed with the corresponding bit in the SWLEVEL
register and the selected PRS input signal to generate the channel output.
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13.5.2 PRS_SWLEVEL - Software Level Register
Offset Bit Position
0x004
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
16
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
Reset
0
0
0
0
0
0
0
0
0
0
0
0
Access
RW
RW
RW
RW
RW
RW
RW
RW
RW
RW
RW
RW
Name
CH11LEVEL
CH10LEVEL
CH9LEVEL
CH8LEVEL
CH7LEVEL
CH6LEVEL
CH5LEVEL
CH4LEVEL
CH3LEVEL
CH2LEVEL
CH1LEVEL
CH0LEVEL
Bit Name Reset Access Description
31:12 Reserved To ensure compatibility with future devices, always write bits to 0. More information in 2.1 Conven-
tions.
11 CH11LEVEL 0 RW Channel 11 Software Level
See bit 0.
10 CH10LEVEL 0 RW Channel 10 Software Level
See bit 0.
9 CH9LEVEL 0 RW Channel 9 Software Level
See bit 0.
8 CH8LEVEL 0 RW Channel 8 Software Level
See bit 0.
7 CH7LEVEL 0 RW Channel 7 Software Level
See bit 0.
6 CH6LEVEL 0 RW Channel 6 Software Level
See bit 0.
5 CH5LEVEL 0 RW Channel 5 Software Level
See bit 0.
4 CH4LEVEL 0 RW Channel 4 Software Level
See bit 0.
3 CH3LEVEL 0 RW Channel 3 Software Level
See bit 0.
2 CH2LEVEL 0 RW Channel 2 Software Level
See bit 0.
1 CH1LEVEL 0 RW Channel 1 Software Level
See bit 0.
0 CH0LEVEL 0 RW Channel 0 Software Level
The value in this register is XOR'ed with the corresponding bit in the SWPULSE register and the selected PRS input signal
to generate the channel output.
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13.5.3 PRS_ROUTE - I/O Routing Register
Offset Bit Position
0x008
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
16
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
Reset
0x0
0
0
0
0
Access
RW
RW
RW
RW
RW
Name
LOCATION
CH3PEN
CH2PEN
CH1PEN
CH0PEN
Bit Name Reset Access Description
31:11 Reserved To ensure compatibility with future devices, always write bits to 0. More information in 2.1 Conven-
tions.
10:8 LOCATION 0x0 RW I/O Location
Decides the location of the PRS I/O pins.
Value Mode Description
0 LOC0 Location 0
1 LOC1 Location 1
7:4 Reserved To ensure compatibility with future devices, always write bits to 0. More information in 2.1 Conven-
tions.
3 CH3PEN 0 RW CH3 Pin Enable
When set, GPIO output from PRS channel 3 is enabled
2 CH2PEN 0 RW CH2 Pin Enable
When set, GPIO output from PRS channel 2 is enabled
1 CH1PEN 0 RW CH1 Pin Enable
When set, GPIO output from PRS channel 1 is enabled
0 CH0PEN 0 RW CH0 Pin Enable
When set, GPIO output from PRS channel 0 is enabled
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13.5.4 PRS_CHx_CTRL - Channel Control Register
Offset Bit Position
0x010
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
16
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
Reset
0
0x0
0x00
0x0
Access
RW
RW
RW
RW
Name
ASYNC
EDSEL
SOURCESEL
SIGSEL
Bit Name Reset Access Description
31:29 Reserved To ensure compatibility with future devices, always write bits to 0. More information in 2.1 Conven-
tions.
28 ASYNC 0 RW Asynchronous reflex
Set to disable synchronization of this reflex signal
27:26 Reserved To ensure compatibility with future devices, always write bits to 0. More information in 2.1 Conven-
tions.
25:24 EDSEL 0x0 RW Edge Detect Select
Select edge detection.
Value Mode Description
0 OFF Signal is left as it is
1 POSEDGE A one HFPERCLK cycle pulse is generated for every positive edge of
the incoming signal
2 NEGEDGE A one HFPERCLK clock cycle pulse is generated for every negative
edge of the incoming signal
3 BOTHEDGES A one HFPERCLK clock cycle pulse is generated for every edge of the
incoming signal
23:22 Reserved To ensure compatibility with future devices, always write bits to 0. More information in 2.1 Conven-
tions.
21:16 SOURCESEL 0x00 RW Source Select
Select input source to PRS channel.
Value Mode Description
0b000000 NONE No source selected
0b000001 VCMP Voltage Comparator
0b000010 ACMP0 Analog Comparator 0
0b000011 ACMP1 Analog Comparator 1
0b000110 DAC0 Digital to Analog Converter 0
0b001000 ADC0 Analog to Digital Converter 0
0b010000 USART0 Universal Synchronous/Asynchronous Receiver/Transmitter 0
0b010001 USART1 Universal Synchronous/Asynchronous Receiver/Transmitter 1
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Bit Name Reset Access Description
0b010010 USART2 Universal Synchronous/Asynchronous Receiver/Transmitter 2
0b011100 TIMER0 Timer 0
0b011101 TIMER1 Timer 1
0b011110 TIMER2 Timer 2
0b011111 TIMER3 Timer 3
0b100100 USB Universal Serial Bus Interface
0b101000 RTC Real-Time Counter
0b101001 UART0 Universal Asynchronous Receiver/Transmitter 0
0b101010 UART1 Universal Asynchronous Receiver/Transmitter 1
0b110000 GPIOL General purpose Input/Output
0b110001 GPIOH General purpose Input/Output
0b110100 LETIMER0 Low Energy Timer 0
0b110111 BURTC Backup RTC
0b111001 LESENSEL Low Energy Sensor Interface
0b111010 LESENSEH Low Energy Sensor Interface
0b111011 LESENSED Low Energy Sensor Interface
15:3 Reserved To ensure compatibility with future devices, always write bits to 0. More information in 2.1 Conven-
tions.
2:0 SIGSEL 0x0 RW Signal Select
Select signal input to PRS channel.
Value Mode Description
SOURCESEL =
0b000000 (NONE)
0bxxx OFF Channel input selection is turned off
SOURCESEL =
0b000001 (VCMP)
0b000 VCMPOUT Voltage comparator output VCMPOUT
SOURCESEL =
0b000010 (ACMP0)
0b000 ACMP0OUT Analog comparator output ACMP0OUT
SOURCESEL =
0b000011 (ACMP1)
0b000 ACMP1OUT Analog comparator output ACMP1OUT
SOURCESEL =
0b000110 (DAC0)
0b000 DAC0CH0 DAC ch0 conversion done DAC0CH0
0b001 DAC0CH1 DAC ch1 conversion done DAC0CH1
SOURCESEL =
0b001000 (ADC0)
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Bit Name Reset Access Description
0b000 ADC0SINGLE ADC single conversion done ADC0SINGLE
0b001 ADC0SCAN ADC scan conversion done ADC0SCAN
SOURCESEL =
0b010000 (USART0)
0b000 USART0IRTX USART 0 IRDA out USART0IRTX
0b001 USART0TXC USART 0 TX complete USART0TXC
0b010 USART0RXDATAV USART 0 RX Data Valid USART0RXDATAV
SOURCESEL =
0b010001 (USART1)
0b001 USART1TXC USART 1 TX complete USART1TXC
0b010 USART1RXDATAV USART 1 RX Data Valid USART1RXDATAV
SOURCESEL =
0b010010 (USART2)
0b001 USART2TXC USART 2 TX complete USART2TXC
0b010 USART2RXDATAV USART 2 RX Data Valid USART2RXDATAV
SOURCESEL =
0b011100 (TIMER0)
0b000 TIMER0UF Timer 0 Underflow TIMER0UF
0b001 TIMER0OF Timer 0 Overflow TIMER0OF
0b010 TIMER0CC0 Timer 0 Compare/Capture 0 TIMER0CC0
0b011 TIMER0CC1 Timer 0 Compare/Capture 1 TIMER0CC1
0b100 TIMER0CC2 Timer 0 Compare/Capture 2 TIMER0CC2
SOURCESEL =
0b011101 (TIMER1)
0b000 TIMER1UF Timer 1 Underflow TIMER1UF
0b001 TIMER1OF Timer 1 Overflow TIMER1OF
0b010 TIMER1CC0 Timer 1 Compare/Capture 0 TIMER1CC0
0b011 TIMER1CC1 Timer 1 Compare/Capture 1 TIMER1CC1
0b100 TIMER1CC2 Timer 1 Compare/Capture 2 TIMER1CC2
SOURCESEL =
0b011110 (TIMER2)
0b000 TIMER2UF Timer 2 Underflow TIMER2UF
0b001 TIMER2OF Timer 2 Overflow TIMER2OF
0b010 TIMER2CC0 Timer 2 Compare/Capture 0 TIMER2CC0
0b011 TIMER2CC1 Timer 2 Compare/Capture 1 TIMER2CC1
0b100 TIMER2CC2 Timer 2 Compare/Capture 2 TIMER2CC2
SOURCESEL =
0b011111 (TIMER3)
0b000 TIMER3UF Timer 3 Underflow TIMER3UF
0b001 TIMER3OF Timer 3 Overflow TIMER3OF
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Bit Name Reset Access Description
0b010 TIMER3CC0 Timer 3 Compare/Capture 0 TIMER3CC0
0b011 TIMER3CC1 Timer 3 Compare/Capture 1 TIMER3CC1
0b100 TIMER3CC2 Timer 3 Compare/Capture 2 TIMER3CC2
SOURCESEL =
0b100100 (USB)
0b000 USBSOF USB Start of Frame USBSOF
0b001 USBSOFSR USB Start of Frame Sent/Received USBSOFSR
SOURCESEL =
0b101000 (RTC)
0b000 RTCOF RTC Overflow RTCOF
0b001 RTCCOMP0 RTC Compare 0 RTCCOMP0
0b010 RTCCOMP1 RTC Compare 1 RTCCOMP1
SOURCESEL =
0b101001 (UART0)
0b001 UART0TXC USART 0 TX complete UART0TXC
0b010 UART0RXDATAV USART 0 RX Data Valid UART0RXDATAV
SOURCESEL =
0b101010 (UART1)
0b001 UART1TXC USART 0 TX complete UART1TXC
0b010 UART1RXDATAV USART 0 RX Data Valid UART1RXDATAV
SOURCESEL =
0b110000 (GPIO)
0b000 GPIOPIN0 GPIO pin 0 GPIOPIN0
0b001 GPIOPIN1 GPIO pin 1 GPIOPIN1
0b010 GPIOPIN2 GPIO pin 2 GPIOPIN2
0b011 GPIOPIN3 GPIO pin 3 GPIOPIN3
0b100 GPIOPIN4 GPIO pin 4 GPIOPIN4
0b101 GPIOPIN5 GPIO pin 5 GPIOPIN5
0b110 GPIOPIN6 GPIO pin 6 GPIOPIN6
0b111 GPIOPIN7 GPIO pin 7 GPIOPIN7
SOURCESEL =
0b110001 (GPIO)
0b000 GPIOPIN8 GPIO pin 8 GPIOPIN8
0b001 GPIOPIN9 GPIO pin 9 GPIOPIN9
0b010 GPIOPIN10 GPIO pin 10 GPIOPIN10
0b011 GPIOPIN11 GPIO pin 11 GPIOPIN11
0b100 GPIOPIN12 GPIO pin 12 GPIOPIN12
0b101 GPIOPIN13 GPIO pin 13 GPIOPIN13
0b110 GPIOPIN14 GPIO pin 14 GPIOPIN14
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Bit Name Reset Access Description
0b111 GPIOPIN15 GPIO pin 15 GPIOPIN15
SOURCESEL =
0b110100 (LETIM-
ER0)
0b000 LETIMER0CH0 LETIMER CH0 Out LETIMER0CH0
0b001 LETIMER0CH1 LETIMER CH1 Out LETIMER0CH1
SOURCESEL =
0b110111 (BURTC)
0b000 BURTCOF BURTC Overflow BURTCOF
0b001 BURTCCOMP0 BURTC Compare 0 BURTCCOMP0
SOURCESEL =
0b111001 (LE-
SENSE)
0b000 LESENSESCANRES0 LESENSE SCANRES register, bit 0 LESENSESCANRES0
0b001 LESENSESCANRES1 LESENSE SCANRES register, bit 1 LESENSESCANRES1
0b010 LESENSESCANRES2 LESENSE SCANRES register, bit 2 LESENSESCANRES2
0b011 LESENSESCANRES3 LESENSE SCANRES register, bit 3 LESENSESCANRES3
0b100 LESENSESCANRES4 LESENSE SCANRES register, bit 4 LESENSESCANRES4
0b101 LESENSESCANRES5 LESENSE SCANRES register, bit 5 LESENSESCANRES5
0b110 LESENSESCANRES6 LESENSE SCANRES register, bit 6 LESENSESCANRES6
0b111 LESENSESCANRES7 LESENSE SCANRES register, bit 7 LESENSESCANRES7
SOURCESEL =
0b111010 (LE-
SENSE)
0b000 LESENSESCANRES8 LESENSE SCANRES register, bit 8 LESENSESCANRES8
0b001 LESENSESCANRES9 LESENSE SCANRES register, bit 9 LESENSESCANRES9
0b010 LESENSESCANRES10 LESENSE SCANRES register, bit 10 LESENSESCANRES10
0b011 LESENSESCANRES11 LESENSE SCANRES register, bit 11 LESENSESCANRES11
0b100 LESENSESCANRES12 LESENSE SCANRES register, bit 12 LESENSESCANRES12
0b101 LESENSESCANRES13 LESENSE SCANRES register, bit 13 LESENSESCANRES13
0b110 LESENSESCANRES14 LESENSE SCANRES register, bit 14 LESENSESCANRES14
0b111 LESENSESCANRES15 LESENSE SCANRES register, bit 15 LESENSESCANRES15
SOURCESEL =
0b111011 (LE-
SENSE)
0b000 LESENSEDEC0 LESENSE Decoder PRS out 0 LESENSEDEC0
0b001 LESENSEDEC1 LESENSE Decoder PRS out 1 LESENSEDEC1
0b010 LESENSEDEC2 LESENSE Decoder PRS out 2 LESENSEDEC2
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14. EBI - External Bus Interface
43210
EBI
(DEVICE)
External
Async.
Device
Parallel Interface
Quick Facts
What?
The EBI is used for accessing external parallel devi-
ces. The devices appear as a part of the
EFM32WG's internal memory map and are therefore
extremely simple to use.
Why?
Even though the EFM32WG is versatile, there might
be a need for specific external devices such as extra
RAM, FLASH, LCD, TFT. The EBI simplifies the ac-
cess to such devices.
How?
Through memory mapping the devices appear as a
part of the internal memory map. When the process-
or performs read or writes to the address range of
the EBI, the EBI handles the data transfers to and
from the external devices. The EBI may be inter-
faced by the DMA, thus enabling operation in EM1.
14.1 Introduction
The External Bus Interface provides access to external parallel interface devices such as SRAM, FLASH, ADCs and LCDs. The inter-
face is memory mapped into the address bus of the Cortex-M4. This enables seamless access from software without manually manipu-
lating the IO settings each time a read or write is performed. The data and address lines can be multiplexed in order to reduce the
number of pins required to interface the external devices. The bus timing is adjustable to meet specifications of the external devices.
The interface is limited to asynchronous devices and TFT.
14.2 Features
• Programmable interface for various memory types
• 4 memory bank regions
• Individual chip select line (EBI_CSn) per memory bank
• Accurate control of setup, strobe, hold and turn-around timing per memory bank
• Individual active high / active low setting of interface control signals per memory bank
• Slave read/write cycle extension per memory bank
• Page mode read
• NAND Flash support
• Both multiplexed and non-multiplexed address and data line configurations
• Up to 28 address lines
• Up to 16-bit data bus width
• Automatic translation when AHB transaction width and memory width differ
• Configurable prefetch from external device
• Write buffer to limit stalling of the Cortex-M4 or DMA
• TFT Direct Drive
• Programmable display and porch sizes
• Programmable bus timing (frequency, setup and hold timing)
• Individual active high / active low setting of interface control signals
• Frame buffer can be either on-chip or off-chip
• Alpha-blending and masking
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14.3 Functional Description
An overview of the EBI module is shown in the following figure. The EBI module consists of two submodules. The first submodule im-
plements a generic external device interface to for example SRAM or Flash devices. The second submodule implements a TFT RGB
interface which can be used together with the generic external device interface to perform TFT Direct Drive from an external framebuff-
er to a TFT display.
The EBI has multiplexed and non-multiplexed addressing modes. Fastest operation is achieved when using a non-multiplexed address-
ing mode. The multiplexed addressing modes are somewhat slower and require an external latch, but they use a significantly lower
number of pins. The use of the 16 EBI_AD pin connections depends on the addressing mode. They are used for both address and data
in the multiplexed modes. Also for the non-multiplexed 8-bit address mode both the address and data fit into these 16 EBI_AD pins. If
more address bits or data bits are needed, external latches can be used to support up to 24-bit addresses or 16-bit data in the multi-
plexed addressing modes using only the 16 EBI_AD pins. Furthermore, independent of the addressing mode, up to 28 non-multiplexed
address lines can be enabled on the EBI_A pin connections.
When a read operation is requested by the Cortex-M4 or DMA via the EBI's AHB interface, the address is transferred onto the EBI_AD
and/or EBI_A bus. After a specific number of cycles, the EBI_REn pin is activated and data is read from the EBI_AD bus. When a write
operation is requested, the address is transferred onto the EBI_AD and/or EBI_A bus and subsequently the write data is transferred
onto the EBI_AD bus as the EBI_WEn pin is activated. The detailed operation in the supported modes is presented in the following
sections.
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BLA[Z7:
,ADus
EELWEVI
EBLREn
LBLn[1
Lcsnp
ELARD
EELALE
,NAN DW
,NAND
BLDCL
LDATAE
BLVSVN
ELHSYN
BLCSTFr
Timing
AHB
EBI_AD[15:0]
APB
CONTROL
Data/Address
EBI_REn
EBI_BLn[1:0]
EBI_CSn[3:0]
EBI_ARDY
EBI_ALE
Polarity
MODE
TFT Timing
AHB
APB
TFT CONTROL
EBI_DCLK
EBI_DATAEN
EBI_VSYNC
EBI_HSYNC
EBI_CSTFTn
TFT Polarity
TFT Size
EBI_A[27:0]
EBI_WEn
EBI_NANDWEn
EBI_NANDREn
Memory Interface
EBI
TFT Interface
Figure 14.1. EBI Overview
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14.3.1 Non-Multiplexed 8-Bit Data, 8-Bit Address Mode
In this mode, 8-bit address and 8-bit data is supported. The address is put on the higher 8 bits of the EBI_AD lines while the data uses
the lower 8 bits. This mode is set by programming the MODE field in the EBI_CTRL register to D8A8. The address space can be exten-
ded to 256 MB by using the EBI_A lines as described in 14.3.6 Extended Addressing. Read and write signals in 8-bit mode are shown
in the following figures.
ADDR[7:0]
EBI_AD[15:8]
RDSETUP
(0, 1, 2, ...)
RDSTRB
(1, 2, 3, ...)
EBI_CSn
EBI_REn
Z
RDHOLD
(0, 1, 2, ...)
Z DATA[7:0] Z
EBI_AD[7:0]
Figure 14.2. EBI Non-multiplexed 8-bit Data, 8-bit Address Read Operation
ADDR[7:0]
EBI_AD[15:8]
WRSETUP
(0, 1, 2, ...)
WRSTRB
(1, 2, 3, ...)
EBI_CSn
EBI_WEn
Z
DATA[7:0] Z
EBI_AD[7:0]
WRHOLD
(0, 1, 2, ...)
Figure 14.3. EBI Non-multiplexed 8-bit Data, 8-bit Address Write Operation
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DATA
ZXAT
AT
14.3.2 Multiplexed 16-bit Data, 16-bit Address Mode
In this mode, 16-bit address and 16-bit data is supported, but the utilization of an external latch is required. The 16-bit address and 16-
bit data bits are multiplexed on the EBI_AD lines. An illustration of such a setup is shown in the following figure. This mode is set by
programming the MODE field in the EBI_CTRL register to D16A16ALE.
Note: In this mode the 16-bit address is organized in 2-byte chunks at memory addresses aligned to 2-byte offsets. Consequently, the
LSB of the 16-bit address will always be 0. In order to double the address space, the 16-bit address is internally shifted one bit to the
right so that the LSB of the address driven into the EBI_AD bus, i.e. the EBI_AD[0]-bit, corresponds to the second least significant bit of
the address, i.e. ADDR[1]. At the external device, the LSB of the address must be tied either low or high in order to create a full ad-
dress.
EBI
(DEVICE)
External
Async.
Device
Latch ADDR
DATA
Control
ALE
EBI_AD
Figure 14.4. EBI Address Latch Setup
At the start of the transaction the address is output on the EBI_AD lines. The Latch is controlled by the ALE (Address Latch Enable)
signal and stores the address. Then the data is read or written according to operation. Read and write signals are shown in the follow-
ing figures.
ADDR[16:1]
EBI_AD[15:0]
EBI_ALE
ADDRSETUP
(1, 2, 3, ...)
Z DATA[15:0]
EBI_CSn
EBI_REn
Z
RDSETUP
(0, 1, 2, ...)
RDSTRB
(1, 2, 3, ...)
RDHOLD
(0, 1, 2, ...)
Figure 14.5. EBI Multiplexed 16-Bit Data, 16-Bit Address Read Operation
ADDR[16:1]
EBI_AD[15:0]
EBI_ALE
ADDRSETUP
(1, 2, 3, ...)
DATA[15:0]
EBI_CSn
EBI_WEn
Z
WRSETUP
(0, 1, 2, ...)
WRSTRB
(1, 2, 3, ...)
WRHOLD
(0, 1, 2, ...)
ADDRHOLD
(0, 1, 2, ...)
Figure 14.6. EBI Multiplexed 16-Bit Data, 16-Bit Address Write Operation
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177
14.3.3 Multiplexed 8-Bit Data, 24-Bit Address Mode
This mode allows 24-bit address with 8-bit data multiplexed on the EBI_AD lines. The upper 8 bits of the EBI_AD lines are consecutive-
ly used for the highest 8 bits and the lowest 8 bits of the address. The lower 8 bits of the EBI_AD lines are used for the middle 8
address bits and for data. This mode is set by programming the MODE field in the EBI_CTRL register to D8A24ALE. Read and write
signals are shown in the following figures.
ADDR[23:16]
EBI_AD[15:8]
EBI_ALE
ADDRSETUP
(1, 2, 3, ...)
RDSETUP
(0, 1, 2, ...)
RDSTRB
(1, 2, 3, ...)
EBI_CSn
EBI_REn
Z
RDHOLD
(0, 1, 2, ...)
ADDR[15:8] Z DATA[7:0] Z
EBI_AD[7:0]
ADDR[7:0]
Figure 14.7. EBI Multiplexed 8-Bit Data, 24-Bit Address Read Operation
ADDR[23:16]
EBI_AD[15:8]
EBI_ALE
ADDRSETUP
(1, 2, 3, ...)
ADDRHOLD
(0, 1, 2, ...)
WRSETUP
(0, 1, 2, ...)
EBI_CSn
EBI_WEn
Z
WRSTRB
(1, 2, 3, ...)
ADDR[15:8] DATA[7:0] Z
EBI_AD[7:0]
ADDR[7:0]
WRHOLD
(0, 1, 2, ...)
Figure 14.8. EBI Multiplexed 8-Bit Data, 24-Bit Address Write Operation
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14.3.4 Non-Multiplexed 16-Bit Data, N-Bit Address Mode
In this non-multiplexed mode 16-bit data is driven on the 16 EBI_AD lines. The addresses are driven on the EBI_A lines. The address
space can be up to 256 MB as described in 14.3.6 Extended Addressing. This mode is set by programming the MODE field in the
EBI_CTRL register to D16. Read and write signals are shown in the following figures for the case in which N address lines on EBI_A
have been enabled.
Note: In this mode the 16-bit address is organized in 2-byte chunks at memory addresses aligned to 2-byte offsets. Consequently, the
LSB of the 16-bit address will always be 0. In order to double the address space, the 16-bit address is internally shifted one bit to the
right so that the LSB of the address driven into the EBI_A bus, i.e. the EBI_A[0]-bit, corresponds to the second least significant bit of the
address, i.e. ADDR[1]. At the external device, the LSB of the address must be tied either low or high in order to create a full address.
ADDR[N:1]
EBI_A[N-1:0]
RDSETUP
(0, 1, 2, ...)
RDSTRB
(1, 2, 3, ...)
EBI_CSn
EBI_REn
Z
RDHOLD
(0, 1, 2, ...)
Z DATA[15:0] Z
EBI_AD[15:0]
Figure 14.9. EBI Non-Multiplexed 16-Bit Data Read Operation with Extended Address
ADDR[N:1]
EBI_A[N-1:0]
WRSETUP
(0, 1, 2, ...)
WRSTRB
(1, 2, 3, ...)
EBI_CSn
EBI_WEn
Z
DATA[15:0] Z
EBI_AD[15:0]
WRHOLD
(0, 1, 2, ...)
Figure 14.10. EBI Non-Multiplexed 16-Bit Data Write Operation with Extended Address
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14.3.5 Page Mode Read Operation
Page mode read operation can enhance the performance of a sequence of consecutive asynchronous read transactions by allowing
data at subsequent intrapage addresses to be read faster. Page mode operation is enabled by setting the PAGEMODE bitfield in the
EBI_RDTIMING (or EBI_RDTIMINGn) register to 1. If enabled, the RDPA bitfield in the EBI_PAGECTRL register defines the duration of
an intrapage access and the PAGELEN bitfield in the EBI_PAGECTRL register defines the number of members in a page. Page mode
reads can for example be triggered by consecutive reads resulting from wide AHB reads which are automatically translated into multiple
narrow external device reads. Page mode reads can also be triggered by sequential reads resulting from the EBI prefetch unit.
The number of members in a page together with the width of the external device and the INCHIT bit of the EBI_PAGECTRL register
define whether an address change results in an interpage access or in an intrapage access as shown in the following table.
Table 14.1. EBI Intrapage Hit Condition for Read on Address Addr (Non-Mentioned Addr Bits are Unchanged)
PAGELEN, INCHIT 8-bit External Device 16-bit External Device
PAGELEN=MEMBER4, INCHIT=0 Addr[1:0] changed Addr[2:0] changed
PAGELEN=MEMBER8, INCHIT=0 Addr[2:0] changed Addr[3:0] changed
PAGELEN=MEMBER16, INCHIT=0 Addr[3:0] changed Addr[4:0] changed
PAGELEN=MEMBER32, INCHIT=0 Addr[4:0] changed Addr[5:0] changed
PAGELEN=MEMBER4, INCHIT=1 Addr[1:0] incremented by 1 Addr[2:0] incremented by 2
PAGELEN=MEMBER8, INCHIT=1 Addr[2:0] incremented by 1 Addr[3:0] incremented by 2
PAGELEN=MEMBER16, INCHIT=1 Addr[3:0] incremented by 1 Addr[4:0] incremented by 2
PAGELEN=MEMBER32, INCHIT=1 Addr[4:0] incremented by 1 Addr[5:0] incremented by 2
The initial page mode transaction uses the read setup and read strobe timing as shown in the following figures depending on the used
addressing mode. Subsequent transactions are started by changing the low-order address bits and use the page access time defined in
the RDPA bitfield of the EBI_PAGECTRL register. The read hold state RDHOLD is only performed at the end of a page mode read
sequence or when bus turn-around occurs. Note that bus turn-around can occur even if only read transactions are performed as the
D16A16ALE addressing mode will drive the EBI_AD lines when programming the external address latch. In this case one bus turn-
around RDHOLDX cycle is automatically inserted in between the read and the write action on the EBI_AD lines. Note that for the
D16A16ALE addressing mode the RDPA state immediately follows the ADDRSETUP state, so the HALFALE feature will typically be
required to satisfy the external address latch hold requirement. In the D8A24ALE addressing mode there is no need to reprogram the
external address latch for intrapage addresses as the external latch then only latches the most significant, non-changed address lines.
The following figures show typical page mode read sequences for all addressing modes.
ADDR0
EBI_AD[15:8]
RDSETUP
(0, 1, 2, ...)
RDSTRB
(1, 2, 3, ...)
EBI_CSn
EBI_REn
RDHOLD
(0, 1, 2, ...)
Z DATA0
EBI_AD[7:0] DATA1 DATA2 DATA3
ADDR1 ADDR2 ADDR3 Z
Z
RDPA
(1, 2, 3, ...)
RDPA
(1, 2, 3, ...)
RDPA
(1, 2, 3, ...)
Figure 14.11. EBI Page Mode Read Operation for D8A8 Addressing Mode
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ADDR0
EBI_AD[15:0]
EBI_ALE
ADDRSETUP
(1, 2, 3, ...)
Z DATA0
EBI_CSn
EBI_REn
RDSETUP
(0, 1, 2, ...)
RDSTRB
(1, 2, 3, ...)
RDHOLD
(0, 1, 2, ...)
ADDR1 Z DATA1
RDSETUP
(0, 1, 2, ...)
RDPA
(1, 2, 3, ...)
RDHOLD
(0, 1, 2, ...)
ADDRSETUP
(1, 2, 3, ...)
Z
Figure 14.12. EBI Page Mode Read Operation for D16A16ALE Addressing Mode
ADDR0[23:16]
EBI_AD[15:8]
ADDRSETUP
(0, 1, 2, ...)
RDSTRB
(1, 2, 3, ...)
EBI_CSn
RDHOLD
(0, 1, 2, ...)
DATA0
EBI_AD[7:0] DATA1 DATA2 DATA3
ADDR1[7:0] ADDR2[7:0] ADDR3[7:0] Z
Z
RDPA
(1, 2, 3, ...)
RDPA
(1, 2, 3, ...)
RDPA
(1, 2, 3, ...)
EBI_ALE
EBI_REn
RDSETUP
(0, 1, 2, ...)
ADDR0[15:8]
ADDR0[7:0]
Z
Figure 14.13. EBI Page Mode Read Operation for D8A24ALE Addressing Mode
ADDR0
EBI_A[N-1:0]
RDSETUP
(0, 1, 2, ...)
RDSTRB
(1, 2, 3, ...)
EBI_CSn
EBI_REn
RDHOLD
(0, 1, 2, ...)
Z DATA0
EBI_AD[15:0] DATA1 DATA2 DATA3
ADDR1 ADDR2 ADDR3 Z
Z
RDPA
(1, 2, 3, ...)
RDPA
(1, 2, 3, ...)
RDPA
(1, 2, 3, ...)
Figure 14.14. EBI Page Mode Read Operation for D16 Addressing Mode
The maximum duration that a page is kept open is defined in the KEEPOPEN bitfield of the EBI_PAGECTRL register. New read trans-
actions which hit in an open page are started with RDPA intrapage timing if the KEEPOPEN time has not been exceeded at the start of
such a transaction. The default setting of KEEPOPEN, which is equal to 0, will therefore never allow for intrapage timing to occur.
Transactions are allowed to finish if the KEEPOPEN time is exceeded during the transaction. Otherwise the RDSTRB interpage timing
is used for the read transaction. Next to exceeding the KEEPOPEN time there are other reasons for closing an open page. In particular
EBI transactions which result in a write or a non-intrapage read always cause the page to be closed. Also the lack of a new EBI trans-
action will cause an open page to be closed. In order to prevent this last scenario as much as possible read transactions can often be
made back to back. This is achieved by enabling prefetching by setting PREFETCH to 1 in the EBI_RDTIMING (or EBI_RDTIMINGn)
register and by disallowing idle state insertion in between transfers by setting the NOIDLE (or NOIDLEn) bit to 1 in EBI_CTRL register.
The following figure shows an example in which only ADDR1 benefits from intrapage timing because an unrelated AHB transfer not
directed at the EBI causes late arrival of ADDR2. ADDR2 arrives too late to be inserted as a back to back read transfer. The page is
considered closed and ADDR2 can therefore not benefit from intrapage timing and it results in an interpage access instead.
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ADDR0
EBI_A[N-1:0]
RDSETUP
(0, 1, 2, ...)
RDSTRB
(1, 2, 3, ...)
EBI_CSn
EBI_REn
RDHOLD
(0, 1, 2, ...)
Z DATA0
EBI_AD[15:0] DATA1
ADDR1 Z ADDR2
RDPA
(1, 2, 3, ...)
ADDR0
AHB ADDRESS NON-EBI ADDR2
ADDR1
RDSETUP
(0, 1, 2, ...)
Z
RDSTRB
(1, 2, 3, ...)
IDLE
Figure 14.15. EBI Page Closing
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DATA
AT
14.3.6 Extended Addressing
Extended addressing is used to extend the address range for any of the addressing modes described in 14.3.1 Non-Multiplexed 8-Bit
Data, 8-Bit Address Mode, 14.3.2 Multiplexed 16-bit Data, 16-bit Address Mode, 14.3.3 Multiplexed 8-Bit Data, 24-Bit Address Mode,
and 14.3.4 Non-Multiplexed 16-Bit Data, N-Bit Address Mode. Up to 28 address bits can be individually enabled on the EBI_A address
lines providing up to 256 MB of address space per memory bank. The operation on the EBI_AD lines is not affected by this. See
14.3.12 Bank Access for the memory map definitions related to the EBI. An example of address extension for the D16 mode is shown in
Figure 14.9 EBI Non-Multiplexed 16-Bit Data Read Operation with Extended Address on page 246 and Figure 14.10 EBI Non-Multi-
plexed 16-Bit Data Write Operation with Extended Address on page 246. A further example for address extension in the multiplexed 16-
bit data, 16-bit address mode of 14.3.2 Multiplexed 16-bit Data, 16-bit Address Mode is shown in the following figure. This is achieved
by programming the MODE field in the EBI_CTRL register to D16A16ALE and by enabling the required address lines via the ALB and
APEN bitfields of the EBI_ROUTE register.
EBI
(DEVICE)
External
Async.
Device
Latch ADDR LSBs
DATA
Control
ALE
ADDR MSBs
EBI_AD
EBI_A
Figure 14.16. EBI Extended Address Latch Setup
Read and write signals for using extended addressing in the D16A16ALE mode are shown in the following figures for the case in which
N extra address lines have been enabled. At the start of the transaction the lower address bits are output on the EBI_AD lines. The
Latch is controlled by the ALE (Address Latch Enable) signal and stores the address. Then the data is read or written according to
operation. The higher address bits are output on the EBI_A lines throughout the transfer.
ADDR[16:1]
EBI_ALE
EBI_AD[15:0]
ADDRSETUP
(1, 2, 3, ...)
Z DATA[15:0]
EBI_CSn
EBI_REn
Z
RDSETUP
(0, 1, 2, ...)
RDSTRB
(1, 2, 3, ...)
RDHOLD
(0, 1, 2, ...)
ADDR[16+N:17]
EBI_A[16+N-1:16]
Figure 14.17. EBI 16-Bit Data Multiplexed Read Operation using Extended Addressing
ADDR[16:1]
EBI_AD[15:0]
EBI_ALE
ADDRSETUP
(1, 2, 3, ...)
DATA[15:0]
EBI_CSn
EBI_WEn
Z
WRSETUP
(0, 1, 2, ...)
WRSTRB
(1, 2, 3, ...)
WRHOLD
(0, 1, 2, ...)
ADDRHOLD
(0, 1, 2, ...)
ADDR[16+N:17]
EBI_A[16+N-1:16]
Figure 14.18. EBI 16-Bit Data Multiplexed Write Operation using Extended Addressing
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In order to minimize the pin requirements both the lower bound and the upper bound of the enabled EBI_A lines can be set. This is
done in the ALB and APEN bitfields of the EBI_ROUTE register respectively. For example, in case all memory banks use the 8-bit ad-
dressing mode D8A8, then the lower 8 address bits are always output on EBI_AD. Therefore, if address extension is required, only
address bits 8 and upwards need to be enabled on EBI_A. This is done by setting the EBI_A lower bound to 8 by setting ALB to A8 in
EBI_ROUTE and by enabling the required higher address lines via the APEN bitfield in EBI_ROUTE. The operation of the APEN and
ALB bitfields is shown in the following table for some typical configurations.
Table 14.2. EBI Enabling EBI_ADDR Lines for Transaction with Address "Addr" and Data "Data"
Configuration Addresses on EBI_A Addresses/data on EBI_AD
MODE = D8A8, ALB = A8, APEN = A28 EBI_A[27:8] = Addr[27:8] EBI_AD[15:0] = {Addr[7:0], Data[7:0]}
MODE = D16A16ALE, ALB = A16, APEN =
A27
EBI_A[26:16] = Addr[27:17] EBI_AD[15:0] = Addr[16:1]; Data[15:0]
MODE = D8A24ALE, ALB = A24, APEN =
A28
EBI_A[27:24] = Addr[27:24] EBI_AD[15:0] = Addr[23:8]; {Addr[7:0], Da-
ta[7:0]}
MODE = D16, ALB = A0, APEN = A27 EBI_A[26:0] = Addr[27:1] EBI_AD[15:0] = Data[15:0]
14.3.7 Prefetch Unit and Write Buffer
Prefetching from external memory can enhance the performance of a sequence of consecutive transfers. In particular sequential code
execution from external memory can benefit from prefetch. Also prefetch will typically lead to better utilization of intrapage accesses in
case page mode is used. If prefetch is enabled, the prefetch unit will sequentially prefetch one data item of the same width as the last
Cortex-M4 or DMA read transaction handled by the EBI. Note that one prefetch transaction might lead to multiple external device trans-
actions as described in Table 14.3 EBI Mapping of AHB Transactions to External Device Transactions on page 255. Prefetch is not
performed in reaction to write transactions, nor will prefetch cross bank boundaries. The prefetch unit is enabled via the PREFETCH
bitfield in the EBI_RDTIMING and EBI_RDTIMINGn registers. When the ITS bitfield in the EBI_CTRL register is set to 0, the PRE-
FETCH bitfield from EBI_RDTIMING applies to all 4 memory banks. When ITS is set to 1 the prefetch unit can be individually enabled
per bank. In this case register EBI_RDTIMING only applies to bank 0. Prefetch enabling for bank n is then defined in the EBI_RDTI-
MINGn register.
The EBI has a 1 entry 32-bit wide write buffer. The write buffer can be used to limit stalling by partially decoupling the Cortex-M4 or
DMA from a potentially slow external device. Only writes which are guaranteed to not cause an error (e.g. timeout) in the EBI will be
buffered when the write buffer is enabled, such that precise error generation is guaranteed. The write buffer is disabled via the WBUF-
DIS bitfield in the EBI_WRTIMING and EBI_WRTIMINGn registers. When the ITS bitfield in the EBI_CTRL register is set to 0, the
WBUFDIS bitfield from EBI_WRTIMING applies to all 4 memory banks. When ITS is set to 1 the write buffer can be individually disa-
bled per bank. In this case register EBI_WRTIMING only applies to bank 0. Write buffer disabling for bank n is then defined in the
EBI_WRTIMINGn register.
The AHBACT status bit in the EBI_STATUS register indicates whether an AHB transaction is still active in the EBI or not. When per-
forming an AHB write, the AHBACT bit stays 1 until the required transaction(s) with the external device have finished, independent of
whether the AHB write gets buffered or not. On an AHB read with prefetching enabled, AHBACT stays high until the potential external
device prefetch transaction(s) have finished.
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14.3.8 Strobe Length
For external devices with low, but non-zero, setup requirements the performance overhead for EBI transactions can be relatively large if
a full cycle setup time needs to be used. It is possible to borrow half of the cycle time from a neighboring strobe phase in order to define
setup times with a granularity of half the internal clock period.
The durations of the EBI_ALE, EBI_REn, EBI_WEn, EBI_NANDREn and EBI_NANDWEn strobes can be individually decreased by half
the internal clock period via the HALFALE, HALFRE and HALFWE bitfields in the address timing, read timing and write timing registers
respectively. In case of EBI_ALE the trailing edge of the strobe can be moved half a clock period earlier. In case of EBI_REn,
EBI_WEn, EBI_NANDREn and EBI_NANDWEn the leading edge of the strobe can be moved half a clock period later. Decreasing the
length of the EBI_ALE strobe can be thought of as increasing the length of the RDSETUP phase by the same amount. Similarly, de-
creasing the length of the EBI_REn, EBI_WEn, EBI_NANDREn, EBI_NANDWEn strobes can be thought of as increasing the length of
the RDSETUP and WRSETUP phases. Note that the length of the ADDRSETUP, RDSTRB, and WRSTRB phases is still 1 or more
internal clock cycles. For example, when HALFRE is set to 1 and RDSTRB is programmed to 2, the length of the RDSTRB phase is 2
cycles. The duration of the EBI_REn pulse is however decreased by half a cycle to 1 1/2 cycles.
The following figures show read and write transactions in the multiplexed 16-bit address, 16-bit data mode in which half strobes are
enabled for EBI_ALE, EBI_REn and EBI_WEn.
ADDR[16:1]
EBI_AD[15:0]
EBI_ALE
ADDRSETUP
(1, 2, 3, ...)
Z DATA[15:0]
EBI_CSn
EBI_REn
Z
RDSETUP
(0, 1, 2, ...)
RDSTRB
(1, 2, 3, ...)
RDHOLD
(0, 1, 2, ...)
(½ , 1 ½ , 2 ½ , ...) (½) (½ , 1 ½ , 2 ½ , ...)(½)
Figure 14.19. EBI Multiplexed Read Operation with Reduced Length Strobes
ADDR[16:1]
EBI_AD[15:0]
EBI_ALE
ADDRSETUP
(1, 2, 3, ...)
DATA[15:0]
EBI_CSn
EBI_WEn
Z
ADDRHOLD
(0, 1, 2, ...)
WRSTRB
(1, 2, 3, ...)
WRHOLD
(0, 1, 2, ...)
(½ , 1 ½ , 2 ½ , ...) (½) (½ , 1 ½ , 2 ½ , ...)(½)
WRSETUP
(0, 1, 2, ...)
Figure 14.20. EBI Multiplexed Write Operation with Reduced Length Strobes
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ADDRO[7:O]
ADDR1[7:O]
Z
X DATAO[7:O] X
Z
X DATA
1[7:o] X
14.3.9 Bus Turn-Around and Idle Cycles
The EBI_AD lines can be driven by either the EFM32WG or by the external device. Depending on the characteristics of an external
device, the RDHOLD should be programmed to ensure adequate bus turnaround time. Default the EBI inserts an initial IDLE cycle,
during which the EBI does not drive the EBI_AD lines, after each external transaction. Furthermore, the EBI deasserts the EBI_CSn,
EBI_REn, and EBI_WEn lines during IDLE cycles. In case of subsequent IDLE cycles, after the initial one, the EBI will drive the EBI_AD
lines while keeping the EBI_CSn, EBI_REn, and EBI_WEn lines deasserted. The IDLE state insertion is shown for two back-to-back
read transactions in the first following figure. In case that the IDLE state provides the required bus turn-around time, the RDHOLD pa-
rameter can be programmed to 0. For increased performance, the automatic IDLE state insertion can be prevented by setting the NOI-
DLE/NOIDLEn bits in the EBI_CTRL register to 1. This scenario is shown in the second following figure for two back-to-back reads in a
non-multiplexed addressing mode. Note that in case RDSETUP and RDHOLD are both programmed to 0, then the EBI_REn line will
not be deasserted between back-to-back read transfers. The same will happen for non-multiplexed back-to-back write transactions with
WRSETUP and WRHOLD both programmed to 0. In case that NOIDLE/NOIDLEn is 1 and a read is immediately followed by a write on
the EBI_AD lines, one bus turn-around cycle called RDHOLDX is automatically inserted in between the read and the write action. Dur-
ing a RDHOLDX cycle the external EBI signals are driven in the same way as during regular RDHOLD cycles, i.e. the EBI_REn line will
get deasserted while the EBI_CSn line will stay asserted.
An IDLE cycle will automatically get inserted for the following cases:
• Between two external device transactions in case the NOIDLE/NOIDLEn bit is 0.
• Between two external device transactions to different banks.
• When no request for an external transaction is available in the EBI.
A RDHOLDX cycle will automatically get inserted for the following case:
• Between a read and a subsequent write on the EBI_AD lines. Note that this is only possible if NOIDLE/ NOIDLEn is set to 1. Also
note that a read in a multiplexed addressing mode (e.g. D16A16ALE) starts with a write on the EBI_AD lines when it is in the ADDR-
SETUP state.
ADDR0[7:0]
EBI_AD[15:8]
RDSETUP
(0, 1, 2, ...)
RDSTRB
(1, 2, 3, ...)
EBI_CSn
EBI_REn
RDHOLD
(0, 1, 2, ...)
Z DATA0[7:0]
EBI_AD[7:0]
ADDR1[7:0]
Z DATA1[7:0]
IDLE
(1, 2, ...)
RDSETUP
(0, 1, 2, ...)
RDSTRB
(1, 2, 3, ...)
RDHOLD
(0, 1, 2, ...)
IDLE
(1, 2, ...)
Figure 14.21. EBI Enforced IDLE Cycles between Transactions
ADDR0[7:0]
EBI_AD[15:8]
RDSETUP
(0, 1, 2, ...)
RDSTRB
(1, 2, 3, ...)
EBI_CSn
EBI_REn
RDHOLD
(0, 1, 2, ...)
Z DATA0[7:0]
EBI_AD[7:0]
ADDR1[7:0]
Z DATA1[7:0]
RDSETUP
(0, 1, 2, ...)
RDSTRB
(1, 2, 3, ...)
RDHOLD
(0, 1, 2, ...)
Figure 14.22. EBI No Enforced IDLE Cycles between Transactions
Note: In case NOIDLE/NOIDLEn bits are set in EBI_CTRL the read or write strobes can remain asserted for back-to-back transfers if
no further separation is guaranteed via for example RDSETUP, RDHOLD, WRSETUP, or WRHOLD bitfields.
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14.3.10 Timing
The duration of the states in the transaction is defined by the corresponding uppercase name above the state, e.g. the address setup
state in Figure 14.8 EBI Multiplexed 8-Bit Data, 24-Bit Address Write Operation on page 245 is active for a number of internal clock
cycles defined by ADDRSET bitfield in the EBI_ADDRTIMING register. Similar timing can be defined by the RDSTRB bitfield in the
EBI_RDTIMING register and WRSTRB in the EBI_WRTIMING register. These parameters all have a minimum duration of 1 cycle,
which is set by HW in case the bitfield is programmed to 0.
The setup and hold timing parameters are ADDRHOLD in the EBI_ADDRTIMING register, RDHOLD and RDSETUP in the
EBI_RDTIMING register and WRHOLD and WR SETUP in the EBI_WRTIMING register. Writing a value m to one of these bitfields
results in a duration of the corresponding state of m cycles. If these parameters are set to 0, it effectively means that the state is skip-
ped.
Page mode access time is defined in the RDPA bitfield of the EBI_PAGECTRL register. This parameters has a minimum duration of 1
cycle, which is set by HW in case the bitfield is programmed to 0.
When the ITS bitfield in the EBI_CTRL register is set to 0, the timing set defined in the EBI_ADDRTIMING, EBI_RDTIMING and
EBI_WRTIMING registers applies to all 4 memory banks. When ITS is set to 1 each memory bank uses an individual timing set. In this
case registers EBI_ADDRTIMING, EBI_RDTIMING and EBI_WRTIMING only apply to bank 0. Timing for bank n is then defined in the
EBI_ADDRTIMINGn, EBI_RDTIMINGn and EBI_WRTIMINGn registers.
Note: All timing related bitfields have a default value which is equal to the highest possible value for these bitfields, which makes the
default values a better fit for slow memory devices. This differs from the EFM32G devices in which the default values correspond to the
lowest possible values, which would only be appropriate for fast memory devices.
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14.3.11 Data Access Width
The mapping of AHB transactions to external device accesses depends on the data width of the external device and on whether or not
it supports byte lanes. The data width of external devices is specified in the MODE and MODEn bitfields of the EBI_CTRL register. An
external device is specified to be either 8-bit or 16-bit wide. Availability of byte lane support by the external device is specified via the
BL and BLn bitfields of the EBI_CTRL register. When the ITS bitfield in the EBI_CTRL register is set to 0, the MODE and BL bitfields
apply to all 4 memory banks. When ITS is set to 1 each memory bank uses an individual mode and byte lane enable definition. In this
case bitfields MODE and BL only apply to bank 0. The mode and byte lane availability for bank n is then defined in the MODEn and BLn
bitfields.
In case the AHB transaction width does not match the width of the selected device, the EBI automatically translates the AHB transac-
tion into 1 or more external device transactions matching the capabilities of that device. If one AHB transaction is translated into multi-
ple external transactions, then the external transactions have incrementing addresses and start with the lowest data byte(s) from the
AHB transaction. The translation, and possibly bus fault generation, is explained below and in the following table:
• If the AHB transaction width is larger than the external device width, then multiple consecutive external transactions are performed
starting with the least significant data.
• If the AHB transaction width is smaller than the external device width, then EBI behavior depends on whether or not byte lanes are
available for the selected device. Reads either use byte lane support when available, or read according to the full external device
width and disregard the superfluous data. Writes normally either use byte lane support when available, or perform a read-modify-
write sequence to only change the required data. However, NAND Flash does not support byte lanes or random access read-modi-
fy-write and therefore a hard fault is generated in case of an 8-bit write to a bank designated as 16-bit NAND bank.
Table 14.3. EBI Mapping of AHB Transactions to External Device Transactions
Data Access by
Cortex- M4, DMA,
or prefetch
8-bit External De-
vice (non- NAND)
transaction(s)
16-bit External De-
vice (non- NAND)
transaction(s) (with
byte lanes)
16-bit External De-
vice (non- NAND)
transaction(s)
(without byte
lanes)
8-bit NAND Flash
transaction(s)
16-bit NAND Flash
transaction(s)
8-bit read 1 x 8-bit read 1 x 8-bit read (using
byte lane)
1 x 16-bit read 1 x 8-bit read 1 x 16-bit read
16-bit read 2 x 8-bit read 1 x 16-bit read 1 x 16-bit read 2 x 8-bit read 1 x 16-bit read
32-bit read 4 x 8-bit read 2 x 16-bit read 2 x 16-bit read 4 x 8-bit read 2 x 16-bit read
8-bit write 1 x 8-bit write 1 x 8-bit write (using
byte lane)
1 x 16-bit read; 1 x
16-bit write (read-
modify-write)
1 x 8-bit write - (Hard fault)
16-bit write 2 x 8-bit write 1 x 16-bit write 1 x 16-bit write 2 x 8-bit write 1 x 16-bit write
32-bit write 4 x 8-bit write 2 x 16-bit write 2 x 16-bit write 4 x 8-bit write 2 x 16-bit write
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14.3.12 Bank Access
The EBI is split in 4 different address regions, each connected to an individual EBI_CSn line. When accessing one of the memory re-
gions, the corresponding CSn line is asserted. This way up to 4 separate devices can share the EBI lines and be identified by the
EBI_CSn line. Each bank can individually be enabled or disabled in the EBI_CTRL register.
The bank separation depends on whether the access originates from code space or not and on the setting of the ALTMAP bit in the
EBI_CTRL register. From code space three 32 MB banks and one 128 MB bank can be accessed. From data space either four 64 MB
banks (when ALTMAP bit is 0) or four 256 MB banks (when the ALTMAP bit is 1) can be accessed as shown in the following figures.
The EBI regions starting at address 0x80000000 in the memory map of the EFM32WG can also be used for code execution. When
running code via EBI regions starting at this address, the Cortex-M4 uses the System bus interface to fetch instructions. This results in
reduced performance as the Cortex-M4 accesses stack, other data in SRAM and peripherals using the System bus interface. Code
accesses via the System bus interface will not be cached. Furthermore, it should be noted that the address area from 0xA0000000 to
0xC0000000 is marked NX (no-execute) by default. To be able to run code via the EBI efficiently, the EBI is also mapped in the code
space at address 0x12000000. When running code from this space, the Cortex-M4 fetches instructions through the I/D-Code bus inter-
face, leaving the System bus interface for data access. Instructions fetched via the I/D-Code bus interface can be cached to increase
performance. The EBI regions mapped into the code space can however only be accessed by the CPU, i.e. not the DMA.
Depending on the setting of the ITS bitfield in the EBI_CTRL register. The external device behavior, including for example data width,
timing definitions, page mode operation, and pin polarities, is either defined for all banks at once or individually per bank.
EBI Region 0 (32 MB)
Code
0x00000000
0x1fffffff
0x20000000
0x7fffffff
0x12000000
EBI Region 1 (32 MB)
EBI Region 2 (32 MB)
0x13ffffff
0x14000000
0x15ffffff
0x16000000
0x17ffffff
0x18000000
0x1fffffff
EBI Region 3
(128 MB)
EBI Region 0 (64 MB)
0x80000000
EBI Region 2 (64 MB)
EBI Region 1 (64 MB)
0x83ffffff
0x84000000
0x87ffffff
0x88000000
0x8bffffff
0x8c000000
0x8fffffff
EBI Region 3 (64 MB)
EBI Regions
0x80000000
0xbfffffff
0xc0000000
0xffffffff
0x12000000
0x8fffffff
Figure 14.23. EBI Default Memory Map (ALTMAP = 0)
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EBI Region 0 (32 MB)
Code
0x00000000
0x1fffffff
EBI Regions
0x80000000
0xbfffffff
0xc0000000
0xffffffff
0x20000000
0x7fffffff
0x12000000
EBI Region 1 (32 MB)
EBI Region 2 (32 MB)
0x13ffffff
0x14000000
0x15ffffff
0x16000000
0x17ffffff
0x18000000
0x1fffffff
EBI Region 3 (128 MB)
EBI Region 0 (256 MB)
0x80000000
EBI Region 2 (256 MB)
EBI Region 1 (256 MB)
0x8fffffff
0x90000000
0x9fffffff
0xa0000000
0xafffffff
0xb0000000
0xbfffffff
EBI Region 3 (256 MB)
0x12000000
Figure 14.24. EBI Alternative Memory Map (ALTMAP = 1)
14.3.13 WAIT/ARDY
Some external devices are able to indicate that they are not finished with either write or read operation by asserting the WAIT / ARDY
line. This input signal is used to extend the REn/WEn cycles for slow devices. The interpretation of the polarity of this signal can be
configured with the ARDYPOL bit in EBI_POLARITY. E.g. if the ARDYPOL is set to ACTIVELOW, then the REn/WEn cycle is extended
while the ARDY line is kept low. The ARDY functionality is enabled by setting the ARDYEN bit in the EBI_CTRL register. It is also
possible to enable a timeout check, which generates a bus error if the ARDY is not deasserted within the timeout period. This prevents
a system lock up condition in the case that the external device does not deassert ARDY. The timeout functionality is disabled by setting
ARDYTODIS in the EBI_CTRL register.
When the ITS bitfield in the EBI_CTRL register is set to 0, the wait behavior defined in the ARDYEN and ARDYTODIS bitfields applies
to all 4 memory banks. When ITS is set to 1 each memory bank uses an individual wait behavior definition. In this case bitfields ARDY-
EN and ARDYTODIS only apply to bank 0. Wait behavior for bank n is then defined in the ARDYnEN and ARDYTOnDIS bitfields.
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14.3.14 NAND Flash Support
NAND Flash devices offer high density at relatively low cost when compared to NOR Flash devices. Unlike NOR Flash, which offers
random read access, NAND Flash devices are based on page access and use an indirect interface. Furthermore, a NAND Flash can
contain invalid bits leading to invalid blocks, which leads to requirements such as bit error detection/correction and bad block manage-
ment.
The EBI offers support for glueless connection of a NAND Flash by implementing dedicated EBI_NANDREn and EBI_NANDWEn pins
and by providing hardware for single error correction double error detection (SEC-DED) Error Correction Code (ECC) generation.
NAND Flash support is enabled by setting the EN bitfield in the EBI_NANDCTRL register to 1. The BANKSEL bitfield in
EBI_NANDCTRL defines which memory bank has a NAND Flash devices attached to it. NAND Flash data width, read timing, and write
timing are programmed via the standard EBI registers as described in 14.3.14.2 Width and Timing Configuration. ECC support is de-
scribed in Section 14.3.15 Error Correction Code.
Both standard and Chip Enable Don't Care (CEDC) NAND Flash devices are supported and they can be attached as shown in the
following figures. For standard NAND Flash devices, the Chip Enable (CEn) pin needs to remain asserted low during the entire read
cycle busy period, in which data is transferred from the memory array into the NAND Flash internal data registers in order to prevent an
early return to standby mode. CEDC NAND Flash devices do not have this restriction, but they do not support the automatic sequential
read function. For CEDC NAND Flash the shared EBI_REn and EBI_WEn pins can be used instead of the dedicated EBI_NANDREn
and EBI_NANDWEn pins.
EBI
(DEVICE) NAND
Flash
GPIO
CLE
ALE
R/B
CEn
WPn
IO[]
WEn
REn
EBI_NANDREn
GPIO (0)
EBI_A[25] (1)
EBI_A[24] (1)
EBI_NANDWEn
EBI_AD[] (3)
GPIO (4)
Figure 14.25. EBI Connection with Standard NAND Flash
EBI
(DEVICE) CE don’t care
NAND
Flash
GPIO
CLE
ALE
R/B
CEn
WPn
IO[]
WEn
REn
EBI_NANDREn(2)
GPIO (4)
EBI_CSn
EBI_A[25] (1)
EBI_A[24] (1)
EBI_NANDWEn(2)
EBI_AD[] (3)
Figure 14.26. EBI Connection with Chip Enable Don't Care NAND Flash
Note:
• (0) For a standard NAND Flash the EBI_CSn should be left unconnected
• (1) The address lines mapping to the NAND Flash ALE and CLE signals can be chosen as explained in 14.3.14.1 Register Selection
• (2) For a CEDC NAND Flash the shared EBI_REn and EBI_WEn pins can be used instead of the dedicated EBI_NANDREn and
EBI_NANDWEn pins
• (3) Both 8-bit and 16-bit NAND Flash are supported.
• (4) The NAND Flash ready/busy (R/B) signal should be observed via GPIO (not via EBI_ARDY)
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14.3.14.1 Register Selection
NAND Flash uses an indirect I/O interface in which the NAND Flash is controlled by programming the NAND Flash internal Command,
Address, and Data registers. NAND Flash does not use dedicated address lines. Because of this indirect I/O interface the NAND Flash
memory size is not restricted by the memory map of the EFM32WG. The NAND Command, Address, and Data registers can be ac-
cessed via memory mapped IO in which two address lines are chosen for connection with the ALE and CLE signals. The memory map-
ping and the two used address lines should be chosen such that they adhere to the ALE/CLE encoding shown in the following table.
Either EBI_A or EBI_AD address lines can be used as long as the chosen addressing mode does not multiplex data signals onto the
chosen lines. The EBI_A[25:24] address lines used in Figure 14.25 EBI Connection with Standard NAND Flash on page 258 and Figure
14.26 EBI Connection with Chip Enable Don't Care NAND Flash on page 258 are just an example.
Table 14.4. EBI NAND Flash Register Select
ALE CLE Selected NAND Flash Register
0 0 Data Register
0 1 Command Register
1 0 Address Register
1 1 Undefined
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14.3.14.2 Width and Timing Configuration
The regular EBI registers are used for defining transfer width, read timing, and write timing for the transactions on the NAND Flash
interface. NAND Flash specific parameters as for example block size or the number of address cycles are not configured in the EBI and
need to be dealt with via driver software. Also higher level tasks as for example wear-leveling, bad block management, and logical-to-
physical block mapping should be addressed via driver software.
External transaction width is defined via the address mode as defined in MODE field of EBI_CTRL. As only 3 NAND Flash registers are
memory mapped it suffices to use either the D8A8 or D16 address mode. The D16A16ALE and D8A24ALE address modes can also be
used, but they require unnecessary external address latch cycles and/or circuitry. For a 8-bit wide NAND Flash device, the D8A8 ad-
dress mode is therefore recommended, whereas for a 16-bit wide NAND Flash device the D16 address mode is recommended. If the
AHB transaction width does not match the external NAND device transaction width, then automatic transaction translation is performed
as described in 14.3.11 Data Access Width. Note that a bus fault is generated in case of an 8-bit write to a 16-bit NAND device as
neither byte lanes nor read-modify-write is supported for NAND Flash.
NAND Flash write timing is defined in the EBI_WRTIMING(n) register. The following figures show the command latch, address latch
and data input timing respectively assuming the D8A8 address mode with EBI_AD[x] used as ALE and EBI_AD[y] used as CLE.
EBI_AD[y] = NAND CLE
WRSETUP
(0, 1, 2, ...)
WRSTRB
(1, 2, 3, ...)
GPIO or EBI_CSn = NAND CEn
EBI_NANDWEn = NAND WEn
COMMAND
EBI_AD[7:0] = NAND IO
WRHOLD
(0, 1, 2, ...)
EBI_AD[x] = NAND ALE
tDS tDH
tCS tCH
tCLS
tALS
tCLH
tALH
tWP
GPIO = NAND R/B
tWB
Figure 14.27. EBI NAND Flash Command Latch Timing
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EBI_AD[y] = NAND CLE
WRSETUP
(0, 1, 2, ...)
WRSTRB
(1, 2, 3, ...)
GPIO or EBI_CSn = NAND CEn
EBI_NANDWEn = NAND WEn
ADDRESS
EBI_AD[7:0] = NAND IO
WRHOLD
(0, 1, 2, ...)
EBI_AD[x] = NAND ALE
tDS tDH
tCS tCH
tCLS
tALS
tCLH
tALH
tWP tWH
tWC
Figure 14.28. EBI NAND Flash Address Latch Timing
EBI_AD[y] = NAND CLE
WRSETUP
(0, 1, 2, ...)
WRSTRB
(1, 2, 3, ...)
GPIO or EBI_CSn = NAND CEn
EBI_NANDWEn = NAND WEn
DATA IN
EBI_AD[7:0] = NAND IO
WRHOLD
(0, 1, 2, ...)
EBI_AD[x] = NAND ALE
tDS tDH
tCS tCH
tCLS
tALS
tCLH
tALH
tWP tWH
tWC
Figure 14.29. EBI NAND Flash Data Input Timing
The EBI_WRTIMING(n) setting requirements for satisfying the NAND Flash timing parameters for command latching, address latching
and data input timing are shown in the following table.
Table 14.5. EBI NAND Flash Write Timing
NAND Flash Write Timing Parameter EBI Write Timing Parameter Requirements
tADL <= t(WRHOLD) + t(WRSETUP) + t(WRSTRB)
tALS <= t(WRSETUP) + t(WRSTRB)
tCS <= t(WRSETUP) + t(WRSTRB)
tCLS <= t(WRSETUP) + t(WRSTRB)
tDS <= t(WRSETUP) + t(WRSTRB)
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NAND Flash Write Timing Parameter EBI Write Timing Parameter Requirements
tALH <= t(WRHOLD)
tCH <= t(WRHOLD)
tCLH <= t(WRHOLD)
tDH <= t(WRHOLD)
tWC <= t(WRHOLD) + t(WRSETUP) + t(WRSTRB)
tWH <= t(WRHOLD) + t(WRSETUP)
tWP <= t(WRSTRB)
tWB (R/B edges can be detected by edge triggered GPIO interrupts)
NAND Flash read timing is defined in the EBI_RDTIMING(n) register. The following figure shows the NAND Flash data output timing
assuming the D8A8 address mode.
RDSETUP
(0, 1, 2, ...)
RDSTRB
(1, 2, 3, ...)
GPIO or EBI_CSn = NAND CEn
EBI_NANDWEn = NAND REn
DATA OUT
EBI_AD[7:0] = NAND IO
RDHOLD
(0, 1, 2, ...)
tRHOH
tRP
ZZ
tREH
GPIO = NAND R/B
tRR
tCEA
tREA tRHZ
tRC
Figure 14.30. EBI NAND Flash Data Output Timing
The EBI_RDTIMING(n) setting requirements for satisfying the NAND Flash timing parameters for data output timing are shown in the
following table.
Table 14.6. EBI NAND Flash Read Timing
NAND Read Timing Parameter EBI Read Timing Parameter Requirements
tCEA <= t(RDSETUP) + t(RDSTRB)
tREA <= t(RDSTRB)
tRP <= t(RDSTRB)
tRHZ <= t(RDHOLD)
tREH <= t(RDHOLD) + t(RDSETUP)
tRC <= t(RDHOLD) + t(RDSETUP) + t(RDSTRB)
tRR <= t(RDSETUP) (assuming software wait for R/B high)
tAR <= t(RDSETUP)
tCLR <= t(RDSETUP)
tIR <= t(RDSETUP)
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The NAND Flash timing parameters tWHR and tRHW define separation of read and write pulses and therefore they can be satisfied by
a combination of EBI_RDTIMING(n) and EBI_WRTIMING(n) settings as shown in the following table.
Table 14.7. EBI NAND Flash Read/Write Timing Requirements
NAND Timing Parameter EBI Timing Parameter
tWHR <= t(WRHOLD) + t(RDSETUP)
tRHW <= t(RDHOLD) + t(WRSETUP)
Remaining NAND Flash timing parameters, e.g. tRST and tPROG, should be dealt with in software.
14.3.14.3 Application Examples
A typical 528-byte page read sequence for an 8-bit wide NAND Flash is as follows:
• Configuration: Enable and select the memory bank connected to the NAND Flash device via the EN and BANKSEL bitfields in the
EBI_NANDCTRL register. Set the MODE field of the EBI_CTRL register to D8A8 indicating that the attached device is 8-bit wide.
Program the EBI_RDTIMING and EBI_WRTIMING registers to fulfill the NAND timing requirements.
• Command and address phase: Program the NAND Command register to the page read command and program the NAND Address
register to the required read address. This can be done via Cortex- M4 or DMA writes to the memory mapped NAND Command and
Address registers. The automatic data access width conversions described in 14.3.11 Data Access Width can be used if desired to
for example automatically perform 4 consecutive address byte transactions in response to one 32-bit word AHB write to the NAND
Address register (in this case the 2 address LSBs should not be used to map onto the NAND ALE/CLE signals).
• Data transfer phase: Wait for the NAND Flash internal data transfer phase to complete as indicated via its ready/busy (R/B) pin. The
user can use the GPIO interrupt functionality for this. The 528-byte data is now ready for sequential transfer from the NAND Flash
Data register.
• Read phase: Clear the ECC_PARITY register and start Error Code Correction (ECC) parity generation by setting both the ECC-
START and ECCCLEAR bitfields in the EBI_CMD register to 1. Now all subsequently transferred data to/from the NAND Flash devi-
ces is used to generate the ECC parity code into the EBI_ECCPARITY register. Read 512 subsequent bytes of main area data from
the NAND Flash Data register via DMA transfers. This can for example be done via 32-bit word DMA transfers (as long as the two
address LSBs are not used to map onto the NAND ALE/CLE signals). Stop ECC parity generation by setting the ECCSTOP bitfield
in the EBI_CMD register to 1 so that following transactions will not modify the parity result. Read out the final 16 bytes from the
NAND Flash spare data area.
• Error correction phase: Compare the ECC code contained in the read spare area data against the computed ECC code from the
EBI_ECCPARITY register. The user software can accept, correct, or discard the read data according the comparison result. No au-
tomatic correction is performed.
A typical 528-byte page program sequence for an 8-bit wide NAND Flash is as follows:
• Configuration: Configure the EBI for NAND Flash support via the EBI_NANDCTRL, EBI_CTRL, EBI_RDTIMING and EBI_WRTIM-
ING registers.
• Command and address phase: Program the NAND Command register to command for page programming (serial data input) and
program the NAND Address register to the desired write address.
• Write phase: Clear the ECC_PARITY register and start Error Code Correction (ECC) parity generation by setting both the ECC-
START and ECCCLEAR bitfields in the EBI_CMD register to 1. Now all subsequently transferred data to/from the NAND Flash devi-
ces is used to generate the ECC parity code into the EBI_ECCPARITY register. Write 512 subsequent bytes of user main data to
the NAND Flash Data register via for example DMA transfers. Stop ECC parity generation and read out the computed ECC parity
data from EBI_ECCPARITY. Write the final 16 bytes of spare data including the computed ECC parity data bytes.
• Program phase: Write the auto program command to the NAND Flash Command register after which the NAND Flash will indicate
that it is busy via its read/busy (R/B) pin. After read/busy goes high again, the success of the program command can be verified by
programming the read status command.
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14.3.15 Error Correction Code
The EBI provides provides hardware support for generation of an Error Correction Code (ECC). The used ECC is a Hamming (Hsiao)
code providing single bit error correction and double error detection (SECDED). ECC can be used to detect and/or correct failing bits in
a NAND Flash page. ECC generation is enabled by setting bitfield ECCSTART in the EBI_CMD register to 1. All subsequent data traffic
to/from the memory bank specified in the BANKSEL bitfield of the EBI_NANDCTRL register is then used for generation of the ECC into
the EBI_ECCPARITY register independent of the address in that bank. ECC generation is stopped by writing 1 to the ECCSTOP bitfield
in the EBI_CMD register. The EBI_ECCPARITY register is cleared by writing 1 to the ECCCLEAR register. The ECCACT status bit in
the EBI_STATUS register shows whether ECC generation is active or not.
The ECC computation is as shown in the following figure and table. Although the table only shows the ECC generation for 8-bit data
transfers, the ECC hardware also works for 16-bit data transfers. In that case only the interpretation of the parity bits is different.
Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0
Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0
Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0
Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0
Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0
Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0
Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0
Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0
Byte 0
Byte 1
Byte 2
Byte 3
Byte N-4
Byte N-3
Byte N-2
Byte N-1
P8'
P8
P8'
P8
P32'
P16
P16'
P8'
P8
P8'
P8
P32
P16
P16'
...
...
...
...
...
...
...
...
...
...
...
...
...
...
...
P1 P1' P1 P1' P1 P1' P1 P1'
P2 P2' P2 P2'
P4 P4'
Figure 14.31. EBI ECC Generation
Table 14.8. EBI ECC Bit/Column Parity
Parity Bit Generation for 8-Bit Data
P1' Bit 6 xor Bit 4 xor Bit 2 xor Bit 0 xor P1'
P1 Bit 7 xor Bit 5 xor Bit 3 xor Bit 1 xor P1
P2' Bit 5 xor Bit 4 xor Bit 1 xor Bit 0 xor P2'
P2 Bit 7 xor Bit 6 xor Bit 3 xor Bit 2 xor P2
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Parity Bit Generation for 8-Bit Data
P4' Bit 3 xor Bit 2 xor Bit 1 xor Bit 0 xor P4'
P4 Bit 7 xor Bit 6 xor Bit 5 xor Bit 4 xor P4
Table 14.9. EBI ECC Byte/Row Parity
Parity Bit Generation for 8-Bit Data
RP(x) Byte(x)(7) xor Byte(x)(6) xor Byte(x)(5) xor Byte(x)(4) xor Byte(x)
(3) xor Byte(x)(2) xor Byte(x)(1) xor Byte(x)(0)
P8' RP(0) xor RP(2) xor RP(4) xor RP(6) xor ... xor RP(N-4) xor
RP(N-2)
P8 RP(1) xor RP(3) xor RP(5) xor RP(7) xor ... xor RP(N-3)xor
RP(N-1)
P16' RP(0) xor RP(1) xor RP(4) xor RP(5) xor ... xor RP(N-4) xor
RP(N-3)
P16 RP(2) xor RP(3) xor RP(6) xor RP(7) xor ... xor RP(N-2) xor
RP(N-1)
... ...
The generated ECC code can be read from the EBI_ECCPARITY register according to the format shown in the following figure. The
number of valid ECC bits depends on the number of transferred bytes during the time that the ECC hardware is running as indicated in
the following table.
P32768 P32768' P16384 P16384' P8192 P8192' P4096 P4096'EBI_ECCPARITY[31:24]
MSB LSB
P2048 P2048' P1024 P1024' P512 P512' P256 P256'EBI_ECCPARITY[23:16]
P128 P128' P64 P64' P32 P32' P16 P16'EBI_ECCPARITY[15:8]
P8 P8' P4 P4' P2 P2' P1 P1'EBI_ECCPARITY[7:0]
Figure 14.32. EBI EBI_ECCPARITY Format
Table 14.10. EBI EBI_ECCPARITY Calid Bits
Number of Data Bytes Used for ECC Generation Valid EBI_ECCPARITY Bits
256 EBI_ECCPARITY[21:0]
512 EBI_ECCPARITY[23:0]
1024 EBI_ECCPARITY[25:0]
2048 EBI_ECCPARITY[27:0]
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Number of Data Bytes Used for ECC Generation Valid EBI_ECCPARITY Bits
4096 EBI_ECCPARITY[29:0]
8192 EBI_ECCPARITY[31:0]
Software can compare, XOR, the parity data generated in EBI_ECCPARITY with the parity information stored in the spare area for the
used data set. The syndrome resulting from XOR'ing the valid EBI_ECCPARITY bits with the ECC code read from the spare area can
be used for error detection and correction as shown in the following table.
Table 14.11. EBI Error Detection Result
Error Detection Result Syndrome Interpretation
No Error Syndrome has all valid Pn, Pn'
bits 0
No error has been detected
1-bit Correctable Error For all valid syndrome (Pn, Pn')
pairs: Pn = not(Pn')
1 bit in the user main data is incorrect and it can be corrected. For
8-bit wide data the position of the incorrect bit is indicated by bit
pattern (P4, P2, P1); the position of the incorrect byte is indicated
by (..., P32, P16, P8). For 16-bit wide data the position of the in-
correct bit is (P8, P4, P2, P1); the incorrect byte number is indica-
ted by (..., P64, P32, P16)
ECC Error 1 bit of the XOR result is high An error has been detected in the ECC itself. No error has been
detected in the user data
Uncorrectable Error Other cases Multiple (2 or more) bits are incorrect. This error cannot be correc-
ted
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14.3.16 TFT Direct Drive
TFT Direct Drive can be used to automatically transfer frame data stored in either internal or external memory to a TFT display without
frame buffer. The EBI generates the necessary RGB control signals for the TFT display and it coordinates and aligns the pixel data
transfers accordingly. The Direct Drive engine is enabled by setting the DD bitfield in the EBI_TFTCTRL register to either INTERNAL or
EXTERNAL. The RGB interface consists of 8 or 16 data lines on EBI_AD together with the EBI_DATAEN, EBI_VSYNC, EBI_HSYNC
and EBI_DCLK control signals. EBI_TFTCSn indicates whether the DD bitfield is programmed to DISABLED or not. Whether Direct
Drive is active or not can also be read via the DDACT status bit in the EBI_STATUS register.
The dimensions of the visible display are defined in the VSZ and HSZ bitfields of the EBI_TFTSIZE register. Hardware automatically
adds 1 to the size programmed in these bitfields. The front and back porch sizes are defined in the HFPORCH, HBPORCH, VFPORCH
and VBPORCH bitfields of the EBI_TFTHPORCH and EBI_TFTVPORCH registers. The porch and visible display sizes define the num-
ber of EBI_DCLK pulses per line and the number of lines per frame according to the following equations.
Number of EBI_DCLK pulses per line = HBPORCH + (HSZ + 1) + HFPORCH
Number of lines per frame = VBPORCH + (VSZ + 1) + VFPORCH
The horizontal and vertical synchronization pulses begin at the starts of the horizontal and vertical back porch intervals respectively. For
the HSYNC pulse a delayed start position can be defined in the HSYNCSTART bitfield of the EBI_TFTHPORCH register. The end of
the HSYNC pulse is not delayed and therefore the HSYNC pulse width is shortened when using a non-zero HSYNCSTART. The
widths, or rather end positions, of the HSYNC and VSYNC synchronization pulses are defined in the HSYNC and VSYNC bitfields of
the EBI_TFTSIZE register respectively. The horizontal synchronization pulse width is specified in pixels. The vertical synchronization
pulse width is specified in lines. Hardware automatically adds 1 to the width programmed in these bitfields. The EBI_TFTSIZE bitfields
are shown in the following figure. When Direct Drive is enabled, the VCNT and HCNT bitfields in the EBI_TFTSTATUS register show
how the frame display progresses. VCNT is a counter containing the current line position in a frame. It counts from 0 (first line in the
vertical back porch) to VBPORCH + VSZ + VFPORCH (last line in the vertical front porch). HCNT is a counter containing the current
pixel position within a line. It counts from 0 (first pixel in the horizonal back porch) to HBPORCH + HSZ + HFPORCH (last pixel in the
horizontal front porch).
Total width = HBPORCH + (HSZ + 1) + HFPORCH
Visible Display
HSYNC+1
VSYNC+1
HBPORCH
VBPORCH
VFPORCH
HFPORCH
HCNT=0
VCNT=0
HCNT=HBPORCH+HSZ+HFPORCH
VCNT=0
HCNT=0
VCNT=VBPORCH+VSZ+VFPORCH
HCNT=HBPORCH+HSZ+HFPORCH
VCNT=VBPORCH+VSZ+VFPORCH
HSZ+1
Total height = VBPORCH + (VSZ + 1) + VFPORCH
VSZ+1
Figure 14.33. EBI TFT Size
While the Direct Drive engine is transferring frame data from internal or external memory to the TFT, the EBI can still be used for other
EBI transfers to external devices. The interleaving of such EBI transfers with transfers originating from the Direct Drive engine is con-
trolled via the INTERLEAVE field in the EBI_TFTCTRL register. Interleaving can be limited to occur only during the vertical and horizon-
tal porch intervals by setting the INTERLEAVE field to PORCH. EBI accesses outside the porch intervals while INTERLEAVE is set to
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PORCH can cause the insertion of a high number of wait states on the AHB bus. In case the TFT dot clock EBI_DCLK is relatively slow
compared to the external device access time, interleaving can also be allowed during the active interval of the TFT by setting the IN-
TERLEAVE bitfield to ONEPERDCLK or UNLIMITED. In both cases interleaving during the porch intervals is unlimited as it is when the
PORCH setting is used. If INTERLEAVE is set to ONEPERDCLK then at most 1 EBI access is inserted per EBI_DCLK period in the
active display interval at the point immediately after the pixel transfer. Wait states are inserted on the AHB bus while waiting for this
insertion point. The access time of such an interleaved transfer should be guaranteed by software to fit in the free interval between pixel
transfers as indicated in Figure 14.39 EBI TFT Pixel Timing on page 274. If INTERLEAVE is set to UNLIMITED, which is the default,
then there are no restrictions on performing EBI transactions during Direct Drive operation. Although transactions related to Direct Drive
have priority over other EBI transactions, jitter on the EBI_DCLK can be introduced in case an EBI transaction is ongoing while the
Direct Drive engine wants to insert its next transaction. In case the programmed EBI_DCLK period can not be met, the DDJIT interrupt
flag in the EBI_IF register is set and the EBI_DCLK period is stretched to accommodate the delayed pixel data.
Note: If INTERLEAVE is limited to PORCH only and zero porch sizes are programmed in the EBI_TFTHPORCH and
EBI_TFTVPORCH registers, then no slots are left open for interleaving traffic and therefore interleaving EBI accesses can never finish.
14.3.16.1 Direct Drive from Internal Memory
Any internal memory can be used as the frame source location for Direct Drive. Direct Drive display from internal memory is started by
setting the DD bitfield in the EBI_TFTCTRL register to INTERNAL. The TFT controller indicates that the pixel buffer EBI_TFTDD is
empty and needs to be filled by raising the corresponding DMA request. This DMA request is initially set and it is cleared when
EBI_TFTDD is written. It is set again once the pixel data has been transferred to the display. One DMA request is generated for each
visible pixel. The Direct Drive engine will automatically align the data written to EBI_TFTDD according to the setup and hold require-
ments with respect to EBI_DCLK and send it out to the TFT via the EBI_AD lines. Whether the EBI_TFTDD buffer is full or empty is
also signaled by the DDEMPTY interrupt flag in the EBI_IF register and by the TFTDDEMPTY status bit in the EBI_STATUS register.
Given the relatively low performance of using software polling and interrupts compared to using DMA, these non-DMA mechanisms are
only advised for very low pixel rates. If pixel data is not provided in time the EBI_DCLK will be stretched to accommodate the late pixel
data and the Direct Drive Jitter interrupt flag DDJIT in the EBI_IF register is set. The following figure shows the setup for Direct Drive
from internal memory.
Device
EBI_AD
TFT
EBI_DCLK
EBI_DATAEN
EBI_VSYNC, EBI_HSYNC
EBI_TFTCSn
DATA
Memory
EBI
Figure 14.34. EBI TFT Direct Drive from Internal Memory
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14.3.16.2 Direct Drive from External Memory
Direct Drive can also use an external memory bank as the frame source location. The used bank is defined in the BANKSEL bitfield of
the EBI_TFTCTRL register. Direct Drive display from external memory is started by setting the DD bitfield in the EBI_TFTCTRL register
to EXTERNAL. Data is then streamed directly from the external memory to the TFT. The following figures show the setup for Direct
Drive from external memory when using non-multiplexed and multiplexed address and data lines.
EBI
(MCU)
External
Memory
Device
ADDR
DATA
Control
TFT
EBI_DCLK
EBI_DATAEN
EBI_VSYNC, EBI_HSYNC
EBI_TFTCSn
DATA
EBI_A
EBI_AD
Figure 14.35. EBI TFT Direct Drive from External Memory (Non-Multiplexed Address/Data)
EBI
(DEVICE)
External
Memory
Device
Latch ADDR
DATA
Control
EBI_ALE
TFT
EBI_DCLK
EBI_DATAEN
EBI_VSYNC, EBI_HSYNC
EBI_TFTCSn
DATA
EBI_AD
Figure 14.36. EBI TFT Direct Drive from External Memory (Multiplexed Address/Data)
The start address for the frame transfer is defined in the EBI_TFTFRAMEBASE register. The Direct Drive address is automatically in-
cremented for each visible pixel and it does therefore not depend on the programmed porch sizes. The address increment depends on
the WIDTH bitfield in the EBI_TFTCTRL register. The increment per visible pixel is 1 if the WIDTH bitfield in the EBI_TFTCTRL register
is programmed to BYTE and it is 2 if WIDTH is programmed to HALFWORD. Additionally a horizontal stride is added to the Direct Drive
address at the end of each visible line. This stride can be programmed in the HSTRIDE bitfield of the EBI_TFTSTRIDE register. The
first visible pixel always corresponds to the address defined in the EBI_TFTFRAMEBASE register. On either the vertical or horizontal
synchronization event, as defined in the FBCTRIG bitfield of the EBI_TFTCTRL register, the EBI_TFTFRAMEBASE register is copied
into an internal frame base buffer (FBC). This allows software to reprogram the EBI_TFTFRAMEBASE register based on VSYNC or
HSYNC interrupts, which in turn can be used to for example implement double buffering or scrolling schemes. The HSYNC and VSYNC
interrupts are generated at the same time as the local copy of EBI_TFTFRAMEBASE is made. If software reprograms EBI_TFTFRA-
MEBASE in the interrupt service routine, then the new value will only be used for address generation of the next line (in case FBCTRIG
equals HSYNC) or the next frame (in case FBCTRIG equals VSYNC). For example, when FBCTRIG equals HSYNC and the interrupt
service routine triggered by the HSYNC interrupt reads VCNT as 0, then a software update of EBI_TFTFRAMEBASE will take effect for
Direct Drive addresses of the line which corresponds to a VCNT value of 1. Note that the EBI_TFTSTRIDE register is not relevant in
case the FBCTRIG is set to HSYNC as the HSYNC events reloads the internal frame base copy (FBC) with EBI_TFTFRAMEBASE at
the start of each line. The Direct Drive address computation is summarized in the following figure.
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FBCTRIG = VSYNC:
Visible Display
Local frame base copy FBC gets assigned with EBI_TFTFRAMEBASE on every EBI_VSYNC stobe.
P(HSZ,2)
The address increment per pixel (PSZ) is 1 if the WIDTH bitfield in EBI_TFTCTRL is programmed to BYTE and 2 if the
WIDTH bitfield is programmed to HALFWORD.
Local frame base copy FBC gets assigned with EBI_TFTFRAMEBASE on every EBI_HSYNC stobe.
Direct Drive Address for pixel P(x,y) = FBC + (x * PSZ)
Direct Drive Address for pixel P(x,y) = FBC + (x * PSZ) + (y * ((PSZ * (HSZ + 1)) + HSTRIDE))
P(0,0) P(1,0) P(3,0)P(2,0)
P(0,1) P(1,1) P(2,1) P(3,1)
P(0,2) P(1,2) P(2,2) P(3,2)
P(HSZ,0)
P(HSZ,1)
P(HSZ,VSZ)
P(0,VSZ) P(2,VSZ)P(2,VSZ) P(3,VSZ)
HBPORCH
VBPORCHVFPORCH
HFPORCH
FBCTRIG = HSYNC:
Figure 14.37. EBI Direct Drive Address
Note: In case that the memory bank used for external Direct Drive is defined as 16-bit wide, then the Direct Drive address is internally
shifted one bit to the right before being output on the EBI_AD or EBI_A lines.
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14.3.17 Alpha Blending and Masking
Automatic alpha blending and masking can be performed on AHB data written to or via the EBI. Alpha blending combines a foreground
color with a background color into a new blended color and is further described in 14.3.17.1 Alpha Blending. Masking is a mechanism to
suppress writes matching a specific color. It is used to preserve the background color and is further described in 14.3.17.2 Masking.
Masking, if enabled, is applied before alpha blending as shown in the following figure. Masking and alpha blending can be used for both
internal and external data transfers.
EBI_TFTMASK
EBI_AD
EBI_TFTPIXEL0 EBI_TFTPIXEL1EBI_TFTALPHA
EBI_TFTPIXEL
Mask
Check
Alpha Blend
EBI_AD
AHB WDATA
COLOR1SRC
blend
COLOR0 COLOR1
mask match
external = (MASKBLEND == EMASK) or (MASKBLEND == EALPHA) or
(MASKBLEND == EMASKEALPHA)
blend = (MASKBLEND == IALPHA) or (MASKBLEND == EALPHA)
external
0 1
0 1
0
1
mask match 0 1
Figure 14.38. EBI TFT Alpha Blending and Masking
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14.3.17.1 Alpha Blending
Automatic alpha blending can be performed on AHB data written to or via the EBI. Alpha blending can be enabled for either internal or
external writes by setting the MASKBLEND bitfield in the EBI_TFTCTRL register. Internal writes are writes to the internal
EBI_TFTPIXEL0 register. External writes are writes to the external device attached to the bank defined in the BANKSEL bitfield of the
EBI_TFTCTRL register. Alpha blending works on two data items: a foreground Color0 = {R0, G0, B0} and a background Color1 = {R1,
G1, B1}. These data items are encoded in either 565 RGB or 555 RGB format as defined in the RGBMODE bitfield of the
EBI_TFTCTRL register. In case that the 555 RGB format is used, only the 15 least significant bits of Color0 and Color1 are used for the
alpha blending operation itself. The most significant bit of the foreground Color0 is passed on unmodified as the most significant bit of
the alpha blending result. Alpha blending is performed according to the following formula:
AlphaBlend(Color0, Color1) = ((R0, G0, B0) × EBI_TFTALPHA) + ((R1, G1, B1) × (256 – EBI_TFTALPHA))
256
The 9-bit alpha blending factor is defined in the EBI_TFTALPHA register. The maximum allowed value for EBI_TFTALPHA is 256. An
alpha value of 0 corresponds to a fully transparent color, whereas an alpha value of 256 corresponds to a fully opaque color. The RGB
Color0 data is taken from either the internal write data (written to EBI_TFTPIXEL0) or from the external write data (written to bank
BANKSEL). The Color0 source selection is based on the MASKBLEND bitfield of the EBI_TFTCTRL register. Internal write data is used
for MASKBLEND settings equal to IMASK, IALPHA, or IMASKIALPHA. External write data is used for MASKBLEND settings equal to
EMASK, EALPHA, or EMASKEALPHA. The RGB data for Color1 is read from either the BANKSEL memory bank or from the
EBI_TFTPIXEL1 register as defined in the COLOR1SRC bitfield of the EBI_TFTCTRL register. The alpha blended result will be written
to the BANKSEL memory bank for external writes or to the EBI_TFTPIXEL register for internal writes. For transactions involving an
external memory device, the automatic transaction translation rules as described in 14.3.11 Data Access Width apply. For example, 1
32-bit wide AHB write to a 16-bit wide external memory can be used to automatically perform 2 16-bit alpha blending operations into
external memory. Three configurations of data source and destination are supported as described next.
In-place alpha blending into external memory is performed by writing RGB data D to address A in bank BANKSEL with COLOR1SRC
set to MEM and MASKBLEND set to EMASK, EALPHA, or EMASKEALPHA. Note that in this case the EBI automatically translates the
AHB write transaction into a read-modify-write sequence for the external memory.
Memory[A] = AlphaBlend(D, Memory[A])
Alpha blending into external memory with a Color1 from register is performed by writing RGB data D to address A in bank BANKSEL
with COLOR1SRC set to PIXEL1 and MASKBLEND set to EMASK, EALPHA, or EMASKEALPHA:
Memory[A] = AlphaBlend(D, EBI_TFTPIXEL1)
Internal alpha blending into register EBI_TFTPIXEL is performed by writing RGB data D to EBI_TFTPIXEL0 with COLOR1SRC set to
PIXEL1 and MASKBLEND set to IMASK, IALPHA, or IMASKEALPHA. This alpha blending interface is intended for use by both the
Cortex-M4 and the DMA controller. For DMA operation three DMA requests are generated. One DMA request indicating that
EBI_TFTPIXEL0 requires new data, one DMA request indicating that EBI_TFTPIXEL1 requires new data, and one DMA request indi-
cating that new blended data is available in EBI_TFTPIXEL. The write into EBI_TFTPIXEL0 triggers the alpha blending operation. If
software wants to reprogram EBI_TFTPIXEL1, then this should be done before the EBI_TFTPIXEL0 write, which triggers the alpha
blending. The status of the internal alpha blending interface can also be read via the TFTPIXEL0EMPTY, TFTPIXEL1EMPTY, and
TFTPIXELFULL bits in the EBI_STATUS register.
EBI_TFTPIXEL = AlphaBlend(EBI_TFTPIXEL0, EBI_TFTPIXEL1)
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14.3.17.2 Masking
The masking feature can be used to suppress writes. Instead of the write data, the original background color of a pixel is kept. Masking
is supported for writes to an external device and for writes to internal register EBI_TFTPIXEL0. The 16-bit data value corresponding to
the write data to be masked is defined in the EBI_TFTMASK register. Masking is always based on 16-bit data and it does not depend
on the RGB mode defined in the RGBMODE bitfield of the EBI_TFTCTRL register. For transactions involving an external memory de-
vice, the automatic transaction translation rules as described in 14.3.11 Data Access Width apply. For example, 1 32-bit wide AHB write
to a 16-bit wide external memory can be used to perform masking operations on both 16-bit transactions to the external device. Mask-
ing can for example be used when drawing an icon with rounded corners into an external frame buffer. Such an icon can be written to
the frame buffer using a 2-dimensional copy action. If the color of a pixel outside the rounded corners is set to match the value defined
in the EBI_TFTMASK register, then such a matching data transfer is suppressed. The resulting image in the frame buffer will keep its
original background around the corners of the icon.
External masking is enabled by setting the EMASK bit in the EBI_TFTCTRL register to 1. If enabled, writes to the memory bank defined
in the BANKSEL bitfield of the EBI_TFTCTRL register are suppressed in case the write data matches the value in EBI_TFTMASK.
Internal masking is enabled by setting the IMASK bit in the EBI_TFTCTRL register to 1. If enabled and EBI_TFTPIXEL0 is written with
data matching EBI_TFTMASK, then the background color from EBI_TFTPIXEL1 is copied into EBI_TFTPIXEL. If enabled and
EBI_TFTPIXEL0 is written with data not matching EBI_TFTMASK, then the color from EBI_TFTPIXEL0 (possibly alpha blended with
EBI_TFTPIXEL1) is written into EBI_TFTPIXEL. The three DMA requests and EBI_STATUS bits as described for internal alpha
blending also apply for internal masking.
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Pl
14.3.18 Direct Drive Timing
The timing definition for operating a TFT display in Direct Drive mode depends on where the frame buffer source is located. In case
internal memory is used as source, then only the TFT timing as defined in the EBI_TFTTIMING register is relevant. In case external
memory is used as the source memory, then both the timing parameters of the TFT display and the timing parameters of the memory
bank defined in the BANKSEL bitfield of the EBI_TFTCTRL register are relevant.
The minimum dot clock, EBI_DCLK, period is defined in the DCLKPERIOD bitfield of the EBI_TFTTIMING register. This parameter has
a minimum duration of 1 cycle, which is set by HW, and writing a value n to this bitfield results in an extended duration of 1+n cycles. At
cycle 0 (and then periodically with period DCLKPERIOD + 1) the EBI_DCLK inactive edges are generated. At the cycle defined in the
TFTSTART bitfield of the EBI_TFTTIMING the TFT Direct Drive transaction is started. The TFTSTART bitfield can be used to define the
duty cycle of the EBI_DCLK. This parameter has a minimum duration of 1 cycle, which is set by HW, and writing a value n to this bitfield
results in an extended duration of 1+n cycles. After performing the required actions to produce the required TFT pixel data on the
EBI_AD lines, the TFT transaction will pass through its TFTSETUP and TFTHOLD states as indicated in the first following figure. In this
figure, the duration of the states in the TFT transaction is defined by the corresponding uppercase name above the state and it is ex-
pressed in internal clock cycles. The TFT setup and hold times are set in the TFTHOLD and TFTSETUP bitfields in the EBI_TFTTIM-
ING register. Writing a value m to one of these bitfields results in a duration of the corresponding state of m internal clock cycles. If
these parameters are set to 0, it effectively means that the state is skipped. The TFT setup and hold timing is with respect to the active
edge of EBI_DCLK as defined in the DCLKPOL bitfield in the EBI_TFTPOLARITY register. The TFT setup and hold timing applies to all
TFT signals: EBI_AD, EBI_DATAEN, EBI_VSYNC, EBI_HSYNC and EBI_TFTCSn. The active EBI_DCLK edge is generated in be-
tween the TFTSETUP and TFTHOLD states. The TFTSTART bitfield therefore impacts the position of the active EBI_DCLK edge. The
later the TFT transaction is started, the later it will transition from its TFTSETUP to TFTHOLD state. If needed, the EBI_DCLK period is
automatically stretched beyond the DCLKPERIOD to complete the TFT transaction. EBI_DCLK period stretching occurs when the TFT
transaction does not complete in the specified time, which in turn can occur because of the following reasons:
• Specified timing parameters are conflicting. This can for example happen if the TFT setup plus hold time is programmed to be longer
than the EBI_DCLK period.
• TFT transaction is delayed by an ongoing EBI transaction. This transaction interference can be controlled by setting the transaction
interleaving strategy in the INTERLEAVE bitfield of the EBI_TFTCTRL register.
• TFT transaction data is not delivered in time. For internal Direct Drive this is caused by the Cortex-M4 or DMA not delivering the
data in time. For external Direct Drive the timing parameters defining the external device read access might not allow the TFT trans-
action to complete in time.
In case the specified DCLK_PERIOD is not met, the DDJIT interrupt flag in the EBI_IF register will be set.
PIXEL N
TFTSETUP
(0, 1, 2, ...)
DCLKPERIOD
(1, 2, 3, ...)
EBI_AD[15:0]
EBI_DCLK
TFTHOLD
(0, 1, 2, ...)
ZPIXEL N+1
TFTSETUP
(0, 1, 2, ...)
TFTHOLD
(0, 1, 2, ...)
DCLKPERIOD
(1, 2, 3, ...)
Z Z
Figure 14.39. EBI TFT Pixel Timing
When driving the TFT from internal memory, the TFT timing is defined in the EBI_TFTTIMING register as shown in the following figure.
Before each TFT transaction to the visible part of the display, the EBI will request new pixel data via an interrupt or DMA request. At the
time specified in the TFTSTART bitfield of the EBI_TFTTIMING register (and when pixel data has been provided), the TFT transaction
will start. For internal Direct Drive the TFT state machine will place the pixel data on the EBI_AD lines during the TFTWDATA state after
which the state machine will pass through the programmable TFTSETUP and TFTHOLD states.
EBI_AD[15:0] ZDATA[15:0] Z
TFTWDATA
(1)
EBI_DCLK
TFTHOLD
(0, 1, 2, ...)
TFTSETUP
(0, 1, 2, ...)
TFTSTART
(1, 2, 3, ...)
Figure 14.40. EBI TFT Direct Drive Internal Timing
When the TFT is driven directly from an external memory, the timing definitions for the bank defined in the BANKSEL bitfield of the
EBI_TFTCTRL register and those for the TFT are both used by Direct Drive to generate transactions satisfying the requirements of both
the memory device and the TFT display. The timing definition for the external memory device should be programmed according to its
requirements independent of the TFT timing. The following figure shows an example of the Direct Drive engine accessing an external
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memory using the multiplexed 16-bit data, 16-bit address (D16A16ALE) mode. The TFTSETUP and TFTHOLD states are now en-
closed within the read transaction states of the chosen mode. The external device read transaction is started at a time as defined by
TFTSTART. The read strobe on EBI_REn is automatically extended in duration to satisfy the TFT setup and hold requirements defined
in the TFTSETUP and TFTHOLD bitfields.
ADDR[16:1]
EBI_AD[15:0]
EBI_ALE
ADDRSETUP
(1, 2, 3, ...)
Z DATA[15:0]
EBI_CSn
EBI_REn
Z
RDSETUP
(0, 1, 2, ...)
RDSTRB
(1, 2, 3, ...)
RDHOLD
(0, 1, 2, ...)
EBI_DCLK
TFTHOLD
(0, 1, 2, ...)
TFTSETUP
(0, 1, 2, ...)
TFTSTART
(1, 2, 3, ...)
Figure 14.41. EBI TFT Direct Drive External Timing
The timing parameters related to the horizontal timing are shown in the following figure. These parameters are defined as pixel or
EBI_DCLK counts. The horizontal porch widths are defined in the HBPORCH and HFPORCH bitfields of the EBI_TFTHPORCH regis-
ter. A porch which has its width parameter programmed to 0 will be skipped. The width and start position of the horizontal synchroniza-
tion pulse EBI_HSYNC is programmed via the HSYNC and HSYNCSTART bitfields in the EBI_TFTHPORCH register.
EBI_AD[15:0]
EBI_HSYNC
EBI_DATAEN
EBI_DCLK
P0
HSZ
(1, 2, 3, ...)
HORIZONTAL BACK PORCH P1
...
...
PHSZ HORIZONTAL FRONT PORCH
HBPORCH
(0, 1, 2, ...)
HFPORCH
(0, 1, 2, ...)
...
...
... ...
...
... ...
...
...
...
...
HSYNC
(1, 2, 3, ...)
HSYNCSTART
(0, 1, 2, ...)
Figure 14.42. EBI TFT Horizontal Porch Timing
The timing parameters related to the vertical timing are shown in the following figure. These parameters are defined as line or
EBI_HSYNC counts. The vertical porch widths are defined in the VBPORCH and VFPORCH bitfields of the EBI_TFTVPORCH register.
A porch which has its width parameter programmed to 0 will be skipped. The width of the vertical synchronization pulse EBI_VSYNC is
programmed via the VSYNC bitfield in the EBI_TFTVPORCH register.
LINES
EBI_HSYNC
L0
VSZ
(1, 2, 3, ...)
VERTICAL BACK PORCH L1
...
LVSZ VERTICAL FRONT PORCH
VBPORCH
(0, 1, 2, ...)
VFPORCH
(0, 1, 2, ...)
...
... ...
...
...
...
... ...
EBI_VSYNC
VSYNC
(1, 2, 3, ...)
Figure 14.43. EBI TFT Vertical Porch Timing
The active edge of the EBI_DCLK and the other TFT related signals are by default driven off the positive edge of the internal clock. The
edges of the EBI_DCLK can also be driven off the negative edge of the internal clock by setting the SHIFTDCLK bitfield in the
EBI_TFTCTRL register to 1. The Direct Drive engine then shifts the active DCLK edge 1/2 an internal cycle into the TFTHOLD state.
Effectively the length of TFTSETUP state is increased by 1/2 an internal cycle, whereas the length of the TFTHOLD state is decreased
by 1/2 an internal cycle. SHIFTDCLK should not be set if TFTHOLD is set to zero cycles. The effect of the SHIFTDCLK bitfield is shown
in the following figures for a setup using the falling EBI_DCLK clock as its active edge.
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EBI_AD[15:0]
EBI_DCLK
TFTHOLD
(0, 1, 2, ...)
PIXEL N
TFTSETUP
(0, 1, 2, ...)
INTERNAL CLOCK
Figure 14.44. EBI TFT Pixel Timing: EBI_DCLK driven off Positive Edge Internal Clock
EBI_AD[15:0]
EBI_DCLK
TFTHOLD
(0, 1, 2, ...)
PIXEL N
TFTSETUP
(0, 1, 2, ...)
INTERNAL CLOCK
TFTSETUPHOLD
(½ + ½)
Figure 14.45. EBI TFT Pixel Timing: EBI_DCLK driven off Negative Edge Internal Clock
14.3.19 Control Signal Polarity
It is possible to individually configure the control signals to be active high/low by setting or clearing the appropriate bits in the EBI_PO-
LARITY register. When the ITS bitfield in the EBI_CTRL register is set to 0, the polarities defined in the EBI_POLARITY register applies
to all 4 memory banks. When ITS is set to 1 each memory bank uses an individual polarity definition. In this case register EBI_POLARI-
TY only applies to bank 0. Timing for bank n is then defined in the EBI_POLARITYn register.
The TFT control signals can also be individually configured to be active high/low by setting or clearing the appropriate bits in the
EBI_TFTPOLARITY register.
14.3.20 Pin Configuration
In order to give the EBI access to the external pins of the EFM32WG, the GPIO must be configured accordingly. The lines must be set
to Push-Pull, which is described in detail in the GPIO section.
All the EBI pins are enabled in the EBI_ROUTE register. The EBI_AD, EBI_WEn and EBI_REn pins are all enabled by the EBIPEN bit,
the EBI_CSn pins are enabled by the corresponding CSxPEN bit, the EBI_ALE pin is enabled by the ALEPEN bit , the EBI_BL pins are
enabled by the BLPEN bit, the EBI_NANDWEn and EBI_NANDREn pins are enabled by the NANDPEN bit, the TFT pins EBI_DCLK,
EBI_VSYNC and EBI_HSYNC are all enabled by the TFTPEN bit, the EBI_DATAEN pin is enabled by the DATAENPEN bit, the
EBI_CSTFT pin is enabled by the CSTFTPEN bit, the EBI_A pins are enabled by the ALB and APEN bitfields, and the EBI_ARDY pin is
enabled by the ARDYPEN bit of the EBI_ROUTE register.
For some of the EBI pins, alternative pin locations can be chosen by setting the LOCATION bitfield in the EBI_ROUTE register. These
alternative locations are specified in the datasheet.
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E E R
14.3.21 Interrupts
The TFT controller has 6 separate interrupt flags (VSYNC, HSYNC, VBPORCH, VFPORCH, DDEMPTY, DDJIT) in EBI_IF.
The VSYNC, HSYNC, VBPORCH, and VFPORCH interrupt flags indicate various synchronization points during the display of a frame.
The following figure shows the timing of the VSYNC, HSYNC, VBPORCH, and VFPORCH interrupt flags. The VSYNC and HSYNC
flags are set at the beginning of a frame and at the beginning of a line respectively. The VBPORCH and VFPORCH flags are set at the
end of the vertical back porch and at the beginning of the vertical front porch respectively (provided that the related porch is defined
with a non-zero width).
Visible Display
HBPORCH
VBPORCH
VFPORCH
HFPORCH
VSZ+1
HSZ+1
VSYNC, HSYNC
HSYNC
HSYNC
... ...
VBPORCH
... ...
HSYNC
VSYNC, HSYNC
HSYNC
HSYNC
... ...
... ...
HSYNC
Figure 14.46. EBI TFT Interrupts
The DDEMPTY interrupt flag indicates that the EBI_TFTDD register is empty during Direct Drive from internal memory. The DDJIT in-
terrupt flag indicates that the DCLKPERIOD is not met during Direct Drive operation.
Setting one of the interrupt flags will result in an EBI interrupt if the corresponding interrupt enable bit is set in the EBI_IEN register. All
generated interrupts from the EBI will activate the same interrupt vector when enabled.
14.3.22 DMA Request
In internal Direct Drive mode, when the DD bitfield in EBI_TFTCTRL register is INTERNAL, the TFT controller sends out a DMA request
when the pixel buffer EBI_TFTDD is empty and needs to be filled. This request is initially set and it is cleared when EBI_TFTDD is
written. It is set again once the pixel data has been transferred to the display. One DMA request is generated for each visible pixel.
The masking and alpha blending hardware uses three DMA requests related to the status of thee internal masking and alpha blending
registers EBI_TFTPIXEL0, EBI_TFTPIXEL1, and EBI_TFTPIXEL. The DMA request for EBI_TFTPIXEL0 indicates that new data can
be written to be used for internal masking or alpha blending. This request is initially set and it is cleared when EBI_TFTPIXEL0 is writ-
ten. The request is set again when EBI_TFTPIXEL is read. The DMA request for EBI_TFTPIXEL1 is initially set and it is cleared when
EBI_TFTPIXEL1 is written. Only when both EBI_TFTPIXEL0 and EBI_TFTPIXEL1 have been written, will a EBI_TFTPIXEL read set
the DMA request for EBI_TFTPIXEL1 again. The DMA request for EBI_TFTPIXEL indicates whether new masked and/or blended data
is available for reading in EBI_TFTPIXEL or not. It is set after completion of internal masking and alpha blending in reaction to a write to
EBI_TFTPIXEL0. It is cleared when EBI_TFTPIXEL is read.
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14.4 Register Map
The offset register address is relative to the registers base address.
Offset Name Type Description
0x000 EBI_CTRL RW Control Register
0x004 EBI_ADDRTIMING RW Address Timing Register
0x008 EBI_RDTIMING RW Read Timing Register
0x00C EBI_WRTIMING RW Write Timing Register
0x010 EBI_POLARITY RW Polarity Register
0x014 EBI_ROUTE RW I/O Routing Register
0x018 EBI_ADDRTIMING1 RW Address Timing Register 1
0x01C EBI_RDTIMING1 RW Read Timing Register 1
0x020 EBI_WRTIMING1 RW Write Timing Register 1
0x024 EBI_POLARITY1 RW Polarity Register 1
0x028 EBI_ADDRTIMING2 RW Address Timing Register 2
0x02C EBI_RDTIMING2 RW Read Timing Register 2
0x030 EBI_WRTIMING2 RW Write Timing Register 2
0x034 EBI_POLARITY2 RW Polarity Register 2
0x038 EBI_ADDRTIMING3 RW Address Timing Register 3
0x03C EBI_RDTIMING3 RW Read Timing Register 3
0x040 EBI_WRTIMING3 RW Write Timing Register 3
0x044 EBI_POLARITY3 RW Polarity Register 3
0x048 EBI_PAGECTRL RW Page Control Register
0x04C EBI_NANDCTRL RW NAND Control Register
0x050 EBI_CMD W1 Command Register
0x054 EBI_STATUS RStatus Register
0x058 EBI_ECCPARITY RECC Parity register
0x05C EBI_TFTCTRL RW TFT Control Register
0x060 EBI_TFTSTATUS RTFT Status Register
0x064 EBI_TFTFRAMEBASE RW TFT Frame Base Register
0x068 EBI_TFTSTRIDE RW TFT Stride Register
0x06C EBI_TFTSIZE RW TFT Size Register
0x070 EBI_TFTHPORCH RW TFT Horizontal Porch Register
0x074 EBI_TFTVPORCH RW TFT Vertical Porch Register
0x078 EBI_TFTTIMING RW TFT Timing Register
0x07C EBI_TFTPOLARITY RW TFT Polarity Register
0x080 EBI_TFTDD RW TFT Direct Drive Data Register
0x084 EBI_TFTALPHA RW TFT Alpha Blending Register
0x088 EBI_TFTPIXEL0 RW TFT Pixel 0 Register
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Offset Name Type Description
0x08C EBI_TFTPIXEL1 RW TFT Pixel 1 Register
0x090 EBI_TFTPIXEL RTFT Alpha Blending Result Pixel Register
0x094 EBI_TFTMASK RW TFT Masking Register
0x098 EBI_IF RInterrupt Flag Register
0x09C EBI_IFS W1 Interrupt Flag Set Register
0x0A0 EBI_IFC (R)W1 Interrupt Flag Clear Register
0x0A4 EBI_IEN RW Interrupt Enable Register
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14.5 Register Description
14.5.1 EBI_CTRL - Control Register
Offset Bit Position
0x000
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
16
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
Reset
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0x0
0x0
0x0
0x0
Access
RW
RW
RW
RW
RW
RW
RW
RW
RW
RW
RW
RW
RW
RW
RW
RW
RW
RW
RW
RW
RW
RW
RW
RW
RW
RW
Name
ALTMAP
ITS
BL3
BL2
BL1
BL
ARDYTO3DIS
ARDY3EN
ARDYTO2DIS
ARDY2EN
ARDYTO1DIS
ARDY1EN
ARDYTODIS
ARDYEN
NOIDLE3
NOIDLE2
NOIDLE1
NOIDLE
BANK3EN
BANK2EN
BANK1EN
BANK0EN
MODE3
MODE2
MODE1
MODE
Bit Name Reset Access Description
31 ALTMAP 0 RW Alternative Address Map Enable
This field enables or disables the alternative (256 MB per bank) address map.
30 ITS 0 RW Individual Timing Set, Line Polarity and Mode Definition Enable
This field enables or disables individual timing sets, line polarities and modes per bank.
29:28 Reserved To ensure compatibility with future devices, always write bits to 0. More information in 2.1 Conven-
tions.
27 BL3 0 RW Byte Lane Enable for bank 3
Enables or disables the Byte Lane functionality for bank 3. Ignored when ITS = 0.
26 BL2 0 RW Byte Lane Enable for bank 2
Enables or disables the Byte Lane functionality for bank 2. Ignored when ITS = 0.
25 BL1 0 RW Byte Lane Enable for bank 1
Enables or disables the Byte Lane functionality for bank 1. Ignored when ITS = 0.
24 BL 0 RW Byte Lane Enable for bank 0
Enables or disables the Byte Lane functionality for bank 0. Applies to all banks when ITS = 0. Applies to only bank 0 when
ITS = 1.
23 ARDYTO3DIS 0 RW ARDY Timeout Disable for bank 3
Enables or disables the ARDY timeout functionality for bank 3. The timeout value is 32 internal clock cycles. Ignored when
ITS = 0.
22 ARDY3EN 0 RW ARDY Enable for bank 3
Enables or disables the ARDY functionality for bank 3. Ignored when ITS = 0.
21 ARDYTO2DIS 0 RW ARDY Timeout Disable for bank 2
Enables or disables the ARDY timeout functionality for bank 2. The timeout value is 32 internal clock cycles. Ignored when
ITS = 0.
20 ARDY2EN 0 RW ARDY Enable for bank 2
Enables or disables the ARDY functionality for bank 2. Ignored when ITS = 0.
19 ARDYTO1DIS 0 RW ARDY Timeout Disable for bank 1
Enables or disables the ARDY timeout functionality for bank 1. The timeout value is 32 internal clock cycles. Ignored when
ITS = 0.
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Bit Name Reset Access Description
18 ARDY1EN 0 RW ARDY Enable for bank 1
Enables or disables the ARDY functionality for bank 1. Ignored when ITS = 0.
17 ARDYTODIS 0 RW ARDY Timeout Disable
Enables or disables the ARDY timeout functionality. The timeout value is 32 internal clock cycles. Applies to all banks when
ITS = 0. Applies to only bank 0 when ITS = 1.
16 ARDYEN 0 RW ARDY Enable
Enables or disables the ARDY functionality. Applies to all banks when ITS = 0. Applies to only bank 0 when ITS = 1.
15 NOIDLE3 0 RW No idle cycle insertion on bank 3.
Enables or disables idle state insertion between transfers for bank 3. Ignored when ITS = 0.
14 NOIDLE2 0 RW No idle cycle insertion on bank 2.
Enables or disables idle state insertion between transfers for bank 2. Ignored when ITS = 0.
13 NOIDLE1 0 RW No idle cycle insertion on bank 1.
Enables or disables idle state insertion between transfers for bank 1. Ignored when ITS = 0.
12 NOIDLE 0 RW No idle cycle insertion on bank 0.
Enables or disables idle state insertion between transfers for bank 0. Applies to all banks when ITS = 0. Applies to only
bank 0 when ITS = 1.
11 BANK3EN 0 RW Bank 3 Enable
This field enables or disables bank 3.
10 BANK2EN 0 RW Bank 2 Enable
This field enables or disables bank 2.
9 BANK1EN 0 RW Bank 1 Enable
This field enables or disables bank 1.
8 BANK0EN 0 RW Bank 0 Enable
This field enables or disables bank 0.
7:6 MODE3 0x0 RW Mode 3
This field sets the access mode the EBI will use for interfacing devices on bank 3. Ignored when ITS = 0.
Value Mode Description
0 D8A8 EBI_AD drives 8 bit data, 8 bit address, ALE not used. Extended ad-
dress bits can be enabled on EBI_A in the EBI_ROUTE register.
1 D16A16ALE EBI_AD drives 16 bit data, 16 bit address, ALE is used for address
latching. Extended address bits can be enabled on EBI_A in the
EBI_ROUTE register.
2 D8A24ALE EBI_AD drives 8 bit data, 24 bit address, ALE is used for address
latching. Extended address bits can be enabled on EBI_A in the
EBI_ROUTE register.
3 D16 EBI_AD drives 16 bit data, ALE not used. Extended address bits can
be enabled on EBI_A in the EBI_ROUTE register.
5:4 MODE2 0x0 RW Mode 2
This field sets the access mode the EBI will use for interfacing devices on bank 2. Ignored when ITS = 0.
Value Mode Description
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Bit Name Reset Access Description
0 D8A8 EBI_AD drives 8 bit data, 8 bit address, ALE not used. Extended ad-
dress bits can be enabled on EBI_A in the EBI_ROUTE register.
1 D16A16ALE EBI_AD drives 16 bit data, 16 bit address, ALE is used for address
latching. Extended address bits can be enabled on EBI_A in the
EBI_ROUTE register.
2 D8A24ALE EBI_AD drives 8 bit data, 24 bit address, ALE is used for address
latching. Extended address bits can be enabled on EBI_A in the
EBI_ROUTE register.
3 D16 EBI_AD drives 16 bit data, ALE not used. Extended address bits can
be enabled on EBI_A in the EBI_ROUTE register.
3:2 MODE1 0x0 RW Mode 1
This field sets the access mode the EBI will use for interfacing devices on bank 1. Ignored when ITS = 0.
Value Mode Description
0 D8A8 EBI_AD drives 8 bit data, 8 bit address, ALE not used. Extended ad-
dress bits can be enabled on EBI_A in the EBI_ROUTE register.
1 D16A16ALE EBI_AD drives 16 bit data, 16 bit address, ALE is used for address
latching. Extended address bits can be enabled on EBI_A in the
EBI_ROUTE register.
2 D8A24ALE EBI_AD drives 8 bit data, 24 bit address, ALE is used for address
latching. Extended address bits can be enabled on EBI_A in the
EBI_ROUTE register.
3 D16 EBI_AD drives 16 bit data, ALE not used. Extended address bits can
be enabled on EBI_A in the EBI_ROUTE register.
1:0 MODE 0x0 RW Mode
This field sets the access mode the EBI will use for interfacing devices. Applies to all banks when ITS = 0. Applies to only
bank 0 when ITS = 1.
Value Mode Description
0 D8A8 EBI_AD drives 8 bit data, 8 bit address, ALE not used. Extended ad-
dress bits can be enabled on EBI_A in the EBI_ROUTE register.
1 D16A16ALE EBI_AD drives 16 bit data, 16 bit address, ALE is used for address
latching. Extended address bits can be enabled on EBI_A in the
EBI_ROUTE register.
2 D8A24ALE EBI_AD drives 8 bit data, 24 bit address, ALE is used for address
latching. Extended address bits can be enabled on EBI_A in the
EBI_ROUTE register.
3 D16 EBI_AD drives 16 bit data, ALE not used. Extended address bits can
be enabled on EBI_A in the EBI_ROUTE register.
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14.5.2 EBI_ADDRTIMING - Address Timing Register
Offset Bit Position
0x004
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
16
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
Reset
0
0x3
0x3
Access
RW
RW
RW
Name
HALFALE
ADDRHOLD
ADDRSETUP
Bit Name Reset Access Description
31:29 Reserved To ensure compatibility with future devices, always write bits to 0. More information in 2.1 Conven-
tions.
28 HALFALE 0 RW Half Cycle ALE Strobe Duration Enable
Enables or disables half cycle duration of the ALE strobe in the last ADDRSETUP cycle.
27:10 Reserved To ensure compatibility with future devices, always write bits to 0. More information in 2.1 Conven-
tions.
9:8 ADDRHOLD 0x3 RW Address Hold Time
Sets the number of cycles the address is held after ALE is asserted.
7:2 Reserved To ensure compatibility with future devices, always write bits to 0. More information in 2.1 Conven-
tions.
1:0 ADDRSETUP 0x3 RW Address Setup Time
Sets the number of cycles the address is driven onto the ADDRDAT bus before ALE is asserted. If set to 0, 1 cycle is inser-
ted by HW.
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14.5.3 EBI_RDTIMING - Read Timing Register
Offset Bit Position
0x008
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
16
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
Reset
0
0
0
0x3
0x3F
0x3
Access
RW
RW
RW
RW
RW
RW
Name
PAGEMODE
PREFETCH
HALFRE
RDHOLD
RDSTRB
RDSETUP
Bit Name Reset Access Description
31 Reserved To ensure compatibility with future devices, always write bits to 0. More information in 2.1 Conven-
tions.
30 PAGEMODE 0 RW Page Mode Access Enable
Enables or disables page mode reads.
29 PREFETCH 0 RW Prefetch Enable
Enables or disables prefetching of data from sequential address.
28 HALFRE 0 RW Half Cycle REn Strobe Duration Enable
Enables or disables half cycle duration of the REn strobe in the last RDSTRB cycle.
27:18 Reserved To ensure compatibility with future devices, always write bits to 0. More information in 2.1 Conven-
tions.
17:16 RDHOLD 0x3 RW Read Hold Time
Sets the number of cycles CSn is held active after the REn is deasserted. This interval is used for bus turnaround.
15:14 Reserved To ensure compatibility with future devices, always write bits to 0. More information in 2.1 Conven-
tions.
13:8 RDSTRB 0x3F RW Read Strobe Time
Sets the number of cycles the REn is held active. After the specified number of cycles, data is read. If set to 0, 1 cycle is
inserted by HW.
7:2 Reserved To ensure compatibility with future devices, always write bits to 0. More information in 2.1 Conven-
tions.
1:0 RDSETUP 0x3 RW Read Setup Time
Sets the number of cycles the address setup before REn is asserted.
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14.5.4 EBI_WRTIMING - Write Timing Register
Offset Bit Position
0x00C
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
16
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
Reset
0
0
0x3
0x3F
0x3
Access
RW
RW
RW
RW
RW
Name
WBUFDIS
HALFWE
WRHOLD
WRSTRB
WRSETUP
Bit Name Reset Access Description
31:30 Reserved To ensure compatibility with future devices, always write bits to 0. More information in 2.1 Conven-
tions.
29 WBUFDIS 0 RW Write Buffer Disable
Enables or disables the write buffer.
28 HALFWE 0 RW Half Cycle WEn Strobe Duration Enable
Enables or disables half cycle duration of the WEn strobe in the last WRSTRB cycle.
27:18 Reserved To ensure compatibility with future devices, always write bits to 0. More information in 2.1 Conven-
tions.
17:16 WRHOLD 0x3 RW Write Hold Time
Sets the number of cycles CSn is held active after the WEn is deasserted.
15:14 Reserved To ensure compatibility with future devices, always write bits to 0. More information in 2.1 Conven-
tions.
13:8 WRSTRB 0x3F RW Write Strobe Time
Sets the number of cycles the WEn is held active. If set to 0, 1 cycle is inserted by HW.
7:2 Reserved To ensure compatibility with future devices, always write bits to 0. More information in 2.1 Conven-
tions.
1:0 WRSETUP 0x3 RW Write Setup Time
Sets the number of cycles the address setup before WEn is asserted.
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14.5.5 EBI_POLARITY - Polarity Register
Offset Bit Position
0x010
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
16
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
Reset
0
0
0
0
0
0
Access
RW
RW
RW
RW
RW
RW
Name
BLPOL
ARDYPOL
ALEPOL
WEPOL
REPOL
CSPOL
Bit Name Reset Access Description
31:6 Reserved To ensure compatibility with future devices, always write bits to 0. More information in 2.1 Conven-
tions.
5 BLPOL 0 RW BL Polarity
Sets the polarity of the EBI_BLn lines.
Value Mode Description
0 ACTIVELOW BLn[1:0] are active low.
1 ACTIVEHIGH BLn[1:0] are active high.
4 ARDYPOL 0 RW ARDY Polarity
Sets the polarity of the EBI_ARDY line.
Value Mode Description
0 ACTIVELOW ARDY is active low.
1 ACTIVEHIGH ARDY is active high.
3 ALEPOL 0 RW Address Latch Polarity
Sets the polarity of the EBI_ALE line.
Value Mode Description
0 ACTIVELOW ALE is active low.
1 ACTIVEHIGH ALE is active high.
2 WEPOL 0 RW Write Enable Polarity
Sets the polarity of the EBI_WEn and EBI_NANDWEn lines.
Value Mode Description
0 ACTIVELOW WEn and NANDWEn are active low.
1 ACTIVEHIGH WEn and NANDWEn are active high.
1 REPOL 0 RW Read Enable Polarity
Sets the polarity of the EBI_REn and EBI_NANDREn lines.
Value Mode Description
0 ACTIVELOW REn and NANDREn are active low.
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Bit Name Reset Access Description
1 ACTIVEHIGH REn and NANDREn are active high.
0 CSPOL 0 RW Chip Select Polarity
Sets the polarity of the EBI_CSn line.
Value Mode Description
0 ACTIVELOW CSn is active low.
1 ACTIVEHIGH CSn is active high.
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14.5.6 EBI_ROUTE - I/O Routing Register
Offset Bit Position
0x014
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
16
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
Reset
0x0
0
0
0
0x00
0x0
0
0
0
0
0
0
0
0
0
Access
RW
RW
RW
RW
RW
RW
RW
RW
RW
RW
RW
RW
RW
RW
RW
Name
LOCATION
CSTFTPEN
DATAENPEN
TFTPEN
APEN
ALB
NANDPEN
BLPEN
ARDYPEN
ALEPEN
CS3PEN
CS2PEN
CS1PEN
CS0PEN
EBIPEN
Bit Name Reset Access Description
31 Reserved To ensure compatibility with future devices, always write bits to 0. More information in 2.1 Conven-
tions.
30:28 LOCATION 0x0 RW I/O Location
Decides the location of the EBI I/O pins.
Value Mode Description
0 LOC0 Location 0
1 LOC1 Location 1
2 LOC2 Location 2
27 Reserved To ensure compatibility with future devices, always write bits to 0. More information in 2.1 Conven-
tions.
26 CSTFTPEN 0 RW EBI_CSTFT Pin Enable
When set, the EBI_CSTFT pin is enabled
25 DATAENPEN 0 RW EBI_TFT Pin Enable
When set, the EBI_DATAEN pin is enabled
24 TFTPEN 0 RW EBI_TFT Pin Enable
When set, the EBI_DCLK, EBI_VSYNC and EBI_HSYNC pins are enabled
23 Reserved To ensure compatibility with future devices, always write bits to 0. More information in 2.1 Conven-
tions.
22:18 APEN 0x00 RW EBI_A Pin Enable
Selects which non-multiplexed address lines are enabled on EBI_A. The lower bound L is set to 0, 8, 16 or 24 as defined in
the ALB field.
Value Mode Description
0 A0 All EBI_A pins are disabled.
5 A5 EBI_A[4:L] pins enabled.
6 A6 EBI_A[5:L] pins enabled.
7 A7 EBI_A[6:L] pins enabled.
8 A8 EBI_A[7:L] pins enabled.
9 A9 EBI_A[8:L] pins enabled.
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Bit Name Reset Access Description
10 A10 EBI_A[9:L] pins enabled.
11 A11 EBI_A[10:L] pins enabled.
12 A12 EBI_A[11:L] pins enabled.
13 A13 EBI_A[12:L] pins enabled.
14 A14 EBI_A[13:L] pins enabled.
15 A15 EBI_A[14:L] pins enabled.
16 A16 EBI_A[15:L] pins enabled.
17 A17 EBI_A[16:L] pins enabled.
18 A18 EBI_A[17:L] pins enabled.
19 A19 EBI_A[18:L] pins enabled.
20 A20 EBI_A[19:L] pins enabled.
21 A21 EBI_A[20:L] pins enabled.
22 A22 EBI_A[21:L] pins enabled.
23 A23 EBI_A[22:L] pins enabled.
24 A24 EBI_A[23:L] pins enabled.
25 A25 EBI_A[24:L] pins enabled.
26 A26 EBI_A[25:L] pins enabled.
27 A27 EBI_A[26:L] pins enabled.
28 A28 EBI_A[27:L] pins enabled.
17:16 ALB 0x0 RW Sets the lower bound for EBI_A enabling
Sets the lower bound of the EBI_A lines which can be enabled in the APEN field.
Value Mode Description
0 A0 Address lines from EBI_A[0] and upwards can be enabled via APEN.
1 A8 Address lines from EBI_A[8] and upwards can be enabled via APEN.
2 A16 Address lines from EBI_A[16] and upwards can be enabled via APEN.
3 A24 Address lines from EBI_A[24] and upwards can be enabled via APEN.
15:13 Reserved To ensure compatibility with future devices, always write bits to 0. More information in 2.1 Conven-
tions.
12 NANDPEN 0 RW NANDRE and NANDWE Pin Enable
When set, the NANDREn and NANDWEn Pin pins are enabled
11:8 Reserved To ensure compatibility with future devices, always write bits to 0. More information in 2.1 Conven-
tions.
7 BLPEN 0 RW EBI_BL[1:0] Pin Enable
When set, the EBI_BL[1:0] pins are enabled
6 ARDYPEN 0 RW EBI_ARDY Pin Enable
When set, the EBI_ARDY pin is enabled
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Bit Name Reset Access Description
5 ALEPEN 0 RW EBI_ALE Pin Enable
When set, the EBI_ALE pin is enabled
4 CS3PEN 0 RW EBI_CS3 Pin Enable
When set, the EBI_CS3 pin is enabled
3 CS2PEN 0 RW EBI_CS2 Pin Enable
When set, the EBI_CS2 pin is enabled
2 CS1PEN 0 RW EBI_CS1 Pin Enable
When set, the EBI_CS1 pin is enabled
1 CS0PEN 0 RW EBI_CS0 Pin Enable
When set, the EBI_CS0 pin is enabled
0 EBIPEN 0 RW EBI Pin Enable
When set, the EBI_AD[15:0], EBI_WEn and EBI_REn pins are enabled
14.5.7 EBI_ADDRTIMING1 - Address Timing Register 1
Offset Bit Position
0x018
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
16
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
Reset
0
0x3
0x3
Access
RW
RW
RW
Name
HALFALE
ADDRHOLD
ADDRSETUP
Bit Name Reset Access Description
31:29 Reserved To ensure compatibility with future devices, always write bits to 0. More information in 2.1 Conven-
tions.
28 HALFALE 0 RW Half Cycle ALE Strobe Duration Enable
Enables or disables half cycle duration of the ALE strobe in the last address setup cycle.
27:10 Reserved To ensure compatibility with future devices, always write bits to 0. More information in 2.1 Conven-
tions.
9:8 ADDRHOLD 0x3 RW Address Hold Time
Sets the number of cycles the address is held after ALE is asserted.
7:2 Reserved To ensure compatibility with future devices, always write bits to 0. More information in 2.1 Conven-
tions.
1:0 ADDRSETUP 0x3 RW Address Setup Time
Sets the number of cycles the address is driven onto the ADDRDAT bus before ALE is asserted. If set to 0, 1 cycle is inser-
ted by HW.
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14.5.8 EBI_RDTIMING1 - Read Timing Register 1
Offset Bit Position
0x01C
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
16
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
Reset
0
0
0
0x3
0x3F
0x3
Access
RW
RW
RW
RW
RW
RW
Name
PAGEMODE
PREFETCH
HALFRE
RDHOLD
RDSTRB
RDSETUP
Bit Name Reset Access Description
31 Reserved To ensure compatibility with future devices, always write bits to 0. More information in 2.1 Conven-
tions.
30 PAGEMODE 0 RW Page Mode Access Enable
Enables or disables page mode reads.
29 PREFETCH 0 RW Prefetch Enable
Enables or disables prefetching of data from sequential address.
28 HALFRE 0 RW Half Cycle REn Strobe Duration Enable
Enables or disables half cycle duration of the REn strobe in the last RDSTRB cycle.
27:18 Reserved To ensure compatibility with future devices, always write bits to 0. More information in 2.1 Conven-
tions.
17:16 RDHOLD 0x3 RW Read Hold Time
Sets the number of cycles CSn is held active after the REn is deasserted. This interval is used for bus turnaround.
15:14 Reserved To ensure compatibility with future devices, always write bits to 0. More information in 2.1 Conven-
tions.
13:8 RDSTRB 0x3F RW Read Strobe Time
Sets the number of cycles the REn is held active. After the specified number of cycles, data is read. If set to 0, 1 cycle is
inserted by HW.
7:2 Reserved To ensure compatibility with future devices, always write bits to 0. More information in 2.1 Conven-
tions.
1:0 RDSETUP 0x3 RW Read Setup Time
Sets the number of cycles the address setup before REn is asserted.
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14.5.9 EBI_WRTIMING1 - Write Timing Register 1
Offset Bit Position
0x020
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
16
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
Reset
0
0
0x3
0x3F
0x3
Access
RW
RW
RW
RW
RW
Name
WBUFDIS
HALFWE
WRHOLD
WRSTRB
WRSETUP
Bit Name Reset Access Description
31:30 Reserved To ensure compatibility with future devices, always write bits to 0. More information in 2.1 Conven-
tions.
29 WBUFDIS 0 RW Write Buffer Disable
Enables or disables the write buffer.
28 HALFWE 0 RW Half Cycle WEn Strobe Duration Enable
Enables or disables half cycle duration of the WEn strobe in the last WRSTRB cycle.
27:18 Reserved To ensure compatibility with future devices, always write bits to 0. More information in 2.1 Conven-
tions.
17:16 WRHOLD 0x3 RW Write Hold Time
Sets the number of cycles CSn is held active after the WEn is deasserted.
15:14 Reserved To ensure compatibility with future devices, always write bits to 0. More information in 2.1 Conven-
tions.
13:8 WRSTRB 0x3F RW Write Strobe Time
Sets the number of cycles the WEn is held active. If set to 0, 1 cycle is inserted by HW.
7:2 Reserved To ensure compatibility with future devices, always write bits to 0. More information in 2.1 Conven-
tions.
1:0 WRSETUP 0x3 RW Write Setup Time
Sets the number of cycles the address setup before WEn is asserted.
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14.5.10 EBI_POLARITY1 - Polarity Register 1
Offset Bit Position
0x024
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
16
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
Reset
0
0
0
0
0
0
Access
RW
RW
RW
RW
RW
RW
Name
BLPOL
ARDYPOL
ALEPOL
WEPOL
REPOL
CSPOL
Bit Name Reset Access Description
31:6 Reserved To ensure compatibility with future devices, always write bits to 0. More information in 2.1 Conven-
tions.
5 BLPOL 0 RW BL Polarity
Sets the polarity of the EBI_BLn lines.
Value Mode Description
0 ACTIVELOW BLn[1:0] are active low.
1 ACTIVEHIGH BLn[1:0] are active high.
4 ARDYPOL 0 RW ARDY Polarity
Sets the polarity of the EBI_ARDY line.
Value Mode Description
0 ACTIVELOW ARDY is active low.
1 ACTIVEHIGH ARDY is active high.
3 ALEPOL 0 RW Address Latch Polarity
Sets the polarity of the EBI_ALE line.
Value Mode Description
0 ACTIVELOW ALE is active low.
1 ACTIVEHIGH ALE is active high.
2 WEPOL 0 RW Write Enable Polarity
Sets the polarity of the EBI_WEn and EBI_NANDWEn lines.
Value Mode Description
0 ACTIVELOW WEn and NANDWEn are active low.
1 ACTIVEHIGH WEn and NANDWEn are active high.
1 REPOL 0 RW Read Enable Polarity
Sets the polarity of the EBI_REn and EBI_NANDREn lines.
Value Mode Description
0 ACTIVELOW REn and NANDREn are active low.
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Bit Name Reset Access Description
1 ACTIVEHIGH REn and NANDREn are active high.
0 CSPOL 0 RW Chip Select Polarity
Sets the polarity of the EBI_CSn line.
Value Mode Description
0 ACTIVELOW CSn is active low.
1 ACTIVEHIGH CSn is active high.
14.5.11 EBI_ADDRTIMING2 - Address Timing Register 2
Offset Bit Position
0x028
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
16
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
Reset
0
0x3
0x3
Access
RW
RW
RW
Name
HALFALE
ADDRHOLD
ADDRSETUP
Bit Name Reset Access Description
31:29 Reserved To ensure compatibility with future devices, always write bits to 0. More information in 2.1 Conven-
tions.
28 HALFALE 0 RW Half Cycle ALE Strobe Duration Enable
Enables or disables half cycle duration of the ALE strobe in the last address setup cycle.
27:10 Reserved To ensure compatibility with future devices, always write bits to 0. More information in 2.1 Conven-
tions.
9:8 ADDRHOLD 0x3 RW Address Hold Time
Sets the number of cycles the address is held after ALE is asserted.
7:2 Reserved To ensure compatibility with future devices, always write bits to 0. More information in 2.1 Conven-
tions.
1:0 ADDRSETUP 0x3 RW Address Setup Time
Sets the number of cycles the address is driven onto the ADDRDAT bus before ALE is asserted. If set to 0, 1 cycle is inser-
ted by HW.
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14.5.12 EBI_RDTIMING2 - Read Timing Register 2
Offset Bit Position
0x02C
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
16
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
Reset
0
0
0
0x3
0x3F
0x3
Access
RW
RW
RW
RW
RW
RW
Name
PAGEMODE
PREFETCH
HALFRE
RDHOLD
RDSTRB
RDSETUP
Bit Name Reset Access Description
31 Reserved To ensure compatibility with future devices, always write bits to 0. More information in 2.1 Conven-
tions.
30 PAGEMODE 0 RW Page Mode Access Enable
Enables or disables page mode reads.
29 PREFETCH 0 RW Prefetch Enable
Enables or disables prefetching of data from sequential address.
28 HALFRE 0 RW Half Cycle REn Strobe Duration Enable
Enables or disables half cycle duration of the REn strobe in the last RDSTRB cycle.
27:18 Reserved To ensure compatibility with future devices, always write bits to 0. More information in 2.1 Conven-
tions.
17:16 RDHOLD 0x3 RW Read Hold Time
Sets the number of cycles CSn is held active after the REn is deasserted. This interval is used for bus turnaround.
15:14 Reserved To ensure compatibility with future devices, always write bits to 0. More information in 2.1 Conven-
tions.
13:8 RDSTRB 0x3F RW Read Strobe Time
Sets the number of cycles the REn is held active. After the specified number of cycles, data is read. If set to 0, 1 cycle is
inserted by HW.
7:2 Reserved To ensure compatibility with future devices, always write bits to 0. More information in 2.1 Conven-
tions.
1:0 RDSETUP 0x3 RW Read Setup Time
Sets the number of cycles the address setup before REn is asserted.
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14.5.13 EBI_WRTIMING2 - Write Timing Register 2
Offset Bit Position
0x030
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
16
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
Reset
0
0
0x3
0x3F
0x3
Access
RW
RW
RW
RW
RW
Name
WBUFDIS
HALFWE
WRHOLD
WRSTRB
WRSETUP
Bit Name Reset Access Description
31:30 Reserved To ensure compatibility with future devices, always write bits to 0. More information in 2.1 Conven-
tions.
29 WBUFDIS 0 RW Write Buffer Disable
Enables or disables the write buffer.
28 HALFWE 0 RW Half Cycle WEn Strobe Duration Enable
Enables or disables half cycle duration of the WEn strobe in the last WRSTRB cycle.
27:18 Reserved To ensure compatibility with future devices, always write bits to 0. More information in 2.1 Conven-
tions.
17:16 WRHOLD 0x3 RW Write Hold Time
Sets the number of cycles CSn is held active after the WEn is deasserted.
15:14 Reserved To ensure compatibility with future devices, always write bits to 0. More information in 2.1 Conven-
tions.
13:8 WRSTRB 0x3F RW Write Strobe Time
Sets the number of cycles the WEn is held active. If set to 0, 1 cycle is inserted by HW.
7:2 Reserved To ensure compatibility with future devices, always write bits to 0. More information in 2.1 Conven-
tions.
1:0 WRSETUP 0x3 RW Write Setup Time
Sets the number of cycles the address setup before WEn is asserted.
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14.5.14 EBI_POLARITY2 - Polarity Register 2
Offset Bit Position
0x034
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
16
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
Reset
0
0
0
0
0
0
Access
RW
RW
RW
RW
RW
RW
Name
BLPOL
ARDYPOL
ALEPOL
WEPOL
REPOL
CSPOL
Bit Name Reset Access Description
31:6 Reserved To ensure compatibility with future devices, always write bits to 0. More information in 2.1 Conven-
tions.
5 BLPOL 0 RW BL Polarity
Sets the polarity of the EBI_BLn lines.
Value Mode Description
0 ACTIVELOW BLn[1:0] are active low.
1 ACTIVEHIGH BLn[1:0] are active high.
4 ARDYPOL 0 RW ARDY Polarity
Sets the polarity of the EBI_ARDY line.
Value Mode Description
0 ACTIVELOW ARDY is active low.
1 ACTIVEHIGH ARDY is active high.
3 ALEPOL 0 RW Address Latch Polarity
Sets the polarity of the EBI_ALE line.
Value Mode Description
0 ACTIVELOW ALE is active low.
1 ACTIVEHIGH ALE is active high.
2 WEPOL 0 RW Write Enable Polarity
Sets the polarity of the EBI_WEn and EBI_NANDWEn lines.
Value Mode Description
0 ACTIVELOW WEn and NANDWEn are active low.
1 ACTIVEHIGH WEn and NANDWEn are active high.
1 REPOL 0 RW Read Enable Polarity
Sets the polarity of the EBI_REn and EBI_NANDREn lines.
Value Mode Description
0 ACTIVELOW REn and NANDREn are active low.
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Bit Name Reset Access Description
1 ACTIVEHIGH REn and NANDREn are active high.
0 CSPOL 0 RW Chip Select Polarity
Sets the polarity of the EBI_CSn line.
Value Mode Description
0 ACTIVELOW CSn is active low.
1 ACTIVEHIGH CSn is active high.
14.5.15 EBI_ADDRTIMING3 - Address Timing Register 3
Offset Bit Position
0x038
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
16
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
Reset
0
0x3
0x3
Access
RW
RW
RW
Name
HALFALE
ADDRHOLD
ADDRSETUP
Bit Name Reset Access Description
31:29 Reserved To ensure compatibility with future devices, always write bits to 0. More information in 2.1 Conven-
tions.
28 HALFALE 0 RW Half Cycle ALE Strobe Duration Enable
Enables or disables half cycle duration of the ALE strobe in the last address setup cycle.
27:10 Reserved To ensure compatibility with future devices, always write bits to 0. More information in 2.1 Conven-
tions.
9:8 ADDRHOLD 0x3 RW Address Hold Time
Sets the number of cycles the address is held after ALE is asserted.
7:2 Reserved To ensure compatibility with future devices, always write bits to 0. More information in 2.1 Conven-
tions.
1:0 ADDRSETUP 0x3 RW Address Setup Time
Sets the number of cycles the address is driven onto the ADDRDAT bus before ALE is asserted. If set to 0, 1 cycle is inser-
ted by HW.
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14.5.16 EBI_RDTIMING3 - Read Timing Register 3
Offset Bit Position
0x03C
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
16
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
Reset
0
0
0
0x3
0x3F
0x3
Access
RW
RW
RW
RW
RW
RW
Name
PAGEMODE
PREFETCH
HALFRE
RDHOLD
RDSTRB
RDSETUP
Bit Name Reset Access Description
31 Reserved To ensure compatibility with future devices, always write bits to 0. More information in 2.1 Conven-
tions.
30 PAGEMODE 0 RW Page Mode Access Enable
Enables or disables page mode reads.
29 PREFETCH 0 RW Prefetch Enable
Enables or disables prefetching of data from sequential address.
28 HALFRE 0 RW Half Cycle REn Strobe Duration Enable
Enables or disables half cycle duration of the REn strobe in the last RDSTRB cycle.
27:18 Reserved To ensure compatibility with future devices, always write bits to 0. More information in 2.1 Conven-
tions.
17:16 RDHOLD 0x3 RW Read Hold Time
Sets the number of cycles CSn is held active after the REn is deasserted. This interval is used for bus turnaround.
15:14 Reserved To ensure compatibility with future devices, always write bits to 0. More information in 2.1 Conven-
tions.
13:8 RDSTRB 0x3F RW Read Strobe Time
Sets the number of cycles the REn is held active. After the specified number of cycles, data is read. If set to 0, 1 cycle is
inserted by HW.
7:2 Reserved To ensure compatibility with future devices, always write bits to 0. More information in 2.1 Conven-
tions.
1:0 RDSETUP 0x3 RW Read Setup Time
Sets the number of cycles the address setup before REn is asserted.
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14.5.17 EBI_WRTIMING3 - Write Timing Register 3
Offset Bit Position
0x040
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
16
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
Reset
0
0
0x3
0x3F
0x3
Access
RW
RW
RW
RW
RW
Name
WBUFDIS
HALFWE
WRHOLD
WRSTRB
WRSETUP
Bit Name Reset Access Description
31:30 Reserved To ensure compatibility with future devices, always write bits to 0. More information in 2.1 Conven-
tions.
29 WBUFDIS 0 RW Write Buffer Disable
Enables or disables the write buffer.
28 HALFWE 0 RW Half Cycle WEn Strobe Duration Enable
Enables or disables half cycle duration of the WEn strobe in the last WRSTRB cycle.
27:18 Reserved To ensure compatibility with future devices, always write bits to 0. More information in 2.1 Conven-
tions.
17:16 WRHOLD 0x3 RW Write Hold Time
Sets the number of cycles CSn is held active after the WEn is deasserted.
15:14 Reserved To ensure compatibility with future devices, always write bits to 0. More information in 2.1 Conven-
tions.
13:8 WRSTRB 0x3F RW Write Strobe Time
Sets the number of cycles the WEn is held active. If set to 0, 1 cycle is inserted by HW.
7:2 Reserved To ensure compatibility with future devices, always write bits to 0. More information in 2.1 Conven-
tions.
1:0 WRSETUP 0x3 RW Write Setup Time
Sets the number of cycles the address setup before WEn is asserted.
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14.5.18 EBI_POLARITY3 - Polarity Register 3
Offset Bit Position
0x044
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
16
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
Reset
0
0
0
0
0
0
Access
RW
RW
RW
RW
RW
RW
Name
BLPOL
ARDYPOL
ALEPOL
WEPOL
REPOL
CSPOL
Bit Name Reset Access Description
31:6 Reserved To ensure compatibility with future devices, always write bits to 0. More information in 2.1 Conven-
tions.
5 BLPOL 0 RW BL Polarity
Sets the polarity of the EBI_BLn lines.
Value Mode Description
0 ACTIVELOW BLn[1:0] are active low.
1 ACTIVEHIGH BLn[1:0] are active high.
4 ARDYPOL 0 RW ARDY Polarity
Sets the polarity of the EBI_ARDY line.
Value Mode Description
0 ACTIVELOW ARDY is active low.
1 ACTIVEHIGH ARDY is active high.
3 ALEPOL 0 RW Address Latch Polarity
Sets the polarity of the EBI_ALE line.
Value Mode Description
0 ACTIVELOW ALE is active low.
1 ACTIVEHIGH ALE is active high.
2 WEPOL 0 RW Write Enable Polarity
Sets the polarity of the EBI_WEn and EBI_NANDWEn lines.
Value Mode Description
0 ACTIVELOW WEn and NANDWEn are active low.
1 ACTIVEHIGH WEn and NANDWEn are active high.
1 REPOL 0 RW Read Enable Polarity
Sets the polarity of the EBI_REn and EBI_NANDREn lines.
Value Mode Description
0 ACTIVELOW REn and NANDREn are active low.
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Bit Name Reset Access Description
1 ACTIVEHIGH REn and NANDREn are active high.
0 CSPOL 0 RW Chip Select Polarity
Sets the polarity of the EBI_CSn line.
Value Mode Description
0 ACTIVELOW CSn is active low.
1 ACTIVEHIGH CSn is active high.
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14.5.19 EBI_PAGECTRL - Page Control Register
Offset Bit Position
0x048
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
16
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
Reset
0x00
0x7
0
0x0
Access
RW
RW
RW
RW
Name
KEEPOPEN
RDPA
INCHIT
PAGELEN
Bit Name Reset Access Description
31:27 Reserved To ensure compatibility with future devices, always write bits to 0. More information in 2.1 Conven-
tions.
26:20 KEEPOPEN 0x00 RW Maximum Page Open Time.
Sets the maximum number of consecutive cycles a page can be considered open. Needs to be larger than 0 in order to be
able to benefit from RDPA timing.
19:11 Reserved To ensure compatibility with future devices, always write bits to 0. More information in 2.1 Conven-
tions.
10:8 RDPA 0x7 RW Page Read Access Time
Sets the number of cycles needed for intrapage page access time. If set to 0, 1 cycle is inserted by HW.
7:5 Reserved To ensure compatibility with future devices, always write bits to 0. More information in 2.1 Conven-
tions.
4 INCHIT 0 RW Intrapage hit only on incremental addresses
Sets whether page hits occur on any member in a page or only on incremental addresses.
3:2 Reserved To ensure compatibility with future devices, always write bits to 0. More information in 2.1 Conven-
tions.
1:0 PAGELEN 0x0 RW Page Length
Sets the page length.
Value Mode Description
0 MEMBER4 4 members in a page.
1 MEMBER8 8 members in a page.
2 MEMBER16 16 members in a page.
3 MEMBER32 32 members in a page.
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14.5.20 EBI_NANDCTRL - NAND Control Register
Offset Bit Position
0x04C
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
16
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
Reset
0x0
0
Access
RW
RW
Name
BANKSEL
EN
Bit Name Reset Access Description
31:6 Reserved To ensure compatibility with future devices, always write bits to 0. More information in 2.1 Conven-
tions.
5:4 BANKSEL 0x0 RW NAND Flash Bank
This field sets the Memory Bank which is connected to a NAND Flash device
Value Mode Description
0 BANK0 Memory bank 0 is connected to a NAND Flash device.
1 BANK1 Memory bank 1 is connected to a NAND Flash device.
2 BANK2 Memory bank 2 is connected to a NAND Flash device.
3 BANK3 Memory bank 3 is connected to a NAND Flash device.
3:1 Reserved To ensure compatibility with future devices, always write bits to 0. More information in 2.1 Conven-
tions.
0 EN 0 RW NAND Flash control enable
This field enables NAND Flash control for the memory bank defined in BANK.
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14.5.21 EBI_CMD - Command Register
Offset Bit Position
0x050
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
16
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
Reset
0
0
0
Access
W1
W1
W1
Name
ECCCLEAR
ECCSTOP
ECCSTART
Bit Name Reset Access Description
31:3 Reserved To ensure compatibility with future devices, always write bits to 0. More information in 2.1 Conven-
tions.
2 ECCCLEAR 0 W1 Error Correction Code Clear
Write to 1 to clear ECCPARITY.
1 ECCSTOP 0 W1 Error Correction Code Generation Stop
Write to 1 to stop ECC generation.
0 ECCSTART 0 W1 Error Correction Code Generation Start
Write to 1 to start ECC generation.
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14.5.22 EBI_STATUS - Status Register
Offset Bit Position
0x054
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
16
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
Reset
0
0
0
0
0
0
0
Access
R
R
R
R
R
R
R
Name
TFTDDEMPTY
DDACT
TFTPIXELFULL
TFTPIXEL1EMPTY
TFTPIXEL0EMPTY
ECCACT
AHBACT
Bit Name Reset Access Description
31:14 Reserved To ensure compatibility with future devices, always write bits to 0. More information in 2.1 Conven-
tions.
13 TFTDDEMPTY 0 R EBI_TFTDD register is empty.
Indicates that EBI_TFTDD register is empty.
12 DDACT 0 R EBI Busy with Direct Drive Transactions.
Indicates that EBI is busy with Direct Drive Transactions.
11 Reserved To ensure compatibility with future devices, always write bits to 0. More information in 2.1 Conven-
tions.
10 TFTPIXELFULL 0 R EBI_TFTPIXEL0 is full.
Indicates that EBI_TFTPIXEL is full.
9 TFTPIXEL1EMPTY 0 R EBI_TFTPIXEL1 is empty.
Indicates that EBI_TFTPIXEL1 is empty.
8 TFTPIXEL0EMPTY 0 R EBI_TFTPIXEL0 is empty.
Indicates that EBI_TFTPIXEL0 is empty.
7:5 Reserved To ensure compatibility with future devices, always write bits to 0. More information in 2.1 Conven-
tions.
4 ECCACT 0 R EBI ECC Generation Active.
Indicates that EBI is generating ECC.
3:1 Reserved To ensure compatibility with future devices, always write bits to 0. More information in 2.1 Conven-
tions.
0 AHBACT 0 R EBI Busy with AHB Transaction.
Indicates that EBI is busy with an AHB Transaction.
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14.5.23 EBI_ECCPARITY - ECC Parity register
Offset Bit Position
0x058
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
16
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
Reset
0x00000000
Access
R
Name
ECCPARITY
Bit Name Reset Access Description
31:0 ECCPARITY 0x00000000 R ECC Parity Data
ECC Parity Data.
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14.5.24 EBI_TFTCTRL - TFT Control Register
Offset Bit Position
0x05C
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
16
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
Reset
0
0x0
0
0
0x0
0
0
0x0
0x0
Access
RW
RW
RW
RW
RW
RW
RW
RW
RW
Name
RGBMODE
BANKSEL
WIDTH
COLOR1SRC
INTERLEAVE
FBCTRIG
SHIFTDCLKEN
MASKBLEND
DD
Bit Name Reset Access Description
31:25 Reserved To ensure compatibility with future devices, always write bits to 0. More information in 2.1 Conven-
tions.
24 RGBMODE 0 RW TFT RGB Mode
This field sets TFT RGB Mode.
Value Mode Description
0 RGB565 RGB data is 565.
1 RGB555 RGB data is 555.
23:22 Reserved To ensure compatibility with future devices, always write bits to 0. More information in 2.1 Conven-
tions.
21:20 BANKSEL 0x0 RW Graphics Bank
This field sets the Memory Bank containing the Frame Buffer
Value Mode Description
0 BANK0 Memory bank 0 is used for Direct Drive, Masking, and Alpha Blending.
1 BANK1 Memory bank 1 is used for Direct Drive, Masking, and Alpha Blending.
2 BANK2 Memory bank 2 is used for Direct Drive, Masking, and Alpha Blending.
3 BANK3 Memory bank 3 is used for Direct Drive, Masking, and Alpha Blending.
19:17 Reserved To ensure compatibility with future devices, always write bits to 0. More information in 2.1 Conven-
tions.
16 WIDTH 0 RW TFT Transaction Width
This field sets TFT tranaction width.
Value Mode Description
0 BYTE TFT Data is 8 bit wide.
1 HALFWORD TFT Data is 16 bit wide.
15:13 Reserved To ensure compatibility with future devices, always write bits to 0. More information in 2.1 Conven-
tions.
12 COLOR1SRC 0 RW Masking/Alpha Blending Color1 Source
This field sets the Masking/Alpha Blending Color1 Source.
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Bit Name Reset Access Description
Value Mode Description
0 MEM Masking/Alpha Blending color 1 is read from external memory.
1 PIXEL1 Masking/Alpha Blending color 1 is read from EBI_TFTPIXEL1.
11:10 INTERLEAVE 0x0 RW Interleave Mode
This field sets the TFT Direct Drive Interleave mode.
Value Mode Description
0 UNLIMITED Allow unlimited interleaved EBI accesses per EBI_DCLK period. This
can cause jitter on the EBI_DCLK
1 ONEPERDCLK Allow 1 interleaved EBI access per EBI_DCLK period.
2 PORCH Only allow EBI accesses during TFT porches.
9 FBCTRIG 0 RW TFT Frame Base Copy Trigger
Sets the trigger on which the TFTFRAMEBASE is copied into an internal buffer. Direct Drive address generation is based
on the internal buffer.
Value Mode Description
0 VSYNC TFTFRAMEBASE is buffered on the vertical synchronization event
EBI_VSYNC.
1 HSYNC TFTFRAMEBASE is buffered on the horizontal synchronization event
EBI_HSYNC.
8 SHIFTDCLKEN 0 RW TFT EBI_DCLK Shift Enable
When this bit is set, EBI_DCLK edges are driven off the negative (instead of the positive) edge of the internal clock.
SHIFTDCLKEN is only allowed to be set to 1 if TFTHOLD in EBI_TFTTIMING is at least 1.
7:5 Reserved To ensure compatibility with future devices, always write bits to 0. More information in 2.1 Conven-
tions.
4:2 MASKBLEND 0x0 RW TFT Mask and Blend Mode
This field sets the Mask and Blend Mode.
Value Mode Description
0 DISABLED Masking and Blending are disabled.
1 IMASK Internal Masking is enabled.
2 IALPHA Internal Alpha Blending is enabled.
3 IMASKIALPHA Internal Masking and Alpha Blending are enabled.
5 EMASK External Masking is enabled.
6 EALPHA External Alpha Blending is enabled.
7 EMASKEALPHA External Masking and Alpha Blending are enabled.
1:0 DD 0x0 RW TFT Direct Drive Mode
This field sets the Direct Mode.
Value Mode Description
0 DISABLED Direct Drive is disabled.
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Bit Name Reset Access Description
1 INTERNAL Direct Drive from internal memory enabled and started.
2 EXTERNAL Direct Drive from external memory enabled and started.
14.5.25 EBI_TFTSTATUS - TFT Status Register
Offset Bit Position
0x060
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
16
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
Reset
0x000
0x000
Access
R
R
Name
VCNT
HCNT
Bit Name Reset Access Description
31:27 Reserved To ensure compatibility with future devices, always write bits to 0. More information in 2.1 Conven-
tions.
26:16 VCNT 0x000 R Vertical Count
Contains the current line position within a frame (initial line in vertical back porch has VCNT = 0).
15:11 Reserved To ensure compatibility with future devices, always write bits to 0. More information in 2.1 Conven-
tions.
10:0 HCNT 0x000 R Horizontal Count
Contains the current pixel position within a line (initial pixel in horizontal backporch has HCNT = 0).
14.5.26 EBI_TFTFRAMEBASE - TFT Frame Base Register
Offset Bit Position
0x064
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
16
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
Reset
0x0000000
Access
RW
Name
FRAMEBASE
Bit Name Reset Access Description
31:28 Reserved To ensure compatibility with future devices, always write bits to 0. More information in 2.1 Conven-
tions.
27:0 FRAMEBASE 0x0000000 RW Frame Base Address
Sets the frame base address.
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14.5.27 EBI_TFTSTRIDE - TFT Stride Register
Offset Bit Position
0x068
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
16
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
Reset
0x000
Access
RW
Name
HSTRIDE
Bit Name Reset Access Description
31:12 Reserved To ensure compatibility with future devices, always write bits to 0. More information in 2.1 Conven-
tions.
11:0 HSTRIDE 0x000 RW Horizontal Stride
Sets the horizontal stride added to the Direct Drive address at the end of each line.
14.5.28 EBI_TFTSIZE - TFT Size Register
Offset Bit Position
0x06C
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
16
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
Reset
0x000
0x000
Access
RW
RW
Name
VSZ
HSZ
Bit Name Reset Access Description
31:26 Reserved To ensure compatibility with future devices, always write bits to 0. More information in 2.1 Conven-
tions.
25:16 VSZ 0x000 RW Vertical Size (excluding porches)
Sets the vertical size in lines. Set to required size minus 1.
15:10 Reserved To ensure compatibility with future devices, always write bits to 0. More information in 2.1 Conven-
tions.
9:0 HSZ 0x000 RW Horizontal Size (excluding porches)
Sets the horizontal size in pixels. Set to required size minus 1.
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14.5.29 EBI_TFTHPORCH - TFT Horizontal Porch Register
Offset Bit Position
0x070
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
16
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
Reset
0x0
0x00
0x00
0x00
Access
RW
RW
RW
RW
Name
HSYNCSTART
HBPORCH
HFPORCH
HSYNC
Bit Name Reset Access Description
31:30 Reserved To ensure compatibility with future devices, always write bits to 0. More information in 2.1 Conven-
tions.
29:28 HSYNCSTART 0x0 RW HSYNC Start Delay
Sets the HSYNC start position into the horizontal back porch in DCLK cycles.
27:26 Reserved To ensure compatibility with future devices, always write bits to 0. More information in 2.1 Conven-
tions.
25:18 HBPORCH 0x00 RW Horizontal Back Porch Size
Sets the horizontal back porch size in pixels.
17:16 Reserved To ensure compatibility with future devices, always write bits to 0. More information in 2.1 Conven-
tions.
15:8 HFPORCH 0x00 RW Horizontal Front Porch Size
Sets the horizontal front porch size in pixels.
7 Reserved To ensure compatibility with future devices, always write bits to 0. More information in 2.1 Conven-
tions.
6:0 HSYNC 0x00 RW Horizontal Synchronization Pulse Width
Sets the horizontal synchronization pulse width. Set to required width minus 1. Width is reduced in case HSYNCSTART >
0.
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14.5.30 EBI_TFTVPORCH - TFT Vertical Porch Register
Offset Bit Position
0x074
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
16
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
Reset
0x00
0x00
0x00
Access
RW
RW
RW
Name
VBPORCH
VFPORCH
VSYNC
Bit Name Reset Access Description
31:26 Reserved To ensure compatibility with future devices, always write bits to 0. More information in 2.1 Conven-
tions.
25:18 VBPORCH 0x00 RW Vertical Back Porch Size
Sets the Vertical back porch size in pixels.
17:16 Reserved To ensure compatibility with future devices, always write bits to 0. More information in 2.1 Conven-
tions.
15:8 VFPORCH 0x00 RW Vertical Front Porch Size
Sets the Vertical front porch size in pixels.
7 Reserved To ensure compatibility with future devices, always write bits to 0. More information in 2.1 Conven-
tions.
6:0 VSYNC 0x00 RW Vertical Synchronization Pulse Width
Sets the Vertical synchronization pulse width. Set to required width minus 1.
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14.5.31 EBI_TFTTIMING - TFT Timing Register
Offset Bit Position
0x078
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
16
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
Reset
0x0
0x0
0x000
0x000
Access
RW
RW
RW
RW
Name
TFTHOLD
TFTSETUP
TFTSTART
DCLKPERIOD
Bit Name Reset Access Description
31:30 Reserved To ensure compatibility with future devices, always write bits to 0. More information in 2.1 Conven-
tions.
29:28 TFTHOLD 0x0 RW TFT Hold Time
Sets the number of internal clock cycles the RGB data is held after the active edge of EBI_DCLK.
27:26 Reserved To ensure compatibility with future devices, always write bits to 0. More information in 2.1 Conven-
tions.
25:24 TFTSETUP 0x0 RW TFT Setup Time
Sets the number of internal clock cycles the RGB data is driven before the active edge of EBI_DCLK.
23 Reserved To ensure compatibility with future devices, always write bits to 0. More information in 2.1 Conven-
tions.
22:12 TFTSTART 0x000 RW TFT Direct Drive Transaction Start
Sets the starting position of the External Direct Drive Transaction relative to the DCLK inactive edge.
11 Reserved To ensure compatibility with future devices, always write bits to 0. More information in 2.1 Conven-
tions.
10:0 DCLKPERIOD 0x000 RW TFT Direct Drive Transaction (EBI_DCLK) Period
Sets the Direct Drive transaction (EBI_DCLK) period in internal cycles. Set to required cycle count minus 1.
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14.5.32 EBI_TFTPOLARITY - TFT Polarity Register
Offset Bit Position
0x07C
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
16
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
Reset
0
0
0
0
0
Access
RW
RW
RW
RW
RW
Name
VSYNCPOL
HSYNCPOL
DATAENPOL
DCLKPOL
CSPOL
Bit Name Reset Access Description
31:5 Reserved To ensure compatibility with future devices, always write bits to 0. More information in 2.1 Conven-
tions.
4 VSYNCPOL 0 RW VSYNC Polarity
Sets the polarity of the EBI_VSYNC line.
Value Mode Description
0 ACTIVELOW VSYNC is active low.
1 ACTIVEHIGH VSYNC is active high.
3 HSYNCPOL 0 RW Address Latch Polarity
Sets the polarity of the EBI_HSYNC line.
Value Mode Description
0 ACTIVELOW HSYNC is active low.
1 ACTIVEHIGH HSYNC is active high.
2 DATAENPOL 0 RW TFT DATAEN Polarity
Sets the polarity of the EBI_DATAEN line.
Value Mode Description
0 ACTIVELOW DATAEN is active low.
1 ACTIVEHIGH DATAEN is active high.
1 DCLKPOL 0 RW TFT DCLK Polarity
Sets the active edge polarity of the EBI_DCLK line.
Value Mode Description
0 ACTIVEFALLING DCLK falling edge is the active edge.
1 ACTIVERISING DCLK rising edge the active edge.
0 CSPOL 0 RW TFT Chip Select Polarity
Sets the polarity of the EBI_CSTFT line.
Value Mode Description
0 ACTIVELOW CSTFT is active low.
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Bit Name Reset Access Description
1 ACTIVEHIGH CSTFT is active high.
14.5.33 EBI_TFTDD - TFT Direct Drive Data Register
Offset Bit Position
0x080
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
16
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
Reset
0x0000
Access
RW
Name
DATA
Bit Name Reset Access Description
31:16 Reserved To ensure compatibility with future devices, always write bits to 0. More information in 2.1 Conven-
tions.
15:0 DATA 0x0000 RW TFT Direct Drive Data from Internal Memory
Sets the RGB value used when Direct Drive from internal memory is used (DD = INTERNAL)
14.5.34 EBI_TFTALPHA - TFT Alpha Blending Register
Offset Bit Position
0x084
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
16
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
Reset
0x000
Access
RW
Name
ALPHA
Bit Name Reset Access Description
31:9 Reserved To ensure compatibility with future devices, always write bits to 0. More information in 2.1 Conven-
tions.
8:0 ALPHA 0x000 RW TFT Alpha Blending Factor
Sets the alpha blending factor. The maximum value is 256.
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14.5.35 EBI_TFTPIXEL0 - TFT Pixel 0 Register
Offset Bit Position
0x088
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
16
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
Reset
0x0000
Access
RW
Name
DATA
Bit Name Reset Access Description
31:16 Reserved To ensure compatibility with future devices, always write bits to 0. More information in 2.1 Conven-
tions.
15:0 DATA 0x0000 RW RGB data.
Sets the RGB data value according to the format defined in RGBMODE.
14.5.36 EBI_TFTPIXEL1 - TFT Pixel 1 Register
Offset Bit Position
0x08C
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
16
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
Reset
0x0000
Access
RW
Name
DATA
Bit Name Reset Access Description
31:16 Reserved To ensure compatibility with future devices, always write bits to 0. More information in 2.1 Conven-
tions.
15:0 DATA 0x0000 RW RGB data.
Sets the RGB data value according to the format defined in RGBMODE.
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14.5.37 EBI_TFTPIXEL - TFT Alpha Blending Result Pixel Register
Offset Bit Position
0x090
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
16
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
Reset
0x0000
Access
R
Name
DATA
Bit Name Reset Access Description
31:16 Reserved To ensure compatibility with future devices, always write bits to 0. More information in 2.1 Conven-
tions.
15:0 DATA 0x0000 R Alpha Blending Result
RGB result of Alpha Blending operation according to the format defined in RGBMODE.
14.5.38 EBI_TFTMASK - TFT Masking Register
Offset Bit Position
0x094
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
16
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
Reset
0x0000
Access
RW
Name
TFTMASK
Bit Name Reset Access Description
31:16 Reserved To ensure compatibility with future devices, always write bits to 0. More information in 2.1 Conven-
tions.
15:0 TFTMASK 0x0000 RW TFT Mask Value
Sets the mask value. Data write transactions matching this value are suppressed.
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14.5.39 EBI_IF - Interrupt Flag Register
Offset Bit Position
0x098
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
16
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
Reset
0
0
0
0
0
0
Access
R
R
R
R
R
R
Name
DDJIT
DDEMPTY
VFPORCH
VBPORCH
HSYNC
VSYNC
Bit Name Reset Access Description
31:6 Reserved To ensure compatibility with future devices, always write bits to 0. More information in 2.1 Conven-
tions.
5 DDJIT 0 R Direct Drive Jitter Interrupt Flag
Set when DCLKPERIOD is not met.
4 DDEMPTY 0 R Direct Drive Data Empty Interrupt Flag
Set when Direct Drive engine EBI_TFTDD data is empty.
3 VFPORCH 0 R Vertical Front Porch Interrupt Flag
Set at beginning of Vertical Front Porch.
2 VBPORCH 0 R Vertical Back Porch Interrupt Flag
Set at end of Vertical Back Porch.
1 HSYNC 0 R Horizontal Sync Interrupt Flag
Set at Horizontal Sync pulse.
0 VSYNC 0 R Vertical Sync Interrupt Flag
Set at Vertical Sync pulse.
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14.5.40 EBI_IFS - Interrupt Flag Set Register
Offset Bit Position
0x09C
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
16
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
Reset
0
0
0
0
0
0
Access
W1
W1
W1
W1
W1
W1
Name
DDJIT
DDEMPTY
VFPORCH
VBPORCH
HSYNC
VSYNC
Bit Name Reset Access Description
31:6 Reserved To ensure compatibility with future devices, always write bits to 0. More information in 2.1 Conven-
tions.
5 DDJIT 0 W1 Direct Drive Jitter Interrupt Flag Set
Write to 1 to set Direct Drive Jitter Interrupt flag.
4 DDEMPTY 0 W1 Direct Drive Data Empty Interrupt Flag Set
Write to 1 to set Direct Drive Data Empty Interrupt flag.
3 VFPORCH 0 W1 Vertical Front Porch Interrupt Flag Set
Write to 1 to set Vertical Front Porch Interrupt flag.
2 VBPORCH 0 W1 Vertical Back Porch Interrupt Flag Set
Write to 1 to set Vertical Back Porch Interrupt flag.
1 HSYNC 0 W1 Horizontal Sync Interrupt Flag Set
Write to 1 to set Horizontal Sync interrupt flag.
0 VSYNC 0 W1 Vertical Sync Interrupt Flag Set
Write to 1 to set Vertical Sync interrupt flag.
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14.5.41 EBI_IFC - Interrupt Flag Clear Register
Offset Bit Position
0x0A0
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
16
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
Reset
0
0
0
0
0
0
Access
(R)W1
(R)W1
(R)W1
(R)W1
(R)W1
(R)W1
Name
DDJIT
DDEMPTY
VFPORCH
VBPORCH
HSYNC
VSYNC
Bit Name Reset Access Description
31:6 Reserved To ensure compatibility with future devices, always write bits to 0. More information in 2.1 Conven-
tions.
5 DDJIT 0 (R)W1 Direct Drive Jitter Interrupt Flag Clear
Write to 1 to clear Direct Drive Jitter Interrupt flag.
4 DDEMPTY 0 (R)W1 Direct Drive Data Empty Interrupt Flag Clear
Write to 1 to clear Direct Drive Data Empty Interrupt flag.
3 VFPORCH 0 (R)W1 Vertical Front Porch Interrupt Flag Clear
Write to 1 to clear Vertical Front Porch interrupt flag.
2 VBPORCH 0 (R)W1 Vertical Back Porch Interrupt Flag Clear
Write to 1 to clear Vertical Back Porch interrupt flag.
1 HSYNC 0 (R)W1 Horizontal Sync Interrupt Flag Clear
Write to 1 to clear Horizontal Sync interrupt flag.
0 VSYNC 0 (R)W1 Vertical Sync Interrupt Flag Clear
Write to 1 to clear Vertical Sync interrupt flag.
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14.5.42 EBI_IEN - Interrupt Enable Register
Offset Bit Position
0x0A4
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
16
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
Reset
0
0
0
0
0
0
Access
RW
RW
RW
RW
RW
RW
Name
DDJIT
DDEMPTY
VFPORCH
VBPORCH
HSYNC
VSYNC
Bit Name Reset Access Description
31:6 Reserved To ensure compatibility with future devices, always write bits to 0. More information in 2.1 Conven-
tions.
5 DDJIT 0 RW Direct Drive Jitter Interrupt Enable
Set to enable interrupt on Direct Drive Jitter Interrupt flag.
4 DDEMPTY 0 RW Direct Drive Data Empty Interrupt Enable
Set to enable interrupt on Direct Drive Data Empty Interrupt flag.
3 VFPORCH 0 RW Vertical Front Porch Interrupt Enable
Set to enable interrupt on beginning of Vertical Front Porch interrupt flag.
2 VBPORCH 0 RW Vertical Back Porch Interrupt Enable
Set to enable interrupt on end of Vertical Back Porch interrupt flag.
1 HSYNC 0 RW Horizontal Sync Interrupt Enable
Set to enable interrupt on Horizontal Sync interrupt flag.
0 VSYNC 0 RW Vertical Sync Interrupt Enable
Set to enable interrupt on Vertical Sync interrupt flag.
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15. USB - Universal Serial Bus Controller
43210
Quick Facts
What?
The USB is a full-speed/low-speed USB 2.0 compli-
ant USB Controller that can be used in OTG Dual
Role Device, Device and Host configurations. The
on-chip 3.3V regulator delivers up to 50 mA and can
also be used to power external components, elimi-
nating the need for an external LDO. The on-chip
regulator allows the system to run from a battery uti-
lizing the full voltage range of the EFM32 still being
compliant with the 3.3V +/- 10% USB voltage range.
Why?
USB provides a robust, industry-standard way to in-
terface PCs and other portable devices.
How?
The flexible and highly software-configurable archi-
tecture of the USB Controller makes it easy to imple-
ment both device- and host-capable solutions. The
on-chip OTG PHY with software controllable pull-up
and pull-down resistors, VBUS comparators and ID-
line detection reduces the number of external com-
ponents to a minimum. Third-party USB software
stacks are also available, reducing the development
time substantially. By utilizing the very low energy
consumption in EM2, the USB device will be able to
wake up and perform tasks several times a second
without violating the 2.5 mA maximum average cur-
rent during suspend.
15.1 Introduction
The USB is a full-speed/low-speed USB 2.0 compliant OTG host/device controller. The architecture is very flexible and allows the USB
to be used in On-the-go (OTG) Dual-Role Device, Device and Host-only configurations. The USB supports HNP and SRP protocols and
both OTG Revisions 1.3 and 2.0 are supported. The on-chip voltage regulator and PHY reduces the number of external components to
a minimum. A switchable external 5V supply or step-up regulator is needed for OTG Dual Role Device and Host configurations.
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15.2 Features
• Fully compliant with Universal Serial Bus Specification, Revision 2.0
• Supports full-speed (12 Mbit/s) and low-speed (1.5 Mbit/s) host and device
• Dedicated Internal DMA Controller
• 12 software-configurable endpoints (6 IN, 6 OUT) in addition to endpoint 0
• 2 kB endpoint memory
• Resume/Reset detection in EM2 (during suspend)
• SRP detection in EM2 (during host session off)
• Soft connect/disconnect
• Full OTG support
• Compliant with On-The-Go and Embedded Host Supplement to the USB Revision 2.0 Specification, Revision 2.0
• Compliant with USB On-The-Go Supplement, Revision 1.3
• Supports Host Negotiation Protocol (HNP) and Session Request Protocol (SRP)
• On-chip PHY
• Internal pull-up and pull-down resistors
• Voltage comparators for monitoring VBUS voltage
• A/B Device identification using ID line
• Charge/discharge of VBUS for VBUS-pulsing
• Internal 3.3 V Regulator
• Output voltage: 3.3V
• Output current: 50 mA
• Input voltage range: 4.0 - 5.5V
• Enabled automatically when input voltage applied
• Low quiescent current: 100 µA
• Dedicated input pin allows regulator to be used in OTG and host configurations
• Output pin can be used to power the EFM32 itself as well as external components
• Regulator voltage output sense feature for detecting USB plug/unplug events (also available in EM2/3)
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AHB Master
AHB Slave
15.3 USB System Description
A block diagram of the USB is shown in the following figure.
OTG
PHY
USB_VBUS
Voltage
Regulator
(3.3 V)
USB_DP
USB_DM
USB_ID
USB_VREGI
USB_VREGO
AHB Master
AHB Slave
AHB
2 KB
FIFO RAM
USB_VBUSEN
VREGO
Sense
USB Core
w/ DMA Controller
APB Slave
APB
USB Interrupt
SOF PRS USB_DMPU
USB System
(control)
Figure 15.1. USB Block Diagram
The USB consists of a digital logic part, a 2 kB endpoint RAM, OTG PHY and a voltage regulator with output voltage sensor. The volt-
age regulator provides a stable 3.3 V supply for the PHY, but can also be used to power the EFM32 itself as well as external compo-
nents.
The digital logic of the USB is split into two parts: system and core.
The system part is accessed using USB registers from offset 0x000 to 0x018 and controls the voltage regulator and enabling/disabling
of the PHY and USB pins. This part is clocked by HFCORECLKUSB and is accessed using an APB slave interface. The system part can
thus be accessed independently of the core part, without HFCORECLKUSBC running.
The core part is clocked by HFCORECLKUSBC and is accessed using an AHB slave interface. This interface is used for accessing the
FIFO contents and the registers in the core part starting at offset 0x3C000. An additional master interface is used by the internal DMA
controller of the core. The core part takes care of all the USB protocol related functionality. The clock to the system part must not be
disabled when the core part is active.
There are 8 pins associated with the USB. USB_VBUS should be connected to the VBUS (5V) pin on the USB receptacle. It is connec-
ted to the voltage comparators and current sink/source in the PHY. USB_DP and USB_DM are the USB D+ and D- pins. These are the
USB data signaling pins. USB_ID is the OTG ID pin used to detect the device type (A or B). This pin can be left unconnected when not
used. USB_VREGI is the input to the voltage regulator and USB_VREGO is the regulated output. USB_VBUSEN is used to turn on and
off VBUS power when operating as host-only or OTG A-Device. USB_DMPU is used to enable/disable an external D- pull-up resistor.
This is needed for low-speed device only. USB_VBUSEN and USB_DMPU will be high-impedance until the pins are enabled from soft-
ware. Thus, if a defined level is required during start-up an external pull-up/pull-down can be used.
15.3.1 USB Initialization
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The USB requires the device to run from a 48 MHz crystal (2500 ppm or better). The core part of the USB will always run from HFCOR-
ECLKUSBC which is HFCLK undivided (48 MHz). The current consumption for the rest of the device can be reduced by dividing down
HFCORECLK using the CMU_HFCORECLKDIV register. Bandwidth requirements for the specific USB application must be taken into
account when dividing down HFCORECLK.
Follow these steps to enable the USB:
1. Enable the clock to the system part by setting USB in CMU_HFCORECLKEN0.
2. If the internal USB regulator is bypassed (by applying 3.3V on USB_VREGI and USB_VREGO externally), disable the regulator by
setting VREGDIS in USB_CTRL.
3. If the PHY is powered from VBUS using the internal regulator, the VREGO sense circuit should be enabled by setting VREGOSEN
in USB_CTRL.
4. Enable the USB PHY pins by setting PHYPEN in USB_ROUTE.
5. If host or OTG dual-role device, set VBUSENAP in USB_CTRL to the desired value and then enable the USB_VBUSEN pin in
USB_ROUTE. Set the MODE for the pin to PUSHPULL.
6. If low-speed device, set DMPUAP in USB_CTRL to the desired value and then enable the USB_DMPU pin in USB_ROUTE. Set
the MODE for the pin to PUSHPULL.
7. Make sure HFXO is ready and selected. The core part requires the undivided HFCLK to be 48 MHz when USB is active (during
suspend/session-off a 32 kHz clock is used).
8. Enable the clock to the core part by setting USBC in CMU_HFCORECLKEN0.
9. Wait for the core to come out of reset. This is easiest done by polling a core register with non-zero reset value until it reads a non-
zero value. This takes approximately 20 48-MHz cycles.
10. Start initializing the USB core as described in USB Core Description.
15.3.2 Configurations
The USB can be used as Device, OTG Dual Role Device or Host. The sections below describe the different configurations. External
ESD protection and series resistors for impedance matching are required. The voltage regulator requires a 4.7 µF external decoupling
capacitor on the input and a 1 µF external decoupling capacitor on the output. Decoupling not related to USB is not shown in the fig-
ures.
15.3.2.1 Bus-Powered Device
A bus-powered device configuration is shown in the following figure. In this configuration, the voltage regulator powers the PHY and the
EFM32 at 3.3 V. The voltage regulator output (USB_VREGO) can also be used to power other components of the system.
In this configuration, the VREGO sense circuit should be left disabled.
Device
USB_DP
USB_DM
Standard B
VBUS
D+
D-
GND
USB_VBUS
USB_VREGI
USB_VREGO
(ESD Protection)
VDD
Figure 15.2. Bus-Powered Device
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15.3.2.2 Self-Powered Device
A self-powered device configuration is shown in the following figure. When the USB is configured as a self-powered device, the voltage
regulator is typically used to power the PHY only, although it may also be used to power other 3.3 V components. When the USB is
connected to a host, the voltage regulator is activated. Software can detect this event by enabling the VREGO Sense High (VREGOSH)
interrupt. The PHY pins can then be enabled and USB traffic can start. The VREGO Sense Low (VREGOSL) interrupt can be used to
detect when VBUS voltage disappears (for example if the USB cable is unplugged).
In this configuration, the VREGO sense circuit must be enabled.
Device
USB_DP
USB_DM
Standard B
VBUS
D+
D-
GND
USB_VREGI
USB_VREGO
(ESD Protection)
VDD
1.8V – 3.6V
Figure 15.3. Self-Powered Device
15.3.2.3 Self-Powered Device (with Bus-Power Switch)
A self-powered device (with bus-power switch) may switch power supply to VBUS when connected to a host. This is typically useful for
extending the life of battery-powered devices and enables the use of coin-cell driven systems with low maximum peak current. The
external components required typically include 2 transistors, 2 diodes and a few resistors. See application note for details. This allows
seamless power supply switching between a battery and the voltage regulator output.
The VREGO Sense High interrupt is used to detect when VBUS becomes present. Software can then enable the external transistor
connected to USB_VREGO, effectively switching the power source. A regular GPIO pin is used to control this transistor. If necessary,
the application may have to reduce the current consumption before switching to the USB power source. If VBUS voltage is removed,
the circuit switches automatically back to the battery power supply. If necessary software must react quickly to this event and reduce
the current consumption (for example by reducing the clock frequency) to avoid excessive voltage drop. This configuration is shown in
the following figure.
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In this configuration, the VREGO sense circuit must be enabled.
Device
USB_DP
USB_DM
Standard B
VBUS
D+
D-
GND
USB_VBUS
USB_VREGI
USB_VREGO
(ESD Protection)
VDD
1.8V – 3.6V
Dual- Power
Circuit
(enable) GPIO
Figure 15.4. Self-Powered Device (with Bus-Power Switch)
15.3.2.4 OTG Dual Role Device (5V)
An OTG Dual Role Device (5V) configuration is shown in the following figure. When 5V is available, the internal regulator can be used
to power the EFM32. An external power switch is needed to control VBUS power. For over-current detection a regular GPIO input pin
with interrupt is used. The application should turn off or limit VBUS power when over-current is detected. In OTG mode, the maximum
VBUS decoupling capacitance is 6.5 µF.
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In this configuration, the VREGO sense circuit should be left disabled.
Device
USB_DP
USB_DM
Micro-AB
VBUS
D+
D-
ID
USB_VBUS
USB_VREGI
USB_VREGO
(ESD Protection)
VDD
USB_ID
GND
5V
USB_VBUSEN
GPIO (over-current)
Power switch +
over-current detection
Vin
Vout
EN
OC
Figure 15.5. OTG Dual Role Device (5V)
15.3.2.5 OTG Dual Role Device (5V Step-Up Regulator)
An OTG Dual Role Device (5V step-up regulator) configuration is shown in the following figure. When 5V is not available, an external
5V step-up regulator is needed. In this configuration, the voltage for the EFM32 must be in the range 3.0V - 3.6V. In this mode the
voltage regulator is bypassed by connecting both the input and output to the external supply. This effectively causes the PHY to be
powered directly from the external 3.0 - 3.6 V supply. The voltage regulator should be disabled when operating in this mode. For over-
current detection a regular GPIO input pin with interrupt is used. The application should turn off or limit VBUS power when over-current
is detected. In OTG mode, the maximum VBUS decoupling capacitance is 6.5 µF.
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In this configuration, the VREGO sense circuit should be left disabled.
Device
USB_DP
USB_DM
Micro-AB
VBUS
D+
D-
ID
USB_VBUS
USB_VREGI
USB_VREGO
(ESD Protection)
VDD
USB_ID
GND
5V
USB_VBUSEN
GPIO (over-current)
Power switch +
over-current detection
Vin
Vout
EN
OC
Figure 15.6. OTG Dual Role Device (5V Step-Up Regulator)
15.3.2.6 Host
A host configuration is shown in the following figure. In this example a 5V step-up regulator is used. If 5V is available, a power switch
can be used instead, as shown in Figure 15.5 OTG Dual Role Device (5V) on page 329. The host configuration is equal to OTG Dual
Role Device, except for the USB_ID pin which is not used and the USB connector which is a USB Standard-A Connector. In host mode,
the minimum VBUS decoupling capacitance is 96 µF.
In this configuration, the VREGO sense circuit should be left disabled.
Device
USB_DP
USB_DM
Standard A
VBUS
D+
D-
USB_VBUS
USB_VREGO
USB_VREGI
(ESD Protection)
VDD
GND
3.0V – 3.6V
USB_VBUSEN
GPIO (over-current)
EN Vout
Vin
OC
5V step-up
Figure 15.7. Host
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15.3.3 PHY
The USB includes an internal full-speed/low-speed PHY with built-in pull-up/pull-down resistors, VBUS comparators and ID line state
sensing. During suspend, the PHY enters a low-power state where only the single-ended receivers are active. The PHY is disabled by
default and should be enabled by setting PHYPEN in USB_ROUTE before the USB core clock is enabled.
The PHY is powered by the internal voltage regulator output (USB_VREGO). To power the PHY directly from an external source (for
example an external 3.3 V LDO), connect both USB_VREGO and USB_VREGI to the external 3.3 V supply voltage. To stop the quies-
cent current present with the voltage regulator enabled in this configuration, disable the the regulator by setting VREGDIS in
USB_CTRL after power up. Then the regulator is effectively bypassed.
When VREGO Sense is enabled, the PHY is automatically disabled internally when the VREGO Sense output is low. This will happen if
VBUS-power disappears. The application can detect this by keeping the VREGO Sense Low Interrupt enabled. Note that PHYPEN in
USB_ROUTE will not be set to 0 in this case. Also, the PHY must always be disabled manually when there is no voltage applied to
VREGO.
15.3.4 Voltage Regulator
The voltage regulator is used to regulate the 5 V VBUS voltage down to 3.3 V which is the operating voltage for the PHY.
A decoupling capacitor is required on USB_VREGI and USB_VREGO. Note that the USB standard requires the total capacitance on
VBUS to be 1 µF minimum and 10 uF maximum for regular devices. OTG devices can have maximum 6.5 µF capacitance on VBUS.
The voltage regulator is enabled by default and can thus be used to power the EFM32 itself. Systems not using the USB should disable
the regulator by setting VREGDIS in USB_CTRL. A voltage sense circuit monitors the output voltage and can be used to detect when
the voltage regulator becomes active. This sense circuit can also be used to detect when the voltage drops (typically due to the USB
cable being unplugged). If regulator voltage monitoring is not required (i.e. it is known that the VREGO voltage is always present), the
sense circuit should be left disabled.
During suspend, the bias current for the regulator can be reduced if the current requirements in EM2/3 are low. The bias current in
EM2/3 is controlled by BIASPROGEM23 in USB_CTRL. When EM2/3 is entered, the bias current for the regulator switches to what is
specified in BIASPROGEM23 in USB_CTRL. When entering EM0 again (due to USB resume/reset signaling or any other wake-up in-
terrupt) the regulator switches back to using the value specified in BIASPROGEM01 in USB_CTRL.
15.3.5 Interrupts and PRS
Interrupts from the core and system part share a common USB interrupt line to the CPU. The interrupt flags for the system part are
grouped together in the USB_IF register. The interrupt events from the core are controlled by several core interrupt flag registers.
There are two PRS outputs from the USB: SOF and SOFSR. In Host mode, SOF toggles every time an SOF is generated. In Device
mode, SOF toggles every time an SOF token is received from the USB host or when an SOF token is missed at the start of frame. In
Host mode, SOFSR toggles every time an SOF is successfully transmitted. In Device mode, SOFSR toggles only when a valid SOF
token is received from the USB host. Both PRS outputs must be synchronized in the PRS when used (i.e. it is an asynchronous PRS
output). The edge-to-pulse converter in the PRS can be used to convert the edges into pulses if needed. The PRS outputs go to 0 in
EM2/3.
15.3.6 USB in EM2
During suspend and session-off EM2 should be used to save power and meet the average current requirements dictated by the USB
standard. Before entering EM2, HFCORECLKUSBC must be switched from 48 MHz to 32 kHz (LFXO or LFRCO). This is done using the
CMU_CMD and CMU_STATUS registers. While HFCORECLKUSBC is 32 kHz, the USB core registers (starting from offset 0x3C000)
cannot be accessed and the the internal DMA in the USB core will not be able to access the AHB bus. Upon EM2 wake-up, HFCOR-
ECLKUSBC must be switched back to 48 MHz before accessing the core registers. The device always starts up from HFRCO so soft-
ware must restart HFXO and switch from HFRCO to HFXO. The USB system clock, HFCORECLKUSB, must be kept enabled during
EM2. The USB system registers can be accessed immediately upon EM2 wake-up, while running from HFRCO. Follow the steps out-
lined the USB Core Description when entering EM2 during suspend and session-off.
The FIFO content is lost when entering EM2. In addition, most of the USB core registers are reset and therefore need to be backed up
in RAM.
EM3 cannot be used when the USB is active. However, EM3 can be used while waiting for the internal voltage regulator to be activated
(i.e. VBUS becomes 5V).
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15.4 USB Core Description
This section describes the programming requirements for the USB Core in Host and Device modes.
Important features/parameters for the core are:
• HNP- and SRP-Capable OTG (Device and Host)
• Internal DMA (Buffer Pointer Based)
• Dedicated TX FIFOS for each endpoint in device mode
• 6 IN/OUT endpoints in addition to endpoint 0 (in device mode)
• 14 host channels (in host mode)
• Dynamic FIFO sizing
• Non-Periodic Request Queue Depth: 8
• Host Mode Periodic Request Queue Depth: 8
The core has the following limitations:
• Link Power Management (LPM) is not supported
• ADP is not supported
Portions Copyright © 2010 Synopsys, Inc. Used with permission. Synopsys and DesignWare are registered trademarks of Synopsys,
Inc.
15.4.1 Overview: Programming the Core
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Each significant programming feature of the core is discussed in a separate section.
This chapter uses abbreviations for register names and their fields. For detailed information on registers, see the end of this chapter.
The application must perform a core initialization sequence. If the cable is connected during power-up, the Current Mode of Operation
bit in the Core Interrupt register (USB_GINTSTS.CURMOD) reflects the mode. The core enters Host mode when an “A” plug is connec-
ted, or Device mode when a “B” plug is connected.
This section explains the initialization of the core after power-on. The application must follow the initialization sequence irrespective of
Host or Device mode operation. All core global registers are initialized according to the core’s configuration.
1. Program the following fields in the Global AHB Configuration (USB_GAHBCFG) register.
• DMA Mode bit
• AHB Burst Length field
• Global Interrupt Mask bit = 1
• Non-periodic TxFIFO Empty Level (can be enabled only when the core is operating in Slave mode as a host.)
• Periodic TxFIFO Empty Level (can be enabled only when the core is operating in Slave mode)
2. Program the following field in the Global Interrupt Mask (USB_GINTMSK) register:
• USB_GINTMSK.RXFLVLMSK = 0
3. Program the following fields in USB_GUSBCFG register.
• HNP Capable bit
• SRP Capable bit
• External HS PHY or Internal FS Serial PHY Selection bit
• Time-Out Calibration field
• USB Turnaround Time field
4. The software must unmask the following bits in the USB_GINTMSK register.
• OTG Interrupt Mask
• Mode Mismatch Interrupt Mask
5. The software can read the USB_GINTSTS.CURMOD bit to determine whether the core is operating in Host or Device mode. The
software the follows either the 15.4.1.1 Host Initialization or 15.4.1.2 Device Initialization sequence.
Note: The core is designed to be interrupt-driven. Polling interrupt mechanism is not recommended: this may result in undefined resolu-
tions.
Note: In device mode, just after Power On Reset or a Soft Reset, the USB_GINTSTS.SOF bit is set to 1 for debug purposes. This
status must be cleared and can be ignored.
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15.4.1.1 Host Initialization
To initialize the core as host, the application must perform the following steps.
1. Program USB_GINTMSK.PRTINT to unmask.
2. Program the USB_HCFG register to select full-speed host.
3. Program the USB_HPRT.PRTPWR bit to 1. This drives VBUS on the USB.
4. Wait for the USB_HPRT.PRTCONNDET interrupt. This indicates that a device is connect to the port.
5. Program the USB_HPRT.PRTRST bit to 1. This starts the reset process.
6. Wait at least 10 ms for the reset process to complete.
7. Program the USB_HPRT.PRTRST bit to 0.
8. Wait for the USB_HPRT.PRTENCHNG interrupt.
9. Read the USB_HPRT.PRTSPD field to get the enumerated speed.
10. Program the USB_HFIR register with a value corresponding to the selected PHY clock. At this point, the host is up and running and
the port register begins to report device disconnects, etc. The port is active with SOFs occurring down the enabled port.
11. Program the RXFSIZE register to select the size of the receive FIFO.
12. Program the NPTXFSIZE register to select the size and the start address of the Non-periodic Transmit FIFO for non-periodic trans-
actions.
13. Program the USB_HPTXFSIZ register to select the size and start address of the Periodic Transmit FIFO for periodic transactions.
To communicate with devices, the system software must initialize and enable at least one channel as described in 15.4.1.2 Device Initi-
alization.
15.4.1.1.1 Host Connection
The following steps explain the host connection flow:
1. When the USB Cable is plugged to the Host port, the core triggers USB_GINTSTS.CONIDSTSCHNG interrupt.
2. When the Host application detects USB_GINTSTS.CONIDSTSCHNG interrupt, the application can perform one of the following ac-
tions:
• Turn on VBUS by setting USB_HPRT.PRTPWR = 1 or
• Wait for SRP Signaling from Device to turn on VBUS.
3. The PHY indicates VBUS power-on by detecting a VBUS valid voltage level.
4. When the Host Core detects the device connection, it triggers the Host Port Interrupt (USB_GINTSTS.PRTINT) to the application.
5. When USB_GINTSTS.PRTINT is triggered, the application reads the USB_HPRT register to check if the Port Connect Detected
(USB_HPRT.PRTCONNDET) bit is set or not.
15.4.1.1.2 Host Disconnection
The following steps explain the host disconnection flow:
1. When the Device is disconnected from the USB Cable (but the cable is still connected to the USB host), the Core triggers
USB_GINTSTS.DISCONNINT (Disconnect Detected) interrupt.
Note: If the USB cable is disconnected from the Host port without removing the device, the core generates an additional interrupt -
USB_GINTSTS.CONIDSTSCHNG (Connector ID Status Change).
2. The Host application can choose to turn off the VBUS by programming USB_HPRT.PRTPWR = 0.
15.4.1.2 Device Initialization
The application must perform the following steps to initialize the core at device on, power on, or after a mode change from Host to
Device.
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1. Program the following fields in USB_DCFG register.
• Device Speed
• Non-Zero-Length Status OUT Handshake
• Periodic Frame Interval
2. Program the USB_GINTMSK register to unmask the following interrupts.
• USB Reset
• Enumeration Done
• Early Suspend
• USB Suspend
3. Wait for the USB_GINTSTS.USBRST interrupt, which indicates a reset has been detected on the USB and lasts for about 10 ms.
On receiving this interrupt, the application must perform the steps listed in 15.4.4.1.1 Initialization on USB Reset.
4. Wait for the USB_GINTSTS.ENUMDONE interrupt. This interrupt indicates the end of reset on the USB. On receiving this interrupt,
the application must read the USB_DSTS register to determine the enumeration speed and perform the steps listed in
15.4.4.1.2 Initialization on Enumeration Completion.
At this point, the device is ready to accept SOF packets and perform control transfers on control endpoint 0.
15.4.1.2.1 Device Connection
The device connect process varies depending on the if the VBUS is on or off when the device is connected to the USB cable.
When VBUS is on When the Device is Connected
If VBUS is on when the device is connected to the USB cable, there is no SRP from the device. The device connection flow is as fol-
lows:
1. The device triggers the USB_GINTSTS.SESSREQINT [bit 30] interrupt bit.
2. When the device application detects the USB_GINTSTS.SESSREQINT interrupt, it programs the required bits in the USB_DCFG
register.
3. When the Host drives Reset, the Device triggers USB_GINTSTS.USBRST [bit 12] on detecting the Reset. The host then follows
the USB 2.0 Enumeration sequence.
When VBUS is off When the Device is Connected
If VBUS is off when the device is connected to the USB cable, the device initiates SRP in OTG Revision 1.3 mode. The device connec-
tion flow is as follows:
1. The application initiates SRP by writing the Session Request bit in the OTG Control and Status register. The core perform data-line
pulsing followed by VBUS pulsing.
2. The host starts a new session by turning on VBUS, indicating SRP success. The core interrupts the application by setting the Ses-
sion Request Success Status Change bit in the OTG Interrupt Status register.
3. The application reads the Session Request Success bit in the OTG Control and Status register and programs the required bits in
USB_DCFG register.
4. When Host drives Reset, the Device triggers USB_GINTSTS.USBRST on detecting the Reset. The host then follows the USB 2.0
Enumeration sequence.
15.4.1.2.2 Device Disconnection
The device session ends when the USB cable is disconnected or if the VBUS is switched off by the Host.
The device disconnect flow is as follows:
1. When the USB cable is unplugged or when the VBUS is switched off by the Host, the Device core trigger USB_GINTSTS.OTGINT
[bit 2] interrupt bit.
2. When the device application detects USB_GINTSTS.OTGINT interrupt, it checks that the USB_GOTGINT.SESENDDET (Session
End Detected) bit is set to 1.
15.4.1.2.3 Device Soft Disconnection
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The application can perform a soft disconnect by setting the Soft disconnect bit (SFTDISCON) in Device Control Register (USB_DCTL).
Send/Receive USB Transfers -> Soft Disconnect -> Soft reset -> USB Device Enumeration
Sequence of operations:
1. The application configures the device to send or receive transfers.
2. The application sets the Soft disconnect bit (SFTDISCON) in the Device Control Register (USB_DCTL).
3. The application sets the Soft Reset bit (CSFTRST) in the Reset Register (USB_GRSTCTL).
4. Poll the USB_GRSTCTL register until the core clears the soft reset bit, which ensures the soft reset is completed properly.
5. Initialize the core according to the instructions in 15.4.1.2 Device Initialization.
Suspend -> Soft Disconnect -> Soft Reset -> USB Device Enumeration
Sequence of operations:
1. The core detects a USB suspend and generates a Suspend Detected interrupt.
2. The application sets the Stop PHY Clock bit in the Power and Clock Gating Control register, the core puts the PHY in suspend
mode, and the PHY clock stops.
3. The application clears the Stop PHY Clock bit in the Power and Clock Gating Control register, and waits for the PHY clock to come
back. The core takes the PHY back to normal mode, and the PHY clock comes back.
4. The application sets the Soft disconnect bit (SFTDISCON) in Device Control Register (USB_DCTL).
5. The application sets the Soft Reset bit (CSFTRST) in the Reset Register (USB_GRSTCTL).
6. Poll the USB_GRSTCTL register until the core clears the soft reset bit, which ensures the soft reset is completed properly.
7. Initialize the core according to the instructions in 15.4.1.2 Device Initialization.
15.4.2 Modes of Operation
•15.4.2.1 Overview: DMA/Slave Modes
•15.4.2.2 DMA Mode
•15.4.2.3 Slave Mode
15.4.2.1 Overview: DMA/Slave Modes
The application can operate the core in either of two modes:
• In 15.4.2.2 DMA Mode — The core fetches the data to be transmitted or updates the received data on the AHB.
• In 15.4.2.3 Slave Mode — The application initiates the data transfers for data fetch and store.
15.4.2.2 DMA Mode
In DMA Mode, the OTG host uses the AHB master Interface for transmit packet data fetch (AHB to USB) and receive data update (USB
to AHB). The AHB master uses the programmed DMA address (USB_HCx_DMAADDR register in host mode and
USB_DIEPx_DMAADDR/USB_DOEPx_DMAADDR register in device mode) to access the data buffers.
15.4.2.2.1 Transfer-Level Operation
In DMA mode, the application is interrupted only after the programmed transfer size is transmitted or received (provided the core de-
tects no NAK/Timeout/Error response in Host mode, or Timeout/CRC Error in Device mode). The application must handle all transac-
tion errors. In Device mode, all the USB errors are handled by the core itself.
15.4.2.2.2 Transaction-Level Operation
This mode is similar to transfer-level operation with the programmed transfer size equal to one packet size (either maximum packet
size, or a short packet size).
15.4.2.3 Slave Mode
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In Slave mode, the application can operate the core either in transaction-level (packet-level) operation or in pipelined transaction-level
operation.
15.4.2.3.1 Transaction-Level Operation
The application handles one data packet at a time per channel/endpoint in transaction-level operations. Based on the handshake re-
sponse received on the USB, the application determines whether to retry the transaction or proceed with the next, until the end of the
transfer. The application is interrupted on completion of every packet. The application performs transaction-level operations for a chan-
nel/endpoint for a transmission (host: OUT/device: IN) or reception (host: IN/device: OUT) as shown in the following figures.
Host Mode
For an OUT transaction, the application enables the channel and writes the data packet into the corresponding (Periodic or Non-period-
ic) transmit FIFO. The core automatically writes the channel number into the corresponding (Periodic or Non-periodic) Request Queue,
along with the last DWORD write of the packet. For an IN transaction, the application enables the channel and the core automatically
writes the channel number into the corresponding Request queue. The application must wait for the packet received interrupt, then
empty the packet from the receive FIFO.
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Device Mode
For an IN transaction, the application enables the endpoint, writes the data packet into the corresponding transmit FIFO, and waits for
the packet completion interrupt from the core. For an OUT transaction, the application enables the endpoint, waits for the packet re-
ceived interrupt from the core, then empties the packet from the receive FIFO.
Note: The application has to finish writing one complete packet before switching to a different channel/endpoint FIFO. Violating this rule
results in an error.
Start
Write 1 packet to
the Transmit FIFO
Set up the
channel/endpoint
Get interrupt?
Get channel/endpoint
interrupt status
Retry required?
Transfer
complete?
Done
Rewrite packet to the
Transmit FIFO
YES
NO
YES
NO
YES
NO
Figure 15.8. Transmit Transaction-Level Operation in Slave Mode
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Set up the
Channel / Endpoint
Start
Read Receive
Status Queue
Read the packet
from the Receive
FIFO
Done
Transfer complete?
Retry required?
RXFLVL or
Ch/EP interrupt?
YES
NO
YES
NO
YES
NO
Figure 15.9. Receive Transaction-Level Operation in Slave Mode
15.4.2.3.2 Pipelined Transaction-Level Operation
The application can pipeline more than one transaction (IN or OUT) with pipelined transaction-level operation, which is analogous to
Transfer mode in DMA mode. In pipelined transaction-level operation, the application can program the core to perform multiple transac-
tions. The advantage of this mode compared to transaction-level operation is that the application is not interrupted on a packet basis.
15.4.2.3.2.1 Host Mode
For an OUT transaction, the application sets up a transfer and enables the channel. The application can write multiple packets back-to-
back for the same channel into the transmit FIFO, based on the space availability. It can also pipeline OUT transactions for multiple
channels by writing into the HCHARn register, followed by a packet write to that channel. The core writes the channel number, along
with the last DWORD write for the packet, into the Request queue and schedules transactions on the USB in the same order.
For an IN transaction, the application sets up a transfer and enables the channel, and the core writes the channel number into the Re-
quest queue. The application can schedule IN transactions on multiple channels, provided space is available in the Request queue. The
core initiates an IN token on the USB only when there is enough space to receive at least of one maximum-packet-size packet of the
channel in the top of the Request queue.
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15.4.2.3.2.2 Device Mode
For an IN transaction, the application sets up a transfer and enables the endpoint. The application can write multiple packets back-to-
back for the same endpoint into the transmit FIFO, based on available space. It can also pipeline IN transactions for multiple channels
by writing into the USB_DIEPx_CTL register followed by a packet write to that endpoint. The core writes the endpoint number, along
with the last DWORD write for the packet into the Request queue. The core transmits the data in the transmit FIFO when an IN token is
received on the USB.
For an OUT transaction, the application sets up a transfer and enables the endpoint. The core receives the OUT data into the receive
FIFO, when it has available space. As the packets are received into the FIFO, the application must empty data from it.
From this point on in this chapter, the terms “Pipelined Transaction mode” and “Transfer mode” are used interchangeably.
15.4.3 Host Programming Model
Before you program the Host, read 15.4.1 Overview: Programming the Core and 15.4.2 Modes of Operation.
This section discusses the following topics:
•15.4.3.1 Channel Initialization
•15.4.3.2 Halting a Channel
•15.4.3.3 Sending a Zero-Length Packet in Slave/DMA Modes
•15.4.3.4 Handling Babble Conditions
•15.4.3.5 Handling Disconnects
•15.4.3.6 Host Programming Operations
•15.4.3.6.1 Writing the Transmit FIFO in Slave Mode
•15.4.3.6.2 Reading the Receive FIFO in Slave Mode
15.4.3.1 Channel Initialization
The application must initialize one or more channels before it can communicate with connected devices. To initialize and enable a
channel, the application must perform the following steps.
1. Program the USB_GINTMSK register to unmask the following:
2. Channel Interrupt
• Non-periodic Transmit FIFO Empty for OUT transactions (applicable for Slave mode that operates in pipelined transaction-level
with the Packet Count field programmed with more than one).
• Non-periodic Transmit FIFO Half-Empty for OUT transactions (applicable for Slave mode that operates in pipelined transaction-
level with the Packet Count field programmed with more than one).
3. Program the USB_USB_HAINTMSK register to unmask the selected channels’ interrupts.
4. Program the HCINTMSK register to unmask the transaction-related interrupts of interest given in the Host Channel Interrupt regis-
ter.
5. Program the selected channel’s USB_HCx_TSIZ register.
Program the register with the total transfer size, in bytes, and the expected number of packets, including short packets. The appli-
cation must program the PID field with the initial data PID (to be used on the first OUT transaction or to be expected from the first
IN transaction).
6. Program the selected channels’ USB_HCx_DMAADDR register(s) with the buffer start address (DMA mode only).
7. Program the USB_HCx_CHAR register of the selected channel with the device’s endpoint characteristics, such as type, speed,
direction, and so forth. (The channel can be enabled by setting the Channel Enable bit to 1 only when the application is ready to
transmit or receive any packet).
Repeat the above steps for other channels.
Note: De-allocate channel means after the transfer has completed, the channel is disabled. When the application is ready to start the
next transfer, the application re-initializes the channel by following these steps.
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15.4.3.2 Halting a Channel
The application can disable any channel by programming the USB_HCx_CHAR register with the USB_HCx_CHAR.CHDIS and
USB_HCx_CHAR.CHENA bits set to 1. This enables the host to flush the posted requests (if any) and generates a Channel Halted
interrupt. The application must wait for the USB_HCx_INT.CHHLTD interrupt before reallocating the channel for other transactions. The
host does not interrupt the transaction that has been already started on USB.
In Slave mode operation, before disabling a channel, the application must ensure that there is at least one free space available in the
Non-periodic Request Queue (when disabling a non-periodic channel) or the Periodic Request Queue (when disabling a periodic chan-
nel). The application can simply flush the posted requests when the Request queue is full (before disabling the channel), by program-
ming the USB_HCx_CHAR register with the USB_HCx_CHAR.CHDIS bit set to 1, and the USB_HCx_CHAR.CHENA bit reset to 0.
The core generates a RXFLVL interrupt when there is an entry in the queue. The application must read/ pop the USB_GRXSTSP regis-
ter to generate the Channel Halted interrupt.
To disable a channel in DMA mode operation, the application need not check for space in the Request queue. The host checks for
space in which to write the Disable request on the disabled channel’s turn during arbitration. Meanwhile, all posted requests are drop-
ped from the Request queue when the USB_HCx_CHAR.CHDIS bit is set to 1.
The application is expected to disable a channel under any of the following conditions:
1. When a USB_HCx_INT.XFERCOMPL interrupt is received during a non-periodic IN transfer or high-bandwidth interrupt IN transfer
(Slave mode only)
2. When a USB_HCx_INT.STALL, USB_HCx_INT.XACTERR, USB_HCx_INT.BBLERR, or USB_HCx_INT.DATATGLERR interrupt
is received for an IN or OUT channel (Slave mode only). For high-bandwidth interrupt INs in Slave mode, once the application has
received a DATATGLERR interrupt it must disable the channel and wait for a Channel Halted interrupt. The application must be
able to receive other interrupts (DATATGLERR, NAK, Data, XACTERR, BBLERR) for the same channel before receiving the halt.
3. When a USB_GINTSTS.DISCONNINT (Disconnect Device) interrupt is received. The application must check for the
USB_HPRT.PRTCONNSTS, because when the device directly connected to the host is disconnected, USB_HPRT.PRTCONNSTS
is reset. The software must issue a soft reset to ensure that all channels are cleared. When the device is reconnected, the host
must issue a USB Reset.
4. When the application aborts a transfer before normal completion (Slave and DMA modes).
Note: In DMA mode, keep the following guideline in mind: Channel disable must not be programmed for periodic channels. At the end
of the next frame (in the worst case), the core generates a channel halted and disables the channel automatically.
15.4.3.3 Sending a Zero-Length Packet in Slave/DMA Modes
To send a zero-length data packet, the application must initialize an OUT channel as follows.
1. Program the USB_HCx_TSIZ register of the selected channel with a correct PID, XFERSIZE = 0, and PKTCNT = 1.
2. Program the USB_HCx_CHAR register of the selected channel with CHENA = 1 and the device’s endpoint characteristics, such as
type, speed, and direction.
The application must treat a zero-length data packet as a separate transfer, and cannot combine it with a non-zero-length transfer.
15.4.3.4 Handling Babble Conditions
The core handles two cases of babble: packet babble and port babble. Packet babble occurs if the device sends more data than the
maximum packet size for the channel. Port babble occurs if the core continues to receive data from the device at EOF2 (the end of
frame 2, which is very close to SOF).
When the core detects a packet babble, it stops writing data into the Rx buffer and waits for the end of packet (EOP). When it detects
an EOP, it flushes already-written data in the Rx buffer and generates a Babble interrupt to the application.
When detects a port babble, it flushes the RxFIFO and disables the port. The core then generates a Port Disabled Interrupt
(USB_GINTSTS.PRTINT, USB_HPRT.PRTENCHNG). On receiving this interrupt, the application must determine that this is not due to
an overcurrent condition (another cause of the Port Disabled interrupt) by checking USB_HPRT.PRTOVRCURRACT, then perform a
soft reset. The core does not send any more tokens after it has detected a port babble condition.
15.4.3.5 Handling Disconnects
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If the device is disconnected suddenly, a USB_GINTSTS.DISCONNINT interrupt is generated. When the application receives this inter-
rupt, it must issue a soft reset by programming the USB_GRSTCTL.CSFTRST bit.
15.4.3.6 Host Programming Operations
The table below provides links to the programming sequence for the different types of USB transactions.
Table 15.1. Host Programming Operations
Mode IN OUT/SETUP
Control
Slave 15.4.3.6.5 Bulk and Control IN Transac-
tions in Slave Mode
15.4.3.6.4 Bulk and Control OUT/SETUP
Transactions in Slave Mode
DMA 15.4.3.6.8 Bulk and Control IN Transac-
tions in DMA Mode
15.4.3.6.7 Bulk and Control OUT/SETUP
Transactions in DMA Mode
Bulk
Slave 15.4.3.6.5 Bulk and Control IN Transac-
tions in Slave Mode
15.4.3.6.4 Bulk and Control OUT/SETUP
Transactions in Slave Mode
DMA 15.4.3.6.8 Bulk and Control IN Transac-
tions in DMA Mode
15.4.3.6.7 Bulk and Control OUT/SETUP
Transactions in DMA Mode
Interrupt
Slave 15.4.3.6.10 Interrupt IN Transactions in
Slave Mode
15.4.3.6.9 Interrupt OUT Transactions in
Slave Mode
DMA 15.4.3.6.12 Interrupt IN Transactions in
DMA Mode
15.4.3.6.11 Interrupt OUT Transactions in
DMA Mode
Isochronous
Slave 15.4.3.6.14 Isochronous IN Transactions in
Slave Mode
15.4.3.6.13 Isochronous OUT Transactions
in Slave Mode
DMA 15.4.3.6.16 Isochronous IN Transactions in
DMA Mode
15.4.3.6.15 Isochronous OUT Transactions
in DMA Mode
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15.4.3.6.1 Writing the Transmit FIFO in Slave Mode
The following figure shows the flow diagram for writing to the transmit FIFO in Slave mode. The host automatically writes an entry (OUT
request) to the Periodic/Non-periodic Request Queue, along with the last DWORD write of a packet. The application must ensure that
at least one free space is available in the Periodic/Non-periodic Request Queue before starting to write to the transmit FIFO. The appli-
cation must always write to the transmit FIFO in DWORDs. If the packet size is non-DWORD aligned, the application must use padding.
The host determines the actual packet size based on the programmed maximum packet size and transfer size.
Start
1 MPS or LPS
FIFO space available?
Write 1 packet data
to Transmit FIFO
More packets
to send?
Done
Wait for
USB_GAHBCFG, NPTXFEMPLVL
or
USB_GAHBCFG, PTXFEMPLVL
interrupt
Read USB_GNPTXSTS /
USB_HPTXFSIZ registers
for available FIFO and
Queue spaces
NO
YES
YES
NO
MPS: Max Packet Size
LPS: Last Packet Size
Figure 15.10. Transmit FIFO Write Task in Slave Mode
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15.4.3.6.2 Reading the Receive FIFO in Slave Mode
The following figure shows the flow diagram for reading the receive FIFO in Slave mode. The application must ignore all packet sta-
tuses other than IN Data Packet (0b0010).
Start
RXFLVL
Interrupt?
Mask RXFLVL
interrupt
Read
USB_GRXSTSP
PKTSTS = 0b0010?
BCNT > 0?
Read the received
packet from the
Receive FIFO
Unmask RXFLVL
interrupt
Unmask RXFLVL
interrupt
YES
YES NO
NO
NO
YES
Figure 15.11. Receive FIFO Read Task in Slave Mode
15.4.3.6.3 Control Transactions in Slave Mode
Setup, Data, and Status stages of a control transfer must be performed as three separate transfers. Setup- Data- or Status-stage OUT
transactions are performed similarly to the bulk OUT transactions explained in 15.4.3.6.4 Bulk and Control OUT/SETUP Transactions in
Slave Mode. Data- or Status-stage IN transactions are performed similarly to the bulk IN transactions explained in 15.4.3.6.5 Bulk and
Control IN Transactions in Slave Mode. For all three stages, the application is expected to set the USB_HC1_CHAR.EPTYPE field to
Control. During the Setup stage, the application is expected to set the USB_HC1_TSIZ.PID field to SETUP.
15.4.3.6.4 Bulk and Control OUT/SETUP Transactions in Slave Mode
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To initialize the core after power-on reset, the application must follow the sequence in 15.4.1 Overview: Programming the Core. Before
it can communicate with the connected device, it must initialize a channel as described in 15.4.3.1 Channel Initialization. See Figure
15.10 Transmit FIFO Write Task in Slave Mode on page 343 and 15.4.3.6.2 Reading the Receive FIFO in Slave Mode for Read or
Write data to and from the FIFO in Slave mode.
A typical bulk or control OUT/SETUP pipelined transaction-level operation in Slave mode is shown in Figure 15.12 Normal Bulk/Control
OUT/SETUP and Bulk/Control IN Transactions in Slave Mode on page 346. See channel 1 (ch_1). Two bulk OUT packets are trans-
mitted. A control SETUP transaction operates the same way but has only one packet. The assumptions are:
• The application is attempting to send two maximum-packet-size packets (transfer size = 1,024 bytes).
• The Non-periodic Transmit FIFO can hold two packets (128 bytes for FS).
• The Non-periodic Request Queue depth = 4.
15.4.3.6.4.1 Normal Bulk and Control OUT/SETUP Operations
The sequence of operations in the following figure (channel 1) is as follows:
1. Initialize channel 1 as explained in 15.4.3.1 Channel Initialization.
2. Write the first packet for channel 1.
3. Along with the last DWORD write, the core writes an entry to the Non-periodic Request Queue.
4. As soon as the non-periodic queue becomes non-empty, the core attempts to send an OUT token in the current frame.
5. Write the second (last) packet for channel 1.
6. The core generates the XFERCOMPL interrupt as soon as the last transaction is completed successfully.
7. In response to the XFERCOMPL interrupt, de-allocate the channel for other transfers.
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init_reg(ch_1)
write_tx_fifo
(ch_1)
write_tx_fifo
(ch_1)
1
init_reg(ch_2)
1
set_ch_en
(ch_2)
set_ch_en
(ch_2)
set_ch_en
(ch_2)
set_ch_en
(ch_2)
read_rx_sts
read_rx_fifo
read_rx_sts
read_rx_fifo
read_rx_sts
Disable
(ch_2)
read_rx_sts
De-allocate
(ch_2)
De-allocate
(ch_1)
1 MPS
1 MPS
RXFLVL interrupt
1 MPS
XFERCOMPL interrupt
RXFLVL interrupt
RXFLVL interrupt
1 MPS
XFERCOMPL interrupt
RXFLVL interrupt
CHHLTD interrupt
ch_1
ch_2
ch_1
ch_2
OUT
DATA0
MPS
ACK
DATA0
IN
ACK
OUT
DATA1
MPS
ACK
IN
DATA1
ACK
ch_2
ch_2
ch_1
ch_2
ch_2
Non-Periodic Request
Queue
Assume that this queue
can hold 4 entries.
2
2
5
5
7
7
9
11
13
12
1010
8
6
6
4
3
34
Figure 15.12. Normal Bulk/Control OUT/SETUP and Bulk/Control IN Transactions in Slave Mode
15.4.3.6.4.2 Handling Interrupts
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The channel-specific interrupt service routine for bulk and control OUT/SETUP transactions in Slave mode is shown in the following
code samples.
Unmask (NAK/XACTERR/STALL/XFERCOMPL)
if (XFERCOMPL)
{
Reset Error Count
Mask ACK
De-allocate Channel
}
else if (STALL)
{
Transfer Done = 1
Unmask CHHLTD
Disable Channel
}
else if (NAK or XACTERR)
{
Rewind Buffer Pointers
Unmask CHHLTD
Disable Channel
if (XACTERR)
{
Increment Error Count
Unmask ACK
}
else
{
Reset Error Count
}
}
else if (CHHLTD)
{
Mask CHHLTD
if (Transfer Done or (Error_count == 3))
{
De-allocate Channel
}
else
{
Re-initialize Channel
}
}
else if (ACK)
{
Reset Error Count
Mask ACK
}
The application is expected to write the data packets into the transmit FIFO when space is available in the transmit FIFO and the Re-
quest queue. The application can make use of USB_GINTSTS.NPTXFEMP interrupt to find the transmit FIFO space.
The application is expected to write the requests as and when the Request queue space is available and until the XFERCOMPL inter-
rupt is received.
15.4.3.6.5 Bulk and Control IN Transactions in Slave Mode
To initialize the core after power-on reset, the application must follow the sequence in 15.4.1 Overview: Programming the Core. Before
it can communicate with the connected device, it must initialize a channel as described in 15.4.3.1 Channel Initialization. See Figure
15.10 Transmit FIFO Write Task in Slave Mode on page 343 and Figure 15.11 Receive FIFO Read Task in Slave Mode on page 344
for read or write data to and from the FIFO in Slave mode.
A typical bulk or control IN pipelined transaction-level operation in Slave mode is shown in Figure 15.12 Normal Bulk/Control OUT/
SETUP and Bulk/Control IN Transactions in Slave Mode on page 346. See channel 2 (ch_2). The assumptions are:
1. The application is attempting to receive two maximum-sized packets (transfer size = 1,024 bytes).
2. The receive FIFO can contain at least one maximum-packet-size packet and two status DWORDs per packet (72 bytes for FS).
3. The Non-periodic Request Queue depth = 4.
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15.4.3.6.5.1 Normal Bulk and Control IN Operations
The sequence of operations in Figure 15.12 Normal Bulk/Control OUT/SETUP and Bulk/Control IN Transactions in Slave Mode on
page 346 is as follows:
1. Initialize channel 2 as explained in 15.4.3.1 Channel Initialization.
2. Set the USB_HC2_CHAR.CHENA bit to write an IN request to the Non-periodic Request Queue.
3. The core attempts to send an IN token after completing the current OUT transaction.
4. The core generates an RXFLVL interrupt as soon as the received packet is written to the receive FIFO.
5. In response to the RXFLVL interrupt, mask the RXFLVL interrupt and read the received packet status to determine the number of
bytes received, then read the receive FIFO accordingly. Following this, unmask the RXFLVL interrupt.
6. The core generates the RXFLVL interrupt for the transfer completion status entry in the receive FIFO.
7. The application must read and ignore the receive packet status when the receive packet status is not an IN data packet
(USB_GRXSTSR.PKTSTS != 0b0010).
8. The core generates the XFERCOMPL interrupt as soon as the receive packet status is read.
9. In response to the XFERCOMPL interrupt, disable the channel (see 15.4.3.2 Halting a Channel) and stop writing the
USB_HC2_CHAR register for further requests. The core writes a channel disable request to the non-periodic request queue as
soon as the USB_HC2_CHAR register is written.
10. The core generates the RXFLVL interrupt as soon as the halt status is written to the receive FIFO.
11. Read and ignore the receive packet status.
12. The core generates a CHHLTD interrupt as soon as the halt status is popped from the receive FIFO.
13. In response to the CHHLTD interrupt, de-allocate the channel for other transfers.
Note: For Bulk/Control IN transfers, the application must write the requests when the Request queue space is available, and until the
XFERCOMPL interrupt is received.
15.4.3.6.5.2 Handling Interrupts
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The channel-specific interrupt service routine for bulk and control IN transactions in Slave mode is shown in the following code sam-
ples.
Unmask (XACTERR/XFERCOMPL/BBLERR/STALL/DATATGLERR)
if (XFERCOMPL)
{
Reset Error Count
Unmask CHHLTD
Disable Channel
Reset Error Count
Mask ACK
}
else if (XACTERR or BBLERR or STALL)
{
Unmask CHHLTD
Disable Channel
if (XACTERR)
{
Increment Error Count
Unmask ACK
}
}
else if (CHHLTD)
{
Mask CHHLTD
if (Transfer Done or (Error_count == 3))
{
De-allocate Channel
}
else
{
Re-initialize Channel
}
}
else if (ACK)
{
Reset Error Count
Mask ACK
}
else if (DATATGLERR)
{
Reset Error Count
}
15.4.3.6.6 Control Transactions in DMA Mode
Setup, Data, and Status stages of a control transfer must be performed as three separate transfers. Setup- and Data- or Status-stage
OUT transactions are performed similarly to the bulk OUT transactions explained in 15.4.3.6.7 Bulk and Control OUT/SETUP Transac-
tions in DMA Mode. Data- or Status-stage IN transactions are performed similarly to the bulk IN transactions explained in
15.4.3.6.8 Bulk and Control IN Transactions in DMA Mode. For all three stages, the application is expected to set the
USB_HC1_CHAR.EPTYPE field to Control. During the Setup stage, the application is expected to set the USB_HC1_TSIZ.PID field to
SETUP.
15.4.3.6.7 Bulk and Control OUT/SETUP Transactions in DMA Mode
To initialize the core after power-on reset, the application must follow the sequence in 15.4.1 Overview: Programming the Core. Before
it can communicate with the connected device, it must initialize a channel as described in 15.4.3.1 Channel Initialization.
This section discusses the following topics:
•15.4.3.6.7.1 Overview
•15.4.3.6.7.2 Normal Bulk and Control OUT/SETUP Operations
•15.4.3.6.7.3 NAK Handling with DMA
•15.4.3.6.7.4 Handling Interrupts
15.4.3.6.7.1 Overview
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• The application is attempting to send two maximum-packet-size packets (transfer size = 1,024 bytes).
• The Non-periodic Transmit FIFO can hold two packets (128 bytes for FS).
• The Non-periodic Request Queue depth = 4.
15.4.3.6.7.2 Normal Bulk and Control OUT/SETUP Operations
The sequence of operations in Figure 15.12 Normal Bulk/Control OUT/SETUP and Bulk/Control IN Transactions in Slave Mode on
page 346 is as follows:
1. Initialize and enable channel 1 as explained in 15.4.3.1 Channel Initialization.
2. The host starts fetching the first packet as soon as the channel is enabled. For DMA mode, the host uses the programmed DMA
address to fetch the packet.
3. After fetching the last DWORD of the second (last) packet, the host masks channel 1 internally for further arbitration.
4. The host generates a CHHLTD interrupt as soon as the last packet is sent.
5. In response to the CHHLTD interrupt, de-allocate the channel for other transfers.
The channel-specific interrupt service routine for bulk and control OUT/SETUP transactions in DMA mode is shown in 15.4.3.6.7.4 Han-
dling Interrupts.
15.4.3.6.7.3 NAK Handling with DMA
1. The Host sends a Bulk OUT Transaction.
2. The Device responds with NAK.
3. If the application has unmasked NAK, the core generates the corresponding interrupt(s) to the application. The application is not
required to service these interrupts, since the core takes care of rewinding of buffer pointers and re-initializing the Channel without
application intervention.
4. When the Device returns an ACK, the core continues with the transfer.
Optionally, the application can utilize these interrupts. If utilized by the application:
• The NAK interrupt is masked by the application.
• The core does not generate a separate interrupt when NAK is received by the Host functionality.
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Application Programming Flow
1. The application programs a channel to do a bulk transfer for a particular data size in each transaction.
• Packet Data size can be up to 512 KBytes
• Zero-length data must be programmed as a separate transaction.
2. Program the transfer size register with:
• Transfer size
• Packet count
3. Program the DMA address.
4. Program the USB_HCx_CHAR to enable the channel.
5. The Interrupt handling by the application is as depicted in the flow diagram.
Note: The NAK interrupts are still generated internally. The application can mask off these interrupts from reaching it. The application
can use these interrupts optionally.
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ACK
HostApplication DeviceAHB USB
OUT
DATA0
MPS
1
MPS
1
MPS
init_reg( ch_1)
init_reg( ch_2)
ch_2
ch_2
ch_1
ch_1
De- allocate
(ch_1)
IN
ch_2
ch_2
ch_2
ch_1
ACK
OUT
DATA1
MPS
3
1
ACK
DATA0
IN
ACK
DATA1
1
MPS
1
MPS
1
2
2
5
4
5
De- allocate
(ch_2)
ch_2
8
6
3
4
7
CHHLTD interrupt
CHHLTD interrupt
Non-Periodic Request
Queue
Assume that this queue can
hold 4 entries.
Figure 15.13. Normal Bulk/Control OUT/SETUP and Bulk/Control IN Transactions in DMA Mode
15.4.3.6.7.4 Handling Interrupts
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The channel-specific interrupt service routine for bulk and control OUT/SETUP transactions in DMA mode is shown in the following
code samples.
Start
Unmasked the required
USB_HAINTMSK and
USB_HCx_INTMSK status bits
Interrupt?
Read USB_HAINT to determine the
channel which caused the Interrupt
and read the corresponding
USB_HCx_INT
USB_HCx_INT.
CHHLTD = 1?
USB_HCx_INT.
ACK = 1?
Service based on the other interrupt
status bits namely: AHBERR,
FRMOVRERR, BBLERR and
DATATGLERR
Reset
Err_cnt
USB_HCx_INT.NAK = 1 /
USB_HCx_INT.ACK = 1?
Err_cnt =
Err_cnt+1
1. Reset Err_cnt
2. De-allocate channel
Err_cnt == 3?
De-allocate
channel
1. Reprogram Buffer pointers
2. Re-initialize channel
1. Err_cnt = 1
2. Re-initialize channel
3. Reprogram Buffer pointers
YES
NO
NO
NO
YES
YES,
USB_HCx_INT.XACTERR = 1
YES,
USB_HCx_INT.STALL = 1 or
USB_HCx_INT.XFERCOMPL = 1
NO
YES
NO
YES
Figure 15.14. Interrupt Service Routine for Bulk/Control OUT Transaction in DMA Mode
In the previous figure, the Interrupt Service Routine is not required to handle NAK responses. This is the difference of proposed flow
with respect to current flow. Similar flow is applicable for Control flow also.
The NAK status bits in USB_HCx_INT registers are updated. The application can unmask these interrupts when it requires the core to
generate an interrupt for NAK. The NAK status is updated because during Xact_err scenarios, this status provides a means for the
application to determine whether the Xact_err occurred three times consecutively or there were NAK responses in between two
Xact_err. This provides a mechanism for the application to reset the error counter accordingly. The application must read the NAK/ACK
along with the xact_err. If NAK/ACK is not set, the Xact_err count must be incremented otherwise application must initialize the
Xact_err count to 1.
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Unmask (CHHLTD)
if (CHHLTD)
{
if (XFERCOMPL or STALL)
{
Reset Error Count (Error_count=1)
Mask ACK
De-allocate Channel
}
else if (XACTERR)
{
if (NAK/ACK)
{
Error_count = 1
Re-initialize Channel
Rewind Buffer Pointers
}
else
{
Error_count = Error_count + 1
if (Error_count == 3)
{
De allocate channel
}
else
{
Re-initialize Channel
Rewind Buffer Pointers
}
}
}
}
else if (ACK)
{
Reset Error Count (Error_count=1)
Mask ACK
}
As soon as the channel is enabled, the core attempts to fetch and write data packets, in multiples of the maximum packet size, to the
transmit FIFO when space is available in the transmit FIFO and the Request queue. The core stops fetching as soon as the last packet
is fetched.
15.4.3.6.8 Bulk and Control IN Transactions in DMA Mode
To initialize the core after power-on reset, the application must follow the sequence in 15.4.1 Overview: Programming the Core. Before
it can communicate with the connected device, it must initialize a channel as described in 15.4.3.1 Channel Initialization.
A typical bulk or control IN operation in DMA mode is shown in Figure 15.13 Normal Bulk/Control OUT/SETUP and Bulk/Control IN
Transactions in DMA Mode on page 352. See channel 2 (ch_2).
The assumptions are:
1. The application is attempting to receive two maximum-packet-size packets (transfer size = 1,024 bytes).
2. The receive FIFO can hold at least one maximum-packet-size packet and two status DWORDs per packet (72 bytes for FS).
3. The Non-periodic Request Queue depth = 4.
15.4.3.6.8.1 Normal Bulk and Control IN Operations
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The sequence of operations in Figure 15.13 Normal Bulk/Control OUT/SETUP and Bulk/Control IN Transactions in DMA Mode on page
352 is as follows:
1. Initialize and enable channel 2 as explained in 15.4.3.1 Channel Initialization.
2. The host writes an IN request to the Request queue as soon as channel 2 receives the grant from the arbiter. (Arbitration is per-
formed in a round-robin fashion, with fairness.).
3. The host starts writing the received data to the system memory as soon as the last byte is received with no errors.
4. When the last packet is received, the host sets an internal flag to remove any extra IN requests from the Request queue.
5. The host flushes the extra requests.
6. The final request to disable channel 2 is written to the Request queue. At this point, channel 2 is internally masked for further arbi-
tration.
7. The host generates the CHHLTD interrupt as soon as the disable request comes to the top of the queue.
8. In response to the CHHLTD interrupt, de-allocate the channel for other transfers.
15.4.3.6.8.2 Handling Interrupts
The channel-specific interrupt service routine for bulk and control IN transactions in DMA mode is shown in the following flow:
Unmask (CHHLTD)
if (CHHLTD)
{
if (XFERCOMPL or STALL or BBLERR)
{
Reset Error Count Mask ACK De-allocate Channel
}
else if (XACTERR)
{
if (Error_count == 2)
{
De-allocate Channel
}
else
{
Unmask ACK
Unmask NAK
Unmask DATATGLERR
Increment Error
Count Re-initialize Channel
}
}
}
else if (ACK or NAK or DATATGLERR)
{
Reset Error Count
Mask ACK
Mask NAK
Mask DATATGLERR
}
15.4.3.6.9 Interrupt OUT Transactions in Slave Mode
To initialize the core after power-on reset, the application must follow the sequence in 15.4.1 Overview: Programming the Core. Before
it can communicate with the connected device, it must initialize a channel as described in 15.4.3.1 Channel Initialization. See Figure
15.10 Transmit FIFO Write Task in Slave Mode on page 343 and Figure 15.11 Receive FIFO Read Task in Slave Mode on page 344
for read or write data to and from the FIFO in Slave mode.
A typical interrupt OUT operation in Slave mode is shown in Figure 15.15 Normal Interrupt OUT/IN Transactions in Slave Mode on page
357. See channel 1 (ch_1). The assumptions are:
• The application is attempting to send one packet in every frame (up to 1 maximum packet size), starting with the odd frame (transfer
size = 1,024 bytes).
• The Periodic Transmit FIFO can hold one packet.
• Periodic Request Queue depth = 4.
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15.4.3.6.9.1 Normal Interrupt OUT Operation
The sequence of operations in Figure 15.15 Normal Interrupt OUT/IN Transactions in Slave Mode on page 357 is as follows:
1. Initialize and enable channel 1 as explained in 15.4.3.1 Channel Initialization. The application must set the
USB_HC1_CHAR.ODDFRM bit.
2. Write the first packet for channel 1. For a high-bandwidth interrupt transfer, the application must write the subsequent packets up to
MC (maximum number of packets to be transmitted in the next frame times before switching to another channel).
3. Along with the last DWORD write of each packet, the host writes an entry to the Periodic Request Queue.
4. The host attempts to send an OUT token in the next (odd) frame.
5. The host generates an XFERCOMPL interrupt as soon as the last packet is transmitted successfully.
6. In response to the XFERCOMPL interrupt, reinitialize the channel for the next transfer.
15.4.3.6.9.2 Handling Interrupts
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XFERCOMPL mtermpl
chl
|\
|
|
|
chZ \1l
XFERCOMPL mtermpl
, I \J
9mg)
I
The channel-specific interrupt service routine for Interrupt OUT transactions in Slave mode is shown in the following flow:
USBHostAHBApplication Device
init_reg(ch_1)
write_tx_fifo
(ch_1)
write_tx_fifo
(ch_1)
1
init_reg(ch_2)
1
set_ch_en
(ch_2)
set_ch_en
(ch_2)
read_rx_sts
read_rx_fifo
read_rx_sts
1 MPS
XFERCOMPL interrupt
1 MPS
XFERCOMPL interrupt
RXFLVL interrupt
XFERCOMPL interrupt
ch_2
ch_1
OUT
DATA0
MPS
ACK
DATA0
IN
ACK
OUT
DATA1
MPS
ACK
IN
DATA1
ch_2
ch_1
Periodic Request
Queue
Assume that this queue
can hold 4 entries.
2
2
5
6
6
7
9
8
54
3
4
init_reg(ch_1)
write_tx_fifo
(ch_1)
init_reg(ch_1)
init_reg(ch_2)
1 MPS
1 MPS
Odd
frame
Even
frame
RXFLVL interrupt
3
Figure 15.15. Normal Interrupt OUT/IN Transactions in Slave Mode
Unmask (NAK/XACTERR/STALL/XFERCOMPL/FRMOVRUN)
if (XFERCOMPL)
{
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Reset Error Count
Mask ACK
De-allocate Channel
}
else if (STALL or FRMOVRUN)
{
Mask ACK
Unmask CHHLTD
Disable Channel
if (STALL)
{
Transfer Done = 1
}
}
else if (NAK or XACTERR)
{
Rewind Buffer Pointers
Reset Error Count
Mask ACK
Unmask CHHLTD
Disable Channel
}
else if (CHHLTD)
{
Mask CHHLTD
if (Transfer Done or (Error_count == 3))
{
De-allocate Channel
}
else
{
Re-initialize Channel (in next b_interval - 1 Frame)
}
}
else if (ACK)
{
Reset Error Count
Mask ACK
}
The application is expected to write the data packets into the transmit FIFO when the space is available in the transmit FIFO and the
Request queue up to the count specified in the MC field before switching to another channel. The application uses the
USB_GINTSTS.NPTXFEMP interrupt to find the transmit FIFO space.
15.4.3.6.10 Interrupt IN Transactions in Slave Mode
To initialize the core after power-on reset, the application must follow the sequence in 15.4.1 Overview: Programming the Core. Before
it can communicate with the connected device, it must initialize a channel as described in 15.4.3.1 Channel Initialization. See Figure
15.10 Transmit FIFO Write Task in Slave Mode on page 343 and Figure 15.11 Receive FIFO Read Task in Slave Mode on page 344
for read or write data to and from the FIFO in Slave mode.
A typical interrupt-IN operation in Slave mode is shown in Figure 15.15 Normal Interrupt OUT/IN Transactions in Slave Mode on page
357. See channel 2 (ch_2). The assumptions are:
1. The application is attempting to receive one packet (up to 1 maximum packet size) in every frame, starting with odd. (transfer size
= 1,024 bytes).
2. The receive FIFO can hold at least one maximum-packet-size packet and two status DWORDs per packet (1,031 bytes for FS).
3. Periodic Request Queue depth = 4.
15.4.3.6.10.1 Normal Interrupt IN Operation
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The sequence of operations in Figure 15.15 Normal Interrupt OUT/IN Transactions in Slave Mode on page 357 (channel 2) is as fol-
lows:
1. Initialize channel 2 as explained in 15.4.3.1 Channel Initialization. The application must set the USB_HC2_CHAR.ODDFRM bit.
2. Set the USB_HC2_CHAR.CHENA bit to write an IN request to the Periodic Request Queue. For a high-bandwidth interrupt trans-
fer, the application must write the USB_HC2_CHAR register MC (maximum number of expected packets in the next frame) times
before switching to another channel.
3. The host writes an IN request to the Periodic Request Queue for each USB_HC2_CHAR register write with a CHENA bit set.
4. The host attempts to send an IN token in the next (odd) frame.
5. As soon as the IN packet is received and written to the receive FIFO, the host generates an RXFLVL interrupt.
6. In response to the RXFLVL interrupt, read the received packet status to determine the number of bytes received, then read the
receive FIFO accordingly. The application must mask the RXFLVL interrupt before reading the receive FIFO, and unmask after
reading the entire packet.
7. The core generates the RXFLVL interrupt for the transfer completion status entry in the receive FIFO. The application must read
and ignore the receive packet status when the receive packet status is not an IN data packet (USB_GRXSTSR.PKTSTS !=
0b0010).
8. The core generates an XFERCOMPL interrupt as soon as the receive packet status is read.
9. In response to the XFERCOMPL interrupt, read the USB_HC2_TSIZ.PKTCNT field. If USB_HC2_TSIZ.PKTCNT != 0, disable the
channel (as explained in 15.4.3.2 Halting a Channel) before re-initializing the channel for the next transfer, if any). If
USB_HC2_TSIZ.PKTCNT == 0, reinitialize the channel for the next transfer. This time, the application must reset the
USB_HC2_CHAR.ODDFRM bit.
15.4.3.6.10.2 Handling Interrupts
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The channel-specific interrupt service routine for an interrupt IN transaction in Slave mode is a follows.
Unmask (NAK/XACTERR/XFERCOMPL/BBLERR/STALL/FRMOVRUN/DATATGLERR)
if (XFERCOMPL)
{
Reset Error Count
Mask ACK
if (USB_HCx_TSIZ.PKTCNT == 0)
{
De-allocate Channel
}
else
{
Transfer Done = 1
Unmask CHHLTD
Disable Channel
}
}
else if (STALL or FRMOVRUN or NAK or DATATGLERR or BBLERR)
{
Mask ACK
Unmask CHHLTD
Disable Channel
if (STALL or BBLERR)
{
Reset Error Count
Transfer Done = 1
}
else if (!FRMOVRUN)
{
Reset Error Count
}
}
else if (XACTERR)
{
Increment Error Count
Unmask ACK
Unmask CHHLTD
Disable Channel
}
else if (CHHLTD)
{
Mask CHHLTD
if (Transfer Done or (Error_count == 3))
{
De-allocate Channel
}
else
{
Re-initialize Channel (in next b_interval - 1 Frame)
}
}
else if (ACK)
{
Reset Error Count
Mask ACK
}
The application is expected to write the requests for the same channel when the Request queue space is available up to the count
specified in the MC field before switching to another channel (if any).
15.4.3.6.11 Interrupt OUT Transactions in DMA Mode
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To initialize the core after power-on reset, the application must follow the sequence in 15.4.1 Overview: Programming the Core. Before
it can communicate with the connected device, it must initialize a channel as described in 15.4.3.1 Channel Initialization.
A typical interrupt OUT operation in DMA mode is shown in Figure 15.16 Normal Interrupt OUT/IN Transactions in DMA Mode on page
363. See channel 1 (ch_1). The assumptions are:
• The application is attempting to transmit one packet in every frame (up to 1 maximum packet size of 1,024 bytes).
• The Periodic Transmit FIFO can hold one packet (1 KB for FS).
• Periodic Request Queue depth = 4.
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15.4.3.6.11.1 Normal Interrupt OUT Operation
1. Initialize and enable channel 1 as explained in 15.4.3.1 Channel Initialization.
2. The host starts fetching the first packet as soon the channel is enabled and writes the OUT request along with the last DWORD
fetch. In high-bandwidth transfers, the host continues fetching the next packet (up to the value specified in the MC field) before
switching to the next channel.
3. The host attempts to send the OUT token in the beginning of the next odd frame.
4. After successfully transmitting the packet, the host generates a CHHLTD interrupt.
5. In response to the CHHLTD interrupt, reinitialize the channel for the next transfer.
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|\
I
I
I
I ch72 \fil
I
‘7
c:
HI
USBHostAHBApplication Device
init_reg(ch_1)
1
init_reg(ch_2)
1
1 MPS
CHHLTD interrupt
1 MPS
CHHLTD interrupt
XFERCOMPL interrupt
ch_2
ch_1
OUT
DATA0
MPS
ACK
DATA0
IN
ACK
OUT
DATA1
MPS
ACK
IN
DATA1
ch_2
ch_1
Periodic Request
Queue
Assume that this queue
can hold 4 entries.
4
5
5
4
3
2
3
init_reg(ch_1)
init_reg(ch_1)
init_reg(ch_2)
1 MPS
1 MPS
Odd
frame
Even
frame
2
Figure 15.16. Normal Interrupt OUT/IN Transactions in DMA Mode
15.4.3.6.11.2 Handling Interrupts
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The following code sample shows the channel-specific ISR for an interrupt OUT transaction in DMA mode.
Unmask (CHHLTD)
if (CHHLTD)
{
if (XFERCOMPL)
{
Reset Error Count
Mask ACK
if (Transfer Done)
{
De-allocate Channel
}
else
{
Re-initialize Channel (in next b_interval - 1 Frame)
}
}
else if (STALL)
{
Transfer Done = 1
Reset Error Count
Mask ACK
De-allocate Channel
}
else if (NAK or FRMOVRUN)
{
Mask ACK
Rewind Buffer Pointers
Re-initialize Channel (in next b_interval - 1 Frame)
if (NAK)
{
Reset Error Count
}
}
else if (XACTERR)
{
if (Error_count == 2)
{
De-allocate Channel
}
else
{
Increment Error Count
Rewind Buffer Pointers
Unmask ACK
Re-initialize Channel (in next b_interval - 1 Frame)
}
}
}
else if (ACK)
{
Reset Error Count
Mask ACK
}
As soon as the channel is enabled, the core attempts to fetch and write data packets, in maximum packet size multiples, to the transmit
FIFO when the space is available in the transmit FIFO and the Request queue. The core stops fetching as soon as the last packet is
fetched (the number of packets is determined by the MC field of the USB_HCx_CHAR register).
15.4.3.6.12 Interrupt IN Transactions in DMA Mode
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To initialize the core after power-on reset, the application must follow the sequence in 15.4.1 Overview: Programming the Core. Before
it can communicate with the connected device, it must initialize a channel as described in 15.4.3.1 Channel Initialization.
A typical interrupt IN operation in DMA mode is shown in Figure 15.16 Normal Interrupt OUT/IN Transactions in DMA Mode on page
363. See channel 2 (ch_2). The assumptions are:
• The application is attempting to receive one packet in every frame (up to 1 maximum packet size of 1,024 bytes).
• The receive FIFO can hold at least one maximum-packet-size packet and two status DWORDs per packet (1,032 bytes for FS).
• Periodic Request Queue depth = 4.
15.4.3.6.12.1 Normal Interrupt IN Operation
The sequence of operations in Figure 15.16 Normal Interrupt OUT/IN Transactions in DMA Mode on page 363 (channel 2) is as follows:
1. Initialize and enable channel 2 as explained in 15.4.3.1 Channel Initialization.
2. The host writes an IN request to the Request queue as soon as the channel 2 gets the grant from the arbiter (round-robin with
fairness). In high-bandwidth transfers, the host writes consecutive writes up to MC times.
3. The host attempts to send an IN token at the beginning of the next (odd) frame.
4. As soon the packet is received and written to the receive FIFO, the host generates a CHHLTD interrupt.
5. In response to the CHHLTD interrupt, reinitialize the channel for the next transfer.
15.4.3.6.12.2 Handling Interrupts
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The channel-specific interrupt service routine for Interrupt IN transactions in DMA mode is as follows.
Unmask (CHHLTD)
if (CHHLTD)
{
if (XFERCOMPL)
{
Reset Error Count
Mask ACK
if (Transfer Done)
{
De-allocate Channel
}
else
{
Re-initialize Channel (in next b_interval - 1 Frame)
}
}
else if (STALL or BBLERR)
{
Reset Error Count
Mask ACK
De-allocate Channel
}
else if (NAK or DATATGLERR or FRMOVRUN)
{
Mask ACK
Re-initialize Channel (in next b_interval - 1 Frame)
if (DATATGLERR or NAK)
{
Reset Error Count
}
}
else if (XACTERR)
{
if (Error_count == 2)
{
De-allocate Channel
}
else
{
Increment Error Count
Unmask ACK
Re-initialize Channel (in next b_interval - 1 Frame)
}
}
}
else if (ACK)
{
Reset Error Count
Mask ACK
}
As soon as the channel is enabled, the core attempts to write the requests into the Request queue when the space is available up to
the count specified in the MC field.
15.4.3.6.13 Isochronous OUT Transactions in Slave Mode
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To initialize the core after power-on reset, the application must follow the sequence in 15.4.1 Overview: Programming the Core. Before
it can communicate with the connected device, it must initialize a channel as described in 15.4.3.1 Channel Initialization. See Figure
15.10 Transmit FIFO Write Task in Slave Mode on page 343 and Figure 15.11 Receive FIFO Read Task in Slave Mode on page 344
for read or write data to and from the FIFO in Slave mode.
A typical isochronous OUT operation in Slave mode is shown in Figure 15.17 Normal Isochronous OUT/IN Transactions in Slave Mode
on page 368. See channel 1 (ch_1). The assumptions are:
• The application is attempting to send one packet every frame (up to 1 maximum packet size), starting with an odd frame. (transfer
size = 1,024 bytes).
• The Periodic Transmit FIFO can hold one packet (1 KB).
• Periodic Request Queue depth = 4.
15.4.3.6.13.1 Normal Isochronous OUT Operation
The sequence of operations in Figure 15.18 Normal Isochronous OUT/IN Transactions in DMA Mode on page 371 (channel 1) is as
follows:
1. Initialize and enable channel 1 as explained in 15.4.3.1 Channel Initialization. The application must set the
USB_HC1_CHAR.ODDFRM bit.
2. Write the first packet for channel 1. For a high-bandwidth isochronous transfer, the application must write the subsequent packets
up to MC (maximum number of packets to be transmitted in the next frame) times before switching to another channel.
3. Along with the last DWORD write of each packet, the host writes an entry to the Periodic Request Queue.
4. The host attempts to send the OUT token in the next frame (odd).
5. The host generates the XFERCOMPL interrupt as soon as the last packet is transmitted successfully.
6. In response to the XFERCOMPL interrupt, reinitialize the channel for the next transfer.
15.4.3.6.13.2 Handling Interrupts
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|
|
|
| |
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chl | I
Ch 2 I 4 I
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The channel-specific interrupt service routine for isochronous OUT transactions in Slave mode is shown in the following flow:
USBHostAHBApplication Device
init_reg(ch_1)
write_tx_fifo
(ch_1)
write_tx_fifo
(ch_1)
1
init_reg(ch_2)
1
set_ch_en
(ch_2)
set_ch_en
(ch_2)
read_rx_sts
read_rx_fifo
read_rx_sts
1 MPS
XFERCOMPL interrupt
1 MPS
XFERCOMPL interrupt
RXFLVL interrupt
XFERCOMPL interrupt
ch_2
ch_1
OUT
DATA0
MPS
DATA0
IN
OUT
DATA1
MPS
IN
DATA0
ch_2
ch_1
Periodic Request
Queue
Assume that this queue
can hold 4 entries.
2
2
5
6
6
7
9
8
5
4
3
4
init_reg(ch_1)
write_tx_fifo
(ch_1)
init_reg(ch_1)
init_reg(ch_2)
1 MPS
1 MPS
Odd
frame
Even
frame
RXFLVL interrupt
3
Figure 15.17. Normal Isochronous OUT/IN Transactions in Slave Mode
Unmask (FRMOVRUN/XFERCOMPL)
if (XFERCOMPL)
{
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De-allocate Channel
}
else if (FRMOVRUN)
{
Unmask CHHLTD
Disable Channel
}
else if (CHHLTD)
{
Mask CHHLTD
De-allocate Channel
}
15.4.3.6.14 Isochronous IN Transactions in Slave Mode
To initialize the core after power-on reset, the application must follow the sequence in 15.4.1 Overview: Programming the Core. Before
it can communicate with the connected device, it must initialize a channel as described in 15.4.3.1 Channel Initialization. See Figure
15.10 Transmit FIFO Write Task in Slave Mode on page 343 and Figure 15.11 Receive FIFO Read Task in Slave Mode on page 344
for read or write data to and from the FIFO in Slave mode.
A typical isochronous IN operation in Slave mode is shown in Figure 15.17 Normal Isochronous OUT/IN Transactions in Slave Mode on
page 368. See channel 2 (ch_2). The assumptions are:
• The application is attempting to receive one packet (up to 1 maximum packet size) in every frame starting with the next odd frame.
(transfer size = 1,024 bytes).
• The receive FIFO can hold at least one maximum-packet-size packet and two status DWORDs per packet (1,031 bytes for FS).
• Periodic Request Queue depth = 4.
15.4.3.6.14.1 Normal Isochronous IN Operation
The sequence of operations in Figure 15.17 Normal Isochronous OUT/IN Transactions in Slave Mode on page 368 (channel 2) is as
follows:
1. Initialize channel 2 as explained in 15.4.3.1 Channel Initialization. The application must set the USB_HC2_CHAR.ODDFRM bit.
2. Set the USB_HC2_CHAR.CHENA bit to write an IN request to the Periodic Request Queue. For a high-bandwidth isochronous
transfer, the application must write the USB_HC2_CHAR register MC (maximum number of expected packets in the next frame)
times before switching to another channel.
3. The host writes an IN request to the Periodic Request Queue for each USB_HC2_CHAR register write with the CHENA bit set.
4. The host attempts to send an IN token in the next odd frame.
5. As soon as the IN packet is received and written to the receive FIFO, the host generates an RXFLVL interrupt.
6. In response to the RXFLVL interrupt, read the received packet status to determine the number of bytes received, then read the
receive FIFO accordingly. The application must mask the RXFLVL interrupt before reading the receive FIFO, and unmask it after
reading the entire packet.
7. The core generates an RXFLVL interrupt for the transfer completion status entry in the receive FIFO. This time, the application
must read and ignore the receive packet status when the receive packet status is not an IN data packet
(USB_GRXSTSR.PKTSTS != 0b0010).
8. The core generates an XFERCOMPL interrupt as soon as the receive packet status is read.
9. In response to the XFERCOMPL interrupt, read the USB_HC2_TSIZ.PKTCNT field. If USB_HC2_TSIZ.PKTCNT != 0, disable the
channel (as explained in 15.4.3.2 Halting a Channel) before re-initializing the channel for the next transfer, if any. If
USB_HC2_TSIZ.PKTCNT == 0, reinitialize the channel for the next transfer. This time, the application must reset the
USB_HC2_CHAR.ODDFRM bit.
15.4.3.6.14.2 Handling Interrupts
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The channel-specific interrupt service routine for an isochronous IN transaction in Slave mode is as follows.
Unmask (XACTERR/XFERCOMPL/FRMOVRUN/BBLERR)
if (XFERCOMPL or FRMOVRUN)
{
if (XFERCOMPL and (USB_HCx_TSIZ.PKTCNT == 0))
{
Reset Error Count
De-allocate Channel
}
else
{
Unmask CHHLTD
Disable Channel
}
}
else if (XACTERR or BBLERR)
{
Increment Error Count
Unmask CHHLTD
Disable Channel
}
else if (CHHLTD)
{
Mask CHHLTD
if (Transfer Done or (Error_count == 3))
{
De-allocate Channel
}
else
{
Re-initialize Channel
}
}
15.4.3.6.15 Isochronous OUT Transactions in DMA Mode
To initialize the core after power-on reset, the application must follow the sequence in 15.4.1 Overview: Programming the Core. Before
it can communicate with the connected device, it must initialize a channel as described in 15.4.3.1 Channel Initialization.
A typical isochronous OUT operation in DMA mode is shown in Figure 15.18 Normal Isochronous OUT/IN Transactions in DMA Mode
on page 371. See channel 1 (ch_1). The assumptions are:
• The application is attempting to transmit one packet every frame (up to 1 maximum packet size of 1,024 bytes).
• The Periodic Transmit FIFO can hold one packet (1 KB).
• Periodic Request Queue depth = 4.
15.4.3.6.15.1 Normal Isochronous OUT Operation
1. Initialize and enable channel 1 as explained in 15.4.3.1 Channel Initialization.
2. The host starts fetching the first packet as soon as the channel is enabled, and writes the OUT request along with the last DWORD
fetch. In high-bandwidth transfers, the host continues fetching the next packet (up to the value specified in the MC field) before
switching to the next channel.
3. The host attempts to send an OUT token in the beginning of the next (odd) frame.
4. After successfully transmitting the packet, the host generates a CHHLTD interrupt.
5. In response to the CHHLTD interrupt, reinitialize the channel for the next transfer.
15.4.3.6.15.2 Handling Interrupts
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1 MP3 DATAO
CHHLTD Inlermpl
chl
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chZ \1l
DATAO
The channel-specific interrupt service routine for Isochronous OUT transactions in DMA mode is shown in the following flow:
USBHostAHBApplication Device
init_reg(ch_1)
1
init_reg(ch_2)
1
1 MPS
CHHLTD interrupt
1 MPS
CHHLTD interrupt
CHHLTD interrupt
ch_2
ch_1
OUT
DATA0
MPS
DATA0
IN
OUT
DATA1
MPS
IN
DATA0
ch_2
ch_1
Periodic Request
Queue
Assume that this queue
can hold 4 entries.
4
5
5
4
3
2
3
init_reg(ch_1)
init_reg(ch_1)
init_reg(ch_2)
1 MPS
1 MPS
Odd
frame
Even
frame
2
Figure 15.18. Normal Isochronous OUT/IN Transactions in DMA Mode
Unmask (CHHLTD)
if (CHHLTD)
{
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if (XFERCOMPL or FRMOVRUN)
{
De-allocate Channel
}
}
15.4.3.6.16 Isochronous IN Transactions in DMA Mode
To initialize the core after power-on reset, the application must follow the sequence in 15.4.1 Overview: Programming the Core. Before
it can communicate with the connected device, it must initialize a channel as described in 15.4.3.1 Channel Initialization.
A typical isochronous IN operation in DMA mode is shown in Figure 15.18 Normal Isochronous OUT/IN Transactions in DMA Mode on
page 371. See channel 2 (ch_2). The assumptions are:
• The application is attempting to receive one packet in every frame (up to 1 maximum packet size of 1,024 bytes).
• The receive FIFO can hold at least one maximum-packet-size packet and two status DWORDS per packet (1,031 bytes).
• Periodic Request Queue depth = 4.
15.4.3.6.16.1 Normal Isochronous IN Operation
The sequence of operations in Figure 15.18 Normal Isochronous OUT/IN Transactions in DMA Mode on page 371 (channel 2) is as
follows:
1. Initialize and enable channel 2 as explained in 15.4.3.1 Channel Initialization.
2. The host writes an IN request to the Request queue as soon as the channel 2 gets the grant from the arbiter (round-robin with
fairness). In high-bandwidth transfers, the host performs consecutive writes up to MC times.
3. The host attempts to send an IN token at the beginning of the next (odd) frame.
4. As soon the packet is received and written to the receive FIFO, the host generates a CHHLTD interrupt.
5. In response to the CHHLTD interrupt, reinitialize the channel for the next transfer.
15.4.3.6.16.2 Handling Interrupts
The channel-specific interrupt service routine for an isochronous IN transaction in DMA mode is as follows.
Unmask (CHHLTD)
if (CHHLTD)
{
if (XFERCOMPL or FRMOVRUN)
{
if (XFERCOMPL and (USB_HCx_TSIZ.PKTCNT == 0))
{
Reset Error Count
De-allocate Channel
}
else
{
De-allocate Channel
}
}
else if (XACTERR or BBLERR)
{
if (Error_count == 2)
{
De-allocate Channel
}
else
{
Increment Error Count
Re-enable Channel (in next b_interval - 1 Frame)
}
}
}
15.4.4 Device Programming Model
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Before you program the Device, be sure to read 15.4.1 Overview: Programming the Core and 15.4.2 Modes of Operation.
15.4.4.1 Endpoint Initialization
This section addresses the following topics:
•15.4.4.1.1 Initialization on USB Reset
•15.4.4.1.2 Initialization on Enumeration Completion
•15.4.4.1.3 Initialization on SetAddress Command
•15.4.4.1.4 Initialization on SetConfiguration/SetInterface Command
•15.4.4.1.5 Endpoint Activation
•15.4.4.1.6 Endpoint Deactivation
•15.4.4.1.7 Device DMA/Slave Mode Initialization
15.4.4.1.1 Initialization on USB Reset
1. Set the NAK bit for all OUT endpoints
• USB_DOEPx_CTL.SNAK = 1 (for all OUT endpoints)
2. Unmask the following interrupt bits:
• USB_USB_DAINTMSK.INEP0 = 1 (control 0 IN endpoint)
• USB_USB_DAINTMSK.OUTEP0 = 1 (control 0 OUT endpoint)
• USB_DOEPMSK.SETUP = 1
• USB_DOEPMSK.XFERCOMPL = 1
• USB_DIEPMSK.XFERCOMPL = 1
• USB_DIEPMSK.TIMEOUTMSK = 1
3. To transmit or receive data, the device must initialize more registers as specified in 15.4.4.1.7 Device DMA/Slave Mode Initializa-
tion.
4. Set up the Data FIFO RAM for each of the FIFOs
• Program the USB_GRXFSIZ Register, to be able to receive control OUT data and setup data. At a minimum, this must be equal
to 1 max packet size of control endpoint 0 + 2 DWORDs (for the status of the control OUT data packet) + 10 DWORDs (for
setup packets).
• Program the Device IN Endpoint Transmit FIFO size register (depending on the FIFO number chosen), to be able to transmit
control IN data. At a minimum, this must be equal to 1 max packet size of control endpoint 0.
5. Program the following fields in the endpoint-specific registers for control OUT endpoint 0 to receive a SETUP packet
• USB_DOEP0TSIZ.SUPCNT = 3 (to receive up to 3 back-to-back SETUP packets)
• In DMA mode, USB_DOEP0DMAADDR register with a memory address to store any SETUP packets received
At this point, all initialization required to receive SETUP packets is done, except for enabling control OUT endpoint 0 in DMA mode.
15.4.4.1.2 Initialization on Enumeration Completion
1. On the Enumeration Done interrupt (USB_GINTSTS.ENUMDONE), read the USB_DSTS register to determine the enumeration
speed.
2. Program the USB_DIEP0CTL.MPS field to set the maximum packet size. This step configures control endpoint 0. The maximum
packet size for a control endpoint depends on the enumeration speed.
3. In DMA mode, program the USB_DOEP0CTL register to enable control OUT endpoint 0, to receive a SETUP packet.
• USB_DOEP0CTL.EPENA = 1
At this point, the device is ready to receive SOF packets and is configured to perform control transfers on control endpoint 0.
15.4.4.1.3 Initialization on SetAddress Command
This section describes what the application must do when it receives a SetAddress command in a SETUP packet.
1. Program the USB_DCFG register with the device address received in the SetAddress command.
2. Program the core to send out a status IN packet.
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15.4.4.1.4 Initialization on SetConfiguration/SetInterface Command
This section describes what the application must do when it receives a SetConfiguration or SetInterface command in a SETUP packet.
1. When a SetConfiguration command is received, the application must program the endpoint registers to configure them with the
characteristics of the valid endpoints in the new configuration.
2. When a SetInterface command is received, the application must program the endpoint registers of the endpoints affected by this
command.
3. Some endpoints that were active in the prior configuration or alternate setting are not valid in the new configuration or alternate
setting. These invalid endpoints must be deactivated.
4. For details on a particular endpoint’s activation or deactivation, see 15.4.4.1.5 Endpoint Activation and 15.4.4.1.6 Endpoint Deacti-
vation.
5. Unmask the interrupt for each active endpoint and mask the interrupts for all inactive endpoints in the USB_USB_DAINTMSK reg-
ister.
6. Set up the Data FIFO RAM for each FIFO. See 15.4.7.1 Data FIFO RAM Allocation for more detail.
7. After all required endpoints are configured, the application must program the core to send a status IN packet.
At this point, the device core is configured to receive and transmit any type of data packet.
15.4.4.1.5 Endpoint Activation
This section describes the steps required to activate a device endpoint or to configure an existing device endpoint to a new type.
1. Program the characteristics of the required endpoint into the following fields of the USB_DIEPx_CTL register (for IN or bidirectional
endpoints) or the USB_DOEPx_CTL register (for OUT or bidirectional endpoints).
• Maximum Packet Size
• USB Active Endpoint = 1
• Endpoint Start Data Toggle (for interrupt and bulk endpoints)
• Endpoint Type
• TxFIFO Number
2. Once the endpoint is activated, the core starts decoding the tokens addressed to that endpoint and sends out a valid handshake
for each valid token received for the endpoint.
15.4.4.1.6 Endpoint Deactivation
This section describes the steps required to deactivate an existing endpoint.
1. In the endpoint to be deactivated, clear the USB Active Endpoint bit in the USB_DIEPx_CTL register (for IN or bidirectional end-
points) or the USB_DOEPx_CTL register (for OUT or bidirectional endpoints).
2. Once the endpoint is deactivated, the core ignores tokens addressed to that endpoint, resulting in a timeout on the USB.
15.4.4.1.7 Device DMA/Slave Mode Initialization
The application must meed the following conditions to set up the device core to handle traffic.
• In Slave mode, USB_GINTMSK.NPTXFEMPMSK, and USB_GINTMSK.RXFLVLMSK must be unset.
• In DMA mode, the aforementioned interrupts must be masked.
15.4.4.1.8 Transfer Stop Process
When the core is operating as a device, use the following programing sequence if you want to stop any transfers (because of an inter-
rupt from the host, typically a reset).
15.4.4.1.8.1 Transfer Stop Programming Flow for IN Endpoints
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Sequence of operations:
1. Disable the IN endpoint by programming USB_DIEP0CTL/USB_DIEPx_CTL.EPDIS = 1.
2. Wait for the USB_DIEPx_INT.EPDISBLD interrupt, which indicates that the IN endpoint is completely disabled. When the EP-
DISBLD interrupt is asserted, the core clears the following bits:
• USB_DIEP0CTL/USB_DIEPx_CTL.EPDIS = 0
• USB_DIEP0CTL/USB_DIEPx_CTL.EPENA = 0
3. Flush the TX FIFO by programming the following bits:
• USB_GRSTCTL.TXFFLSH = 1
• USB_GRSTCTL.TXFNUM = FIFO number specific to endpoint
4. The application can start polling till USB_GRSTCTL.TXFFLSH is cleared. When this bit is cleared, it ensures that there is no data
left in the TX FIFO.
15.4.4.1.8.2 Transfer Stop Programming Flow for OUT Endpoints
Sequence of operations:
1. Enable all OUT endpoints by setting USB_DOEP0CTL/USB_DOEPx_CTL.EPENA = 1.
2. Before disabling any OUT endpoint, the application must enable Global OUT NAK mode in the core, according to the instructions in
15.4.4.2.2.5 Setting the Global OUT NAK. This ensures that data in the RX FIFO is sent to the application successfully. Set
USB_DCTL.USB_DCTL.SGOUTNAK = 1.
3. Wait for the USB_GINTSTS.GOUTNAKEFF interrupt.
4. Disable all active OUT endpoints by programming the following register bits:
• USB_DOEP0CTL/USB_DOEPx_CTL.EPENA = 1
• USB_DOEP0CTL/USB_DOEPx_CTL.EPDIS = 1
• USB_DOEP0CTL/USB_DOEPx_CTL.SNAK = 1
5. Wait for the USB_DOEP0INT/USB_DOEPx_INT.EPDISBLD interrupt for each OUT endpoint programmed in the previous step.
The USB_DOEP0INT/USB_DOEPx_INT.EPDISBLD interrupt indicates that the corresponding OUT endpoint is completely disa-
bled. When the EPDISBLD interrupt is asserted, the core clears the following bits:
• USB_DOEP0CTL/USB_DOEPx_CTL.EPENA = 0
• USB_DOEP0CTL/USB_DOEPx_CTL.EPDIS = 0
Note: The application must not flush the Rx FIFO, as the Global OUT NAK effective interrupt earlier ensures that there is no data left in
the Rx FIFO.
15.4.4.2 Device Programming Operations
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The table below provides links to the programming sequence for different USB transaction types.
Table 15.2. Transaction Programming Sequences
Device Mode IN SETUP OUT
Control
Slave 15.4.4.2.3.11 Generic Non-Peri-
odic (Bulk and Control) IN Data
Transfers in DMA and Slave
Mode
15.4.4.2.1 OUT Data Transfers
in Slave and DMA Modes
15.4.4.2.2.8 Generic Non-Iso-
chronous OUT Data Transfers
in DMA and Slave Modes
DMA 15.4.4.2.3.11 Generic Non-Peri-
odic (Bulk and Control) IN Data
Transfers in DMA and Slave
Mode
15.4.4.2.1 OUT Data Transfers
in Slave and DMA Modes
15.4.4.2.2.8 Generic Non-Iso-
chronous OUT Data Transfers
in DMA and Slave Modes
Bulk
Slave 15.4.4.2.3.11 Generic Non-Peri-
odic (Bulk and Control) IN Data
Transfers in DMA and Slave
Mode
—15.4.4.2.2.8 Generic Non-Iso-
chronous OUT Data Transfers
in DMA and Slave Modes
DMA 15.4.4.2.3.11 Generic Non-Peri-
odic (Bulk and Control) IN Data
Transfers in DMA and Slave
Mode
—15.4.4.2.2.8 Generic Non-Iso-
chronous OUT Data Transfers
in DMA and Slave Modes
Interrupt
Slave 15.4.4.2.3.13 Generic Periodic
IN (Interrupt and Isochronous)
Data Transfers and
15.4.4.2.3.14 Generic Periodic
IN Data Transfers Using the Pe-
riodic Transfer Interrupt Feature
—15.4.4.2.2.8 Generic Non-Iso-
chronous OUT Data Transfers
in DMA and Slave Modes and
15.4.4.2.2.10 Generic Interrupt
OUT Data Transfers Using Peri-
odic Transfer Interrupt Feature
DMA 15.4.4.2.3.13 Generic Periodic
IN (Interrupt and Isochronous)
Data Transfers and
15.4.4.2.3.14 Generic Periodic
IN Data Transfers Using the Pe-
riodic Transfer Interrupt Feature
—15.4.4.2.2.8 Generic Non-Iso-
chronous OUT Data Transfers
in DMA and Slave Modes and
15.4.4.2.2.10 Generic Interrupt
OUT Data Transfers Using Peri-
odic Transfer Interrupt Feature
Isochronous
Slave 15.4.4.2.3.13 Generic Periodic
IN (Interrupt and Isochronous)
Data Transfers
—15.4.4.2.2.2 Control Read
Transfers (SETUP, Data IN,
Status OUT) and
15.4.4.2.2.12 Incomplete Iso-
chronous OUT Data Transfers
in DMA and Slave Modes
DMA 15.4.4.2.3.13 Generic Periodic
IN (Interrupt and Isochronous)
Data Transfers and
15.4.4.2.3.14 Generic Periodic
IN Data Transfers Using the Pe-
riodic Transfer Interrupt Feature
—15.4.4.2.2.2 Control Read
Transfers (SETUP, Data IN,
Status OUT) and
15.4.4.2.2.12 Incomplete Iso-
chronous OUT Data Transfers
in DMA and Slave Modes
15.4.4.2.1 OUT Data Transfers in Slave and DMA Modes
This section describes the internal data flow and application-level operations during data OUT transfers and setup transactions.
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15.4.4.2.1.1 Control Setup Transactions
This section describes how the core handles SETUP packets and the application’s sequence for handling setup transactions. To initial-
ize the core after power-on reset, the application must follow the sequence in 15.4.1 Overview: Programming the Core. Before it can
communicate with the host, it must initialize an endpoint as described in 15.4.4.1 Endpoint Initialization. See 15.4.4.2.2.4 Packet Read
from FIFO in Slave Mode.
Application Requirements
1. To receive a SETUP packet, the USB_DOEPx_TSIZ.SUPCNT field in a control OUT endpoint must be programmed to a non-zero
value. When the application programs the SUPCNT field to a non-zero value, the core receives SETUP packets and writes them to
the receive FIFO, irrespective of the USB_DOEPx_CTL.NAK status and USB_DOEPx_CTL.EPENA bit setting. The SUPCNT field
is decremented every time the control endpoint receives a SETUP packet. If the SUPCNT field is not programmed to a proper val-
ue before receiving a SETUP packet, the core still receives the SETUP packet and decrements the SUPCNT field, but the applica-
tion possibly is not be able to determine the correct number of SETUP packets received in the Setup stage of a control transfer.
• USB_DOEPx_TSIZ.SUPCNT = 3
2. In DMA mode, the OUT endpoint must also be enabled, to transfer the received SETUP packet data from the internal receive FIFO
to the external memory.
• USB_DOEPx_CTL.EPENA = 1
3. The application must always allocate some extra space in the Receive Data FIFO, to be able to receive up to three SETUP packets
on a control endpoint.
• The space to be Reserved is (4 * n) + 6 DWORDs, where n is the number of control endpoints supported by the device. Three
DWORDs are required for the first SETUP packet, 1 DWORD is required for the Setup Stage Done DWORD, and 6 DWORDs
are required to store two extra SETUP packets among all control endpoints.
• 3 DWORDs per SETUP packet are required to store 8 bytes of SETUP data and 4 bytes of SETUP status (Setup Packet Pat-
tern). The core reserves this space in the receive data.
• FIFO to write SETUP data only, and never uses this space for data packets.
4. In Slave mode, the application must read the 2 DWORDs of the SETUP packet from the receive FIFO. In DMA mode, the core
writes the 2 DWORDs of SETUP data to the memory.
5. The application must read and discard the Setup Stage Done DWORD from the receive FIFO.
Internal Data Flow
1. When a SETUP packet is received, the core writes the received data to the receive FIFO, without checking for available space in
the receive FIFO and irrespective of the endpoint’s NAK and Stall bit settings.
• The core internally sets the IN NAK and OUT NAK bits for the control IN/OUT endpoints on which the SETUP packet was re-
ceived.
2. For every SETUP packet received on the USB, 3 DWORDs of data is written to the receive FIFO, and the SUPCNT field is decre-
mented by 1.
• The first DWORD contains control information used internally by the core
• The second DWORD contains the first 4 bytes of the SETUP command
• The third DWORD contains the last 4 bytes of the SETUP command
3. When the Setup stage changes to a Data IN/OUT stage, the core writes an entry (Setup Stage Done DWORD) to the receive
FIFO, indicating the completion of the Setup stage.
4. On the AHB side, SETUP packets are emptied either by the DMA or the application. In DMA mode, the SETUP packets (2
DWORDs) are written to the memory location programmed in the USB_DOEPx_DMAADDR register, only if the endpoint is ena-
bled. If the endpoint is not enabled, the data remains in the receive FIFO until the enable bit is set.
5. When either the DMA or the application pops the Setup Stage Done DWORD from the receive FIFO, the core interrupts the appli-
cation with a USB_DOEPx_INT.SETUP interrupt, indicating it can process the received SETUP packet.
• The core clears the endpoint enable bit for control OUT endpoints.
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Application Programming Sequence
1. Program the USB_DOEPx_TSIZ register.
• USB_DOEPx_TSIZ.SUPCNT = 3
2. In DMA mode, program the USB_DOEPx_DMAADDR register and USB_DOEPx_CTL register with the endpoint characteristics
and set the Endpoint Enable bit (USB_DOEPx_CTL.EPENA).
• Endpoint Enable = 1
3. In Slave mode, wait for the USB_GINTSTS.RXFLVL interrupt and empty the data packets from the receive FIFO, as explained in
15.4.4.2.2.4 Packet Read from FIFO in Slave Mode. This step can be repeated many times.
4. Assertion of the USB_DOEPx_INT.SETUP interrupt marks a successful completion of the SETUP Data Transfer.
• On this interrupt, the application must read the USB_DOEPx_TSIZ register to determine the number of SETUP packets re-
ceived and process the last received SETUP packet.
• In DMA mode, the application must also determine if the interrupt bit USB_DOEPx_INT.BACK2BACKSETUP is set. This bit is
set if the core has received more than three back-to-back SETUP packets. If this is the case, the application must ignore the
USB_DOEPx_TSIZ.SUPCNT value and use the USB_DOEPx_DMAADDR directly to read out the last SETUP packet received.
USB_DOEPx_DMAADDR-8 provides the pointer to the last valid SETUP data.
Note: If the application has not enabled EP0 before the host sends the SETUP packet, the core ACKs the SETUP packet and stores it
in the FIFO, but does not write to the memory until EP0 is enabled. When the application enables the EP0 (first enable) and clears the
NAK bit at the same time the Host sends DATA OUT, the DATA OUT is stored in the RxFIFO. The OTG core then writes the setup data
to the memory and disables the endpoint. Though the application expects a Transfer Complete interrupt for the Data OUT phase, this
does not occur, because the SETUP packet, rather than the DATA OUT packet, enables EP0 the first time. Thus, the DATA OUT pack-
et is still in the RxFIFO until the application re-enables EP0. The application must enable EP0 one more time for the core to process the
DATA OUT packet.
The following figure charts this flow:
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Wait for
USB_DOEPx_INT.SETUP
Back2Back Setup
Interrupt bit set ?
Find setup cmd type
ctr-rd/wr/2 stage
setup_np_in_pkt
Sata IN phase
Setup_addr =
Rd_Reg(USB_DOEPx_DMA
rem_supcnt =
Rd_Reg(USB_DOEPx_TSIZ)
setup_cmd[31:0] = mem[4-2 * rem_supcnt]
setup_cmd[63:32] = mem[5-2 * rem_supcnt]
setup_cmd[31:0] = mem[setup_addr-8]
setup_cmd[63:32] = mem[setup_addr-4]
setup_np_in_pkt
Data IN phase
rcv_out_pkt
Data OUT phase
NO YES
Read Write
2-stage
Figure 15.19. Processing a SETUP Packet
15.4.4.2.1.2 Handling More Than Three Back-to-Back SETUP Packets
Per the USB 2.0 specification, normally, during a SETUP packet error, a host does not send more than three back-to-back SETUP
packets to the same endpoint. However, the USB 2.0 specification does not limit the number of back-to-back SETUP packets a host
can send to the same endpoint. When this condition occurs, the core generates an interrupt (USB_DOEPx_INT.BACK2BACKSETUP).
In DMA mode, the core also rewinds the DMA address for that endpoint (USB_DOEPx_DMAADDR) and overwrites the first SETUP
packet in system memory with the fourth, second with the fifth, and so on. If the BACK2BACKSETUP interrupt is asserted, the applica-
tion must read the OUT endpoint DMA register (USB_DOEPx_DMAADDR) to determine the final SETUP data in system memory.
In DMA mode, the application can mask the BACK2BACKSETUP interrupt, but after receiving the DOEPINT.SETUP interrupt, the ap-
plication can read the DOEPINT.BACK2BACKSETUP interrupt bit. In Slave mode, the application can use the USB_GINTSTS.RXFLVL
interrupt to read out the SETUP packets from the FIFO whenever the core receives the SETUP packet.
15.4.4.2.2 Control Transfers
This section describes the various types of control transfers.
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15.4.4.2.2.1 Control Write Transfers (SETUP, Data OUT, Status IN)
This section describes control write transfers.
Application Programming Sequence
1. Assertion of the USB_DOEPx_INT.SETUP Packet interrupt indicates that a valid SETUP packet has been transferred to the appli-
cation. See 15.4.4.2.1 OUT Data Transfers in Slave and DMA Modes for more details. At the end of the Setup stage, the applica-
tion must reprogram the USB_DOEPx_TSIZ.SUPCNT field to 3 to receive the next SETUP packet.
2. If the last SETUP packet received before the assertion of the SETUP interrupt indicates a data OUT phase, program the core to
perform a control OUT transfer as explained in 15.4.4.2.2.8 Generic Non-Isochronous OUT Data Transfers in DMA and Slave
Modes. In DMA mode, the application must reprogram the USB_DOEPx_DMAADDR register to receive a control OUT data packet
to a different memory location.
3. In a single OUT data transfer on control endpoint 0, the application can receive up to 64 bytes. If the application is expecting more
than 64 bytes in the Data OUT stage, the application must re-enable the endpoint to receive another 64 bytes, and must continue
to do so until it has received all the data in the Data stage.
4. Assertion of the USB_DOEPx_INT.Transfer Completed interrupt on the last data OUT transfer indicates the completion of the data
OUT phase of the control transfer.
5. On completion of the data OUT phase, the application must do the following.
• To transfer a new SETUP packet in DMA mode, the application must re-enable the control OUT endpoint as explained in
15.4.4.2.1 OUT Data Transfers in Slave and DMA Modes.
• USB_DOEPx_CTL.EPENA = 1
• To execute the received Setup command, the application must program the required registers in the core. This step is optional,
based on the type of Setup command received.
6. For the status IN phase, the application must program the core as described in 15.4.4.2.3.11 Generic Non-Periodic (Bulk and Con-
trol) IN Data Transfers in DMA and Slave Mode to perform a data IN transfer.
7. Assertion of the USB_DIEPx_INT.XFERCOMPL interrupt indicates completion of the status IN phase of the control transfer.
8. The previous step must be repeated until the USB_DIEPx_INT.XFERCOMPL interrupt is detected on the endpoint, marking the
completion of the control write transfer.
15.4.4.2.2.2 Control Read Transfers (SETUP, Data IN, Status OUT)
This section describes control read transfers.
Application Programming Sequence
1. Assertion of the USB_DOEPx_INT.SETUP Packet interrupt indicates that a valid SETUP packet has been transferred to the appli-
cation. See 15.4.4.2.1 OUT Data Transfers in Slave and DMA Modes for more details. At the end of the Setup stage, the applica-
tion must reprogram the USB_DOEPx_TSIZ.SUPCNT field to 3 to receive the next SETUP packet.
2. If the last SETUP packet received before the assertion of the SETUP interrupt indicates a data IN phase, program the core to per-
form a control IN transfer as explained in 15.4.4.2.3.11 Generic Non-Periodic (Bulk and Control) IN Data Transfers in DMA and
Slave Mode.
3. On a single IN data transfer on control endpoint 0, the application can transmit up to 64 bytes. To transmit more than 64 bytes in
the Data IN stage, the application must re-enable the endpoint to transmit another 64 bytes, and must continue to do so, until it has
transmitted all the data in the Data stage.
4. The previous step must be repeated until the USB_DIEPx_INT.XFERCOMPL interrupt is detected for every IN transfer on the end-
point.
5. The USB_DIEPx_INT.XFERCOMPL interrupt on the last IN data transfer marks the completion of the control transfer’s Data stage.
6. To perform a data OUT transfer in the status OUT phase, the application must program the core as described in 15.4.4.2.1 OUT
Data Transfers in Slave and DMA Modes.
• The application must program the USB_DCFG.NZSTSOUTHSHK handshake field to a proper setting before transmitting an da-
ta OUT transfer for the Status stage.
• In DMA mode, the application must reprogram the USB_DOEPx_DMAADDR register to receive the control OUT data packet to
a different memory location.
7. Assertion of the USB_DOEPx_INT.XFERCOMPL interrupt indicates completion of the status OUT phase of the control transfer.
This marks the successful completion of the control read transfer.
• To transfer a new SETUP packet in DMA mode, the application must re-enable the control OUT endpoint as explained in
15.4.4.2.1 OUT Data Transfers in Slave and DMA Modes.
• USB_DOEPx_CTL.EPENA = 1
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15.4.4.2.2.3 Two-Stage Control Transfers (SETUP/Status IN)
This section describes two-stage control transfers.
Application Programming Sequence
1. Assertion of the USB_DOEPx_INT.SETUP interrupt indicates that a valid SETUP packet has been transferred to the application.
See 15.4.4.2.1 OUT Data Transfers in Slave and DMA Modes for more detail. To receive the next SETUP packet, the application
must reprogram the USB_DOEPx_TSIZ.SUPCNT field to 3 at the end of the Setup stage.
2. Decode the last SETUP packet received before the assertion of the SETUP interrupt. If the packet indicates a two-stage control
command, the application must do the following.
• To transfer a new SETUP packet in DMA mode, the application must re-enable the control OUT endpoint. See 15.4.4.2.1 OUT
Data Transfers in Slave and DMA Modes for details.
• USB_DOEPx_CTL.EPENA = 1
• Depending on the type of Setup command received, the application can be required to program registers in the core to execute
the received Setup command.
3. For the status IN phase, the application must program the core described in 15.4.4.2.3.11 Generic Non-Periodic (Bulk and Control)
IN Data Transfers in DMA and Slave Mode to perform a data IN transfer.
4. Assertion of the USB_DIEPx_INT.XFERCOMPL interrupt indicates the completion of the status IN phase of the control transfer.
5. The previous step must be repeated until the USB_DIEPx_INT.XFERCOMPL interrupt is detected on the endpoint, marking the
completion of the two-stage control transfer.
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Example: Two-Stage Control Transfer
These notes refer to the following figure.
1. SETUP packet #1 is received on the USB and is written to the receive FIFO, and the core responds with an ACK handshake. This
handshake is lost and the host detects a timeout.
2. The SETUP packet in the receive FIFO results in a USB_GINTSTS.RXFLVL interrupt to the application, causing the application to
empty the receive FIFO.
3. SETUP packet #2 on the USB is written to the receive FIFO, and the core responds with an ACK handshake.
4. The SETUP packet in the receive FIFO sends the application the USB_GINTSTS.RXFLVL interrupt and the application empties
the receive FIFO.
5. After the second SETUP packet, the host sends a control IN token for the status phase. The core issues a NAK response to this
token, and writes a Setup Stage Done entry to the receive FIFO. This entry results in a USB_GINTSTS.RXFLVL interrupt to the
application, which empties the receive FIFO. After reading out the Setup Stage Done DWORD, the core asserts the
USB_DOEPx_INT.SETUP packet interrupt to the application.
6. On this interrupt, the application processes SETUP Packet #2, decodes it to be a two-stage control command, and clears the con-
trol IN NAK bit.
• USB_DIEPx_CTL.CNAK = 1
7. When the application clears the IN NAK bit, the core interrupts the application with a USB_DIEPx_INT.INTKNTXFEMP interrupt.
On this interrupt, the application enables the control IN endpoint with a USB_DIEPx_TSIZ.XFERSIZE of 0 and a
USB_DIEPx_TSIZ.PKTCNT of 1. This results in a zero-length data packet for the status IN token on the USB.
8. At the end of the status IN phase, the core interrupts the application with a USB_DIEPx_INT.XFERCOMPL interrupt.
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Host USB Device Application
ACK Lost
proc_setup_pkt #2
setup data1
setup data2
setup data1
7
8
XFERSIZE = 0 bytes
PKTCNT = 1
EPENA = 1
idle until intr
rcv_out_data
SETUP
8 bytes
ACK
SETUP
8 bytes
IN
NAK
IN(STATUS)
8 bytes
ACK
NAK
IN
setup_xact_1
setup_xact_2
status_xact_2
status_xact_2
setup data2
setup done
setup data1
Control IN NAK = 1
Control OUT NAK = 1
idle until intr
rcv_out_data
idle until intr
rcv_out_data
idle until intr
setup_np_in_pkt
idle until intr
Control IN NAK = 1
Control OUT NAK = 1
RXFLVL interrupt
RXFLVL interrupt
RXFLVL interrupt
SETUP interrupt
Clear IN NAK
sts data rdy
INTKNTXFEMP interrupt
XFERCOMPL interrupt
6
5
3
4
1
Figure 15.20. Two-Stage Control Transfer
15.4.4.2.2.4 Packet Read from FIFO in Slave Mode
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This section describes how to read packets (OUT data and SETUP packets) from the receive FIFO in Slave mode.
1. On catching a USB_GINTSTS.RXFLVL interrupt, the application must read the Receive Status Pop register (USB_GRXSTSP).
2. The application can mask the USB_GINTSTS.RXFLVL interrupt by writing to USB_GINTMSK.RXFLVL = 0, until it has read the
packet from the receive FIFO.
3. If the received packet’s byte count is not 0, the byte count amount of data is popped from the receive Data FIFO and stored in
memory. If the received packet byte count is 0, no data is popped from the Receive Data FIFO.
4. The receive FIFO’s packet status readout indicates one of the following.
5. Global OUT NAK Pattern: PKTSTS = Global OUT NAK, BCNT = 0x000, EPNUM = Dont Care (0x0), DPID = Dont Care (0b00).
This data indicates that the global OUT NAK bit has taken effect.
a. SETUP Packet Pattern: PKTSTS = SETUP, BCNT = 0x008, EPNUM = Control EP Num, DPID = D0. This data indicates that a
SETUP packet for the specified endpoint is now available for reading from the receive FIFO.
b. Setup Stage Done Pattern: PKTSTS = Setup Stage Done, BCNT = 0x0, EPNUM = Control EPNum, DPID = Don’t Care
(0b00). This data indicates that the Setup stage for the specified endpoint has completed and the Data stage has started. After
this entry is popped from the receive FIFO, the core asserts a Setup interrupt on the specified control OUT endpoint.
c. Data OUT Packet Pattern: PKTSTS = DataOUT, BCNT = size of the Received data OUT packet, EPNUM = EPNum on which
the packet was received, DPID = Actual Data PID.
d. Data Transfer Completed Pattern: PKTSTS = Data OUT Transfer Done, BCNT = 0x0, EPNUM = OUT EP Num on which the
data transfer is complete, DPID = Dont Care (0b00). This data indicates that a OUT data transfer for the specified OUT end-
point has completed. After this entry is popped from the receive FIFO, the core asserts a Transfer Completed interrupt on the
specified OUT endpoint.
The encoding for the PKTSTS is listed in the USB register descriptions.
6. After the data payload is popped from the receive FIFO, the USB_GINTSTS.RXFLVL interrupt must be unmasked.
7. Steps 1–5 are repeated every time the application detects assertion of the interrupt line due to USB_GINTSTS.RXFLVL. Reading
an empty receive FIFO can result in undefined core behavior.
wait until
USB_GINTSTS.RXFLVL
rd_data = rd_reg(USB_RXSTSP)
rd_data.BCNT = 0
mem[0:dword_cnt-1] =
rd_rxfifo(rd_data.EPNUM,
dword_cnt)
NO
YES
dword_cnt =
BCNT[11:2] +
(BCNT[1] | BCNT[0])
rcv_out_pkt()
packet store
in memory
Figure 15.21. Receive FIFO Packet Read in Slave Mode
15.4.4.2.2.5 Setting the Global OUT NAK
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Internal Data Flow
1. When the application sets the Global OUT NAK (USB_DCTL.SGOUTNAK), the core stops writing data, except SETUP packets, to
the receive FIFO. Irrespective of the space availability in the receive FIFO, non-isochronous OUT tokens receive a NAK handshake
response, and the core ignores isochronous OUT data packets
2. The core writes the Global OUT NAK pattern to the receive FIFO. The application must reserve enough receive FIFO space to
write this data pattern. See 15.4.7.1 Data FIFO RAM Allocation.
3. When either the core (in DMA mode) or the application (in Slave mode) pops the Global OUT NAK pattern DWORD from the re-
ceive FIFO, the core sets the USB_GINTSTS.GOUTNAKEFF interrupt.
4. Once the application detects this interrupt, it can assume that the core is in Global OUT NAK mode. The application can clear this
interrupt by clearing the USB_DCTL.SGOUTNAK bit.
Application Programming Sequence
1. To stop receiving any kind of data in the receive FIFO, the application must set the Global OUT NAK bit by programming the fol-
lowing field.
• USB_DCTL.SGOUTNAK = 1
2. Wait for the assertion of the interrupt USB_GINTSTS.GOUTNAKEFF. When asserted, this interrupt indicates that the core has
stopped receiving any type of data except SETUP packets.
3. The application can receive valid OUT packets after it has set USB_DCTL.SGOUTNAK and before the core asserts the
USB_GINTSTS.GOUTNAKEFF interrupt.
4. The application can temporarily mask this interrupt by writing to the USB_GINTMSK.GOUTNAKEFFMSK bit.
• USB_GINTMSK.GINNAKEFFMSK = 0
5. Whenever the application is ready to exit the Global OUT NAK mode, it must clear the USB_DCTL.SGOUTNAK bit. This also
clears the USB_GINTSTS.GOUTNAKEFF interrupt.
• USB_DCTL.CGOUTNAK = 1
6. If the application has masked this interrupt earlier, it must be unmasked as follows:
• USB_GINTMSK.GOUTNAKEFFMSK = 1
15.4.4.2.2.6 Disabling an OUT Endpoint
The application must use this sequence to disable an OUT endpoint that it has enabled.
Application Programming Sequence
1. Before disabling any OUT endpoint, the application must enable Global OUT NAK mode in the core, as described in
15.4.4.2.2.5 Setting the Global OUT NAK.
• USB_DCTL.SGOUTNAK = 1
• Wait for the USB_GINTSTS.GOUTNAKEFF interrupt
2. Disable the required OUT endpoint by programming the following fields:
• USB_DOEPx_CTL.EPDIS = 1
• USB_DOEPx_CTL.SNAK = 1
3. Wait for the USB_DOEPx_INT.EPDISBLD interrupt, which indicates that the OUT endpoint is completely disabled. When the EP-
DISBLD interrupt is asserted, the core also clears the following bits.
• USB_DOEPx_CTL.EPDIS = 0
• USB_DOEPx_CTL.EPENA = 0
4. The application must clear the Global OUT NAK bit to start receiving data from other non-disabled OUT endpoints.
• USB_DCTL.SGOUTNAK = 0
15.4.4.2.2.7 Stalling a Non-Isochronous OUT Endpoint
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This section describes how the application can stall a non-isochronous endpoint.
1. Put the core in the Global OUT NAK mode, as described in 15.4.4.2.2.5 Setting the Global OUT NAK.
2. Disable the required endpoint, as described in Section 15.4.4.2.2.6 Disabling an OUT Endpoint.
• When disabling the endpoint, instead of setting the USB_DOEPx_CTL.SNAK bit, set USB_DOEPx_CTL.STALL = 1.
• The Stall bit always takes precedence over the NAK bit.
3. When the application is ready to end the STALL handshake for the endpoint, the USB_DOEPx_CTL.STALL bit must be cleared.
4. If the application is setting or clearing a STALL for an endpoint due to a SetFeature.Endpoint Halt or ClearFeature.Endpoint Halt
command, the Stall bit must be set or cleared before the application sets up the Status stage transfer on the control endpoint.
15.4.4.2.2.8 Generic Non-Isochronous OUT Data Transfers in DMA and Slave Modes
To initialize the core after power-on reset, the application must follow the sequence in 15.4.1 Overview: Programming the Core. Before
it can communicate with the host, it must initialize an endpoint as described in 15.4.4.1 Endpoint Initialization. See 15.4.4.2.2.4 Packet
Read from FIFO in Slave Mode.
This section describes a regular non-isochronous OUT data transfer (control, bulk, or interrupt).
Application Requirements
1. Before setting up an OUT transfer, the application must allocate a buffer in the memory to accommodate all data to be received as
part of the OUT transfer, then program that buffer’s size and start address (in DMA mode) in the endpoint-specific registers.
2. For OUT transfers, the Transfer Size field in the endpoint’s Transfer Size register must be a multiple of the maximum packet size of
the endpoint, adjusted to the DWORD boundary.
if (mps[epnum] mod 4) == 0
transfer size[epnum] = n * (mps[epnum]) //Dword Aligned
else
transfer size[epnum] = n * (mps[epnum] + 4 - (mps[epnum] mod 4)) //Non Dword Aligned
packet count[epnum] = n
n > 0
3. In DMA mode, the core stores a received data packet in the memory, always starting on a DWORD boundary. If the maximum
packet size of the endpoint is not a multiple of 4, the core inserts byte pads at end of a maximum-packet-size packet up to the end
of the DWORD.
4. On any OUT endpoint interrupt, the application must read the endpoint’s Transfer Size register to calculate the size of the payload
in the memory. The received payload size can be less than the programmed transfer size.
• Payload size in memory = application-programmed initial transfer size – core updated final transfer size
• Number of USB packets in which this payload was received = application-programmed initial packet count – core updated final
packet count
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Internal Data Flow
1. The application must set the Transfer Size and Packet Count fields in the endpoint-specific registers, clear the NAK bit, and enable
the endpoint to receive the data.
2. Once the NAK bit is cleared, the core starts receiving data and writes it to the receive FIFO, as long as there is space in the receive
FIFO. For every data packet received on the USB, the data packet and its status are written to the receive FIFO. Every packet
(maximum packet size or short packet) written to the receive FIFO decrements the Packet Count field for that endpoint by 1.
• OUT data packets received with Bad Data CRC are flushed from the receive FIFO automatically.
• After sending an ACK for the packet on the USB, the core discards non-isochronous OUT data packets that the host, which
cannot detect the ACK, re-sends. The application does not detect multiple back-to-back data OUT packets on the same end-
point with the same data PID. In this case the packet count is not decremented.
• If there is no space in the receive FIFO, isochronous or non-isochronous data packets are ignored and not written to the receive
FIFO. Additionally, non-isochronous OUT tokens receive a NAK handshake reply.
• In all the above three cases, the packet count is not decremented because no data is written to the receive FIFO.
3. When the packet count becomes 0 or when a short packet is received on the endpoint, the NAK bit for that endpoint is set. Once
the NAK bit is set, the isochronous or non-isochronous data packets are ignored and not written to the receive FIFO, and non-
isochronous OUT tokens receive a NAK handshake reply.
4. After the data is written to the receive FIFO, either the application (in Slave mode) or the core’s DMA engine (in DMA mode), reads
the data from the receive FIFO and writes it to external memory, one packet at a time per endpoint.
5. At the end of every packet write on the AHB to external memory, the transfer size for the endpoint is decremented by the size of
the written packet.
6. The OUT Data Transfer Completed pattern for an OUT endpoint is written to the receive FIFO on one of the following conditions.
• The transfer size is 0 and the packet count is 0
• The last OUT data packet written to the receive FIFO is a short packet (0 <= packet size < maximum packet size)
7. When either the application or the DMA pops this entry (OUT Data Transfer Completed), a Transfer Completed interrupt is gener-
ated for the endpoint and the endpoint enable is cleared.
Application Programming Sequence
1. Program the USB_DOEPx_TSIZ register for the transfer size and the corresponding packet count. Additionally, in DMA mode, pro-
gram the USB_DOEPx_DMAADDR register.
2. Program the USB_DOEPx_CTL register with the endpoint characteristics, and set the Endpoint Enable and ClearNAK bits.
• USB_DOEPx_CTL.EPENA = 1
• USB_DOEPx_CTL.CNAK = 1
3. In Slave mode, wait for the USB_GINTSTS.RXFLVL level interrupt and empty the data packets from the receive FIFO as explained
in 15.4.4.2.2.4 Packet Read from FIFO in Slave Mode.
• This step can be repeated many times, depending on the transfer size.
4. Asserting the USB_DOEPx_INT.XFERCOMPL interrupt marks a successful completion of the non-isochronous OUT data transfer.
5. Read the USB_DOEPx_TSIZ register to determine the size of the received data payload.
Note: The XFERSIZE is not decremented for the last packet. This is as per design behavior.
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Slave Mode Bulk OUT Transaction
The following figure depicts the reception of a single bulk OUT data packet from the USB to the AHB and describes the events involved
in the process.
init_out_ep
Host USB Device Application
xact_1
XFERSIZE = 512 bytes
PKTCNT = 1
idle until intr
rcv_out_pkt()
OUT
512 bytes
ACK
NAK
OUT
idle until intr
RXFLVL interrupt
USB_DOEPx_CTLNAK = 1
PKTCNT = 0
XFERSIZE = 0
XFERCOMPL interrupt
8
1wr_reg(USB_DOEPx_TSIZ)
wr_reg(USB_DOEPx_CTL)
EPENA = 1
CNAK = 1
on new transfer
or RxFIFO not
empty
2
3
4
5
6
7
Figure 15.22. Slave Mode Bulk OUT Transaction
After a SetConfiguration/SetInterface command, the application initializes all OUT endpoints by setting USB_DOEPx_CTL.CNAK = 1
and USB_DOEPx_CTL.EPENA = 1, and setting a suitable XFERSIZE and PKTCNT in the USB_DOEPx_TSIZ register.
1. Host attempts to send data (OUT token) to an endpoint.
2. When the core receives the OUT token on the USB, it stores the packet in the RxFIFO because space is available there.
3. After writing the complete packet in the RxFIFO, the core then asserts the USB_GINTSTS.RXFLVL interrupt.
4. On receiving the PKTCNT number of USB packets, the core sets the NAK bit for this endpoint internally to prevent it from receiving
any more packets.
5. The application processes the interrupt and reads the data from the RxFIFO.
6. When the application has read all the data (equivalent to XFERSIZE), the core generates a USB_DOEPx_INT.XFERCOMPL inter-
rupt.
7. The application processes the interrupt and uses the setting of the USB_DOEPx_INT.XFERCOMPL interrupt bit to determine that
the intended transfer is complete.
15.4.4.2.2.9 Generic Isochronous OUT Data Transfer in DMA and Slave Modes
To initialize the core after power-on reset, the application must follow the sequence in 15.4.1 Overview: Programming the Core. Before
it can communicate with the host, it must initialize an endpoint as described in 15.4.4.1 Endpoint Initialization. See 15.4.4.2.2.4 Packet
Read from FIFO in Slave Mode.
This section describes a regular isochronous OUT data transfer.
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Application Requirements
1. All the application requirements for non-isochronous OUT data transfers also apply to isochronous OUT data transfers
2. For isochronous OUT data transfers, the Transfer Size and Packet Count fields must always be set to the number of maximum-
packet-size packets that can be received in a single frame and no more. Isochronous OUT data transfers cannot span more than 1
frame.
• 1 <= packet count[epnum] <= 3
3. In Slave mode, when isochronous OUT endpoints are supported in the device, the application must read all isochronous OUT data
packets from the receive FIFO (data and status) before the end of the periodic frame (USB_GINTSTS.EOPF interrupt). In DMA
mode, the application must guarantee enough bandwidth to allow emptying the isochronous OUT data packet from the receive
FIFO before the end of each periodic frame.
4. To receive data in the following frame, an isochronous OUT endpoint must be enabled after the USB_GINTSTS.EOPF and before
the USB_GINTSTS.SOF.
Internal Data Flow
1. The internal data flow for isochronous OUT endpoints is the same as that for non-isochronous OUT endpoints, but for a few differ-
ences.
2. When an isochronous OUT endpoint is enabled by setting the Endpoint Enable and clearing the NAK bits, the Even/Odd frame bit
must also be set appropriately. The core receives data on a isochronous OUT endpoint in a particular frame only if the following
condition is met.
• USB_DOEPx_CTL.DPIDEOF (Even/Odd frame) = USB_DSTS.SOFFN[0]
3. When either the application or the internal DMA completely reads an isochronous OUT data packet (data and status) from the re-
ceive FIFO, the core updates the USB_DOEPx_TSIZ.RXDPIDSUPCNT (Received DPID) field with the data PID of the last isochro-
nous OUT data packet read from the receive FIFO.
Application Programming Sequence
1. Program the USB_DOEPx_TSIZ register for the transfer size and the corresponding packet count. When in DMA mode, also pro-
gram the USB_DOEPx_DMAADDR register.
2. Program the USB_DOEPx_CTL register with the endpoint characteristics and set the Endpoint Enable, ClearNAK, and Even/Odd
frame bits.
• Endpoint Enable = 1
• CNAK = 1
• Even/Odd frame = (0: Even/1: Odd)
3. In Slave mode, wait for the USB_GINTSTS.Rx StsQ level interrupt and empty the data packets from the receive FIFO as explained
in 15.4.4.2.2.4 Packet Read from FIFO in Slave Mode.
• This step can be repeated many times, depending on the transfer size.
4. The assertion of the USB_DOEPx_INT.XFERCOMPL interrupt marks the completion of the isochronous OUT data transfer. This
interrupt does not necessarily mean that the data in memory is good.
5. This interrupt can not always be detected for isochronous OUT transfers. Instead, the application can detect the
USB_GINTSTS.INCOMPLP (Incomplete Isochronous OUT data) interrupt. See 15.4.4.2.2.12 Incomplete Isochronous OUT Data
Transfers in DMA and Slave Modes, for more details
6. Read the USB_DOEPx_TSIZ register to determine the size of the received transfer and to determine the validity of the data re-
ceived in the frame. The application must treat the data received in memory as valid only if one of the following conditions is met.
• USB_DOEPx_TSIZ.RXDPID = D0 and the number of USB packets in which this payload was received = 1
• USB_DOEPx_TSIZ.RXDPID = D1 and the number of USB packets in which this payload was received = 2
• USB_DOEPx_TSIZ.RXDPID = D2 and the number of USB packets in which this payload was received = 3
• The number of USB packets in which this payload was received = App Programmed Initial Packet Count – Core Updated
Final Packet Count
The application can discard invalid data packets.
15.4.4.2.2.10 Generic Interrupt OUT Data Transfers Using Periodic Transfer Interrupt Feature
This section describes a regular INTR OUT data transfer with the Periodic Transfer Interrupt feature.
To initialize the core after power-on reset, the application must follow the sequence in 15.4.1 Overview: Programming the Core. Before
it can communicate with the host, it must initialize an endpoint as described in 15.4.4.1 Endpoint Initialization. See 15.4.4.2.2.4 Packet
Read from FIFO in Slave Mode.
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Application Requirements
1. Before setting up a periodic OUT transfer, the application must allocate a buffer in the memory to accommodate all data to be re-
ceived as part of the OUT transfer, then program that buffer’s size and start address in the endpoint-specific registers.
2. For Interrupt OUT transfers, the Transfer Size field in the endpoint’s Transfer Size register must be a multiple of the maximum
packet size of the endpoint, adjusted to the DWORD boundary. The Transfer Size programmed can span across multiple frames
based on the periodicity after which the application want to receive the USB_DOEPx_INT.XFERCOMPL interrupt
• transfer size[epnum] = n * (mps[epnum] + 4 - (mps[epnum] mod 4))
• packet count[epnum] = n
• n > 0 (Higher value of n reduces the periodicity of the USB_DOEPx_INT.XFERCOMPL interrupt)
• 1 < packet count[epnum] < n (Higher value of n reduces the periodicity of the USB_DOEPx_INT.XFERCOMPL interrupt)
3. In DMA mode, the core stores a received data packet in the memory, always starting on a DWORD boundary. If the maximum
packet size of the endpoint is not a multiple of 4, the core inserts byte pads at end of a maximum-packet-size packet up to the end
of the DWORD. The application will not be informed about the frame number on which a specific packet has been received.
4. On USB_DOEPx_INT.XFERCOMPL interrupt, the application must read the endpoint’s Transfer Size register to calculate the size
of the payload in the memory. The received payload size can be less than the programmed transfer size.
• Payload size in memory = application-programmed initial transfer size – core updated final transfer size.
• Number of USB packets in which this payload was received = application-programmed initial packet count – core updated final
packet count.
• If for some reason, the host stops sending tokens, there are no interrupts to the application, and the application must timeout on
its own.
5. The assertion of the USB_DOEPx_INT.XFERCOMPL interrupt marks the completion of the interrupt OUT data transfer. This inter-
rupt does not necessarily mean that the data in memory is good.
6. Read the USB_DOEPx_TSIZ register to determine the size of the received transfer and to determine the validity of the data re-
ceived in the frame.
Internal Data Flow
1. The application must set the Transfer Size and Packet Count fields in the endpoint-specific registers, clear the NAK bit, and enable
the endpoint to receive the data.
• The application must enable the USB_DCTL.IGNRFRMNUM
2. When an interrupt OUT endpoint is enabled by setting the Endpoint Enable and clearing the NAK bits, the Even/Odd frame will be
ignored by the core.
3. Once the NAK bit is cleared, the core starts receiving data and writes it to the receive FIFO, as long as there is space in the receive
FIFO. For every data packet received on the USB, the data packet and its status are written to the receive FIFO. Every packet
(maximum packet size or short packet) written to the receive FIFO decrements the Packet Count field for that endpoint by 1.
• OUT data packets received with Bad Data CRC or any packet error are flushed from the receive FIFO automatically.
• Interrupt packets with PID errors are not passed to application. Core discards the packet, sends ACK and does not decrement
packet count.
• If there is no space in the receive FIFO, interrupt data packets are ignored and not written to the receive FIFO. Additionally,
interrupt OUT tokens receive a NAK handshake reply.
4. When the packet count becomes 0 or when a short packet is received on the endpoint, the NAK bit for that endpoint is set. Once
the NAK bit is set, the isochronous or interrupt data packets are ignored and not written to the receive FIFO, and interrupt OUT
tokens receive a NAK handshake reply.
5. After the data is written to the receive FIFO, the core’s DMA engine reads the data from the receive FIFO and writes it to external
memory, one packet at a time per endpoint.
6. At the end of every packet write on the AHB to external memory, the transfer size for the endpoint is decremented by the size of
the written packet.
7. The OUT Data Transfer Completed pattern for an OUT endpoint is written to the receive FIFO on one of the following conditions.
• The transfer size is 0 and the packet count is 0.
• The last OUT data packet written to the receive FIFO is a short packet (0 < packet size < maximum packet size)
8. When either the application or the DMA pops this entry (OUT Data Transfer Completed), a Transfer Completed interrupt is gener-
ated for the endpoint and the endpoint enable is cleared.
15.4.4.2.2.11 Generic Isochronous OUT Data Transfers Using Periodic Transfer Interrupt Feature
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This section describes a regular isochronous OUT data transfer with the Periodic Transfer Interrupt feature.
To initialize the core after power-on reset, the application must follow the sequence in 15.4.1 Overview: Programming the Core. Before
it can communicate with the host, it must initialize an endpoint as described in 15.4.4.1 Endpoint Initialization. For packet writes in Slave
mode, see 15.4.4.2.2.4 Packet Read from FIFO in Slave Mode.
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Application Requirements
1. Before setting up ISOC OUT transfers spanned across multiple frames, the application must allocate buffer in the memory to ac-
commodate all data to be received as part of the OUT transfers, then program that buffer’s size and start address in the endpoint-
specific registers.
• The application must mask the USB_GINTSTS.INCOMPLP (Incomplete ISO OUT).
• The application must enable the USB_DCTL.IGNRFRMNUM
2. For ISOC transfers, the Transfer Size field in the USB_DOEPx_TSIZ.XFERSIZE register must be a multiple of the maximum pack-
et size of the endpoint, adjusted to the DWORD boundary. The Transfer Size programmed can span across multiple frames based
on the periodicity after which the application wants to receive the USB_DOEPx_INT.XFERCOMPL interrupt
• transfer size[epnum] = n * (mps[epnum] + 4 - (mps[epnum] mod 4))
• packet count[epnum] = n
• n > 0 (Higher value of n reduces the periodicity of the USB_DOEPx_INT.XFERCOMPL interrupt)
• 1 =< packet count[epnum] =< n (Higher value of n reduces the periodicity of the USB_DOEPx_INT.XFERCOMPL interrupt).
3. In DMA mode, the core stores a received data packet in the memory, always starting on a DWORD boundary. If the maximum
packet size of the endpoint is not a multiple of 4, the core inserts byte pads at end of a maximum-packet-size packet up to the end
of the DWORD. The application will not be informed about the frame number and the PID value on which a specific OUT packet
has been received.
4. The assertion of the USB_DOEPx_INT.XFERCOMPL interrupt marks the completion of the isochronous OUT data transfer. This
interrupt does not necessarily mean that the data in memory is good.
• On USB_DOEPx_INT.XFERCOMPL, the application must read the endpoint’s Transfer Size register to calculate the size of the
payload in the memory.
• Payload size in memory = application-programmed initial transfer size - core updated final transfer size
• Number of USB packets in which this payload was received = application-programmed initial packet count – core updated final
packet count.
• If for some reason, the host stop sending tokens, there will be no interrupt to the application, and the application must timeout
on its own.
5. The assertion of the USB_DOEPx_INT.XFERCOMPL can also mark a packet drop on USB due to unavailability of space in the
RxFifo or due to any packet errors.
• The application must read the USB_DOEPx_INT.PKTDRPSTS (USB_DOEPx_INT.Bit[11] is now used as the
USB_DOEPx_INT.PKTDRPSTS) register to differentiate whether the USB_DOEPx_INT.XFERCOMPL was generated due to
the normal end of transfer or due to dropped packets. In case of packets being dropped on the USB due to unavailability of
space in the RxFifo or due to any packet errors the endpoint enable bit is cleared.
• In case of packet drop on the USB application must re-enable the endpoint after recalculating the values
USB_DOEPx_TSIZ.XFERSIZE and USB_DOEPx_TSIZ.PKTCNT.
• Payload size in memory = application-programmed initial transfer size - core updated final transfer size
• Number of USB packets in which this payload was received = application-programmed initial packet count - core updated final
packet count.
Note: Due to application latencies it is possible that DOEPINT.XFERCOMPL interrupt is generated without DOEPINT.PKTDRPSTS be-
ing set, This scenario is possible only if back-to-back packets are dropped for consecutive frames and the PKTDRPSTS is merged, but
the XFERSIZE and PktCnt values for the endpoint are nonzero. In this case, the application must proceed further by programming the
PKTCNT and XFERSIZE register for the next frame, as it would if PKTDRPSTS were being set.
The following figure gives the application flow for Isochronous OUT Periodic Transfer Interrupt feature.
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If
USB_DOEPx_TSIZ.PKTCNT
==0
Start
Initialize variables.
Allocate a buffer in the System Memory for multiple
transfers. The buffer size must be a multiple of MaxPktSize
Program the DMA address
USB_DOEPx_DMA = START Address of the Data Memory
Program XFER_SIZE register
USB_DOEPx_TSI.ZXFERSIZE = XferSize Spanning across multiple Xfers
USB_DOEPx_TSI.Z .PKTCNT= Program PktCnt for multiple Xfers
Program the Global INT STS
GINTMSK.INCOMPLPMSK = 0 // Mask IncompISOCOUT Interrupt
Program EP Ctrl register to start the xfer
USB_DOEPx_CTL.CNAK = 1
USB_DOEPx_CTL.EPENA = 1
USB_DOEPx_CTL.SNAK = 0
USB_DOEPx_CTL.EPDIS = 0
Wait for USB_DOEPx_INT.XFERCOMPL
interrupt and report error if timeout expires
Received short packet
Return
If
USB_DOEPx_TSIZ.XFERSIZE
== 0
End of transfer
If
USB_DOEPx_INT.PKTDRPSTS
==1
ISOC OUT PktDrop
If
USB_DOEPx_TSIZ.XFERSIZE
!= 0
Received short packet
ERROR
Re-compute XFERSIZE
and PKTCNT
NO
YES NO
YES
NO YES NO
YES
Figure 15.23. ISOC OUT Application Flow for Periodic Transfer Interrupt Feature
15.4.4.2.2.12 Incomplete Isochronous OUT Data Transfers in DMA and Slave Modes
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To initialize the core after power-on reset, the application must follow the sequence in 15.4.1 Overview: Programming the Core. Before
it can communicate with the host, it must initialize an endpoint as described in 15.4.4.1 Endpoint Initialization. See 15.4.4.2.2.4 Packet
Read from FIFO in Slave Mode.
This section describes the application programming sequence when isochronous OUT data packets are dropped inside the core.
Internal Data Flow
1. For isochronous OUT endpoints, the USB_DOEPx_INT.XFERCOMPL interrupt possibly is not always asserted. If the core drops
isochronous OUT data packets, the application could fail to detect the USB_DOEPx_INT.XFERCOMPL interrupt under the follow-
ing circumstances.
• When the receive FIFO cannot accommodate the complete ISO OUT data packet, the core drops the received ISO OUT data.
• When the isochronous OUT data packet is received with CRC errors.
• When the isochronous OUT token received by the core is corrupted.
• When the application is very slow in reading the data from the receive FIFO.
2. When the core detects an end of periodic frame before transfer completion to all isochronous OUT endpoints, it asserts the
USB_GINTSTS.INCOMPLP (Incomplete Isochronous OUT data) interrupt, indicating that a USB_DOEPx_INT.XFERCOMPL inter-
rupt is not asserted on at least one of the isochronous OUT endpoints. At this point, the endpoint with the incomplete transfer re-
mains enabled, but no active transfers remains in progress on this endpoint on the USB.
3. This step is applicable only if the core is operating in slave mode. Application Programming Sequence
4. This step is applicable only if the core is operating in slave mode. Asserting the USB_GINTSTS.INCOMPLP (Incomplete Isochro-
nous OUT data) interrupt indicates that in the current frame, at least one isochronous OUT endpoint has an incomplete transfer.
5. If this occurs because isochronous OUT data is not completely emptied from the endpoint, the application must ensure that the
DMA or the application empties all isochronous OUT data (data and status) from the receive FIFO before proceeding.
• When all data is emptied from the receive FIFO, the application can detect the USB_DOEPx_INT.XFERCOMPL interrupt. In this
case, the application must re-enable the endpoint to receive isochronous OUT data in the next frame, as described in
15.4.4.2.2.2 Control Read Transfers (SETUP, Data IN, Status OUT).
6. When it receives a USB_GINTSTS.incomplete Isochronous OUT data interrupt, the application must read the control registers of
all isochronous OUT endpoints (USB_DOEPx_CTL) to determine which endpoints had an incomplete transfer in the current frame.
An endpoint transfer is incomplete if both the following conditions are met.
• USB_DOEPx_CTL.DPIDEOF (Even/Odd frame) = USB_DSTS.SOFFN[0]
• USB_DOEPx_CTL.EPENA (Endpoint Enable) = 1
7. The previous step must be performed before the USB_GINTSTS.SOF interrupt is detected, to ensure that the current frame num-
ber is not changed.
8. For isochronous OUT endpoints with incomplete transfers, the application must discard the data in the memory and disable the
endpoint by setting the USB_DOEPx_CTL.EPDIS (Endpoint Disable) bit.
9. Wait for the USB_DOEPx_INT.EPDIS (Endpoint Disabled) interrupt and enable the endpoint to receive new data in the next frame
as explained in 15.4.4.2.2.2 Control Read Transfers (SETUP, Data IN, Status OUT).
• Because the core can take some time to disable the endpoint, the application possibly is not able to receive the data in the next
frame after receiving bad isochronous data.
15.4.4.2.3 IN Data Transfers in Slave and DMA Modes
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This section describes the internal data flow and application-level operations during IN data transfers.
•15.4.4.2.3.1 Packet Write in Slave Mode
•15.4.4.2.3.2 Setting Global Non-Periodic IN Endpoint NAK
•15.4.4.2.3.3 Setting IN Endpoint NAK
•15.4.4.2.3.4 IN Endpoint Disable
•15.4.4.2.3.5 Bulk IN Stall
•15.4.4.2.2.12 Incomplete Isochronous OUT Data Transfers in DMA and Slave Modes
•15.4.4.2.2.7 Stalling a Non-Isochronous OUT Endpoint
•15.4.4.2.3.8 Worst-Case Response Time
•15.4.4.2.3.9 Choosing the Value of USB_GUSBCFG.USBTRDTIM
•15.4.4.2.3.10 Handling Babble Conditions
•15.4.4.2.3.11 Generic Non-Periodic (Bulk and Control) IN Data Transfers in DMA and Slave Mode
•15.4.4.2.3.12 Examples
•15.4.4.2.3.13 Generic Periodic IN (Interrupt and Isochronous) Data Transfers
•15.4.4.2.3.14 Generic Periodic IN Data Transfers Using the Periodic Transfer Interrupt Feature
15.4.4.2.3.1 Packet Write in Slave Mode
This section describes how the application writes data packets to the endpoint FIFO in Slave mode.
1. The application can either choose polling or interrupt mode.
• In polling mode, application monitors the status of the endpoint transmit data FIFO, by reading the USB_DIEPx_TXFSTS regis-
ter, to determine, if there is enough space in the data FIFO.
• In interrupt mode, application waits for the USB_DIEPx_INT.TXFEMP interrupt and then reads the USB_DIEPx_TXFSTS regis-
ter, to determine, if there is enough space in the data FIFO.
• To write a single non-zero length data packet, there must be space to write the entire packet is the data FIFO.
• For writing zero length packet, application must not look for FIFO space.
2. Using one of the above mentioned methods, when the application determines that there is enough space to write a transmit packet,
the application must first write into the endpoint control register, before writing the data into the data FIFO. The application, typically
must do a read modify write on the USB_DIEPx_CTL, to avoid modifying the contents of the register, except for setting the End-
point Enable bit.
The application can write multiple packets for the same endpoint, into the transmit FIFO, if space is available. For periodic IN endpoints,
application must write packets only for one frame. It can write packets for the next periodic transaction, only after getting transfer com-
plete for the previous transaction.
15.4.4.2.3.2 Setting Global Non-Periodic IN Endpoint NAK
Internal Data Flow
1. When the application sets the Global Non-periodic IN NAK bit (USB_DCTL.SGNPINNAK), the core stops transmitting data on the
non-periodic endpoint, irrespective of data availability in the Non-periodic Transmit FIFO.
2. Non-isochronous IN tokens receive a NAK handshake reply
3. The core asserts the USB_GINTSTS.GINNAKEFF interrupt in response to the USB_DCTL.SGNPINNAK bit.
4. Once the application detects this interrupt, it can assume that the core is in the Global Non-periodic IN NAK mode. The application
can clear this interrupt by clearing the USB_DCTL.SGNPINNAK bit.
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Application Programming Sequence
1. To stop transmitting any data on non-periodic IN endpoints, the application must set the USB_DCTL.SGNPINNAK bit. To set this
bit, the following field must be programmed
• USB_DCTL.SGNPINNAK = 1
2. Wait for the assertion of the USB_GINTSTS.GINNAKEFF interrupt. This interrupt indicates the core has stopped transmitting data
on the non-periodic endpoints.
3. The core can transmit valid non-periodic IN data after the application has set the USB_DCTL.SGNPINNAK bit, but before the as-
sertion of the USB_GINTSTS.GINNAKEFF interrupt.
4. The application can optionally mask this interrupt temporarily by writing to the USB_GINTMSK.GINNAKEFFMSK bit.
• USB_GINTMSK.GINNAKEFFMSK = 0
5. To exit Global Non-periodic IN NAK mode, the application must clear the USB_DCTL.SGNPINNAK. This also clears the
USB_GINTSTS.GINNAKEFF interrupt.
• USB_DCTL.SGNPINNAK = 1
6. If the application has masked this interrupt earlier, it must be unmasked as follows:
• USB_GINTMSK.GINNAKEFFMSK = 1
15.4.4.2.3.3 Setting IN Endpoint NAK
Internal Data Flow
1. When the application sets the IN NAK for a particular endpoint, the core stops transmitting data on the endpoint, irrespective of
data availability in the endpoint’s transmit FIFO.
2. Non-isochronous IN tokens receive a NAK handshake reply
• Isochronous IN tokens receive a zero-data-length packet reply
3. The core asserts the USB_DIEPx_INT.INEPNAKEFF (IN NAK Effective) interrupt in response to the USB_DIEPx_CTL.SNAK (Set
NAK) bit.
4. Once this interrupt is seen by the application, the application can assume that the endpoint is in IN NAK mode. This interrupt can
be cleared by the application by setting the USB_DIEPx_CTL. Clear NAK bit.
Application Programming Sequence
1. To stop transmitting any data on a particular IN endpoint, the application must set the IN NAK bit. To set this bit, the following field
must be programmed.
• USB_DIEPx_CTL.SNAK = 1
2. Wait for assertion of the USB_DIEPx_INT.INEPNAKEFF (NAK Effective) interrupt. This interrupt indicates the core has stopped
transmitting data on the endpoint.
3. The core can transmit valid IN data on the endpoint after the application has set the NAK bit, but before the assertion of the NAK
Effective interrupt.
4. The application can mask this interrupt temporarily by writing to the USB_DIEPMSK.INEPNAKEFFMSK (NAK Effective) bit.
• USB_DIEPMSK.INEPNAKEFFMSK (NAK Effective) = 0
5. To exit Endpoint NAK mode, the application must clear the USB_DIEPx_CTL.NAK status. This also clears the
USB_DIEPx_INT.INEPNAKEFF (NAK Effective) interrupt.
• USB_DIEPx_CTL.CNAK = 1
6. If the application masked this interrupt earlier, it must be unmasked as follows:
• USB_DIEPMSK.INEPNAKEFFMSK (NAK Effective) = 1
15.4.4.2.3.4 IN Endpoint Disable
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Use the following sequence to disable a specific IN endpoint (periodic/non-periodic) that has been previously enabled.
Application Programming Sequence:
1. In Slave mode, the application must stop writing data on the AHB, for the IN endpoint to be disabled.
2. The application must set the endpoint in NAK mode. See 15.4.4.2.3.3 Setting IN Endpoint NAK.
• USB_DIEPx_CTL.SNAK = 1
3. Wait for USB_DIEPx_INT.INEPNAKEFF (NAK Effective) interrupt.
4. Set the following bits in the USB_DIEPx_CTL register for the endpoint that must be disabled.
• USB_DIEPx_CTL.EPDIS (Endpoint Disable) = 1
• USB_DIEPx_CTL.SNAK = 1
5. Assertion of USB_DIEPx_INT.EPDISBLD (Endpoint Disabled) interrupt indicates that the core has completely disabled the speci-
fied endpoint. Along with the assertion of the interrupt, the core also clears the following bits.
• USB_DIEPx_CTL.EPENA = 0
• USB_DIEPx_CTL.EPDIS = 0
6. The application must read the USB_DIEPx_TSIZ register for the periodic IN EP, to calculate how much data on the endpoint was
transmitted on the USB.
7. The application must flush the data in the Endpoint transmit FIFO, by setting the following fields in the USB_GRSTCTL register.
• USB_GRSTCTL.TXFNUM = Endpoint Transmit FIFO Number
• USB_GRSTCTL.TXFFLSH = 1
The application must poll the USB_GRSTCTL register, until the TXFFLSH bit is cleared by the core, which indicates the end of flush
operation. To transmit new data on this endpoint, the application can re-enable the endpoint at a later point.
15.4.4.2.3.5 Bulk IN Stall
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USB
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These notes refer to the following figure.
1. The application has scheduled an IN transfer on receiving the USB_DIEPx_INT.INTKNTXFEMP (IN Token Received When TxFI-
FO Empty) interrupt.
2. When the transfer is in progress, the application must force a STALL on the endpoint. This could be because the application has
received a SetFeature.Endpoint Halt command. The application sets the Stall bit, disables the endpoint and waits for the
USB_DIEPx_INT.EPDISBLD (Endpoint Disabled) interrupt. This generates STALL handshakes for the endpoint on the USB.
3. On receiving the interrupt, the application flushes the Non-periodic Transmit FIFO and clears the USB_DCTL.SGNPINNAK (Global
IN NP NAK) bit.
4. On receiving the ClearFeature.Endpoint Halt command, the application clears the Stall bit.
5. The endpoint behaves normally and the application can re-enable the endpoint for new transfers
Host USB Device Application
XFERSIZE = 1025 bytes
PKTCNT = 3
EPENA = 1
idle until intr
IN
do_in_xfer
NAK
512 bytes
clr stall
do_in_xfer
xact_1 data rdy
INTKNTXFEMP
interrupt
3
1
IN
ACK
IN
STALL
IN
NAK
512 bytes
IN
ACK
setup_np_in_pkt
setup_np_in_pkt
xact_2 data rdy
set_stall
ep_disable;
flush_nper_tx_fifo;
Clr Global IN NP Nak
wait for host / app to
clear stall
IN
STALL
NPTXFEMP
interrupt
EPDisabled interrupt
INTKNTXFEMP
interrupt
2
4
5
xact_1 of 2
xact_2 of 2
new xact
Figure 15.24. Bulk IN Stall
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15.4.4.2.3.6 Incomplete Isochronous IN Data Transfers
This section describes what the application must do on an incomplete isochronous IN data transfer.
Internal Data Flow
1. An isochronous IN transfer is treated as incomplete in one of the following conditions.
a. The core receives a corrupted isochronous IN token on at least one isochronous IN endpoint. In this case, the application de-
tects a USB_GINTSTS.INCOMPISOIN (Incomplete Isochronous IN Transfer) interrupt.
b. The application or DMA is slow to write the complete data payload to the transmit FIFO and an IN token is received before the
complete data payload is written to the FIFO. In this case, the application detects a USB_DIEPx_INT.INTKNTXFEMP (IN To-
ken Received When TxFIFO Empty) interrupt. The application can ignore this interrupt, as it eventually results in a
USB_GINTSTS.INCOMPISOIN (Incomplete Isochronous IN Transfer) interrupt at the end of periodic frame.
i. The core transmits a zero-length data packet on the USB in response to the received IN token.
2. In either of the aforementioned cases, in Slave mode, the application must stop writing the data payload to the transmit FIFO as
soon as possible.
3. The application must set the NAK bit and the disable bit for the endpoint. In DMA mode, the core automatically stops fetching the
data payload when the endpoint disable bit is set.
4. The core disables the endpoint, clears the disable bit, and asserts the Endpoint Disable interrupt for the endpoint.
Application Programming Sequence
1. The application can ignore the USB_DIEPx_INT.INTKNTXFEMP (IN Token Received When TxFIFO empty) interrupt on any iso-
chronous IN endpoint, as it eventually results in a USB_GINTSTS.INCOMPISOIN (Incomplete Isochronous IN Transfer) interrupt.
2. Assertion of the USB_GINTSTS.INCOMPISOIN (Incomplete Isochronous IN Transfer) interrupt indicates an incomplete isochro-
nous IN transfer on at least one of the isochronous IN endpoints.
3. The application must read the Endpoint Control register for all isochronous IN endpoints to detect endpoints with incomplete IN
data transfers.
4. In Slave mode, the application must stop writing data to the Periodic Transmit FIFOs associated with these endpoints on the AHB.
5. In both modes of operation, program the following fields in the USB_DIEPx_CTL register to disable the endpoint.
• USB_DIEPx_CTL.SNAK = 1
• USB_DIEPx_CTL.EPDIS (Endpoint Disable) = 1
6. The USB_DIEPx_INT.EPDISBLD (Endpoint Disabled) interrupt’s assertion indicates that the core has disabled the endpoint.
• At this point, the application must flush the data in the associated transmit FIFO or overwrite the existing data in the FIFO by
enabling the endpoint for a new transfer in the next frame. To flush the data, the application must use the USB_GRSTCTL reg-
ister.
15.4.4.2.3.7 Stalling Non-Isochronous IN Endpoints
This section describes how the application can stall a non-isochronous endpoint.
Application Programming Sequence
1. Disable the IN endpoint to be stalled. Set the Stall bit as well.
2. USB_DIEPx_CTL.EPDIS (Endpoint Disable) = 1, when the endpoint is already enabled.
• USB_DIEPx_CTL.STALL = 1
• The Stall bit always takes precedence over the NAK bit
3. Assertion of the USB_DIEPx_INT.EPDISBLD (Endpoint Disabled) interrupt indicates to the application that the core has disabled
the specified endpoint.
4. The application must flush the Non-periodic or Periodic Transmit FIFO, depending on the endpoint type. In case of a non-periodic
endpoint, the application must re-enable the other non-periodic endpoints, which do not need to be stalled, to transmit data.
5. Whenever the application is ready to end the STALL handshake for the endpoint, the USB_DIEPx_CTL.STALL bit must be cleared.
6. If the application sets or clears a STALL for an endpoint due to a SetFeature.Endpoint Halt command or ClearFeature.Endpoint
Halt command, the Stall bit must be set or cleared before the application sets up the Status stage transfer on the control endpoint.
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Special Case: Stalling the Control IN/OUT Endpoint
The core must stall IN/OUT tokens if, during the Data stage of a control transfer, the host sends more IN/OUT tokens than are specified
in the SETUP packet. In this case, the application must to enable USB_DIEPx_INT.INTKNTXFEMP and
USB_DOEPx_INT.OUTTKNEPDIS interrupts during the Data stage of the control transfer, after the core has transferred the amount of
data specified in the SETUP packet. Then, when the application receives this interrupt, it must set the STALL bit in the corresponding
endpoint control register, and clear this interrupt.
15.4.4.2.3.8 Worst-Case Response Time
When the acts as a device, there is a worst case response time for any tokens that follow an isochronous OUT. This worst case re-
sponse time depends on the AHB clock frequency.
The core registers are in the AHB domain, and the core does not accept another token before updating these register values. The worst
case is for any token following an isochronous OUT, because for an isochronous transaction, there is no handshake and the next token
could come sooner. This worst case value is 7 PHY clocks in FS mode.
If this worst case condition occurs, the core responds to bulk/interrupt tokens with a NAK and drops isochronous and SETUP tokens.
The host interprets this as a timeout condition for SETUP and retries the SETUP packet. For isochronous transfers, the INCOMPISOIN
and INCOMPLP interrupts inform the application that isochronous IN/OUT packets were dropped.
15.4.4.2.3.9 Choosing the Value of USB_GUSBCFG.USBTRDTIM
The value in USB_GUSBCFG.USBTRDTIM is the time it takes for the MAC, in terms of PHY clocks after it has received an IN token, to
get the FIFO status, and thus the first data from PFC (Packet FIFO Controller) block. This time involves the synchronization delay be-
tween the PHY and AHB clocks. This delay is 5 clocks.
Once the MAC receives an IN token, this information (token received) is synchronized to the AHB clock by the PFC (the PFC runs on
the AHB clock). The PFC then reads the data from the SPRAM and writes it into the dual clock source buffer. The MAC then reads the
data out of the source buffer (4 deep).
If the AHB is running at a higher frequency than the PHY (in Low-speed mode), the application can use a smaller value for
USB_GUSBCFG.USBTRDTIM. The following figure explains the 5-clock delay. This diagram has the following signals:
• tkn_rcvd: Token received information from MAC to PFC
• dynced_tkn_rcvd: Doubled sync tkn_rcvd, from pclk to hclk domain
• spr_read: Read to SPRAM
• spr_addr: Address to SPRAM
• spr_rdata: Read data from SPRAM
• srcbuf_push: Push to the source buffer
• srcbuf_rdata: Read data from the source buffer. Data seen by MAC
The application can use the following formula to calculate the value of USB_GUSBCFG.USBTRDTIM:
4 × AHB Clock + 1 PHY Clock = (2 clock sync + 1 clock memory address + 1 clock memory data from sync RAM) + (1 PHY Clock (next PHY clock MAC can sample the 2-clock FIFO output))
15.4.4.2.3.10 Handling Babble Conditions
If receives a packet that is larger than the maximum packet size for that endpoint, the core stops writing data to the Rx buffer and waits
for the end of packet (EOP). When the core detects the EOP, it flushes the packet in the Rx buffer and does not send any response to
the host.
If the core continues to receive data at the EOF2 (the end of frame 2, which is very close to SOF), the core generates an early_suspend
interrupt (USB_GINTSTS.ERLYSUSP). On receiving this interrupt, the application must check the erratic_error status bit
(USB_DSTS.ERRTICERR). If this bit is set, the application must take it as a long babble and perform a soft reset.
15.4.4.2.3.11 Generic Non-Periodic (Bulk and Control) IN Data Transfers in DMA and Slave Mode
To initialize the core after power-on reset, the application must follow the sequence in 15.4.1 Overview: Programming the Core. Before
it can communicate with the host, it must initialize an endpoint as described in 15.4.4.1 Endpoint Initialization. For packet writes in Slave
mode, see 15.4.4.2.3.1 Packet Write in Slave Mode.
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Application Requirements
1. Before setting up an IN transfer, the application must ensure that all data to be transmitted as part of the IN transfer is part of a
single buffer, and must program the size of that buffer and its start address (in DMA mode) to the endpoint-specific registers.
2. For IN transfers, the Transfer Size field in the Endpoint Transfer Size register denotes a payload that constitutes multiple maxi-
mum-packet-size packets and a single short packet. This short packet is transmitted at the end of the transfer.
• To transmit a few maximum-packet-size packets and a short packet at the end of the transfer:
• Transfer size[epnum] = n * mps[epnum] + sp (where n is an integer >= 0, and 0 <= sp < mps[epnum])
• If (sp > 0), then packet count[epnum] = n + 1. Otherwise, packet count[epnum] = n
a. To transmit a single zero-length data packet:
• Transfer size[epnum] = 0
• Packet count[epnum] = 1
b. To transmit a few maximum-packet-size packets and a zero-length data packet at the end of the transfer, the application must
split the transfer in two parts. The first sends maximum-packet-size data packets and the second sends the zero-length data
packet alone.
c. First transfer: transfer size[epnum] = n * mps[epnum]; packet count = n;
d. Second transfer: transfer size[epnum] = 0; packet count = 1;
3. In DMA mode, the core fetches an IN data packet from the memory, always starting at a DWORD boundary. If the maximum pack-
et size of the IN endpoint is not a multiple of 4, the application must arrange the data in the memory with pads inserted at the end
of a maximum-packet-size packet so that a new packet always starts on a DWORD boundary.
4. Once an endpoint is enabled for data transfers, the core updates the Transfer Size register. At the end of IN transfer, which ended
with a Endpoint Disabled interrupt, the application must read the Transfer Size register to determine how much data posted in the
transmit FIFO was already sent on the USB.
5. Data fetched into transmit FIFO = Application-programmed initial transfer size – core-updated final transfer size
• Data transmitted on USB = (application-programmed initial packet count – Core updated final packet count) * mps[epnum]
• Data yet to be transmitted on USB = (Application-programmed initial transfer size – data transmitted on USB)
Internal Data Flow
1. The application must set the Transfer Size and Packet Count fields in the endpoint-specific registers and enable the endpoint to
transmit the data.
2. In Slave mode, the application must also write the required data to the transmit FIFO for the endpoint. In DMA mode, the core
fetches the data from memory according to the application setting for the endpoint.
3. Every time a packet is written into the transmit FIFO, either by the core’s internal DMA (in DMA mode) or the application (in Slave
Mode), the transfer size for that endpoint is decremented by the packet size. The data is fetched from the memory (DMA/Applica-
tion), until the transfer size for the endpoint becomes 0. After writing the data into the FIFO, the “number of packets in FIFO” count
is incremented (this is a 3-bit count, internally maintained by the core for each IN endpoint transmit FIFO. The maximum number of
packets maintained by the core at any time in an IN endpoint FIFO is eight). For zero-length packets, a separate flag is set for each
FIFO, without any data in the FIFO.
4. Once the data is written to the transmit FIFO, the core reads it out upon receiving an IN token. For every non-isochronous IN data
packet transmitted with an ACK handshake, the packet count for the endpoint is decremented by one, until the packet count is
zero. The packet count is not decremented on a TIMEOUT.
5. For zero length packets (indicated by an internal zero length flag), the core sends out a zero-length packet for the IN token and
decrements the Packet Count field.
6. If there is no data in the FIFO for a received IN token and the packet count field for that endpoint is zero, the core generates a IN
Tkn Rcvd When FIFO Empty Interrupt for the endpoint, provided the endpoint NAK bit is not set. The core responds with a NAK
handshake for non-isochronous endpoints on the USB.
7. For Control IN endpoint, if there is a TIMEOUT condition, the USB_DIEPx_INT.TIMEOUT interrupt is generated.
8. When the transfer size is 0 and the packet count is 0, the transfer complete interrupt for the endpoint is generated and the endpoint
enable is cleared.
Application Programming Sequence
1. Program the USB_DIEPx_TSIZ register with the transfer size and corresponding packet count. In DMA mode, also program the
USB_DIEPx_DMAADDR register.
2. Program the USB_DIEPx_CTL register with the endpoint characteristics and set the CNAK and Endpoint Enable bits.
3. In slave mode when transmitting non-zero length data packet, the application must poll the USB_DIEPx_TXFSTS register (where x
is the FIFO number associated with that endpoint) to determine whether there is enough space in the data FIFO. The application
can optionally use USB_DIEPx_INT.TXFEMP before writing the data.
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XFE
PKT
EPE
wr
idle until inlr
\b
15.4.4.2.3.12 Examples
Slave Mode Bulk IN Transaction
These notes refer to the following figure.
1. The host attempts to read data (IN token) from an endpoint.
2. On receiving the IN token on the USB, the core returns a NAK handshake, because no data is available in the transmit FIFO.
3. To indicate to the application that there was no data to send, the core generates a USB_DIEPx_INT.INTKNTXFEMP (IN Token
Received When TxFIFO Empty) interrupt.
4. When data is ready, the application sets up the USB_DIEPx_TSIZ register with the Transfer Size and Packet Count fields.
5. The application writes one maximum packet size or less of data to the Non-periodic TxFIFO.
6. The host reattempts the IN token.
7. Because data is now ready in the FIFO, the core now responds with the data and the host ACKs it.
8. Because the XFERSIZE is now zero, the intended transfer is complete. The device core generates a USB_DIEPx_INT.XFER-
COMPL interrupt.
9. The application processes the interrupt and uses the setting of the USB_DIEPx_INT.XFERCOMPL interrupt bit to determine that
the intended transfer is complete.
Host USB Device Application
XFERSIZE = 512 bytes
PKTCNT = 1
EPENA = 1
IN
IN
NAK
512 bytes
INTKNTXFEMP
interrupt
IN
ACK
setup_np_in_pkt
XFERCOMPL
interrupt
1
IN
NAK
xact_1
new xfer rdy?
idle until intr
wr_reg(ep.DIEPTSIZn)
Yes
wait for
xfer
idle until intr
In Tkn = 0
Timeout = 0
XferComp = 1
2
3
44
5
6
7
8
9
Figure 15.25. Slave Mode Bulk IN Transaction
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Slave Mode Bulk IN Transfer (Pipelined Transaction)
These notes refer to the following figure.
1. The host attempts to read data (IN token) from an endpoint.
2. On receiving the IN token on the USB, the core returns a NAK handshake, because no data is available in the transmit FIFO.
3. To indicate that there was no data to send, the core generates an USB_DIEPx_INT.INTKNTXFEMP (In Token Received When
TxFIFO Empty) interrupt.
4. When data is ready, the application sets up the USB_DIEPx_TSIZ register with the transfer size and packet count.
5. The application writes one maximum packet size or less of data to the Non-periodic TxFIFO.
6. The host reattempts the IN token.
7. Because data is now ready in the FIFO, the core responds with the data, and the host ACKs it.
8. When the TxFIFO level falls below the halfway mark, the core generates a USB_GINTSTS.NPTXFEMP (NonPeriodic TxFIFO
Empty) interrupt. This triggers the application to start writing additional data packets to the FIFO.
9. A data packet for the second transaction is ready in the TxFIFO.
10. A data packet for third transaction is ready in the TxFIFO while the data for the second packet is being sent on the bus.
11. The second data packet is sent to the host.
12. The last short packet is sent to the host.
13. Because the last packet is sent and XFERSIZE is now zero, the intended transfer is complete. The core generates a
USB_DIEPx_INT.XFERCOMPL interrupt.
14. The application processes the interrupt and uses the setting of the USB_DIEPx_INT.XFERCOMPL interrupt bit to determine that
the intended transfer is complete
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XFE
PKT
EPE
In Tk
Time
ACK
XlerC
nfll in
Host USB Device Application
XFERSIZE = 1025 bytes
PKTCNT = 3
EPENA = 1
IN
NAK
512 bytes
INTKNTXFEMP
interrupt
IN
ACK
XFERCOMPL
interrupt
1
xact_1
wr_reg(xfer_size_reg)
idle until intr
In Tkn = 0
Timeout = 0
ACK = 0
XferComp = 1
2
3
4
5
6
78
14
setup_np_in_pkt
512 bytes
IN
ACK
1 byte
IN
ACK
idle until intr
xact_2
xact_3
xact_2
setup_np_in_pkt
setup_np_in_pkt
NPTXFEMP
interrupt
9
10
2
11
xact_1 of 3
xact_2 of 3
xact_3 of 3 12 13
Figure 15.26. Slave Mode Bulk IN Transfer (Pipelined Transaction)
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Slave Mode Bulk IN Two-Endpoint Transfer
These notes refer to the following figure.
1. The host attempts to read data (IN token) from endpoint 1.
2. On receiving the IN token on the USB, the core returns a NAK handshake, because no data is available in the transmit FIFO for
endpoint 1, and generates a USB_DIEP1_INT.INTKNTXFEMP (In Token Received When TxFIFO Empty) interrupt.
3. The application processes the interrupt and initializes USB_DIEP1_TSIZ register with the Transfer Size and Packet Count fields.
The application starts writing the transaction data to the transmit FIFO.
4. The application writes one maximum packet size or less of data for endpoint 1 to the Non-periodic TxFIFO.
5. Meanwhile, the host attempts to read data (IN token) from endpoint 2.
6. On receiving the IN token on the USB, the core returns a NAK handshake, because no data is available in the transmit FIFO for
endpoint 2, and the core generates a USB_DIEP2_INT.INTKNTXFEMP (In Token Received When TxFIFO Empty) interrupt.
7. Because the application has completed writing the packet for endpoint 1, it initializes the USB_DIEP2_TSIZ register with the Trans-
fer Size and Packet Count fields. The application starts writing the transaction data into the transmit FIFO for endpoint 2.
8. The host repeats its attempt to read data (IN token) from endpoint 1.
9. Because data is now ready in the TxFIFO, the core returns the data, which the host ACKs.
10. Meanwhile, the application has initialized the data for the next two packets in the TxFIFO (ep2.xact1 and ep1.xact2, in order).
11. The host repeats its attempt to read data (IN token) from endpoint 2.
12. Because endpoint 2’s data is ready, the core responds with the data (ep2.xact_1), which the host ACKs.
13. Meanwhile, the application has initialized the data for the next two packets in the TxFIFO (ep2.xact2 and ep1.xact3, in order). The
application has finished initializing data for the two endpoints involved in this scenario.
14. The host repeats its attempt to read data (IN token) from endpoint 1.
15. Because data is now ready in the FIFO, the core responds with the data, which the host ACKs.
16. The host repeats its attempt to read data (IN token) from endpoint 2.
17. With data now ready in the FIFO, the core responds with the data, which the host ACKs.
18. With the last packet for endpoint 2 sent and its XFERSIZE now zero, the intended transfer is complete. The core generates a
USB_DIEP2_INT.XFERCOMPL interrupt for this endpoint.
19. The application processes the interrupt and uses the setting of the USB_DIEP2_INT.XFERCOMPL interrupt bit to determine that
the intended transfer on endpoint 2 is complete.
20. The host repeats its attempt to read data (IN token) from endpoint 1 (last transaction).
21. With data now ready in the FIFO, the core responds with the data, which the host ACKs.
22. Because the last endpoint one packet has been sent and XFERSIZE is now zero, the intended transfer is complete. The core gen-
erates a USB_DIEP1_INT.XFERCOMPL interrupt for this endpoint.
23. The application processes the interrupt and uses the setting of the USB_DIEP1_INT.XFERCOMPL interrupt bit to determine that
the intended transfer on endpoint 1 is complete.
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v A:
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12
In, ep1
NAK
ep1,InTkn
TxF Emp intr
idle until
intr
EP_NUM 1 register set
XferSize = 1025 bytes
PktCnt = 3
EPEna = 1
ep 2 drvr
idle until
intr
ep1. setup_np_in_pkt
ep1. setup_np_in_pkt
idle until
intr
wr_reg(ep2, DIEPTSIZn)
ep2. setup_np_in_pkt
ep2. setup_np_in_pkt
idle until
intr
ep1 . xact_1
3
wr_reg(ep1, DIEPTSIZn)
4
5
IN, ep2
NAK
6
IN, ep2
ep2. InTknTxFEmp intr
7
8
In, ep1
512 bytes
512 bytes
512 bytes
10 bytes
1 byte
9
ep1 . xact_1
ep1 . xact_2
ep1 . xact_2
ep2 . xact_2
ep1 . xact_2
ep1 . xact_3
ep1. setup_np_in_pkt
10
ACK
IN, ep2
11
12
13
14
ACK
IN, ep1
15
ACK
16
IN, ep2
17 18 19
EP_NUM 2 register set
XferSize = 522 bytes
PktCnt = 2
EPEna = 1
xfer_complete = 1
20
In, ep1
ACK
21
22
ep1,Xfer
Comp intr
23
xfer_complete = 1
Figure 15.27. Slave Mode Bulk IN Two-Endpoint Transfer
15.4.4.2.3.13 Generic Periodic IN (Interrupt and Isochronous) Data Transfers
To initialize the core after power-on reset, the application must follow the sequence in 15.4.1 Overview: Programming the Core. Before
it can communicate with the host, it must initialize an endpoint as described in 15.4.4.1 Endpoint Initialization. For packet writes in Slave
mode, see 15.4.4.2.3.1 Packet Write in Slave Mode.
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Application Requirements
1. Application requirements 1, 2, 3, and 4 of 15.4.4.2.3.11 Generic Non-Periodic (Bulk and Control) IN Data Transfers in DMA and
Slave Mode also apply to periodic IN data transfers, except for a slight modification of Requirement 2.
• The application can only transmit multiples of maximum-packet-size data packets or multiples of maximum-packet-size packets,
plus a short packet at the end. To transmit a few maximum-packet-size packets and a short packet at the end of the transfer,
the following conditions must be met.
• transfer size[epnum] = n * mps[epnum] + sp(where n is an integer # 0, and 0 >= sp < mps[epnum])
• If (sp > 0), packet count[epnum] = n + 1Otherwise, packet count[epnum] = n;
• mc[epnum] = packet count[epnum]
• The application cannot transmit a zero-length data packet at the end of transfer. It can transmit a single zero-length data packet
by it self. To transmit a single zero-length data packet,
• transfer size[epnum] = 0
• packet count[epnum] = 1
• mc[epnum] = packet count[epnum]
2. The application can only schedule data transfers 1 frame at a time.
• (USB_DIEPx_TSIZ.MC – 1) * USB_DIEPx_CTL.MPS =< USB_DIEPx_TSIZ.XFERSIZE =< USB_DIEPx_TSIZ.MC *
USB_DIEPx_CTL.MPS
• USB_DIEPx_TSIZ.PKTCNT = USB_DIEPx_TSIZ.MC
• If USB_DIEPx_TSIZ.XFERSIZE < USB_DIEPx_TSIZ.MC * USB_DIEPx_CTL.MPS, the last data packet of the transfer is a short
packet.
3. This step is not applicable for isochronous data transfers, only for interrupt transfers. The application can schedule data transfers
for multiple frames, only if multiples of max packet sizes (up to 3 packets), must be transmitted every frame. This is can be done,
only when the core is operating in DMA mode. This is not a recommended mode though.
• ((n*USB_DIEPx_TSIZ.MC) - 1)*USB_DIEPx_CTL.MPS <= USB_DIEPx_TSIZ.XFERSIZE <=
n*USB_DIEPx_TSIZ.MC*USB_DIEPx_CTL.MPS
• USB_DIEPx_TSIZ.PKTCNT = n*USB_DIEPx_TSIZ.MC
• n is the number of frames for which the data transfers are scheduled
Data Transmitted per frame in this case would be USB_DIEPx_TSIZ.MC*USB_DIEPx_CTL.MPS, in all the frames except the last
one. In the frame “n”, the data transmitted would be (USB_DIEPx_TSIZ.XFERSIZE -
(n-1)*USB_DIEPx_TSIZ.MC*USB_DIEPx_CTL.MPS)
4. For Periodic IN endpoints, the data must always be prefetched 1 frame ahead for transmission in the next frame. This can be done,
by enabling the Periodic IN endpoint 1 frame ahead of the frame in which the data transfer is scheduled.
5. The complete data to be transmitted in the frame must be written into the transmit FIFO (either by the application or the DMA),
before the Periodic IN token is received. Even when 1 DWORD of the data to be transmitted per frame is missing in the transmit
FIFO when the Periodic IN token is received, the core behaves as when the FIFO was empty. When the transmit FIFO is empty,
6. A zero data length packet would be transmitted on the USB for ISO IN endpoints
• A NAK handshake would be transmitted on the USB for INTR IN endpoints
7. For a High Bandwidth IN endpoint with three packets in a frame, the application can program the endpoint FIFO size to be
2*max_pkt_size and have the third packet load in after the first packet has been transmitted on the USB.
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Internal Data Flow
1. The application must set the Transfer Size and Packet Count fields in the endpoint-specific registers and enable the endpoint to
transmit the data.
2. In Slave mode, the application must also write the required data to the associated transmit FIFO for the endpoint. In DMA mode,
the core fetches the data for the endpoint from memory, according to the application setting.
3. Every time either the core’s internal DMA (in DMA mode) or the application (in Slave mode) writes a packet to the transmit FIFO,
the transfer size for that endpoint is decremented by the packet size. The data is fetched from DMA or application memory until the
transfer size for the endpoint becomes 0.
4. When an IN token is received for an periodic endpoint, the core transmits the data in the FIFO, if available. If the complete data
payload (complete packet) for the frame is not present in the FIFO, then the core generates an IN Token Received When TxFIFO
Empty Interrupt for the endpoint.
• A zero-length data packet is transmitted on the USB for isochronous IN endpoints
• A NAK handshake is transmitted on the USB for interrupt IN endpoints
5. The packet count for the endpoint is decremented by 1 under the following conditions:
• For isochronous endpoints, when a zero- or non-zero-length data packet is transmitted
• For interrupt endpoints, when an ACK handshake is transmitted
• When the transfer size and packet count are both 0, the Transfer Completed interrupt for the endpoint is generated and the
endpoint enable is cleared.
6. At the “Periodic frame Interval” (controlled by USB_DCFG.PERFRINT), when the core finds non-empty any of the isochronous IN
endpoint FIFOs scheduled for the current frame non-empty, the core generates a USB_GINTSTS.INCOMPISOIN interrupt.
Application Programming Sequence (Transfer Per Frame)
1. Program the USB_DIEPx_TSIZ register. In DMA mode, also program the USB_DIEPx_DMAADDR register.
2. Program the USB_DIEPx_CTL register with the endpoint characteristics and set the CNAK and Endpoint Enable bits.
3. In Slave mode, write the data to be transmitted in the next frame to the transmit FIFO.
4. Asserting the USB_DIEPx_INT.INTKNTXFEMP (In Token Received When TxFifo Empty) interrupt indicates that either the DMA or
application has not yet written all data to be transmitted to the transmit FIFO.
5. If the interrupt endpoint is already enabled when this interrupt is detected, ignore the interrupt. If it is not enabled, enable the end-
point so that the data can be transmitted on the next IN token attempt.
• If the isochronous endpoint is already enabled when this interrupt is detected, see 15.4.4.2.3.6 Incomplete Isochronous IN Data
Transfers for more details.
6. The core handles timeouts internally on interrupt IN endpoints programmed as periodic endpoints without application intervention.
The application, thus, never detects a USB_DIEPx_INT.TIMEOUT interrupt for periodic interrupt IN endpoints.
7. Asserting the USB_DIEPx_INT.XFERCOMPL interrupt with no USB_DIEPx_INT.INTKNTXFEMP (In Token Received When TxFifo
Empty) interrupt indicates the successful completion of an isochronous IN transfer. A read to the USB_DIEPx_TSIZ register must
indicate transfer size = 0 and packet count = 0, indicating all data is transmitted on the USB.
8. Asserting the USB_DIEPx_INT.XFERCOMPL interrupt, with or without the USB_DIEPx_INT.INTKNTXFEMP (In Token Received
When TxFifo Empty) interrupt, indicates the successful completion of an interrupt IN transfer. A read to the USB_DIEPx_TSIZ reg-
ister must indicate transfer size = 0 and packet count = 0, indicating all data is transmitted on the USB.
9. Asserting the USB_GINTSTS.INCOMPISOIN (Incomplete Isochronous IN Transfer) interrupt with none of the aforementioned inter-
rupts indicates the core did not receive at least 1 periodic IN token in the current frame.
10. For isochronous IN endpoints, see 15.4.4.2.3.6 Incomplete Isochronous IN Data Transfers, for more details.
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15.4.4.2.3.14 Generic Periodic IN Data Transfers Using the Periodic Transfer Interrupt Feature
This section describes a typical Periodic IN (ISOC / INTR) data transfer with the Periodic Transfer Interrupt feature.
1. Before setting up an IN transfer, the application must ensure that all data to be transmitted as part of the IN transfer is part of a
single buffer, and must program the size of that buffer and its start address (in DMA mode) to the endpoint-specific registers.
2. For IN transfers, the Transfer Size field in the Endpoint Transfer Size register denotes a payload that constitutes multiple maxi-
mum-packet-size packets and a single short packet. This short packet is transmitted at the end of the transfer.
a. To transmit a few maximum-packet-size packets and a short packet at the end of the transfer:
• Transfer size[epnum] = n * mps[epnum] + sp (where n is an integer > 0, and 0 < sp < mps[epnum]. A higher value of n
reduces the periodicity of the USB_DOEPx_INT.XFERCOMPL interrupt)
• If (sp > 0), then packet count[epnum] = n + 1. Otherwise, packet count[epnum] = n
b. To transmit a single zero-length data packet:
• Transfer size[epnum] = 0
• Packet count[epnum] = 1
c. To transmit a few maximum-packet-size packets and a zero-length data packet at the end of the transfer, the application must
split the transfer in two parts. The first sends maximum-packet-size data packets and the second sends the zero-length data
packet alone.
• First transfer: transfer size[epnum] = n * mps[epnum]; packet count = n;
• Second transfer: transfer size[epnum] = 0; packet count = 1;
d. The application can only transmit multiples of maximum-packet-size data packets or multiples of maximum-packet-size pack-
ets, plus a short packet at the end. To transmit a few maximum-packet-size packets and a short packet at the end of the trans-
fer, the following conditions must be met.
• transfer size[epnum] = n * mps[epnum] + sp (where n is an integer > 0, and 0 < sp < mps[epnum])
• If (sp > 0), packet count[epnum] = n + 1 Otherwise, packet count[epnum] = n;
• mc[epnum] = number of packets to be sent out in a frame.
e. The application cannot transmit a zero-length data packet at the end of transfer. It can transmit a single zero-length data pack-
et by itself. To transmit a single zero-length data packet,
• transfer size[epnum] = 0
• packet count[epnum] = 1
• mc[epnum] = packet count[epnum]
3. In DMA mode, the core fetches an IN data packet from the memory, always starting at a DWORD boundary. If the maximum pack-
et size of the IN endpoint is not a multiple of 4, the application must arrange the data in the memory with pads inserted at the end
of a maximum-packet-size packet so that a new packet always starts on a DWORD boundary.
4. Once an endpoint is enabled for data transfers, the core updates the Transfer Size register. At the end of IN transfer, which ended
with a Endpoint Disabled interrupt, the application must read the Transfer Size register to determine how much data posted in the
transmit FIFO was already sent on the USB.
• Data fetched into transmit FIFO = Application-programmed initial transfer size - core-updated final transfer size
• Data transmitted on USB = (application-programmed initial packet count - Core updated final packet count) * mps[epnum]
• Data yet to be transmitted on USB = (Application-programmed initial transfer size - data transmitted on USB)
5. The application can schedule data transfers for multiple frames, only if multiples of max packet sizes (up to 3 packets), must be
transmitted every frame. This is can be done, only when the core is operating in DMA mode.
• ((n*USB_DIEPx_TSIZ.MC) - 1)*USB_DIEPx_CTL.MPS <= USB_DIEPx_TSIZ.XFERSIZE <=
n*USB_DIEPx_TSIZ.MC*USB_DIEPx_CTL.MPS
• USB_DIEPx_TSIZ.PKTCNT = n*USB_DIEPx_TSIZ.MC
• n is the number of frames for which the data transfers are scheduled. Data Transmitted per frame in this case is
USB_DIEPx_TSIZ.MC*USB_DIEPx_CTL.MPS in all frames except the last one. In frame n, the data transmitted is
(USB_DIEPx_TSIZ.XFERSIZE – (n – 1) * USB_DIEPx_TSIZ.MC * USB_DIEPx_CTL.MPS)
6. For Periodic IN endpoints, the data must always be prefetched 1 frame ahead for transmission in the next frame. This can be done,
by enabling the Periodic IN endpoint 1 frame ahead of the frame in which the data transfer is scheduled.
7. The complete data to be transmitted in the frame must be written into the transmit FIFO, before the Periodic IN token is received.
Even when 1 DWORD of the data to be transmitted per frame is missing in the transmit FIFO when the Periodic IN token is re-
ceived, the core behaves as when the FIFO was empty. When the transmit FIFO is empty,
• A zero data length packet would be transmitted on the USB for ISOC IN endpoints
• A NAK handshake would be transmitted on the USB for INTR IN endpoints
• USB_DIEPx_TSIZ.PKTCNT is not decremented in this case.
8. For a High Bandwidth IN endpoint with three packets in a frame, the application can program the endpoint FIFO size to be 2 *
max_pkt_size and have the third packet load in after the first packet has been transmitted on the USB.
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Start Notes
Requirements For XferSize and PktCnt programming:
1. The Packet Size has to be MaxPktSize for all frames except for the
last packet, which can be a short packet
2. Short packets are not allowed in between transfers
3. The core will read packets from system memory only from DWORD-
aligned addresses.
4. If MaxPktSize is not DWORD aligned, the application must insert
pads at the end of the packet so that new packets are always
DWORD aligned.
5. Thresholding in not supported for the Periodic Transfer Interrupt
Enhancement.
Return
Intialize variables.
Allocate a buffer in the System Memory. XferBuffer size
should be multiple ot MaxPktSize.
Program the DMA address
DIEPDMA = START Address of the Data Memory
Program Xfer_Size register
USB_DIEPx_TSIZ.XFERSIZE = XferSize spanning across multiple Xfers
USB_DIEPx_TSIZ.PKTCNT = Program PktCnt for multiple Xfers
USB_DIEPx_TSIZ.MC = Max Number of Packets in a frame
Program the Global INT STS
USB_GINTMSK.INCOMPLSOCINMSK = 0b0 // Mask IncompISOCIN Interrupt
If USB_DIEPx_TSIZ
XFERSIZE != 0 or
USB_DIEPx_TSIZ
PKTCNT != 0
De-allocate Data
Ram Memory
Program EP Ctrl register to start the xfer
USB_DIEPx_CTL.CNAK = 0b1
USB_DIEPx_CTL.TXFNUM = tx_fifo_num
USB_DIEPx_CTL.EPENA = 0b1
USB_DIEPx_CTL.SNAK = 0b0
USB_DIEPx_CTL.EPDIS = 0b0
Wait for USB_DOEPX_INT XFERCOMPL interrupt and
report an error if timeout expires.
Check for error scenario.
If no error scenario, set report error.
YES
NO
Figure 15.28. Periodic IN Application Flow for Periodic Transfer Interrupt Feature
15.4.5 OTG Revision 1.3 Programming Model
This section describes the OTG programming model when the core is configured to support OTG Revision 1.3 of the specification.
The core is an OTG device supporting HNP and SRP. When the core is connected to an “A” plug, it is referred to as an A-device. When
the core is connected to a “B” plug it is referred to as a B-device. In Host mode, the core turns off Vbus to conserve power. SRP is a
method by which the B-device signals the A-device to turn on Vbus power. A device must perform both data-line pulsing and Vbus
pulsing, but a host can detect either data-line pulsing or Vbus pulsing for SRP. HNP is a method by which the B-device negotiates and
switches to host role. In Negotiated mode after HNP, the B-device suspends the bus and reverts to the device role.
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15.4.5.1 A-Device Session Request Protocol
The application must set the SRP-Capable bit in the Core USB Configuration register. This enables the core to detect SRP as an A-
device.
1. To save power, the application suspends and turns off port power when the bus is idle by writing the Port Suspend and Port Power
bits in the Host Port Control and Status register.
2. PHY indicates port power off by detecting that VBUS voltage level is no longer valid.
3. The device must detect SE0 for at least 2 ms to start SRP when Vbus power is off.
4. To initiate SRP, the device turns on its data line pull-up resistor for 5 to 10 ms. The core detects data-line pulsing.
5. The device drives Vbus above the A-device session valid (2.0 V minimum) for Vbus pulsing.
The core interrupts the application on detecting SRP. The Session Request Detected bit is set in Global Interrupt Status register
(USB_GINTSTS.SESSREQINT).
6. The application must service the Session Request Detected interrupt and turn on the Port Power bit by writing the Port Power bit in
the Host Port Control and Status register. The PHY indicates port power-on by detecting a valid VBUS level.
7. When the USB is powered, the device connects, completing the SRP process.
15.4.5.2 B-Device Session Request Protocol
The application must set the SRP-Capable bit in the Core USB Configuration register. This enables the core to initiate SRP as a B-
device. SRP is a means by which the core can request a new session from the host.
1. To save power, the host suspends and turns off port power when the bus is idle. PHY indicates port power off by detecting a not
valid VBUS level.
The core sets the Early Suspend bit in the Core Interrupt register after 3 ms of bus idleness. Following this, the core sets the USB
Suspend bit in the Core Interrupt register.
The PHY indicates the end of the B-device session by detecting a VBUS level below session valid.
2. PHY to enables the VBUS discharge function to speed up Vbus discharge.
3. The PHY indicates the session’s end by detecting a session end voltage level on VBUS. This is the initial condition for SRP. The
core requires 2 ms of SE0 before initiating SRP.
The application must wait until Vbus discharges to 0.2 V after USB_GOTGCTL.BSESVLD is deasserted. This discharge time can
be obtained from the datasheet.
4. The application initiates SRP by writing the Session Request bit in the OTG Control and Status register. The core perform data-line
pulsing followed by Vbus pulsing.
5. The host detects SRP from either the data-line or Vbus pulsing, and turns on Vbus. The PHY indicates Vbus power-on by detecting
a valid VBUS level.
6. The core performs Vbus pulsing.
The host starts a new session by turning on Vbus, indicating SRP success. The core interrupts the application by setting the Ses-
sion Request Success Status Change bit in the OTG Interrupt Status register. The application reads the Session Request Success
bit in the OTG Control and Status register.
7. When the USB is powered, the core connects, completing the SRP process.
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15.4.5.3 A-Device Host Negotiation Protocol
HNP switches the USB host role from the A-device to the B-device. The application must set the HNP-Capable bit in the Core USB
Configuration register to enable the core to perform HNP as an A#device.
1. The core sends the B-device a SetFeature b_hnp_enable descriptor to enable HNP support. The B-device’s ACK response indi-
cates that the B-device supports HNP. The application must set Host Set HNP Enable bit in the OTG Control and Status register to
indicate to the core that the B-device supports HNP.
2. When it has finished using the bus, the application suspends by writing the Port Suspend bit in the Host Port Control and Status
register.
3. When the B-device observes a USB suspend, it disconnects, indicating the initial condition for HNP. The B-device initiates HNP
only when it must switch to the host role; otherwise, the bus continues to be suspended.
The core sets the Host Negotiation Detected interrupt in the OTG Interrupt Status register, indicating the start of HNP.
The PHY turns off the D+ and D- pulldown resistors to indicate a device role. The PHY enable the D + pull-up resistor indicates a
connect for B-device.
The application must read the Current Mode bit in the OTG Control and Status register to determine Device mode operation.
4. The B-device detects the connection, issues a USB reset, and enumerates the core for data traffic.
5. The B-device continues the host role, initiating traffic, and suspends the bus when done.
The core sets the Early Suspend bit in the Core Interrupt register after 3 ms of bus idleness. Following this, the core sets the USB
Suspend bit in the Core Interrupt register.
6. In Negotiated mode, the core detects the suspend, disconnects, and switches back to the host role. The core turns on the D+ and
D- pulldown resistors to indicate its assumption of the host role.
7. The core sets the Connector ID Status Change interrupt in the OTG Interrupt Status register. The application must read the con-
nector ID status in the OTG Control and Status register to determine the core’s operation as an A-device. This indicates the com-
pletion of HNP to the application. The application must read the Current Mode bit in the OTG Control and Status register to deter-
mine Host mode operation.
8. The B-device connects, completing the HNP process.
15.4.5.4 B-Device Host Negotiation Protocol
HNP switches the USB host role from B-device to A-device. The application must set the HNP-Capable bit in the Core USB Configura-
tion register to enable the core to perform HNP as a B-device.
1. The A-device sends the SetFeature b_hnp_enable descriptor to enable HNP support. The core’s ACK response indicates that it
supports HNP. The application must set the Device HNP Enable bit in the OTG Control and Status register to indicate HNP sup-
port.
The application sets the HNP Request bit in the OTG Control and Status register to indicate to the core to initiate HNP.
2. When it has finished using the bus, the A-device suspends by writing the Port Suspend bit in the Host Port Control and Status
register.
• The core sets the Early Suspend bit in the Core Interrupt register after 3 ms of bus idleness. Following this, the core sets the
USB Suspend bit in the Core Interrupt register.
• The core disconnects and the A-device detects SE0 on the bus, indicating HNP. The core enables the D+ and D- pulldown re-
sistors to indicate its assumption of the host role. The A-device responds by activating its D+ pull-up resistor within 3 ms of
detecting SE0. The core detects this as a connect.
• The core sets the Host Negotiation Success Status Change interrupt in the OTG Interrupt Status register, indicating the HNP
status. The application must read the Host Negotiation Success bit in the OTG Control and Status register to determine host
negotiation success. The application must read the Current Mode bit in the Core Interrupt register (USB_GINTSTS) to deter-
mine Host mode operation.
3. The application sets the reset bit (USB_HPRT.PRTRST) and the core issues a USB reset and enumerates the A-device for data
traffic
4. The core continues the host role of initiating traffic, and when done, suspends the bus by writing the Port Suspend bit in the Host
Port Control and Status register.
5. In Negotiated mode, when the A-device detects a suspend, it disconnects and switches back to the host role. The core disables the
D+ and D- pulldown resistors to indicate the assumption of the device role.
6. The application must read the Current Mode bit in the Core Interrupt (USB_GINTSTS) register to determine the Host mode opera-
tion.
7. The core connects, completing the HNP process.
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15.4.6 OTG Revision 2.0 Programming Model
OTG Revision 2.0 supports the new Attach Detection Protocol (ADP). This protocol enables a local device (an OTG device or Embed-
ded Host) to detect when a remote device is attached or detached.
Note: ADP is not supported by the core.
In addition to ADP, OTG Revision 2.0 also supports enhanced SRP and HNP, which are described in the following sections:
•15.4.6.1 OTG Revision 2.0 Session Request Protocol
•15.4.6.2 OTG Revision 2.0 Host Negotiation Protocol
Note: VBUS pulsing is not supported in OTG Revision 2.0 mode.
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,____
15.4.6.1 OTG Revision 2.0 Session Request Protocol
When the core is behaving as an A-device, it can power off VBUS when no session is active until the B-device initiates a SRP. The
SRP detection is handled by the core.
The following figure illustrates the programming steps that need to be performed by A-device’s application (core as A-device) when B-
device initiates a SRP to establish a connection.
If host’s application decides to
turn on VBUS voluntarily,
then the application need
not wait for SRP from
device
Program USB_GINTMSK.
(Unmask OTGINT,
MODEMIS,
SESSREQINT)
Host mode (PHY
not driving VBUS)
Interrupt?
Read USB_GINTSTS
GINTSTS.
SESSREQINT = 1?
Host Initialization Steps. Refer to the Host
Initialization section of this chapter for
more information.
(In this step the OTG FSM is in a_host
state.)
Host Transactions
NO
YES
YES
NO
Note
If MODEMIS interrupt is detected during this
process, it means that the
connector has been plugged out or
interchanged. This can be confirmed by
reading USB_GINTSTS.CONIDSTSCHNG.
Figure 15.29. SRP Detection by Core When Operating as A-Device
The following figure illustrates the steps that need to be performed by B-device’s application (core as B-device) in order to establishing
a connection with A-device by signaling a SRP.
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©¢$g
1. Program USB_GINTMSK
(unmask OTGINT)
2. Read USB_GOTGCTL
Device (OTG
FSM in b_idle state)
USB_GOTGCTL.
BSESVLD = 1 ?
Read USB_GINTSTS
YES
(This indicates that VBUS is
already being driven and
hence there is no need for a
SRP)
Interrupt?
Set USB_GOTGCTL.
SESREQ = 1
Device Transactions
USB_GINTSTS.
OTGINT = 1?
Read USB_GOTGINT
USB_GOTGINT.
SESREQSUCSTSCHNG = 1 ?
1. Read USB_GOTGCTL.
2. Clear USB_GOTGINT.SESREQSUCSTSCHNG by
writing a 1.
USB_GOTGCTL.
SESREQSCS = 1?
Device Initialization Steps. For more
information, see Device Initialization
section of this chapter.
NO
NO
YES
NO
NO
NO
YES
YES
YES
Figure 15.30. SRP Initiation by the Core When Acting as a B-Device
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Note: The programming flow illustrated in the previous figure is similar to OTG revision 1.3. This is because the presence or absence of
VBUS pulsing is transparent to the application.
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15.4.6.2 OTG Revision 2.0 Host Negotiation Protocol
When the core is operating as A-device, the application must execute a GetStatus() operation to the Bdevice with a frequency of
THOST_REQ_POLL to determine the state of the host request flag in the B-device. If the host request flag is set in B-device it must
program the core to change its role within THOST_REQ_SUSP.
The following figure shows the programming steps that need to be performed by A-device’s application (core as A-device) in order to
change its role to device. In this figure, the A-device performs a role change, becomes a B-device and then reverts back to host (A-
device) mode of operation.
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Host mode
(Send SetFeature Command to enable
b_hnp_enable feature in HNP capable
devices. HNP polling mechanism is also
involved. This is done when OTG FSM
is in a_host state)
Interrupt?
Remain as Host (The host’s
application can take a call
whether to switch off VBUS or
not)
Host to Device to Host
Program
USB_GOTGCTL.HSTSETHNPEN = 1
Program USB_HPRT.PRTSUSP = 1
Unmask USB_GINTSTS.OTGINT
Read USB_GINTSTS
USB_GINTSTS.
OTGINT = 1?
Interrupt?
Read USB_GINTSTS.CURMOD
USB_GINTSTS.
CURMOD = 0?
C1
C1
1. Unmask USB_GINTSTS.ERLYSUSP.
2. Device Initialization Steps. For more
information, see the Device Initialization
section of this chapter.
Start of Device
transactions
End of Device
transactions
Interrupt?
Read USB_GINTSTS
USB_GINTSTS.
ERLYSUSP = 1 ?
Interrupt?
Read USB_GINTSTS
USB_GINTSTS.
USBSUSP = 1 ?
Application starts
200 ms timer
Interrupt
within
200 ms?
Read USB_GINTSTS
USB_GINTSTS.WKUPINT = 1
or
USB_GINTSTS.RESETDET?
Read USB_GINTSTS
Check that CURMOD = 0
Host Initialization Steps. For more
information, see the Host Initialization
section of this chapter.
Host Mode
Transactions
NO
NO
YES
YES
NO
YES
NO
YES
NO
YES
NO
YES
NO
YES
NO
YES
YES
NO
YES
NO
A-Device as USB Host A-Device as USB Device
Figure 15.31. HNP When the Core is an A-Device
The following figure shows the programming steps that need to be performed by B-device’s application (core as B-device) in order to
change its role to Host. In this figure, the B-device performs a role change, becomes a Host and then reverts back to Device mode of
operation.
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Device mode (Receive
SetFeature Command and OTG
FSM is in b_peripheral state)
Interrupt?
1. Program USB_GOTGCTL.DEVSETHNPEN = 1
2. Program USB_GOTGCTL.HNPREQ = 1
Read USB_GINTSTS
USB_GINTSTS.
ERLYSUSP = 1?
Interrupt?
USB_GINTSTS.
USBSUSP = 1?
C1
Read USB_GINTSTS
Interrupt?
Read USB_GINTSTS
USB_GINTSTS.
OTGINT = 1?
C1
Read USB_GOTGINT
USB_GOTGINT.
HSTNEGSUCSTSCHNG = 1 ?
Clear USB_GOTGINT.
HSTNEGSUCSTSCHNG
Read USB_GOTGCTL
USB_GOTGCTL.
HSTNEGSUCS = 1 ?
Read USB_GINTSTS.
Check that CURMOD = 1.
Host Initialization Steps
(USB_HPRT.PRTPWR should not be
programmed). For more information, see the
Host Initialization section in this chapter.
Set USB_HPRT.PRTSUSP = 1.
Unmask GINTSTS.OTGINT.
Does B-Device
want to remain
host ?
Interrupt?
Read USB_GINTSTS
USB_GINTSTS.
DISCONNINT = 1 ?
Read USB_GINTSTS.CURMOD and ensure
it is 0. Device Initialization Steps. For more
information, see the Device Initialization
section in this chapter.
Program
USB_HPRT.PRTRES = 1 for
a predefined time.
Host Initialization.
(USB_HPRT.PRTPWR should
not be programmed)
The application
should ensure that
this process happens
within 200 ms
NO
YES
YES
NO
NO
NO
YES
NO
YES
NO
YES
Remain as Device
NO
YES
Start of Host
transactions
End of Host
transactions
YES
NO
NO
YES
YES
NO
Device Mode
Transactions
Figure 15.32. HNP When the Core is a B-Device
Note: During HNP process where the B-device is going to assume the role of a host, the B-device application needs to ensure that a
USB reset process is programmed (in USB_HPRT register) within 150 ms (TB_ACON_BSE0) of getting a USB_HPRT.PRTCONNDET
interrupt.
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15.4.7 FIFO RAM Allocation
15.4.7.1 Data FIFO RAM Allocation
External RAM must be allocated among different FIFOs in the core before any transactions can start. The application must follow this
procedure every time it changes core FIFO RAM allocation.
The application must allocate data RAM per FIFO based on the AHB’s operating frequency, the PHY Clock frequency, the available
AHB bandwidth, and the performance required on the USB. Based on the above mentioned criteria, the application must provide a table
as described below with RAM sizes for each FIFO in each mode.
The core shares a single FIFO RAM between transmit FIFO(s) and receive FIFO.
In DMA mode—The FIFO RAM is also used for storing the some register information.
The Device mode Endpoint DMA address registers (USB_DIEP0DMAADDR, USB_DOEP0DMAADDR, USB_DIEPx_DMAADDR,
USB_DOEPx_DMAADDR) and Host mode Channel DMA registers (USB_HCx_DMAADDR) are stored in the FIFO RAM.
• This register information are stored at the end of the FIFO RAM after the space allocated for receive and Transmit FIFO. These
register space must also be taken into account when calculating the total FIFO depth of the core as explained in the following sec-
tions.
The registers USB_DIEPx_DMAADDR/USB_DOEPx_DMAADDR are maintained in RAM.
The following rules apply while calculating how much RAM space must be allocated to store these registers.
Host Mode:
• Slave mode only: No space needed.
• DMA mode: One location per channel.
Device Mode:
• Slave mode only: No space needed.
• DMA mode: One location per end point direction.
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15.4.7.1.1 Device Mode
15.4.7.1.1.1 Tx FIFO Operation
When allocating data RAM for FIFOs in Device mode keep in mind these factors:
1. Receive FIFO RAM allocation:
• RAM for SETUP Packets: 4 * n + 6 locations must be Reserved in the receive FIFO to receive up to n SETUP packets on con-
trol endpoints, where n is the number of control endpoints the device core supports. The core does not use these locations,
which are Reserved for SETUP packets, to write any other data.
• One location for Global OUT NAK
• Status information is written to the FIFO along with each received packet. Therefore, a minimum space of (Largest Packet Size /
4) + 1 must be allotted to receive packets. If a high-bandwidth endpoint is enabled, or multiple isochronous endpoints are ena-
bled, then at least two (Largest Packet Size / 4) + 1 spaces must be allotted to receive back-to-back packets. Typically, two
(Largest Packet Size / 4) + 1 spaces are recommended so that when the previous packet is being transferred to AHB, the USB
can receive the subsequent packet. If AHB latency is high, you must allocate enough space to receive multiple packets. This is
critical to prevent dropping any isochronous packets.
• Along with each endpoint's last packet, transfer complete status information is also pushed to the FIFO. Typically, one location
for each OUT endpoint is recommended.
2. Transmit FIFO RAM Allocation: The minimum RAM space required for each IN Endpoint Transmit FIFO is the maximum packet
size for that particular IN endpoint. More space allocated in the transmit IN Endpoint FIFO results in a better performance on the
USB and can hide latencies on the AHB.
Table 15.3. Device Mode FIFO RAM Sizes
FIFO Name Data RAM Size
Receive data FIFO rx_fifo_size. This must include RAM for setup packets, OUT end-
point control information and data OUT packets, as mentioned
earlier.
Transmit FIFO 0 tx_fifo_size[0]
Transmit FIFO 1 tx_fifo_size[1]
Transmit FIFO 2 tx_fifo_size[2]
... ...
Transmit FIFO i tx_fifo_size[i]
With this information, the following registers must be programmed as follows:
1. Receive FIFO Size Register (USB_GRXFSIZ)
• USB_GRXFSIZ.Receive FIFO Depth = rx_fifo_size;
2. Device IN Endpoint Transmit FIFO0 Size Register (USB_GNPTXFSIZ)
• USB_GNPTXFSIZ.non-periodic Transmit FIFO Depth = tx_fifo_size[0];
• USB_GNPTXFSIZ.non-periodic Transmit RAM Start Address = rx_fifo_size;
3. Device IN Endpoint Transmit FIFO#1 Size Register (USB_DIEPTXF1)
• USB_DIEPTXF1. Transmit RAM Start Address = USB_GNPTXFSIZ.FIFO0 Transmit RAM Start Address + tx_fifo_size[0];
4. Device IN Endpoint Transmit FIFO#2 Size Register (USB_DIEPTXF2)
• USB_DIEPTXF2.Transmit RAM Start Address = USB_DIEPTXF1.Transmit RAM Start Address + tx_fifo_size[1];
5. Device IN Endpoint Transmit FIFO#i Size Register (USB_DIEPTXFi)
• USB_DIEPTXFm.Transmit RAM Start Address = USB_DIEPTXFi-1.Transmit RAM Start Address + tx_fifo_size[i-1];
6. The transmit FIFOs and receive FIFO must be flushed after the RAM allocation is done, for the proper functioning of the FIFOs.
• USB_GRSTCTL.TXFNUM = 0x10
• USB_GRSTCTL.TXFFLSH = 1
• USB_GRSTCTL.RXFFLSH = 1
The application must wait until the TXFFLSH bit and the RXFFLSH bits are cleared before performing any operation on the core.
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15.4.7.1.2 Host Mode
Considerations for allocating data RAM for Host Mode FIFOs are listed here:
Receive FIFO RAM Allocation
Status information is written to the FIFO along with each received packet. Therefore, a minimum space of (Largest Packet Size / 4) + 2
must be allotted to receive packets. If a high-bandwidth channel is enabled, or multiple isochronous channels are enabled, then at least
two (Largest Packet Size / 4) + 2 spaces must be allotted to receive back-to-back packets. Typically, two (Largest Packet Size / 4) + 2
spaces are recommended so that when the previous packet is being transferred to AHB, the USB can receive the subsequent packet. If
AHB latency is high, you must allocate enough space to receive multiple packets.
Along with each host channel’s last packet, information on transfer complete status and channel halted is also pushed to the FIFO. So
two locations must be allocated for this.
For handling NAK in DMA mode, the application must determine the number of Control/Bulk OUT endpoint data that must fit into the
TX_FIFO at the same instant. Based on this, one location each is required for Control/Bulk OUT endpoints.
For example, when the host addresses one Control OUT endpoint and three Bulk OUT endpoints, and all these must fit into the non-
periodic TX_FIFO at the same time, then four extra locations are required in the RX FIFO to store the rewind status information for each
of these endpoints.
Transmit FIFO RAM Allocation
The minimum amount of RAM required for the Host Non-periodic Transmit FIFO is the largest maximum packet size among all suppor-
ted non-periodic OUT channels.
More space allocated in the Transmit Non-periodic FIFO results in better performance on the USB and can hide AHB latencies. Typical-
ly, two Largest Packet Sizes’ worth of space is recommended, so that when the current packet is under transfer to the USB, the AHB
can get the next packet. If the AHB latency is large, then you must allocate enough space to buffer multiple packets.
The minimum amount of RAM required for Host periodic Transmit FIFO is the largest maximum packet size among all supported peri-
odic OUT channels. If there is at lease one High Bandwidth Isochronous OUT endpoint, then the space must be at least two times the
maximum packet size of that channel.
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15.4.7.1.2.1 Internal Register Storage Space Allocation
When operating in DMA mode, the DMA address register for each host channel (USB_HCx_DMAADDR) is stored in the FIFO RAM.
One location for each channel must be reserved for this.
Table 15.4. Host Mode FIFO RAM Sizes
FIFO Name Data RAM Size
Receive Data FIFO rx_fifo_size
Non-periodic Transmit FIFO tx_fifo_size[0]
IN Endpoint Transmit FIFO tx_fifo_size[1]
With this information, the following registers must be programmed:
1. Receive FIFO Size Register (USB_GRXFSIZ)
• USB_GRXFSIZ.RXFDEP = rx_fifo_size;
2. Non-periodic Transmit FIFO Size Register (USB_GNPTXFSIZ)
• USB_GNPTXFSIZ.NPTXFDEP = tx_fifo_size[0];
• USB_GNPTXFSIZ.NPTXFSTADDR = rx_fifo_size;
3. Host Periodic Transmit FIFO Size Register (USB_HPTXFSIZ)
• USB_HPTXFSIZ.PTXFSIZE = tx_fifo_size[1];
• USB_HPTXFSIZ.PTXFSTADDR = USB_GNPTXFSIZ.NPTXFSTADDR + tx_fifo_size[0];
4. The transmit FIFOs and receive FIFO must be flushed after RAM allocation for proper FIFO function.
• USB_GRSTCTL.TXFNUM = 0x10
• USB_GRSTCTL.TXFFLSH = 1
• USB_GRSTCTL.RXFFLSH = 1
The application must wait until the TXFFLSH bit and the RXFFLSH bits are cleared before performing any operation on the core.
15.4.7.1.3 Summary of Guidelines for Choosing Data FIFO RAM Depth in Host Mode
15.4.7.1.3.1 RX FIFO Size
The RX FIFO size must be equal to at least twice the largest value of MPS size used. The recommended minimum RXFIFO depth =
((largest packet size/4)*2)+2. (+2) is required by the core for the status quadlets internally.
15.4.7.1.3.2 Non Periodic TX FIFO Size
This should be equal to at least twice the largest value of MPS size used. The recommended minimum non-periodic TXFIFO depth =
((largest packet size/4)*2).
15.4.7.1.3.3 Periodic TX FIFO Size
The recommended size for Periodic TXFIFO is sum total of (MPS*MC)/4 for all the channels.
Note: In the above recommendations, always round off the MPS value to the nearest multiple of 4. For example, if the largest value of
MPS=125, use the rounded-off value, which is 128.
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15.4.7.1.4 Calculating the Total FIFO Size
The RxFIFO is shared between the host and device. The Host TxFIFOs are also shared with Device IN endpoint TxFIFOs 0 through n.
There are three ways to calculate the total FIFO size.
Method 1
Use this method if you are using the following conditions:
• Minimum FIFO depth allocation
• The FIFO must equal at least one MaxPacketSize (MPS).
Device RxFIFO =
• (4 * number of control endpoints + 6) + ((largest USB packet used / 4) + 1 for status information) + (2 * number of OUT endpoints) +
1 for Global NAK
Note: Include the Control OUT endpoint in the number of OUT endpoints.
Host RxFIFO =
• Slave mode
Minimum requirement: (largest USB packet used / 4) + 1 for status information + 1 transfer complete
• DMA mode
(largest USB packet used / 4) + 1 for status information + 1 transfer complete + 1 location each bulk/ control out endpoint for han-
dling NAK scenario
Host Non-Periodic TxFIFO =
• largest non-periodic USB packet used / 4
Host Periodic TxFIFO =
• Sum total of (MPS*MC)/4 of all periodic channels or 1500 locations, whichever is lower.
Device IN Endpoint TxFIFOs (a separate FIFO is allocated to each IN endpoint) =
• IN Endpoints Max packet Size / 4
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Method 2
Use this method if you are using the recommended minimum FIFO depth allocation with support for high-bandwidth endpoints. This
FIFO allocation enables the core to transfer a packet on the USB while the previous (next) packet is simultaneously transferred to the
AHB. This FIFO allocation improves the core’s performance.
Device RxFIFO =
• (4 * number of control endpoints + 6) + 2 * ((largest USB packet used / 4) + 1) +(2 * number of OUT endpoints) + 1
Host RxFIFO =
• Slave mode
2 * ((largest USB packet used / 4) + 1 + 1)
• DMA mode
2 * ((largest USB packet used / 4) + 1 + 1) + 1 location each bulk/control out endpoint for handling NAK scenario
Host Non-Periodic TxFIFO =
• 2 * (largest non-periodic USB packet used / 4)
Host Periodic TxFIFO =
• Sum total of (MPS*MC)/4 for all periodic channels or 1500 location, whichever is lower.
Device IN Endpoint-Specific TxFIFOs (a separate FIFO is allocated to each endpoint) =
• 2 * (max_pkt_size for the endpoint) / 4.
//DMA mode
OTG Total RAM = (Device RxFIFO or Host RxFIFO; choose the largest one) +((Host Non-Periodic TxFIFO + Host peiod
ic TxFIFO) or
(Device IN Endpoint TxFIFO #0 + #1 + #2 + #n)); choose the largest one +
(1 location per Host channel or 1 location per Device Endpoint direction; choose
the largest one)
//Slave mode
OTG Total RAM = (Device RxFIFO or Host RxFIFO; choose the largest one) +
((Host Non-Periodic TxFIFO + Host peiodic TxFIFO) or
(Device IN Endpoint TxFIFO #0 + #1 + #2 + #n)); choose the largest one
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Method 3
Use this method if you are using the recommended FIFO depth allocation that supports high-bandwidth endpoints and high AHB laten-
cy.
Note:
• x = (AHB latency + time to transfer largest packet on AHB) / time to transfer largest packet on USB.
• The value of x is an integer. Any fractional value is rounded to the nearest integer. For example: x = 20 ms / 17,039 ms = 1.17 ms =
2 ms.
Device RxFIFO =
• (4 * number of control endpoints + 6) + (x + 1) * ((largest USB packet used / 4) + 1)+ (2 * number of OUT endpoints) + 1
Note: Include the Control OUT endpoint in the number of OUT endpoints.
Host RxFIFO =
• Slave mode
(x + 1) * ((largest USB packet used / 4) + 1 + 1)
• DMA mode
(x + 1) * ((largest USB packet used / 4) + 1 + 1) + 1 location each bulk/control out endpoint for handling NAK scenario
Host Non-Periodic TxFIFO =
• (x + 1) * (largest non-periodic USB packet used / 4)
Host Periodic TxFIFO =
• (x+1) * (Sum total of (MPS*MC)/4 of all periodic channels or 1500 locations, whichever is lower).
Device IN Endpoint-Specific TxFIFOs (a separate FIFO is allocated to each endpoint) =
• (x+1)*(max_pkt_size for the endpoint)/4
//DMA mode
OTG Total RAM = (Device RxFIFO or Host RxFIFO; choose the largest one) +
((Host Non-Periodic TxFIFO + Host periodic TxFIFO) OR
(Device IN Endpoint TxFIFO #0 + #1 + #2 + #n); choose the largest one) +
(1 location per Host channel or 1 location per Device Endpoint direction; choose the largest one)
//Slave mode
OTG Total RAM = (Device RxFIFO or Host RxFIFO; choose the largest one) +
((Host Non-Periodic TxFIFO + Host periodic TxFIFO) OR
(Device IN Endpoint TxFIFO #0 + #1 + #2 + #n); choose the largest one)
15.4.7.2 Dynamic FIFO Allocation
The application can change the RAM allocation for each FIFO during the operation of the core.
15.4.7.2.1 Host Mode
In Host mode, before changing FIFO data RAM allocation, the application must determine the following.
All channels are disabled
• All FIFOs are empty
Once these conditions are met, the application can reallocate FIFO data RAM as explained in 15.4.7.1 Data FIFO RAM Allocation.
After reallocating the FIFO data RAM, the application must flush all FIFOs in the core using the USB_GRSTCTL.TXFFLSH (TxFIFO
Flush) and USB_GRSTCTL.RXFFLSH (RxFIFO Flush) fields. Flushing is required to reset the pointers in the FIFOs for proper FIFO
operation after reallocation. For more information on flushing FIFOs, see 15.4.7.2.3 Flushing TxFIFOs in the Core and 15.4.7.2.4 Flush-
ing RxFIFOs in the Core.
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15.4.7.2.2 Device Mode
In Device mode, before changing FIFO data RAM allocation, the application must determine the following.
• All IN and OUT endpoints are disabled
• NAK mode is enabled in the core on all IN endpoints
• Global OUT NAK mode is enabled in the core
• All FIFOs are empty
Once these conditions are met, the application can reallocate FIFO data RAM as explained in 15.4.7.1 Data FIFO RAM Allocation.
When NAK mode is enabled in the core, the core responds with a NAK handshake on all tokens received on the USB, except for SET-
UP packets.
After the reallocating the FIFO data RAM, the application must flush all FIFOs in the core using the USB_GRSTCTL.TXFFLSH (TxFIFO
Flush) and USB_GRSTCTL.RXFFLSH (RxFIFO Flush) fields. Flushing is required to reset the pointers in the FIFOs for proper FIFO
operation after reallocation. For more information on flushing FIFOs, see 15.4.7.2.3 Flushing TxFIFOs in the Core and 15.4.7.2.4 Flush-
ing RxFIFOs in the Core.
15.4.7.2.3 Flushing TxFIFOs in the Core
The application can flush all TxFIFOs in the core using USB_GRSTCTL.TXFFLSH as follows:
1. Check that USB_GINTSTS.GINNAKEFF=0. If this bit is cleared then set USB_DCTL.SGNPINNAK=1.
2. Wait for USB_GINTSTS.GINNAKEFF=1, which indicates the NAK setting has taken effect to all IN endpoints.
3. Poll USB_GRSTCTL.AHBIDLE until it is 1.
AHBIdle = H indicates that the core is not writing anything to the FIFO.
4. Check that USB_GRSTCTL.TXFFLSH =0. If it is 0, then write the TxFIFO number you want to flush to USB_GRSTCTL.TXFNUM.
5. Set USB_GRSTCTL.TXFFLSH=1and wait for it to clear.
6. Set the USB_DCTL.GCNPINNAK bit.
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::|
C:
15.4.7.2.4 Flushing RxFIFOs in the Core
The application can flush all RxFIFOs in the core using USB_GRSTCTL.RXFFLSH as follows:
1. Check the status of the USB_GINTSTS.GOUTNAKEFF bit. If it has been cleared, then set USB_DCTL.SGOUTNAK=1. Else, clear
USB_GINTSTS.GOUTNAKEFF.
NAK Effective interrupt = 1 indicates that the core is not writing to FIFO.
2. Wait for USB_GINTSTS.GOUTNAKEFF=1, which indicates the NAK setting has taken effect to all OUT endpoints.
3. Poll the USB_GRSTCTL.AHBIDLE until it is 1.
AHBIDLE = 1 indicates that the core is not reading anything from the FIFO.
4. Set USB_GRSTCTL.RXFFLSH=1 and wait for it to clear.
5. Set the USB_DCTL.GCOUTNAK bit.
otg_intr_handler
OTG
interrupt?
Wait for interrupt
Host /
Device common
interrupt ?
Read USB_HAINT
Read USB_HCx_INT
Generate channel-specific
software interrupt.
Read USB_GINTSTS
Read USB_GOTGCTL
Generate OTG software
interrupt
Clear interrupt
Generate device global
software interrupt
Generate gobal
software interrupt
RTL
in Device
mode?
Host Port
Interrupt ?
IN endpoint
interrupt ?
Read USB_DAINT
Read USB_DOEPx_INT
Generate OUT-endpoint-
specific software interrupt.
Read USB_DIEPx_INT
Generate IN-endpoint-
specific software interrupt.
Clear interrupt
Read USB_HPRT
Generate port-specific
software interrupt.
Generate host global
software interrupt
Host
global
interrupt ?
Device
global
interrupt ?
NO
YES
NO
YES
NO YES
NO
YES
YES
NO
YES
NO
YES
NO
Figure 15.33. Core Interrupt Handler
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15.4.8 Suspend/Resume and SRP
This chapter describes different methods of saving power when the USB is suspended. This chapter discusses the following topics:
•15.4.8.1 Placing PHY in Low Power Mode Without Entering Suspend
•15.4.8.1.1 When the Core is in Host Mode
•15.4.8.1.2 When the Core is in Device Mode
•15.4.8.2 Suspend
•15.4.8.2.1 Using EM2
•15.4.8.2.1.1 Overview of the EM2 Programming Model
•15.4.8.2.1.2 EM2 When the Core is in Host Mode
•15.4.8.2.1.3 EM2 When the Core is in Device Mode
•15.4.8.2.2 Using Clock Gating in EM0/EM1
•15.4.8.2.2.1 Internal Clock Gating when the Core is in Host Mode
•15.4.8.2.2.2 Internal Clock Gating when the Core is in Device Mode
15.4.8.1 Placing PHY in Low Power Mode Without Entering Suspend
The core can place the PHY in low power mode (the differential receiver is disabled) without entering suspend.
15.4.8.1.1 When the Core is in Host Mode
Programming Flow for the Host Core to Put PHY in Low Power Mode
1. To turn off port power, perform write operation to set the following bits in the USB_HPRT register:
• USB_HPRT.PRTPWR = 0;
• USB_HPRT.PRTENA = 0;
2. To put PHY in low power mode, perform read-modify-write operation to set the following bits in the USB_PCGCCTL register:
• USB_PCGCCTL.STOPPCLK = 1
• USB_PCGCCTL.GATEHCLK = 0
Programming Flow for the Host Core to Make PHY Exit Low Power Mode
If your device is non-SRP capable, the host must implement polling to detect the device connection by turning on the port and exiting
PHY low power mode periodically and checking for connect.
1. To turn on port power, perform write operation to set the following bits in the USB_HPRT register:
• USB_HPRT.PRTPWR = 1
• USB_HPRT.PRTENA = 0
2. To exit PHY low power mode, perform read-modify-write operation to set the following bits in the USB_PCGCCTL register:
• USB_PCGCCTL.STOPPCLK = 0
• USB_PCGCCTL.STOPHCLK = 0
3. Wait for the USB_HPRT Port Connect Detected (PRTCONNDET) bit to be set and do the enumeration of the device.
If your device is SRP-capable, when the device initiates SRP request, the Host core asynchronously detects SRP and the PHY exits
low power mode.
1. Wait for Session Request from the device, or New Session Detected Interrupt (SESSREQINT) in the USB_GINTSTS register.
2. To turn on port power, perform write operation to set the following bits in the USB_HPRT register:
• USB_HPRT.PRTPWR = 1
• USB_HPRT.PRTENA = 0
3. Wait for the USB_HPRT Port Connect Detected (PRTCONNDET) bit to be set and do the enumeration of Device.
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15.4.8.1.2 When the Core is in Device Mode
To make PHY enter low power mode, complete the following steps:
1. Ensure that the following signals are set as follows:
• VBUS voltage level must be below the session valid level (VBUS is not active)
• DP/DM must be SE0
2. From the application, perform read-modify-write operation to set USB_PCGCCTL.STOPPCLK = 1.
15.4.8.2 Suspend
When the core is in Suspend, the following power conservation options are available to use:
•15.4.8.2.1 Using EM2 — You can enter EM2, turning off power (and reseting) parts of the core
•15.4.8.2.2 Using Clock Gating in EM0/EM1 — You can choose gate the AHB clock to some parts of the core
This section discusses methods of conserving power by using one of the above methods.
15.4.8.2.1 Using EM2
15.4.8.2.1.1 Overview of the EM2 Programming Model
When the USB is suspended or the session is not valid, the PHY is driven into Suspend mode, stopping the PHY clock to reduce power
consumption in the PHY and the core. To further reduce power consumption, the core also supports AHB clock gating and using EM2.
The following sections show the procedures you must follow to use EM2 while in suspend/session-off.
During EM2, the clock to the core must be switched to one of the 32 kHz sources (LFRCO or LFXO). This core needs this clock to
detect Resume and SRP events.
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15.4.8.2.1.2 EM2 When the Core is in Host Mode
Host Mode Suspend in EM2
Sequence of operations:
1. Back up the essential registers of the core. Read and store the following core registers:
• USB_GINTMSK • USB_DAINTMSK
• USB_GOTGCTL • USB_DIEPMSK
• USB_GAHBCFG • USB_DOEPMSK
• USB_GUSBCFG • USB_DIEPx_CTL
• USB_GRXFSIZ • USB_DIEPx_TSIZ
• USB_GNPTXFSIZ • USB_DIEPx_DMAADDR
• USB_DCFG • USB_PCGCCTL
• USB_DCTL • USB_DIEPTXFn
2. The application sets the Port Suspend bit in the Host Port CSR, and the core drives a USB suspend.
3. The application sets the Power Clamp bit in the Power and Clock Gating Control register.
4. The application sets the Reset to Power-Down Modules bit in the Power and Clock Gating Control register.
5. The application sets the Stop PHY Clock bit in the Power and Clock Gating Control register, the core suspends the PHY and the
PHY clock stops. If USB_HCFG.ENA32KHZS is set, switch the USBC clock to 32 kHz.
6. Enter EM2.
Host Mode Resume in EM2
Sequence of operations:
1. The resume event starts by the application waking up from EM2 (on an interrupt)
2. Switch USBC clock back to 48 MHz.
3. The application clears the Stop PHY Clock bit and the core takes the PHY back to normal mode. The PHY clock starts up.
4. The application clears the Power Clamp bit. The core starts driving Resume signaling on the USB.
5. The application clears the Reset to Power-Down Modules bit.
6. The application programs registers in the CSR and sets the Port Resume bit in Host Port CSR (Setting the Port Resume bit is
required by the core, although Resume signaling starts earlier).
7. The application clears the Port Resume bit and the core stops driving Resume signaling.
The core is in normal operating mode.
Note: The application must insert delays of at least 2 PHY clocks between all steps in this sequence. This requirement applies to all
USB EM2 programming sequences.
Host Mode Remote Wakeup in EM2
Sequence of operations:
1. The core detects Remote Wakeup signaling on the USB. The PHY exits suspend mode and the PHY clock restarts.
2. The core generates a Remote Wakeup Detected interrupt. The Remote Wakeup interrupt is generated using the 32 kHz clock de-
pending on the USB_HCFG.RESVALID (ResumeValidPeriod) programmed. The Host Core starts resume signaling at this stage.
3. The USBC clock is switched back to normal 48 MHz clock.
4. The application clears the Stop PHY Clock bit.
5. The application clears the Power Clamp bit.
6. The application clears the Reset to Power-Down Modules bit
7. The application programs CSRs and sets the Port Resume bit. The core continues to drive Resume signaling on the USB.
8. The application clears the Port Resume bit and the core stops driving Resume signaling.
The core enters normal operating mode.
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Host Mode Session End in EM2
Sequence of operations:
1. Back up the essential registers of the core. Read and store the following core registers:
• USB_GINTMSK • USB_DAINTMSK
• USB_GOTGCTL • USB_DIEPMSK
• USB_GAHBCFG • USB_DOEPMSK
• USB_GUSBCFG • USB_DIEPx_CTL
• USB_GRXFSIZ • USB_DIEPx_TSIZ
• USB_GNPTXFSIZ • USB_DIEPx_DMAADDR
• USB_DCFG • USB_PCGCCTL
• USB_DCTL • USB_DIEPTXFn
2. The application sets the Port Suspend bit in the Host Port CSR and the core drives a USB suspend.
3. The application clears the Port Power bit.
4. The application sets the Power Clamp bit in the Power and Clock Gating Control register, and the core clamps the signals between
the internal modules on different power rails.
5. The application sets the Reset to Power-Down Modules bit in the Power and Clock Gating Control register.
6. The application sets the Stop PHY Clock bit in the Power and Clock Gating Control register, and the core suspends the PHY, stop-
ping the PHY clock.
7. Switch USBC clock to 32 kHz.
8. Enter EM2.
Host Mode Session Start (EM2 -> EM0)
Sequence of operations:
1. Exit EM2/Enter EM0).
2. Switch USBC clock back to 48 MHz.
3. The application clears the Stop PHY Clock bit.
4. The application clears the Power Clamp bit. The application clears the Reset to Power-Down Modules bit.
5. The application programs CSRs and sets the Port Power bit to turn on VBUS.
6. The core detects the connection and drives the USB reset.
The core enters normal operating mode.
Host Mode Session End (EM0 -> EM2)
Sequence of operations:
1. Back up the essential registers of the core. Read and store the following core registers:
• USB_GINTMSK • USB_DAINTMSK
• USB_GOTGCTL • USB_DIEPMSK
• USB_GAHBCFG • USB_DOEPMSK
• USB_GUSBCFG • USB_DIEPx_CTL
• USB_GRXFSIZ • USB_DIEPx_TSIZ
• USB_GNPTXFSIZ • USB_DIEPx_DMAADDR
• USB_DCFG • USB_PCGCCTL
• USB_DCTL
2. The application sets the Port Suspend bit in the Host Port CSR and the core drives a USB suspend.
3. The application clears the Port Power bit.
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4. The application sets the Power Clamp bit in the Power and Clock Gating Control register, and the core clamps the signals between
the internal modules on different power rails.
5. The application sets the Reset to Power-Down Modules bit in the Power and Clock Gating Control register.
6. The application sets the Stop PHY Clock bit in the Power and Clock Gating Control register.
7. Enter EM2.
Host Mode Sessions Start (SRP) (EM2 -> EM0)
Sequence of operations:
1. The core detects SRP (data line pulsing) on the bus. The core de-asserts the suspend_n signal to the PHY, generating the PHY
clock. The SRP Detected interrupt is generated.
2. The application clears the Stop PHY Clock bit, the core deasserts the suspend_n signal to the PHY to generate the PHY clock.
3. The power (VDD_DN) is turned on and stabilizes.
4. The application clears the Power Clamp bit.
5. The application clears the Reset to Power-Down Modules bit.
6. The application programs the CSRs, and sets the Port Power bit to turn on VBUS.
7. The core detects device connection and drives a USB reset.
The core enters normal operating mode.
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15.4.8.2.1.3 EM2 When the Core is in Device Mode
Device Mode Suspend With EM2
In Device mode, the device validates the host-driven Resume signal for a period of 1.5 μs (75 clock cycles at 48 MHz). With a 32-KHz
clock, 2.34 ms is required (75 clock cycles at 32 KHz) to detect the resume. Hence, the application programs USB_DCFG.RESVALID
with a value of 4 clock cycles (125 μs). If the core is in Suspend mode, the device thus detects the resume and the host signals a
resume for a minimum of 125 μs.
If the device is being reset from suspend, it begins a high-speed detection handshake after detecting SE0 for no fewer than 2.5 μs. With
a 48-MHz clock, detection occurs after 120 clock cycles (2.5 μs). With a 32-kHz clock, 120 clock cycles signifies 3.75 msec. Hence, a
programmable value of 4 clock cycles (125 μs) is used to detect reset.
The 32-KHz Suspend feature incorporates switching to the 32-KHz clock during suspend and resume/ remote wakeup until the system
comes up and starts driving 48 MHz.
Sequence of operations:
1. Detect Suspend state. Wait for an interrupt from the device core and check that USB_GINTSTS.USBSUSP is set to 1.
2. Back up the essential registers of the core. Read and store the following core registers:
• USB_GINTMSK • USB_DAINTMSK
• USB_GOTGCTL • USB_DIEPMSK
• USB_GAHBCFG • USB_DOEPMSK
• USB_GUSBCFG • USB_DIEPx_CTL
• USB_GRXFSIZ • USB_DIEPx_TSIZ
• USB_GNPTXFSIZ • USB_DIEPx_DMAADDR
• USB_DCFG • USB_PCGCCTL
• USB_DCTL • USB_DIEPTXFn
3. The application sets the PWRCLMP bit in the Power and Clock Gating Control (USB_PCGCCTL) register.
4. The application sets the USB_PCGCCTL.RSTPDWNMODULE bit.
5. The application sets the USB_PCGCCTL.STOPPCLK bit.
6. Switch USB Core Clock (USBC) to 32 kHz.
7. Enter EM2.
Device Mode Resume (EM2 -> EM0)
Sequence if operations:
1. The core detects Resume signaling on the USB. The core generates a Resume Detected interrupt.
2. Switch USB Core Clock (USBC) back to 48 MHz.
3. The application clears the STOPPCLK bit.
4. The application clears the USB_PCGCCTL.PWRCLMP and USB_PCGCCTL.RSTPDWNMODULE bits.
5. Restore the USB_GUSBCFG and USB_DCFG registers with the values stored during the Save operation before entering EM2.
6. Restore the following core registers with the values stored during the Save operation before entering EM2:
• USB_GINTMSK • USB_DIEPMSK
• USB_GOTGCTL • USB_DOEPMSK
• USB_GUSBCFG • USB_DIEPx_CTL
• USB_GRXFSIZ • USB_DIEPx_TSIZ
• USB_GNPTXFSIZ • USB_DIEPx_DMAADDR
• USB_DAINTMSK • USB_DIEPTXFn
7. The application programs CSRs, then sets the Power-On Programming Done bit in the Device Control register.
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Device Mode Remote Wakeup (EM2 -> EM0)
Sequence if operations:
1. An interrupt wakes up the device from EM2.
2. Switch USB Core Clock (USBC) back to 48 MHz.
3. The application clears the STOPPCLK and GATEHCLK bits in the USB_PCGCCTL register.
4. The application clears the USB_PCGCCTL.PWRCLMP and USB_PCGCCTL.RSTPDWNMODULE bits.
5. Restore the USB_GUSBCFG and USB_DCFG registers with the values stored during the Save operation before entering EM2 .
6. Drive remote wakeup from the core. Program USB_DCTL by performing write-only operation with the following values:
• USB_DCTL.RMTWKUPSIG = 1
• Other Bits = Value stored during the Save operation before entering EM2
7. Clear all interrupt status. Wait for at least 1 millisecond of remote wakeup time and then program GINSTS register with
0xFFFFFFFF to clear all the status register fields.
8. Restore the following core registers with the values stored during the Save operation before entering EM2:
• USB_GINTMSK • USB_DIEPMSK
• USB_GOTGCTL • USB_DOEPMSK
• USB_GUSBCFG • USB_DIEPx_CTL
• USB_GRXFSIZ • USB_DIEPx_TSIZ
• USB_GNPTXFSIZ • USB_DIEPx_DMAADDR
• USB_DAINTMSK • USB_DIEPTXFn
9. Wait for remote wakeup time (1-15ms) and then program USB_DCTL by performing read-modify-write to set
USB_DCTL.RMTWKUPSIG = 0.
Device Mode Session End (EM0 -> EM2)
Sequence of operations:
1. The core detects a USB suspend and generates a Suspend Detected interrupt. The host turns off VBUS.
2. The application sets the Power Clamp bit in the Power and Clock Gating Control register.
3. The application sets the Reset to Power-Down Modules bit in the Power and Clock Gating Control register.
4. The application sets the Stop PHY Clock bit in the Power and Clock Gating Control register.
5. Switch USB Core clock (USBC) to 32 kHz.
6. Enter EM2.
Device Mode Session Start (EM2 -> EM0)
Sequence of operations:
1. The core detects VBUS on (voltage level within session-valid). A New Session Detected interrupt is generated.
2. Switch USB Core clock (USBC) back to 48 MHz.
3. The application clears the Stop PHY Clock bit.
4. The application clears the Power Clamp bit.
5. The application clears the Reset to Power-Down Modules bit.
6. The application programs CSRs.
7. The cores detects a USB reset.
The core enters normal operating mode.
15.4.8.2.2 Using Clock Gating in EM0/EM1
The core supports HCLK gating to reduce dynamic power to internal modules to the core during Suspend/ session-off state in EM0 and
EM1.
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15.4.8.2.2.1 Internal Clock Gating when the Core is in Host Mode
The following sections show the procedures you must follow to use the clock gating feature.
Host Mode Suspend and Resume With Clock Gating
Sequence of operations:
1. The application sets the Port Suspend bit in the Host Port CSR, and the core drives a USB suspend.
2. The application sets the Stop PHY Clock bit in the Power and Clock Gating Control register. The application sets the Gate hclk bit
in the Power and Clock Gating Control register, the core gates the hclk internally.
3. The core remains in Suspend mode.
4. The application clears the Gate hclk and Stop PHY Clock bits, and the PHY clock is generated.
5. The application sets the Port Resume bit, and the core starts driving Resume signaling.
6. The application clears the Port Resume bit after at least 20 ms.
7. The core is in normal operating mode.
Host Mode Suspend and Remote Wakeup With Clock Gating
Sequence of operations:
1. The application sets the Port Suspend bit in the Host Port CSR, and the core drives a USB suspend.
2. The application sets the Stop PHY Clock bit in the Power and Clock Gating Control register. The application sets the Gate hclk bit
in the Power and Clock Gating Control register, and the core gates hclk internally.
3. The core remains in Suspend mode.
4. The Remote Wakeup signaling from the device is detected. The core generates a Remote Wakeup Detected interrupt.
5. The application clears the Gate hclk and Stop PHY Clock bits. The core sets the Port Resume bit.
6. The application clears the Port Resume bit after at least 20 ms.
7. The core is in normal operating mode.
Host Mode Session End and Start With Clock Gating
Sequence of operations:
1. The application sets the Port Suspend bit in the Host Port CSR, and the core drives a USB suspend.
2. The application clears the Port Power bit. The core turns off VBUS.
3. The application sets the Stop PHY Clock bit in the Power and Clock Gating Control register. The application sets the Gate hclk bit
in the Power and Clock Gating Control register, and the core gates hclk internally.
4. The core remains in Low-Power mode.
5. The application clears the Gate hclk bit and the application clears the Stop PHY Clock bit to start the PHY clock.
6. The application sets the Port Power bit to turn on VBUS.
7. The core detects device connection and drives a USB reset.
8. The core is in normal operating mode.
Host Mode Session End and SRP With Clock Gating
Sequence of operations:
1. The application sets the Port Suspend bit in the Host Port CSR, and the core drives a USB suspend.
2. The application clears the Port Power bit. The core turns off VBUS.
3. The application sets the Stop PHY Clock bit in the Power and Clock Gating Control register. The application sets the Gate hclk bit
in the Power and Clock Gating Control register, and the core gates hclk internally.
4. The core remains in Low-Power mode.
5. SRP (data line pulsing) from the device is detected. An SRP Request Detected interrupt is generated.
6. The application clears the Gate hclk bit and the Stop PHY Clock bit.
7. The core sets the Port Power bit to turn on VBUS.
8. The core detects device connection and drives a USB reset.
9. The core is in normal operating mode.
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15.4.8.2.2.2 Internal Clock Gating when the Core is in Device Mode
The following sections show the procedures you must follow to use the clock gating feature.
Device Mode Suspend and Resume With Clock Gating
Sequence of operations:
1. The core detects a USB suspend and generates a Suspend Detected interrupt.
2. The application sets the Stop PHY Clock bit in the Power and Clock Gating Control register. The application sets the Gate hclk bit
in the Power and Clock Gating Control register, and the core gates hclk.
3. The core remains in Suspend mode.
4. The Resume signaling from the host is detected. A Resume Detected interrupt is generated.
5. The application clears the Gate hclk bit and the Stop PHY Clock bit.
6. The host finishes Resume signaling.
7. The core is in normal operating mode.
Device Mode Suspend and Remote Wakeup With Clock Gating
Sequence of operations:
1. The core detects a USB suspend and generates a Suspend Detected interrupt.
2. The application sets the Stop PHY Clock bit in the Power and Clock Gating Control register. The application sets the Gate hclk bit
in the Power and Clock Gating Control register, the core gates hclk.
3. The core remains in Suspend mode.
4. The application clears the Gate hclk bit and the Stop PHY Clock bit.
5. The application sets the Remote Wakeup bit in the Device Control register, the core starts driving Remote Wakeup signaling.
6. The host drives Resume signaling.
7. The core is in normal operating mode.
Device Mode Session End and Start With Clock Gating
Sequence of operations:
1. The core detects a USB suspend, and generates a Suspend Detected interrupt. The host turns off VBUS.
2. The application sets the Stop PHY Clock bit in the Power and Clock Gating Control register. The application sets the Gate hclk bit
in the Power and Clock Gating Control register, and the core gates hclk.
3. The core remains in Low-Power mode.
4. The new session is detected (A session-valid voltage is detected). A New Session Detected interrupt is generated.
5. The application clears the Gate hclk and Stop PHY Clock bits.
6. The core detects USB reset.
7. The core is in normal operating mode.
Device Mode Session End and SRP With Clock Gating
Sequence of operations:
1. The core detects a USB suspend, and generates a Suspend Detected interrupt. The host turns off VBUS.
2. The application sets the Stop PHY Clock bit in the Power and Clock Gating Control register. The application sets the Gate hclk bit
in the Power and Clock Gating Control register, and the core gates hclk.
3. The core remains in Low-Power mode.
4. The application clears the Gate hclk and Stop PHY Clock bits.
5. The application sets the SRP Request bit, and the core drives data line and VBUS pulsing.
6. The host turns on VBUS, detects device connection, and drives a USB reset.
7. The core is in normal operating mode.
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15.4.9 Register Usage
Only the Core Global, Power and Clock Gating, Data FIFO Access, and Host Port registers can be accessed in both Host and Device
modes. When the core is operating in one mode, either Device or Host, the application must not access registers from the other mode.
If an illegal access occurs, a Mode Mismatch interrupt is generated and reflected in the Core Interrupt register (USB_GINTSTS.MO-
DEMIS).
When the core switches from one mode to another, the registers in the new mode must be reprogrammed as they would be after a
power-on reset.
The memory map for the core is as follows:
• Core Global Registers are located in the address offset-range [0x3C000, 0x3C3FF] and typically start with first letter G.
• Host Mode Registers are located in the address offset-range [0x3C400, 0x3C7FF] and start with first letter H.
• Device Mode Registers are located in the address offset-range [0x3C800, 0x3CDFF] and start with first letter D.
• The Power and Clock Gating register is located at offset 0x3CE00.
• The Device EP/Host Channel FIFOs start at address offset 0x3D000 with 4K spacing. These registers, available in both Host and
Device modes, are used to read or write the FIFO space for a specific endpoint or a channel, in a given direction. If a host channel is
of type IN, the FIFO can only be read on the channel. Similarly, if a host channel is of type OUT, the FIFO can only be written on the
channel.
• The Direct RAM Access area start at address offset 0x5C000.
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15.5 Register Map
The offset register address is relative to the registers base address.
Offset Name Type Description
0x000 USB_CTRL RW System Control Register
0x004 USB_STATUS RSystem Status Register
0x008 USB_IF RInterrupt Flag Register
0x00C USB_IFS W1 Interrupt Flag Set Register
0x010 USB_IFC (R)W1 Interrupt Flag Clear Register
0x014 USB_IEN RW Interrupt Enable Register
0x018 USB_ROUTE RW I/O Routing Register
0x3C000 USB_GOTGCTL RWH OTG Control and Status Register
0x3C004 USB_GOTGINT RW1H OTG Interrupt Register
0x3C008 USB_GAHBCFG RW AHB Configuration Register
0x3C00C USB_GUSBCFG RWH USB Configuration Register
0x3C010 USB_GRSTCTL RWH Reset Register
0x3C014 USB_GINTSTS RWH Interrupt Register
0x3C018 USB_GINTMSK RW Interrupt Mask Register
0x3C01C USB_GRXSTSR RReceive Status Debug Read Register
0x3C020 USB_GRXSTSP RReceive Status Read and Pop Register
0x3C024 USB_GRXFSIZ RW Receive FIFO Size Register
0x3C028 USB_GNPTXFSIZ RW Non-periodic Transmit FIFO Size Register
0x3C02C USB_GNPTXSTS RNon-periodic Transmit FIFO/Queue Status Register
0x3C05C USB_GDFIFOCFG RW Global DFIFO Configuration Register
0x3C100 USB_HPTXFSIZ RW Host Periodic Transmit FIFO Size Register
0x3C104 USB_DIEPTXF1 RW Device IN Endpoint Transmit FIFO 1 Size Register
0x3C108 USB_DIEPTXF2 RW Device IN Endpoint Transmit FIFO 2 Size Register
0x3C10C USB_DIEPTXF3 RW Device IN Endpoint Transmit FIFO 3 Size Register
0x3C110 USB_DIEPTXF4 RW Device IN Endpoint Transmit FIFO 4 Size Register
0x3C114 USB_DIEPTXF5 RW Device IN Endpoint Transmit FIFO 5 Size Register
0x3C118 USB_DIEPTXF6 RW Device IN Endpoint Transmit FIFO 6 Size Register
0x3C400 USB_HCFG RW Host Configuration Register
0x3C404 USB_HFIR RW Host Frame Interval Register
0x3C408 USB_HFNUM RHost Frame Number/Frame Time Remaining Register
0x3C410 USB_HPTXSTS RHost Periodic Transmit FIFO/Queue Status Register
0x3C414 USB_HAINT RHost All Channels Interrupt Register
0x3C418 USB_HAINTMSK RW Host All Channels Interrupt Mask Register
0x3C440 USB_HPRT RWH Host Port Control and Status Register
0x3C500 USB_HC0_CHAR RWH Host Channel x Characteristics Register
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Offset Name Type Description
0x3C508 USB_HC0_INT RW1H Host Channel x Interrupt Register
0x3C50C USB_HC0_INTMSK RW Host Channel x Interrupt Mask Register
0x3C510 USB_HC0_TSIZ RW Host Channel x Transfer Size Register
0x3C514 USB_HC0_DMAADDR RW Host Channel x DMA Address Register
... USB_HCx_CHAR RWH Host Channel x Characteristics Register
... USB_HCx_INT RW1H Host Channel x Interrupt Register
... USB_HCx_INTMSK RW Host Channel x Interrupt Mask Register
... USB_HCx_TSIZ RW Host Channel x Transfer Size Register
... USB_HCx_DMAADDR RW Host Channel x DMA Address Register
0x3C6A0 USB_HC13_CHAR RWH Host Channel x Characteristics Register
0x3C6A8 USB_HC13_INT RW1H Host Channel x Interrupt Register
0x3C6AC USB_HC13_INTMSK RW Host Channel x Interrupt Mask Register
0x3C6B0 USB_HC13_TSIZ RW Host Channel x Transfer Size Register
0x3C6B4 USB_HC13_DMAADDR RW Host Channel x DMA Address Register
0x3C800 USB_DCFG RW Device Configuration Register
0x3C804 USB_DCTL RWH Device Control Register
0x3C808 USB_DSTS RDevice Status Register
0x3C810 USB_DIEPMSK RW Device IN Endpoint Common Interrupt Mask Register
0x3C814 USB_DOEPMSK RW Device OUT Endpoint Common Interrupt Mask Register
0x3C818 USB_DAINT RDevice All Endpoints Interrupt Register
0x3C81C USB_DAINTMSK RW Device All Endpoints Interrupt Mask Register
0x3C828 USB_DVBUSDIS RW Device VBUS Discharge Time Register
0x3C82C USB_DVBUSPULSE RW Device VBUS Pulsing Time Register
0x3C834 USB_DIEPEMPMSK RW Device IN Endpoint FIFO Empty Interrupt Mask Register
0x3C900 USB_DIEP0CTL RWH Device IN Endpoint 0 Control Register
0x3C908 USB_DIEP0INT RWH Device IN Endpoint 0 Interrupt Register
0x3C910 USB_DIEP0TSIZ RW Device IN Endpoint 0 Transfer Size Register
0x3C914 USB_DIEP0DMAADDR RW Device IN Endpoint 0 DMA Address Register
0x3C918 USB_DIEP0TXFSTS RDevice IN Endpoint 0 Transmit FIFO Status Register
0x3C920 USB_DIEP0_CTL RWH Device IN Endpoint x+1 Control Register
0x3C928 USB_DIEP0_INT RWH Device IN Endpoint x+1 Interrupt Register
0x3C930 USB_DIEP0_TSIZ RW Device IN Endpoint x+1 Transfer Size Register
0x3C934 USB_DIEP0_DMAADDR RW Device IN Endpoint x+1 DMA Address Register
0x3C938 USB_DIEP0_TXFSTS RDevice IN Endpoint x+1 Transmit FIFO Status Register
... USB_DIEPx_CTL RWH Device IN Endpoint x+1 Control Register
... USB_DIEPx_INT RWH Device IN Endpoint x+1 Interrupt Register
... USB_DIEPx_TSIZ RW Device IN Endpoint x+1 Transfer Size Register
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Offset Name Type Description
... USB_DIEPx_DMAADDR RW Device IN Endpoint x+1 DMA Address Register
... USB_DIEPx_TXFSTS RDevice IN Endpoint x+1 Transmit FIFO Status Register
0x3C9C0 USB_DIEP5_CTL RWH Device IN Endpoint x+1 Control Register
0x3C9C8 USB_DIEP5_INT RWH Device IN Endpoint x+1 Interrupt Register
0x3C9D0 USB_DIEP5_TSIZ RW Device IN Endpoint x+1 Transfer Size Register
0x3C9D4 USB_DIEP5_DMAADDR RW Device IN Endpoint x+1 DMA Address Register
0x3C9D8 USB_DIEP5_TXFSTS RDevice IN Endpoint x+1 Transmit FIFO Status Register
0x3CB00 USB_DOEP0CTL RWH Device OUT Endpoint 0 Control Register
0x3CB08 USB_DOEP0INT RWH Device OUT Endpoint 0 Interrupt Register
0x3CB10 USB_DOEP0TSIZ RW Device OUT Endpoint 0 Transfer Size Register
0x3CB14 USB_DOEP0DMAADDR RW Device OUT Endpoint 0 DMA Address Register
0x3CB20 USB_DOEP0_CTL RWH Device OUT Endpoint x+1 Control Register
0x3CB28 USB_DOEP0_INT RWH Device OUT Endpoint x+1 Interrupt Register
0x3CB30 USB_DOEP0_TSIZ RWH Device OUT Endpoint x+1 Transfer Size Register
0x3CB34 USB_DOEP0_DMAADDR RW Device OUT Endpoint x+1 DMA Address Register
... USB_DOEPx_CTL RWH Device OUT Endpoint x+1 Control Register
... USB_DOEPx_INT RWH Device OUT Endpoint x+1 Interrupt Register
... USB_DOEPx_TSIZ RWH Device OUT Endpoint x+1 Transfer Size Register
... USB_DOEPx_DMAADDR RW Device OUT Endpoint x+1 DMA Address Register
0x3CBC0 USB_DOEP5_CTL RWH Device OUT Endpoint x+1 Control Register
0x3CBC8 USB_DOEP5_INT RWH Device OUT Endpoint x+1 Interrupt Register
0x3CBD0 USB_DOEP5_TSIZ RWH Device OUT Endpoint x+1 Transfer Size Register
0x3CBD4 USB_DOEP5_DMAADDR RW Device OUT Endpoint x+1 DMA Address Register
0x3CE00 USB_PCGCCTL RWH Power and Clock Gating Control Register
0x3D000 USB_FIFO0D0 RW Device EP 0/Host Channel 0 FIFO
... USB_FIFO0Dx RW Device EP 0/Host Channel 0 FIFO
0x3D7FC USB_FIFO0D511 RW Device EP 0/Host Channel 0 FIFO
0x3E000 USB_FIFO1D0 RW Device EP 1/Host Channel 1 FIFO
... USB_FIFO1Dx RW Device EP 1/Host Channel 1 FIFO
0x3E7FC USB_FIFO1D511 RW Device EP 1/Host Channel 1 FIFO
0x3F000 USB_FIFO2D0 RW Device EP 2/Host Channel 2 FIFO
... USB_FIFO2Dx RW Device EP 2/Host Channel 2 FIFO
0x3F7FC USB_FIFO2D511 RW Device EP 2/Host Channel 2 FIFO
0x40000 USB_FIFO3D0 RW Device EP 3/Host Channel 3 FIFO
... USB_FIFO3Dx RW Device EP 3/Host Channel 3 FIFO
0x407FC USB_FIFO3D511 RW Device EP 3/Host Channel 3 FIFO
0x41000 USB_FIFO4D0 RW Device EP 4/Host Channel 4 FIFO
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Offset Name Type Description
... USB_FIFO4Dx RW Device EP 4/Host Channel 4 FIFO
0x417FC USB_FIFO4D511 RW Device EP 4/Host Channel 4 FIFO
0x42000 USB_FIFO5D0 RW Device EP 5/Host Channel 5 FIFO
... USB_FIFO5Dx RW Device EP 5/Host Channel 5 FIFO
0x427FC USB_FIFO5D511 RW Device EP 5/Host Channel 5 FIFO
0x43000 USB_FIFO6D0 RW Device EP 6/Host Channel 6 FIFO
... USB_FIFO6Dx RW Device EP 6/Host Channel 6 FIFO
0x437FC USB_FIFO6D511 RW Device EP 6/Host Channel 6 FIFO
0x44000 USB_FIFO7D0 RW Host Channel 7 FIFO
... USB_FIFO7Dx RW Host Channel 7 FIFO
0x447FC USB_FIFO7D511 RW Host Channel 7 FIFO
0x45000 USB_FIFO8D0 RW Host Channel 8 FIFO
... USB_FIFO8Dx RW Host Channel 8 FIFO
0x457FC USB_FIFO8D511 RW Host Channel 8 FIFO
0x46000 USB_FIFO9D0 RW Host Channel 9 FIFO
... USB_FIFO9Dx RW Host Channel 9 FIFO
0x467FC USB_FIFO9D511 RW Host Channel 9 FIFO
0x47000 USB_FIFO10D0 RW Host Channel 10 FIFO
... USB_FIFO10Dx RW Host Channel 10 FIFO
0x477FC USB_FIFO10D511 RW Host Channel 10 FIFO
0x48000 USB_FIFO11D0 RW Host Channel 11 FIFO
... USB_FIFO11Dx RW Host Channel 11 FIFO
0x487FC USB_FIFO11D511 RW Host Channel 11 FIFO
0x49000 USB_FIFO12D0 RW Host Channel 12 FIFO
... USB_FIFO12Dx RW Host Channel 12 FIFO
0x497FC USB_FIFO12D511 RW Host Channel 12 FIFO
0x4A000 USB_FIFO13D0 RW Host Channel 13 FIFO
... USB_FIFO13Dx RW Host Channel 13 FIFO
0x4A7FC USB_FIFO13D511 RW Host Channel 13 FIFO
0x5C000 USB_FIFORAM0 RW Direct Access to Data FIFO RAM for Debugging (2 KB)
... USB_FIFORAMx RW Direct Access to Data FIFO RAM for Debugging (2 KB)
0x5C7FC USB_FIFORAM511 RW Direct Access to Data FIFO RAM for Debugging (2 KB)
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15.6 Register Description
15.6.1 USB_CTRL - System Control Register
Offset Bit Position
0x000
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
16
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
Reset
0x0
0x0
0
0
0
0
Access
RW
RW
RW
RW
RW
RW
Name
BIASPROGEM23
BIASPROGEM01
VREGOSEN
VREGDIS
DMPUAP
VBUSENAP
Bit Name Reset Access Description
31:26 Reserved To ensure compatibility with future devices, always write bits to 0. More information in 2.1 Conven-
tions.
25:24 BIASPROGEM23 0x0 RW Regulator Bias Programming Value in EM2/3
Regulator bias current setting in EM2/3 (i.e. while USB in suspend).
23:22 Reserved To ensure compatibility with future devices, always write bits to 0. More information in 2.1 Conven-
tions.
21:20 BIASPROGEM01 0x0 RW Regulator Bias Programming Value in EM0/1
Regulator bias current setting in EM0/1 (i.e. while USB active).
19:18 Reserved To ensure compatibility with future devices, always write bits to 0. More information in 2.1 Conven-
tions.
17 VREGOSEN 0 RW VREGO Sense Enable
Set this bit to enable USB_VREGO voltage level sensing.
16 VREGDIS 0 RW Voltage Regulator Disable
Set this bit to disable the voltage regulator.
15:2 Reserved To ensure compatibility with future devices, always write bits to 0. More information in 2.1 Conven-
tions.
1 DMPUAP 0 RW DMPU Active Polarity
Use this bit to select the active polarity of the USB_DMPU pin.
Value Mode Description
0 LOW USB_DMPU is active low.
1 HIGH USB_DMPU is active high.
0 VBUSENAP 0 RW VBUSEN Active Polarity
Use this bit to select the active polarity of the USB_VBUSEN pin.
Value Mode Description
0 LOW USB_VBUSEN is active low.
1 HIGH USB_VBUSEN is active high.
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15.6.2 USB_STATUS - System Status Register
Offset Bit Position
0x004
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
16
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
Reset
0
Access
R
Name
VREGOS
Bit Name Reset Access Description
31:1 Reserved To ensure compatibility with future devices, always write bits to 0. More information in 2.1 Conven-
tions.
0 VREGOS 0 R VREGO Sense Output
USB_VREGO Voltage Sense output. 0 when no USB_VREGO voltage, 1 when USB_VREGO above approximately 1.8 V.
Always 0 when VREGOSEN in USB_CTRL is 0.
15.6.3 USB_IF - Interrupt Flag Register
Offset Bit Position
0x008
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
16
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
Reset
1
1
Access
R
R
Name
VREGOSL
VREGOSH
Bit Name Reset Access Description
31:2 Reserved To ensure compatibility with future devices, always write bits to 0. More information in 2.1 Conven-
tions.
1 VREGOSL 1 R VREGO Sense Low Interrupt Flag
Set when USB_VREGO drops below approximately 1.8 V.
0 VREGOSH 1 R VREGO Sense High Interrupt Flag
Set when USB_VREGO goes above approximately 1.8 V.
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15.6.4 USB_IFS - Interrupt Flag Set Register
Offset Bit Position
0x00C
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
16
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
Reset
0
0
Access
W1
W1
Name
VREGOSL
VREGOSH
Bit Name Reset Access Description
31:2 Reserved To ensure compatibility with future devices, always write bits to 0. More information in 2.1 Conven-
tions.
1 VREGOSL 0 W1 Set VREGO Sense Low Interrupt Flag
Write to 1 to set the VREGO Sense Low Interrupt Flag.
0 VREGOSH 0 W1 Set VREGO Sense High Interrupt Flag
Write to 1 to set the VREGO Sense High Interrupt Flag.
15.6.5 USB_IFC - Interrupt Flag Clear Register
Offset Bit Position
0x010
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
16
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
Reset
0
0
Access
(R)W1
(R)W1
Name
VREGOSL
VREGOSH
Bit Name Reset Access Description
31:2 Reserved To ensure compatibility with future devices, always write bits to 0. More information in 2.1 Conven-
tions.
1 VREGOSL 0 (R)W1 Clear VREGO Sense Low Interrupt Flag
Write to 1 to clear the VREGO Sense Low Interrupt Flag.
0 VREGOSH 0 (R)W1 Clear VREGO Sense High Interrupt Flag
Write to 1 to clear the VREGO Sense High Interrupt Flag.
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15.6.6 USB_IEN - Interrupt Enable Register
Offset Bit Position
0x014
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
16
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
Reset
0
0
Access
RW
RW
Name
VREGOSL
VREGOSH
Bit Name Reset Access Description
31:2 Reserved To ensure compatibility with future devices, always write bits to 0. More information in 2.1 Conven-
tions.
1 VREGOSL 0 RW VREGO Sense Low Interrupt Enable
Enable interrupt on VREGO Sense Low.
0 VREGOSH 0 RW VREGO Sense High Interrupt Enable
Enable interrupt on VREGO Sense High.
15.6.7 USB_ROUTE - I/O Routing Register
Offset Bit Position
0x018
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
16
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
Reset
0
0
0
Access
RW
RW
RW
Name
DMPUPEN
VBUSENPEN
PHYPEN
Bit Name Reset Access Description
31:3 Reserved To ensure compatibility with future devices, always write bits to 0. More information in 2.1 Conven-
tions.
2 DMPUPEN 0 RW DMPU Pin Enable
When set, the USB_DMPU pin is enabled.
1 VBUSENPEN 0 RW VBUSEN Pin Enable
When set, the USB_VBUSEN pin is enabled.
0 PHYPEN 0 RW USB PHY Pin Enable
When set, the USB PHY and USB pins are enabled. The USB_DP and USB_DM are changed from regular GPIO pins to
USB pins.
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15.6.8 USB_GOTGCTL - OTG Control and Status Register
The OTG Control and Status register controls the behavior and reflects the status of the OTG function of the core.
Offset Bit Position
0x3C000
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
16
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
Reset
0
0
0
0
1
0
0
0
0
0
0
0
0
0
0
0
0
Access
RW
R
R
R
R
RW
RW
RW
R
RW
RW
RW
RW
RW
RW
RW
R
Name
OTGVER
BSESVLD
ASESVLD
DBNCTIME
CONIDSTS
DEVHNPEN
HSTSETHNPEN
HNPREQ
HSTNEGSCS
AVALIDOVVAL
AVALIDOVEN
BVALIDOVVAL
BVALIDOVEN
VBVALIDOVVAL
VBVALIDOVEN
SESREQ
SESREQSCS
Bit Name Reset Access Description
31:21 Reserved To ensure compatibility with future devices, always write bits to 0. More information in 2.1 Conven-
tions.
20 OTGVER 0 RW OTG Version
Indicates the OTG revision.
Value Mode Description
0 OTG13 OTG Version 1.3. In this version the core supports data line pulsing
and VBus pulsing for SRP.
1 OTG20 OTG Version 2.0. In this version the core supports only data line puls-
ing for SRP.
19 BSESVLD 0 R B-Session Valid device only
Indicates the Device mode transceiver status for B-session valid. In OTG mode, you can use this bit to determine if the
device is connected or disconnected.
18 ASESVLD 0 R A-Session Valid host only
Indicates the Host mode transceiver status for A-session valid.
17 DBNCTIME 0 R Long/Short Debounce Time host only
Indicates the debounce time of a detected connection.
Value Mode Description
0 LONG Long debounce time, used for physical connections (100 ms + 2.5 us).
1 SHORT Short debounce time, used for soft connections (2.5 us).
16 CONIDSTS 1 R Connector ID Status host and device
Indicates the connector ID status on a connect event.
Value Mode Description
0 A The core is in A-Device mode.
1 B The core is in B-Device mode.
15:12 Reserved To ensure compatibility with future devices, always write bits to 0. More information in 2.1 Conven-
tions.
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Bit Name Reset Access Description
11 DEVHNPEN 0 RW Device HNP Enabled device only
The application sets this bit when it successfully receives a SetFeature.SetHNPEnable command from the connected USB
host.
10 HSTSETHNPEN 0 RW Host Set HNP Enable host only
The application sets this bit when it has successfully enabled HNP (using the SetFeature.SetHNPEnable command) on the
connected device.
9 HNPREQ 0 RW HNP Request device only
The application sets this bit to initiate an HNP request to the connected USB host. The application can clear this bit by
writing a 0 when the Host Negotiation Success Status Change bit in the OTG Interrupt register (USB_GOTGINT.HSTNEG-
SUCSTSCHNG) is set. The core clears this bit when the HSTNEGSUCSTSCHNG bit is cleared.
8 HSTNEGSCS 0 R Host Negotiation Success device only
The core sets this bit when host negotiation is successful. The core clears this bit when the HNP Request (HNPREQ) bit in
this register is set.
7 AVALIDOVVAL 0 RW Avalid Override Value
This bit is used to set Override value for Avalid signal when USB_GOTGCTL.AVALIDOVEN is set.
6 AVALIDOVEN 0 RW AValid Override Enable
This bit is used to enable/disable the software to override the Avalid signal using the USB_GOTGCTL.AVALIDOVVAL.
When set Avalid received from the PHY is overridden with USB_GOTGCTL.AVALIDOVVAL.
5 BVALIDOVVAL 0 RW Bvalid Override Value
This bit is used to set Override value for Bvalid signal when USB_GOTGCTL.BVALIDOVEN is set.
4 BVALIDOVEN 0 RW BValid Override Enable
This bit is used to enable/disable the software to override the Bvalid signal using the USB_GOTGCTL.BVALIDOVVAL.
When set Bvalid received from the PHY is overridden with USB_GOTGCTL.BVALIDOVVAL.
3 VBVALIDOVVAL 0 RW VBUS Valid Override Value
This bit is used to set Override value for vbusvalid signal when USB_GOTGCTL.VBVALIDOVEN is set.
2 VBVALIDOVEN 0 RW VBUS-Valid Override Enable
This bit is used to enable/disable the software to override the vbusvalid signal using the USB_GOTGCTL.VBVALIDOVVAL.
When set, vbusvalid received from the PHY is overridden with USB_GOTGCTL.VBVALIDOVVAL.
1 SESREQ 0 RW Session Request device only
The application sets this bit to initiate a session request on the USB. The application can clear this bit by writing a 0 when
the Host Negotiation Success Status Change bit in the OTG Interrupt register (USB_GOTGINT.HSTNEGSUCSTSCHNG)
is set. The core clears this bit when the HSTNEGSUCSTSCHNG bit is cleared. The application must wait until the VBUS
discharges to 0.2 V, after the B-Session Valid bit in this register (USB_GOTGCTL.BSESVLD) is cleared. This discharge
time can be obtained from the datasheet.
0 SESREQSCS 0 R Session Request Success device only
The core sets this bit when a session request initiation is successful.
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15.6.9 USB_GOTGINT - OTG Interrupt Register
The application reads this register whenever there is an OTG interrupt and clears the bits in this register to clear the OTG interrupt.
Offset Bit Position
0x3C004
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
16
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
Reset
0
0
0
0
0
0
Access
RW1H
RW1H
RW1H
RW1H
RW1H
RW1H
Name
DBNCEDONE
ADEVTOUTCHG
HSTNEGDET
HSTNEGSUCSTSCHNG
SESREQSUCSTSCHNG
SESENDDET
Bit Name Reset Access Description
31:20 Reserved To ensure compatibility with future devices, always write bits to 0. More information in 2.1 Conven-
tions.
19 DBNCEDONE 0 RW1H Debounce Done host only
The core sets this bit when the debounce is completed after the device connect. The application can start driving USB reset
after seeing this interrupt. This bit is only valid when the HNP Capable or SRP Capable bit is set in the Core USB Configu-
ration register (USB_GUSBCFG.HNPCAP or USB_GUSBCFG.SRPCAP, respectively). This bit can be set only by the core
and the application should write 1 to clear it.
18 ADEVTOUTCHG 0 RW1H A-Device Timeout Change host and device
The core sets this bit to indicate that the A-device has timed out while waiting for the B-device to connect. This bit can be
set only by the core and the application should write 1 to clear it.
17 HSTNEGDET 0 RW1H Host Negotiation Detected host and device
The core sets this bit when it detects a host negotiation request on the USB. This bit can be set only by the core and the
application should write 1 to clear it.
16:10 Reserved To ensure compatibility with future devices, always write bits to 0. More information in 2.1 Conven-
tions.
9 HSTNEG-
SUCSTSCHNG
0 RW1H Host Negotiation Success Status Change host and device
The core sets this bit on the success or failure of a USB host negotiation request. The application must read the Host Nego-
tiation Success bit of the OTG Control and Status register (USB_GOTGCTL.HSTNEGSCS) to check for success or failure.
This bit can be set only by the core and the application should write 1 to clear it.
8 SESREQ-
SUCSTSCHNG
0 RW1H Session Request Success Status Change host and device
The core sets this bit on the success or failure of a session request. The application must read the Session Request Suc-
cess bit in the OTG Control and Status register (USB_GOTGCTL.SESREQSCS) to check for success or failure. This bit
can be set only by the core and the application should write 1 to clear it.
7:3 Reserved To ensure compatibility with future devices, always write bits to 0. More information in 2.1 Conven-
tions.
2 SESENDDET 0 RW1H Session End Detected host and device
The core sets this bit when VBUS is in the range 0.8V - 2.0V. This bit can be set only by the core and the application should
write 1 to clear it.
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15.6.10 USB_GAHBCFG - AHB Configuration Register
This register can be used to configure the core after power-on or a change in mode. This register mainly contains AHB system-related
configuration parameters. Do not change this register after the initial programming. The application must program this register before
starting any transactions on either the AHB or the USB.
Offset Bit Position
0x3C008
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
16
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
Reset
0
0
0
0
0
0x0
0
Access
RW
RW
RW
RW
RW
RW
RW
Name
NOTIALLDMAWRIT
REMMEMSUPP
PTXFEMPLVL
NPTXFEMPLVL
DMAEN
HBSTLEN
GLBLINTRMSK
Bit Name Reset Access Description
31:23 Reserved To ensure compatibility with future devices, always write bits to 0. More information in 2.1 Conven-
tions.
22 NOTIALLDMAWRIT 0 RW Notify All DMA Writes
This bit is programmed to enable the System DMA Done functionality for all the DMA write Transactions corresponding to
the Channel/Endpoint. This bit is valid only when USB_GAHBCFG.REMMEMSUPP is set to 1. When set, the core asserts
int_dma_req for all the DMA write transactions on the AHB interface along with int_dma_done, chep_last_transact and
chep_number signal informations. The core waits for sys_dma_done signal for all the DMA write transactions in order to
complete the transfer of a particular Channel/Endpoint. When cleared, the core asserts int_dma_req signal only for the last
transaction of DMA write transfer corresponding to a particular Channel/Endpoint. Similarly, the core waits for
sys_dma_done signal only for that transaction of DMA write to complete the transfer of a particular Channel/Endpoint.
21 REMMEMSUPP 0 RW Remote Memory Support
This bit is programmed to enable the functionality to wait for the system DMA Done Signal for the DMA Write Transfers.
When set, the int_dma_req output signal is asserted when HSOTG DMA starts write transfer to the external memory. When
the core is done with the Transfers it asserts int_dma_done signal to flag the completion of DMA writes from HSOTG. The
core then waits for sys_dma_done signal from the system to proceed further and complete the Data Transfer corresponding
to a particular Channel/Endpoint. When cleared, the int_dma_req and int_dma_done signals are not asserted and the core
proceeds with the assertion of the XferComp interrupt as soon as the DMA write transfer is done at the HSOTG Core Boun-
dary and it doesn't wait for the sys_dma_done signal to complete the DATA.
20:9 Reserved To ensure compatibility with future devices, always write bits to 0. More information in 2.1 Conven-
tions.
8 PTXFEMPLVL 0 RW Periodic TxFIFO Empty Level host only
Indicates when the Periodic TxFIFO Empty Interrupt bit in the Core Interrupt register (USB_GINTSTS.PTXFEMP) is trig-
gered. This bit is used only in Slave mode.
Value Mode Description
0 HALFEMPTY USB_GINTSTS.PTXFEMP interrupt indicates that the Periodic TxFIFO
is half empty.
1 EMPTY USB_GINTSTS.PTXFEMP interrupt indicates that the Periodic TxFIFO
is completely empty.
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Bit Name Reset Access Description
7 NPTXFEMPLVL 0 RW Non-Periodic TxFIFO Empty Level host and device
This bit is used only in Slave mode. In host mode this bit indicates when the Non-Periodic TxFIFO Empty Interrupt bit in the
Core Interrupt register (USB_GINTSTS.NPTXFEMP) is triggered. In device mode, this bit indicates when IN endpoint
Transmit FIFO empty interrupt (USB_DIEP0INT/USB_DIEPx_INT.TXFEMP) is triggered.
Value Mode Description
0 HALFEMPTY Host Mode: USB_GINTSTS.NPTXFEMP interrupt indicates that the
Non-Periodic TxFIFO is half empty.
Device Mode: USB_DIEP0INT/USB_DIEPx_INT.TXFEMP interrupt in-
dicates that the IN Endpoint TxFIFO is half empty.
1 EMPTY Host Mode: USB_GINTSTS.NPTXFEMP interrupt indicates that the
Non-Periodic TxFIFO is completely empty.
Device Mode: USB_DIEP0INT/USB_DIEPx_INT.TXFEMP interrupt in-
dicates that the IN Endpoint TxFIFO is completely empty.
6 Reserved To ensure compatibility with future devices, always write bits to 0. More information in 2.1 Conven-
tions.
5 DMAEN 0 RW DMA Enable host and device
When set to 0 the core operates in Slave mode. When set to 1 the core operates in a DMA mode.
4:1 HBSTLEN 0x0 RW Burst Length/Type host and device
This field is used in DMA mode.
Value Mode Description
0 SINGLE Single transfer.
1 INCR Incrementing burst of unspecified length.
3 INCR4 4-beat incrementing burst.
5 INCR8 8-beat incrementing burst.
7 INCR16 16-beat incrementing burst.
0 GLBLINTRMSK 0 RW Global Interrupt Mask host and device
The application uses this bit to mask or unmask the interrupt line assertion to itself. Irrespective of this bit's setting, the
interrupt status registers are updated by the core. Set to unmask.
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15.6.11 USB_GUSBCFG - USB Configuration Register
This register can be used to configure the core after power-on or a changing to Host mode or Device mode. It contains USB and USB-
PHY related configuration parameters. The application must program this register before starting any transactions on either the AHB or
the USB. Do not make changes to this register after the initial programming.
Offset Bit Position
0x3C00
C
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
16
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
Reset
0
0
0
0
0
0x5
0
0
0
0x0
Access
W1
RW
RW
RW
RW
RW
RW
RW
RW
RW
Name
CORRUPTTXPKT
FORCEDEVMODE
FORCEHSTMODE
TXENDDELAY
TERMSELDLPULSE
USBTRDTIM
HNPCAP
SRPCAP
FSINTF
TOUTCAL
Bit Name Reset Access Description
31 CORRUPTTXPKT 0 W1 Corrupt Tx packet host and device
This bit is for debug purposes only. Never Set this bit to 1. The application should always write 0 to this bit.
30 FORCEDEVMODE 0 RW Force Device Mode host and device
Writing a 1 to this bit forces the core to device mode irrespective of the state of the ID pin. After setting the force bit, the
application must wait at least 25 ms before the change to take effect.
29 FORCEHSTMODE 0 RW Force Host Mode host and device
Writing a 1 to this bit forces the core to host mode irrespective of the state of the ID pin. After setting the force bit, the
application must wait at least 65 ms before the change to take effect.
28 TXENDDELAY 0 RW Tx End Delay device only
Writing 1 to this bit enables the core to follow the TxEndDelay timings as per UTMI+ specification 1.05 section 4.1.5 for
opmode signal during remote wakeup.
27:23 Reserved To ensure compatibility with future devices, always write bits to 0. More information in 2.1 Conven-
tions.
22 TERMSELDLPULSE 0 RW TermSel DLine Pulsing Selection device only
This bit selects utmi_termselect to drive data line pulse during SRP.
Value Mode Description
0 TXVALID Data line pulsing using utmi_txvalid.
1 TERMSEL Data line pulsing using utmi_termsel.
21:14 Reserved To ensure compatibility with future devices, always write bits to 0. More information in 2.1 Conven-
tions.
13:10 USBTRDTIM 0x5 RW USB Turnaround Time device only
Sets the turnaround time in PHY clocks. Specifies the response time For a MAC request to the Packet FIFO Controller
(PFC) to fetch data from the DFIFO (SPRAM). Always write this field to 5.
9 HNPCAP 0 RW HNP-Capable host and device
The application uses this bit to control the core's HNP capabilities. Set to enable HNP capability.
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Bit Name Reset Access Description
8 SRPCAP 0 RW SRP-Capable host and device
The application uses this bit to control the core's SRP capabilities. If the core operates as a non-SRP-capable B-device, it
cannot request the connected A-device (host) to activate VBUS and start a session. Set to enable SRP capability.
7:6 Reserved To ensure compatibility with future devices, always write bits to 0. More information in 2.1 Conven-
tions.
5 FSINTF 0 RW Full-Speed Serial Interface Select host and device
Always write this bit to 0.
4:3 Reserved To ensure compatibility with future devices, always write bits to 0. More information in 2.1 Conven-
tions.
2:0 TOUTCAL 0x0 RW Timeout Calibration host and device
Always write this field to 0.
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15.6.12 USB_GRSTCTL - Reset Register
The application uses this register to reset various hardware features inside the core.
Offset Bit Position
0x3C010
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
16
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
Reset
1
0
0x00
0
0
0
0
Access
R
R
RW
RW1H
RW1H
RW1H
RW1H
Name
AHBIDLE
DMAREQ
TXFNUM
TXFFLSH
RXFFLSH
FRMCNTRRST
CSFTRST
Bit Name Reset Access Description
31 AHBIDLE 1 R AHB Master Idle host and device
Indicates that the AHB Master State Machine is in the IDLE condition.
30 DMAREQ 0 R DMA Request Signal host and device
Indicates that the DMA request is in progress. Used for debug.
29:11 Reserved To ensure compatibility with future devices, always write bits to 0. More information in 2.1 Conven-
tions.
10:6 TXFNUM 0x00 RW TxFIFO Number host and device
This is the FIFO number that must be flushed using the TxFIFO Flush bit. This field must not be changed until the core
clears the TxFIFO Flush bit.
Value Mode Description
0 F0 Host mode: Non-periodic TxFIFO flush.
Device: Tx FIFO 0 flush
1 F1 Host mode: Periodic TxFIFO flush.
Device: TXFIFO 1 flush.
2 F2 Device mode: TXFIFO 2 flush.
3 F3 Device mode: TXFIFO 3 flush.
4 F4 Device mode: TXFIFO 4 flush.
5 F5 Device mode: TXFIFO 5 flush.
6 F6 Device mode: TXFIFO 6 flush.
16 FALL Flush all the transmit FIFOs in device or host mode.
5 TXFFLSH 0 RW1H TxFIFO Flush host and device
This bit selectively flushes a single or all transmit FIFOs, but cannot do so if the core is in the midst of a transaction. The
application must write this bit only after checking that the core is neither writing to the TxFIFO nor reading from the TxFIFO.
NAK Effective Interrupt ensures the core is not reading from the FIFO. USB_GRSTCTL.AHBIDLE ensures the core is not
writing anything to the FIFO. Flushing is normally recommended when FIFOs are reconfigured. FIFO flushing is also rec-
ommended during device endpoint disable. The application must wait until the core clears this bit before performing any
operations. This bit takes eight clocks to clear.
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Bit Name Reset Access Description
4 RXFFLSH 0 RW1H RxFIFO Flush host and device
The application can flush the entire RxFIFO using this bit, but must first ensure that the core is not in the middle of a trans-
action. The application must only write to this bit after checking that the core is neither reading from the RxFIFO nor writing
to the RxFIFO. The application must wait until the bit is cleared before performing any other operations. This bit requires 8
clocks to clear.
3 Reserved To ensure compatibility with future devices, always write bits to 0. More information in 2.1 Conven-
tions.
2 FRMCNTRRST 0 RW1H Host Frame Counter Reset host only
The application writes this bit to reset the frame number counter inside the core. When the frame counter is reset, the sub-
sequent SOF sent out by the core has a frame number of 0. When application writes 1 to the bit, it might not be able to read
back the value as it will get cleared by the core in a few clock cycles.
1 Reserved To ensure compatibility with future devices, always write bits to 0. More information in 2.1 Conven-
tions.
0 CSFTRST 0 RW1H Core Soft Reset host and device
Resets the core by clearing the interrupts and all the CSR registers except the following register bits:
USB_PCGCCTL.RSTPDWNMODULE, USB_PCGCCTL.GATEHCLK, USB_PCGCCTL.PWRCLMP,
USB_GUSBCFG.FSINTF, USB_HCFG.FSLSPCLKSEL, USB_DCFG.DEVSPD.
All module state machines (except the AHB Slave Unit) are reset to the IDLE state, and all the transmit FIFOs and the
receive FIFO are flushed. Any transactions on the AHB Master are terminated as soon as possible, after gracefully com-
pleting the last data phase of an AHB transfer. Any transactions on the USB are terminated immediately. The application
can write to this bit any time it wants to reset the core. This is a self-clearing bit and the core clears this bit after all the
necessary logic is reset in the core, which can take several clocks, depending on the current state of the core. Once this bit
is cleared software must wait at least 3 clock cycles before doing any access to the core. Software must also must check
that bit 31 of this register is 1 (AHB Master is IDLE) before starting any operation.
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15.6.13 USB_GINTSTS - Interrupt Register
This register interrupts the application for system-level events in the current mode (Device mode or Host mode). Some of the bits in this
register are valid only in Host mode, while others are valid in Device mode only. This register also indicates the current mode. To clear
the interrupt status bits of type RW1H, the application must write 1 into the bit.
The FIFO status interrupts are read only; once software reads from or writes to the FIFO while servicing these interrupts, FIFO interrupt
conditions are cleared automatically.
The application must clear the USB_GINTSTS register at initialization before unmasking the interrupt bit to avoid any interrupts gener-
ated prior to initialization.
Offset Bit Position
0x3C014
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
16
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
Reset
0
0
0
1
1
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
1
0
0
0
0
0
Access
RW1H
RW1H
RW1H
RW1H
R
R
R
RW1H
RW1H
RW1H
RW1H
R
R
RW
RW1H
RW1H
RW1H
RW1H
RW1H
R
R
R
R
RW1H
R
RW1H
R
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Offset Bit Position
Name
WKUPINT
SESSREQINT
DISCONNINT
CONIDSTSCHNG
PTXFEMP
HCHINT
PRTINT
RESETDET
FETSUSP
INCOMPLP
INCOMPISOIN
OEPINT
IEPINT
EOPF
ISOOUTDROP
ENUMDONE
USBRST
USBSUSP
ERLYSUSP
GOUTNAKEFF
GINNAKEFF
NPTXFEMP
RXFLVL
SOF
OTGINT
MODEMIS
CURMOD
Bit Name Reset Access Description
31 WKUPINT 0 RW1H Resume/Remote Wakeup Detected Interrupt host and device
Wakeup Interrupt during Suspend state. In Device mode this interrupt is asserted only when Host Initiated Resume is de-
tected on USB. In Host mode this interrupt is asserted only when Device Initiated Remote Wakeup is detected on USB.
This bit can be set only by the core and the application should write 1 to clear.
30 SESSREQINT 0 RW1H Session Request/New Session Detected Interrupt host and device
In Host mode, this interrupt is asserted when a session request is detected from the device. In Device mode, this interrupt
is asserted when the VBUS voltage reaches the session-valid level. This bit can be set only by the core and the application
should write 1 to clear.
29 DISCONNINT 0 RW1H Disconnect Detected Interrupt host only
Asserted when a device disconnect is detected. This bit can be set only by the core and the application should write 1 to
clear it.
28 CONIDSTSCHNG 1 RW1H Connector ID Status Change host and device
The core sets this bit when there is a change in connector ID status. This bit can be set only by the core and the application
should write 1 to clear it.
27 Reserved To ensure compatibility with future devices, always write bits to 0. More information in 2.1 Conven-
tions.
26 PTXFEMP 1 R Periodic TxFIFO Empty host only
This interrupt is asserted when the Periodic Transmit FIFO is either half or completely empty and there is space for at least
one entry to be written in the Periodic Request Queue. The half or completely empty status is determined by the Periodic
TxFIFO Empty Level bit in the Core AHB Configuration register (USB_GAHBCFG.PTXFEMPLVL).
25 HCHINT 0 R Host Channels Interrupt host only
The core sets this bit to indicate that an interrupt is pending on one of the channels of the core (in Host mode). The applica-
tion must read the Host All Channels Interrupt (USB_HAINT) register to determine the exact number of the channel on
which the interrupt occurred, and then read the corresponding Host Channel-x Interrupt (USB_HCx_INT) register to deter-
mine the exact cause of the interrupt. The application must clear the appropriate status bit in the USB_HCx_INT register to
clear this bit.
24 PRTINT 0 R Host Port Interrupt host only
The core sets this bit to indicate a change in port status in Host mode. The application must read the Host Port Control and
Status (USB_HPRT) register to determine the exact event that caused this interrupt. The application must clear the appro-
priate status bit in the Host Port Control and Status register to clear this bit.
23 RESETDET 0 RW1H Reset detected Interrupt device only
In Device mode, this interrupt is asserted when a reset is detected on the USB in EM2 when the device is in Suspend.
In Host mode, this interrupt is not asserted.
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Bit Name Reset Access Description
22 FETSUSP 0 RW1H Data Fetch Suspended device only
This interrupt is valid only in DMA mode. This interrupt indicates that the core has stopped fetching data for IN endpoints
due to the unavailability of TxFIFO space or Request Queue space. This interrupt is used by the application for an endpoint
mismatch algorithm.
For example, after detecting an endpoint mismatch, the application: Sets a Global non-periodic IN NAK handshake, Disa-
bles In endpoints, Flushes the FIFO, Determines the token sequence from the IN Token Sequence, Re-enables the end-
points, Clears the Global non-periodic IN NAK handshake.
If the Global non-periodic IN NAK is cleared, the core has not yet fetched data for the IN endpoint, and the IN token is
received: the core generates an IN Token Received when FIFO Empty interrupt. The OTG then sends the host a NAK re-
sponse. To avoid this scenario, the application can check the USB_GINTSTS.FETSUSP interrupt, which ensures that the
FIFO is full before clearing a Global NAK handshake. Alternatively, the application can mask the IN Token Received when
FIFO Empty interrupt when clearing a Global IN NAK handshake.
21 INCOMPLP 0 RW1H Incomplete Periodic Transfer host and device
In Host mode, the core sets this interrupt bit when there are incomplete periodic transactions still pending which are sched-
uled for the current frame. In Device mode, the core sets this interrupt to indicate that there is at least one isochronous OUT
endpoint on which the transfer is not completed in the current frame. This bit can be set only by the core and the application
should write 1 to clear it.
20 INCOMPISOIN 0 RW1H Incomplete Isochronous IN Transfer device only
The core sets this interrupt to indicate that there is at least one isochronous IN endpoint on which the transfer is not com-
pleted in the current frame.
19 OEPINT 0 R OUT Endpoints Interrupt device only
The core sets this bit to indicate that an interrupt is pending on one of the OUT endpoints of the core (in Device mode). The
application must read the Device All Endpoints Interrupt (USB_DAINT) register to determine the exact number of the OUT
endpoint on which the interrupt occurred, and then read the corresponding Device OUT Endpoint-x Interrupt
(USB_DOEP0INT/USB_DOEPx_INT) register to determine the exact cause of the interrupt. The application must clear the
appropriate status bit in the corresponding USB_DOEP0INT/USB_DOEPx_INT register to clear this bit.
18 IEPINT 0 R IN Endpoints Interrupt device only
The core sets this bit to indicate that an interrupt is pending on one of the IN endpoints of the core (in Device mode). The
application must read the Device All Endpoints Interrupt (USB_DAINT) register to determine the exact number of the IN
endpoint on Device IN Endpoint-x Interrupt (USB_DIEP0INT/USB_DIEPx_INT) register to determine the exact cause of the
interrupt. The application must clear the appropriate status bit in the corresponding USB_DIEP0INT/USB_DIEPx_INT regis-
ter to clear this bit.
17:16 Reserved To ensure compatibility with future devices, always write bits to 0. More information in 2.1 Conven-
tions.
15 EOPF 0 RW End of Periodic Frame Interrupt
Indicates that the period specified in the Periodic Frame Interval field of the Device Configuration register (DCFG_PER-
FRINT) has been reached in the current microframe.
14 ISOOUTDROP 0 RW1H Isochronous OUT Packet Dropped Interrupt device only
The core sets this bit when it fails to write an isochronous OUT packet into the RxFIFO because the RxFIFO does not have
enough space to accommodate a maximum packet size packet for the isochronous OUT endpoint.
13 ENUMDONE 0 RW1H Enumeration Done device only
The core sets this bit to indicate that speed enumeration is complete. The application must read the Device Status
(USB_DSTS) register to obtain the enumerated speed.
12 USBRST 0 RW1H USB Reset device only
The core sets this bit to indicate that a reset is detected on the USB.
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Bit Name Reset Access Description
11 USBSUSP 0 RW1H USB Suspend device only
The core sets this bit to indicate that a suspend was detected on the USB. The core enters the Suspended state when
there is no activity on the bus for an extended period of time.
10 ERLYSUSP 0 RW1H Early Suspend device only
The core sets this bit to indicate that an Idle state has been detected on the USB for 3 ms.
9:8 Reserved To ensure compatibility with future devices, always write bits to 0. More information in 2.1 Conven-
tions.
7 GOUTNAKEFF 0 R Global OUT NAK Effective device only
Indicates that the Set Global OUT NAK bit in the Device Control register (USB_DCTL.SGOUTNAK), set by the application,
has taken effect in the core. This bit can be cleared by writing the Clear Global OUT NAK bit in the Device Control register
(USB_DCTL.CGOUTNAK).
6 GINNAKEFF 0 R Global IN Non-periodic NAK Effective device only
Indicates that the Set Global Non-periodic IN NAK bit in the Device Control register (USB_DCTL.SGNPINNAK), set by the
application, has taken effect in the core. That is, the core has sampled the Global IN NAK bit set by the application. This bit
can be cleared by clearing the Clear Global Non-periodic IN NAK bit in the Device Control register (USB_DCTL.CGNPIN-
NAK). This interrupt does not necessarily mean that a NAK handshake is sent out on the USB. The STALL bit takes prece-
dence over the NAK bit.
5 NPTXFEMP 1 R Non-Periodic TxFIFO Empty host only
This interrupt is asserted when the Non-periodic TxFIFO is either half or completely empty, and there is space for at least
one entry to be written to the Non-periodic Transmit Request Queue. The half or completely empty status is determined by
the Non-periodic TxFIFO Empty Level bit in the Core AHB Configuration register (USB_GAHBCFG.NPTXFEMPLVL).
4 RXFLVL 0 R RxFIFO Non-Empty host and device
Indicates that there is at least one packet pending to be read from the RxFIFO.
3 SOF 0 RW1H Start of Frame host and device
In Host mode, the core sets this bit to indicate that an SOF (FS) or Keep-Alive (LS) is transmitted on the USB. The applica-
tion must write a 1 to this bit to clear the interrupt.
In Device mode, in the core sets this bit to indicate that an SOF token has been received on the USB. The application can
read the Device Status register to get the current frame number. This interrupt is seen only when the core is operating at
full-speed (FS). This bit can be set only by the core and the application should write 1 to clear it.
2 OTGINT 0 R OTG Interrupt host and device
The core sets this bit to indicate an OTG protocol event. The application must read the OTG Interrupt Status (USB_GOT-
GINT) register to determine the exact event that caused this interrupt. The application must clear the appropriate status bit
in the USB_GOTGINT register to clear this bit.
1 MODEMIS 0 RW1H Mode Mismatch Interrupt host and device
The core sets this bit when the application is trying to access a Host mode register, when the core is operating in Device
mode or when the application accesses a Device mode register, when the core is operating in Host mode. The register
access is ignored by the core internally and does not affect the operation of the core. This bit can be set only by the core
and the application should write 1 to clear it.
0 CURMOD 0 R Current Mode of Operation host and device
Indicates the current mode.
Value Mode Description
0 DEVICE Device mode.
1 HOST Host mode.
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15.6.14 USB_GINTMSK - Interrupt Mask Register
This register works with the Interrupt Register (USB_GINTSTS) to interrupt the application. When an interrupt bit is masked (bit is 0),
the interrupt associated with that bit is not generated. However, the USB_GINTSTS register bit corresponding to that interrupt is still
set.
Offset Bit Position
0x3C018
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
16
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
Reset
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
Access
RW
RW
RW
RW
RW
RW
RW
RW
RW
RW
RW
RW
RW
RW
RW
RW
RW
RW
RW
RW
RW
RW
RW
RW
RW
RW
Name
WKUPINTMSK
SESSREQINTMSK
DISCONNINTMSK
CONIDSTSCHNGMSK
PTXFEMPMSK
HCHINTMSK
PRTINTMSK
RESETDETMSK
FETSUSPMSK
INCOMPLPMSK
INCOMPISOINMSK
OEPINTMSK
IEPINTMSK
EOPFMSK
ISOOUTDROPMSK
ENUMDONEMSK
USBRSTMSK
USBSUSPMSK
ERLYSUSPMSK
GOUTNAKEFFMSK
GINNAKEFFMSK
NPTXFEMPMSK
RXFLVLMSK
SOFMSK
OTGINTMSK
MODEMISMSK
Bit Name Reset Access Description
31 WKUPINTMSK 0 RW Resume/Remote Wakeup Detected Interrupt Mask host and device
Set to 1 to unmask WKUPINT interrupt.
30 SESSREQINTMSK 0 RW Session Request/New Session Detected Interrupt Mask host and
device
Set to 1 to unmask SESSREQINT interrupt.
29 DISCONNINTMSK 0 RW Disconnect Detected Interrupt Mask host and device
Set to 1 to unmask DISCONNINT interrupt.
28 CON-
IDSTSCHNGMSK
0 RW Connector ID Status Change Mask host and device
Set to 1 to unmask CONIDSTSCHNG interrupt.
27 Reserved To ensure compatibility with future devices, always write bits to 0. More information in 2.1 Conven-
tions.
26 PTXFEMPMSK 0 RW Periodic TxFIFO Empty Mask host only
Set to 1 to unmask PTXFEMP interrupt.
25 HCHINTMSK 0 RW Host Channels Interrupt Mask host only
Set to 1 to unmask HCHINT interrupt.
24 PRTINTMSK 0 RW Host Port Interrupt Mask host only
Set to 1 to unmask PRTINT interrupt.
23 RESETDETMSK 0 RW Reset detected Interrupt Mask device only
Set to 1 to unmask RESETDET interrupt.
22 FETSUSPMSK 0 RW Data Fetch Suspended Mask device only
Set to 1 to unmask FETSUSP interrupt.
21 INCOMPLPMSK 0 RW Incomplete Periodic Transfer Mask host and device
Set to 1 to unmask INCOMPLP interrupt.
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Bit Name Reset Access Description
20 INCOMPISOINMSK 0 RW Incomplete Isochronous IN Transfer Mask device only
Set to 1 to unmask INCOMPISOIN interrupt.
19 OEPINTMSK 0 RW OUT Endpoints Interrupt Mask device only
Set to 1 to unmask OEPINT interrupt.
18 IEPINTMSK 0 RW IN Endpoints Interrupt Mask device only
Set to 1 to unmask IEPINT interrupt.
17:16 Reserved To ensure compatibility with future devices, always write bits to 0. More information in 2.1 Conven-
tions.
15 EOPFMSK 0 RW End of Periodic Frame Interrupt Mask device only
Set to 1 to unmask EOPF interrupt.
14 ISOOUTDROPMSK 0 RW Isochronous OUT Packet Dropped Interrupt Mask device only
Set to 1 to unmask ISOOUTDROP interrupt.
13 ENUMDONEMSK 0 RW Enumeration Done Mask device only
Set to 1 to unmask ENUMDONE interrupt.
12 USBRSTMSK 0 RW USB Reset Mask device only
Set to 1 to unmask USBRST interrupt.
11 USBSUSPMSK 0 RW USB Suspend Mask device only
Set to 1 to unmask USBSUSP interrupt.
10 ERLYSUSPMSK 0 RW Early Suspend Mask device only
Set to 1 to unmask ERLYSUSP interrupt.
9:8 Reserved To ensure compatibility with future devices, always write bits to 0. More information in 2.1 Conven-
tions.
7 GOUTNAKEFFMSK 0 RW Global OUT NAK Effective Mask device only
Set to 1 to unmask GOUTNAKEFF interrupt.
6 GINNAKEFFMSK 0 RW Global Non-periodic IN NAK Effective Mask device only
Set to 1 to unmask GINNAKEFF interrupt.
5 NPTXFEMPMSK 0 RW Non-Periodic TxFIFO Empty Mask host only
Set to 1 to unmask NPTXFEMP interrupt.
4 RXFLVLMSK 0 RW Receive FIFO Non-Empty Mask host and device
Set to 1 to unmask RXFLVL interrupt.
3 SOFMSK 0 RW Start of Frame Mask host and device
Set to 1 to unmask SOF interrupt.
2 OTGINTMSK 0 RW OTG Interrupt Mask host and device
Set to 1 to unmask OTGINT interrupt.
1 MODEMISMSK 0 RW Mode Mismatch Interrupt Mask host and device
Set to 1 to unmask MODEMIS interrupt.
0 Reserved To ensure compatibility with future devices, always write bits to 0. More information in 2.1 Conven-
tions.
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15.6.15 USB_GRXSTSR - Receive Status Debug Read Register
A read to the Receive Status Debug Read register returns the contents of the top of the Receive FIFO. The receive status contents
must be interpreted differently in Host and Device modes. The core ignores the receive status pop/read when the receive FIFO is empty
and returns a value of 0x00000000. The application must only pop the Receive Status FIFO when the Receive FIFO Non-Empty bit of
the Core Interrupt register (USB_GINTSTS.RXFLVL) is asserted.
Offset Bit Position
0x3C01
C
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
16
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
Reset
0x0
0x0
0x0
0x000
0x0
Access
R
R
R
R
R
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Offset Bit Position
Name
FN
PKTSTS
DPID
BCNT
CHEPNUM
Bit Name Reset Access Description
31:25 Reserved To ensure compatibility with future devices, always write bits to 0. More information in 2.1 Conven-
tions.
24:21 FN 0x0 R Frame Number device only
This is the least significant 4 bits of the Frame number in which the packet is received on the USB.
20:17 PKTSTS 0x0 R Packet Status (host or device)
Indicates the status of the received packet.
Value Mode Description
1 GOUTNAK Device mode: Global OUT NAK (triggers an interrupt).
2 PKTRCV Host mode: IN data packet received.
Device mode: OUT data packet received.
3 XFERCOMPL Host mode: IN transfer completed (triggers an interrupt).
Device mode: OUT transfer completed (triggers an interrupt).
4 SETUPCOMPL Device mode: SETUP transaction completed (triggers an interrupt).
5 TGLERR Host mode: Data toggle error (triggers an interrupt).
6 SETUPRCV Device mode: SETUP data packet received.
7 CHLT Host mode: Channel halted (triggers an interrupt).
16:15 DPID 0x0 R Data PID (host or device)
Host mode: Indicates the Data PID of the received packet. Device mode: Indicates the Data PID of the received OUT data
packet.
Value Mode Description
0 DATA0 DATA0 PID.
1 DATA1 DATA1 PID.
2 DATA2 DATA2 PID.
3 MDATA MDATA PID.
14:4 BCNT 0x000 R Byte Count (host or device)
Host mode: Indicates the byte count of the received IN data packet.
Device mode: Indicates the byte count of the received data packet.
3:0 CHEPNUM 0x0 R Channel Number host only / Endpoint Number device only
Host mode: Indicates the channel number to which the current received packet belongs.
Device mode: Indicates the endpoint number to which the current received packet belongs.
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15.6.16 USB_GRXSTSP - Receive Status Read and Pop Register
A read to the Receive Status Read and Pop register returns the contents of the top of the Receive FIFO and pops the top data entry out
of the RxFIFO. The receive status contents must be interpreted differently in Host and Device modes. The core ignores the receive
status pop/read when the receive FIFO is empty and returns a value of 0x00000000. The application must only pop the Receive Status
FIFO when the Receive FIFO Non-Empty bit of the Core Interrupt register (USB_GINTSTS.RXFLVL) is asserted.
Offset Bit Position
0x3C020
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
16
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
Reset
0x0
0x0
0x0
0x000
0x0
Access
R
R
R
R
R
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Offset Bit Position
Name
FN
PKTSTS
DPID
BCNT
CHEPNUM
Bit Name Reset Access Description
31:25 Reserved To ensure compatibility with future devices, always write bits to 0. More information in 2.1 Conven-
tions.
24:21 FN 0x0 R Frame Number device only
This is the least significant 4 bits of the Frame number in which the packet is received on the USB.
20:17 PKTSTS 0x0 R Packet Status (host or device)
Indicates the status of the received packet.
Value Mode Description
1 GOUTNAK Device mode: Global OUT NAK (triggers an interrupt).
2 PKTRCV Host mode: IN data packet received.
Device mode: OUT data packet received.
3 XFERCOMPL Host mode: IN transfer completed (triggers an interrupt).
Device mode: OUT transfer completed (triggers an interrupt).
4 SETUPCOMPL Device mode: SETUP transaction completed (triggers an interrupt).
5 TGLERR Host mode: Data toggle error (triggers an interrupt).
6 SETUPRCV Device mode: SETUP data packet received.
7 CHLT Host mode: Channel halted (triggers an interrupt).
16:15 DPID 0x0 R Data PID (host or device)
Host mode: Indicates the Data PID of the received packet.
Device mode: Indicates the Data PID of the received OUT data packet.
Value Mode Description
0 DATA0 DATA0 PID.
1 DATA1 DATA1 PID.
2 DATA2 DATA2 PID.
3 MDATA MDATA PID.
14:4 BCNT 0x000 R Byte Count (host or device)
Host mode: Indicates the byte count of the received IN data packet.
Device mode: Indicates the byte count of the received data packet.
3:0 CHEPNUM 0x0 R Channel Number host only / Endpoint Number device only
Host mode: Indicates the channel number to which the current received packet belongs.
Device mode: Indicates the endpoint number to which the current received packet belongs.
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15.6.17 USB_GRXFSIZ - Receive FIFO Size Register
The application can program the RAM size that must be allocated to the RxFIFO.
Offset Bit Position
0x3C024
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
16
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
Reset
0x200
Access
RW
Name
RXFDEP
Bit Name Reset Access Description
31:10 Reserved To ensure compatibility with future devices, always write bits to 0. More information in 2.1 Conven-
tions.
9:0 RXFDEP 0x200 RW RxFIFO Depth
This value is in terms of 32-bit words. Minimum value is 16. Maximum value is 512.
15.6.18 USB_GNPTXFSIZ - Non-periodic Transmit FIFO Size Register
The application can program the RAM size and the memory start address for the Non-periodic TxFIFO.
Offset Bit Position
0x3C028
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
16
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
Reset
0x0200
0x200
Access
RW
RW
Name
NPTXFINEPTXF0DEP
NPTXFSTADDR
Bit Name Reset Access Description
31:16 NPTXFI-
NEPTXF0DEP
0x0200 RW Non-periodic TxFIFO Depth host only / IN Endpoint TxFIFO 0
Depth device only
This value is in terms of 32-bit words. Minimum value is 16. Maximum value is 512.
15:10 Reserved To ensure compatibility with future devices, always write bits to 0. More information in 2.1 Conven-
tions.
9:0 NPTXFSTADDR 0x200 RW Non-periodic Transmit RAM Start Address host only
This field contains the memory start address for Non-periodic Transmit FIFO RAM. Programmed values must not exceed
the reset value.
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15.6.19 USB_GNPTXSTS - Non-periodic Transmit FIFO/Queue Status Register
This register is used in host mode only. This read-only register contains the free space information for the Non-periodic TxFIFO and the
Nonperiodic Transmit Request Queue.
Offset Bit Position
0x3C02
C
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
16
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
Reset
0x00
0x08
0x0200
Access
R
R
R
Name
NPTXQTOP
NPTXQSPCAVAIL
NPTXFSPCAVAIL
Bit Name Reset Access Description
31 Reserved To ensure compatibility with future devices, always write bits to 0. More information in 2.1 Conven-
tions.
30:24 NPTXQTOP 0x00 R Top of the Non-periodic Transmit Request Queue
Entry in the Non-periodic Tx Request Queue that is currently being processed by the MAC.
Bits [6:3]: Channel/endpoint number.
Bits [2:1]: 00: IN/OUT token, 01: Zero-length transmit packet (device IN/host OUT), 10: Unused, 11: Channel halt com-
mand.
Bit [0]: Terminate (last Entry for selected channel/endpoint).
23:16 NPTXQSPCAVAIL 0x08 R Non-periodic Transmit Request Queue Space Available
Indicates the amount of free space (locations) available in the Non-periodic Transmit Request Queue. This queue holds
both IN and OUT requests in Host mode. Device mode has only IN requests.
15:0 NPTXFSPCAVAIL 0x0200 R Non-periodic TxFIFO Space Available
Indicates the amount of free space available in the Non-periodic TxFIFO. Values are in terms of 32-bit words.
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15.6.20 USB_GDFIFOCFG - Global DFIFO Configuration Register
Offset Bit Position
0x3C05
C
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
16
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
Reset
0x01F2
0x0200
Access
RW
RW
Name
EPINFOBASEADDR
GDFIFOCFG
Bit Name Reset Access Description
31:16 EPINFOBASEADDR 0x01F2 RW Endpoint Info Base Address
This field provides the start address of the EP info controller.
15:0 GDFIFOCFG 0x0200 RW DFIFO Config
This field is for dynamic programming of the DFIFO Size. This value takes effect only when the application programs a non
zero value to this register. The core does not have any corrective logic if the FIFO sizes are programmed incorrectly.
15.6.21 USB_HPTXFSIZ - Host Periodic Transmit FIFO Size Register
This register holds the size and the memory start address of the Periodic TxFIFO.
Offset Bit Position
0x3C100
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
16
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
Reset
0x200
0x400
Access
RW
RW
Name
PTXFSIZE
PTXFSTADDR
Bit Name Reset Access Description
31:26 Reserved To ensure compatibility with future devices, always write bits to 0. More information in 2.1 Conven-
tions.
25:16 PTXFSIZE 0x200 RW Host Periodic TxFIFO Depth
This value is in terms of 32-bit words. Minimum value is 16. Maximum value is 512.
15:11 Reserved To ensure compatibility with future devices, always write bits to 0. More information in 2.1 Conven-
tions.
10:0 PTXFSTADDR 0x400 RW Host Periodic TxFIFO Start Address
This field contains the memory start address for Host Periodic TxFIFO.
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15.6.22 USB_DIEPTXF1 - Device IN Endpoint Transmit FIFO 1 Size Register
This register holds the size and memory start address of IN endpoint TxFIFO 1 in Device mode. For IN endpoint FIFO 0 use
USB_GNPTXFSIZ register for programming the size and memory start address.
Offset Bit Position
0x3C104
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
16
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
Reset
0x200
0x400
Access
RW
RW
Name
INEPNTXFDEP
INEPNTXFSTADDR
Bit Name Reset Access Description
31:26 Reserved To ensure compatibility with future devices, always write bits to 0. More information in 2.1 Conven-
tions.
25:16 INEPNTXFDEP 0x200 RW IN Endpoint TxFIFO Depth
This value is in terms of 32-bit words. Minimum value is 16. Maximum value is 512.
15:11 Reserved To ensure compatibility with future devices, always write bits to 0. More information in 2.1 Conven-
tions.
10:0 INEPNTXFSTADDR 0x400 RW IN Endpoint FIFO 1 Transmit RAM Start Address
This field contains the memory start address for IN endpoint Transmit FIFO 1.
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15.6.23 USB_DIEPTXF2 - Device IN Endpoint Transmit FIFO 2 Size Register
This register holds the size and memory start address of IN endpoint TxFIFO 2 in Device mode. For IN endpoint FIFO 0 use
USB_GNPTXFSIZ register for programming the size and memory start address.
Offset Bit Position
0x3C108
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
16
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
Reset
0x200
0x600
Access
RW
RW
Name
INEPNTXFDEP
INEPNTXFSTADDR
Bit Name Reset Access Description
31:26 Reserved To ensure compatibility with future devices, always write bits to 0. More information in 2.1 Conven-
tions.
25:16 INEPNTXFDEP 0x200 RW IN Endpoint TxFIFO Depth
This value is in terms of 32-bit words. Minimum value is 16. Maximum value is 512.
15:11 Reserved To ensure compatibility with future devices, always write bits to 0. More information in 2.1 Conven-
tions.
10:0 INEPNTXFSTADDR 0x600 RW IN Endpoint FIFO 2 Transmit RAM Start Address
This field contains the memory start address for IN endpoint Transmit FIFO 2.
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15.6.24 USB_DIEPTXF3 - Device IN Endpoint Transmit FIFO 3 Size Register
This register holds the size and memory start address of IN endpoint TxFIFO 3 in Device mode. For IN endpoint FIFO 0 use
USB_GNPTXFSIZ register for programming the size and memory start address.
Offset Bit Position
0x3C10
C
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
16
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
Reset
0x200
0x800
Access
RW
RW
Name
INEPNTXFDEP
INEPNTXFSTADDR
Bit Name Reset Access Description
31:26 Reserved To ensure compatibility with future devices, always write bits to 0. More information in 2.1 Conven-
tions.
25:16 INEPNTXFDEP 0x200 RW IN Endpoint TxFIFO Depth
This value is in terms of 32-bit words. Minimum value is 16. Maximum value is 512.
15:12 Reserved To ensure compatibility with future devices, always write bits to 0. More information in 2.1 Conven-
tions.
11:0 INEPNTXFSTADDR 0x800 RW IN Endpoint FIFO 3 Transmit RAM Start Address
This field contains the memory start address for IN endpoint Transmit FIFO 3.
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15.6.25 USB_DIEPTXF4 - Device IN Endpoint Transmit FIFO 4 Size Register
This register holds the size and memory start address of IN endpoint TxFIFO 4 in Device mode. For IN endpoint FIFO 0 use
USB_GNPTXFSIZ register for programming the size and memory start address.
Offset Bit Position
0x3C110
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
16
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
Reset
0x200
0xA00
Access
RW
RW
Name
INEPNTXFDEP
INEPNTXFSTADDR
Bit Name Reset Access Description
31:26 Reserved To ensure compatibility with future devices, always write bits to 0. More information in 2.1 Conven-
tions.
25:16 INEPNTXFDEP 0x200 RW IN Endpoint TxFIFO Depth
This value is in terms of 32-bit words. Minimum value is 16. Maximum value is 512.
15:12 Reserved To ensure compatibility with future devices, always write bits to 0. More information in 2.1 Conven-
tions.
11:0 INEPNTXFSTADDR 0xA00 RW IN Endpoint FIFO 4 Transmit RAM Start Address
This field contains the memory start address for IN endpoint Transmit FIFO 4.
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15.6.26 USB_DIEPTXF5 - Device IN Endpoint Transmit FIFO 5 Size Register
This register holds the size and memory start address of IN endpoint TxFIFO 5 in Device mode. For IN endpoint FIFO 0 use
USB_GNPTXFSIZ register for programming the size and memory start address.
Offset Bit Position
0x3C114
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
16
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
Reset
0x200
0xC00
Access
RW
RW
Name
INEPNTXFDEP
INEPNTXFSTADDR
Bit Name Reset Access Description
31:26 Reserved To ensure compatibility with future devices, always write bits to 0. More information in 2.1 Conven-
tions.
25:16 INEPNTXFDEP 0x200 RW IN Endpoint TxFIFO Depth
This value is in terms of 32-bit words. Minimum value is 16. Maximum value is 512.
15:12 Reserved To ensure compatibility with future devices, always write bits to 0. More information in 2.1 Conven-
tions.
11:0 INEPNTXFSTADDR 0xC00 RW IN Endpoint FIFO 5 Transmit RAM Start Address
This field contains the memory start address for IN endpoint Transmit FIFO 5.
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15.6.27 USB_DIEPTXF6 - Device IN Endpoint Transmit FIFO 6 Size Register
This register holds the size and memory start address of IN endpoint TxFIFO 6 in Device mode. For IN endpoint FIFO 0 use
USB_GNPTXFSIZ register for programming the size and memory start address.
Offset Bit Position
0x3C118
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
16
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
Reset
0x200
0xE00
Access
RW
RW
Name
INEPNTXFDEP
INEPNTXFSTADDR
Bit Name Reset Access Description
31:26 Reserved To ensure compatibility with future devices, always write bits to 0. More information in 2.1 Conven-
tions.
25:16 INEPNTXFDEP 0x200 RW IN Endpoint TxFIFO Depth
This value is in terms of 32-bit words. Minimum value is 16. Maximum value is 512.
15:12 Reserved To ensure compatibility with future devices, always write bits to 0. More information in 2.1 Conven-
tions.
11:0 INEPNTXFSTADDR 0xE00 RW IN Endpoint FIFO 6 Transmit RAM Start Address
This field contains the memory start address for IN endpoint Transmit FIFO 6.
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15.6.28 USB_HCFG - Host Configuration Register
This register configures the core after power-on. Do not make changes to this register after initializing the host.
Offset Bit Position
0x3C400
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
16
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
Reset
0
0x00
0
0
0x0
Access
RW
RW
RW
RW
RW
Name
MODECHTIMEN
RESVALID
ENA32KHZS
FSLSSUPP
FSLSPCLKSEL
Bit Name Reset Access Description
31 MODECHTIMEN 0 RW Mode Change Time
This bit is used to enable/disable the Host core to wait 200 clock cycles at the end of Resume before changing the PHY
opmode to normal operation. When set to 0 the Host core waits for either 200 PHY clock cycles or a linestate of SE0 at the
end of resume to the change the PHY opmode to normal operation. When set to 1 the Host core waits only for a linstate of
SE0 at the end of resume to change the PHY opmode to normal operation.
30:16 Reserved To ensure compatibility with future devices, always write bits to 0. More information in 2.1 Conven-
tions.
15:8 RESVALID 0x00 RW Resume Validation Period
This field is effective only when USB_HCFG.ENA32KHZS is set. It will control the resume period when the core resumes
from suspend. The core counts for RESVALID number of clock cycles to detect a valid resume when
USB_HCFG.ENA32KHZS is set.
7 ENA32KHZS 0 RW Enable 32 KHz Suspend mode
When this bit is set the core expects that the clock to the core during Suspend is switched from 48 MHz to 32 KHz.
6:3 Reserved To ensure compatibility with future devices, always write bits to 0. More information in 2.1 Conven-
tions.
2 FSLSSUPP 0 RW FS- and LS-Only Support
The application uses this bit to control the core's enumeration speed. Using this bit, the application can make the core enu-
merate as a FS host, even If the connected device supports HS traffic. Do not make changes to this field after initial pro-
gramming.
Value Mode Description
0 HSFSLS HS/FS/LS, based on the maximum speed supported by the connected
device.
1 FSLS FS/LS-only, even If the connected device can support HS.
1:0 FSLSPCLKSEL 0x0 RW FS/LS PHY Clock Select
Use this field to set the internal PHY clock frequency. Set to 48 MHz in FS Host mode and 6 MHz in LS Host mode. When
you select a 6 MHz clock during LS mode, you must do a soft reset.
Value Mode Description
1 DIV1 Internal PHY clock is running at 48 MHz (undivided).
2 DIV8 Internal PHY clock is running at 6 MHz (48 MHz divided by 8).
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15.6.29 USB_HFIR - Host Frame Interval Register
This register stores the frame interval information for the current speed to which the core has enumerated.
Offset Bit Position
0x3C404
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
16
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
Reset
0
0x17D7
Access
RW
RW
Name
HFIRRLDCTRL
FRINT
Bit Name Reset Access Description
31:17 Reserved To ensure compatibility with future devices, always write bits to 0. More information in 2.1 Conven-
tions.
16 HFIRRLDCTRL 0 RW Reload Control
This bit allows dynamic reloading of the HFIR register during run time. This bit needs to be programmed during initial con-
figuration and its value should not be changed during runtime.
Value Mode Description
0 STATIC The HFIR cannot be reloaded dynamically.
1 DYNAMIC The HFIR can be dynamically reloaded during runtime.
15:0 FRINT 0x17D7 RW Frame Interval
The value that the application programs to this field specifies the interval between two consecutive SOFs (FS) or Keep-
Alive tokens (LS). This field contains the number of PHY clocks that constitute the required frame interval. The application
can write a value to this register only after the Port Enable bit of the Host Port Control and Status register
(USB_HPRT.PRTENA) has been set. If no value is programmed, the core calculates the value based on the PHY clock
specified in the FS/LS PHY Clock Select field of the Host Configuration register (USB_HCFG.FSLSPCLKSEL). Do not
change the value of this field after the initial configuration. Set to 48000 (1 ms at 48 MHz) for FS and 6000 (1 ms at 6 MHz)
for LS.
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15.6.30 USB_HFNUM - Host Frame Number/Frame Time Remaining Register
This register indicates the current frame number. It also indicates the time remaining (in terms of the number of PHY clocks) in the
current frame.
Offset Bit Position
0x3C408
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
16
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
Reset
0x0000
0x3FFF
Access
R
R
Name
FRREM
FRNUM
Bit Name Reset Access Description
31:16 FRREM 0x0000 R Frame Time Remaining
Indicates the amount of time remaining in the current Frame, in terms of PHY clocks. This field decrements on each PHY
clock. When it reaches zero, this field is reloaded with the value in the Frame Interval register and a new SOF is transmitted
on the USB.
15:0 FRNUM 0x3FFF R Frame Number
This field increments when a new SOF is transmitted on the USB, and is reset to 0 when it reaches 0x3FFF.
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15.6.31 USB_HPTXSTS - Host Periodic Transmit FIFO/Queue Status Register
This read-only register contains the free space information for the Periodic TxFIFO and the Periodic Transmit Request Queue.
Offset Bit Position
0x3C410
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
16
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
Reset
0x00
0x08
0x0200
Access
R
R
R
Name
PTXQTOP
PTXQSPCAVAIL
PTXFSPCAVAIL
Bit Name Reset Access Description
31:24 PTXQTOP 0x00 R Top of the Periodic Transmit Request Queue
This indicates the Entry in the Periodic Tx Request Queue that is currently being processes by the MAC. This register is
used for debugging.
Bit [7]: Odd/Even Frame. 0: send in even Frame, 1: send in odd Frame.
Bits [6:3]: Channel/endpoint number.
Bits [2:1]: Type. 00: IN/OUT, 01: Zero-length packet, 10: Unused, 11: Disable channel command.
Bit [0]: Terminate (last Entry for the selected channel/endpoint).
23:16 PTXQSPCAVAIL 0x08 R Periodic Transmit Request Queue Space Available
Indicates the number of free locations available to be written in the Periodic Transmit Request Queue. This queue holds
both IN and OUT requests.
15:0 PTXFSPCAVAIL 0x0200 R Periodic Transmit Data FIFO Space Available
Indicates the number of free locations available to be written to in the Periodic TxFIFO. Values are in terms of 32-bit words.
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15.6.32 USB_HAINT - Host All Channels Interrupt Register
When a significant event occurs on a channel, the Host All Channels Interrupt register interrupts the application using the Host Chan-
nels Interrupt bit of the Core Interrupt register (USB_GINTSTS.HCHINT). There is one interrupt bit per channel. Bits in this register are
set and cleared when the application sets and clears bits in the corresponding Host Channel x Interrupt register.
Offset Bit Position
0x3C414
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
16
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
Reset
0x0000
Access
R
Name
HAINT
Bit Name Reset Access Description
31:14 Reserved To ensure compatibility with future devices, always write bits to 0. More information in 2.1 Conven-
tions.
13:0 HAINT 0x0000 R Channel Interrupt for channel 0 - 13.
When the interrupt bit for a channel x set, one or more of the interrupt flags in the USB_HCx_INT are set.
15.6.33 USB_HAINTMSK - Host All Channels Interrupt Mask Register
The Host All Channel Interrupt Mask register works with the Host All Channel Interrupt register to interrupt the application when an
event occurs on a channel. There is one interrupt mask bit per channel. Set bits to unmask.
Offset Bit Position
0x3C418
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
16
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
Reset
0x0000
Access
RW
Name
HAINTMSK
Bit Name Reset Access Description
31:14 Reserved To ensure compatibility with future devices, always write bits to 0. More information in 2.1 Conven-
tions.
13:0 HAINTMSK 0x0000 RW Channel Interrupt Mask for channel 0 - 13
Set bit n to unmask channel n interrupts.
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15.6.34 USB_HPRT - Host Port Control and Status Register
This register is available only in Host mode. This register holds USB port-related information such as USB reset, enable, suspend, re-
sume, connect status, and test mode for the port. Some bits in this register can trigger an interrupt to the application through the Host
Port Interrupt bit of the Core Interrupt register (USB_GINTSTS.PRTINT). On a Port Interrupt, the application must read this register and
clear the bit that caused the interrupt. For the RW1H bits, the application must write a 1 to the bit to clear the interrupt.
Offset Bit Position
0x3C440
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
16
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
Reset
0x0
0x0
0
0x0
0
0
0
0
0
0
0
0
0
Access
R
RW
RW
R
RW
RW1H
RW
RW1H
R
RW1H
RW1H
RW1H
R
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Offset Bit Position
Name
PRTSPD
PRTTSTCTL
PRTPWR
PRTLNSTS
PRTRST
PRTSUSP
PRTRES
PRTOVRCURRCHNG
PRTOVRCURRACT
PRTENCHNG
PRTENA
PRTCONNDET
PRTCONNSTS
Bit Name Reset Access Description
31:19 Reserved To ensure compatibility with future devices, always write bits to 0. More information in 2.1 Conven-
tions.
18:17 PRTSPD 0x0 R Port Speed
Indicates the speed of the device attached to this port.
Value Mode Description
0 HS High speed.
1 FS Full speed.
2 LS Low speed.
16:13 PRTTSTCTL 0x0 RW Port Test Control
The application writes a nonzero value to this field to put the port into a Test mode, and the corresponding pattern is sig-
naled on the port.
Value Mode Description
0 DISABLE Test mode disabled.
1 J Test_J mode.
2 K Test_K mode.
3 SE0NAK Test_SE0_NAK mode.
4 PACKET Test_Packet mode.
5 FORCE Test_Force_Enable.
12 PRTPWR 0 RW Port Power
The application uses this field to control power to this port. The core can clear this bit on an over current condition.
Value Mode Description
0 OFF Power off.
1 ON Power on.
11:10 PRTLNSTS 0x0 R Port Line Status
Indicates the current logic level USB data lines. Bit [0]: Logic level of D+. Bit [1]: Logic level of D-.
9 Reserved To ensure compatibility with future devices, always write bits to 0. More information in 2.1 Conven-
tions.
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Bit Name Reset Access Description
8 PRTRST 0 RW Port Reset
When the application sets this bit, a reset sequence is started on this port. The application must time the reset period and
clear this bit after the reset sequence is complete. The application must leave this bit set for at least 10 ms to start a reset
on the port. The application can leave it set for another 10 ms in addition to the required minimum duration, before clearing
the bit, even though there is no maximum limit set by the USB standard.
7 PRTSUSP 0 RW1H Port Suspend
The application sets this bit to put this port in Suspend mode. The core only stops sending SOFs when this is set. To stop
the PHY clock, the application must set USB_PCGCCTL.STOPPCLK, which puts the PHY into suspend mode. The read
value of this bit reflects the current suspend status of the port. This bit is cleared by the core after a remote wakeup signal
is detected or the application sets the Port Reset bit or Port Resume bit in this register or the Resume/Remote Wakeup
Detected Interrupt bit or Disconnect Detected Interrupt bit in the Core Interrupt register (USB_GINTSTS.WKUPINT or
USB_GINTSTS.DISCONNINT respectively). This bit is cleared by the core even if there is no device connected to the Host.
6 PRTRES 0 RW Port Resume
The application sets this bit to drive resume signaling on the port. The core continues to drive the resume signal until the
application clears this bit. If the core detects a USB remote wakeup sequence, as indicated by the Port Resume/Remote
Wakeup Detected Interrupt bit of the Core Interrupt register (USB_GINTSTS.WKUPINT), the core starts driving resume sig-
naling without application intervention and clears this bit when it detects a disconnect condition. The read value of this bit
indicates whether the core is currently driving resume signaling.
5 PRTOVR-
CURRCHNG
0 RW1H Port Overcurrent Change
The core sets this bit when the status of the Port Overcurrent Active bit (bit 4) in this register changes. This bit can be set
only by the core and the application should write 1 to clear it.
4 PRTOVRCURRACT 0 R Port Overcurrent Active
Indicates the overcurrent condition of the port. When there is an overcurrent condition this bit is 1.
3 PRTENCHNG 0 RW1H Port Enable/Disable Change
The core sets this bit when the status of the Port Enable bit[2] of this register changes. This bit can be set only by the core
and the application should write 1 to clear it.
2 PRTENA 0 RW1H Port Enable
A port is enabled only by the core after a reset sequence, and is disabled by an overcurrent condition, a disconnect condi-
tion, or by the application clearing this bit. The application cannot set this bit by a register write. It can only clear it to disable
the port by writing 1. This bit does not trigger any interrupt to the application.
1 PRTCONNDET 0 RW1H Port Connect Detected
The core sets this bit when a device connection is detected to trigger an interrupt to the application using the Host Port
Interrupt bit of the Core Interrupt register (USB_GINTSTS.PRTINT). This bit can be set only by the core and the application
should write 1 to clear it. The application must write a 1 to this bit to clear the interrupt.
0 PRTCONNSTS 0 R Port Connect Status
When this bit is 1 a device is attached to the port.
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15.6.35 USB_HCx_CHAR - Host Channel x Characteristics Register
Offset Bit Position
0x3C500
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
16
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
Reset
0
0
0
0x00
0x0
0x0
0
0
0x0
0x000
Access
RW1H
RW1H
RW
RW
RW
RW
RW
RW
RW
RW
Name
CHENA
CHDIS
ODDFRM
DEVADDR
MC
EPTYPE
LSPDDEV
EPDIR
EPNUM
MPS
Bit Name Reset Access Description
31 CHENA 0 RW1H Channel Enable
This field is set by the application and cleared by the core. The state of this bit reflects the channel enable status.
30 CHDIS 0 RW1H Channel Disable
The application sets this bit to stop transmitting/receiving data on a channel, even before the transfer for that channel is
complete. The application must wait for the Channel Disabled interrupt before treating the channel as disabled.
29 ODDFRM 0 RW Odd Frame
This field is set (reset) by the application to indicate that the OTG host must perform a transfer in an odd frame. This field is
applicable for only periodic (isochronous and interrupt) transactions.
28:22 DEVADDR 0x00 RW Device Address
This field selects the specific device serving as the data source or sink.
21:20 MC 0x0 RW Multi Count
For periodic transfers this field indicates to the host the number of transactions that must be executed per frame for this
periodic endpoint. For non-periodic transfers, this field is used only in DMA mode, and specifies the number packets to be
fetched for this channel before the internal DMA engine changes arbitration.
19:18 EPTYPE 0x0 RW Endpoint Type
Indicates the transfer type selected.
Value Mode Description
0 CONTROL Control endpoint.
1 ISO Isochronous endpoint.
2 BULK Bulk endpoint.
3 INT Interrupt endpoint.
17 LSPDDEV 0 RW Low-Speed Device
This field is set by the application to indicate that this channel is communicating to a low-speed device.
16 Reserved To ensure compatibility with future devices, always write bits to 0. More information in 2.1 Conven-
tions.
15 EPDIR 0 RW Endpoint Direction
Indicates whether the transaction is IN or OUT.
Value Mode Description
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Bit Name Reset Access Description
0 OUT Direction is OUT.
1 IN Direction is IN.
14:11 EPNUM 0x0 RW Endpoint Number
Indicates the endpoint number on the device serving as the data source or sink.
10:0 MPS 0x000 RW Maximum Packet Size
Indicates the maximum packet size of the associated endpoint.
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15.6.36 USB_HCx_INT - Host Channel x Interrupt Register
This register indicates the status of a channel with respect to USB- and AHB-related events. The application must read this register
when the Host Channels Interrupt bit of the Core Interrupt register (USB_GINTSTS.HCHINT) is set. Before the application can read this
register, it must first read the Host All Channels Interrupt (USB_HAINT) register to get the exact channel number for the Host Channel x
Interrupt register. The application must clear the appropriate bit in this register to clear the corresponding bits in the USB_HAINT and
USB_GINTSTS registers.
Offset Bit Position
0x3C508
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
16
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
Reset
0
0
0
0
0
0
0
0
0
0
Access
RW1H
RW1H
RW1H
RW1H
RW1H
RW1H
RW1H
RW1H
RW1H
RW1H
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Offset Bit Position
Name
DATATGLERR
FRMOVRUN
BBLERR
XACTERR
ACK
NAK
STALL
AHBERR
CHHLTD
XFERCOMPL
Bit Name Reset Access Description
31:11 Reserved To ensure compatibility with future devices, always write bits to 0. More information in 2.1 Conven-
tions.
10 DATATGLERR 0 RW1H Data Toggle Error
This bit can be set only by the core and the application should write 1 to clear it.
9 FRMOVRUN 0 RW1H Frame Overrun
This bit can be set only by the core and the application should write 1 to clear it.
8 BBLERR 0 RW1H Babble Error
This bit can be set only by the core and the application should write 1 to clear it.
7 XACTERR 0 RW1H Transaction Error
Indicates one of the following errors occurred on the USB: CRC check failure, Timeout, Bit stuff error or False EOP. This bit
can be set only by the core and the application should write 1 to clear it.
6 Reserved To ensure compatibility with future devices, always write bits to 0. More information in 2.1 Conven-
tions.
5 ACK 0 RW1H ACK Response Received/Transmitted Interrupt
This bit can be set only by the core and the application should write 1 to clear it.
4 NAK 0 RW1H NAK Response Received Interrupt
This bit can be set only by the core and the application should write 1 to clear it.
3 STALL 0 RW1H STALL Response Received Interrupt
This bit can be set only by the core and the application should write 1 to clear it.
2 AHBERR 0 RW1H AHB Error
This is generated only in DMA mode when there is an AHB error during AHB read/write. The application can read the corre-
sponding channel's DMA address register to get the error address.
1 CHHLTD 0 RW1H Channel Halted
In DMA mode this bit indicates the transfer completed abnormally either because of any USB transaction error or in re-
sponse to disable request by the application or because of a completed transfer.
0 XFERCOMPL 0 RW1H Transfer Completed
Transfer completed normally without any errors. This bit can be set only by the core and the application should write 1 to
clear it.
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15.6.37 USB_HCx_INTMSK - Host Channel x Interrupt Mask Register
This register reflects the mask for each channel status described in the USB_CHx_INT.
Offset Bit Position
0x3C50
C
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
16
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
Reset
0
0
0
0
0
0
0
0
0
0
Access
RW
RW
RW
RW
RW
RW
RW
RW
RW
RW
Name
DATATGLERRMSK
FRMOVRUNMSK
BBLERRMSK
XACTERRMSK
ACKMSK
NAKMSK
STALLMSK
AHBERRMSK
CHHLTDMSK
XFERCOMPLMSK
Bit Name Reset Access Description
31:11 Reserved To ensure compatibility with future devices, always write bits to 0. More information in 2.1 Conven-
tions.
10 DATATGLERRMSK 0 RW Data Toggle Error Mask
Set to unmask DATATGLERR interrupt.
9 FRMOVRUNMSK 0 RW Frame Overrun Mask
Set to unmask FRMOVRUN interrupt.
8 BBLERRMSK 0 RW Babble Error Mask
Set to unmask BBLERR interrupt.
7 XACTERRMSK 0 RW Transaction Error Mask
Set to unmask XACTERR interrupt.
6 Reserved To ensure compatibility with future devices, always write bits to 0. More information in 2.1 Conven-
tions.
5 ACKMSK 0 RW ACK Response Received/Transmitted Interrupt Mask
Set to unmask ACK interrupt.
4 NAKMSK 0 RW NAK Response Received Interrupt Mask
Set to unmask NAK interrupt.
3 STALLMSK 0 RW STALL Response Received Interrupt Mask
Set to unmask STALL interrupt.
2 AHBERRMSK 0 RW AHB Error Mask
Set to unmask AHBERR interrupt.
1 CHHLTDMSK 0 RW Channel Halted Mask
Set to unmask CHHLTD interrupt.
0 XFERCOMPLMSK 0 RW Transfer Completed Mask
Set to unmask XFERCOMPL interrupt.
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15.6.38 USB_HCx_TSIZ - Host Channel x Transfer Size Register
Offset Bit Position
0x3C510
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
16
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
Reset
0x0
0x000
0x00000
Access
RW
RW
RW
Name
PID
PKTCNT
XFERSIZE
Bit Name Reset Access Description
31 Reserved To ensure compatibility with future devices, always write bits to 0. More information in 2.1 Conven-
tions.
30:29 PID 0x0 RW Packet ID
The application programs this field with the packet ID type to use for the initial transaction. The host maintains this field for
the rest of the transfer.
Value Mode Description
0 DATA0 DATA0 PID.
1 DATA2 DATA2 PID.
2 DATA1 DATA1 PID.
3 MDATA MDATA (non-control) / SETUP (control) PID.
28:19 PKTCNT 0x000 RW Packet Count
This field is programmed by the application with the expected number of packets to be transmitted (OUT) or received (IN).
The host decrements this count on every successful transmission or reception of an OUT/IN packet. Once this count rea-
ches zero, the application is interrupted to indicate normal completion.
18:0 XFERSIZE 0x00000 RW Transfer Size
For an OUT, this field is the number of data bytes the host sends during the transfer. For an IN, this field is the buffer size
that the application has reserved for the transfer. The application is expected to program this field as an integer multiple of
the maximum packet size for IN transactions (periodic and non-periodic).
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15.6.39 USB_HCx_DMAADDR - Host Channel x DMA Address Register
This register is used by the OTG host in the internal DMA mode to maintain the current buffer pointer for IN/OUT transactions. The
starting DMA address must be DWORD-aligned.
Offset Bit Position
0x3C514
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
16
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
Reset
0xXXXXXXXX
Access
RW
Name
DMAADDR
Bit Name Reset Access Description
31:0 DMAADDR 0xXXXXXXX
X
RW DMA Address
This field holds the start address in the external memory from which the data for the endpoint must be fetched or to which it
must be stored. This register is incremented on every AHB transaction. The data for this register field is stored in RAM.
Thus, the reset value is undefined (X).
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15.6.40 USB_DCFG - Device Configuration Register
This register configures the core in Device mode after power-on or after certain control commands or enumeration. Do not make
changes to this register after initial programming.
Offset Bit Position
0x3C800
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
16
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
Reset
0x02
0x0
0x00
0
0
0x0
Access
RW
RW
RW
RW
RW
RW
Name
RESVALID
PERFRINT
DEVADDR
ENA32KHZSUSP
NZSTSOUTHSHK
DEVSPD
Bit Name Reset Access Description
31:26 RESVALID 0x02 RW Resume Validation Period
This field is effective only when USB_DCFG.ENA32KHZSUSP is set. It will control the resume period when the core re-
sumes from suspend. The core counts for RESVALID number of clock cycles to detect a valid resume when
USB_DCFG.ENA32KHZSUSP is set.
25:13 Reserved To ensure compatibility with future devices, always write bits to 0. More information in 2.1 Conven-
tions.
12:11 PERFRINT 0x0 RW Periodic Frame Interval
Indicates the time within a frame at which the application must be notified using the End Of Periodic Frame Interrupt. This
can be used to determine if all the isochronous traffic for that frame is complete.
Value Mode Description
0 80PCNT 80% of the frame interval.
1 85PCNT 85% of the frame interval.
2 90PCNT 90% of the frame interval.
3 95PCNT 95% of the frame interval.
10:4 DEVADDR 0x00 RW Device Address
The application must program this field after every SetAddress control command.
3 ENA32KHZSUSP 0 RW Enable 32 KHz Suspend mode
When this bit is set, the core expects that the PHY clock during Suspend is switched from 48 MHz to 32 KHz.
2 NZSTSOUTHSHK 0 RW Non-Zero-Length Status OUT Handshake
The application can use this field to select the handshake the core sends on receiving a nonzero-length data packet during
the OUT transaction of a control transfer's Status stage. When set to 1 send a STALL handshake on a nonzero-length sta-
tus OUT transaction and do not send the received OUT packet to the application. When set to 0 send the received OUT
packet to the application (zerolength or nonzero-length) and send a handshake based on the NAK and STALL bits for the
endpoint in the Device Endpoint Control register.
1:0 DEVSPD 0x0 RW Device Speed
Indicates the speed at which the application requires the core to enumerate, or the maximum speed the application can
support. However, the actual bus speed is determined only after the chirp sequence is completed, and is based on the
speed of the USB host to which the core is connected.
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Bit Name Reset Access Description
Value Mode Description
2 LS Low speed (PHY clock is 6 MHz). If you select 6 MHz LS mode, you
must do a soft reset.
3 FS Full speed (PHY clock is 48 MHz).
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15.6.41 USB_DCTL - Device Control Register
Offset Bit Position
0x3C804
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
16
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
Reset
0
0
0
0
0
0
0
0x0
0
0
0
0
Access
RW
RW
RW
W1
W1
W1
W1
RW
R
R
RW
RW
Name
NAKONBBLE
IGNRFRMNUM
PWRONPRGDONE
CGOUTNAK
SGOUTNAK
CGNPINNAK
SGNPINNAK
TSTCTL
GOUTNAKSTS
GNPINNAKSTS
SFTDISCON
RMTWKUPSIG
Bit Name Reset Access Description
31:17 Reserved To ensure compatibility with future devices, always write bits to 0. More information in 2.1 Conven-
tions.
16 NAKONBBLE 0 RW NAK on Babble Error
Set NAK automatically on babble. The core sets NAK automatically for the endpoint on which babble is received.
15 IGNRFRMNUM 0 RW Ignore Frame number For Isochronous End points
When set to 0 the core transmits the packets only in the frame number in which they are intended to be transmitted. When
set to 1 the core ignores the frame number, sending packets immediately as the packets are ready.
14:12 Reserved To ensure compatibility with future devices, always write bits to 0. More information in 2.1 Conven-
tions.
11 PWRONPRGDONE 0 RW Power-On Programming Done
The application uses this bit to indicate that register programming is completed after a wake-up from Power Down mode.
10 CGOUTNAK 0 W1 Clear Global OUT NAK
A write to this field clears the Global OUT NAK.
9 SGOUTNAK 0 W1 Set Global OUT NAK
A write to this field sets the Global OUT NAK. The application uses this bit to send a NAK handshake on all OUT endpoints.
The application must set this bit only after making sure that the Global OUT NAK Effective bit in the Core Interrupt Register
(USB_GINTSTS.GOUTNAKEFF) is cleared.
8 CGNPINNAK 0 W1 Clear Global Non-periodic IN NAK
A write to this field clears the Global Non-periodic IN NAK.
7 SGNPINNAK 0 W1 Set Global Non-periodic IN NAK
A write to this field sets the Global Non-periodic IN NAK. The application uses this bit to send a NAK handshake on all non-
periodic IN endpoints. The application must set this bit only after making sure that the Global IN NAK Effective bit in the
Core Interrupt Register (USB_GINTSTS.GINNAKEFF) is cleared.
6:4 TSTCTL 0x0 RW Test Control
Set to a non-zero value to enable test control.
Value Mode Description
0 DISABLE Test mode disabled.
1 J Test_J mode.
2 K Test_K mode.
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Bit Name Reset Access Description
3 SE0NAK Test_SE0_NAK mode.
4 PACKET Test_Packet mode.
5 FORCE Test_Force_Enable.
3 GOUTNAKSTS 0 R Global OUT NAK Status
When this bit is 0 a handshake is sent based on the FIFO Status and the NAK and STALL bit settings. When this bit is 1 no
data is written to the RxFIFO, irrespective of space availability. Sends a NAK handshake on all packets, except on SETUP
transactions. All isochronous OUT packets are dropped.
2 GNPINNAKSTS 0 R Global Non-periodic IN NAK Status
When this bit is 0 a handshake is sent out based on the data availability in the transmit FIFO. When this bit is 1 a NAK
handshake is sent out on all non-periodic IN endpoints, irrespective of the data availability in the transmit FIFO.
1 SFTDISCON 0 RW Soft Disconnect
The application uses this bit to signal the core to do a soft disconnect. As long as this bit is set, the host does not see that
the device is connected, and the device does not receive signals on the USB. The core stays in the disconnected state until
the application clears this bit. When suspended, the minimum duration for which the core must keep this bit set is 1 ms +
2.5 us. When IDLE or performing transactions, the minimum duration for which the core must keep this bit set is 2.5 us.
0 RMTWKUPSIG 0 RW Remote Wakeup Signaling
When the application sets this bit, the core initiates remote signaling to wake up the USB host. The application must set this
bit to instruct the core to exit the Suspend state. As specified in the USB 2.0 specification, the application must clear this bit
1-15 ms after setting it.
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15.6.42 USB_DSTS - Device Status Register
This register indicates the status of the core with respect to USB-related events. It must be read on interrupts from Device All Interrupts
(USB_DAINT) register.
Offset Bit Position
0x3C808
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
16
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
Reset
0x0000
0
0x1
0
Access
R
R
R
R
Name
SOFFN
ERRTICERR
ENUMSPD
SUSPSTS
Bit Name Reset Access Description
31:22 Reserved To ensure compatibility with future devices, always write bits to 0. More information in 2.1 Conven-
tions.
21:8 SOFFN 0x0000 R Frame Number of the Received SOF
This field contains a Frame number. This field may return a non zero value if read immediately after power on reset. In case
the register bits reads non zero immediately after power on reset it does not indicate that SOF has been received from the
host. The read value of this interrupt is valid only after a valid connection between host and device is established.
7:4 Reserved To ensure compatibility with future devices, always write bits to 0. More information in 2.1 Conven-
tions.
3 ERRTICERR 0 R Erratic Error
The core sets this bit to report any erratic errors (PHY error) Due to erratic errors, the core goes into Suspended state and
an interrupt is generated to the application with Early Suspend bit of the Core Interrupt register (USB_GINTSTS.ERLY-
SUSP). If the early suspend is asserted due to an erratic error, the application can only perform a soft disconnect recover.
2:1 ENUMSPD 0x1 R Enumerated Speed
Indicates the speed at which the core has come up after speed detection through a chirp sequence.
Value Mode Description
2 LS Low speed (PHY clock is running at 6 MHz).
3 FS Full speed (PHY clock is running at 48 MHz).
0 SUSPSTS 0 R Suspend Status
In Device mode, this bit is set as long as a Suspend condition is detected on the USB. The core enters the Suspended
state when there is no activity on the bus for an extended period of time. The core comes out of the suspend when there is
any activity on the bus or when the application writes to the Remote Wakeup Signaling bit in the Device Control register
(USB_DCTL.RMTWKUPSIG).
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15.6.43 USB_DIEPMSK - Device IN Endpoint Common Interrupt Mask Register
This register works with each of the Device IN Endpoint Interrupt (USB_DIEP0INT/USB_DIEPx_INT) registers for all endpoints to gen-
erate an interrupt per IN endpoint. The IN endpoint interrupt for a specific status in the USB_DIEP0INT/USB_DIEPx_INT register can
be masked by writing to the corresponding bit in this register. Status bits are masked by default.
Offset Bit Position
0x3C810
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
16
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
Reset
0
0
0
0
0
0
0
0
Access
RW
RW
RW
RW
RW
RW
RW
RW
Name
NAKMSK
TXFIFOUNDRNMSK
INEPNAKEFFMSK
INTKNTXFEMPMSK
TIMEOUTMSK
AHBERRMSK
EPDISBLDMSK
XFERCOMPLMSK
Bit Name Reset Access Description
31:14 Reserved To ensure compatibility with future devices, always write bits to 0. More information in 2.1 Conven-
tions.
13 NAKMSK 0 RW NAK interrupt Mask
Set to 1 to unmask NAK Interrupt.
12:9 Reserved To ensure compatibility with future devices, always write bits to 0. More information in 2.1 Conven-
tions.
8 TXFIFOUNDRNMSK 0 RW Fifo Underrun Mask
Set to 1 to unmask TXFIFOUNDRN Interrupt.
7 Reserved To ensure compatibility with future devices, always write bits to 0. More information in 2.1 Conven-
tions.
6 INEPNAKEFFMSK 0 RW IN Endpoint NAK Effective Mask
Set to 1 to unmask INEPNAKEFF Interrupt.
5 Reserved To ensure compatibility with future devices, always write bits to 0. More information in 2.1 Conven-
tions.
4 INTKNTXFEMPMSK 0 RW IN Token Received When TxFIFO Empty Mask
Set to 1 to unmask INTKNTXFEMP Interrupt.
3 TIMEOUTMSK 0 RW Timeout Condition Mask
Set to 1 to unmask Interrupt TIMEOUT. Applies to Non-isochronous endpoints.
2 AHBERRMSK 0 RW AHB Error Mask
Set to 1 to unmask AHBERR Interrupt.
1 EPDISBLDMSK 0 RW Endpoint Disabled Interrupt Mask
Set to 1 to unmask EPDISBLD Interrupt.
0 XFERCOMPLMSK 0 RW Transfer Completed Interrupt Mask
Set to 1 to unmask XFERCOMPL Interrupt.
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15.6.44 USB_DOEPMSK - Device OUT Endpoint Common Interrupt Mask Register
This register works with each of the Device OUT Endpoint Interrupt (USB_DOEP0INT/USB_DOEPx_INT) registers for all endpoints to
generate an interrupt per OUT endpoint. The OUT endpoint interrupt for a specific status in the USB_DOEP0INT/USB_DOEPx_INT
register can be masked by writing into the corresponding bit in this register. Status bits are masked by default.
Offset Bit Position
0x3C814
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
16
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
Reset
0
0
0
0
0
0
0
0
0
Access
RW
RW
RW
RW
RW
RW
RW
RW
RW
Name
NAKMSK
BBLEERRMSK
OUTPKTERRMSK
BACK2BACKSETUP
OUTTKNEPDISMSK
SETUPMSK
AHBERRMSK
EPDISBLDMSK
XFERCOMPLMSK
Bit Name Reset Access Description
31:14 Reserved To ensure compatibility with future devices, always write bits to 0. More information in 2.1 Conven-
tions.
13 NAKMSK 0 RW NAK interrupt Mask
Set to 1 to unmask NAK Interrupt.
12 BBLEERRMSK 0 RW Babble Error interrupt Mask
Set to 1 to unmask BBLEERR Interrupt.
11:9 Reserved To ensure compatibility with future devices, always write bits to 0. More information in 2.1 Conven-
tions.
8 OUTPKTERRMSK 0 RW OUT Packet Error Mask
Set to 1 to unmask OUTPKTERR Interrupt.
7 Reserved To ensure compatibility with future devices, always write bits to 0. More information in 2.1 Conven-
tions.
6 BACK2BACKSETUP 0 RW Back-to-Back SETUP Packets Received Mask
Set to 1 to unmask BACK2BACKSETUP Interrupt. Applies to control OUT endpoints only.
5 Reserved To ensure compatibility with future devices, always write bits to 0. More information in 2.1 Conven-
tions.
4 OUTTKNEPDISMSK 0 RW OUT Token Received when Endpoint Disabled Mask
Set to 1 to unmask OUTTKNEPDIS Interrupt. Applies to control OUT endpoints only.
3 SETUPMSK 0 RW SETUP Phase Done Mask
Set to 1 to unmask SETUP Interrupt. Applies to control endpoints only.
2 AHBERRMSK 0 RW AHB Error
Set to 1 to unmask AHBERR Interrupt.
1 EPDISBLDMSK 0 RW Endpoint Disabled Interrupt Mask
Set to 1 to unmask EPDISBLD Interrupt.
0 XFERCOMPLMSK 0 RW Transfer Completed Interrupt Mask
Set to 1 to unmask XFERCOMPL Interrupt.
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15.6.45 USB_DAINT - Device All Endpoints Interrupt Register
When a significant event occurs on an endpoint, a Device All Endpoints Interrupt register interrupts the application using the Device
OUT Endpoints Interrupt bit or Device IN Endpoints Interrupt bit of the Core Interrupt register (USB_GINTSTS.OEPINT or
USB_GINTSTS.IEPINT, respectively). There is one interrupt bit per endpoint. For a bidirectional endpoint, the corresponding IN and
OUT interrupt bits are used. Bits in this register are set and cleared when the application sets and clears bits in the corresponding De-
vice Endpoint Interrupt register (USB_DIEP0INT/USB_DIEPx_INT, USB_DOEP0INT/USB_DOEPx_INT).
Offset Bit Position
0x3C818
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
16
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
Reset
0
0
0
0
0
0
0
0
0
0
0
0
0
0
Access
R
R
R
R
R
R
R
R
R
R
R
R
R
R
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Offset Bit Position
Name
OUTEPINT6
OUTEPINT5
OUTEPINT4
OUTEPINT3
OUTEPINT2
OUTEPINT1
OUTEPINT0
INEPINT6
INEPINT5
INEPINT4
INEPINT3
INEPINT2
INEPINT1
INEPINT0
Bit Name Reset Access Description
31:23 Reserved To ensure compatibility with future devices, always write bits to 0. More information in 2.1 Conven-
tions.
22 OUTEPINT6 0 R OUT Endpoint 6 Interrupt Bit
This bit is set when on or more of the interrupt flags in USB_DOEP5_INT are set.
21 OUTEPINT5 0 R OUT Endpoint 5 Interrupt Bit
This bit is set when one or more of the interrupt flags in USB_DOEP4_INT are set.
20 OUTEPINT4 0 R OUT Endpoint 4 Interrupt Bit
This bit is set when one or more of the interrupt flags in USB_DOEP3_INT are set.
19 OUTEPINT3 0 R OUT Endpoint 3 Interrupt Bit
This bit is set when one or more of the interrupt flags in USB_DOEP2_INT are set.
18 OUTEPINT2 0 R OUT Endpoint 2 Interrupt Bit
This bit is set when one or more of the interrupt flags in USB_DOEP1_INT are set.
17 OUTEPINT1 0 R OUT Endpoint 1 Interrupt Bit
This bit is set when one or more of the interrupt flags in USB_DOEP0_INT are set.
16 OUTEPINT0 0 R OUT Endpoint 0 Interrupt Bit
This bit is set when one or more of the interrupt flags in USB_DOEP0INT are set.
15:7 Reserved To ensure compatibility with future devices, always write bits to 0. More information in 2.1 Conven-
tions.
6 INEPINT6 0 R IN Endpoint 6 Interrupt Bit
This bit is set when one or more of the interrupt flags in USB_DIEP5_INT are set.
5 INEPINT5 0 R IN Endpoint 5 Interrupt Bit
This bit is set when one or more of the interrupt flags in USB_DIEP4_INT are set.
4 INEPINT4 0 R IN Endpoint 4 Interrupt Bit
This bit is set when one or more of the interrupt flags in USB_DIEP3_INT are set.
3 INEPINT3 0 R IN Endpoint 3 Interrupt Bit
This bit is set when one or more of the interrupt flags in USB_DIEP2_INT are set.
2 INEPINT2 0 R IN Endpoint 2 Interrupt Bit
This bit is set when one or more of the interrupt flags in USB_DIEP1_INT are set.
1 INEPINT1 0 R IN Endpoint 1 Interrupt Bit
This bit is set when one or more of the interrupt flags in USB_DIEP0_INT are set.
0 INEPINT0 0 R IN Endpoint 0 Interrupt Bit
This bit is set when one or more of the interrupt flags in USB_DIEP0INT are set.
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15.6.46 USB_DAINTMSK - Device All Endpoints Interrupt Mask Register
The Device Endpoint Interrupt Mask register works with the Device Endpoint Interrupt register to interrupt the application when an event
occurs on a device endpoint. However, the Device All Endpoints Interrupt (USB_DAINT) register bit corresponding to that interrupt is
still set.
Offset Bit Position
0x3C81
C
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
16
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
Reset
0
0
0
0
0
0
0
0
0
0
0
0
0
0
Access
RW
RW
RW
RW
RW
RW
RW
RW
RW
RW
RW
RW
RW
RW
Name
OUTEPMSK6
OUTEPMSK5
OUTEPMSK4
OUTEPMSK3
OUTEPMSK2
OUTEPMSK1
OUTEPMSK0
INEPMSK6
INEPMSK5
INEPMSK4
INEPMSK3
INEPMSK2
INEPMSK1
INEPMSK0
Bit Name Reset Access Description
31:23 Reserved To ensure compatibility with future devices, always write bits to 0. More information in 2.1 Conven-
tions.
22 OUTEPMSK6 0 RW OUT Endpoint 6 Interrupt mask Bit
Set to 1 to unmask USB_DAINT.OUTEPINT6.
21 OUTEPMSK5 0 RW OUT Endpoint 5 Interrupt mask Bit
Set to 1 to unmask USB_DAINT.OUTEPINT5.
20 OUTEPMSK4 0 RW OUT Endpoint 4 Interrupt mask Bit
Set to 1 to unmask USB_DAINT.OUTEPINT4.
19 OUTEPMSK3 0 RW OUT Endpoint 3 Interrupt mask Bit
Set to 1 to unmask USB_DAINT.OUTEPINT3.
18 OUTEPMSK2 0 RW OUT Endpoint 2 Interrupt mask Bit
Set to 1 to unmask USB_DAINT.OUTEPINT2.
17 OUTEPMSK1 0 RW OUT Endpoint 1 Interrupt mask Bit
Set to 1 to unmask USB_DAINT.OUTEPINT1.
16 OUTEPMSK0 0 RW OUT Endpoint 0 Interrupt mask Bit
Set to 1 to unmask USB_DAINT.OUTEPINT0.
15:7 Reserved To ensure compatibility with future devices, always write bits to 0. More information in 2.1 Conven-
tions.
6 INEPMSK6 0 RW IN Endpoint 6 Interrupt mask Bit
Set to 1 to unmask USB_DAINT.INEPINT6.
5 INEPMSK5 0 RW IN Endpoint 5 Interrupt mask Bit
Set to 1 to unmask USB_DAINT.INEPINT5.
4 INEPMSK4 0 RW IN Endpoint 4 Interrupt mask Bit
Set to 1 to unmask USB_DAINT.INEPINT4.
3 INEPMSK3 0 RW IN Endpoint 3 Interrupt mask Bit
Set to 1 to unmask USB_DAINT.INEPINT3.
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Bit Name Reset Access Description
2 INEPMSK2 0 RW IN Endpoint 2 Interrupt mask Bit
Set to 1 to unmask USB_DAINT.INEPINT2.
1 INEPMSK1 0 RW IN Endpoint 1 Interrupt mask Bit
Set to 1 to unmask USB_DAINT.INEPINT1.
0 INEPMSK0 0 RW IN Endpoint 0 Interrupt mask Bit
Set to 1 to unmask USB_DAINT.INEPINT0.
15.6.47 USB_DVBUSDIS - Device VBUS Discharge Time Register
This register specifies the VBUS discharge time after VBUS pulsing during SRP.
Offset Bit Position
0x3C828
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
16
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
Reset
0x17D7
Access
RW
Name
DVBUSDIS
Bit Name Reset Access Description
31:16 Reserved To ensure compatibility with future devices, always write bits to 0. More information in 2.1 Conven-
tions.
15:0 DVBUSDIS 0x17D7 RW Device VBUS Discharge Time
Specifies the VBUS discharge time after VBUS pulsing during SRP. This value equals VBUS discharge time in PHY
clocks / 1024. Depending on your VBUS load, this value can need adjustment.
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15.6.48 USB_DVBUSPULSE - Device VBUS Pulsing Time Register
This register specifies the VBUS pulsing time during SRP.
Offset Bit Position
0x3C82
C
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
16
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
Reset
0x5B8
Access
RW
Name
DVBUSPULSE
Bit Name Reset Access Description
31:12 Reserved To ensure compatibility with future devices, always write bits to 0. More information in 2.1 Conven-
tions.
11:0 DVBUSPULSE 0x5B8 RW Device VBUS Pulsing Time
Specifies the VBUS pulsing time during SRP. This value equals VBUS pulsing time in PHY clocks / 1024.
15.6.49 USB_DIEPEMPMSK - Device IN Endpoint FIFO Empty Interrupt Mask Register
This register is used to control the IN endpoint FIFO empty interrupt generation (USB_DIEP0INT/USB_DIEPx_INT.TXFEMP).
Offset Bit Position
0x3C834
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
16
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
Reset
0x0000
Access
RW
Name
DIEPEMPMSK
Bit Name Reset Access Description
31:16 Reserved To ensure compatibility with future devices, always write bits to 0. More information in 2.1 Conven-
tions.
15:0 DIEPEMPMSK 0x0000 RW IN EP Tx FIFO Empty Interrupt Mask Bits
These bits acts as mask bits for USB_DIEP0INT.TXFEMP/USB_DIEPx_INT.TXFEMP interrupt. One bit per IN Endpoint: Bit
0 for IN EP 0, bit 6 for IN EP 6.
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15.6.50 USB_DIEP0CTL - Device IN Endpoint 0 Control Register
This section describes the Control IN Endpoint 0 Control register. Nonzero control endpoints use registers for endpoints 1 - 6.
Offset Bit Position
0x3C900
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
16
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
Reset
0
0
0
0
0x0
0
0x0
0
1
0x0
Access
RW1H
RW1H
W1
W1
RW
RW1H
R
R
R
RW
Name
EPENA
EPDIS
SNAK
CNAK
TXFNUM
STALL
EPTYPE
NAKSTS
USBACTEP
MPS
Bit Name Reset Access Description
31 EPENA 0 RW1H Endpoint Enable
In DMA mode this bit indicates that data is ready to be transmitted on the endpoint. The core clears this bit before setting
the following interrupts on this endpoint: Endpoint Disabled, Transfer Completed.
30 EPDIS 0 RW1H Endpoint Disable
The application sets this bit to stop transmitting data on an endpoint, even before the transfer for that endpoint is complete.
The application must wait for the Endpoint Disabled interrupt before treating the endpoint as disabled. The core clears this
bit before setting the Endpoint Disabled Interrupt. The application must set this bit only if Endpoint Enable is already set for
this endpoint.
29:28 Reserved To ensure compatibility with future devices, always write bits to 0. More information in 2.1 Conven-
tions.
27 SNAK 0 W1 Set NAK
A write to this bit sets the NAK bit for the endpoint. Using this bit, the application can control the transmission of NAK hand-
shakes on an endpoint. The core can also set this bit for an endpoint after a SETUP packet is received on that endpoint.
26 CNAK 0 W1 Clear NAK
A write to this bit clears the NAK bit for the endpoint.
25:22 TXFNUM 0x0 RW TxFIFO Number
This value is set to the FIFO number that is assigned to IN Endpoint 0.
21 STALL 0 RW1H Handshake
The application can only set this bit, and the core clears it, when a SETUP token is received for this endpoint. If a NAK bit,
Global Nonperiodic IN NAK, or Global OUT NAK is set along with this bit, the STALL bit takes priority.
20 Reserved To ensure compatibility with future devices, always write bits to 0. More information in 2.1 Conven-
tions.
19:18 EPTYPE 0x0 R Endpoint Type
Hardcoded to 0. Endpoint 0 is always a control endpoint.
17 NAKSTS 0 R NAK Status
When this bit is 0 the core is transmitting non-NAK handshakes based on the FIFO status. When this bit is 1 the core is
transmitting NAK handshakes on this endpoint. When this bit is set, either by the application or core, the core stops trans-
mitting data, even if there is data available in the TxFIFO. Irrespective of this bit's setting, the core always responds to SET-
UP data packets with an ACK handshake.
16 Reserved To ensure compatibility with future devices, always write bits to 0. More information in 2.1 Conven-
tions.
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Bit Name Reset Access Description
15 USBACTEP 1 R USB Active Endpoint
This bit is always 1, indicating that control endpoint 0 is always active in all configurations and interfaces.
14:2 Reserved To ensure compatibility with future devices, always write bits to 0. More information in 2.1 Conven-
tions.
1:0 MPS 0x0 RW Maximum Packet Size
The application must program this field with the maximum packet size for the current logical endpoint.
Value Mode Description
0 64B 64 bytes.
1 32B 32 bytes.
2 16B 16 bytes.
3 8B 8 bytes.
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15.6.51 USB_DIEP0INT - Device IN Endpoint 0 Interrupt Register
This register indicates the status of endpoint 0 with respect to USB- and AHB-related events. The application must read this register
when the IN Endpoints Interrupt bit of the Core Interrupt register (USB_GINTSTS.IEPINT) is set. Before the application can read this
register, it must first read the Device All Endpoints Interrupt (USB_DAINT) register to get the exact endpoint number for the Device
Endpoint Interrupt register. The application must clear the appropriate bit in this register to clear the corresponding bits in the
USB_DAINT and USB_GINTSTS registers.
Offset Bit Position
0x3C908
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
16
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
Reset
0
0
0
1
0
0
0
0
0
0
Access
RW1H
RW1H
RW1H
R
RW1H
RW1H
RW1H
RW1H
RW1H
RW1H
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Offset Bit Position
Name
NAKINTRPT
BBLEERR
PKTDRPSTS
TXFEMP
INEPNAKEFF
INTKNTXFEMP
TIMEOUT
AHBERR
EPDISBLD
XFERCOMPL
Bit Name Reset Access Description
31:14 Reserved To ensure compatibility with future devices, always write bits to 0. More information in 2.1 Conven-
tions.
13 NAKINTRPT 0 RW1H NAK Interrupt
The core generates this interrupt when a NAK is transmitted or received by the device. In case of isochronous IN endpoints
the interrupt gets generated when a zero length packet is transmitted due to un-availability of data in the TXFifo.
12 BBLEERR 0 RW1H NAK Interrupt
The core generates this interrupt when babble is received for the endpoint.
11 PKTDRPSTS 0 RW1H Packet Drop Status
This bit indicates to the application that an ISO OUT packet has been dropped. This bit does not have an associated mask
bit and does not generate an interrupt.
10:8 Reserved To ensure compatibility with future devices, always write bits to 0. More information in 2.1 Conven-
tions.
7 TXFEMP 1 R Transmit FIFO Empty
This interrupt is asserted when the TxFIFO for this endpoint is either half or completely empty. The half or completely empty
status is determined by the TxFIFO Empty Level bit in the Core AHB Configuration register
(USB_GAHBCFG.NPTXFEMPLVL).
6 INEPNAKEFF 0 RW1H IN Endpoint NAK Effective
Applies to periodic IN endpoints only. This bit can be cleared when the application clears the IN endpoint NAK by writing to
USB_DIEP0CTL.CNAK. This interrupt indicates that the core has sampled the NAK bit set (either by the application or by
the core). The interrupt indicates that the IN endpoint NAK bit set by the application has taken effect in the core. This inter-
rupt does not guarantee that a NAK handshake is sent on the USB. A STALL bit takes priority over a NAK bit.
5 Reserved To ensure compatibility with future devices, always write bits to 0. More information in 2.1 Conven-
tions.
4 INTKNTXFEMP 0 RW1H IN Token Received When TxFIFO is Empty
Indicates that an IN token was received when the associated TxFIFO (periodic/non-periodic) was empty. This interrupt is
asserted on the endpoint for which the IN token was received.
3 TIMEOUT 0 RW1H Timeout Condition
Indicates that the core has detected a timeout condition on the USB for the last IN token on this endpoint.
2 AHBERR 0 RW1H AHB Error
This is generated in DMA mode when there is an AHB error during an AHB read/write. The application can read the corre-
sponding endpoint DMA address register to get the error address.
1 EPDISBLD 0 RW1H Endpoint Disabled Interrupt
This bit indicates that the endpoint is disabled per the application's request.
0 XFERCOMPL 0 RW1H Transfer Completed Interrupt
This field indicates that the programmed transfer is complete on the AHB as well as on the USB, for this endpoint.
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15.6.52 USB_DIEP0TSIZ - Device IN Endpoint 0 Transfer Size Register
The application must modify this register before enabling endpoint 0. Once endpoint 0 is enabled using Endpoint Enable bit of the De-
vice Control Endpoint 0 Control register (USB_DIEP0CTL.EPENA), the core modifies this register. The application can only read this
register once the core has cleared the Endpoint Enable bit. Nonzero endpoints use the registers for endpoints 1-6.
Offset Bit Position
0x3C910
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
16
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
Reset
0x0
0x00
Access
RW
RW
Name
PKTCNT
XFERSIZE
Bit Name Reset Access Description
31:21 Reserved To ensure compatibility with future devices, always write bits to 0. More information in 2.1 Conven-
tions.
20:19 PKTCNT 0x0 RW Packet Count
Indicates the total number of USB packets that constitute the Transfer Size amount of data for endpoint 0. This field is de-
cremented every time a packet (maximum size or short packet) is read from the TxFIFO.
18:7 Reserved To ensure compatibility with future devices, always write bits to 0. More information in 2.1 Conven-
tions.
6:0 XFERSIZE 0x00 RW Transfer Size
Indicates the transfer size in bytes for endpoint 0. The core interrupts the application only after it has exhausted the transfer
size amount of data. The transfer size can be set to the maximum packet size of the endpoint, to be interrupted at the end
of each packet. The core decrements this field every time a packet from the external memory is written to the TxFIFO.
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15.6.53 USB_DIEP0DMAADDR - Device IN Endpoint 0 DMA Address Register
Offset Bit Position
0x3C914
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
16
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
Reset
0xXXXXXXXX
Access
RW
Name
DIEP0DMAADDR
Bit Name Reset Access Description
31:0 DIEP0DMAADDR 0xXXXXXXX
X
RW DMA Address
Holds the start address of the external memory for fetching endpoint data. For control endpoints, this field stores control
OUT data packets as well as SETUP transaction data packets. When more than three SETUP packets are received back-
to-back, the SETUP data packet in the memory is overwritten. This register is incremented on every AHB transaction. The
application can give only a DWORD-aligned address. The data for this register field is stored in RAM. Thus, the reset value
is undefined (X).
15.6.54 USB_DIEP0TXFSTS - Device IN Endpoint 0 Transmit FIFO Status Register
This read-only register contains the free space information for the Device IN endpoint 0 TxFIFO.
Offset Bit Position
0x3C918
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
16
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
Reset
0x0200
Access
R
Name
SPCAVAIL
Bit Name Reset Access Description
31:16 Reserved To ensure compatibility with future devices, always write bits to 0. More information in 2.1 Conven-
tions.
15:0 SPCAVAIL 0x0200 R TxFIFO Space Available
Indicates the amount of free space available in the Endpoint TxFIFO. Values are in terms of 32-bit words.
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15.6.55 USB_DIEPx_CTL - Device IN Endpoint x+1 Control Register
The application uses this register to control the behavior of each logical endpoint other than endpoint 0.
Offset Bit Position
0x3C920
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
16
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
Reset
0
0
0
0
0
0
0x0
0
0x0
0
0
0
0x000
Access
RW1H
RW1H
W1
W1
W1
W1
RW
RW1H
RW
R
R
RW
RW
Name
EPENA
EPDIS
SETD1PIDOF
SETD0PIDEF
SNAK
CNAK
TXFNUM
STALL
EPTYPE
NAKSTS
DPIDEOF
USBACTEP
MPS
Bit Name Reset Access Description
31 EPENA 0 RW1H Endpoint Enable
In DMA mode for IN endpoints, this bit indicates that data is ready to be transmitted on the endpoint. The core clears this bit
before setting any of the following interrupts on this endpoint: SETUP Phase Done, Endpoint Disabled, Transfer Comple-
ted. For control endpoints in DMA mode, this bit must be set to be able to transfer SETUP data packets in memory.
30 EPDIS 0 RW1H Endpoint Disable
The application sets this bit to stop transmitting/receiving data on an endpoint, even before the transfer for that endpoint is
complete. The application must wait for the Endpoint Disabled interrupt before treating the endpoint as disabled. The core
clears this bit before setting the Endpoint Disabled interrupt. The application must set this bit only if Endpoint Enable is al-
ready set for this endpoint.
29 SETD1PIDOF 0 W1 Set DATA1 PID / Odd Frame
For bulk and interrupt endpoints writing this field sets the Endpoint Data PID / Even or Odd Frame (DPIDEOF) field in this
register to DATA1ODD.
For isochronous endpoints writing this field sets the Endpoint Data PID / Even or Odd Frame (DPIDEOF) field to odd (DA-
TA1ODD).
28 SETD0PIDEF 0 W1 Set DATA0 PID / Even Frame
For bulk and interrupt endpoints writing this field sets the Endpoint Data PID / Even or Odd Frame (DPIDEOF) field in this
register to DATA0EVEN.
For isochronous endpoints writing this field sets the Endpoint Data PID / Even or Odd Frame (DPIDEOF) field to odd (DA-
TA0EVEN).
27 SNAK 0 W1 Set NAK
A write to this bit sets the NAK bit for the endpoint. Using this bit, the application can control the transmission of NAK hand-
shakes on an endpoint. The core can also set this bit for an endpoint after a SETUP packet is received on that endpoint.
26 CNAK 0 W1 Clear NAK
A write to this bit clears the NAK bit for the endpoint.
25:22 TXFNUM 0x0 RW TxFIFO Number
These bits specify the FIFO number associated with this endpoint. Each active IN endpoint must be programmed to a sepa-
rate FIFO number. This field is valid only for IN endpoints.
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Bit Name Reset Access Description
21 STALL 0 RW1H Handshake
For bulk and interrupt endpoints: The application sets this bit to stall all tokens from the USB host to this endpoint. If a NAK
bit, Global Non-periodic IN NAK, or Global OUT NAK is set along with this bit, the STALL bit takes priority. In this case only
the application can clear this bit, never the core.
When control endpoint: The application can only set this bit, and the core clears it, when a SETUP token is received for this
endpoint. If a NAK bit, Global Non-periodic IN NAK, or Global OUT NAK is set along with this bit, the STALL bit takes priori-
ty. Irrespective of this bit's setting, the core always responds to SETUP data packets with an ACK handshake.
20 Reserved To ensure compatibility with future devices, always write bits to 0. More information in 2.1 Conven-
tions.
19:18 EPTYPE 0x0 RW Endpoint Type
This is the transfer type supported by this logical endpoint.
Value Mode Description
0 CONTROL Control Endpoint.
1 ISO Isochronous Endpoint.
2 BULK Bulk Endpoint.
3 INT Interrupt Endpoint.
17 NAKSTS 0 R NAK Status
When this bit is 0 the core is transmitting non-NAK handshakes based on the FIFO status. When this bit is 1 the core is
transmitting NAK handshakes on this endpoint. When either the application or the core sets this bit the core stops receiving
any data on an OUT endpoint, even if there is space in the RxFIFO to accommodate the incoming packet. For non-isochro-
nous IN endpoints the core stops transmitting any data on an IN endpoint, even if there data is available in the TxFIFO. For
isochronous IN endpoints the core sends out a zero-length data packet, even if there data is available in the TxFIFO. Irre-
spective of this bit's setting, the core always responds to SETUP data packets with an ACK handshake.
16 DPIDEOF 0 R Endpoint Data PID / Even or Odd Frame
For interrupt/bulk endpoints this field contains the PID of the packet to be received or transmitted on this endpoint. The
application must program the PID of the first packet to be received or transmitted on this endpoint, after the endpoint is
activated. The applications use the SETD1PIDOF and SETD0PIDEF fields of this register to program either DATA0 or DA-
TA1 PID. For isochronous endpoints, this field indicates the frame number in which the core transmits/receives isochronous
data for this endpoint. The application must program the even/odd frame number in which it intends to transmit/receive iso-
chronous data for this endpoint using the SETD0PIDEF and SETD1PIDOF fields in this register.
Value Mode Description
0 DATA0EVEN DATA0 PID / Even Frame.
1 DATA1ODD DATA1 PID / Odd Frame.
15 USBACTEP 0 RW USB Active Endpoint
Indicates whether this endpoint is active in the current configuration and interface. The core clears this bit for all endpoints
after detecting a USB reset. After receiving the SetConfiguration and SetInterface commands, the application must program
endpoint registers accordingly and set this bit.
14:11 Reserved To ensure compatibility with future devices, always write bits to 0. More information in 2.1 Conven-
tions.
10:0 MPS 0x000 RW Maximum Packet Size
The application must program this field with the maximum packet size for the current logical endpoint. This value is in bytes.
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15.6.56 USB_DIEPx_INT - Device IN Endpoint x+1 Interrupt Register
This register indicates the status of an endpoint with respect to USB- and AHB-related events. The application must read this register
when the IN Endpoints Interrupt bit of the Core Interrupt register (USB_GINTSTS.IEPINT) is set. Before the application can read this
register, it must first read the Device All Endpoints Interrupt (USB_DAINT) register to get the exact endpoint number for the Device
Endpoint x+1 Interrupt register. The application must clear the appropriate bit in this register to clear the corresponding bits in the
USB_DAINT and USB_GINTSTS registers.
Offset Bit Position
0x3C928
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
16
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
Reset
0
0
0
1
0
0
0
0
0
0
Access
RW1H
RW1H
RW1H
R
RW1H
RW1H
RW1H
RW1H
RW1H
RW1H
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Offset Bit Position
Name
NAKINTRPT
BBLEERR
PKTDRPSTS
TXFEMP
INEPNAKEFF
INTKNTXFEMP
TIMEOUT
AHBERR
EPDISBLD
XFERCOMPL
Bit Name Reset Access Description
31:14 Reserved To ensure compatibility with future devices, always write bits to 0. More information in 2.1 Conven-
tions.
13 NAKINTRPT 0 RW1H NAK Interrupt
The core generates this interrupt when a NAK is transmitted or received by the device. In case of isochronous IN endpoints
the interrupt gets generated when a zero length packet is transmitted due to un-availability of data in the TXFifo.
12 BBLEERR 0 RW1H NAK Interrupt
The core generates this interrupt when babble is received for the endpoint.
11 PKTDRPSTS 0 RW1H Packet Drop Status
This bit indicates to the application that an ISO OUT packet has been dropped. This bit does not have an associated mask
bit and does not generate an interrupt.
10:8 Reserved To ensure compatibility with future devices, always write bits to 0. More information in 2.1 Conven-
tions.
7 TXFEMP 1 R Transmit FIFO Empty
This interrupt is asserted when the TxFIFO for this endpoint is either half or completely empty. The half or completely empty
status is determined by the TxFIFO Empty Level bit in the Core AHB Configuration register
(USB_GAHBCFG.NPTXFEMPLVL).
6 INEPNAKEFF 0 RW1H IN Endpoint NAK Effective
Applies to periodic IN endpoints only. This bit can be cleared when the application clears the IN endpoint NAK by writing to
USB_DIEPx_CTL.CNAK. This interrupt indicates that the core has sampled the NAK bit set (either by the application or by
the core). The interrupt indicates that the IN endpoint NAK bit set by the application has taken effect in the core. This inter-
rupt does not guarantee that a NAK handshake is sent on the USB. A STALL bit takes priority over a NAK bit.
5 Reserved To ensure compatibility with future devices, always write bits to 0. More information in 2.1 Conven-
tions.
4 INTKNTXFEMP 0 RW1H IN Token Received When TxFIFO is Empty
Applies to non-periodic IN endpoints only. Indicates that an IN token was received when the associated TxFIFO (periodic/
non-periodic) was empty. This interrupt is asserted on the endpoint for which the IN token was received.
3 TIMEOUT 0 RW1H Timeout Condition
Applies only to Control IN endpoints. Indicates that the core has detected a timeout condition on the USB for the last IN
token on this endpoint.
2 AHBERR 0 RW1H AHB Error
This is generated only in DMA mode when there is an AHB error during an AHB read/write. The application can read the
corresponding endpoint DMA address register to get the error address.
1 EPDISBLD 0 RW1H Endpoint Disabled Interrupt
This bit indicates that the endpoint is disabled per the application's request.
0 XFERCOMPL 0 RW1H Transfer Completed Interrupt
This field indicates that the programmed transfer is complete on the AHB as well as on the USB, for this endpoint.
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15.6.57 USB_DIEPx_TSIZ - Device IN Endpoint x+1 Transfer Size Register
The application must modify this register before enabling the endpoint. Once the endpoint is enabled using Endpoint Enable bit of the
Device Endpoint x+1 Control register (USB_DIEPx_CTL.EPENA), the core modifies this register. The application can only read this reg-
ister once the core has cleared the Endpoint Enable bit.
Offset Bit Position
0x3C930
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
16
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
Reset
0x0
0x000
0x00000
Access
RW
RW
RW
Name
MC
PKTCNT
XFERSIZE
Bit Name Reset Access Description
31 Reserved To ensure compatibility with future devices, always write bits to 0. More information in 2.1 Conven-
tions.
30:29 MC 0x0 RW Multi Count
For periodic IN endpoints, this field indicates the number of packets that must be transmitted per frame on the USB. The
core uses this field to calculate the data PID for isochronous IN endpoints.
28:19 PKTCNT 0x000 RW Packet Count
Indicates the total number of USB packets that constitute the Transfer Size amount of data. This field is decremented every
time a packet (maximum size or short packet) is read from the TxFIFO.
18:0 XFERSIZE 0x00000 RW Transfer Size
Indicates the transfer size in bytes. The core interrupts the application only after it has exhausted the transfer size amount
of data. The transfer size can be set to the maximum packet size of the endpoint, to be interrupted at the end of each pack-
et. The core decrements this field every time a packet from the external memory is written to the TxFIFO.
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15.6.58 USB_DIEPx_DMAADDR - Device IN Endpoint x+1 DMA Address Register
Offset Bit Position
0x3C934
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
16
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
Reset
0xXXXXXXXX
Access
RW
Name
DMAADDR
Bit Name Reset Access Description
31:0 DMAADDR 0xXXXXXXX
X
RW DMA Address
Holds the start address of the external memory for fetching endpoint data. For control endpoints, this field stores control
OUT data packets as well as SETUP transaction data packets. When more than three SETUP packets are received back-
to-back, the SETUP data packet in the memory is overwritten. This register is incremented on every AHB transaction. The
application can give only a DWORD-aligned address. The data for this register field is stored in RAM. Thus, the reset value
is undefined (X).
15.6.59 USB_DIEPx_TXFSTS - Device IN Endpoint x+1 Transmit FIFO Status Register
This read-only register contains the free space information for the Device IN endpoint TxFIFO.
Offset Bit Position
0x3C938
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
16
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
Reset
0x0200
Access
R
Name
SPCAVAIL
Bit Name Reset Access Description
31:16 Reserved To ensure compatibility with future devices, always write bits to 0. More information in 2.1 Conven-
tions.
15:0 SPCAVAIL 0x0200 R TxFIFO Space Available
Indicates the amount of free space available in the Endpoint TxFIFO. Values are in terms of 32-bit words.
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15.6.60 USB_DOEP0CTL - Device OUT Endpoint 0 Control Register
The application uses this register to control the behavior of each logical endpoint other than endpoint 0.
Offset Bit Position
0x3CB0
0
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
16
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
Reset
0
0
0
0
0
0
0x0
0
1
0x0
Access
RW1H
R
W1
W1
RW1H
RW
R
R
R
R
Name
EPENA
EPDIS
SNAK
CNAK
STALL
SNP
EPTYPE
NAKSTS
USBACTEP
MPS
Bit Name Reset Access Description
31 EPENA 0 RW1H Endpoint Enable
In DMA mode this bit indicates that the application has allocated the memory to start receiving data from the USB. The core
clears this bit before setting any of the following interrupts on this endpoint: SETUP Phase Done, Endpoint Disabled, Trans-
fer Completed. In DMA mode, this bit must be set for the core to transfer SETUP data packets into memory.
30 EPDIS 0 R Endpoint Disable
This bit is always 0. The application cannot disable control OUT endpoint 0.
29:28 Reserved To ensure compatibility with future devices, always write bits to 0. More information in 2.1 Conven-
tions.
27 SNAK 0 W1 Set NAK
A write to this bit sets the NAK bit for the endpoint. Using this bit, the application can control the transmission of NAK hand-
shakes on an endpoint. The core can also set bit on a Transfer Completed interrupt, or after a SETUP is received on the
endpoint.
26 CNAK 0 W1 Clear NAK
A write to this bit clears the NAK bit for the endpoint.
25:22 Reserved To ensure compatibility with future devices, always write bits to 0. More information in 2.1 Conven-
tions.
21 STALL 0 RW1H Handshake
The application can only set this bit, and the core clears it, when a SETUP token is received for this endpoint. If a NAK bit
or Global OUT NAK is set along with this bit, the STALL bit takes priority. Irrespective of this bit's setting, the core always
responds to SETUP data packets with an ACK handshake.
20 SNP 0 RW Snoop Mode
This bit configures the endpoint to Snoop mode. In Snoop mode, the core does not check the correctness of OUT packets
before transferring them to application memory.
19:18 EPTYPE 0x0 R Endpoint Type
Hardcoded to 0. Endpoint 0 is always a control endpoint.
17 NAKSTS 0 R NAK Status
When this bit is 0 the core is transmitting non-NAK handshakes based on the FIFO status. When this bit is 1 the core is
transmitting NAK handshakes on this endpoint. When either the application or the core sets this bit, the core stops receiving
data, even if there is space in the RxFIFO to accommodate the incoming packet. Irrespective of this bit's setting, the core
always responds to SETUP data packets with an ACK handshake.
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Bit Name Reset Access Description
16 Reserved To ensure compatibility with future devices, always write bits to 0. More information in 2.1 Conven-
tions.
15 USBACTEP 1 R USB Active Endpoint
This bit is always 1, indicating that a control endpoint 0 is always active in all configurations and interfaces.
14:2 Reserved To ensure compatibility with future devices, always write bits to 0. More information in 2.1 Conven-
tions.
1:0 MPS 0x0 R Maximum Packet Size
The maximum packet size for control OUT endpoint 0 is the same as what is programmed in control IN Endpoint 0.
Value Mode Description
0 64B 64 bytes.
1 32B 32 bytes.
2 16B 16 bytes.
3 8B 8 bytes.
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15.6.61 USB_DOEP0INT - Device OUT Endpoint 0 Interrupt Register
This register indicates the status of endpoint 0 with respect to USB- and AHB-related events. The application must read this register
when the OUT Endpoints Interrupt bit of the Core Interrupt register (USB_GINTSTS.OEPINT) is set. Before the application can read
this register, it must first read the Device All Endpoints Interrupt (USB_DAINT) register to get the exact endpoint number for the Device
Endpoint Interrupt register. The application must clear the appropriate bit in this register to clear the corresponding bits in the
USB_DAINT and USB_GINTSTS registers.
Offset Bit Position
0x3CB0
8
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
16
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
Reset
0
0
0
0
0
0
0
0
0
Access
RW1H
RW1H
RW1H
RW1H
RW1H
RW1H
RW1H
RW1H
RW1H
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Offset Bit Position
Name
NAKINTRPT
BBLEERR
PKTDRPSTS
BACK2BACKSETUP
OUTTKNEPDIS
SETUP
AHBERR
EPDISBLD
XFERCOMPL
Bit Name Reset Access Description
31:14 Reserved To ensure compatibility with future devices, always write bits to 0. More information in 2.1 Conven-
tions.
13 NAKINTRPT 0 RW1H NAK Interrupt
The core generates this interrupt when a NAK is transmitted or received by the device. In case of isochronous IN endpoints
the interrupt gets generated when a zero length packet is transmitted due to un-availability of data in the TXFifo.
12 BBLEERR 0 RW1H NAK Interrupt
The core generates this interrupt when babble is received for the endpoint.
11 PKTDRPSTS 0 RW1H Packet Drop Status
This bit indicates to the application that an ISO OUT packet has been dropped. This bit does not have an associated mask
bit and does not generate an interrupt.
10:7 Reserved To ensure compatibility with future devices, always write bits to 0. More information in 2.1 Conven-
tions.
6 BACK2BACKSETUP 0 RW1H Back-to-Back SETUP Packets Received
This bit indicates that the core has received more than three back-to-back SETUP packets for this particular endpoint.
5 Reserved To ensure compatibility with future devices, always write bits to 0. More information in 2.1 Conven-
tions.
4 OUTTKNEPDIS 0 RW1H OUT Token Received When Endpoint Disabled
Indicates that an OUT token was received when the endpoint was not yet enabled. This interrupt is asserted on the end-
point for which the OUT token was received.
3 SETUP 0 RW1H Setup Phase Done
Indicates that the SETUP phase for the control endpoint is complete and no more back-to-back SETUP packets were re-
ceived for the current control transfer. On this interrupt, the application can decode the received SETUP data packet.
2 AHBERR 0 RW1H AHB Error
This is generated only in DMA mode when there is an AHB error during an AHB read/write. The application can read the
corresponding endpoint DMA address register to get the error address.
1 EPDISBLD 0 RW1H Endpoint Disabled Interrupt
This bit indicates that the endpoint is disabled per the application's request.
0 XFERCOMPL 0 RW1H Transfer Completed Interrupt
This field indicates that the programmed transfer is complete on the AHB as well as on the USB, for this endpoint.
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15.6.62 USB_DOEP0TSIZ - Device OUT Endpoint 0 Transfer Size Register
The application must modify this register before enabling the endpoint. Once the endpoint is enabled using Endpoint Enable bit of the
Device Endpoint x+1 Control register (USB_DOEPx_CTL.EPENA), the core modifies this register. The application can only read this
register once the core has cleared the Endpoint Enable bit.
Offset Bit Position
0x3CB1
0
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
16
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
Reset
0x0
0
0x00
Access
RW
RW
RW
Name
SUPCNT
PKTCNT
XFERSIZE
Bit Name Reset Access Description
31 Reserved To ensure compatibility with future devices, always write bits to 0. More information in 2.1 Conven-
tions.
30:29 SUPCNT 0x0 RW SETUP Packet Count
This field specifies the number of back-to-back SETUP data packets the endpoint can receive.
28:20 Reserved To ensure compatibility with future devices, always write bits to 0. More information in 2.1 Conven-
tions.
19 PKTCNT 0 RW Packet Count
This field is decremented to zero after a packet is written into the RxFIFO.
18:7 Reserved To ensure compatibility with future devices, always write bits to 0. More information in 2.1 Conven-
tions.
6:0 XFERSIZE 0x00 RW Transfer Size
Indicates the transfer size in bytes for endpoint 0. The core interrupts the application only after it has exhausted the transfer
size amount of data. The transfer size can be set to the maximum packet size of the endpoint, to be interrupted at the end
of each packet. The core decrements this field every time a packet is read from the RxFIFO and written to the external
memory.
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15.6.63 USB_DOEP0DMAADDR - Device OUT Endpoint 0 DMA Address Register
Offset Bit Position
0x3CB1
4
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
16
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
Reset
0xXXXXXXXX
Access
RW
Name
DOEP0DMAADDR
Bit Name Reset Access Description
31:0 DOEP0DMAADDR 0xXXXXXXX
X
RW DMA Address
Holds the start address of the external memory for storing endpoint data. For control endpoints, this field stores control
OUT data packets as well as SETUP transaction data packets. When more than three SETUP packets are received back-
to-back, the SETUP data packet in the memory is overwritten. This register is incremented on every AHB transaction. The
application can give only a DWORD-aligned address. The data for this register field is stored in RAM. Thus, the reset value
is undefined (X).
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15.6.64 USB_DOEPx_CTL - Device OUT Endpoint x+1 Control Register
The application uses this register to control the behavior of each logical endpoint other than endpoint 0.
Offset Bit Position
0x3CB2
0
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
16
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
Reset
0
0
0
0
0
0
0
0
0x0
0
0
0
0x000
Access
RW1H
RW1H
W1
W1
W1
W1
RW1H
RW
RW
R
R
RW
RW
Name
EPENA
EPDIS
SETD1PIDOF
SETD0PIDEF
SNAK
CNAK
STALL
SNP
EPTYPE
NAKSTS
DPIDEOF
USBACTEP
MPS
Bit Name Reset Access Description
31 EPENA 0 RW1H Endpoint Enable
In DMA mode this bit indicates that the application has allocated the memory to start receiving data from the USB. The core
clears this bit before setting any of the following interrupts on this endpoint: SETUP Phase Done, Endpoint Disabled, Trans-
fer Completed. For control endpoints in DMA mode, this bit must be set to be able to transfer SETUP data packets in mem-
ory.
30 EPDIS 0 RW1H Endpoint Disable
The application sets this bit to stop transmitting/receiving data on an endpoint, even before the transfer for that endpoint is
complete. The application must wait for the Endpoint Disabled interrupt before treating the endpoint as disabled. The core
clears this bit before setting the Endpoint Disabled interrupt. The application must set this bit only if Endpoint Enable is al-
ready set for this endpoint.
29 SETD1PIDOF 0 W1 Set DATA1 PID / Odd Frame
For bulk and interrupt endpoints writing this field sets the Endpoint Data PID / Even or Odd Frame (DPIDEOF) field in this
register to DATA1ODD. For isochronous endpoints writing this field sets the Endpoint Data PID / Even or Odd Frame (DPI-
DEOF) field to odd (DATA1ODD).
28 SETD0PIDEF 0 W1 Set DATA0 PID / Even Frame
For bulk and interrupt endpoints writing this field sets the Endpoint Data PID / Even or Odd Frame (DPIDEOF) field in this
register to DATA0EVEN. For isochronous endpoints writing this field sets the Endpoint Data PID / Even or Odd Frame
(DPIDEOF) field to odd (DATA0EVEN).
27 SNAK 0 W1 Set NAK
A write to this bit sets the NAK bit for the endpoint. Using this bit, the application can control the transmission of NAK hand-
shakes on an endpoint. The core can also set this bit for an endpoint after a SETUP packet is received on that endpoint.
26 CNAK 0 W1 Clear NAK
A write to this bit clears the NAK bit for the endpoint.
25:22 Reserved To ensure compatibility with future devices, always write bits to 0. More information in 2.1 Conven-
tions.
21 STALL 0 RW1H STALL Handshake
For non-control, non-isochronous endpoints: The application sets this bit to stall all tokens from the USB host to this end-
point. If a NAK bit, Global Non-periodic IN NAK, or Global OUT NAK is set along with this bit, the STALL bit takes priority.
Only the application can clear this bit, never the core.
For control endpoints: The application can only set this bit, and the core clears it, when a SETUP token is received for this
endpoint. If a NAK bit, Global Non-periodic IN NAK, or Global OUT NAK is set along with this bit, the STALL bit takes priori-
ty. Irrespective of this bit's setting, the core always responds to SETUP data packets with an ACK handshake.
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Bit Name Reset Access Description
20 SNP 0 RW Snoop Mode
This bit configures the endpoint to Snoop mode. In Snoop mode, the core does not check the correctness of OUT packets
before transferring them to application memory.
19:18 EPTYPE 0x0 RW Endpoint Type
This is the transfer type supported by this logical endpoint.
Value Mode Description
0 CONTROL Control Endpoint.
1 ISO Isochronous Endpoint.
2 BULK Bulk Endpoint.
3 INT Interrupt Endpoint.
17 NAKSTS 0 R NAK Status
When this bit is 0 the core is transmitting non-NAK handshakes based on the FIFO status. When this bit is 1 the core is
transmitting NAK handshakes on this endpoint. When either the application or the core sets this bit the core stops receiving
any data on an OUT endpoint, even if there is space in the RxFIFO to accommodate the incoming packet. Irrespective of
this bit's setting, the core always responds to SETUP data packets with an ACK handshake.
16 DPIDEOF 0 R Endpoint Data PID / Even-odd Frame
For interrupt/bulk endpoints: Contains the PID of the packet to be received or transmitted on this endpoint. The application
must program the PID of the first packet to be received or transmitted on this endpoint, after the endpoint is activated. The
application use the SETD1PIDOF and SETD0PIDEF fields of this register to program either DATA0 or DATA1 PID.
For isochronous endpoints: Indicates the frame number in which the core transmits/receives isochronous data for this end-
point. The application must program the even/odd frame number in which it intends to transmit/receive isochronous data for
this endpoint using the SETD1PIDOF and SETD0PIDEF fields in this register.
Value Mode Description
0 DATA0EVEN DATA0 PID / Even Frame.
1 DATA1ODD DATA1 PID / Odd Frame.
15 USBACTEP 0 RW USB Active Endpoint
Indicates whether this endpoint is active in the current configuration and interface. The core clears this bit for all endpoints
after detecting a USB reset. After receiving the SetConfiguration and SetInterface commands, the application must program
endpoint registers accordingly and set this bit.
14:11 Reserved To ensure compatibility with future devices, always write bits to 0. More information in 2.1 Conven-
tions.
10:0 MPS 0x000 RW Maximum Packet Size
The application must program this field with the maximum packet size for the current logical endpoint. This value is in bytes.
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15.6.65 USB_DOEPx_INT - Device OUT Endpoint x+1 Interrupt Register
This register indicates the status of an endpoint with respect to USB- and AHB-related events. The application must read this register
when the OUT Endpoints Interrupt bit of the Core Interrupt register (USB_GINTSTS.OEPINT) is set. Before the application can read
this register, it must first read the Device All Endpoints Interrupt (USB_DAINT) register to get the exact endpoint number for the Device
Endpoint Interrupt register. The application must clear the appropriate bit in this register to clear the corresponding bits in the
USB_DAINT and USB_GINTSTS registers.
Offset Bit Position
0x3CB2
8
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
16
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
Reset
0
0
0
0
0
0
0
0
0
Access
RW1H
RW1H
RW1H
RW1H
RW1H
RW1H
RW1H
RW1H
RW1H
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Offset Bit Position
Name
NAKINTRPT
BBLEERR
PKTDRPSTS
BACK2BACKSETUP
OUTTKNEPDIS
SETUP
AHBERR
EPDISBLD
XFERCOMPL
Bit Name Reset Access Description
31:14 Reserved To ensure compatibility with future devices, always write bits to 0. More information in 2.1 Conven-
tions.
13 NAKINTRPT 0 RW1H NAK Interrupt
The core generates this interrupt when a NAK is transmitted or received by the device.
12 BBLEERR 0 RW1H Babble Error
The core generates this interrupt when babble is received for the endpoint.
11 PKTDRPSTS 0 RW1H Packet Drop Status
This bit indicates to the application that an ISO OUT packet has been dropped. This bit does not have an associated mask
bit and does not generate an interrupt.
10:7 Reserved To ensure compatibility with future devices, always write bits to 0. More information in 2.1 Conven-
tions.
6 BACK2BACKSETUP 0 RW1H Back-to-Back SETUP Packets Received
Applies to Control OUT endpoints only. This bit indicates that the core has received more than three back-to-back SETUP
packets for this particular endpoint.
5 Reserved To ensure compatibility with future devices, always write bits to 0. More information in 2.1 Conven-
tions.
4 OUTTKNEPDIS 0 RW1H OUT Token Received When Endpoint Disabled
Applies only to control OUT endpoints. Indicates that an OUT token was received when the endpoint was not yet enabled.
This interrupt is asserted on the endpoint for which the OUT token was received.
3 SETUP 0 RW1H Setup Phase Done
Applies to control OUT endpoints only. Indicates that the SETUP phase for the control endpoint is complete and no more
back-to-back SETUP packets were received for the current control transfer. On this interrupt, the application can decode
the received SETUP data packet.
2 AHBERR 0 RW1H AHB Error
This is generated only in DMA mode when there is an AHB error during an AHB read/write. The application can read the
corresponding endpoint DMA address register to get the error address.
1 EPDISBLD 0 RW1H Endpoint Disabled Interrupt
This bit indicates that the endpoint is disabled per the application's request.
0 XFERCOMPL 0 RW1H Transfer Completed Interrupt
This field indicates that the programmed transfer is complete on the AHB as well as on the USB, for this endpoint.
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15.6.66 USB_DOEPx_TSIZ - Device OUT Endpoint x+1 Transfer Size Register
The application must modify this register before enabling the endpoint. Once the endpoint is enabled using Endpoint Enable bit of the
Device Endpoint x+1 Control register (USB_DOEPx_CTL.EPENA), the core modifies this register. The application can only read this
register once the core has cleared the Endpoint Enable bit.
Offset Bit Position
0x3CB3
0
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
16
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
Reset
0x0
0x000
0x00000
Access
R
RW
RW
Name
RXDPIDSUPCNT
PKTCNT
XFERSIZE
Bit Name Reset Access Description
31 Reserved To ensure compatibility with future devices, always write bits to 0. More information in 2.1 Conven-
tions.
30:29 RXDPIDSUPCNT 0x0 R Receive Data PID / SETUP Packet Count
For isochronous OUT endpoints: This is the data PID received in the last packet for this endpoint.
For control OUT Endpoints: This field specifies the number of back-to-back SETUP data packets the endpoint can receive.
Value Mode Description
0 DATA0 DATA0 PID.
1 DATA2 DATA2 PID / 1 Packet.
2 DATA1 DATA1 PID / 2 Packets.
3 MDATA MDATA PID / 3 Packets.
28:19 PKTCNT 0x000 RW Packet Count
This field is decremented to zero after a packet is written into the RxFIFO.
18:0 XFERSIZE 0x00000 RW Transfer Size
Indicates the transfer size in bytes. The core interrupts the application only after it has exhausted the transfer size amount
of data. The transfer size can be set to the maximum packet size of the endpoint, to be interrupted at the end of each pack-
et. The core decrements this field every time a packet is read from the RxFIFO and written to the external memory.
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15.6.67 USB_DOEPx_DMAADDR - Device OUT Endpoint x+1 DMA Address Register
Offset Bit Position
0x3CB3
4
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
16
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
Reset
0xXXXXXXXX
Access
RW
Name
DMAADDR
Bit Name Reset Access Description
31:0 DMAADDR 0xXXXXXXX
X
RW DMA Address
Holds the start address of the external memory for storing endpoint data. For control endpoints, this field stores control
OUT data packets as well as SETUP transaction data packets. When more than three SETUP packets are received back-
to-back, the SETUP data packet in the memory is overwritten. This register is incremented on every AHB transaction. The
application can give only a DWORD-aligned address. The data for this register field is stored in RAM. Thus, the reset value
is undefined (X).
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15.6.68 USB_PCGCCTL - Power and Clock Gating Control Register
This register is available in Host and Device modes. The application use this register to control the core's power-down and clock gating
features.
Offset Bit Position
0x3CE0
0
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
16
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
Reset
0
0
0
0
0
0
Access
R
R
RW
RW
RW
RW
Name
RESETAFTERSUSP
PHYSLEEP
RSTPDWNMODULE
PWRCLMP
GATEHCLK
STOPPCLK
Bit Name Reset Access Description
31:9 Reserved To ensure compatibility with future devices, always write bits to 0. More information in 2.1 Conven-
tions.
8 RESETAFTERSUSP 0 R Reset after suspend
When exiting EM2, this bit needs to be set in host mode before clamp is removed if the host needs to issue reset after
suspend. If this bit is not set, then the host issues resume after suspend. This bit is not applicable in device mode and when
EM2 is not used.
7 Reserved To ensure compatibility with future devices, always write bits to 0. More information in 2.1 Conven-
tions.
6 PHYSLEEP 0 R PHY In Sleep
Indicates that the PHY is in Sleep State.
5:4 Reserved To ensure compatibility with future devices, always write bits to 0. More information in 2.1 Conven-
tions.
3 RSTPDWNMODULE 0 RW Reset Power-Down Modules
The application sets this bit to reset the part of the USB that is powered down during EM2. The application clears this bit to
release reset after an waking up from EM2 when the PHY clock is back at 48/6 MHz. Accessing core registers is possible
only when this bit is set to 0.
2 PWRCLMP 0 RW Power Clamp
The application sets this bit before the power is turned off to clamp the signals between the power-on modules and the
power-off modules of the USB core. The application clears the bit to disable the clamping.
1 GATEHCLK 0 RW Gate HCLK
The application sets this bit to gate the clock (HCLK) to modules other than the AHB Slave and Master and wakeup logic
when the USB is suspended or the session is not valid. The application clears this bit when the USB is resumed or a new
session starts.
0 STOPPCLK 0 RW Stop PHY clock
The application sets this bit to stop the PHY clock when the USB is suspended, the session is not valid, or the device is
disconnected. The application clears this bit when the USB is resumed or a new session starts.
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15.6.69 USB_FIFO0Dx - Device EP 0/Host Channel 0 FIFO
This register, available in both Host and Device modes, is used to read or write the FIFO space for endpoint 0 or channel 0, in a given
direction. If a host channel is of type IN, the FIFO can only be read on the channel. Similarly, if a host channel is of type OUT, the FIFO
can only be written on the channel.
Offset Bit Position
0x3D000
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
16
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
Reset
0xXXXXXXXX
Access
RW
Name
FIFO0D
Bit Name Reset Access Description
31:0 FIFO0D 0xXXXXXXX
X
RW Device EP 0/Host Channel 0 FIFO
FIFO 0 push/pop region. Used in slave mode.
15.6.70 USB_FIFO1Dx - Device EP 1/Host Channel 1 FIFO
This register, available in both Host and Device modes, is used to read or write the FIFO space for endpoint 1 or channel 1, in a given
direction. If a host channel is of type IN, the FIFO can only be read on the channel. Similarly, if a host channel is of type OUT, the FIFO
can only be written on the channel.
Offset Bit Position
0x3E000
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
16
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
Reset
0xXXXXXXXX
Access
RW
Name
FIFO1D
Bit Name Reset Access Description
31:0 FIFO1D 0xXXXXXXX
X
RW Device EP 1/Host Channel 1 FIFO
FIFO 1 push/pop region. Used in slave mode.
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15.6.71 USB_FIFO2Dx - Device EP 2/Host Channel 2 FIFO
This register, available in both Host and Device modes, is used to read or write the FIFO space for endpoint 2 or channel 2, in a given
direction. If a host channel is of type IN, the FIFO can only be read on the channel. Similarly, if a host channel is of type OUT, the FIFO
can only be written on the channel.
Offset Bit Position
0x3F000
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
16
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
Reset
0xXXXXXXXX
Access
RW
Name
FIFO2D
Bit Name Reset Access Description
31:0 FIFO2D 0xXXXXXXX
X
RW Device EP 2/Host Channel 2 FIFO
FIFO 2 push/pop region. Used in slave mode.
15.6.72 USB_FIFO3Dx - Device EP 3/Host Channel 3 FIFO
This register, available in both Host and Device modes, is used to read or write the FIFO space for endpoint 3 or channel 3, in a given
direction. If a host channel is of type IN, the FIFO can only be read on the channel. Similarly, if a host channel is of type OUT, the FIFO
can only be written on the channel.
Offset Bit Position
0x40000
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
16
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
Reset
0xXXXXXXXX
Access
RW
Name
FIFO3D
Bit Name Reset Access Description
31:0 FIFO3D 0xXXXXXXX
X
RW Device EP 3/Host Channel 3 FIFO
FIFO 3 push/pop region. Used in slave mode.
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15.6.73 USB_FIFO4Dx - Device EP 4/Host Channel 4 FIFO
This register, available in both Host and Device modes, is used to read or write the FIFO space for endpoint 4 or channel 4, in a given
direction. If a host channel is of type IN, the FIFO can only be read on the channel. Similarly, if a host channel is of type OUT, the FIFO
can only be written on the channel.
Offset Bit Position
0x41000
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
16
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
Reset
0xXXXXXXXX
Access
RW
Name
FIFO4D
Bit Name Reset Access Description
31:0 FIFO4D 0xXXXXXXX
X
RW Device EP 4/Host Channel 4 FIFO
FIFO 4 push/pop region. Used in slave mode.
15.6.74 USB_FIFO5Dx - Device EP 5/Host Channel 5 FIFO
This register, available in both Host and Device modes, is used to read or write the FIFO space for endpoint 5 or channel 5, in a given
direction. If a host channel is of type IN, the FIFO can only be read on the channel. Similarly, if a host channel is of type OUT, the FIFO
can only be written on the channel.
Offset Bit Position
0x42000
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
16
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
Reset
0xXXXXXXXX
Access
RW
Name
FIFO5D
Bit Name Reset Access Description
31:0 FIFO5D 0xXXXXXXX
X
RW Device EP 5/Host Channel 5 FIFO
FIFO 5 push/pop region. Used in slave mode.
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15.6.75 USB_FIFO6Dx - Device EP 6/Host Channel 6 FIFO
This register, available in both Host and Device modes, is used to read or write the FIFO space for endpoint 6 or channel 6, in a given
direction. If a host channel is of type IN, the FIFO can only be read on the channel. Similarly, if a host channel is of type OUT, the FIFO
can only be written on the channel.
Offset Bit Position
0x43000
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
16
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
Reset
0xXXXXXXXX
Access
RW
Name
FIFO6D
Bit Name Reset Access Description
31:0 FIFO6D 0xXXXXXXX
X
RW Device EP 6/Host Channel 6 FIFO
FIFO 6 push/pop region. Used in slave mode.
15.6.76 USB_FIFO7Dx - Host Channel 7 FIFO
This register, available in Host mode, is used to read or write the FIFO space for channel 7, in a given direction. If a host channel is of
type IN, the FIFO can only be read on the channel. Similarly, if a host channel is of type OUT, the FIFO can only be written on the
channel.
Offset Bit Position
0x44000
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
16
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
Reset
0xXXXXXXXX
Access
RW
Name
FIFO7D
Bit Name Reset Access Description
31:0 FIFO7D 0xXXXXXXX
X
RW Host Channel 7 FIFO
FIFO 7 push/pop region. Used in slave mode.
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15.6.77 USB_FIFO8Dx - Host Channel 8 FIFO
This register, available in Host mode, is used to read or write the FIFO space for channel 8, in a given direction. If a host channel is of
type IN, the FIFO can only be read on the channel. Similarly, if a host channel is of type OUT, the FIFO can only be written on the
channel.
Offset Bit Position
0x45000
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
16
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
Reset
0xXXXXXXXX
Access
RW
Name
FIFO8D
Bit Name Reset Access Description
31:0 FIFO8D 0xXXXXXXX
X
RW Host Channel 8 FIFO
FIFO 8 push/pop region. Used in slave mode.
15.6.78 USB_FIFO9Dx - Host Channel 9 FIFO
This register, available in Host mode, is used to read or write the FIFO space for channel 9, in a given direction. If a host channel is of
type IN, the FIFO can only be read on the channel. Similarly, if a host channel is of type OUT, the FIFO can only be written on the
channel.
Offset Bit Position
0x46000
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
16
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
Reset
0xXXXXXXXX
Access
RW
Name
FIFO9D
Bit Name Reset Access Description
31:0 FIFO9D 0xXXXXXXX
X
RW Host Channel 9 FIFO
FIFO 9 push/pop region. Used in slave mode.
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15.6.79 USB_FIFO10Dx - Host Channel 10 FIFO
This register, available in Host mode, is used to read or write the FIFO space for channel 10, in a given direction. If a host channel is of
type IN, the FIFO can only be read on the channel. Similarly, if a host channel is of type OUT, the FIFO can only be written on the
channel.
Offset Bit Position
0x47000
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
16
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
Reset
0xXXXXXXXX
Access
RW
Name
FIFO10D
Bit Name Reset Access Description
31:0 FIFO10D 0xXXXXXXX
X
RW Host Channel 10 FIFO
FIFO 10 push/pop region. Used in slave mode.
15.6.80 USB_FIFO11Dx - Host Channel 11 FIFO
This register, available in Host mode, is used to read or write the FIFO space for channel 11, in a given direction. If a host channel is of
type IN, the FIFO can only be read on the channel. Similarly, if a host channel is of type OUT, the FIFO can only be written on the
channel.
Offset Bit Position
0x48000
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
16
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
Reset
0xXXXXXXXX
Access
RW
Name
FIFO11D
Bit Name Reset Access Description
31:0 FIFO11D 0xXXXXXXX
X
RW Host Channel 11 FIFO
FIFO 11 push/pop region. Used in slave mode.
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15.6.81 USB_FIFO12Dx - Host Channel 12 FIFO
This register, available in Host mode, is used to read or write the FIFO space for channel 12, in a given direction. If a host channel is of
type IN, the FIFO can only be read on the channel. Similarly, if a host channel is of type OUT, the FIFO can only be written on the
channel.
Offset Bit Position
0x49000
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
16
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
Reset
0xXXXXXXXX
Access
RW
Name
FIFO12D
Bit Name Reset Access Description
31:0 FIFO12D 0xXXXXXXX
X
RW Host Channel 12 FIFO
FIFO 12 push/pop region. Used in slave mode.
15.6.82 USB_FIFO13Dx - Host Channel 13 FIFO
This register, available in Host mode, is used to read or write the FIFO space for channel 13, in a given direction. If a host channel is of
type IN, the FIFO can only be read on the channel. Similarly, if a host channel is of type OUT, the FIFO can only be written on the
channel.
Offset Bit Position
0x4A000
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
16
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
Reset
0xXXXXXXXX
Access
RW
Name
FIFO13D
Bit Name Reset Access Description
31:0 FIFO13D 0xXXXXXXX
X
RW Host Channel 13 FIFO
FIFO 13 push/pop region. Used in slave mode.
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15.6.83 USB_FIFORAMx - Direct Access to Data FIFO RAM for Debugging (2 KB)
Offset Bit Position
0x5C000
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
16
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
Reset
0xXXXXXXXX
Access
RW
Name
FIFORAM
Bit Name Reset Access Description
31:0 FIFORAM 0xXXXXXXX
X
RW FIFO RAM
Direct Access to Data FIFO RAM for Debugging (2 KB)
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gill-IT
16. I2C - Inter-Integrated Circuit Interface
43210
DEVICE
I2C master/slave
Other I2C
master
Other I2C
slave
VDD
I2C
EEPROM
SDA
SCL
Quick Facts
What?
The I2C interface allows communication on I2C-
buses with the lowest energy consumption possible.
Why?
I2C is a popular serial bus that enables communica-
tion with a number of external devices using only
two I/O pins.
How?
With the help of DMA, the I2C interface allows I2C
communication with minimal CPU intervention. Ad-
dress recognition is available in all energy modes
(except EM4), allowing the MCU to wait for data on
the I2C-bus with sub-μA current consumption.
16.1 Introduction
The I2C module provides an interface between the MCU and a serial I2C-bus. It is capable of acting as both master and slave, and
supports multi-master buses. Standard-mode, fast-mode and fast-mode plus speeds are supported, allowing transmission rates all the
way from 10 kbit/s up to 1 Mbit/s. Slave arbitration and timeouts are also provided to allow implementation of an SMBus compliant sys-
tem. The interface provided to software by the I2C module allows both fine-grained control of the transmission process and close to
automatic transfers. Automatic recognition of slave addresses is provided in all energy modes (except EM4).
16.2 Features
• True multi-master capability
• Support for different bus speeds
• Standard-mode (Sm) bit rate up to 100 kbit/s
• Fast-mode (Fm) bit rate up to 400 kbit/s
• Fast-mode Plus (Fm+) bit rate up to 1 Mbit/s
• Arbitration for both master and slave (allows SMBus ARP)
• Clock synchronization and clock stretching
• Hardware address recognition
• 7-bit masked address
• General call address
• Active in all energy modes (except EM4)
• 10-bit address support
• Error handling
• Clock low timeout
• Clock high timeout
• Arbitration lost
• Bus error detection
• Double buffered data
• Full DMA support
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16.3 Functional Description
An overview of the I2C module is shown in Figure 16.1 I2C Overview on page 537.
Transmit Buffer
Transmit
Shift Register
I2Cn_SDA
Receive Buffer
Receive
Shift Register
I2C Control and
Status
Peripheral Bus
I2Cn_SCL
Pin
ctrl
Symbol
Generator
Receive
Controller Clock generator
Address
Recognizer
Figure 16.1. I2C Overview
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Ill-lg
16.3.1 I2C-Bus Overview
The I2C-bus uses two wires for communication; a serial data line (SDA) and a serial clock line (SCL) as shown in the following figure.
As a true multi-master bus it includes collision detection and arbitration to resolve situations where multiple masters transmit data at the
same time without data loss.
I2C
master #1
I2C
master #2
I2C slave
#1
I2C slave
#2
I2C slave
#3
SDA
SCL
VDD
Rp
Figure 16.2. I2C-Bus Example
Each device on the bus is addressable by a unique address, and an I2C master can address all the devices on the bus, including other
masters.
Both the bus lines are open-drain. The maximum value of the pull-up resistor can be calculated as a function of the maximal rise-time tr
for the given bus speed, and the estimated bus capacitance Cb as shown in the following equation.
Rp(max) = tr
0.8473 × Cb
The maximal rise times for 100 kHz, 400 kHz, and 1 MHz I2C are 1 µs, 300 ns, and 120 ns respectively.
Note: The GPIO drive strength can be used to control slew rate.
Note: If Vdd drops below the voltage on SCL and SDA lines, the MCU could become back powered and pull the SCL and SDA lines
low.
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16.3.1.1 START and STOP Conditions
START and STOP conditions are used to initiate and stop transactions on the I2C-bus. All transactions on the bus begin with a START
condition (S) and end with a STOP condition (P). As shown in the following figure, a START condition is generated by pulling the SDA
line low while SCL is high, and a STOP condition is generated by pulling the SDA line high while SCL is high.
Figure 16.3. I2C START and STOP Conditions
SCL
SDA
S P
START condition STOP condition
Figure 16.4. I2C START and STOP Conditions
The START and STOP conditions are easily identifiable bus events as they are the only conditions on the bus where a transition is
allowed on SDA while SCL is high. During the actual data transmission, SDA is only allowed to change while SCL is low, and must be
stable while SCL is high. One bit is transferred per clock pulse on the I2C-bus as shown in the following figure.
Figure 16.5. I2C Bit Transfer on I2C-Bus
SCL
SDA
Data stable Data change
allowed
Data change
allowed
Figure 16.6. I2C Bit Transfer on I2C-Bus
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16.3.1.2 Bus Transfer
When a master wants to initiate a transfer on the bus, it waits until the bus is idle and transmits a START condition on the bus. The
master then transmits the address of the slave it wishes to interact with and a single R/W bit telling whether it wishes to read from the
slave (R/W bit set to 1) or write to the slave (R/W bit set to 0).
After the 7-bit address and the R/W bit, the master releases the bus, allowing the slave to acknowledge the request. During the next bit-
period, the slave pulls SDA low (ACK) if it acknowledges the request, or keeps it high if it does not acknowledge it (NACK).
Following the address acknowledge, either the slave or master transmits data, depending on the value of the R/W bit. After every 8 bits
(one byte) transmitted on the SDA line, the transmitter releases the line to allow the receiver to transmit an ACK or a NACK. Both the
data and the address are transmitted with the most significant bit first.
The number of bytes in a bus transfer is unrestricted. The master ends the transmission after a (N)ACK by sending a STOP condition
on the bus. After a STOP condition, any master wishing to initiate a transfer on the bus can try to gain control of it. If the current master
wishes to make another transfer immediately after the current, it can start a new transfer directly by transmitting a repeated START
condition (Sr) instead of a STOP followed by a START.
Examples of I2C transfers are shown in the following figures. The identifiers used are:
• ADDR - Address
• DATA - Data
• S - Start bit
• Sr - Repeated start bit
• P - Stop bit
• W/R - Read(1)/Write(0)
• A - ACK
• N - NACK
R
Sr ADDR DATAA N PWS ADDR DATAA A
Figure 16.7. I2C Single Byte Write to Slave
RS ADDR DATAA DATA NA P
Figure 16.8. I2C Double Byte Read from Slave
RSr ADDR DATAA N PWS ADDR DATAA A
Figure 16.9. I2C Single Byte Write, then Repeated Start and Single Byte Read
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16.3.1.3 Addresses
I2C supports both 7-bit and 10-bit addresses. When using 7-bit addresses, the first byte transmitted after the START-condition contains
the address of the slave that the master wants to contact. In the 7-bit address space, several addresses are reserved. These addresses
are summarized in Table 16.1 I2C Reserved I2C Addresses on page 541, and include a General Call address which can be used to
broadcast a message to all slaves on the I2C-bus.
Table 16.1. I2C Reserved I2C Addresses
I2C Address R/W Description
0000-000 0 General Call address
0000-000 1 START byte
0000-001 X Reserved for the C-Bus format
0000-010 X Reserved for a different bus format
0000-011 X Reserved for future purposes
0000-1XX X Reserved for future purposes
1111-1XX X Reserved for future purposes
1111-0XX X 10 Bit slave addressing mode
16.3.1.4 10-Bit Addressing
To address a slave using a 10-bit address, two bytes are required to specify the address instead of one. The seven first bits of the first
byte must then be 1111 0XX, where XX are the two most significant bits of the 10-bit address. As with 7-bit addresses, the eight bit of
the first byte determines whether the master wishes to read from or write to the slave. The second byte contains the eight least signifi-
cant bits of the slave address.
When a slave receives a 10-bit address, it must acknowledge both the address bytes if they match the address of the slave.
When performing a master transmitter operation, the master transmits the two address bytes and then the remaining data, as shown in
the following figure.
W
S A A DATA A PAddr (2nd byte)ADDR (1st 7 bits)
Figure 16.10. I2C Master Transmitter/Slave Receiver with 10-Bit Address
When performing a master receiver operation however, the master first transmits the two address bytes in a master transmitter opera-
tion, then sends a repeated START followed by the first address byte and then receives data from the addressed slave. The slave ad-
dressed by the 10-bit address in the first two address bytes must remember that it was addressed, and respond with data if the address
transmitted after the repeated start matches its own address. An example of this (with one byte transmitted) is shown in the following
figure.
R
Sr DATAA N PWS A AADDR (1st 7 bits) Addr (2nd byte) ADDR (1st 7 bits)
Figure 16.11. I2C Master Receiver/Slave Transmitter with 10-Bit Address
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16.3.1.5 Arbitration, Clock Synchronization, Clock Stretching
Arbitration and clock synchronization are features aimed at allowing multi-master buses. Arbitration occurs when two devices try to
drive the bus at the same time. If one device drives it low, while the other drives it high, the one attempting to drive it high will not be
able to do so due to the open-drain bus configuration. Both devices sample the bus, and the one that was unable to drive the bus in the
desired direction detects the collision and backs off, letting the other device continue communication on the bus undisturbed.
Clock synchronization is a means of synchronizing the clock outputs from several masters driving the bus at once, and is a requirement
for effective arbitration.
Slaves on the bus are allowed to force the clock output on the bus low in order to pause the communication on the bus and give them-
selves time to process data or perform any real-time tasks they might have. This is called clock stretching.
Arbitration is supported by the I2C module for both masters and slaves. Clock synchronization and clock stretching is also supported.
16.3.2 Enable and Reset
The I2C is enabled by setting the EN bit in the I2Cn_CTRL register. Whenever this bit is cleared, the internal state of the I2C is reset,
terminating any ongoing transfers.
Note: When re-enabling the I2C, the ABORT command or the Bus Idle Timeout feature must be applied prior to use even if the BUSY
flag is not set.
16.3.3 Safely Disabling and Changing Slave Configuration
The I2C slave is partially asynchronous, and some precautions are necessary to always ensure a safe slave disable or slave configura-
tion change. These measures should be taken, if (while the slave is enabled) the user cannot guarantee that an address match will not
occur at the exact time of slave disable or slave configuration change.
Worst case consequences for an address match while disabling slave or changing configuration is that the slave may end up in an
undefined state. To reset the slave back to a known state, the EN bit in I2Cn_CTRL must be reset. This should be done regardless of
whether the slave is going to be re-enabled or not.
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16.3.4 Clock Generation
The SCL signal generated by the I2C master determines the maximum transmission rate on the bus. The clock is generated as a divi-
sion of the peripheral clock, and is given by the following equation:
fSCL =1
Tlow +Thigh
where Tlow and Thigh are the low and high periods of the clock signal respectively, given below. When the clock is not streched, the low
and high periods of the clock signal are:
Thigh =
Nhigh × (CLKDIV + 1)
fHFPERCLK
Tlow =
Nlow × (CLKDIV + 1)
fHFPERCLK
These equations do not apply for low clock division factors (0, 1 and 2) because of synchronization. For these clock division factors, the
formulas for computing high and low periods of the clock signal are given in the following table.
Table 16.2. I2C High and Low Periods for Low CLKDIV
CLKDIV Standard (4:4) Asymmetric (6:3) Fast (11:6)
Tlow Thigh Tlow Thigh Tlow Thigh
0 7/fHFPERCLK 7/fHFPERCLK 9/fHFPERCLK 6/fHFPERCLK 14/fHFPERCLK 9/fHFPERCLK
1 10/fHFPERCLK 10/fHFPERCLK 14/fHFPERCLK 8/fHFPERCLK 24/fHFPERCLK 14/fHFPERCLK
2 15/fHFPERCLK 15/fHFPERCLK 21/fHFPERCLK 12/fHFPERCLK 36/fHFPERCLK 21/fHFPERCLK
The values of Nlow and Nhigh and thus the ratio between the high and low parts of the clock signal is controlled by CLHR in the
I2Cn_CTRL register. The available modes are summarized in the following table along with the highest I2C-bus frequencies in the given
modes that can be achieved without violating the timing specifications of the I2C-bus. The frequencies are calculated taking the maxi-
mum allowed rise and fall times of SDA and SCL into account. Higher frequencies may be achieved in practice. The 3 extra cycles are
synchronization, and must be taken into consideration when DIV in the I2Cn_CLKDIV register has a low value. The maximum data hold
time is dependent on the DIV and is given by:
tHD,DAT-max =4 + DIV
fHFPERCLK
Note: DIV must be set to 1 during slave mode operation.
Table 16.3. I2C Clock Mode
HFPERCLK frequency
(MHz)
Clock Low High Ratio
(CLHR)
Sm max frequency
(kHz)
Fm max frequency
(kHz)
Fm+ max frequency
(kHz)
48 0 92 400 1000
1 74 400 959
2 68 400 799
28 0 92 400 1000
1 81 400 848
2 71 400 736
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HFPERCLK frequency
(MHz)
Clock Low High Ratio
(CLHR)
Sm max frequency
(kHz)
Fm max frequency
(kHz)
Fm+ max frequency
(kHz)
21 0 90 400 1000
1 80 400 954
2 72 368 552
14 0 92 400 1000
1 81 400 636
2 68 368 608
11 0 91 400 785
1 81 333 733
2 71 289 478
6.6 0 91 400 471
1 81 299 439
2 64 286 286
1.2 0 59 85 85
1 54 79 79
2 52 52 52
16.3.5 Arbitration
Arbitration is enabled by default, but can be disabled by setting the ARBDIS bit in I2Cn_CTRL. When arbitration is enabled, the value
on SDA is sensed every time the I2C module attempts to change its value. If the sensed value is different than the value the I2C module
tried to output, it is interpreted as a simultaneous transmission by another device, and that the I2C module has lost arbitration.
Whenever arbitration is lost, the ARBLOST interrupt flag in I2Cn_IF is set, any lines held are released, and the I2C device goes idle. If
an I2C master loses arbitration during the transmission of an address, another master may be trying to address it. The master therefore
receives the rest of the address, and if the address matches the slave address of the master, the master goes into either slave transmit-
ter or slave receiver mode.
Note: Arbitration can be lost both when operating as a master and when operating as a slave.
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16.3.6 Buffers
16.3.6.1 Transmit Buffer and Shift Register
The I2C transmitter is double buffered through the transmit buffer and transmit shift register as shown in Figure 16.1 I2C Overview on
page 537. A byte is loaded into the transmit buffer by writing to I2Cn_TXDATA. When the transmit shift register is empty and ready for
new data, the byte from the transmit buffer is then loaded into the shift register. The byte is then kept in the shift register until it is
transmitted. When a byte has been transmitted, a new byte is loaded into the shift register (if available in the transmit buffer). If the
transmit buffer is empty, then the shift register also remains empty. The TXC flag in I2Cn_STATUS and the TXC interrupt flags in
I2Cn_IF are then set, signaling that the transmit shift register is out of data. TXC is cleared when new data becomes available, but the
TXC interrupt flag must be cleared by software.
Whenever a byte is loaded from the transmit buffer to the transmit shift register, the TXBL flag in I2Cn_STATUS and the TXBL interrupt
flag in I2Cn_IF are set. This indicates that there is room in the buffer for more data. TXBL is cleared automatically when data is written
to the buffer.
If a write is attempted to the transmit buffer while it is not empty, the TXOF interrupt flag in I2Cn_IF is set, indicating the overflow. The
data already in the buffer remains preserved, and no new data is written.
The transmit buffer and the transmit shift register can be cleared by setting command bit CLEARTX in I2Cn_CMD. This will prevent the
I2C module from transmitting the data in the buffer and the shift register, and will make them available for new data. Any byte currently
being transmitted will not be aborted. Transmission of this byte will be completed.
16.3.6.2 Receive Buffer and Shift Register
Like the transmitter, the I2C receiver is double buffered. The receiver uses the receive buffer and receive shift register as shown in
Figure 16.1 I2C Overview on page 537. When a byte has been fully received by the receive shift register, it is loaded into the receive
buffer if there is room for it. Otherwise, the byte waits in the shift register until space becomes available in the buffer.
When a byte becomes available in the receive buffer, the RXDATAV in I2Cn_STATUS and RXDATAV interrupt flag in I2Cn_IF are set.
The data can now be fetched from the buffer using I2Cn_RXDATA. Reading from this register will pull a byte out of the buffer, making
room for a new byte and clearing RXDATAV in I2Cn_STATUS and RXDATAV in I2Cn_IF in the process.
If a read from the receive buffer is attempted through I2Cn_RXDATA while the buffer is empty, the RXUF interrupt flag in I2Cn_IF is set,
and the data read from the buffer is undefined.
I2Cn_RXDATAP can be used to read data from the receive buffer without removing it from the buffer. The RXUF interrupt flag in
I2Cn_IF will never be set as a result of reading from I2Cn_RXDATAP, but the data read through I2Cn_RXDATAP when the receive
buffer is empty is still undefined.
Once a transaction is complete (STOP sent or received), the receive buffer needs to be flushed (all received data must be picked up)
before starting a new transaction.
16.3.7 Master Operation
A bus transaction is initiated by transmitting a START condition (S) on the bus. This is done by setting the START bit in I2Cn_CMD.
The command schedules a START condition, and makes the I2C module generate a start condition whenever the bus becomes free.
The I2C-bus is considered busy whenever another device on the bus transmits a START condition. Until a STOP condition is detected,
the bus is owned by the master issuing the START condition. The bus is considered free when a STOP condition is transmitted on the
bus. After a STOP is detected, all masters that have data to transmit send a START condition and begin transmitting data. Arbitration
ensures that collisions are avoided.
When the START condition has been transmitted, the master must transmit a slave address (ADDR) with an R/W bit on the bus. If this
address is available in the transmit buffer, the master transmits it immediately, but if the buffer is empty, the master holds the I2C-bus
while waiting for software to write the address to the transmit buffer.
After the address has been transmitted, a sequence of bytes can be read from or written to the slave, depending on the value of the
R/W bit (bit 0 in the address byte). If the bit was cleared, the master has entered a master transmitter role, where it now transmits data
to the slave. If the bit was set, it has entered a master receiver role, where it now should receive data from the slave. In either case, an
unlimited number of bytes can be transferred in one direction during the transmission.
At the end of the transmission, the master either transmits a repeated START condition (Sr) if it wishes to continue with another trans-
fer, or transmits a STOP condition (P) if it wishes to release the bus.
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figgmmm
<5 20="" o="">16.3.7.1 Master State Machine
The master state machine is shown in Figure 16.12 I2C Master State Machine on page 546. A master operation starts in the far left of
the state machine, and follows the solid lines through the state machine, ending the operation or continuing with a new operation when
arriving at the right side of the state machine.
Branches in the path through the state machine are the results of bus events and choices made by software, either directly or indirectly.
The dotted lines show where I2C-specific interrupt flags are set along the path and the full-drawn circles show places where interaction
may be required by software to let the transmission proceed.
Waiting
for idle
Idle/busy
57
B3
9B
0
57
S
ADDR R A
N
ADDR W
A
N
DATA P
Sr
XArb. lost 1
97 D7
DF
9F
A
N
A
N
DATA P
Sr
Arb. lost
ADDR R Arb. lost, ADDR match
ADDR W Arb. lost, ADDR match
ADDR X Arb. lost, no match 1
71
Master receiver
Master transmitter
Arbitration lost
Slave transmitter
Slave receiver
0
57
1
93
0/1
Bus state/event
Transmitted by self
Received from slave
START
condition
Interrupt flag set
Interaction required. Wait-
states inserted until manual or
automatic interaction has
been performed
Go to state
A
S P
N
Sr
ACK
STOP
condition
NACK
Repeated START condition
ADDR R
ADDR W
Slave address + read (R/
W bit set)
Slave address + write (R/
W bit cleared)
Bus state (STATE)
73
0P
Bus reset
Figure 16.12. I2C Master State Machine
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16.3.7.2 Interactions
Whenever the I2C module is waiting for interaction from software, it holds the bus clock SCL low, freezing all bus activities, and the
BUSHOLD interrupt flag in I2Cn_IF is set. The action(s) required by software depends on the current state the of the I2C module. This
state can be read from the I2Cn_STATE register.
As an example, Table 16.5 I2C Master Transmitter on page 549 shows the different states the I2C goes through when operating as a
Master Transmitter, i.e. a master that transmits data to a slave. As seen in the table, when a start condition has been transmitted, a
requirement is that there is an address and an R/W bit in the transmit buffer. If the transmit buffer is empty, then the BUSHOLD inter-
rupt flag is set, and the bus is held until data becomes available in the buffer. While waiting for the address, I2Cn_STATE has a value
0x57, which can be used to identify exactly what the I2C module is waiting for.
Note: The bus would never stop at state 0x57 if the address was available in the transmit buffer.
The different interactions used by the I2C module are listed in the following table in prioritized order. If a set of different courses of
action are possible from a given state, the course of action using the highest priority interactions, that first has everything it is waiting for
is the one that is taken.
Table 16.4. I2C Interactions in Prioritized Order
Interaction Priority Software action Automatically continues if
STOP* 1 Set the STOP command bit in
I2Cn_CMD
PSTOP is set (STOP pending)
in I2Cn_STATUS
ABORT 2 Set the ABORT command bit in
I2Cn_CMD
Never, the transmission is abor-
ted
CONT* 3 Set the CONT command bit in
I2Cn_CMD
PCONT is set in I2Cn_STATUS
(CONT pending)
NACK* 4 Set the NACK command bit in
I2Cn_CMD
PNACK is set in I2Cn_STATUS
(NACK pending)
ACK* 5 Set the ACK command bit in
I2Cn_CMD
AUTOACK is set in I2Cn_CTRL
or PACK is set in I2Cn_STA-
TUS (ACK pending)
ADDR+W -> TXDATA 6 Write an address to the transmit
buffer with the R/W bit set
Address is available in transmit
buffer with R/W bit set
ADDR+R -> TXDATA 7 Write an address to the transmit
buffer with the R/W bit cleared
Address is available in transmit
buffer with R/W bit cleared
START* 8 Set the START command bit in
I2Cn_CMD
PSTART is set in I2Cn_STA-
TUS (START pending)
TXDATA 9 Write data to the transmit buffer Data is available in transmit buf-
fer
RXDATA 10 Read data from receive buffer Space is available in receive
buffer
None 11 No interaction is required —
The commands marked with a * in this table can be issued before an interaction is required. When such a command is issued before it
can be used/consumed by the I2C module, the command is set in a pending state, which can be read from the STATUS register. A
pending START command can for instance be identified by PSTART having a high value.
Whenever the I2C module requires an interaction, it checks the pending commands. If one or a combination of these can fulfill an inter-
action, they are consumed by the module and the transmission continues without setting the BUSHOLD interrupt flag in I2Cn_IF to get
an interaction from software. The pending status of a command goes low when it is consumed.
When several interactions are possible from a set of pending commands, the interaction with the highest priority, i.e. the interaction
closest to the top of Table 16.4 I2C Interactions in Prioritized Order on page 547 is applied to the bus.
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Pending commands can be cleared by setting the CLEARPC command bit in I2Cn_CMD.
16.3.7.2.1 Automatic ACK Interaction
When receiving addresses and data, an ACK command in I2Cn_CMD is normally required after each received byte. When AUTOACK
is set in I2Cn_CTRL, an ACK is always pending, and the ACK-pending bit PACK in I2Cn_STATUS is thus always set, even after an
ACK has been consumed. This can be used to reduce the amount of software interaction required during a transfer.
16.3.7.3 Reset State
After a reset, the state of the I2C-bus is unknown. To avoid interrupting transfers on the I2C-bus after a reset of the I2C module or the
entire MCU, the I2C-bus is assumed to be busy when coming out of a reset, and the BUSY flag in I2Cn_STATUS is thus set. To be able
to carry through master operations on the I2C-bus, the bus must be idle.
The bus goes idle when a STOP condition is detected on the bus, but on buses with little activity, the time before the I2C module de-
tects that the bus is idle can be significant. There are two ways of assuring that the I2C module gets out of the busy state.
•Use the ABORT command in I2Cn_CMD. When the ABORT command is issued, the I2C module is instructed that the bus is idle.
The I2C module can then initiate master operations.
• Use the Bus Idle Timeout. When SCL has been high for a long period of time, it is very likely that the bus is idle. Set BITO in
I2Cn_CTRL to an appropriate timeout period and set GIBITO in I2Cn_CTRL. If activity has not been detected on the bus within the
timeout period, the bus is then automatically assumed idle, and master operations can be initiated.
Note: If operating in slave mode, the above approach is not necessary.
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16.3.7.4 Master Transmitter
To transmit data to a slave, the master must operate as a master transmitter. Table 16.5 I2C Master Transmitter on page 549 shows
the states the I2C module goes through while acting as a master transmitter. Every state where an interaction is required has the possi-
ble interactions listed, along with the result of the interactions. The table also shows which interrupt flags are set in the different states.
The interrupt flags enclosed in parenthesis may be set. If the BUSHOLD interrupt in I2Cn_IF is set, the module is waiting for an interac-
tion, and the bus is frozen. The value of I2Cn_STATE will be equal to the values given in the table when the BUSHOLD interrupt flag is
set, and can be used to determine which interaction is required to make the transmission continue.
The interrupt flag START in I2Cn_IF is set when the I2C module transmits the START.
A master operation is started by issuing a START command by setting START in I2Cn_CMD. ADDR +W, i.e. the address of the slave
to address + the R/W bit is then required by the I2C module. If this is not available in the transmit buffer, then the bus is held and the
BUSHOLD interrupt flag is set. The value of I2Cn_STATE will then be 0x57. As seen in the table, the I2C module also stops in this state
if the address is not available after a repeated start condition.
To continue, write a byte to I2Cn_TXDATA with the address of the slave in the 7 most significant bits and the least significant bit
cleared (ADDR+W). This address will then be transmitted, and the slave will reply with an ACK or a NACK. If no slave replies to the
address, the response will also be NACK. If the address was acknowledged, the master now has four choices. It can send a data byte
by placing it in I2Cn_TXDATA (the master should check the TXBL interrupt flag before writing to I2Cn_TXDATA), this byte is then trans-
mitted. The master can also stop the transmission by sending a STOP, it can send a repeated start by sending START, or it can send a
STOP and then a START as soon as possible.
If a NACK was received, the master has to issue a CONT command in addition to providing data in order to continue transmission. This
is not standard I2C, but is provided for flexibility. The rest of the options are similar to when an ACK was received.
If a new byte was transmitted, an ACK or NACK is received after the transmission of the byte, and the master has the same options as
for when the address was sent.
The master may lose arbitration at any time during transmission. In this case, the ARBLOST interrupt flag in I2Cn_IF is set. If the arbi-
tration was lost during the transfer of an address, and SLAVE in I2Cn_CTRL is set, the master then checks which address was trans-
mitted. If it was the address of the master, then the master goes to slave mode.
After a master has transmitted a START and won any arbitration, it owns the bus until it transmits a STOP. After a STOP, the bus is
released, and arbitration decides which bus master gains the bus next. The MSTOP interrupt flag in I2Cn_IF is set when a STOP condi-
tion is transmitted by the master.
Table 16.5. I2C Master Transmitter
I2Cn_STA Description I2Cn_IF Required
interaction
Response
0x57 Start transmitted START interrupt flag
(BUSHOLD interrupt
flag)
ADDR +W -
> TXDATA
ADDR+W will be sent
STOP STOP will be sent and bus released.
STOP +
START
STOP will be sent and bus released. Then a START will
be sent when bus becomes idle.
0x57 Repeated start trans-
mitted
START interrupt flag
(BUSHOLD interrupt
flag)
ADDR +W -
> TXDATA
ADDR+W will be sent
STOP STOP will be sent and bus released.
STOP +
START
STOP will be sent and bus released. Then a START will
be sent when bus becomes idle.
— ADDR+W transmitted TXBL interrupt flag
(TXC interrupt flag)
None —
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I2Cn_STA Description I2Cn_IF Required
interaction
Response
0x97 ADDR+W transmitted,
ACK received
ACK interrupt flag
(BUSHOLD interrupt
flag)
TXDATA DATA will be sent
STOP STOP will be sent. Bus will be released
START Repeated start condition will be sent
STOP +
START
STOP will be sent and the bus released. Then a START
will be sent when the bus becomes idle
0x9F ADDR+W DATA will
be sent transmit-
ted,NACK received
NACK (BUSHOLD in-
terrupt flag)
CONT +
TXDATA
DATA will be sent
STOP STOP will be sent. Bus will be released
START Repeated start condition will be sent
STOP +
START
STOP will be sent and the bus released. Then a START
will be sent when the bus becomes idle
— Data transmitted TXBL interrupt flag
(TXC interrupt flag)
None —
0xD7 Data transmitted,ACK
received
ACK interrupt flag
(BUSHOLD interrupt
flag)
TXDATA DATA will be sent
STOP STOP will be sent. Bus will be released
START Repeated start condition will be sent
STOP +
START
STOP will be sent and the bus released. Then a START
will be sent when the bus becomes idle
0xDF Data transmit-
ted,NACK received
NACK(BUSHOLD in-
terrupt flag)
CONT +
TXDATA
DATA will be sent
STOP STOP will be sent. Bus will be released
START Repeated start condition will be sent
STOP +
START
STOP will be sent and the bus released. Then a START
will be sent when the bus becomes idle
— Stop transmitted MSTOP interrupt flag None —
START START will be sent when bus becomes idle
— Arbitration lost ARBLOST interrupt
flag
None —
START START will be sent when bus becomes idle
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16.3.7.5 Master Receiver
To receive data from a slave, the master must operate as a master receiver, see Table 16.6 I2C Master Receiver on page 551 . This
is done by transmitting ADDR+R as the address byte instead of ADDR+W, which is transmitted to become a master transmitter. The
address byte loaded into the data register thus has to contain the 7- bit slave address in the 7 most significant bits of the byte, and have
the least significant bit set.
When the address has been transmitted, the master receives an ACK or a NACK. If an ACK is received, the ACK interrupt flag in
I2Cn_IF is set, and if space is available in the receive shift register, reception of a byte from the slave begins. If the receive buffer and
shift register is full however, the bus is held until data is read from the receive buffer or another interaction is made. Note that the STOP
and START interactions have a higher priority than the data-available interaction, so if a STOP or START command is pending, the
highest priority interaction will be performed, and data will not be received from the slave.
If a NACK was received, the CONT command in I2Cn_CMD has to be issued in order to continue receiving data, even if there is space
available in the receive buffer and/or shift register.
After a data byte has been received the master must ACK or NACK the received byte. If an ACK is pending or AUTOACK in
I2Cn_CTRL is set, an ACK is sent automatically and reception continues if space is available in the receive buffer.
If a NACK is sent, the CONT command must be used in order to continue transmission. If an ACK or NACK is issued along with a
START or STOP or both, then the ACK/NACK is transmitted and the reception is ended. If START in I2Cn_CMD is set alone, a repea-
ted start condition is transmitted after the ACK/NACK. If STOP in I2Cn_CMD is set, a stop condition is sent regardless of whether
START is set. If START is set in this case, it is set as pending.
As when operating as a master transmitter, arbitration can be lost as a master receiver. When this happens the ARBLOST interrupt flag
in I2Cn_IF is set, and the master has a possibility of being selected as a slave given the correct conditions.
Table 16.6. I2C Master Receiver
I2Cn_STA Description I2Cn_IF Required
interaction
Response
0x57 Start transmitted START interrupt flag
(BUSHOLD interrupt
flag)
ADDR +R ->
TXDATA
ADDR+R will be sent
STOP STOP will be sent and bus released.
STOP +
START
STOP will be sent and bus released. Then a START will
be sent when bus becomes idle.
0x57 Repeated START
transmitted
START interrupt flag
(BUSHOLD interrupt
flag)
ADDR +R ->
TXDATA
ADDR+R will be sent
STOP STOP will be sent and bus released.
STOP +
START
STOP will be sent and bus released. Then a START will
be sent when bus becomes idle.
— ADDR+R transmitted TXBL interrupt flag
(TXC interrupt flag)
None —
0x93 ADDR+R transmitted,
ACK received
ACK interrupt
flag(BUSHOLD)
RXDATA Start receiving
STOP STOP will be sent and the bus released
START Repeated START will be sent
STOP +
START
STOP will be sent and the bus released. Then a START
will be sent when the bus becomes idle
0x9B ADDR+R transmit-
ted,NACK received
NACK (BUSHOLD) CONT +
RXDATA
Continue, start receiving
STOP STOP will be sent and the bus released
START Repeated START will be sent
STOP +
START
STOP will be sent and the bus released. Then a START
will be sent when the bus becomes idle
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I2Cn_STA Description I2Cn_IF Required
interaction
Response
0xB3 Data received RXDATA interrupt
flag(BUSHOLD inter-
rupt flag)
ACK +
RXDATA
ACK will be transmitted, reception continues
NACK +
CONT +
RXDATA
NACK will be transmitted, reception continues
ACK/ NACK
+ STOP
ACK/NACK will be sent and the bus will be released.
ACK/ NACK
+ START
ACK/NACK will be sent, and then a repeated start con-
dition.
ACK/ NACK
+ STOP +
START
ACK/NACK will be sent and the bus will be released.
Then a START will be sent when the bus becomes idle
— Stop received MSTOP interrupt flag None —
START START will be sent when bus becomes idle
— Arbitration lost ARBLOST interrupt
flag
None —
START START will be sent when bus becomes idle
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16.3.8 Bus States
The I2Cn_STATE register can be used to determine which state the I2C module and the I2C bus are in at a given time. The register
consists of the STATE bit-field, which shows which state the I2C module is at in any ongoing transmission, and a set of single-bits,
which reveal the transmission mode, whether the bus is busy or idle, and whether the bus is held by this I2C module waiting for a soft-
ware response.
The possible values of the STATE field are summarized in Table 16.7 I2C STATE Values on page 553. When this field is cleared, the
I2C module is not a part of any ongoing transmission. The remaining status bits in the I2Cn_STATE register are listed in Table 16.8 I2C
Transmission Status on page 553.
Table 16.7. I2C STATE Values
Mode Value Description
IDLE 0 No transmission is being performed by this module.
WAIT 1 Waiting for idle. Will send a start condition as soon as the bus is idle.
START 2 Start being transmitted
ADDR 3 Address being transmitted or has been received
ADDRACK 4 Address ACK/NACK being transmitted or received
DATA 5 Data being transmitted or received
DATAACK 6 Data ACK/NACK being transmitted or received
Table 16.8. I2C Transmission Status
MASTER Set when operating as a master. Cleared at all other times.
Bit Description
BUSY Set whenever there is activity on the bus. Whether or not this module is responsible for the activity cannot
be determined by this byte.
TRANSMITTER Set when operating as a transmitter; either a master transmitter or a slave transmitter. Cleared at all other
times
BUSHOLD Set when the bus is held by this I2C module because an action is required by software.
NACK Only valid when bus is held and STATE is ADDRACK or DATAACK. In that case it is set if a NACK was
received. In all other cases, the bit is cleared.
Note: I2Cn_STATE reflects the internal state of the I2C module, and therefore only held constant as long as the bus is held, i.e. as long
as BUSHOLD in I2Cn_STATUS is set.
16.3.9 Slave Operation
The I2C module operates in master mode by default. To enable slave operation, i.e. to allow the device to be addressed as an I2C
slave, the SLAVE bit in I2Cn_CTRL must be set. In this case the slave operates in a mixed mode, both capable of starting transmis-
sions as a master, and being addressed as a slave. When operating in the slave mode, HFPERCLK frequency must be higher than 4.2
MHz for Standard-mode, 11 MHz for Fast-mode, and 24.4 MHz for Fast-mode Plus.
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16.3.9.1 Slave State Machine
The slave state machine is shown in the following figure. The dotted lines show where I2C-specific interrupt flags are set. The full-drawn
circles show places where interaction may be required by software to let the transmission proceed.
73 D5
DD
0
41
S ADDR R A
N
ADDR W
A
N
DATA P
Sr
Arb. lost 1
71 B1
0
41
A
N
A
N
DATA P
Sr
Slave transmitter
Slave receiver
XArb. lost 1
Idle/busy
0/1
Bus state/event
Transmitted by self
Received from master
Bus state (STATE)
Interrupt flag set
Interaction required. Clock-
stretching applied until manual
or automatic interaction has
been performed
Go to state
Figure 16.13. I2C Slave State Machine
16.3.9.2 Address Recognition
The I2C module provides automatic address recognition for 7-bit addresses. 10-bit address recognition is not fully automatic, but can be
assisted by the 7-bit address comparator as shown in 16.3.11 Using 10-Bit Addresses. Address recognition is supported in all energy
modes (except EM4).
The slave address, i.e. the address which the I2C module should be addressed with, is defined in the I2Cn_SADDR register. In addition
to the address, a mask must be specified, telling the address comparator which bits of an incoming address to compare with the ad-
dress defined in I2Cn_SADDR. The mask is defined in I2Cn_SADDRMASK, and for every zero in the mask, the corresponding bit in the
slave address is treated as a don’t-care.
An incoming address that fails address recognition is automatically replied to with a NACK. Since only the bits defined by the mask are
checked, a mask with a value 0x00 will result in all addresses being accepted. A mask with a value 0x7F will only match the exact
address defined in I2Cn_SADDR, while a mask 0x70 will match all addresses where the three most significant bits in I2Cn_SADDR and
the incoming address are equal.
If GCAMEN in I2Cn_CTRL is set, the general call address is always accepted regardless of the result of the address recognition. The
start-byte, i.e. the general call address with the R/W bit set is ignored unless it is included in the defined slave address.
When an address is accepted by the address comparator, the decision of whether to ACK or NACK the address is passed to software.
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16.3.9.3 Slave Transmitter
When SLAVE in I2Cn_CTRL is set, the RSTART interrupt flag in I2Cn_IF will be set when repeated START conditions are detected.
After a START or repeated START condition, the bus master will transmit an address along with an R/W bit. If there is no room in the
receive shift register for the address, the bus will be held by the slave until room is available in the shift register. Transmission then
continues and the address is loaded into the shift register. If this address does not pass address recognition, it is automatically
NACK’ed by the slave, and the slave goes to an idle state. The address byte is in this case discarded, making the shift register ready
for a new address. It is not loaded into the receive buffer.
If the address was accepted and the R/W bit was set (R), indicating that the master wishes to read from the slave, the slave now goes
into the slave transmitter mode. Software interaction is now required to decide whether the slave wants to acknowledge the request or
not. The accepted address byte is loaded into the receive buffer like a regular data byte. If no valid interaction is pending, the bus is
held until the slave responds with a command. The slave can reject the request with a single NACK command.
The slave will in that case go to an idle state, and wait for the next start condition. To continue the transmission, the slave must make
sure data is loaded into the transmit buffer and send an ACK. The loaded data will then be transmitted to the master, and an ACK or
NACK will be received from the master.
Data transmission can also continue after a NACK if a CONT command is issued along with the NACK. This is not standard I2C howev-
er.
If the master responds with an ACK, it may expect another byte of data, and data should be made available in the transmit buffer. If
data is not available, the bus is held until data is available.
If the response is a NACK however, this is an indication of that the master has received enough bytes and wishes to end the transmis-
sion. The slave now automatically goes idle, unless CONT in I2Cn_CMD is set and data is available for transmission. The latter is not
standard I2C.
The master ends the transmission by sending a STOP or a repeated START. The SSTOP interrupt flag in I2Cn_IF is set when the
master transmits a STOP condition. If the transmission is ended with a repeated START, then the SSTOP interrupt flag is not set.
Note: The SSTOP interrupt flag in I2Cn_IF will be set regardless of whether the slave is participating in the transmission or not, as long
as SLAVE in I2Cn_CTRL is set and a STOP condition is detected
If arbitration is lost at any time during transmission, the ARBLOST interrupt flag in I2Cn_IF is set, the bus is released and the slave
goes idle.
See Table 16.9 I2C Slave Transmitter on page 555 for more information.
Table 16.9. I2C Slave Transmitter
0x41 Repeated START re-
ceived
RSTART interrupt
flag (BUSHOLD in-
terrupt flag)
RXDATA Receive and compare address
I2Cn_STA Description I2Cn_IF Required in-
teraction
Response
0x75 ADDR + R received ADDR interrupt flag ACK +
TXDATA
ACK will be sent, then DATA
RXDATA interrupt flag NACK NACK will be sent, slave goes idle
(BUSHOLD interrupt
flag)
NACK +
CONT +
TXDATA
NACK will be sent, then DATA.
— Data transmitted TXBL interrupt flag
(TXC interrupt flag)
None —
0xD5 Data transmitted, ACK
received
ACK interrupt flag
(BUSHOLD interrupt
flag)
TXDATA DATA will be transmitted
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0x41 Repeated START re-
ceived
RSTART interrupt
flag (BUSHOLD in-
terrupt flag)
RXDATA Receive and compare address
0xDD Data transmitted,
NACK received
NACK interrupt flag None The slave goes idle
(BUSHOLD interrupt
flag)
CONT +
TXDATA
DATA will be transmitted
— Stop received SSTOP interrupt flag None The slave goes idle
START START will be sent when bus becomes idle
— Arbitration lost ARBLOST interrupt
flag
None The slave goes idle
START START will be sent when the bus becomes idle
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16.3.9.4 Slave Receiver
A slave receiver operation is started in the same way as a slave transmitter operation, with the exception that the address transmitted
by the master has the R/W bit cleared (W), indicating that the master wishes to write to the slave. The slave then goes into slave receiv-
er mode.
To receive data from the master, the slave should respond to the address with an ACK and make sure space is available in the receive
buffer. Transmission will then continue, and the slave will receive a byte from the master.
If a NACK is sent without a CONT, the transmission is ended for the slave, and it goes idle. If the slave issues both the NACK and
CONT commands and has space available in the receive buffer, it will be open for continuing reception from the master.
When a byte has been received from the master, the slave must ACK or NACK the byte. The responses here are the same as for the
reception of the address byte.
The master ends the transmission by sending a STOP or a repeated START. The SSTOP interrupt flag is set when the master trans-
mits a STOP condition. If the transmission is ended with a repeated START, then the SSTOP interrupt flag in I2Cn_IF is not set.
Note: The SSTOP interrupt flag in I2Cn_IF will be set regardless of whether the slave is participating in the transmission or not, as long
as SLAVE in I2Cn_CTRL is set and a STOP condition is detected
If arbitration is lost at any time during transmission, the ARBLOST interrupt flag in I2Cn_IF is set, the bus is released and the slave
goes idle.
See Table 16.10 I2C - Slave Receiver on page 557 for more information.
Table 16.10. I2C - Slave Receiver
I2Cn_STA Description I2Cn_IF Required
interaction
Response
— Repeated START re-
ceived
RSTART interrupt flag
(BUSHOLD interrupt
flag)
RXDATA Receive and compare address
0x71 ADDR + W received ADDR interrupt flag
RXDATA interrupt flag
(BUSHOLD interrupt
flag)
ACK +
RXDATA
ACK will be sent and data will be received
NACK NACK will be sent, slave goes idle
NACK +
CONT +
RXDATA
NACK will be sent and DATA will be received.
0xB1 Data received RXDATA interrupt flag
(BUSHOLD interrupt
flag)
ACK +
RXDATA
ACK will be sent and data will be received
NACK NACK will be sent and slave will go idle
NACK +
CONT +
RXDATA
NACK will be sent and data will be received
— Stop received SSTOP interrupt flag None The slave goes idle
START START will be sent when bus becomes idle
— Arbitration lost ARBLOST interrupt
flag
None The slave goes idle
START START will be sent when the bus becomes idle
16.3.10 Transfer Automation
The I2C can be set up to complete transfers with a minimal amount of interaction.
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16.3.10.1 DMA
DMA can be used to automatically load data into the transmit buffer and load data out from the receive buffer. When using DMA, soft-
ware is thus relieved of moving data to and from memory after each transferred byte.
16.3.10.2 Automatic ACK
When AUTOACK in I2Cn_CTRL is set, an ACK is sent automatically whenever an ACK interaction is possible and no higher priority
interactions are pending.
16.3.10.3 Automatic STOP
A STOP can be generated automatically on two conditions. These apply only to the master transmitter.
If AUTOSN in I2Cn_CTRL is set, the I2C module ends a transmission by transmitting a STOP condition when operating as a master
transmitter and a NACK is received.
If AUTOSE in I2Cn_CTRL is set, the I2C module always ends a transmission when there is no more data in the transmit buffer. If data
has been transmitted on the bus, the transmission is ended after the (N)ACK has been received by the slave. If a START is sent when
no data is available in the transmit buffer and AUTOSE is set, then the STOP condition is sent immediately following the START. Soft-
ware must thus make sure data is available in the transmit buffer before the START condition has been fully transmitted if data is to be
transferred.
16.3.11 Using 10-Bit Addresses
When using 10-bit addresses in slave mode, set the I2Cn_SADDR register to 1111 0XX where XX are the two most significant bits of
the 10-bit address, and set I2Cn_SADDRMASK to 0xFF. Address matches will now be given on all 10-bit addresses where the two
most significant bits are correct.
When receiving an address match, the slave must acknowledge the address and receive the first data byte. This byte contains the sec-
ond part of the 10-bit address. If it matches the address of the slave, the slave should ACK the byte to continue the transmission, and if
it does not match, the slave should NACK it.
When the master is operating as a master transmitter, the data bytes will follow after the second address byte. When the master is
operating as a master receiver however, a repeated START condition is sent after the second address byte. The address sent after this
repeated START is equal to the first of the address bytes transmitted previously, but now with the R/W byte set, and only the slave that
found a match on the entire 10-bit address in the previous message should ACK this address. The repeated start should take the mas-
ter into a master receiver mode, and after the single address byte sent this time around, the slave begins transmission to the master.
16.3.12 Error Handling
16.3.12.1 ABORT Command
Some bus errors may require software intervention to be resolved. The I2C module provides an ABORT command, which can be set in
I2Cn_CMD, to help resolve bus errors.
When the bus for some reason is locked up and the I2C module is in the middle of a transmission it cannot get out of, or for some other
reason the I2C wants to abort a transmission, the ABORT command can be used.
Setting the ABORT command will make the I2C module discard any data currently being transmitted or received, release the SDA and
SCL lines and go to an idle mode. ABORT effectively makes the I2C module forget about any ongoing transfers.
16.3.12.2 Bus Reset
A bus reset can be performed by setting the START and STOP commands in I2Cn_CMD while the transmit buffer is empty. A START
condition will then be transmitted, immediately followed by a STOP condition. A bus reset can also be performed by transmitting a
START command with the transmit buffer empty and AUTOSE set.
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16.3.12.3 I2C-Bus Errors
An I2C-bus error occurs when a START or STOP condition is misplaced, which happens when the value on SDA changes while SCL is
high during bit-transmission on the I2C-bus. If the I2C module is part of the current transmission when a bus error occurs, any data
currently being transmitted or received is discarded, SDA and SCL are released, the BUSERR interrupt flag in I2Cn_IF is set to indicate
the error, and the module automatically takes a course of action as defined in Table 16.11 I2C Bus Error Response on page 559.
Table 16.11. I2C Bus Error Response
Misplaced START Misplaced STOP
In a master/slave operation Treated as START. Receive address. Go idle. Perform any pending actions.
16.3.12.4 Bus Lockup
A lockup occurs when a master or slave on the I2C-bus has locked the SDA or SCL at a low value, preventing other devices from put-
ting high values on the bus, and thus making communication on the bus impossible.
Many slave-only devices operating on an I2C-bus are not capable of driving SCL low, but in the rare case that SCL is stuck LOW, the
advice is to apply a hardware reset signal to the slaves on the bus. If this does not work, cycle the power to the devices in order to
make them release SCL.
When SDA is stuck low and SCL is free, a master should send 9 clock pulses on SCL while tristating the SDA. This procedure is per-
formed in the GPIO module after clearing the I2C_ROUTE register and disabling the I2C module. The device that held the bus low
should release it sometime within those 9 clocks. If not, use the same approach as for when SCL is stuck, resetting and possibly cycling
power to the slaves.
Lockup of SDA can be detected by keeping count of the number of continuous arbitration losses during address transmission. If arbitra-
tion is also lost during the transmission of a general call address, i.e. during the transmission of the STOP condition, which should nev-
er happen during normal operation, this is a good indication of SDA lockup.
Detection of SCL lockups can be done using the timeout functionality defined in 16.3.12.6 Clock Low Timeout.
16.3.12.5 Bus Idle Timeout
When SCL has been high for a significant amount of time, this is a good indication of that the bus is idle. On an SMBus system, the bus
is only allowed to be in this state for a maximum of 50 μs before the bus is considered idle.
The bus idle timeout BITO in I2Cn_CTRL can be used to detect situations where the bus goes idle in the middle of a transmission. The
timeout can be configured in BITO, and when the bus has been idle for the given amount of time, the BITO interrupt flag in I2Cn_IF is
set. The bus can also be set idle automatically on a bus idle timeout. This is enabled by setting GIBITO in I2Cn_CTRL.
When the bus idle timer times out, it wraps around and continues counting as long as its condition is true. If the bus is not set idle using
GIBITO or the ABORT command in I2Cn_CMD, this will result in periodic timeouts.
Note: This timeout will be generated even if SDA is held low.
The bus idle timeout is active as long as the bus is busy, i.e. BUSY in I2Cn_STATUS is set. The timeout can be used to get the I2C
module out of the busy-state it enters when reset, see 16.3.7.3 Reset State.
16.3.12.6 Clock Low Timeout
The clock timeout, which can be configured in CLTO in I2Cn_CTRL, starts counting whenever SCL goes low, and times out if SCL does
not go high within the configured timeout. A clock low timeout results in CLTOIF in I2Cn_IF being set, allowing software to take action.
When the timer times out, it wraps around and continues counting as long as SCL is low. An SCL lockup will thus result in periodic
clock low timeouts as long as SCL is low.
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16.3.13 DMA Support
The I2C module has full DMA support. The DMA controller can write to the transmit buffer using the I2Cn_TXDATA register, and it can
read from the receive buffer using the RXDATA register. A request for the DMA controller to read from the I2C receive buffer can come
from the following source:
• Data available in the receive buffer
A write request can come from one of the following sources:
• Transmit buffer and shift register empty. No data to send
• Transmit buffer empty
16.3.14 Interrupts
The interrupts generated by the I2C module are combined into one interrupt vector, I2C_INT. If I2C interrupts are enabled, an interrupt
will be made if one or more of the interrupt flags in I2Cn_IF and their corresponding bits in I2Cn_IEN are set.
16.3.15 Wake-Up
The I2C receive section can be active all the way down to energy mode EM3, and can wake up the CPU on address interrupt. All ad-
dress match modes are supported.
16.4 Register Map
The offset register address is relative to the registers base address.
Offset Name Type Description
0x000 I2Cn_CTRL RW Control Register
0x004 I2Cn_CMD W1 Command Register
0x008 I2Cn_STATE RState Register
0x00C I2Cn_STATUS RStatus Register
0x010 I2Cn_CLKDIV RW Clock Division Register
0x014 I2Cn_SADDR RW Slave Address Register
0x018 I2Cn_SADDRMASK RW Slave Address Mask Register
0x01C I2Cn_RXDATA R(a) Receive Buffer Data Register
0x020 I2Cn_RXDATAP RReceive Buffer Data Peek Register
0x024 I2Cn_TXDATA WTransmit Buffer Data Register
0x028 I2Cn_IF RInterrupt Flag Register
0x02C I2Cn_IFS W1 Interrupt Flag Set Register
0x030 I2Cn_IFC (R)W1 Interrupt Flag Clear Register
0x034 I2Cn_IEN RW Interrupt Enable Register
0x038 I2Cn_ROUTE RW I/O Routing Register
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16.5 Register Description
16.5.1 I2Cn_CTRL - Control Register
Offset Bit Position
0x000
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
16
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
Reset
0x0
0
0x0
0x0
0
0
0
0
0
0
0
Access
RW
RW
RW
RW
RW
RW
RW
RW
RW
RW
RW
Name
CLTO
GIBITO
BITO
CLHR
GCAMEN
ARBDIS
AUTOSN
AUTOSE
AUTOACK
SLAVE
EN
Bit Name Reset Access Description
31:19 Reserved To ensure compatibility with future devices, always write bits to 0. More information in 2.1 Conven-
tions.
18:16 CLTO 0x0 RW Clock Low Timeout
Use to generate a timeout when CLK has been low for the given amount of time. Wraps around and continues counting
when the timeout is reached.
Value Mode Description
0 OFF Timeout disabled
1 40PCC Timeout after 40 prescaled clock cycles. In standard mode at 100 kHz,
this results in a 50us timeout.
2 80PCC Timeout after 80 prescaled clock cycles. In standard mode at 100 kHz,
this results in a 100us timeout.
3 160PCC Timeout after 160 prescaled clock cycles. In standard mode at 100
kHz, this results in a 200us timeout.
4 320PPC Timeout after 320 prescaled clock cycles. In standard mode at 100
kHz, this results in a 400us timeout.
5 1024PPC Timeout after 1024 prescaled clock cycles. In standard mode at 100
kHz, this results in a 1280us timeout.
15 GIBITO 0 RW Go Idle on Bus Idle Timeout
When set, the bus automatically goes idle on a bus idle timeout, allowing new transfers to be initiated.
Value Description
0 A bus idle timeout has no effect on the bus state.
1A bus idle timeout tells the I2C module that the bus is idle, allowing new
transfers to be initiated.
14 Reserved To ensure compatibility with future devices, always write bits to 0. More information in 2.1 Conven-
tions.
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Bit Name Reset Access Description
13:12 BITO 0x0 RW Bus Idle Timeout
Use to generate a timeout when SCL has been high for a given amount time between a START and STOP condition. When
in a bus transaction, i.e. the BUSY flag is set, a timer is started whenever SCL goes high. When the timer reaches the value
defined by BITO, it sets the BITO interrupt flag. The BITO interrupt flag will then be set periodically as long as SCL remains
high. The bus idle timeout is active as long as BUSY is set. It is thus stopped automatically on a timeout if GIBITO is set. It
is also stopped a STOP condition is detected and when the ABORT command is issued. The timeout is activated whenever
the bus goes BUSY, i.e. a START condition is detected.
Value Mode Description
0 OFF Timeout disabled
1 40PCC Timeout after 40 prescaled clock cycles. In standard mode at 100 kHz,
this results in a 50us timeout.
2 80PCC Timeout after 80 prescaled clock cycles. In standard mode at 100 kHz,
this results in a 100us timeout.
3 160PCC Timeout after 160 prescaled clock cycles. In standard mode at 100
kHz, this results in a 200us timeout.
11:10 Reserved To ensure compatibility with future devices, always write bits to 0. More information in 2.1 Conven-
tions.
9:8 CLHR 0x0 RW Clock Low High Ratio
Determines the ratio between the low and high parts of the clock signal generated on SCL as master.
Value Mode Description
0 STANDARD The ratio between low period and high period counters (Nlow:Nhigh) is
4:4
1 ASYMMETRIC The ratio between low period and high period counters (Nlow:Nhigh) is
6:3
2 FAST The ratio between low period and high period counters (Nlow:Nhigh) is
11:6
7 Reserved To ensure compatibility with future devices, always write bits to 0. More information in 2.1 Conven-
tions.
6 GCAMEN 0 RW General Call Address Match Enable
Set to enable address match on general call in addition to the programmed slave address.
Value Description
0 General call address will be NACK'ed if it is not included by the slave
address and address mask.
1 When a general call address is received, a software response is re-
quired.
5 ARBDIS 0 RW Arbitration Disable
A master or slave will not release the bus upon losing arbitration.
Value Description
0 When a device loses arbitration, the ARB interrupt flag is set and the
bus is released.
1 When a device loses arbitration, the ARB interrupt flag is set, but com-
munication proceeds.
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Bit Name Reset Access Description
4 AUTOSN 0 RW Automatic STOP on NACK
Write to 1 to make a master transmitter send a STOP when a NACK is received from a slave.
Value Description
0 Stop is not automatically sent if a NACK is received from a slave.
1 The master automatically sends a STOP if a NACK is received from a
slave.
3 AUTOSE 0 RW Automatic STOP when Empty
Write to 1 to make a master transmitter send a STOP when no more data is available for transmission.
Value Description
0 A stop must be sent manually when no more data is to be transmitted.
1 The master automatically sends a STOP when no more data is availa-
ble for transmission.
2 AUTOACK 0 RW Automatic Acknowledge
Set to enable automatic acknowledges.
Value Description
0 Software must give one ACK command for each ACK transmitted on
the I2C bus.
1 Addresses that are not automatically NACK'ed, and all data is automat-
ically acknowledged.
1 SLAVE 0 RW Addressable as Slave
Set this bit to allow the device to be selected as an I2C slave.
Value Description
0 All addresses will be responded to with a NACK
1 Addresses matching the programmed slave address or the general call
address (if enabled) require a response from software. Other address-
es are automatically responded to with a NACK.
0 EN 0 RW I2C Enable
Use this bit to enable or disable the I2C module.
Value Description
0The I2C module is disabled. And its internal state is cleared
1The I2C module is enabled.
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16.5.2 I2Cn_CMD - Command Register
Offset Bit Position
0x004
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
16
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
Reset
0
0
0
0
0
0
0
0
Access
W1
W1
W1
W1
W1
W1
W1
W1
Name
CLEARPC
CLEARTX
ABORT
CONT
NACK
ACK
STOP
START
Bit Name Reset Access Description
31:8 Reserved To ensure compatibility with future devices, always write bits to 0. More information in 2.1 Conven-
tions.
7 CLEARPC 0 W1 Clear Pending Commands
Set to clear pending commands.
6 CLEARTX 0 W1 Clear TX
Set to clear transmit buffer and shift register. Will not abort ongoing transfer.
5 ABORT 0 W1 Abort transmission
Abort the current transmission making the bus go idle. When used in combination with STOP, a STOP condition is sent as
soon as possible before aborting the transmission. The stop condition is subject to clock synchronization.
4 CONT 0 W1 Continue transmission
Set to continue transmission after a NACK has been received.
3 NACK 0 W1 Send NACK
Set to transmit a NACK the next time an acknowledge is required.
2 ACK 0 W1 Send ACK
Set to transmit an ACK the next time an acknowledge is required.
1 STOP 0 W1 Send stop condition
Set to send stop condition as soon as possible.
0 START 0 W1 Send start condition
Set to send start condition as soon as possible. If a transmission is ongoing and not owned, the start condition will be sent
as soon as the bus is idle. If the current transmission is owned by this module, a repeated start condition will be sent. Use
in combination with a STOP command to automatically send a STOP, then a START when the bus becomes idle.
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16.5.3 I2Cn_STATE - State Register
Offset Bit Position
0x008
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
16
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
Reset
0x0
0
0
0
0
1
Access
R
R
R
R
R
R
Name
STATE
BUSHOLD
NACKED
TRANSMITTER
MASTER
BUSY
Bit Name Reset Access Description
31:8 Reserved To ensure compatibility with future devices, always write bits to 0. More information in 2.1 Conven-
tions.
7:5 STATE 0x0 R Transmission State
The state of any current transmission. Cleared if the I2C module is idle.
Value Mode Description
0 IDLE No transmission is being performed.
1 WAIT Waiting for idle. Will send a start condition as soon as the bus is idle.
2 START Start transmitted or received
3 ADDR Address transmitted or received
4 ADDRACK Address ack/nack transmitted or received
5 DATA Data transmitted or received
6 DATAACK Data ack/nack transmitted or received
4 BUSHOLD 0 R Bus Held
Set if the bus is currently being held by this I2C module.
3 NACKED 0 R Nack Received
Set if a NACK was received and STATE is ADDRACK or DATAACK.
2 TRANSMITTER 0 R Transmitter
Set when operating as a master transmitter or a slave transmitter. When cleared, the system may be operating as a master
receiver, a slave receiver or the current mode is not known.
1 MASTER 0 R Master
Set when operating as an I2C master. When cleared, the system may be operating as an I2C slave.
0 BUSY 1 R Bus Busy
Set when the bus is busy. Whether the I2C module is in control of the bus or not has no effect on the value of this bit. When
the MCU comes out of reset, the state of the bus is not known, and thus BUSY is set. Use the ABORT command or a bus
idle timeout to force the I2C module out of the BUSY state.
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16.5.4 I2Cn_STATUS - Status Register
Offset Bit Position
0x00C
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
16
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
Reset
0
1
0
0
0
0
0
0
0
Access
R
R
R
R
R
R
R
R
R
Name
RXDATAV
TXBL
TXC
PABORT
PCONT
PNACK
PACK
PSTOP
PSTART
Bit Name Reset Access Description
31:9 Reserved To ensure compatibility with future devices, always write bits to 0. More information in 2.1 Conven-
tions.
8 RXDATAV 0 R RX Data Valid
Set when data is available in the receive buffer. Cleared when the receive buffer is empty.
7 TXBL 1 R TX Buffer Level
Indicates the level of the transmit buffer. Set when the transmit buffer is empty, and cleared when it is full.
6 TXC 0 R TX Complete
Set when a transmission has completed and no more data is available in the transmit buffer. Cleared when a new transmis-
sion starts.
5 PABORT 0 R Pending abort
An abort is pending and will be transmitted as soon as possible.
4 PCONT 0 R Pending continue
A continue is pending and will be transmitted as soon as possible.
3 PNACK 0 R Pending NACK
A not-acknowledge is pending and will be transmitted as soon as possible.
2 PACK 0 R Pending ACK
An acknowledge is pending and will be transmitted as soon as possible.
1 PSTOP 0 R Pending STOP
A stop condition is pending and will be transmitted as soon as possible.
0 PSTART 0 R Pending START
A start condition is pending and will be transmitted as soon as possible.
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16.5.5 I2Cn_CLKDIV - Clock Division Register
Offset Bit Position
0x010
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
16
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
Reset
0x000
Access
RW
Name
DIV
Bit Name Reset Access Description
31:9 Reserved To ensure compatibility with future devices, always write bits to 0. More information in 2.1 Conven-
tions.
8:0 DIV 0x000 RW Clock Divider
Specifies the clock divider for the I2C. Note that DIV must be 1 or higher when slave is enabled.
16.5.6 I2Cn_SADDR - Slave Address Register
Offset Bit Position
0x014
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
16
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
Reset
0x00
Access
RW
Name
ADDR
Bit Name Reset Access Description
31:8 Reserved To ensure compatibility with future devices, always write bits to 0. More information in 2.1 Conven-
tions.
7:1 ADDR 0x00 RW Slave address
Specifies the slave address of the device.
0 Reserved To ensure compatibility with future devices, always write bits to 0. More information in 2.1 Conven-
tions.
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16.5.7 I2Cn_SADDRMASK - Slave Address Mask Register
Offset Bit Position
0x018
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
16
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
Reset
0x00
Access
RW
Name
MASK
Bit Name Reset Access Description
31:8 Reserved To ensure compatibility with future devices, always write bits to 0. More information in 2.1 Conven-
tions.
7:1 MASK 0x00 RW Slave Address Mask
Specifies the significant bits of the slave address. Setting the mask to 0x00 will match all addresses, while setting it to 0x7F
will only match the exact address specified by ADDR.
0 Reserved To ensure compatibility with future devices, always write bits to 0. More information in 2.1 Conven-
tions.
16.5.8 I2Cn_RXDATA - Receive Buffer Data Register (Actionable Reads)
Offset Bit Position
0x01C
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
16
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
Reset
0x00
Access
R
Name
RXDATA
Bit Name Reset Access Description
31:8 Reserved To ensure compatibility with future devices, always write bits to 0. More information in 2.1 Conven-
tions.
7:0 RXDATA 0x00 R RX Data
Use this register to read from the receive buffer. Buffer is emptied on read access.
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16.5.9 I2Cn_RXDATAP - Receive Buffer Data Peek Register
Offset Bit Position
0x020
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
16
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
Reset
0x00
Access
R
Name
RXDATAP
Bit Name Reset Access Description
31:8 Reserved To ensure compatibility with future devices, always write bits to 0. More information in 2.1 Conven-
tions.
7:0 RXDATAP 0x00 R RX Data Peek
Use this register to read from the receive buffer. Buffer is not emptied on read access.
16.5.10 I2Cn_TXDATA - Transmit Buffer Data Register
Offset Bit Position
0x024
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
16
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
Reset
0x00
Access
W
Name
TXDATA
Bit Name Reset Access Description
31:8 Reserved To ensure compatibility with future devices, always write bits to 0. More information in 2.1 Conven-
tions.
7:0 TXDATA 0x00 W TX Data
Use this register to write a byte to the transmit buffer.
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16.5.11 I2Cn_IF - Interrupt Flag Register
Offset Bit Position
0x028
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
16
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
Reset
0
0
0
0
0
0
0
0
0
0
0
0
1
0
0
0
0
Access
R
R
R
R
R
R
R
R
R
R
R
R
R
R
R
R
R
Name
SSTOP
CLTO
BITO
RXUF
TXOF
BUSHOLD
BUSERR
ARBLOST
MSTOP
NACK
ACK
RXDATAV
TXBL
TXC
ADDR
RSTART
START
Bit Name Reset Access Description
31:17 Reserved To ensure compatibility with future devices, always write bits to 0. More information in 2.1 Conven-
tions.
16 SSTOP 0 R Slave STOP condition Interrupt Flag
Set when a STOP condition has been received. Will be set regardless of the EFM32 being involved in the transaction or
not.
15 CLTO 0 R Clock Low Timeout Interrupt Flag
Set on each clock low timeout. The timeout value can be set in CLTO bit field in the I2Cn_CTRL register.
14 BITO 0 R Bus Idle Timeout Interrupt Flag
Set on each bus idle timeout. The timeout value can be set in the BITO bit field in the I2Cn_CTRL register.
13 RXUF 0 R Receive Buffer Underflow Interrupt Flag
Set when data is read from the receive buffer through the I2Cn_RXDATA register while the receive buffer is empty.
12 TXOF 0 R Transmit Buffer Overflow Interrupt Flag
Set when data is written to the transmit buffer while the transmit buffer is full.
11 BUSHOLD 0 R Bus Held Interrupt Flag
Set when the bus becomes held by the I2C module.
10 BUSERR 0 R Bus Error Interrupt Flag
Set when a bus error is detected. The bus error is resolved automatically, but the current transfer is aborted.
9 ARBLOST 0 R Arbitration Lost Interrupt Flag
Set when arbitration is lost.
8 MSTOP 0 R Master STOP Condition Interrupt Flag
Set when a STOP condition has been successfully transmitted. If arbitration is lost during the transmission of the STOP
condition, then the MSTOP interrupt flag is not set.
7 NACK 0 R Not Acknowledge Received Interrupt Flag
Set when a NACK has been received.
6 ACK 0 R Acknowledge Received Interrupt Flag
Set when an ACK has been received.
5 RXDATAV 0 R Receive Data Valid Interrupt Flag
Set when data is available in the receive buffer. Cleared automatically when the receive buffer is read.
4 TXBL 1 R Transmit Buffer Level Interrupt Flag
Set when the transmit buffer becomes empty. Cleared automatically when new data is written to the transmit buffer.
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Bit Name Reset Access Description
3 TXC 0 R Transfer Completed Interrupt Flag
Set when the transmit shift register becomes empty and there is no more data in the transmit buffer.
2 ADDR 0 R Address Interrupt Flag
Set when incoming address is accepted, i.e. own address or general call address is received.
1 RSTART 0 R Repeated START condition Interrupt Flag
Set when a repeated start condition is detected.
0 START 0 R START condition Interrupt Flag
Set when a start condition is successfully transmitted.
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16.5.12 I2Cn_IFS - Interrupt Flag Set Register
Offset Bit Position
0x02C
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
16
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
Reset
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
Access
W1
W1
W1
W1
W1
W1
W1
W1
W1
W1
W1
W1
W1
W1
W1
Name
SSTOP
CLTO
BITO
RXUF
TXOF
BUSHOLD
BUSERR
ARBLOST
MSTOP
NACK
ACK
TXC
ADDR
RSTART
START
Bit Name Reset Access Description
31:17 Reserved To ensure compatibility with future devices, always write bits to 0. More information in 2.1 Conven-
tions.
16 SSTOP 0 W1 Set SSTOP Interrupt Flag
Write to 1 to set the SSTOP interrupt flag.
15 CLTO 0 W1 Set Clock Low Interrupt Flag
Write to 1 to set the CLTO interrupt flag.
14 BITO 0 W1 Set Bus Idle Timeout Interrupt Flag
Write to 1 to set the BITO interrupt flag.
13 RXUF 0 W1 Set Receive Buffer Underflow Interrupt Flag
Write to 1 to set the RXUF interrupt flag.
12 TXOF 0 W1 Set Transmit Buffer Overflow Interrupt Flag
Write to 1 to set the TXOF interrupt flag.
11 BUSHOLD 0 W1 Set Bus Held Interrupt Flag
Write to 1 to set the BUSHOLD interrupt flag.
10 BUSERR 0 W1 Set Bus Error Interrupt Flag
Write to 1 to set the BUSERR interrupt flag.
9 ARBLOST 0 W1 Set Arbitration Lost Interrupt Flag
Write to 1 to set the ARBLOST interrupt flag.
8 MSTOP 0 W1 Set MSTOP Interrupt Flag
Write to 1 to set the MSTOP interrupt flag.
7 NACK 0 W1 Set Not Acknowledge Received Interrupt Flag
Write to 1 to set the NACK interrupt flag.
6 ACK 0 W1 Set Acknowledge Received Interrupt Flag
Write to 1 to set the ACK interrupt flag.
5:4 Reserved To ensure compatibility with future devices, always write bits to 0. More information in 2.1 Conven-
tions.
3 TXC 0 W1 Set Transfer Completed Interrupt Flag
Write to 1 to set the TXC interrupt flag.
2 ADDR 0 W1 Set Address Interrupt Flag
Write to 1 to set the ADDR interrupt flag.
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Bit Name Reset Access Description
1 RSTART 0 W1 Set Repeated START Interrupt Flag
Write to 1 to set the RSTART interrupt flag.
0 START 0 W1 Set START Interrupt Flag
Write to 1 to set the START interrupt flag.
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16.5.13 I2Cn_IFC - Interrupt Flag Clear Register
Offset Bit Position
0x030
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
16
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
Reset
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
Access
(R)W1
(R)W1
(R)W1
(R)W1
(R)W1
(R)W1
(R)W1
(R)W1
(R)W1
(R)W1
(R)W1
(R)W1
(R)W1
(R)W1
(R)W1
Name
SSTOP
CLTO
BITO
RXUF
TXOF
BUSHOLD
BUSERR
ARBLOST
MSTOP
NACK
ACK
TXC
ADDR
RSTART
START
Bit Name Reset Access Description
31:17 Reserved To ensure compatibility with future devices, always write bits to 0. More information in 2.1 Conven-
tions.
16 SSTOP 0 (R)W1 Clear SSTOP Interrupt Flag
Write to 1 to clear the SSTOP interrupt flag.
15 CLTO 0 (R)W1 Clear Clock Low Interrupt Flag
Write to 1 to clear the CLTO interrupt flag.
14 BITO 0 (R)W1 Clear Bus Idle Timeout Interrupt Flag
Write to 1 to clear the BITO interrupt flag.
13 RXUF 0 (R)W1 Clear Receive Buffer Underflow Interrupt Flag
Write to 1 to clear the RXUF interrupt flag.
12 TXOF 0 (R)W1 Clear Transmit Buffer Overflow Interrupt Flag
Write to 1 to clear the TXOF interrupt flag.
11 BUSHOLD 0 (R)W1 Clear Bus Held Interrupt Flag
Write to 1 to clear the BUSHOLD interrupt flag.
10 BUSERR 0 (R)W1 Clear Bus Error Interrupt Flag
Write to 1 to clear the BUSERR interrupt flag.
9 ARBLOST 0 (R)W1 Clear Arbitration Lost Interrupt Flag
Write to 1 to clear the ARBLOST interrupt flag.
8 MSTOP 0 (R)W1 Clear MSTOP Interrupt Flag
Write to 1 to clear the MSTOP interrupt flag.
7 NACK 0 (R)W1 Clear Not Acknowledge Received Interrupt Flag
Write to 1 to clear the NACK interrupt flag.
6 ACK 0 (R)W1 Clear Acknowledge Received Interrupt Flag
Write to 1 to clear the ACK interrupt flag.
5:4 Reserved To ensure compatibility with future devices, always write bits to 0. More information in 2.1 Conven-
tions.
3 TXC 0 (R)W1 Clear Transfer Completed Interrupt Flag
Write to 1 to clear the TXC interrupt flag.
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Bit Name Reset Access Description
2 ADDR 0 (R)W1 Clear Address Interrupt Flag
Write to 1 to clear the ADDR interrupt flag.
1 RSTART 0 (R)W1 Clear Repeated START Interrupt Flag
Write to 1 to clear the RSTART interrupt flag.
0 START 0 (R)W1 Clear START Interrupt Flag
Write to 1 to clear the START interrupt flag.
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16.5.14 I2Cn_IEN - Interrupt Enable Register
Offset Bit Position
0x034
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
16
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
Reset
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
Access
RW
RW
RW
RW
RW
RW
RW
RW
RW
RW
RW
RW
RW
RW
RW
RW
RW
Name
SSTOP
CLTO
BITO
RXUF
TXOF
BUSHOLD
BUSERR
ARBLOST
MSTOP
NACK
ACK
RXDATAV
TXBL
TXC
ADDR
RSTART
START
Bit Name Reset Access Description
31:17 Reserved To ensure compatibility with future devices, always write bits to 0. More information in 2.1 Conven-
tions.
16 SSTOP 0 RW SSTOP Interrupt Enable
Enable interrupt on SSTOP.
15 CLTO 0 RW Clock Low Interrupt Enable
Enable interrupt on clock low timeout.
14 BITO 0 RW Bus Idle Timeout Interrupt Enable
Enable interrupt on bus idle timeout.
13 RXUF 0 RW Receive Buffer Underflow Interrupt Enable
Enable interrupt on receive buffer underflow.
12 TXOF 0 RW Transmit Buffer Overflow Interrupt Enable
Enable interrupt on transmit buffer overflow.
11 BUSHOLD 0 RW Bus Held Interrupt Enable
Enable interrupt on bus-held.
10 BUSERR 0 RW Bus Error Interrupt Enable
Enable interrupt on bus error.
9 ARBLOST 0 RW Arbitration Lost Interrupt Enable
Enable interrupt on loss of arbitration.
8 MSTOP 0 RW MSTOP Interrupt Enable
Enable interrupt on MSTOP.
7 NACK 0 RW Not Acknowledge Received Interrupt Enable
Enable interrupt when not-acknowledge is received.
6 ACK 0 RW Acknowledge Received Interrupt Enable
Enable interrupt on acknowledge received.
5 RXDATAV 0 RW Receive Data Valid Interrupt Enable
Enable interrupt on receive buffer full.
4 TXBL 0 RW Transmit Buffer level Interrupt Enable
Enable interrupt on transmit buffer level.
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Bit Name Reset Access Description
3 TXC 0 RW Transfer Completed Interrupt Enable
Enable interrupt on transfer completed.
2 ADDR 0 RW Address Interrupt Enable
Enable interrupt on recognized address.
1 RSTART 0 RW Repeated START condition Interrupt Enable
Enable interrupt on transmitted or received repeated START condition.
0 START 0 RW START Condition Interrupt Enable
Enable interrupt on transmitted or received START condition.
16.5.15 I2Cn_ROUTE - I/O Routing Register
Offset Bit Position
0x038
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
16
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
Reset
0x0
0
0
Access
RW
RW
RW
Name
LOCATION
SCLPEN
SDAPEN
Bit Name Reset Access Description
31:11 Reserved To ensure compatibility with future devices, always write bits to 0. More information in 2.1 Conven-
tions.
10:8 LOCATION 0x0 RW I/O Location
Decides the location of the I2C I/O pins.
Value Mode Description
0 LOC0 Location 0
1 LOC1 Location 1
2 LOC2 Location 2
3 LOC3 Location 3
4 LOC4 Location 4
5 LOC5 Location 5
6 LOC6 Location 6
7:2 Reserved To ensure compatibility with future devices, always write bits to 0. More information in 2.1 Conven-
tions.
1 SCLPEN 0 RW SCL Pin Enable
When set, the SCL pin of the I2C is enabled.
0 SDAPEN 0 RW SDA Pin Enable
When set, the SDA pin of the I2C is enabled.
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17. USART - Universal Synchronous Asynchronous Receiver/Transmitter
43210
Device
USART
RX/
MISO
TX/
MOSI
DMA
controller
RAM
CLK
CS
SPI
USART
SmartCards
IrDA
Quick Facts
What?
The USART handles high-speed UART, SPIbus,
SmartCards, and IrDA communication.
Why?
Serial communication is frequently used in embed-
ded systems and the USART allows efficient com-
munication with a wide range of external devices.
How?
The USART has a wide selection of operating
modes, frame formats and baud rates. The multi-
processor mode allows the USART to remain idle
when not addressed. Triple buffering and DMA sup-
port makes high datarates possible with minimal
CPU intervention and it is possible to transmit and
receive large frames while the MCU remains in EM1.
17.1 Introduction
The Universal Synchronous Asynchronous serial Receiver and Transmitter (USART) is a very flexible serial I/O module. It supports full
duplex asynchronous UART communication as well as RS-485, SPI, MicroWire and 3-wire. It can also interface with ISO7816 Smart-
Cards, and IrDA devices.
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17.2 Features
• Asynchronous and synchronous (SPI) communication
• Full duplex and half duplex
• Separate TX/RX enable
• Separate receive / transmit 2-level buffers, with additional separate shift registers
• Programmable baud rate, generated as an fractional division from the peripheral clock (HFPERCLKUSARTn)
• Max bit-rate
• SPI master mode, peripheral clock rate/2
• SPI slave mode, peripheral clock rate/8
• UART mode, peripheral clock rate/16, 8, 6, or 4
• Asynchronous mode supports
• Majority vote baud-reception
• False start-bit detection
• Break generation/detection
• Multi-processor mode
• Synchronous mode supports
• All 4 SPI clock polarity/phase configurations
• Master and slave mode
• Data can be transmitted LSB first or MSB first
• Configurable number of data bits, 4-16 (plus the parity bit, if enabled)
• HW parity bit generation and check
• Configurable number of stop bits in asynchronous mode: 0.5, 1, 1.5, 2
• HW collision detection
• Multi-processor mode
• IrDA modulator on USART0
• SmartCard (ISO7816) mode
• I2S mode
• Separate interrupt vectors for receive and transmit interrupts
• Loopback mode
• Half duplex communication
• Communication debugging
• PRS RX input
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17.3 Functional Description
An overview of the USART module is shown in the following figure.
TX Buffer
(2-level FIFO)
TX Shift Register
U(S)n_TX
RX Buffer
(2-level FIFO)
RX Shift Register
UART Control
and status
Peripheral Bus
Baud rate
generator
USn_CLK Pin
ctrl
USn_CS
U(S)n_RX
IrDA
modulator
IrDA
demodulator
!RXBLOCK
Figure 17.1. USART Overview
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17.3.1 Modes of Operation
The USART operates in either asynchronous or synchronous mode.
In synchronous mode, a separate clock signal is transmitted with the data. This clock signal is generated by the bus master, and both
the master and slave sample and transmit data according to this clock. Both master and slave modes are supported by the USART.
The synchronous communication mode is compatible with the Serial Peripheral Interface Bus (SPI) standard.
In asynchronous mode, no separate clock signal is transmitted with the data on the bus. The USART receiver thus has to determine
where to sample the data on the bus from the actual data. To make this possible, additional synchronization bits are added to the data
when operating in asynchronous mode, resulting in a slight overhead.
Asynchronous or synchronous mode can be selected by configuring SYNC in USARTn_CTRL. The options are listed with supported
protocols in the following. Full duplex and half duplex communication is supported in both asynchronous and synchronous mode.
Table 17.1. USART Asynchronous vs. Synchronous Mode
SYNC Communication Mode Supported Protocols
0 Asynchronous RS-232, RS-485 (w/external driver), IrDA,
ISO 7816
1 Synchronous SPI, MicroWire, 3-wire
The following table explains the functionality of the different USART pins when the USART operates in different modes. Pin functionality
enclosed in square brackets is optional, and depends on additional configuration parameters. LOOPBK and MASTER are discussed in
17.3.2.5 Local Loopback and 17.3.3.3 Master Mode respectively.
Table 17.2. USART Pin Usage
SYNC LOOPBK MASTER Pin functionality
U(S)n_TX (MO-
SI)
U(S)n_RX (MI-
SO)
USn_CLK USn_CS
0 0 x Data out Data in – [Driver enable]
1 1 x Data out/in – – [Driver enable]
1 0 0 Data in Data out Clock in Slave select
1 0 1 Data out Data in Clock out [Auto slave se-
lect]
1 1 0 Data out/in – Clock in Slave select
1 1 1 Data out/in – Clock out Auto slave select]
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17.3.2 Asynchronous Operation
17.3.2.1 Frame Format
The frame format used in asynchronous mode consists of a set of data bits in addition to bits for synchronization and optionally a parity
bit for error checking. A frame starts with one start-bit (S), where the line is driven low for one bit-period. This signals the start of a
frame, and is used for synchronization. Following the start bit are 4 to 16 data bits and an optional parity bit. Finally, a number of stop-
bits, where the line is driven high, end the frame. An example frame is shown in the following figure.
S 0 1 2 34 [5] [6] [7] [8] [P] Stop
Start or idleStop or idle
Frame
Figure 17.2. USART Asynchronous Frame Format
The number of data bits in a frame is set by DATABITS in USARTn_FRAME, see Table 17.3 USART Data Bits on page 582, and the
number of stop-bits is set by STOPBITS in USARTn_FRAME, see Table 17.4 USART Stop Bits on page 582. Whether or not a parity
bit should be included, and whether it should be even or odd is defined by PARITY, also in USARTn_FRAME. For communication to be
possible, all parties of an asynchronous transfer must agree on the frame format being used.
Table 17.3. USART Data Bits
DATA BITS [3:0] Number of Data bits
0001 4
0010 5
0011 6
0100 7
0101 8 (Default)
0110 9
0111 10
1000 11
1001 12
1010 13
1011 14
1100 15
1101 16
Table 17.4. USART Stop Bits
STOP BITS [1:0] Number of Stop bits
00 0.5
01 1 (Default)
10 1.5
11 2
The order in which the data bits are transmitted and received is defined by MSBF in USARTn_CTRL. When MSBF is cleared, data in a
frame is sent and received with the least significant bit first. When it is set, the most significant bit comes first.
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The frame format used by the transmitter can be inverted by setting TXINV in USARTn_CTRL, and the format expected by the receiver
can be inverted by setting RXINV in USARTn_CTRL. These bits affect the entire frame, not only the data bits. An inverted frame has a
low idle state, a high start-bit, inverted data and parity bits, and low stop-bits.
17.3.2.1.1 Parity Bit Calculation and Handling
When parity bits are enabled, hardware automatically calculates and inserts any parity bits into outgoing frames, and verifies the re-
ceived parity bits in incoming frames. This is true for both asynchronous and synchronous modes, even though it is mostly used in
asynchronous communication. The possible parity modes are defined in the following table. When even parity is chosen, a parity bit is
inserted to make the number of high bits (data + parity) even. If odd parity is chosen, the parity bit makes the total number of high bits
odd.
Table 17.5. USART Parity Bits
STOP BITS [1:0] Description
00 No parity bit (Default)
01 Reserved
10 Even parity
11 Odd parity
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17.3.2.2 Clock Generation
The USART clock defines the transmission and reception data rate. When operating in asynchronous mode, the baud rate (bit-rate) is
given by the following equation
br =
fHFPERCLK
oversample × (1 + USARTn_CLKDIV
256 )
where fHFPERCLK is the peripheral clock (HFPERCLKUSARTn) frequency and oversample is the oversampling rate as defined by OVS in
USARTn_CTRL, see the following table.
Table 17.6. USART Oversampling
OVS [1:0] Oversample
00 16
01 8
10 6
11 4
The USART has a fractional clock divider to allow the USART clock to be controlled more accurately than what is possible with a stand-
ard integral divider.
The clock divider used in the USART is a 15-bit value, with a 13-bit integral part and a 2-bit fractional part. The fractional part is config-
ured in the two LSBs of DIV in USART_CLKDIV. The lowest achievable baud rate at 32 MHz is about 244 bauds/sec.
Fractional clock division is implemented by distributing the selected fraction over four baud periods. The fractional part of the divider
tells how many of these periods should be extended by one peripheral clock cycle.
Given a desired baud rate brdesired, the clock divider USARTn_CLKDIV can be calculated by using the following equation:
USARTn_CLKDIV = 256 × (
fHFPERCLK
oversample × brdesired - 1)
The following table shows a set of desired baud rates and how accurately the USART is able to generate these baud rates when run-
ning at a 4 MHz peripheral clock, using 16x or 8x oversampling.
Table 17.7. USART Baud Rates @ 4MHz Peripheral Clock
Desired baud
rate [baud/s]
USARTn_OVS =00 USARTn_OVS =01
USARTn_CLKDIV/
256
Actual baud rate
[baud/s]
Error % USARTn_CLKDIV/
256
Actual baud rate
[baud/s]
Error %
600 415.75 599.88 -0.02 832.25 600.06 0.01
1200 207.25 1200.48 0.04 415.75 1199.76 -0.02
2400 103.25 2398.082 -0.08 207.25 2400.96 0.04
4800 51 4807.692 0.16 103.25 4796.163 -0.08
9600 25 9615.385 0.16 51 9615.385 0.16
14400 16.25 14492.75 0.64 33.75 14388.49 -0.08
19200 12 19230.77 0.16 25 19230.77 0.16
28800 7.75 28571.43 -0.79 16.25 28985.5 0.64
38400 5.5 38461.54 0.16 12 38461.54 0.16
57600 3.25 58823.53 2.12 7.75 571422.86 -0.79
76800 2.25 76923.08 0.16 5.5 76923.08 0.16
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Desired baud
rate [baud/s]
USARTn_OVS =00 USARTn_OVS =01
USARTn_CLKDIV/
256
Actual baud rate
[baud/s]
Error % USARTn_CLKDIV/
256
Actual baud rate
[baud/s]
Error %
115200 1.25 111111.1 -3.55 3.25 117647.1 2.12
230400 0 250000 8.51 1.25 222222.2 -3.55
17.3.2.3 Data Transmission
Asynchronous data transmission is initiated by writing data to the transmit buffer using one of the methods described in
17.3.2.3.1 Transmit Buffer Operation. When the transmission shift register is empty and ready for new data, a frame from the transmit
buffer is loaded into the shift register, and if the transmitter is enabled, transmission begins. When the frame has been transmitted, a
new frame is loaded into the shift register if available, and transmission continues. If the transmit buffer is empty, the transmitter goes to
an idle state, waiting for a new frame to become available.
Transmission is enabled through the command register USARTn_CMD by setting TXEN, and disabled by setting TXDIS in the same
command register. When the transmitter is disabled using TXDIS, any ongoing transmission is aborted, and any frame currently being
transmitted is discarded. When disabled, the TX output goes to an idle state, which by default is a high value. Whether or not the trans-
mitter is enabled at a given time can be read from TXENS in USARTn_STATUS.
When the USART transmitter is enabled and there is no data in the transmit shift register or transmit buffer, the TXC flag in
USARTn_STATUS and the TXC interrupt flag in USARTn_IF are set, signaling that the transmitter is idle. The TXC status flag is
cleared when a new frame becomes available for transmission, but the TXC interrupt flag must be cleared by software.
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17.3.2.3.1 Transmit Buffer Operation
The transmit-buffer is a 2-level FIFO buffer. A frame can be loaded into the buffer by writing to USARTn_TXDATA, USARTn_TXDA-
TAX, USARTn_TXDOUBLE or USARTn_TXDOUBLEX. Using USARTn_TXDATA allows 8 bits to be written to the buffer, while using
USARTn_TXDOUBLE will write 2 frames of 8 bits to the buffer. If 9-bit frames are used, the 9th bit of the frames will in these cases be
set to the value of BIT8DV in USARTn_CTRL.
To set the 9th bit directly and/or use transmission control, USARTn_TXDATAX and USARTn_TXDOUBLEX must be used.
USARTn_TXDATAX allows 9 data bits to be written, as well as a set of control bits regarding the transmission of the written frame.
Every frame in the buffer is stored with 9 data bits and additional transmission control bits. USARTn_TXDOUBLEX allows two frames,
complete with control bits to be written at once. When data is written to the transmit buffer using USARTn_TXDATAX and
USARTn_TXDOUBLEX, the 9th bit(s) written to these registers override the value in BIT8DV in USARTn_CTRL, and alone define the
9th bits that are transmitted if 9-bit frames are used. The following figure shows the basics of the transmit buffer when DATABITS in
USARTn_FRAME is configured to less than 10 bits.
Write CTRL
Write CTRL
TX buffer element 1
TX buffer element 0
Shift register
Peripheral Bus
Write CTRL
TXDOUBLE,
TXDOUBLEX
TXDATA,
TXDATAX
Figure 17.3. USART Transmit Buffer Operation
When writing more frames to the transmit buffer than there is free space for, the TXOF interrupt flag in USARTn_IF will be set, indicat-
ing the overflow. The data already in the transmit buffer is preserved in this case, and no data is written.
In addition to the interrupt flag TXC in USARTn_IF and status flag TXC in USARTn_STATUS which are set when the transmitter is idle,
TXBL in USARTn_STATUS and the TXBL interrupt flag in USARTn_IF are used to indicate the level of the transmit buffer. TXBIL in
USARTn_CTRL controls the level at which these bits are set. If TXBIL is cleared, they are set whenever the transmit buffer becomes
empty, and if TXBIL is set, they are set whenever the transmit buffer goes from full to half-full or empty. Both the TXBL status flag and
the TXBL interrupt flag are cleared automatically when their condition becomes false.
The transmit buffer, including the transmit shift register can be cleared by setting CLEARTX in USARTn_CMD. This will prevent the
USART from transmitting the data in the buffer and shift register, and will make them available for new data. Any frame currently being
transmitted will not be aborted. Transmission of this frame will be completed.
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17.3.2.3.2 Frame Transmission Control
The transmission control bits, which can be written using USARTn_TXDATAX and USARTn_TXDOUBLEX, affect the transmission of
the written frame. The following options are available:
• Generate break: By setting TXBREAK, the output will be held low during the stop-bit period to generate a framing error. A receiver
that supports break detection detects this state, allowing it to be used e.g. for framing of larger data packets. The line is driven high
before the next frame is transmitted so the next start condition can be identified correctly by the recipient. Continuous breaks lasting
longer than a USART frame are thus not supported by the USART. GPIO can be used for this.
• Disable transmitter after transmission: If TXDISAT is set, the transmitter is disabled after the frame has been fully transmitted.
• Enable receiver after transmission: If RXENAT is set, the receiver is enabled after the frame has been fully transmitted. It is enabled
in time to detect a start-bit directly after the last stop-bit has been transmitted.
• Unblock receiver after transmission: If UBRXAT is set, the receiver is unblocked and RXBLOCK is cleared after the frame has been
fully transmitted.
• Tristate transmitter after transmission: If TXTRIAT is set, TXTRI is set after the frame has been fully transmitted, tristating the trans-
mitter output. Tristating of the output can also be performed automatically by setting AUTOTRI. If AUTOTRI is set TXTRI is always
read as 0.
Note: When in SmartCard mode with repeat enabled, none of the actions, except generate break, will be performed until the frame is
transmitted without failure. Generation of a break in SmartCard mode with repeat enabled will cause the USART to detect a NACK on
every frame.
17.3.2.4 Data Reception
Data reception is enabled by setting RXEN in USARTn_CMD. When the receiver is enabled, it actively samples the input looking for a
transition from high to low indicating the start baud of a new frame. When a start baud is found, reception of the new frame begins if the
receive shift register is empty and ready for new data. When the frame has been received, it is pushed into the receive buffer, making
the shift register ready for another frame of data, and the receiver starts looking for another start baud. If the receive buffer is full, the
received frame remains in the shift register until more space in the receive buffer is available. If an incoming frame is detected while
both the receive buffer and the receive shift register are full, the data in the shift register is overwritten, and the RXOF interrupt flag in
USARTn_IF is set to indicate the buffer overflow.
The receiver can be disabled by setting the command bit RXDIS in USARTn_CMD. Any frame currently being received when the re-
ceiver is disabled is discarded. Whether or not the receiver is enabled at a given time can be read out from RXENS in USARTn_STA-
TUS.
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17.3.2.4.1 Receive Buffer Operation
When data becomes available in the receive buffer, the RXDATAV flag in USARTn_STATUS, and the RXDATAV interrupt flag in
USARTn_IF are set, and when the buffer becomes full, RXFULL in USARTn_STATUS and the RXFULL interrupt flag in USARTn_IF
are set. The status flags RXDATAV and RXFULL are automatically cleared by hardware when their condition is no longer true. This
also goes for the RXDATAV interrupt flag, but the RXFULL interrupt flag must be cleared by software. When the RXFULL flag is set,
notifying that the buffer is full, space is still available in the receive shift register for one more frame.
Data can be read from the receive buffer in a number of ways. USARTn_RXDATA gives access to the 8 least significant bits of the
received frame, and USARTn_RXDOUBLE makes it possible to read the 8 least significant bits of two frames at once, pulling two
frames from the buffer. To get access to the 9th, most significant bit, USARTn_RXDATAX must be used. This register also contains
status information regarding the frame. USARTn_RXDOUBLEX can be used to get two frames complete with the 9th bits and status
bits.
When a frame is read from the receive buffer using USARTn_RXDATA or USARTn_RXDATAX, the frame is pulled out of the buffer,
making room for a new frame. USARTn_RXDOUBLE and USARTn_RXDOUBLEX pull two frames out of the buffer. If an attempt is
done to read more frames from the buffer than what is available, the RXUF interrupt flag in USARTn_IF is set to signal the underflow,
and the data read from the buffer is undefined.
Frames can be read from the receive buffer without removing the data by using USARTn_RXDATAXP and USARTn_RXDOUBLEXP.
USARTn_RXDATAXP gives access the first frame in the buffer with status bits, while USARTn_RXDOUBLEXP gives access to both
frames with status bits. The data read from these registers when the receive buffer is empty is undefined. If the receive buffer contains
one valid frame, the first frame in USARTn_RXDOUBLEXP will be valid. No underflow interrupt is generated by a read using these
registers, i.e. RXUF in USARTn_IF is never set as a result of reading from USARTn_RXDATAXP or USARTn_RXDOUBLEXP.
The basic operation of the receive buffer when DATABITS in USARTn_FRAME is configured to less than 10 bits is shown in the follow-
ing figure.
Status
RX buffer element 0
RX buffer element 1
Shift register
Peripheral Bus
Status
Status
RXDOUBLE
RXDOUBLEX
RXDOUBLEXP
RXDATA,
RXDATAX,
RXDATAXP
Figure 17.4. USART Receive Buffer Operation
The receive buffer, including the receive shift register can be cleared by setting CLEARRX in USARTn_CMD. Any frame currently being
received will not be discarded.
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17.3.2.4.2 Blocking Incoming Data
When using hardware frame recognition, as detailed in 17.3.2.8 Multi-Processor Mode and 17.3.2.9 Collision Detection, it is necessary
to be able to let the receiver sample incoming frames without passing the frames to software by loading them into the receive buffer.
This is accomplished by blocking incoming data.
Incoming data is blocked as long as RXBLOCK in USARTn_STATUS is set. When blocked, frames received by the receiver will not be
loaded into the receive buffer, and software is not notified by the RXDATAV flag in USARTn_STATUS or the RXDATAV interrupt flag in
USARTn_IF at their arrival. For data to be loaded into the receive buffer, RXBLOCK must be cleared in the instant a frame is fully re-
ceived by the receiver. RXBLOCK is set by setting RXBLOCKEN in USARTn_CMD and disabled by setting RXBLOCKDIS also in
USARTn_CMD. There is one exception where data is loaded into the receive buffer even when RXBLOCK is set. This is when an ad-
dress frame is received when operating in multi-processor mode. See 17.3.2.8 Multi-Processor Mode for more information.
Frames received containing framing or parity errors will not result in the FERR and PERR interrupt flags in USARTn_IF being set while
RXBLOCK in USARTn_STATUS is set. Hardware recognition is not applied to these erroneous frames, and they are silently discarded.
Note: If a frame is received while RXBLOCK in USARTn_STATUS is cleared, but stays in the receive shift register because the receive
buffer is full, the received frame will be loaded into the receive buffer when space becomes available even if RXBLOCK is set at that
time.
The overflow interrupt flag RXOF in USARTn_IF will be set if a frame in the receive shift register, waiting to be loaded into the receive
buffer is overwritten by an incoming frame even though RXBLOCK in USARTn_STATUS is set.
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4:1
4:1
17.3.2.4.3 Clock Recovery and Filtering
The receiver samples the incoming signal at a rate 16, 8, 6 or 4 times higher than the given baud rate, depending on the oversampling
mode given by OVS in USARTn_CTRL. Lower oversampling rates make higher baud rates possible, but give less room for errors.
When a high-to-low transition is registered on the input while the receiver is idle, this is recognized as a start-bit, and the baud rate
generator is synchronized with the incoming frame.
For oversampling modes 16, 8 and 6, every bit in the incoming frame is sampled three times to gain a level of noise immunity. These
samples are aimed at the middle of the bit-periods, as visualized in the following figure. With OVS=0 in USARTn_CTRL, the start and
data bits are thus sampled at locations 8, 9 and 10 in the figure, locations 4, 5 and 6 for OVS=1 and locations 3, 4, and 5 for OVS=2.
The value of a sampled bit is determined by majority vote. If two or more of the three bit-samples are high, the resulting bit value is
high. If the majority is low, the resulting bit value is low.
Majority vote is used for all oversampling modes except 4x oversampling. In this mode, a single sample is taken at position 3 as shown
in the following figure.
Majority vote can be disabled by setting MVDIS in USARTn_CTRL.
If the value of the start bit is found to be high, the reception of the frame is aborted, filtering out false start bits possibly generated by
noise on the input.
0 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 1 2 3 4 5 6 7 8 9 10 11
Idle Start bit Bit 0
0 1 2 3 4 5 6 7 8 1 2 3 4 5 6
13
7
12
OVS = 0OVS = 1
0
1 2 3 4 5 6 1
OVS = 2
1 2 3 4 1 2 3 4
OVS = 3
2 3 4 50
Figure 17.5. USART Sampling of Start and Data Bits
If the baud rate of the transmitter and receiver differ, the location each bit is sampled will be shifted towards the previous or next bit in
the frame. This is acceptable for small errors in the baud rate, but for larger errors, it will result in transmission errors.
When the number of stop bits is 1 or more, stop bits are sampled like the start and data bits as seen in the following figure. When a stop
bit has been detected by sampling at positions 8, 9 and 10 for normal mode, or 4, 5 and 6 for smart mode, the USART is ready for a
new start bit. As seen in the following figure, a stop-bit of length 1 normally ends at c, but the next frame will be received correctly as
long as the start-bit comes after position a for OVS=0 and OVS=3, and b for OVS=1 and OVS=2.
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13 14 15 16 1 2 3 4 5 6 7 8 9 10 0/1
1 stop bit
7 8 1 2 3 4 5 6
X
0/1
X
OVS = 0OVS = 1
X X X
X
n’th bit
a b c
Idle or start bit
0/1
OVS = 2
4 1 2 3 0/1
OVS = 3
2 3 46 1 1
1
Figure 17.6. USART Sampling of Stop Bits when Number of Stop Bits are 1 or More
When working with stop bit lengths of half a baud period, the above sampling scheme no longer suffices. In this case, the stop-bit is not
sampled, and no framing error is generated in the receiver if the stop bit is not generated. The line must still be driven high before the
next start bit however for the USART to successfully identify the start bit.
17.3.2.4.4 Parity Error
When parity bits are enabled, a parity check is automatically performed on incoming frames. When a parity error is detected in an in-
coming frame, the data parity error bit PERR in the frame is set, as well as the interrupt flag PERR in USARTn_IF. Frames with parity
errors are loaded into the receive buffer like regular frames.
PERR can be accessed by reading the frame from the receive buffer using the USARTn_RXDATAX, USARTn_RXDATAXP,
USARTn_RXDOUBLEX or USARTn_RXDOUBLEXP registers.
If ERRSTX in USARTn_CTRL is set, the transmitter is disabled on received parity and framing errors. If ERRSRX in USARTn_CTRL is
set, the receiver is disabled on parity and framing errors.
17.3.2.4.5 Framing Error and Break Detection
A framing error is the result of an asynchronous frame where the stop bit was sampled to a value of 0. This can be the result of noise
and baud rate errors, but can also be the result of a break generated by the transmitter on purpose.
When a framing error is detected in an incoming frame, the framing error bit FERR in the frame is set. The interrupt flag FERR in
USARTn_IF is also set. Frames with framing errors are loaded into the receive buffer like regular frames.
FERR can be accessed by reading the frame from the receive buffer using the USARTn_RXDATAX, USARTn_RXDATAXP,
USARTn_RXDOUBLEX or USARTn_RXDOUBLEXP registers.
If ERRSTX in USARTn_CTRL is set, the transmitter is disabled on parity and framing errors. If ERRSRX in USARTn_CTRL is set, the
receiver is disabled on parity and framing errors.
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17.3.2.5 Local Loopback
The USART receiver samples U(S)n_RX by default, and the transmitter drives U(S)n_TX by default. This is not the only option howev-
er. When LOOPBK in USARTn_CTRL is set, the receiver is connected to the U(S)n_TX pin as shown in the following figure. This is
useful for debugging, as the USART can receive the data it transmits, but it is also used to allow the USART to read and write to the
same pin, which is required for some half duplex communication modes. In this mode, the U(S)n_TX pin must be enabled as an output
in the GPIO.
Device
USART
Device
USART
RX U(S)n_RX
TX U(S)n_TX
LOOBPK = 0
RX U(S)n_RX
TX U(S)n_TX
LOOBPK = 1
Figure 17.7. USART Local Loopback
17.3.2.6 Asynchronous Half Duplex Communication
When doing full duplex communication, two data links are provided, making it possible for data to be sent and received at the same
time. In half duplex mode, data is only sent in one direction at a time. There are several possible half duplex setups, as described in the
following sections.
17.3.2.6.1 Single Data-Link
In this setup, the USART both receives and transmits data on the same pin. This is enabled by setting LOOPBK in USARTn_CTRL,
which connects the receiver to the transmitter output. Because they are both connected to the same line, it is important that the USART
transmitter does not drive the line when receiving data, as this would corrupt the data on the line.
When communicating over a single data-link, the transmitter must thus be tristated whenever not transmitting data. This is done by
setting the command bit TXTRIEN in USARTn_CMD, which tristates the transmitter. Before transmitting data, the command bit TXTRI-
DIS, also in USARTn_CMD, must be set to enable transmitter output again. Whether or not the output is tristated at a given time can be
read from TXTRI in USARTn_STATUS. If TXTRI is set when transmitting data, the data is shifted out of the shift register, but is not put
out on U(S)n_TX.
When operating a half duplex data bus, it is common to have a bus master, which first transmits a request to one of the bus slaves,
then receives a reply. In this case, the frame transmission control bits, which can be set by writing to USARTn_TXDATAX, can be used
to make the USART automatically disable transmission, tristate the transmitter and enable reception when the request has been trans-
mitted, making it ready to receive a response from the slave.
Tristating the transmitter can also be performed automatically by the USART by using AUTOTRI in USARTn_CTRL. When AUTOTRI is
set, the USART automatically tristates U(S)n_TX whenever the transmitter is idle, and enables transmitter output when the transmitter
goes active. If AUTOTRI is set TXTRI is always read as 0.
Note: Another way to tristate the transmitter is to enable wired-and or wired-or mode in GPIO. For wired-and mode, outputting a 1 will
be the same as tristating the output, and for wired-or mode, outputting a 0 will be the same as tristating the output. This can only be
done on buses with a pull-up or pull-down resistor respectively.
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17.3.2.6.2 Single Data-Link with External Driver
Some communication schemes, such as RS-485 rely on an external driver. Here, the driver has an extra input which enables it, and
instead of tristating the transmitter when receiving data, the external driver must be disabled.
This can be done manually by assigning a GPIO to turn the driver on or off, or it can be handled automatically by the USART. If AU-
TOCS in USARTn_CTRL is set, the USn_CS output is automatically activated one baud period before the transmitter starts transmitting
data, and deactivated when the last bit has been transmitted and there is no more data in the transmit buffer to transmit, or the transmit-
ter becomes disabled. This feature can be used to turn the external driver on when transmitting data, and turn it off when the data has
been transmitted.
The following figure shows an example configuration where USn_CS is used to automatically enable and disable an external driver.
Device
USART
RX
TX
CS
Figure 17.8. USART Half Duplex Communication with External Driver
The USn_CS output is active low by default, but its polarity can be changed with CSINV in USARTn_CTRL. AUTOCS works regardless
of which mode the USART is in, so this functionality can also be used for automatic chip/slave select when in synchronous mode (e.g.
SPI).
17.3.2.6.3 Two Data-Links
Some limited devices only support half duplex communication even though two data links are available. In this case software is respon-
sible for making sure data is not transmitted when incoming data is expected.
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,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,
17.3.2.7 Large Frames
As each frame in the transmit and receive buffers holds a maximum of 9 bits, both the elements in the buffers are combined when
working with USART-frames of 10 or more data bits.
To transmit such a frame, at least two elements must be available in the transmit buffer. If only one element is available, the USART will
wait for the second element before transmitting the combined frame. Both the elements making up the frame are consumed when
transmitting such a frame.
When using large frames, the 9th bits in the buffers are unused. For an 11 bit frame, the 8 least significant bits are thus taken from the
first element in the buffer, and the 3 remaining bits are taken from the second element as shown in the following figure. The first ele-
ment in the transmit buffer, i.e. element 0 in the following figure is the first element written to the FIFO, or the least significant byte when
writing two bytes at a time using USARTn_TXDOUBLE.
Write CTRL
Write CTRL
Write CTRL
TX buffer element 1
TX buffer element 0
Shift register
Peripheral Bus
0 1 2 3 4 5 6 7 0 1 2
0 1 2
0 1 2 3 4 5 6 7
Figure 17.9. USART Transmission of Large Frames
As shown in the previous figure, frame transmission control bits are taken from the second element in FIFO.
The two buffer elements can be written at the same time using the USARTn_TXDOUBLE or USARTn_TXDOUBLEX register. The
TXDATAX0 bitfield then refers to buffer element 0, and TXDATAX1 refers to buffer element 1.
TX buffer element 1
TX buffer element 0
Shift register
Peripheral Bus
2 1 0 7 6 5 4 3 2 1 0
0 1 2 3 4 5 6 7
0 1 2
Figure 17.10. USART Transmission of Large Frames, MSBF
The previous figure illustrates the order of the transmitted bits when an 11 bit frame is transmitted with MSBF set. If MSBF is set and
the frame is smaller than 10 bits, only the contents of transmit buffer 0 will be transmitted.
When receiving a large frame, BYTESWAP in USARTn_CTRL determines the order the way the large frame is split into the two buffer
elements. If BYTESWAP is cleared, the least significant 8 bits of the received frame are loaded into the first element of the receive
buffer, and the remaining bits are loaded into the second element, as shown in the following figure. The first byte read from the buffer
thus contains the 8 least significant bits. Set BYTESWAP to reverse the order.
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IIIIIIIIIII
Status
RX buffer element 0
RX buffer element 1
Shift register
Peripheral Bus
Status
Status
0 1 2 3 4 5 6 7 0 1 2
0 1 2
0 1 2 3 4 5 6 7
Figure 17.11. USART Reception of Large Frames
The status bits are loaded into both elements of the receive buffer. The frame is not moved from the receive shift register before there
are two free spaces in the receive buffer.
The two buffer elements can be read at the same time using the USARTn_RXDOUBLE or USARTn_RXDOUBLEX register. RXDATA0
then refers to buffer element 0 and RXDATA1 refers to buffer element 1.
Large frames can be used in both asynchronous and synchronous modes.
17.3.2.8 Multi-Processor Mode
To simplify communication between multiple processors, the USART supports a special multi-processor mode. In this mode the 9th
data bit in each frame is used to indicate whether the content of the remaining 8 bits is data or an address.
When multi-processor mode is enabled, an incoming 9-bit frame with the 9th bit equal to the value of MPAB in USARTn_CTRL is identi-
fied as an address frame. When an address frame is detected, the MPAF interrupt flag in USARTn_IF is set, and the address frame is
loaded into the receive register. This happens regardless of the value of RXBLOCK in USARTn_STATUS.
Multi-processor mode is enabled by setting MPM in USARTn_CTRL, and the value of the 9th bit in address frames can be set in MPAB.
Note that the receiver must be enabled for address frames to be detected. The receiver can be blocked however, preventing data from
being loaded into the receive buffer while looking for address frames.
The following example explains basic usage of the multi-processor mode:
1. All slaves enable multi-processor mode and, enable and block the receiver. They will now not receive data unless it is an address
frame. MPAB in USARTn_CTRL is set to identify frames with the 9th bit high as address frames.
2. The master sends a frame containing the address of a slave and with the 9th bit set.
3. All slaves receive the address frame and get an interrupt. They can read the address from the receive buffer. The selected slave
unblocks the receiver to start receiving data from the master.
4. The master sends data with the 9th bit cleared.
5. Only the slave with RX enabled receives the data. When transmission is complete, the slave blocks the receiver and waits for a
new address frame.
When a slave has received an address frame and wants to receive the following data, it must make sure the receiver is unblocked
before the next frame has been completely received in order to prevent data loss.
BIT8DV in USARTn_CTRL can be used to specify the value of the 9th bit without writing to the transmit buffer with USARTn_TXDATAX
or USARTn_TXDOUBLEX, giving higher efficiency in multi-processor mode, as the 9th bit is only set when writing address frames, and
8-bit writes to the USART can be used when writing the data frames.
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17.3.2.9 Collision Detection
The USART supports a basic form of collision detection. When the receiver is connected to the output of the transmitter, either by using
the LOOPBK bit in USARTn_CTRL or through an external connection, this feature can be used to detect whether data transmitted on
the bus by the USART did get corrupted by a simultaneous transmission by another device on the bus.
For collision detection to be enabled, CCEN in USARTn_CTRL must be set, and the receiver enabled. The data sampled by the receiv-
er is then continuously compared with the data output by the transmitter. If they differ, the CCF interrupt flag in USARTn_IF is set. The
collision check includes all bits of the transmitted frames. The CCF interrupt flag is set once for each bit sampled by the receiver that
differs from the bit output by the transmitter. When the transmitter output is disabled, i.e. the transmitter is tristated, collisions are not
registered.
17.3.2.10 SmartCard Mode
In SmartCard mode, the USART supports the ISO 7816 I/O line T0 mode. With exception of the stopbits (guard time), the 7816 data
frame is equal to the regular asynchronous frame. In this mode, the receiver pulls the line low for one baud, half a baud into the guard
time to indicate a parity error. This NAK can for instance be used by the transmitter to re-transmit the frame. SmartCard mode is a half
duplex asynchronous mode, so the transmitter must be tristated whenever not transmitting data.
To enable SmartCard mode, set SCMODE in USARTn_CTRL, set the number of databits in a frame to 8, and configure the number of
stopbits to 1.5 by writing to STOPBITS in USARTn_FRAME.
The SmartCard mode relies on half duplex communication on a single line, so for it to work, both the receiver and transmitter must work
on the same line. This can be achieved by setting LOOPBK in USARTn_CTRL or through an external connection. The TX output
should be configured as open-drain in the GPIO module.
When no parity error is identified by the receiver, the data frame is as shown in the following figure. The frame consists of 8 data bits, a
parity bit, and 2 stop bits. The transmitter does not drive the output line during the guard time.
S01 2 34 5 6 7 PStop
Start or idleStop or idle
ISO 7816 Frame without error
Figure 17.12. USART ISO 7816 Data Frame Without Error
If a parity error is detected by the receiver, it pulls the line I/O line low after half a stop bit, see the following figure. It holds the line low
for one bit-period before it releases the line. In this case, the guard time is extended by one bit period before a new transmission can
start, resulting in a total of 3 stop bits.
S01 2 34 5 6 7 PStop
Start or idle
Stop or idle
ISO 7816 Frame with error
Stop
NAK
Figure 17.13. USART ISO 7816 Data Frame With Error
On a parity error, the NAK is generated by hardware. The NAK generated by the receiver is sampled as the stop-bit of the frame. Be-
cause of this, parity errors when in SmartCard mode are reported with both a parity error and a framing error.
When transmitting a T0 frame, the USART receiver on the transmitting side samples position 16, 17 and 18 in the stop-bit to detect the
error signal when in 16x oversampling mode as shown in the following figure. Sampling at this location places the stop-bit sample in the
middle of the bit-period used for the error signal (NAK).
If a NAK is transmitted by the receiver, it will thus appear as a framing error at the transmitter, and the FERR interrupt flag in
USARTn_IF will be set. If SCRETRANS USARTn_CTRL is set, the transmitter will automatically retransmit a NACK’ed frame. The
transmitter will retransmit the frame until it is ACK’ed by the receiver. This only works when the number of databits in a frame is config-
ured to 8.
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Set SKIPPERRF in USARTn_CTRL to make the receiver discard frames with parity errors. The PERR interrupt flag in USARTn_IF is
set when a frame is discarded because of a parity error.
13 14 15 16 1 2 3 4 5 6 7 8 9 10 11
1/2 stop bit
7 8 1 2 3 4 5 6
13
7
12
OVS = 0OVS = 1
14 15 16
8
PNAK or stop
17 18 X
9 10
X
X
X X X X
X
Stop
1 2 3 4 5 6 7
OVS = 2
1 2 3 4 5 x
OVS = 3
8 x6
4
Figure 17.14. USART SmartCard Stop Bit Sampling
For communication with a SmartCard, a clock signal needs to be generated for the card. This clock output can be generated using one
of the timers. See the ISO 7816 specification for more info on this clock signal.
SmartCard T1 mode is also supported. The T1 frame format used is the same as the asynchronous frame format with parity bit enabled
and one stop bit. The USART must then be configured to operate in asynchronous half duplex mode.
17.3.3 Synchronous Operation
Most of the features in asynchronous mode are available in synchronous mode. Multi-processor mode can be enabled for 9-bit frames,
loopback is available and collision detection can be performed.
17.3.3.1 Frame Format
The frames used in synchronous mode need no start and stop bits since a single clock is available to all parts participating in the com-
munication. Parity bits cannot be used in synchronous mode.
The USART supports frame lengths of 4 to 16 bits per frame. Larger frames can be simulated by transmitting multiple smaller frames,
i.e. a 22 bit frame can be sent using two 11-bit frames, and a 21 bit frame can be generated by transmitting three 7-bit frames. The
number of bits in a frame is set using DATABITS in USARTn_FRAME.
The frames in synchronous mode are by default transmitted with the least significant bit first like in asynchronous mode. The bit-order
can be reversed by setting MSBF in USARTn_CTRL.
The frame format used by the transmitter can be inverted by setting TXINV in USARTn_CTRL, and the format expected by the receiver
can be inverted by setting RXINV, also in USARTn_CTRL.
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17.3.3.2 Clock Generation
The bit-rate in synchronous mode is given by the following equation. As in the case of asynchronous operation, the clock division factor
have a 13-bit integral part and a 2-bit fractional part.
br =
fHFPERCLK
2 × (1 + USARTn_CLKDIV
256 )
Given a desired baud rate brdesired, the clock divider USARTn_CLKDIV can be calculated using the following equation.
USARTn_CLKDIV = 256 × (
fHFPERCLK
2 × brdesired - 1)
When the USART operates in master mode, the highest possible bit rate is half the peripheral clock rate. When operating in slave mode
however, the highest bit rate is an eighth of the peripheral clock:
• Master mode: brmax = fHFPERCLK/2
• Slave mode: brmax = fHFPERCLK/8
On every clock edge data on the data lines, MOSI and MISO, is either set up or sampled. When CLKPHA in USARTn_CTRL is cleared,
data is sampled on the leading clock edge and set-up is done on the trailing edge. If CLKPHA is set however, data is set-up on the
leading clock edge, and sampled on the trailing edge. In addition to this, the polarity of the clock signal can be changed by setting
CLKPOL in USARTn_CTRL, which also defines the idle state of the clock. This results in four different modes which are summarized in
the following table. The following figure shows the resulting timing of data set-up and sampling relative to the bus clock.
Table 17.8. USART SPI Modes
SPI mode CLKPOL CLKPHA Leading edge Trailing edge
0 0 0 Rising, sample Falling, set-up
1 0 1 Rising, set-up Falling, sample
2 1 0 Falling, sample Rising, set-up
3 1 1 Falling, set-up Rising, sample
0 1 2 3 4 5 6 7
0 1 2 3 4 5 6 7
USn_CLK
USn_CS
USn_TX/
USn_RX
CLKPOL = 0
CLKPOL = 1
CLKPHA = 0
CLKPHA = 1 X
X X
X
Figure 17.15. USART SPI Timing
If CPHA=1, the TX underflow flag, TXUF, will be set on the first setup clock edge of a frame in slave mode if TX data is not available. If
CPHA=0, TXUF is set if data is not available in the transmit buffer three HFPERCLK cycles prior to the first sample clock edge. The
RXDATAV flag is updated on the last sample clock edge of a transfer, while the RX overflow interrupt flag, RXOF, is set on the first
sample clock edge if the receive buffer overflows. When a transfer has been performed, interrupt flags TXBL and TXC are updated on
the first setup clock edge of the succeeding frame, or when CS is deasserted.
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17.3.3.3 Master Mode
When in master mode, the USART is in full control of the data flow on the synchronous bus. When operating in full duplex mode, the
slave cannot transmit data to the master without the master transmitting to the slave. The master outputs the bus clock on USn_CLK.
Communication starts whenever there is data in the transmit buffer and the transmitter is enabled. The USART clock then starts, and
the master shifts bits out from the transmit shift register using the internal clock.
When there are no more frames in the transmit buffer and the transmit shift register is empty, the clock stops, and communication ends.
When the receiver is enabled, it samples data using the internal clock when the transmitter transmits data. Operation of the RX and TX
buffers is as in asynchronous mode.
17.3.3.3.1 Operation of USn_CS Pin
When operating in master mode, the USn_CS pin can have one of two functions, or it can be disabled.
If USn_CS is configured as an output, it can be used to automatically generate a chip select for a slave by setting AUTOCS in
USARTn_CTRL. If AUTOCS is set, USn_CS is activated when a transmission begins, and deactivated directly after the last bit has
been transmitted and there is no more data in the transmit buffer. By default, USn_CS is active low, but its polarity can be inverted by
setting CSINV in USARTn_CTRL.
When USn_CS is configured as an input, it can be used by another master that wants control of the bus to make the USART release it.
When USn_CS is driven low, or high if CSINV is set, the interrupt flag SSM in USARTn_IF is set, and if CSMA in USARTn_CTRL is set,
the USART goes to slave mode.
17.3.3.3.2 AUTOTX
A synchronous master is required to transmit data to a slave in order to receive data from the slave. In some cases, only a few words
are transmitted and a lot of data is then received from the slave. In that case, one solution is to keep feeding the TX with data to trans-
mit, but that consumes system bandwidth. Instead AUTOTX can be used.
When AUTOTX in USARTn_CTRL is set, the USART transmits data as long as there is available space in the RX shift register for the
chosen frame size. This happens even though there is no data in the TX buffer. The TX underflow interrupt flag TXUF in USARTn_IF is
set on the first word that is transmitted which does not contain valid data.
During AUTOTX the USART will always send the previous sent bit, thus reducing the number of transitions on the TX output. So if the
last bit sent was a 0, 0's will be sent during AUTOTX and if the last bit sent was a 1, 1's will be sent during AUTOTX.
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17.3.3.3.3 Synchronous Master Sample Delay
To improve speed in certain conditions by reducing the setup-time requirements for the SPI slave, the master can be configured to
sample the data one half SCLK-cycle later, i.e. on the next setup edge, which, in SPI mode 0, is the rising edge. This is enabled by
setting SMSDELAY in USARTn_CTRL and can be used together with all SPI slaves that does not set up new data before the next
setup edge, as the propagation delay of SCLK will ensure sufficient hold time.
Note: If used together with another Silicon Laboratories chip utilizing SSSEARLY, a very thorough understanding of the timing is re-
quired.
01 2 3 4 5 6 7
USn_CLK
USn_CS
USn_TX
(MOSI) X X
01 2 3 4 5 6 7
USn_RX
(MISO) X X
Ordinary Sample Edge Sample Edge with SMSDELAY
Figure 17.16. USART SPI Timing with SMSDELAY
17.3.3.4 Slave Mode
When the USART is in slave mode, data transmission is not controlled by the USART, but by an external master. The USART is there-
fore not able to initiate a transmission, and has no control over the number of bytes written to the master.
The output and input to the USART are also swapped when in slave mode, making the receiver take its input from USn_TX (MOSI) and
the transmitter drive USn_RX (MISO).
To transmit data when in slave mode, the slave must load data into the transmit buffer and enable the transmitter. The data will remain
in the USART until the master starts a transmission by pulling the USn_CS input of the slave low and transmitting data. For every frame
the master transmits to the slave, a frame is transferred from the slave to the master. After a transmission, MISO remains in the same
state as the last bit transmitted. This also applies if the master transmits to the slave and the slave TX buffer is empty.
If the transmitter is enabled in synchronous slave mode and the master starts transmission of a frame, the underflow interrupt flag
TXUF in USARTn_IF will be set if no data is available for transmission to the master.
If the slave needs to control its own chip select signal, this can be achieved by clearing CSPEN in the ROUTE register. The internal
chip select signal can then be controlled through CSINV in the CTRL register. The chip select signal will be CSINV inverted, i.e. if
CSINV is cleared, the chip select is active and vice versa.
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17.3.3.4.1 Synchronous Slave Setup Early
To improve speed in certain conditions by improving the setup time when running in slave mode, the slave can be configured to set up
data one half SCLK-cycle earlier, i.e. on the previous sample edge, which, for SPI mode 0, is the falling edge. This is enabled by setting
SSSEARLY in USARTn_CTRL and can be used with all SPI masters that samples the data on the sample edge, as the SCLK propaga-
tion delay will ensure sufficient hold time.
Note: If used together with another Silicon Laboratories chip utilizing SMSDELAY, a very thorough understanding of the timing is re-
quired.
01 2 3 4 5 6 7
USn_CLK
USn_CS
USn_TX
(MOSI) X X
012 3 4 5 6 7
USn_RX
(MISO) XX
Figure 17.17. USART SPI Slave Timing with SSSEARLY
17.3.3.5 Synchronous Half Duplex Communication
Half duplex communication in synchronous mode is very similar to half duplex communication in asynchronous mode as detailed in
17.3.2.6 Asynchronous Half Duplex Communication. The main difference is that in this mode, the master must generate the bus clock
even when it is not transmitting data, i.e. it must provide the slave with a clock to receive data. To generate the bus clock, the master
should transmit data with the transmitter tristated, i.e. TXTRI in USARTn_STATUS set, when receiving data. If 2 bytes are expected
from the slave, then transmit 2 bytes with the transmitter tristated, and the slave uses the generated bus clock to transmit data to the
master. TXTRI can be set by setting the TXTRIEN command bit in USARTn_CMD.
Note: When operating as SPI slave in half duplex mode, TX has to be tristated (not disabled) during data reception if the slave is to
transmit data in the current transfer.
17.3.3.6 I2S
I2S is a synchronous format for transmission of audio data. The frame format is 32-bit, but since data is always transmitted with MSB
first, an I2S device operating with 16-bit audio may choose to only process the 16 msb of the frame, and only transmit data in the 16
msb of the frame.
In addition to the bit clock used for regular synchronous transfers, I2S mode uses a separate word clock. When operating in mono
mode, with only one channel of data, the word clock pulses once at the start of each new word. In stereo mode, the word clock toggles
at the start of new words, and also gives away whether the transmitted word is for the left or right audio channel; A word transmitted
while the word clock is low is for the left channel, and a word transmitted while the word clock is high is for the right.
When operating in I2S mode, the CS pin is used as a the word clock. In master mode, this is automatically driven by the USART, and in
slave mode, the word clock is expected from an external master.
17.3.3.6.1 Word Format
The general I2S word format is 32 bits wide, but the USART also supports 16-bit and 8-bit words. In addition to this, it can be specified
how many bits of the word should actually be used by the USART. These parameters are given by FORMAT in USARTn_I2SCTRL.
As an example, configuring FORMAT to using a 32-bit word with 16-bit data will make each word on the I2S bus 32-bits wide, but when
receiving data through the USART, only the 16 most significant bits of each word can be read out of the USART. Similarly, only the 16
most significant bits have to be written to the USART when transmitting. The rest of the bits will be transmitted as zeroes.
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17.3.3.6.2 Major Modes
The USART supports a set of different I2S formats as shown in the following table, but it is not limited to these modes. MONO, JUSTI-
FY and DELAY in USARTn_I2SCTRL can be mixed and matched to create an appropriate format. MONO enables mono mode, i.e. one
data stream instead of two which is the default. JUSTIFY aligns data within a word on the I2S bus, either left or right which can bee
seen in the following figures. Finally, DELAY specifies whether a new I2S word should be started directly on the edge of the word-select
signal, or one bit-period after the edge.
Table 17.9. USART I2S Modes
Regular I2S 0 0 1 0
Mode MONO JUSTIFY DELAY CLKPOL
Left-Justified 0 0 0 1
Right-Justified 0 1 0 1
Mono 1 0 0 0
The regular I2S waveform is shown in the following figures. The first figure shows a waveform transmitted with full accuracy. The wor-
dlength can be configured to 32-bit, 16-bit or 8-bit using FORMAT in USARTn_I2SCTRL. In the second figure, I2S data is transmitted
with reduced accuracy, i.e. the data transmitted has less bits than what is possible in the bus format.
Note that the msb of a word transmitted in regular I2S mode is delayed by one cycle with respect to word select.
USn_CLK
USn_CS
(word select)
USn_TX/
USn_RX MSB
Left channelRight channel Right channel
LSB MSBLSB
Figure 17.18. USART Standard I2S Waveform
USn_CLK
USn_CS
(word select)
USn_TX/
USn_RX MSB
Left channelRight channel Right channel
LSB MSB
Figure 17.19. USART Standard I2S Waveform (Reduced Accuracy)
A left-justified stream is shown in the following figure. Note that the MSB comes directly after the edge on the word-select signal in
contradiction to the regular I2S waveform where it comes one bitperiod after.
USn_CLK
USn_CS
(word select)
USn_TX/
USn_RX MSB
Left channelRight channel Right channel
LSB MSB
Figure 17.20. USART Left-Justified I2S Waveform
A right-justified stream is shown in the following figure. The left and right justified streams are equal when the data-size is equal to the
word-width.
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USn_CLK
USn_TX/
USn_RX MSB
Left channelRight channel Right channel
LSBLSB
Figure 17.21. USART Right-Justified I2S Waveform
In mono-mode, the word-select signal pulses at the beginning of each word instead of toggling for each word. Mono I2S waveform is
shown in the following figure.
USn_CLK
USn_CS
(word select)
USn_TX/
USn_RX MSB
Left channelRight channel Right channel
LSB MSB
Figure 17.22. USART Mono I2S Waveform
17.3.3.6.3 Using I2S Mode
When using the USART in I2S mode, DATABITS in USARTn_FRAME must be set to 8 or 16 data-bits. 8 databits can be used in all
modes, and 16 can be used in the modes where the number of bytes in the I2S word is even. In addition to this, MSBF in
USARTn_CTRL should be set, and CLKPOL and CLKPHA in USARTn_CTRL should be cleared.
The USART does not have separate TX and RX buffers for left and right data, so when using I2S in stereo mode, the application must
keep track of whether the buffers contain left or right data. This can be done by observing TXBLRIGHT, RXDATAVRIGHT and
RXFULLRIGHT in USARTn_STATUS. TXBLRIGHT tells whether TX is expecting data for the left or right channel. It will be set with
TXBL if right data is expected. The receiver will set RXDATAVRIGHT if there is at least one right element in the buffer, and RXFULL-
RIGHT if the buffer is full of right elements.
When using I2S with DMA, separate DMA requests can be used for left and right data by setting DMASPLIT in USARTn_I2SCTRL.
In both master and slave mode the USART always starts transmitting on the LEFT channel after being enabled. In master mode, the
transmission will stop if TX becomes empty. In that case, TXC is set. Continuing the transmission in this case will make the data-stream
continue where it left off. To make the USART start on the LEFT channel after going empty, disable and re-enable TX.
17.3.4 PRS-Triggered Transmissions
If a transmission must be started on an event with very little delay, the PRS system can be used to trigger the transmission. The PRS
channel to use as a trigger can be selected using TSEL in USARTn_TRIGCTRL. When a positive edge is detected on this signal, the
receiver is enabled if RXTEN in USARTn_TRIGCTRL is set, and the transmitter is enabled if TXTEN in USARTn_TRIGCTRL is set.
Only one signal input is supported by the USART.
The AUTOTX feature can also be enabled via PRS. If an external SPI device sets a pin high when there is data to be read from the
device, this signal can be routed to the USART through the PRS system and be used to make the USART clock data out of the external
device. If AUTOTXTEN in USARTn_TRIGCTRL is set, the USART will transmit data whenever the PRS signal selected by TSEL is high
given that there is enough room in the RX buffer for the chosen frame size. Note that if there is no data in the TX buffer when using
AUTOTX, the TX underflow interrupt will be set.
AUTOTXTEN can also be combined with TXTEN to make the USART transmit a command to the external device prior to clocking out
data. To do this, disable TX using the TXDIS command, load the TX buffer with the command and enable AUTOTXTEN and TXTEN.
When the selected PRS input goes high, the USART will now transmit the loaded command, and then continue clocking out while both
the PRS input is high and there is room in the RX buffer.
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17.3.5 PRS RX Input
The USART can be configured to receive data directly from a PRS channel by setting RXPRS in USARTn_INPUT. The PRS channel
used is selected using RXPRSSEL in USARTn_INPUT. This way, for example, a differential RX signal can be input to the ACMP and
the output routed via PRS to the USART.
17.3.6 DMA Support
The USART has full DMA support. The DMA controller can write to the transmit buffer using the registers USARTn_TXDATA,
USARTn_TXDATAX, USARTn_TXDOUBLE and USARTn_TXDOUBLEX, and it can read from the receive buffer using the registers
USARTn_RXDATA, USARTn_RXDATAX, USARTn_RXDOUBLE and USARTn_RXDOUBLEX. This enables single byte transfers, 9 bit
data + control/status bits, double byte and double byte + control/status transfers both to and from the USART.
A request for the DMA controller to read from the USART receive buffer can come from the following source:
• Data available in the receive buffer.
• Data available in the receive buffer and data is for the RIGHT I2S channel. Only used in I2S mode.
A write request can come from one of the following sources:
• Transmit buffer and shift register empty. No data to send.
• Transmit buffer has room for more data.
• Transmit buffer has room for RIGHT I2S data. Only used in I2S mode.
Even though there are two sources for write requests to the DMA, only one should be used at a time, since the requests from both
sources are cleared even though only one of the requests are used.
In some cases, it may be sensible to temporarily stop DMA access to the USART when an error such as a framing error has occurred.
This is enabled by setting ERRSDMA in USARTn_CTRL.
17.3.7 Transmission Delay
By configuring TXDELAY in USARTn_CTRL, the transmitter can be forced to wait a number of bitperiods from it is ready to transmit
data, to it actually transmits the data. This delay is only applied to the first frame transmitted after the transmitter has been idle. When
transmitting frames back-to-back the delay is not introduced between the transmitted frames.
This is useful on half duplex buses, because the receiver always returns received frames to software during the first stop-bit. The bus
may still be driven for up to 3 baud periods, depending on the current frame format. Using the transmission delay, a transmission can
be started when a frame is received, and it is possible to make sure that the transmitter does not begin driving the output before the
frame on the bus is completely transmitted.
TXDELAY in USARTn_CTRL only applies to asynchronous transmission.
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17.3.8 Interrupts
The interrupts generated by the USART are combined into two interrupt vectors. Interrupts related to reception are assigned to one
interrupt vector, and interrupts related to transmission are assigned to the other. Separating the interrupts in this way allows different
priorities to be set for transmission and reception interrupts.
The transmission interrupt vector groups the transmission-related interrupts generated by the following interrupt flags:
• TXC
• TXBL
• TXOF
• CCF
The reception interrupt on the other hand groups the reception-related interrupts, triggered by the following interrupt flags:
• RXDATAV
• RXFULL
• RXOF
• RXUF
• PERR
• FERR
• MPAF
• SSM
If USART interrupts are enabled, an interrupt will be made if one or more of the interrupt flags in USART_IF and their corresponding
bits in USART_IEN are set.
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17.3.9 IrDA Modulator/Demodulator
The IrDA modulator on USART0 implements the physical layer of the IrDA specification, which is necessary for communication over
IrDA. The modulator takes the signal output from the USART module, and modulates it before it leaves USART0. In the same way, the
input signal is demodulated before it enters the actual USART module. The modulator is only available on USART0, and implements
the original Rev. 1.0 physical layer and one high speed extension which supports speeds from 2.4 kbps to 1.152 Mbps.
The data from and to the USART is represented in a NRZ (Non Return to Zero) format, where the signal value is at the same level
through the entire bit period. For IrDA, the required format is RZI (Return to Zero Inverted), a format where a “1” is signalled by holding
the line low, and a “0” is signalled by a short high pulse. An example is given in the following figure.
S 0 1 2 34 5 6 7 PStop
IdleIdle
USART
(NRZ)
IrDA
(RZI)
Figure 17.23. USART Example RZI Signal for a Given Asynchronous USART Frame
The IrDA module is enabled by setting IREN. The USART transmitter output and receiver input is then routed through the IrDA modula-
tor.
The width of the pulses generated by the IrDA modulator is set by configuring IRPW in USARTn_IRCTRL. Four pulse widths are availa-
ble, each defined relative to the configured bit period as listed in the following table.
Table 17.10. USART IrDA Pulse Widths
IRPW Pulse width OVS=0 Pulse width OVS=1 Pulse width OVS=2 Pulse width OVS=3
00 1/16 1/8 1/6 1/4
01 2/16 2/8 2/6 N/A
10 3/16 3/8 N/A N/A
11 4/16 N/A N/A N/A
By default, no filter is enabled in the IrDA demodulator. A filter can be enabled by setting IRFILT in USARTn_IRCTRL. When the filter is
enabled, an incoming pulse has to last for 4 consecutive clock cycles to be detected by the IrDA demodulator.
Note that by default, the idle value of the USART data signal is high. This means that the IrDA modulator generates negative pulses,
and the IrDA demodulator expects negative pulses. To make the IrDA module use RZI signalling, both TXINV and RXINV in
USARTn_CTRL must be set.
The IrDA module can also modulate a signal from the PRS system, and transmit a modulated signal to the PRS system. To use a PRS
channel as transmitter source instead of the USART, set IRPRSEN in USARTn_IRCTRL high. The channel is selected by configuring
IRPRSSEL in USARTn_IRCTRL.
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17.4 Register Map
The offset register address is relative to the registers base address.
Offset Name Type Description
0x000 USARTn_CTRL RW Control Register
0x004 USARTn_FRAME RW USART Frame Format Register
0x008 USARTn_TRIGCTRL RW USART Trigger Control register
0x00C USARTn_CMD W1 Command Register
0x010 USARTn_STATUS RUSART Status Register
0x014 USARTn_CLKDIV RW Clock Control Register
0x018 USARTn_RXDATAX R(a) RX Buffer Data Extended Register
0x01C USARTn_RXDATA R(a) RX Buffer Data Register
0x020 USARTn_RXDOUBLEX R(a) RX Buffer Double Data Extended Register
0x024 USARTn_RXDOUBLE R(a) RX FIFO Double Data Register
0x028 USARTn_RXDATAXP RRX Buffer Data Extended Peek Register
0x02C USARTn_RXDOUBLEXP RRX Buffer Double Data Extended Peek Register
0x030 USARTn_TXDATAX WTX Buffer Data Extended Register
0x034 USARTn_TXDATA WTX Buffer Data Register
0x038 USARTn_TXDOUBLEX WTX Buffer Double Data Extended Register
0x03C USARTn_TXDOUBLE WTX Buffer Double Data Register
0x040 USARTn_IF RInterrupt Flag Register
0x044 USARTn_IFS W1 Interrupt Flag Set Register
0x048 USARTn_IFC (R)W1 Interrupt Flag Clear Register
0x04C USARTn_IEN RW Interrupt Enable Register
0x050 USARTn_IRCTRL RW IrDA Control Register
0x054 USARTn_ROUTE RW I/O Routing Register
0x058 USARTn_INPUT RW USART Input Register
0x05C USARTn_I2SCTRL RW I2S Control Register
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17.5 Register Description
17.5.1 USARTn_CTRL - Control Register
Offset Bit Position
0x000
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
16
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
Reset
0
0
0
0
0x0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0x0
0
0
0
0
0
Access
RW
RW
RW
RW
RW
RW
RW
RW
RW
RW
RW
RW
RW
RW
RW
RW
RW
RW
RW
RW
RW
RW
RW
RW
RW
RW
RW
RW
RW
Name
SMSDELAY
MVDIS
AUTOTX
BYTESWAP
TXDELAY
SSSEARLY
ERRSTX
ERRSRX
ERRSDMA
BIT8DV
SKIPPERRF
SCRETRANS
SCMODE
AUTOTRI
AUTOCS
CSINV
TXINV
RXINV
TXBIL
CSMA
MSBF
CLKPHA
CLKPOL
OVS
MPAB
MPM
CCEN
LOOPBK
SYNC
Bit Name Reset Access Description
31 SMSDELAY 0 RW Synchronous Master Sample Delay
Delay Synchronous Master sample point to the next setup edge to improve timing and allow communication at higher
speeds.
30 MVDIS 0 RW Majority Vote Disable
Disable majority vote for 16x, 8x and 6x oversampling modes.
29 AUTOTX 0 RW Always Transmit When RX Not Full
Transmits as long as RX is not full. If TX is empty, underflows are generated.
28 BYTESWAP 0 RW Byteswap In Double Accesses
Set to switch the order of the bytes in double accesses.
Value Description
0 Normal byte order
1 Byte order swapped
27:26 TXDELAY 0x0 RW TX Delay Transmission
Configurable delay before new transfers. Frames sent back-to-back are not delayed.
Value Mode Description
0 NONE Frames are transmitted immediately
1 SINGLE Transmission of new frames are delayed by a single baud period
2 DOUBLE Transmission of new frames are delayed by two baud periods
3 TRIPLE Transmission of new frames are delayed by three baud periods
25 SSSEARLY 0 RW Synchronous Slave Setup Early
Setup data on sample edge in synchronous slave mode to improve MOSI setup time.
24 ERRSTX 0 RW Disable TX On Error
When set, the transmitter is disabled on framing and parity errors (asynchronous mode only) in the receiver.
Value Description
0 Received framing and parity errors have no effect on transmitter
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Bit Name Reset Access Description
1 Received framing and parity errors disable the transmitter
23 ERRSRX 0 RW Disable RX On Error
When set, the receiver is disabled on framing and parity errors (asynchronous mode only).
Value Description
0 Framing and parity errors have no effect on receiver
1 Framing and parity errors disable the receiver
22 ERRSDMA 0 RW Halt DMA On Error
When set, DMA requests will be cleared on framing and parity errors (asynchronous mode only).
Value Description
0 Framing and parity errors have no effect on DMA requests from the
USART
1 DMA requests from the USART are blocked while the PERR or FERR
interrupt flags are set
21 BIT8DV 0 RW Bit 8 Default Value
The default value of the 9th bit. If 9-bit frames are used, and an 8-bit write operation is done, leaving the 9th bit unspecified,
the 9th bit is set to the value of BIT8DV.
20 SKIPPERRF 0 RW Skip Parity Error Frames
When set, the receiver discards frames with parity errors (asynchronous mode only). The PERR interrupt flag is still set.
19 SCRETRANS 0 RW SmartCard Retransmit
When in SmartCard mode, a NACK'ed frame will be kept in the shift register and retransmitted if the transmitter is still ena-
bled.
18 SCMODE 0 RW SmartCard Mode
Use this bit to enable or disable SmartCard mode.
17 AUTOTRI 0 RW Automatic TX Tristate
When enabled, TXTRI is set by hardware whenever the transmitter is idle, and TXTRI is cleared by hardware when trans-
mission starts.
Value Description
0 The output on U(S)n_TX when the transmitter is idle is defined by
TXINV
1 U(S)n_TX is tristated whenever the transmitter is idle
16 AUTOCS 0 RW Automatic Chip Select
When enabled, the output on USn_CS will be activated one baud-period before transmission starts, and deactivated when
transmission ends.
15 CSINV 0 RW Chip Select Invert
Default value is active low. This affects both the selection of external slaves, as well as the selection of the microcontroller
as a slave.
Value Description
0 Chip select is active low
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Bit Name Reset Access Description
1 Chip select is active high
14 TXINV 0 RW Transmitter output Invert
The output from the USART transmitter can optionally be inverted by setting this bit.
Value Description
0 Output from the transmitter is passed unchanged to U(S)n_TX
1 Output from the transmitter is inverted before it is passed to U(S)n_TX
13 RXINV 0 RW Receiver Input Invert
Setting this bit will invert the input to the USART receiver.
Value Description
0 Input is passed directly to the receiver
1 Input is inverted before it is passed to the receiver
12 TXBIL 0 RW TX Buffer Interrupt Level
Determines the interrupt and status level of the transmit buffer.
Value Mode Description
0 EMPTY TXBL and the TXBL interrupt flag are set when the transmit buffer be-
comes empty. TXBL is cleared when the buffer becomes nonempty.
1 HALFFULL TXBL and TXBLIF are set when the transmit buffer goes from full to
half-full or empty. TXBL is cleared when the buffer becomes full.
11 CSMA 0 RW Action On Slave-Select In Master Mode
This register determines the action to be performed when slave-select is configured as an input and driven low while in
master mode.
Value Mode Description
0 NOACTION No action taken
1 GOTOSLAVEMODE Go to slave mode
10 MSBF 0 RW Most Significant Bit First
Decides whether data is sent with the least significant bit first, or the most significant bit first.
Value Description
0 Data is sent with the least significant bit first
1 Data is sent with the most significant bit first
9 CLKPHA 0 RW Clock Edge For Setup/Sample
Determines where data is set-up and sampled according to the bus clock when in synchronous mode.
Value Mode Description
0 SAMPLELEADING Data is sampled on the leading edge and set-up on the trailing edge of
the bus clock in synchronous mode
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Bit Name Reset Access Description
1 SAMPLETRAILING Data is set-up on the leading edge and sampled on the trailing edge of
the bus clock in synchronous mode
8 CLKPOL 0 RW Clock Polarity
Determines the clock polarity of the bus clock used in synchronous mode.
Value Mode Description
0 IDLELOW The bus clock used in synchronous mode has a low base value
1 IDLEHIGH The bus clock used in synchronous mode has a high base value
7 Reserved To ensure compatibility with future devices, always write bits to 0. More information in 2.1 Conven-
tions.
6:5 OVS 0x0 RW Oversampling
Sets the number of clock periods in a UART bit-period. More clock cycles gives better robustness, while less clock cycles
gives better performance.
Value Mode Description
0 X16 Regular UART mode with 16X oversampling in asynchronous mode
1 X8 Double speed with 8X oversampling in asynchronous mode
2 X6 6X oversampling in asynchronous mode
3 X4 Quadruple speed with 4X oversampling in asynchronous mode
4 MPAB 0 RW Multi-Processor Address-Bit
Defines the value of the multi-processor address bit. An incoming frame with its 9th bit equal to the value of this bit marks
the frame as a multi-processor address frame.
3 MPM 0 RW Multi-Processor Mode
Multi-processor mode uses the 9th bit of the USART frames to tell whether the frame is an address frame or a data frame.
Value Description
0 The 9th bit of incoming frames has no special function
1 An incoming frame with the 9th bit equal to MPAB will be loaded into
the receive buffer regardless of RXBLOCK and will result in the MPAB
interrupt flag being set
2 CCEN 0 RW Collision Check Enable
Enables collision checking on data when operating in half duplex modus.
Value Description
0 Collision check is disabled
1 Collision check is enabled. The receiver must be enabled for the check
to be performed
1 LOOPBK 0 RW Loopback Enable
Allows the receiver to be connected directly to the USART transmitter for loopback and half duplex communication.
Value Description
0 The receiver is connected to and receives data from U(S)n_RX
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Bit Name Reset Access Description
1 The receiver is connected to and receives data from U(S)n_TX
0 SYNC 0 RW USART Synchronous Mode
Determines whether the USART is operating in asynchronous or synchronous mode.
Value Description
0 The USART operates in asynchronous mode
1 The USART operates in synchronous mode
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17.5.2 USARTn_FRAME - USART Frame Format Register
Offset Bit Position
0x004
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
16
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
Reset
0x1
0x0
0x5
Access
RW
RW
RW
Name
STOPBITS
PARITY
DATABITS
Bit Name Reset Access Description
31:14 Reserved To ensure compatibility with future devices, always write bits to 0. More information in 2.1 Conven-
tions.
13:12 STOPBITS 0x1 RW Stop-Bit Mode
Determines the number of stop-bits used.
Value Mode Description
0 HALF The transmitter generates a half stop bit. Stop-bits are not verified by
receiver
1 ONE One stop bit is generated and verified
2 ONEANDAHALF The transmitter generates one and a half stop bit. The receiver verifies
the first stop bit
3 TWO The transmitter generates two stop bits. The receiver checks the first
stop-bit only
11:10 Reserved To ensure compatibility with future devices, always write bits to 0. More information in 2.1 Conven-
tions.
9:8 PARITY 0x0 RW Parity-Bit Mode
Determines whether parity bits are enabled, and whether even or odd parity should be used. Only available in asynchro-
nous mode.
Value Mode Description
0 NONE Parity bits are not used
2 EVEN Even parity are used. Parity bits are automatically generated and
checked by hardware.
3 ODD Odd parity is used. Parity bits are automatically generated and checked
by hardware.
7:4 Reserved To ensure compatibility with future devices, always write bits to 0. More information in 2.1 Conven-
tions.
3:0 DATABITS 0x5 RW Data-Bit Mode
This register sets the number of data bits in a USART frame.
Value Mode Description
1 FOUR Each frame contains 4 data bits
2 FIVE Each frame contains 5 data bits
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Bit Name Reset Access Description
3 SIX Each frame contains 6 data bits
4 SEVEN Each frame contains 7 data bits
5 EIGHT Each frame contains 8 data bits
6 NINE Each frame contains 9 data bits
7 TEN Each frame contains 10 data bits
8 ELEVEN Each frame contains 11 data bits
9 TWELVE Each frame contains 12 data bits
10 THIRTEEN Each frame contains 13 data bits
11 FOURTEEN Each frame contains 14 data bits
12 FIFTEEN Each frame contains 15 data bits
13 SIXTEEN Each frame contains 16 data bits
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17.5.3 USARTn_TRIGCTRL - USART Trigger Control register
Offset Bit Position
0x008
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
16
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
Reset
0
0
0
0x0
Access
RW
RW
RW
RW
Name
AUTOTXTEN
TXTEN
RXTEN
TSEL
Bit Name Reset Access Description
31:7 Reserved To ensure compatibility with future devices, always write bits to 0. More information in 2.1 Conven-
tions.
6 AUTOTXTEN 0 RW AUTOTX Trigger Enable
When set, AUTOTX is enabled as long as the PRS channel selected by TSEL has a high value.
5 TXTEN 0 RW Transmit Trigger Enable
When set, the PRS channel selected by TSEL sets TXEN, enabling the transmitter on positive trigger edges.
4 RXTEN 0 RW Receive Trigger Enable
When set, the PRS channel selected by TSEL sets RXEN, enabling the receiver on positive trigger edges.
3 Reserved To ensure compatibility with future devices, always write bits to 0. More information in 2.1 Conven-
tions.
2:0 TSEL 0x0 RW Trigger PRS Channel Select
Select USART PRS trigger channel. The PRS signal can enable RX and/or TX, depending on the setting of RXTEN and
TXTEN.
Value Mode Description
0 PRSCH0 PRS Channel 0 selected
1 PRSCH1 PRS Channel 1 selected
2 PRSCH2 PRS Channel 2 selected
3 PRSCH3 PRS Channel 3 selected
4 PRSCH4 PRS Channel 4 selected
5 PRSCH5 PRS Channel 5 selected
6 PRSCH6 PRS Channel 6 selected
7 PRSCH7 PRS Channel 7 selected
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17.5.4 USARTn_CMD - Command Register
Offset Bit Position
0x00C
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
16
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
Reset
0
0
0
0
0
0
0
0
0
0
0
0
Access
W1
W1
W1
W1
W1
W1
W1
W1
W1
W1
W1
W1
Name
CLEARRX
CLEARTX
TXTRIDIS
TXTRIEN
RXBLOCKDIS
RXBLOCKEN
MASTERDIS
MASTEREN
TXDIS
TXEN
RXDIS
RXEN
Bit Name Reset Access Description
31:12 Reserved To ensure compatibility with future devices, always write bits to 0. More information in 2.1 Conven-
tions.
11 CLEARRX 0 W1 Clear RX
Set to clear receive buffer and the RX shift register.
10 CLEARTX 0 W1 Clear TX
Set to clear transmit buffer and the TX shift register.
9 TXTRIDIS 0 W1 Transmitter Tristate Disable
Disables tristating of the transmitter output.
8 TXTRIEN 0 W1 Transmitter Tristate Enable
Tristates the transmitter output.
7 RXBLOCKDIS 0 W1 Receiver Block Disable
Set to clear RXBLOCK, resulting in all incoming frames being loaded into the receive buffer.
6 RXBLOCKEN 0 W1 Receiver Block Enable
Set to set RXBLOCK, resulting in all incoming frames being discarded.
5 MASTERDIS 0 W1 Master Disable
Set to disable master mode, clearing the MASTER status bit and putting the USART in slave mode.
4 MASTEREN 0 W1 Master Enable
Set to enable master mode, setting the MASTER status bit. Master mode should not be enabled while TXENS is set to 1.
To enable both master and TX mode, write MASTEREN before TXEN, or enable them both in the same write operation.
3 TXDIS 0 W1 Transmitter Disable
Set to disable transmission.
2 TXEN 0 W1 Transmitter Enable
Set to enable data transmission.
1 RXDIS 0 W1 Receiver Disable
Set to disable data reception. If a frame is under reception when the receiver is disabled, the incoming frame is discarded.
0 RXEN 0 W1 Receiver Enable
Set to activate data reception on U(S)n_RX.
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17.5.5 USARTn_STATUS - USART Status Register
Offset Bit Position
0x010
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
16
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
Reset
0
0
0
0
0
0
1
0
0
0
0
0
0
Access
R
R
R
R
R
R
R
R
R
R
R
R
R
Name
RXFULLRIGHT
RXDATAVRIGHT
TXBSRIGHT
TXBDRIGHT
RXFULL
RXDATAV
TXBL
TXC
TXTRI
RXBLOCK
MASTER
TXENS
RXENS
Bit Name Reset Access Description
31:13 Reserved To ensure compatibility with future devices, always write bits to 0. More information in 2.1 Conven-
tions.
12 RXFULLRIGHT 0 R RX Full of Right Data
When set, the entire RX buffer contains right data. Only used in I2S mode.
11 RXDATAVRIGHT 0 R RX Data Right
When set, reading RXDATA or RXDATAX gives right data. Else left data is read. Only used in I2S mode.
10 TXBSRIGHT 0 R TX Buffer Expects Single Right Data
When set, the TX buffer expects at least a single right data. Else it expects left data. Only used in I2S mode.
9 TXBDRIGHT 0 R TX Buffer Expects Double Right Data
When set, the TX buffer expects double right data. Else it may expect a single right data or left data. Only used in I2S
mode.
8 RXFULL 0 R RX FIFO Full
Set when the RXFIFO is full. Cleared when the receive buffer is no longer full. When this bit is set, there is still room for one
more frame in the receive shift register.
7 RXDATAV 0 R RX Data Valid
Set when data is available in the receive buffer. Cleared when the receive buffer is empty.
6 TXBL 1 R TX Buffer Level
Indicates the level of the transmit buffer. If TXBIL is cleared, TXBL is set whenever the transmit buffer is empty, and if
TXBIL is set, TXBL is set whenever the transmit buffer is half-full or empty.
5 TXC 0 R TX Complete
Set when a transmission has completed and no more data is available in the transmit buffer and shift register. Cleared
when data is written to the transmit buffer.
4 TXTRI 0 R Transmitter Tristated
Set when the transmitter is tristated, and cleared when transmitter output is enabled. If AUTOTRI in USARTn_CTRL is set
this bit is always read as 0.
3 RXBLOCK 0 R Block Incoming Data
When set, the receiver discards incoming frames. An incoming frame will not be loaded into the receive buffer if this bit is
set at the instant the frame has been completely received.
2 MASTER 0 R SPI Master Mode
Set when the USART operates as a master. Set using the MASTEREN command and clear using the MASTERDIS com-
mand.
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Bit Name Reset Access Description
1 TXENS 0 R Transmitter Enable Status
Set when the transmitter is enabled.
0 RXENS 0 R Receiver Enable Status
Set when the receiver is enabled.
17.5.6 USARTn_CLKDIV - Clock Control Register
Offset Bit Position
0x014
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
16
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
Reset
0x0000
Access
RW
Name
DIV
Bit Name Reset Access Description
31:21 Reserved To ensure compatibility with future devices, always write bits to 0. More information in 2.1 Conven-
tions.
20:6 DIV 0x0000 RW Fractional Clock Divider
Specifies the fractional clock divider for the USART.
5:0 Reserved To ensure compatibility with future devices, always write bits to 0. More information in 2.1 Conven-
tions.
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17.5.7 USARTn_RXDATAX - RX Buffer Data Extended Register (Actionable Reads)
Offset Bit Position
0x018
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
16
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
Reset
0
0
0x000
Access
R
R
R
Name
FERR
PERR
RXDATA
Bit Name Reset Access Description
31:16 Reserved To ensure compatibility with future devices, always write bits to 0. More information in 2.1 Conven-
tions.
15 FERR 0 R Data Framing Error
Set if data in buffer has a framing error. Can be the result of a break condition.
14 PERR 0 R Data Parity Error
Set if data in buffer has a parity error (asynchronous mode only).
13:9 Reserved To ensure compatibility with future devices, always write bits to 0. More information in 2.1 Conven-
tions.
8:0 RXDATA 0x000 R RX Data
Use this register to access data read from the USART. Buffer is cleared on read access.
17.5.8 USARTn_RXDATA - RX Buffer Data Register (Actionable Reads)
Offset Bit Position
0x01C
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
16
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
Reset
0x00
Access
R
Name
RXDATA
Bit Name Reset Access Description
31:8 Reserved To ensure compatibility with future devices, always write bits to 0. More information in 2.1 Conven-
tions.
7:0 RXDATA 0x00 R RX Data
Use this register to access data read from USART. Buffer is cleared on read access. Only the 8 LSB can be read using this
register.
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17.5.9 USARTn_RXDOUBLEX - RX Buffer Double Data Extended Register (Actionable Reads)
Offset Bit Position
0x020
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
16
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
Reset
0
0
0x000
0
0
0x000
Access
R
R
R
R
R
R
Name
FERR1
PERR1
RXDATA1
FERR0
PERR0
RXDATA0
Bit Name Reset Access Description
31 FERR1 0 R Data Framing Error 1
Set if data in buffer has a framing error. Can be the result of a break condition.
30 PERR1 0 R Data Parity Error 1
Set if data in buffer has a parity error (asynchronous mode only).
29:25 Reserved To ensure compatibility with future devices, always write bits to 0. More information in 2.1 Conven-
tions.
24:16 RXDATA1 0x000 R RX Data 1
Second frame read from buffer.
15 FERR0 0 R Data Framing Error 0
Set if data in buffer has a framing error. Can be the result of a break condition.
14 PERR0 0 R Data Parity Error 0
Set if data in buffer has a parity error (asynchronous mode only).
13:9 Reserved To ensure compatibility with future devices, always write bits to 0. More information in 2.1 Conven-
tions.
8:0 RXDATA0 0x000 R RX Data 0
First frame read from buffer.
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17.5.10 USARTn_RXDOUBLE - RX FIFO Double Data Register (Actionable Reads)
Offset Bit Position
0x024
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
16
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
Reset
0x00
0x00
Access
R
R
Name
RXDATA1
RXDATA0
Bit Name Reset Access Description
31:16 Reserved To ensure compatibility with future devices, always write bits to 0. More information in 2.1 Conven-
tions.
15:8 RXDATA1 0x00 R RX Data 1
Second frame read from buffer.
7:0 RXDATA0 0x00 R RX Data 0
First frame read from buffer.
17.5.11 USARTn_RXDATAXP - RX Buffer Data Extended Peek Register
Offset Bit Position
0x028
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
16
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
Reset
0
0
0x000
Access
R
R
R
Name
FERRP
PERRP
RXDATAP
Bit Name Reset Access Description
31:16 Reserved To ensure compatibility with future devices, always write bits to 0. More information in 2.1 Conven-
tions.
15 FERRP 0 R Data Framing Error Peek
Set if data in buffer has a framing error. Can be the result of a break condition.
14 PERRP 0 R Data Parity Error Peek
Set if data in buffer has a parity error (asynchronous mode only).
13:9 Reserved To ensure compatibility with future devices, always write bits to 0. More information in 2.1 Conven-
tions.
8:0 RXDATAP 0x000 R RX Data Peek
Use this register to access data read from the USART.
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17.5.12 USARTn_RXDOUBLEXP - RX Buffer Double Data Extended Peek Register
Offset Bit Position
0x02C
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
16
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
Reset
0
0
0x000
0
0
0x000
Access
R
R
R
R
R
R
Name
FERRP1
PERRP1
RXDATAP1
FERRP0
PERRP0
RXDATAP0
Bit Name Reset Access Description
31 FERRP1 0 R Data Framing Error 1 Peek
Set if data in buffer has a framing error. Can be the result of a break condition.
30 PERRP1 0 R Data Parity Error 1 Peek
Set if data in buffer has a parity error (asynchronous mode only).
29:25 Reserved To ensure compatibility with future devices, always write bits to 0. More information in 2.1 Conven-
tions.
24:16 RXDATAP1 0x000 R RX Data 1 Peek
Second frame read from FIFO.
15 FERRP0 0 R Data Framing Error 0 Peek
Set if data in buffer has a framing error. Can be the result of a break condition.
14 PERRP0 0 R Data Parity Error 0 Peek
Set if data in buffer has a parity error (asynchronous mode only).
13:9 Reserved To ensure compatibility with future devices, always write bits to 0. More information in 2.1 Conven-
tions.
8:0 RXDATAP0 0x000 R RX Data 0 Peek
First frame read from FIFO.
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17.5.13 USARTn_TXDATAX - TX Buffer Data Extended Register
Offset Bit Position
0x030
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
16
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
Reset
0
0
0
0
0
0x000
Access
W
W
W
W
W
W
Name
RXENAT
TXDISAT
TXBREAK
TXTRIAT
UBRXAT
TXDATAX
Bit Name Reset Access Description
31:16 Reserved To ensure compatibility with future devices, always write bits to 0. More information in 2.1 Conven-
tions.
15 RXENAT 0 W Enable RX After Transmission
Set to enable reception after transmission.
14 TXDISAT 0 W Clear TXEN After Transmission
Set to disable transmitter and release data bus directly after transmission.
13 TXBREAK 0 W Transmit Data As Break
Set to send data as a break. Recipient will see a framing error or a break condition depending on its configuration and the
value of TXDATA.
12 TXTRIAT 0 W Set TXTRI After Transmission
Set to tristate transmitter by setting TXTRI after transmission.
11 UBRXAT 0 W Unblock RX After Transmission
Set clear RXBLOCK after transmission, unblocking the receiver.
10:9 Reserved To ensure compatibility with future devices, always write bits to 0. More information in 2.1 Conven-
tions.
8:0 TXDATAX 0x000 W TX Data
Use this register to write data to the USART. If TXEN is set, a transfer will be initiated at the first opportunity.
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17.5.14 USARTn_TXDATA - TX Buffer Data Register
Offset Bit Position
0x034
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
16
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
Reset
0x00
Access
W
Name
TXDATA
Bit Name Reset Access Description
31:8 Reserved To ensure compatibility with future devices, always write bits to 0. More information in 2.1 Conven-
tions.
7:0 TXDATA 0x00 W TX Data
This frame will be added to TX buffer. Only 8 LSB can be written using this register. 9th bit and control bits will be cleared.
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17.5.15 USARTn_TXDOUBLEX - TX Buffer Double Data Extended Register
Offset Bit Position
0x038
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
16
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
Reset
0
0
0
0
0
0x000
0
0
0
0
0
0x000
Access
W
W
W
W
W
W
W
W
W
W
W
W
Name
RXENAT1
TXDISAT1
TXBREAK1
TXTRIAT1
UBRXAT1
TXDATA1
RXENAT0
TXDISAT0
TXBREAK0
TXTRIAT0
UBRXAT0
TXDATA0
Bit Name Reset Access Description
31 RXENAT1 0 W Enable RX After Transmission
Set to enable reception after transmission.
30 TXDISAT1 0 W Clear TXEN After Transmission
Set to disable transmitter and release data bus directly after transmission.
29 TXBREAK1 0 W Transmit Data As Break
Set to send data as a break. Recipient will see a framing error or a break condition depending on its configuration and the
value of USARTn_TXDATA.
28 TXTRIAT1 0 W Set TXTRI After Transmission
Set to tristate transmitter by setting TXTRI after transmission.
27 UBRXAT1 0 W Unblock RX After Transmission
Set clear RXBLOCK after transmission, unblocking the receiver.
26:25 Reserved To ensure compatibility with future devices, always write bits to 0. More information in 2.1 Conven-
tions.
24:16 TXDATA1 0x000 W TX Data
Second frame to write to FIFO.
15 RXENAT0 0 W Enable RX After Transmission
Set to enable reception after transmission.
14 TXDISAT0 0 W Clear TXEN After Transmission
Set to disable transmitter and release data bus directly after transmission.
13 TXBREAK0 0 W Transmit Data As Break
Set to send data as a break. Recipient will see a framing error or a break condition depending on its configuration and the
value of TXDATA.
12 TXTRIAT0 0 W Set TXTRI After Transmission
Set to tristate transmitter by setting TXTRI after transmission.
11 UBRXAT0 0 W Unblock RX After Transmission
Set clear RXBLOCK after transmission, unblocking the receiver.
10:9 Reserved To ensure compatibility with future devices, always write bits to 0. More information in 2.1 Conven-
tions.
8:0 TXDATA0 0x000 W TX Data
First frame to write to buffer.
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17.5.16 USARTn_TXDOUBLE - TX Buffer Double Data Register
Offset Bit Position
0x03C
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
16
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
Reset
0x00
0x00
Access
W
W
Name
TXDATA1
TXDATA0
Bit Name Reset Access Description
31:16 Reserved To ensure compatibility with future devices, always write bits to 0. More information in 2.1 Conven-
tions.
15:8 TXDATA1 0x00 W TX Data
Second frame to write to buffer.
7:0 TXDATA0 0x00 W TX Data
First frame to write to buffer.
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17.5.17 USARTn_IF - Interrupt Flag Register
Offset Bit Position
0x040
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
16
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
Reset
0
0
0
0
0
0
0
0
0
0
0
1
0
Access
R
R
R
R
R
R
R
R
R
R
R
R
R
Name
CCF
SSM
MPAF
FERR
PERR
TXUF
TXOF
RXUF
RXOF
RXFULL
RXDATAV
TXBL
TXC
Bit Name Reset Access Description
31:13 Reserved To ensure compatibility with future devices, always write bits to 0. More information in 2.1 Conven-
tions.
12 CCF 0 R Collision Check Fail Interrupt Flag
Set when a collision check notices an error in the transmitted data.
11 SSM 0 R Slave-Select In Master Mode Interrupt Flag
Set when the device is selected as a slave when in master mode.
10 MPAF 0 R Multi-Processor Address Frame Interrupt Flag
Set when a multi-processor address frame is detected.
9 FERR 0 R Framing Error Interrupt Flag
Set when a frame with a framing error is received while RXBLOCK is cleared.
8 PERR 0 R Parity Error Interrupt Flag
Set when a frame with a parity error (asynchronous mode only) is received while RXBLOCK is cleared.
7 TXUF 0 R TX Underflow Interrupt Flag
Set when operating as a synchronous slave, no data is available in the transmit buffer when the master starts transmission
of a new frame.
6 TXOF 0 R TX Overflow Interrupt Flag
Set when a write is done to the transmit buffer while it is full. The data already in the transmit buffer is preserved.
5 RXUF 0 R RX Underflow Interrupt Flag
Set when trying to read from the receive buffer when it is empty.
4 RXOF 0 R RX Overflow Interrupt Flag
Set when data is incoming while the receive shift register is full. The data previously in the shift register is lost.
3 RXFULL 0 R RX Buffer Full Interrupt Flag
Set when the receive buffer becomes full.
2 RXDATAV 0 R RX Data Valid Interrupt Flag
Set when data becomes available in the receive buffer.
1 TXBL 1 R TX Buffer Level Interrupt Flag
Set when the buffer becomes empty if TXBIL is cleared, and is set whenever the transmit buffer goes from full to half-full or
empty if TXBIL is set.
0 TXC 0 R TX Complete Interrupt Flag
This interrupt is used after a transmission when both the TX buffer and shift register are empty.
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17.5.18 USARTn_IFS - Interrupt Flag Set Register
Offset Bit Position
0x044
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
16
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
Reset
0
0
0
0
0
0
0
0
0
0
0
Access
W1
W1
W1
W1
W1
W1
W1
W1
W1
W1
W1
Name
CCF
SSM
MPAF
FERR
PERR
TXUF
TXOF
RXUF
RXOF
RXFULL
TXC
Bit Name Reset Access Description
31:13 Reserved To ensure compatibility with future devices, always write bits to 0. More information in 2.1 Conven-
tions.
12 CCF 0 W1 Set Collision Check Fail Interrupt Flag
Write to 1 to set the CCF interrupt flag.
11 SSM 0 W1 Set Slave-Select in Master mode Interrupt Flag
Write to 1 to set the SSM interrupt flag.
10 MPAF 0 W1 Set Multi-Processor Address Frame Interrupt Flag
Write to 1 to set the MPAF interrupt flag.
9 FERR 0 W1 Set Framing Error Interrupt Flag
Write to 1 to set the FERR interrupt flag.
8 PERR 0 W1 Set Parity Error Interrupt Flag
Write to 1 to set the PERR interrupt flag.
7 TXUF 0 W1 Set TX Underflow Interrupt Flag
Write to 1 to set the TXUF interrupt flag.
6 TXOF 0 W1 Set TX Overflow Interrupt Flag
Write to 1 to set the TXOF interrupt flag.
5 RXUF 0 W1 Set RX Underflow Interrupt Flag
Write to 1 to set the RXUF interrupt flag.
4 RXOF 0 W1 Set RX Overflow Interrupt Flag
Write to 1 to set the RXOF interrupt flag.
3 RXFULL 0 W1 Set RX Buffer Full Interrupt Flag
Write to 1 to set the RXFULL interrupt flag.
2:1 Reserved To ensure compatibility with future devices, always write bits to 0. More information in 2.1 Conven-
tions.
0 TXC 0 W1 Set TX Complete Interrupt Flag
Write to 1 to set the TXC interrupt flag.
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17.5.19 USARTn_IFC - Interrupt Flag Clear Register
Offset Bit Position
0x048
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
16
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
Reset
0
0
0
0
0
0
0
0
0
0
0
Access
(R)W1
(R)W1
(R)W1
(R)W1
(R)W1
(R)W1
(R)W1
(R)W1
(R)W1
(R)W1
(R)W1
Name
CCF
SSM
MPAF
FERR
PERR
TXUF
TXOF
RXUF
RXOF
RXFULL
TXC
Bit Name Reset Access Description
31:13 Reserved To ensure compatibility with future devices, always write bits to 0. More information in 2.1 Conven-
tions.
12 CCF 0 (R)W1 Clear Collision Check Fail Interrupt Flag
Write to 1 to clear the CCF interrupt flag.
11 SSM 0 (R)W1 Clear Slave-Select In Master Mode Interrupt Flag
Write to 1 to clear the SSM interrupt flag.
10 MPAF 0 (R)W1 Clear Multi-Processor Address Frame Interrupt Flag
Write to 1 to clear the MPAF interrupt flag.
9 FERR 0 (R)W1 Clear Framing Error Interrupt Flag
Write to 1 to clear the FERR interrupt flag.
8 PERR 0 (R)W1 Clear Parity Error Interrupt Flag
Write to 1 to clear the PERR interrupt flag.
7 TXUF 0 (R)W1 Clear TX Underflow Interrupt Flag
Write to 1 to clear the TXUF interrupt flag.
6 TXOF 0 (R)W1 Clear TX Overflow Interrupt Flag
Write to 1 to clear the TXOF interrupt flag.
5 RXUF 0 (R)W1 Clear RX Underflow Interrupt Flag
Write to 1 to clear the RXUF interrupt flag.
4 RXOF 0 (R)W1 Clear RX Overflow Interrupt Flag
Write to 1 to clear the RXOF interrupt flag.
3 RXFULL 0 (R)W1 Clear RX Buffer Full Interrupt Flag
Write to 1 to clear the RXFULL interrupt flag.
2:1 Reserved To ensure compatibility with future devices, always write bits to 0. More information in 2.1 Conven-
tions.
0 TXC 0 (R)W1 Clear TX Complete Interrupt Flag
Write to 1 to clear the TXC interrupt flag.
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17.5.20 USARTn_IEN - Interrupt Enable Register
Offset Bit Position
0x04C
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
16
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
Reset
0
0
0
0
0
0
0
0
0
0
0
0
0
Access
RW
RW
RW
RW
RW
RW
RW
RW
RW
RW
RW
RW
RW
Name
CCF
SSM
MPAF
FERR
PERR
TXUF
TXOF
RXUF
RXOF
RXFULL
RXDATAV
TXBL
TXC
Bit Name Reset Access Description
31:13 Reserved To ensure compatibility with future devices, always write bits to 0. More information in 2.1 Conven-
tions.
12 CCF 0 RW Collision Check Fail Interrupt Enable
Enable interrupt on collision check error detected.
11 SSM 0 RW Slave-Select In Master Mode Interrupt Enable
Enable interrupt on slave-select in master mode.
10 MPAF 0 RW Multi-Processor Address Frame Interrupt Enable
Enable interrupt on multi-processor address frame.
9 FERR 0 RW Framing Error Interrupt Enable
Enable interrupt on framing error.
8 PERR 0 RW Parity Error Interrupt Enable
Enable interrupt on parity error (asynchronous mode only).
7 TXUF 0 RW TX Underflow Interrupt Enable
Enable interrupt on TX underflow.
6 TXOF 0 RW TX Overflow Interrupt Enable
Enable interrupt on TX overflow.
5 RXUF 0 RW RX Underflow Interrupt Enable
Enable interrupt on RX underflow.
4 RXOF 0 RW RX Overflow Interrupt Enable
Enable interrupt on RX overflow.
3 RXFULL 0 RW RX Buffer Full Interrupt Enable
Enable interrupt on RX Buffer full.
2 RXDATAV 0 RW RX Data Valid Interrupt Enable
Enable interrupt on RX data.
1 TXBL 0 RW TX Buffer Level Interrupt Enable
Enable interrupt on TX buffer level.
0 TXC 0 RW TX Complete Interrupt Enable
Enable interrupt on TX complete.
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17.5.21 USARTn_IRCTRL - IrDA Control Register
Offset Bit Position
0x050
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
16
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
Reset
0
0x0
0
0x0
0
Access
RW
RW
RW
RW
RW
Name
IRPRSEN
IRPRSSEL
IRFILT
IRPW
IREN
Bit Name Reset Access Description
31:8 Reserved To ensure compatibility with future devices, always write bits to 0. More information in 2.1 Conven-
tions.
7 IRPRSEN 0 RW IrDA PRS Channel Enable
Enable the PRS channel selected by IRPRSSEL as input to IrDA module instead of TX.
6:4 IRPRSSEL 0x0 RW IrDA PRS Channel Select
A PRS can be used as input to the pulse modulator instead of TX. This value selects the channel to use.
Value Mode Description
0 PRSCH0 PRS Channel 0 selected
1 PRSCH1 PRS Channel 1 selected
2 PRSCH2 PRS Channel 2 selected
3 PRSCH3 PRS Channel 3 selected
4 PRSCH4 PRS Channel 4 selected
5 PRSCH5 PRS Channel 5 selected
6 PRSCH6 PRS Channel 6 selected
7 PRSCH7 PRS Channel 7 selected
3 IRFILT 0 RW IrDA RX Filter
Set to enable filter on IrDA demodulator.
Value Description
0 No filter enabled
1 Filter enabled. IrDA pulse must be high for at least 4 consecutive clock
cycles to be detected
2:1 IRPW 0x0 RW IrDA TX Pulse Width
Configure the pulse width generated by the IrDA modulator as a fraction of the configured USART bit period.
Value Mode Description
0 ONE IrDA pulse width is 1/16 for OVS=0 and 1/8 for OVS=1
1 TWO IrDA pulse width is 2/16 for OVS=0 and 2/8 for OVS=1
2 THREE IrDA pulse width is 3/16 for OVS=0 and 3/8 for OVS=1
3 FOUR IrDA pulse width is 4/16 for OVS=0 and 4/8 for OVS=1
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Bit Name Reset Access Description
0 IREN 0 RW Enable IrDA Module
Enable IrDA module and rout USART signals through it.
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17.5.22 USARTn_ROUTE - I/O Routing Register
Offset Bit Position
0x054
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
16
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
Reset
0x0
0
0
0
0
Access
RW
RW
RW
RW
RW
Name
LOCATION
CLKPEN
CSPEN
TXPEN
RXPEN
Bit Name Reset Access Description
31:11 Reserved To ensure compatibility with future devices, always write bits to 0. More information in 2.1 Conven-
tions.
10:8 LOCATION 0x0 RW I/O Location
Decides the location of the USART I/O pins.
Value Mode Description
0 LOC0 Location 0
1 LOC1 Location 1
2 LOC2 Location 2
3 LOC3 Location 3
4 LOC4 Location 4
5 LOC5 Location 5
7:4 Reserved To ensure compatibility with future devices, always write bits to 0. More information in 2.1 Conven-
tions.
3 CLKPEN 0 RW CLK Pin Enable
When set, the CLK pin of the USART is enabled.
Value Description
0 The USn_CLK pin is disabled
1 The USn_CLK pin is enabled
2 CSPEN 0 RW CS Pin Enable
When set, the CS pin of the USART is enabled.
Value Description
0 The USn_CS pin is disabled
1 The USn_CS pin is enabled
1 TXPEN 0 RW TX Pin Enable
When set, the TX/MOSI pin of the USART is enabled
Value Description
0 The U(S)n_TX (MOSI) pin is disabled
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Bit Name Reset Access Description
1 The U(S)n_TX (MOSI) pin is enabled
0 RXPEN 0 RW RX Pin Enable
When set, the RX/MISO pin of the USART is enabled.
Value Description
0 The U(S)n_RX (MISO) pin is disabled
1 The U(S)n_RX (MISO) pin is enabled
17.5.23 USARTn_INPUT - USART Input Register
Offset Bit Position
0x058
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
16
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
Reset
0
0x0
Access
RW
RW
Name
RXPRS
RXPRSSEL
Bit Name Reset Access Description
31:5 Reserved To ensure compatibility with future devices, always write bits to 0. More information in 2.1 Conven-
tions.
4 RXPRS 0 RW PRS RX Enable
When set, the PRS channel selected as input to RX.
3:0 RXPRSSEL 0x0 RW RX PRS Channel Select
Select PRS channel as input to RX.
Value Mode Description
0 PRSCH0 PRS Channel 0 selected
1 PRSCH1 PRS Channel 1 selected
2 PRSCH2 PRS Channel 2 selected
3 PRSCH3 PRS Channel 3 selected
4 PRSCH4 PRS Channel 4 selected
5 PRSCH5 PRS Channel 5 selected
6 PRSCH6 PRS Channel 6 selected
7 PRSCH7 PRS Channel 7 selected
8 PRSCH8 PRS Channel 8 selected
9 PRSCH9 PRS Channel 9 selected
10 PRSCH10 PRS Channel 10 selected
11 PRSCH11 PRS Channel 11 selected
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17.5.24 USARTn_I2SCTRL - I2S Control Register
Offset Bit Position
0x05C
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
16
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
Reset
0x0
0
0
0
0
0
Access
RW
RW
RW
RW
RW
RW
Name
FORMAT
DELAY
DMASPLIT
JUSTIFY
MONO
EN
Bit Name Reset Access Description
31:11 Reserved To ensure compatibility with future devices, always write bits to 0. More information in 2.1 Conven-
tions.
10:8 FORMAT 0x0 RW I2S Word Format
Configure the data-width used internally for I2S data
Value Mode Description
0 W32D32 32-bit word, 32-bit data
1 W32D24M 32-bit word, 32-bit data with 8 lsb masked
2 W32D24 32-bit word, 24-bit data
3 W32D16 32-bit word, 16-bit data
4 W32D8 32-bit word, 8-bit data
5 W16D16 16-bit word, 16-bit data
6 W16D8 16-bit word, 8-bit data
7 W8D8 8-bit word, 8-bit data
7:5 Reserved To ensure compatibility with future devices, always write bits to 0. More information in 2.1 Conven-
tions.
4 DELAY 0 RW Delay on I2S data
Set to add a one-cycle delay between a transition on the word-clock and the start of the I2S word. Should be set for stand-
ard I2S format
3 DMASPLIT 0 RW Separate DMA Request For Left/Right Data
When set DMA requests for right-channel data are put on the TXBLRIGHT and RXDATAVRIGHT DMA requests.
2 JUSTIFY 0 RW Justification of I2S Data
Determines whether the I2S data is left or right justified
Value Mode Description
0 LEFT Data is left-justified
1 RIGHT Data is right-justified
1 MONO 0 RW Stero or Mono
Switch between stereo and mono mode. Set for mono
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Bit Name Reset Access Description
0 EN 0 RW Enable I2S Mode
Set the U(S)ART in I2S mode.
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18. UART - Universal Asynchronous Receiver/ Transmitter
43210
Device
UART
RX
TX
DMA
controller
RAM
Quick Facts
What?
The UART is capable of high-speed asynchronous
serial communication
Why?
Serial communication is frequently used in embed-
ded systems and the UART allows efficient commu-
nication with a wide range of external devices.
How?
The UART has a wide selection of operating modes,
frame formats and baud rates. The multi-processor
mode allows the UART to remain idle when not ad-
dressed. Triple buffering and DMA support makes
high datarates possible with minimal CPU interven-
tion and it is possible to transmit and receive large
frames while the MCU remains in EM1.
18.1 Introduction
The Universal Asynchronous serial Receiver and Transmitter (UART) is a very flexible serial I/O module. It supports full- and half-du-
plex asynchronous UART communication.
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18.2 Features
• Full duplex and half duplex
• Separate TX / RX enable
• Separate receive / transmit 2-level buffers, with additional separate shift registers
• Programmable baud rate, generated as an fractional division from the peripheral clock (HFPERCLK)
• Max bit-rate
• UART standard mode, peripheral clock rate / 16
• UART FAST mode, peripheral clock rate / 8
• Asynchronous mode supports
• Majority vote baud-reception
• False start-bit detection
• Break generation/detection
• Multi-processor mode
• Configurable number of data bits, 4-16 (plus the parity bit, if enabled)
• HW parity bit generation and check
• Configurable number of stop bits in asynchronous mode: 0.5, 1, 1.5, 2
• HW collision detection
• Multi-processor mode
• Separate interrupt vectors for receive and transmit interrupts
• Loopback mode
• Half duplex communication
• Communication debugging
• PRS can trigger transmissions
• Full DMA support
• PRS RX input
18.3 Functional Description
The UART is functionally equivalent to the USART with the exceptions defined in the following table. The register map and register
descriptions are equal to those of the USART. See the USART chapter for detailed information on the operation of the UART.
Table 18.1. UART Limitations
Feature Limitation
Synchronous operation Not available. SYNC, CSMA, SMSDELAY, SSSEARLY, CSINV, CPOL and CPHA in
USARTn_CTRL, and MASTEREN in USARTn_STATUS are always 0.
Transmission direction Always LSB first. MSBF in USARTn_CTRL is always 0.
Chip-select Not available. AUTOCS in USARTn_CTRL is always 0.
SmartCard mode Not available. SCMODE in USARTn_CTRL is always 0.
Frame size Limited to 8-9 databits. Other configurations of DATABITS in USARTn_FRAME are not
possible.
IrDA Not available. IREN in USARTn_IRCTRL is always 0.
18.4 Register Description
The register description of the UART is equivalent to the register description of the USART except the limitations mentioned in Table
18.1 UART Limitations on page 638. See the USART chapter for complete information.
18.5 Register Map
The register map of the UART is equivalent to the register map of the USART. See the USART chapter for complete information.
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19. LEUART - Low Energy Universal Asynchronous Receiver/Transmitter
43210
LEUART
RX
TX
DMA
controller
RAM
Quick Facts
What?
The LEUART provides full UART communication us-
ing a low frequency 32.768 kHz clock, and has spe-
cial features for communication without CPU inter-
vention.
Why?
It allows UART communication to be performed in
low energy modes, using only a few μA during active
communication and only 150 nA when waiting for in-
coming data.
How?
A low frequency clock signal allows communication
with less energy. Using DMA, the LEUART can
transmit and receive data with minimal CPU inter-
vention. Special UART-frames can be configured to
help control the data flow, further automating data
transmission.
19.1 Introduction
The unique LEUARTTM, the Low Energy UART, is a UART that allows two-way UART communication on a strict power budget. Only a
32.768 kHz clock is needed to allow UART communication at baud rates up to 9600.
Even when the EFM is in low energy mode EM2 (with most core functionality turned off), the LEUART can wait for an incoming UART
frame while having an extremely low energy consumption. When a UART frame is completely received, the CPU can quickly be woken
up. Alternatively, multiple frames can be transferred via the Direct Memory Access (DMA) module into RAM memory before waking up
the CPU.
Received data can optionally be blocked until a configurable start frame is detected. A signal frame can be configured to generate an
interrupt to indicate e.g. the end of a data transmission. The start frame and signal frame can be used in combination for instance to
handle higher level communication protocols.
Similarly, data can be transmitted in EM2 either on a frame-by-frame basis with data from the CPU or through use of the DMA.
The LEUART includes all necessary hardware support to make asynchronous serial communication possible with minimum of software
intervention and energy consumption.
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19.2 Features
• Low energy asynchronous serial communications
• Full/half duplex communication
• Separate TX / RX enable
• Separate double buffered transmit buffer and receive buffer
• Programmable baud rate, generated as a fractional division of the LFBCLK
• Supports baud rates from 300 baud/s to 9600 baud/s
• Can use a high frequency clock source for even higher baud rates
• Configurable number of data bits: 8 or 9 (plus parity bit, if enabled)
• Configurable parity: off, even or odd
• HW parity bit generation and check
• Configurable number of stop bits, 1 or 2
• Capable of sleep-mode wake-up on received frame
• Either wake-up on any received byte or
• Wake up only on specified start and signal frames
• Supports transmission and reception in EM0, EM1 and EM2 with
• Full DMA support
• Specified start-byte can start reception automatically
• IrDA modulator (pulse generator, pulse extender)
• Multi-processor mode
• Loopback mode
• Half duplex communication
• Communication debugging
• PRS RX input
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w.
19.3 Functional Description
An overview of the LEUART module is shown in the following figure.
TX Buffer
TX Shift Register
Signal frame interrupt
RX Buffer
RX Shift Register
UART Control
and status
Peripheral Bus
TX Baud rate
generator
RX Baud rate
generator
Start frame
(STARTFRAME)
RX Wakeup
SYNC
=
Pulse
extend
Pulse
gen
Signal frame
(SIGFRAME)
=Start frame interrupt
!RXBLOCK
PRS Input
LEUn_RX
LEUn_TX
Figure 19.1. LEUART Overview
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19.3.1 Frame Format
The frame format used by the LEUART consists of a set of data bits in addition to bits for synchronization and optionally a parity bit for
error checking. A frame starts with one start-bit (S), where the line is driven low for one bit-period. This signals the start of a frame, and
is used for synchronization. Following the start bit are 8 or 9 data bits and an optional parity bit. The data is transmitted with the least
significant bit first. Finally, a number of stop-bits, where the line is driven high, end the frame. The frame format is shown in the follow-
ing figure.
S 0 1 2 34 5 6 7 [8] [P] Stop
Start or idleStop or idle
Frame
Figure 19.2. LEUART Asynchronous Frame Format
The number of data bits in a frame is set by DATABITS in LEUARTn_CTRL, and the number of stop-bits is set by STOPBITS in
LEUARTn_CTRL. Whether or not a parity bit should be included, and whether it should be even or odd is defined by PARITY in
LEUARTn_CTRL. For communication to be possible, all parties of an asynchronous transfer must agree on the frame format being
used.
The frame format used by the LEUART can be inverted by setting INV in LEUARTn_CTRL. This affects the entire frame, resulting in a
low idle state, a high start-bit, inverted data and parity bits, and low stop-bits. INV should only be changed while the receiver is disabled.
19.3.1.1 Parity Bit Calculation and Handling
Hardware automatically inserts parity bits into outgoing frames and checks the parity bits of incoming frames. The possible parity
modes are defined in Table 19.1 LEUART Parity Bit on page 642. When even parity is chosen, a parity bit is inserted to make the
number of high bits (data + parity) even. If odd parity is chosen, the parity bit makes the total number of high bits odd. When parity bits
are disabled, which is the default configuration, the parity bit is omitted.
Table 19.1. LEUART Parity Bit
PARITY [1:0] Description
00 No parity (default)
01 Reserved
10 Even parity
11 Odd parity
See 19.3.5.4 Parity Error for more information on parity bit handling.
19.3.2 Clock Source
The LEUART clock source is selected by the LFB bit field the CMU_LFCLKSEL register. The clock is prescaled by the LEUARTn bit-
field in the CMU_LFBPRESC0 register and enabled by the LEUARTn bit in the CMU_LFBCLKEN0.
To use this module, the LE interface clock must be enabled in CMU_HFCORECLKEN0, in addition to the module clock.
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19.3.3 Clock Generation
The LEUART clock defines the transmission and reception data rate. The clock generator employs a fractional clock divider to allow
baud rates that are not attainable by integral division of the 32.768 kHz clock that drives the LEUART.
The clock divider used in the LEUART is a 12-bit value, with a 7-bit integral part and a 5-bit fractional part. The baud rate of the
LEUART is given by :
br =
fLEUARTn
1 + LEUARTn_CLKDIV
256
where fLEUARTn is the clock frequency supplied to the LEUART. The value of LEUARTn_CLKDIV thus defines the baud rate of the
LEUART. The integral part of the divider is right-aligned in the upper 24 bits of LEUARTn_CLKDIV and the fractional part is left-aligned
in the lower 8 bits. The divider is thus a 256th of LEUARTn_CLKDIV as seen in the equation.
LEUARTn_CLKDIV = 256 ×
fLEUARTn
brDESIRED – 1
The following table lists a set of desired baud rates and the closest baud rates reachable by the LEUART with a 32.768 kHz clock
source. It also shows the average baud rate error.
Table 19.2. LEUART Baud Rates
Desired baud rate
[baud/s]
LEUARTn_CLKDIV LEUARTn_CLKDIV/256 Actual baud rate
[baud/s]
Error [%]
300 27704 108.21875 300.0217 0.01
600 13728 53.625 599.8719 -0.02
1200 6736 26.3125 1199.744 -0.02
2400 3240 12.65625 2399.487 -0.02
4800 1488 5.8125 4809.982 0.21
9600 616 2.40625 9619.963 0.21
19.3.4 Data Transmission
Data transmission is initiated by writing data to the transmit buffer using one of the methods described in 19.3.4.1 Transmit Buffer Oper-
ation. When the transmission shift register is empty and ready for new data, a frame from the transmit buffer is loaded into the shift
register, and if the transmitter is enabled, transmission begins. When the frame has been transmitted, a new frame is loaded into the
shift register if available, and transmission continues. If the transmit buffer is empty, the transmitter goes to an idle state, waiting for a
new frame to become available. Transmission is enabled through the command register LEUARTn_CMD by setting TXEN, and disa-
bled by setting TXDIS. When the transmitter is disabled using TXDIS, any ongoing transmission is aborted, and any frame currently
being transmitted is discarded. When disabled, the TX output goes to an idle state, which by default is a high value. Whether or not the
transmitter is enabled at a given time can be read from TXENS in LEUARTn_STATUS. After a transmission, when there is no more
data in the shift register or transmit buffer, the TXC flag in LEUARTn_STATUS and the TXC interrupt flag in LEUARTn_IF are set, sig-
naling that the transmitter is idle. The TXC status flag is cleared when a new byte becomes available for transmission, but the TXC
interrupt flag must be cleared by software.
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i
\|H|H|l\l\
fl
19.3.4.1 Transmit Buffer Operation
A frame can be loaded into the transmit buffer by writing to LEUARTn_TXDATA or LEUARTn_TXDATAX. Using LEUARTn_TXDATA
allows 8 bits to be written to the buffer. If 9 bit frames are used, the 9th bit will in that case be set to the value of BIT8DV in
LEUARTn_CTRL. To set the 9th bit directly and/or use transmission control, LEUARTn_TXDATAX must be used. When writing data to
the transmit buffer using LEUARTn_TXDATAX, the 9th bit written to LEUARTn_TXDATAX overrides the value in BIT8DV, and alone
defines the 9th bit that is transmitted if 9-bit frames are used.
If a write is attempted to the transmit buffer when it is not empty, the TXOF interrupt flag in LEUARTn_IF is set, indicating the overflow.
The data already in the buffer is in that case preserved, and no data is written.
In addition to the interrupt flag TXC in LEUARTn_IF and the status flag TXC in LEUARTn_STATUS which are set when the transmitter
becomes idle, TXBL in LEUARTn_STATUS and the TXBL interrupt flag in LEUARTn_IF are used to indicate the level of the transmit
buffer. Whenever the transmit buffer becomes empty, these flags are set high. Both the TXBL status flag and the TXBL interrupt flag
are cleared automatically when data is written to the transmit buffer.
The transmit buffer, including the TX shift register can be cleared by setting command bit CLEARTX in LEUARTn_CMD. This will pre-
vent the LEUART from transmitting the data in the buffer and shift register, and will make them available for new data. Any frame cur-
rently being transmitted will not be aborted. Transmission of this frame will be completed. An overview of the operation of the transmit-
ter is shown in the following figure.
TXENS
d0-d8 control d0 d2 d4 d6 d8d7d5d3d1 control
TXDATA
TXDATAX
BIT8DV 0
LEUn_TX Transmit shift register
Transmit buffer
Figure 19.3. LEUART Transmitter Overview
19.3.4.2 Frame Transmission Control
The transmission control bits, which can be written using LEUARTn_TXDATAX, affect the transmission of the written frame. The follow-
ing options are available:
• Generate break: By setting WBREAK, the output will be held low during the first stop-bit period to generate a framing error. A receiv-
er that supports break detection detects this state, allowing it to be used e.g. for framing of larger data packets. The line is driven
high for one baud period before the next frame is transmitted so the next start condition can be identified correctly by the recipient.
Continuous breaks lasting longer than an UART frame are thus not supported by the LEUART. GPIO can be used for this. Note that
when AUTOTRI in LEUARTn_CTRL is used, the transmitter is not tristated before the high-bit after the break has been transmitted.
• Disable transmitter after transmission: If TXDISAT is set, the transmitter is disabled after the frame has been fully transmitted.
• Enable receiver after transmission: If RXENAT is set, the receiver is enabled after the frame has been fully transmitted. It is enabled
in time to detect a start-bit directly after the last stop-bit has been transmitted.
The transmission control bits in the LEUART cannot tristate the transmitter. This is performed automatically by hardware however, if
AUTOTRI in LEUARTn_CTRL is set. See 19.3.7 Half Duplex Communication for more information on half duplex operation.
19.3.4.3 Jitter in Transmitted Data
Internally the LEUART module uses only the positive edges of the 32.768 kHz clock (LFBCLK) for transmission and reception. Trans-
mitted data will thus have jitter equal to the difference between the optimal data set-up location and the closest positive edge on the
32.768 kHz clock. The jitter in on the location data is set up by the transmitter will thus be no more than half a clock period according to
the optimal set-up location. The jitter in the period of a single baud output by the transmitter will never be more than one clock period.
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19.3.5 Data Reception
Data reception is enabled by setting RXEN in LEUARTn_CMD. When the receiver is enabled, it actively samples the input looking for a
transition from high to low indicating the start baud of a new frame. When a start baud is found, reception of the new frame begins if the
receive shift register is empty and ready for new data. When the frame has been received, it is pushed into the receive buffer, making
the shift register ready for another frame of data, and the receiver starts looking for another start baud. If the receive buffer is full, the
received frame remains in the shift register until more space in the receive buffer is available.
If an incoming frame is detected while both the receive buffer and the receive shift register are full, the data in the receive shift register
is overwritten, and the RXOF interrupt flag in LEUARTn_IF is set to indicate the buffer overflow.
The receiver can be disabled by setting the command bit RXDIS in LEUARTn_CMD. Any frame currently being received when the re-
ceiver is disabled is discarded. Whether or not the receiver is enabled at a given time can be read out from RXENS in LEUARTn_STA-
TUS.
19.3.5.1 Receive Buffer Operation
When data becomes available in the receive buffer, the RXDATAV flag in LEUARTn_STATUS and the RXDATAV interrupt flag in
LEUARTn_IF are set. Both the RXDATAV status flag and the RXDATAV interrupt flag are cleared by hardware when data is no longer
available, i.e. when data has been read out of the buffer.
Data can be read from receive buffer using either LEUARTn_RXDATA or LEUARTn_RXDATAX. LEUARTn_RXDATA gives access to
the 8 least significant bits of the received frame, while LEUARTn_RXDATAX must be used to get access to the 9th, most significant bit.
The latter register also contains status information regarding the frame.
When a frame is read from the receive buffer using LEUARTn_RXDATA or LEUARTn_RXDATAX, the frame is removed from the buf-
fer, making room for a new one. If an attempt is done to read more frames from the buffer than what is available, the RXUF interrupt
flag in LEUARTn_IF is set to signal the underflow, and the data read from the buffer is undefined.
Frames can also be read from the receive buffer without removing the data by using LEUARTn_RXDATAXP, which gives access to the
frame in the buffer including control bits. Data read from this register when the receive buffer is empty is undefined. No underflow inter-
rupt is generated by a read using LEUARTn_RXDATAXP, i.e. the RXUF interrupt flag is never set as a result of reading from
LEUARTn_RXDATAXP.
An overview of the operation of the receiver is shown in the following figure.
RXENS !RXBLOCK
d0-d8 status d0 d2 d4 d6 d8d7d5d3d1 status
RXDATA
RXDATAX
(RXDATAXP)
LEUn_RX
Receive buffer
Receive shift register
Figure 19.4. LEUART Receiver Overview
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19.3.5.2 Blocking Incoming Data
When using hardware frame recognition, as detailed in 19.3.5.6 Programmable Start Frame, 19.3.5.7 Programmable Signal Frame, and
19.3.5.8 Multi-Processor Mode, it is necessary to be able to let the receiver sample incoming frames without passing the frames to
software by loading them into the receive buffer. This is accomplished by blocking incoming data.
Incoming data is blocked as long as RXBLOCK in LEUARTn_STATUS is set. When blocked, frames received by the receiver will not be
loaded into the receive buffer, and software is not notified by the RXDATAV bit in LEUARTn_STATUS or the RXDATAV interrupt flag in
LEUARTn_IF at their arrival. For data to be loaded into the receive buffer, RXBLOCK must be cleared in the instant a frame is fully
received by the receiver. RXBLOCK is set by setting RXBLOCKEN in LEUARTn_CMD and disabled by setting RXBLOCKDIS also in
LEUARTn_CMD. There are two exceptions where data is loaded into the receive buffer even when RXBLOCK is set. The first is when
an address frame is received when in operating in multi-processor mode as shown in 19.3.5.8 Multi-Processor Mode. The other case is
when receiving a start-frame when SFUBRX in LEUARTn_CTRL is set; see 19.3.5.6 Programmable Start Frame.
Frames received containing framing or parity errors will not result in the FERR and PERR interrupt flags in LEUARTn_IF being set while
RXBLOCK is set. Hardware recognition is not applied to these erroneous frames, and they are silently discarded.
Note: If a frame is received while RXBLOCK in LEUARTn_STATUS is cleared, but stays in the receive shift register because the re-
ceive buffer is full, the received frame will be loaded into the receive buffer when space becomes available even if RXBLOCK is set at
that time. The overflow interrupt flag RXOF in LEUARTn_IF will be set if a frame in the receive shift register, waiting to be loaded into
the receive buffer is overwritten by an incoming frame even though RXBLOCK is set.
19.3.5.3 Data Sampling
The receiver samples each incoming baud as close as possible to the middle of the baud-period. Except for the start-bit, only a single
sample is taken of each of the incoming bauds.
The length of a baud-period is given by 1 + LEUARTn_CLKDIV/256, as a number of 32.768 kHz clock periods. Let the clock cycle
where a start-bit is first detected be given the index 0. The optimal sampling point for each baud in the UART frame is then given by the
following equation:
Sopt(n) = n×
(
1 + LEUARTn_CLKDIV
256
)
+CLKDIV
512
where n is the bit-index.
Since samples are only done on the positive edges of the 32.768 kHz clock, the actual samples are performed on the closest positive
edge, i.e. the edge given by the following equation:
S(n) = floor
(
n×
(
1 + LEUARTn_CLKDIV
256
)
+LEUARTn_CLKDIV
512
)
The sampling location will thus have jitter according to difference between Sopt and S. The start-bit is found at n=0, then follows the
data bits, any parity bit, and the stop bits.
If the value of the start-bit is found to be high, then the start-bit is discarded, and the receiver waits for a new start-bit.
19.3.5.4 Parity Error
When the parity bit is enabled, a parity check is automatically performed on incoming frames. When a parity error is detected in a
frame, the data parity error bit PERR in the frame is set, as well as the interrupt flag PERR. Frames with parity errors are loaded into
the receive buffer like regular frames.
PERR can be accessed by reading the frame from the receive buffer using the LEUARTn_RXDATAX register.
19.3.5.5 Framing Error and Break Detection
A framing error is the result of a received frame where the stop bit was sampled to a value of 0. This can be the result of noise and
baud rate errors, but can also be the result of a break generated by the transmitter on purpose.
When a framing error is detected, the framing error bit FERR in the received frame is set. The interrupt flag FERR in LEUARTn_IF is
also set. Frames with framing errors are loaded into the receive buffer like regular frames.
FERR can be accessed by reading the frame from the receive buffer using the LEUARTn_RXDATAX or LEUARTn_RXDATAXP regis-
ters.
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19.3.5.6 Programmable Start Frame
The LEUART can be configured to start receiving data when a special start frame is detected on the input. This can be useful when
operating in low energy modes, allowing other devices to gain the attention of the LEUART by transmitting a given frame.
When SFUBRX in LEUARTn_CTRL is set, an incoming frame matching the frame defined in LEUARTn_STARTFRAME will result in
RXBLOCK in LEUARTn_STATUS being cleared. This can be used to enable reception when a specified start frame is detected. If the
receiver is enabled and blocked, i.e. RXENS and RXBLOCK in LEUARTn_STATUS are set, the receiver will receive all incoming
frames, but unless an incoming frame is a start frame it will be discarded and not loaded into the receive buffer. When a start frame is
detected, the block is cleared, and frames received from that point, including the start frame, are loaded into the receive buffer.
An incoming start frame results in the STARTF interrupt flag in LEUARTn_IF being set, regardless of the value of SFUBRX in
LEUARTn_CTRL. This allows an interrupt to be made when the start frame is detected.
When 8 data-bit frame formats are used, only the 8 least significant bits of LEUARTn_STARTFRAME are compared to incoming
frames. The full length of LEUARTn_STARTFRAME is used when operating with frames consisting of 9 data bits.
Note: The receiver must be enabled for start frames to be detected. In addition, a start frame with a parity error or framing error is not
detected as a start frame.
19.3.5.7 Programmable Signal Frame
As well as the configurable start frame, a special signal frame can be specified. When a frame matching the frame defined in
LEUARTn_SIGFRAME is detected by the receiver, the SIGF interrupt flag in LEUARTn_IF is set. As for start frame detection, the re-
ceiver must be enabled for signal frames to be detected.
One use of the programmable signal frame is to signal the end of a multi-frame message transmitted to the LEUART. An interrupt will
then be triggered when the packet has been completely received, allowing software to process it. Used in conjunction with the program-
mable start frame and DMA, this makes it possible for the LEUART to automatically begin the reception of a packet on a specified start
frame, load the entire packet into memory, and give an interrupt when reception of a packet has completed. The device can thus wait
for data packets in EM2, and only be woken up when a packet has been completely received.
A signal frame with a parity error or framing error is not detected as a signal frame.
19.3.5.8 Multi-Processor Mode
To simplify communication between multiple processors and maintain compatibility with the USART, the LEUART supports a multi-pro-
cessor mode. In this mode the 9th data bit in each frame is used to indicate whether the content of the remaining 8 bits is data or an
address.
When multi-processor mode is enabled, an incoming 9-bit frame with the 9th bit equal to the value of MPAB in LEUARTn_CTRL is
identified as an address frame. When an address frame is detected, the MPAF interrupt flag in LEUARTn_IF is set, and the address
frame is loaded into the receive register. This happens regardless of the value of RXBLOCK in LEUARTn_STATUS.
Multi-processor mode is enabled by setting MPM in LEUARTn_CTRL. The mode can be used in buses with multiple slaves, allowing
the slaves to be addressed using the special address frames. An addressed slave, which was previously blocking reception using
RXBLOCK, would then unblock reception, receive a message from the bus master, and then block reception again, waiting for the next
message. See the USART for a more detailed example.
Note: The programmable start frame functionality can be used for automatic address matching, enabling reception on a correctly con-
figured incoming frame.
An address frame with a parity error or a framing error is not detected as an address frame.
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DE
19.3.6 Loopback
The LEUART receiver samples LEUn_RX by default, and the transmitter drives LEUn_TX by default. This is not the only configuration
however. When LOOPBK in LEUARTn_CTRL is set, the receiver is connected to the LEUn_TX pin as shown in the following figure.
This is useful for debugging, as the LEUART can receive the data it transmits, but it is also used to allow the LEUART to read and write
to the same pin, which is required for some half duplex communication modes. In this mode, the LEUn_TX pin must be enabled as an
output in the GPIO.
Device
LEUART
Device
LEUART
RX LEUn_RX
TX LEUn_TX
LOOPBK = 0
RX LEUn_RX
TX LEUn_TX
LOOPBK = 1
Figure 19.5. LEUART Local Loopback
19.3.7 Half Duplex Communication
When doing full duplex communication, two data links are provided, making it possible for data to be sent and received at the same
time. In half duplex mode, data is only sent in one direction at a time. There are several possible half duplex setups, as described in the
following sections.
19.3.7.1 Single Data-Link
In this setup, the LEUART both receives and transmits data on the same pin. This is enabled by setting LOOPBK in LEUARTn_CTRL,
which connects the receiver to the transmitter output. Because they are both connected to the same line, it is important that the
LEUART transmitter does not drive the line when receiving data, as this would corrupt the data on the line.
When communicating over a single data-link, the transmitter must thus be tristated whenever not transmitting data. If AUTOTRI in
LEUARTn_CTRL is set, the LEUART automatically tristates LEUn_TX whenever the transmitter is inactive. It is then the responsibility
of the software protocol to make sure the transmitter is not transmitting data whenever incoming data is expected.
The transmitter can also be tristated from software by configuring the GPIO pin as an input and disabling the LEUART output on
LEUn_TX.
Note: Another way to tristate the transmitter is to enable wired-and or wired-or mode in GPIO. For wired-and mode, outputting a 1 will
be the same as tristating the output, and for wired-or mode, outputting a 0 will be the same as tristating the output. This can only be
done on buses with a pull-up or pull-down resistor respectively.
19.3.7.2 Single Data-Link with External Driver
Some communication schemes, such as RS-485 rely on an external driver. Here, the driver has an extra input which enables it, and
instead of Tristating the transmitter when receiving data, the external driver must be disabled. The USART has hardware support for
automatically turning the driver on and off. When using the LEUART in such a setup, the driver must be controlled by a GPIO. The
following figure shows an example configuration using an external driver.
Device
LEUART
RX
TX
GPIO
Figure 19.6. LEUART Half Duplex Communication with External Driver
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19.3.7.3 Two Data-Links
Some limited devices only support half duplex communication even though two data links are available. In this case software is respon-
sible for making sure data is not transmitted when incoming data is expected.
19.3.8 Transmission Delay
By configuring TXDELAY in LEUARTn_CTRL, the transmitter can be forced to wait a number of bit periods from it is ready to transmit
data, to it actually transmits the data. This delay is only applied to the first frame transmitted after the transmitter has been idle. When
transmitting frames back-to-back the delay is not introduced between the transmitted frames.
This is useful on half duplex buses, because the receiver always returns received frames to software during the first stop-bit. The bus
may still be driven for up to 3 baud periods, depending on the current frame format. Using the transmission delay, a transmission can
be started when a frame is received, and it is possible to make sure that the transmitter does not begin driving the output before the
frame on the bus is completely transmitted.
19.3.9 PRS RX Input
The LEUART can be configured to receive data directly from the PRS channel by setting RX_PRS in LEUARTn_INPUT. The PRS
channel used can be selected using RX_PRS_SEL in LEUARTn_INPUT.
19.3.10 DMA Support
The LEUART has full DMA support in energy modes EM0 – EM2. The DMA controller can write to the transmit buffer using the regis-
ters LEUARTn_TXDATA and LEUARTn_TXDATAX, and it can read from receive buffer using the registers LEUARTn_RXDATA and
LEUARTn_RXDATAX. This enables single byte transfers and 9 bit data + control/status bits transfers both to and from the LEUART.
The DMA will start up the HFRCO and run from this when it is waken by the LEUART in EM2. The HFRCO is disabled once the trans-
action is done.
A request for the DMA controller to read from the receive buffer can come from one of the following sources:
• Receive buffer full
A write request can come from one of the following sources:
• Transmit buffer and shift register empty. No data to send.
• Transmit buffer empty
In some cases, it may be sensible to temporarily stop DMA access to the LEUART when a parity or framing error has occurred. This is
enabled by setting ERRSDMA in LEUARTn_CTRL. When this bit is set, the DMA controller will not get requests from the receive buffer
if a framing error or parity error is detected in the received byte. The ERRSDMA bit applies only to the RX DMA.
When operating in EM2, the DMA controller must be powered up in order to perform the transfer. This is automatically performed for
read operations if RXDMAWU in LEUARTn_CTRL is set and for write operations if TXDMAWU in LEUARTn_CTRL is set. To make
sure the DMA controller still transfers bits to and from the LEUART in low energy modes, these bits must thus be configured according-
ly.
Note: When RXDMAWU or TXDMAWU is set, the system will not be able to go to EM2/EM3 before all related LEUART DMA requests
have been processed. This means that if RXDMAWU is set and the LEUART receives a frame, the system will not be able to go to
EM2/EM3 before the frame has been read from the LEUART. In order for the system to go to EM2 during the last byte transmission,
LEUART_CTRL_TXDMAWU must be cleared in the DMA interrupt service routine. This is because TXBL will be high during that last
byte transfer.
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19.3.11 Pulse Generator / Pulse Extender
The LEUART has an optional pulse generator for the transmitter output, and a pulse extender on the receiver input. These are enabled
by setting PULSEEN in LEUARTn_PULSECTRL, and with INV in LEUARTn_CTRL set, they will change the output/input format of the
LEUART from NRZ to RZI as shown in the following figure.
S 0 1 2 34 5 6 7 PStop
IdleIdle
NRZ
RZI
Figure 19.7. LEUART - NRZ vs. RZI
If PULSEEN in LEUARTn_PULSECTRL is set while INV in LEUARTn_CTRL is cleared, the output waveform will like RZI shown in the
previous figure, only inverted.
The width of the pulses from the pulse generator can be configured using PULSEW in LEUARTn_PULSECTRL. The generated pulse
width is PULSEW + 1 cycles of the 32.768 kHz clock, which makes pulse width from 31.25 μs to 500 μs possible.
Since the incoming signal is only sampled on positive clock edges, the width of the incoming pulses must be at least two 32.768 kHz
clock periods wide for reliable detection by the LEUART receiver. They must also be shorter than half a UART baud period.
At 2400 baud/s or lower, the pulse generator is able to generate RZI pulses compatible with the IrDA physical layer specification. The
external IrDA device must generate pulses of sufficient length for successful two-way communication.
19.3.11.1 Interrupts
The interrupts generated by the LEUART are combined into one interrupt vector. If LEUART interrupts are enabled, an interrupt will be
made if one or more of the interrupt flags in LEUARTn_IF and their corresponding bits in LEUART_IEN are set.
19.3.12 Register Access
Since this module is a Low Energy Peripheral, and runs off a clock which is asynchronous to the HFCORECLK, special considerations
must be taken when accessing registers. Please refer to 5.2.4 Access to Low Energy Peripherals (Asynchronous Registers) for a de-
scription on how to perform register accesses to Low Energy Peripherals.
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19.4 Register Map
The offset register address is relative to the registers base address.
Offset Name Type Description
0x000 LEUARTn_CTRL RW Control Register
0x004 LEUARTn_CMD W1 Command Register
0x008 LEUARTn_STATUS RStatus Register
0x00C LEUARTn_CLKDIV RW Clock Control Register
0x010 LEUARTn_STARTFRAME RW Start Frame Register
0x014 LEUARTn_SIGFRAME RW Signal Frame Register
0x018 LEUARTn_RXDATAX R(a) Receive Buffer Data Extended Register
0x01C LEUARTn_RXDATA R(a) Receive Buffer Data Register
0x020 LEUARTn_RXDATAXP RReceive Buffer Data Extended Peek Register
0x024 LEUARTn_TXDATAX WTransmit Buffer Data Extended Register
0x028 LEUARTn_TXDATA WTransmit Buffer Data Register
0x02C LEUARTn_IF RInterrupt Flag Register
0x030 LEUARTn_IFS W1 Interrupt Flag Set Register
0x034 LEUARTn_IFC (R)W1 Interrupt Flag Clear Register
0x038 LEUARTn_IEN RW Interrupt Enable Register
0x03C LEUARTn_PULSECTRL RW Pulse Control Register
0x040 LEUARTn_FREEZE RW Freeze Register
0x044 LEUARTn_SYNCBUSY RSynchronization Busy Register
0x054 LEUARTn_ROUTE RW I/O Routing Register
0x0AC LEUARTn_INPUT RW LEUART Input Register
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19.5 Register Description
19.5.1 LEUARTn_CTRL - Control Register (Async Reg)
For more information about Asynchronous Registers, see 5.2.4 Access to Low Energy Peripherals (Asynchronous Registers).
Offset Bit Position
0x000
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
16
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
Reset
0x0
0
0
0
0
0
0
0
0
0
0
0x0
0
0
Access
RW
RW
RW
RW
RW
RW
RW
RW
RW
RW
RW
RW
RW
RW
Name
TXDELAY
TXDMAWU
RXDMAWU
BIT8DV
MPAB
MPM
SFUBRX
LOOPBK
ERRSDMA
INV
STOPBITS
PARITY
DATABITS
AUTOTRI
Bit Name Reset Access Description
31:16 Reserved To ensure compatibility with future devices, always write bits to 0. More information in 2.1 Conven-
tions.
15:14 TXDELAY 0x0 RW TX Delay Transmission
Configurable delay before new transfers. Frames sent back-to-back are not delayed.
Value Mode Description
0 NONE Frames are transmitted immediately
1 SINGLE Transmission of new frames are delayed by a single baud period
2 DOUBLE Transmission of new frames are delayed by two baud periods
3 TRIPLE Transmission of new frames are delayed by three baud periods
13 TXDMAWU 0 RW TX DMA Wakeup
Set to wake the DMA controller up when in EM2 and space is available in the transmit buffer.
Value Description
0 While in EM2, the DMA controller will not get requests about space be-
ing available in the transmit buffer
1 DMA is available in EM2 for the request about space available in the
transmit buffer
12 RXDMAWU 0 RW RX DMA Wakeup
Set to wake the DMA controller up when in EM2 and data is available in the receive buffer.
Value Description
0 While in EM2, the DMA controller will not get requests about data being
available in the receive buffer
1 DMA is available in EM2 for the request about data in the receive buf-
fer
11 BIT8DV 0 RW Bit 8 Default Value
When 9-bit frames are transmitted, the default value of the 9th bit is given by BIT8DV. If TXDATA is used to write a frame,
then the value of BIT8DV is assigned to the 9th bit of the outgoing frame. If a frame is written with TXDATAX however, the
default value is overridden by the written value.
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Bit Name Reset Access Description
10 MPAB 0 RW Multi-Processor Address-Bit
Defines the value of the multi-processor address bit. An incoming frame with its 9th bit equal to the value of this bit marks
the frame as a multi-processor address frame.
9 MPM 0 RW Multi-Processor Mode
Set to enable multi-processor mode.
Value Description
0 The 9th bit of incoming frames have no special function
1 An incoming frame with the 9th bit equal to MPAB will be loaded into
the receive buffer regardless of RXBLOCK and will result in the MPAB
interrupt flag being set
8 SFUBRX 0 RW Start-Frame UnBlock RX
Clears RXBLOCK when the start-frame is found in the incoming data. The start-frame is loaded into the receive buffer.
Value Description
0 Detected start-frames have no effect on RXBLOCK
1 When a start-frame is detected, RXBLOCK is cleared and the start-
frame is loaded into the receive buffer
7 LOOPBK 0 RW Loopback Enable
Set to connect receiver to LEUn_TX instead of LEUn_RX.
Value Description
0 The receiver is connected to and receives data from LEUn_RX
1 The receiver is connected to and receives data from LEUn_TX
6 ERRSDMA 0 RW Clear RX DMA On Error
When set,RX DMA requests will be cleared on framing and parity errors.
Value Description
0 Framing and parity errors have no effect on DMA requests from the
LEUART
1 RX DMA requests from the LEUART are disabled if a framing error or
parity error occurs.
5 INV 0 RW Invert Input And Output
Set to invert the output on LEUn_TX and input on LEUn_RX.
Value Description
0 A high value on the input/output is 1, and a low value is 0.
1 A low value on the input/output is 1, and a high value is 0.
4 STOPBITS 0 RW Stop-Bit Mode
Determines the number of stop-bits used. Only used when transmitting data. The receiver only verifies that one stop bit is
present.
Value Mode Description
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Bit Name Reset Access Description
0 ONE One stop-bit is transmitted with every frame
1 TWO Two stop-bits are transmitted with every frame
3:2 PARITY 0x0 RW Parity-Bit Mode
Determines whether parity bits are enabled, and whether even or odd parity should be used.
Value Mode Description
0 NONE Parity bits are not used
2 EVEN Even parity are used. Parity bits are automatically generated and
checked by hardware.
3 ODD Odd parity is used. Parity bits are automatically generated and checked
by hardware.
1 DATABITS 0 RW Data-Bit Mode
This register sets the number of data bits.
Value Mode Description
0 EIGHT Each frame contains 8 data bits
1 NINE Each frame contains 9 data bits
0 AUTOTRI 0 RW Automatic Transmitter Tristate
When set, LEUn_TX is tristated whenever the transmitter is inactive.
Value Description
0 LEUn_TX is held high when the transmitter is inactive. INV inverts the
inactive state.
1 LEUn_TX is tristated when the transmitter is inactive
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19.5.2 LEUARTn_CMD - Command Register (Async Reg)
For more information about Asynchronous Registers, see 5.2.4 Access to Low Energy Peripherals (Asynchronous Registers).
Offset Bit Position
0x004
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
16
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
Reset
0
0
0
0
0
0
0
0
Access
W1
W1
W1
W1
W1
W1
W1
W1
Name
CLEARRX
CLEARTX
RXBLOCKDIS
RXBLOCKEN
TXDIS
TXEN
RXDIS
RXEN
Bit Name Reset Access Description
31:8 Reserved To ensure compatibility with future devices, always write bits to 0. More information in 2.1 Conven-
tions.
7 CLEARRX 0 W1 Clear RX
Set to clear receive buffer and the RX shift register.
6 CLEARTX 0 W1 Clear TX
Set to clear transmit buffer and the TX shift register.
5 RXBLOCKDIS 0 W1 Receiver Block Disable
Set to clear RXBLOCK, resulting in all incoming frames being loaded into the receive buffer.
4 RXBLOCKEN 0 W1 Receiver Block Enable
Set to set RXBLOCK, resulting in all incoming frames being discarded.
3 TXDIS 0 W1 Transmitter Disable
Set to disable transmission.
2 TXEN 0 W1 Transmitter Enable
Set to enable data transmission.
1 RXDIS 0 W1 Receiver Disable
Set to disable data reception. If a frame is under reception when the receiver is disabled, the incoming frame is discarded.
0 RXEN 0 W1 Receiver Enable
Set to activate data reception on LEUn_RX.
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19.5.3 LEUARTn_STATUS - Status Register
Offset Bit Position
0x008
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
16
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
Reset
0
1
0
0
0
0
Access
R
R
R
R
R
R
Name
RXDATAV
TXBL
TXC
RXBLOCK
TXENS
RXENS
Bit Name Reset Access Description
31:6 Reserved To ensure compatibility with future devices, always write bits to 0. More information in 2.1 Conven-
tions.
5 RXDATAV 0 R RX Data Valid
Set when data is available in the receive buffer. Cleared when the receive buffer is empty.
4 TXBL 1 R TX Buffer Level
Indicates the level of the transmit buffer. Set when the transmit buffer is empty, and cleared when it is full.
3 TXC 0 R TX Complete
Set when a transmission has completed and no more data is available in the transmit buffer. Cleared when a new transmis-
sion starts.
2 RXBLOCK 0 R Block Incoming Data
When set, the receiver discards incoming frames. An incoming frame will not be loaded into the receive buffer if this bit is
set at the instant the frame has been completely received.
1 TXENS 0 R Transmitter Enable Status
Set when the transmitter is enabled.
0 RXENS 0 R Receiver Enable Status
Set when the receiver is enabled. The receiver must be enabled for start frames, signal frames, and multi-processor ad-
dress bit detection.
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19.5.4 LEUARTn_CLKDIV - Clock Control Register (Async Reg)
For more information about Asynchronous Registers, see 5.2.4 Access to Low Energy Peripherals (Asynchronous Registers).
Offset Bit Position
0x00C
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
16
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
Reset
0x000
Access
RW
Name
DIV
Bit Name Reset Access Description
31:15 Reserved To ensure compatibility with future devices, always write bits to 0. More information in 2.1 Conven-
tions.
14:3 DIV 0x000 RW Fractional Clock Divider
Specifies the fractional clock divider for the LEUART.
2:0 Reserved To ensure compatibility with future devices, always write bits to 0. More information in 2.1 Conven-
tions.
19.5.5 LEUARTn_STARTFRAME - Start Frame Register (Async Reg)
For more information about Asynchronous Registers, see 5.2.4 Access to Low Energy Peripherals (Asynchronous Registers).
Offset Bit Position
0x010
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
16
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
Reset
0x000
Access
RW
Name
STARTFRAME
Bit Name Reset Access Description
31:9 Reserved To ensure compatibility with future devices, always write bits to 0. More information in 2.1 Conven-
tions.
8:0 STARTFRAME 0x000 RW Start Frame
When a frame matching STARTFRAME is detected by the receiver, STARTF interrupt flag is set, and if SFUBRX is set,
RXBLOCK is cleared. The start-frame is be loaded into the RX buffer.
EFM32WG Reference Manual
LEUART - Low Energy Universal Asynchronous Receiver/Transmitter
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19.5.6 LEUARTn_SIGFRAME - Signal Frame Register (Async Reg)
For more information about Asynchronous Registers, see 5.2.4 Access to Low Energy Peripherals (Asynchronous Registers).
Offset Bit Position
0x014
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
16
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
Reset
0x000
Access
RW
Name
SIGFRAME
Bit Name Reset Access Description
31:9 Reserved To ensure compatibility with future devices, always write bits to 0. More information in 2.1 Conven-
tions.
8:0 SIGFRAME 0x000 RW Signal Frame
When a frame matching SIGFRAME is detected by the receiver, SIGF interrupt flag is set.
19.5.7 LEUARTn_RXDATAX - Receive Buffer Data Extended Register (Actionable Reads)
Offset Bit Position
0x018
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
16
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
Reset
0
0
0x000
Access
R
R
R
Name
FERR
PERR
RXDATA
Bit Name Reset Access Description
31:16 Reserved To ensure compatibility with future devices, always write bits to 0. More information in 2.1 Conven-
tions.
15 FERR 0 R Receive Data Framing Error
Set if data in buffer has a framing error. Can be the result of a break condition.
14 PERR 0 R Receive Data Parity Error
Set if data in buffer has a parity error.
13:9 Reserved To ensure compatibility with future devices, always write bits to 0. More information in 2.1 Conven-
tions.
8:0 RXDATA 0x000 R RX Data
Use this register to access data read from the LEUART. Buffer is cleared on read access.
EFM32WG Reference Manual
LEUART - Low Energy Universal Asynchronous Receiver/Transmitter
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19.5.8 LEUARTn_RXDATA - Receive Buffer Data Register (Actionable Reads)
Offset Bit Position
0x01C
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
16
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
Reset
0x00
Access
R
Name
RXDATA
Bit Name Reset Access Description
31:8 Reserved To ensure compatibility with future devices, always write bits to 0. More information in 2.1 Conven-
tions.
7:0 RXDATA 0x00 R RX Data
Use this register to access data read from LEUART. Buffer is cleared on read access. Only the 8 LSB can be read using
this register.
19.5.9 LEUARTn_RXDATAXP - Receive Buffer Data Extended Peek Register
Offset Bit Position
0x020
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
16
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
Reset
0
0
0x000
Access
R
R
R
Name
FERRP
PERRP
RXDATAP
Bit Name Reset Access Description
31:16 Reserved To ensure compatibility with future devices, always write bits to 0. More information in 2.1 Conven-
tions.
15 FERRP 0 R Receive Data Framing Error Peek
Set if data in buffer has a framing error. Can be the result of a break condition.
14 PERRP 0 R Receive Data Parity Error Peek
Set if data in buffer has a parity error.
13:9 Reserved To ensure compatibility with future devices, always write bits to 0. More information in 2.1 Conven-
tions.
8:0 RXDATAP 0x000 R RX Data Peek
Use this register to access data read from the LEUART.
EFM32WG Reference Manual
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19.5.10 LEUARTn_TXDATAX - Transmit Buffer Data Extended Register (Async Reg)
For more information about Asynchronous Registers, see 5.2.4 Access to Low Energy Peripherals (Asynchronous Registers).
Offset Bit Position
0x024
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
16
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
Reset
0
0
0
0x000
Access
W
W
W
W
Name
RXENAT
TXDISAT
TXBREAK
TXDATA
Bit Name Reset Access Description
31:16 Reserved To ensure compatibility with future devices, always write bits to 0. More information in 2.1 Conven-
tions.
15 RXENAT 0 W Enable RX After Transmission
Set to enable reception after transmission.
Value Description
0 -
1 The receiver is enabled, setting RXENS after the frame has been
transmitted
14 TXDISAT 0 W Disable TX After Transmission
Set to disable transmitter directly after transmission has competed.
Value Description
0 -
1 The transmitter is disabled, clearing TXENS after the frame has been
transmitted
13 TXBREAK 0 W Transmit Data As Break
Set to send data as a break. Recipient will see a framing error or a break condition depending on its configuration and the
value of TXDATA.
Value Description
0 The specified number of stop-bits are transmitted
1 Instead of the ordinary stop-bits, 0 is transmitted to generate a break. A
single stop-bit is generated after the break to allow the receiver to de-
tect the start of the next frame
12:9 Reserved To ensure compatibility with future devices, always write bits to 0. More information in 2.1 Conven-
tions.
8:0 TXDATA 0x000 W TX Data
Use this register to write data to the LEUART. If the transmitter is enabled, a transfer will be initiated at the first opportunity.
EFM32WG Reference Manual
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19.5.11 LEUARTn_TXDATA - Transmit Buffer Data Register (Async Reg)
For more information about Asynchronous Registers, see 5.2.4 Access to Low Energy Peripherals (Asynchronous Registers).
Offset Bit Position
0x028
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
16
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
Reset
0x00
Access
W
Name
TXDATA
Bit Name Reset Access Description
31:8 Reserved To ensure compatibility with future devices, always write bits to 0. More information in 2.1 Conven-
tions.
7:0 TXDATA 0x00 W TX Data
This frame will be added to the transmit buffer. Only 8 LSB can be written using this register. 9th bit and control bits will be
cleared.
EFM32WG Reference Manual
LEUART - Low Energy Universal Asynchronous Receiver/Transmitter
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19.5.12 LEUARTn_IF - Interrupt Flag Register
Offset Bit Position
0x02C
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
16
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
Reset
0
0
0
0
0
0
0
0
0
1
0
Access
R
R
R
R
R
R
R
R
R
R
R
Name
SIGF
STARTF
MPAF
FERR
PERR
TXOF
RXUF
RXOF
RXDATAV
TXBL
TXC
Bit Name Reset Access Description
31:11 Reserved To ensure compatibility with future devices, always write bits to 0. More information in 2.1 Conven-
tions.
10 SIGF 0 R Signal Frame Interrupt Flag
Set when a signal frame is detected.
9 STARTF 0 R Start Frame Interrupt Flag
Set when a start frame is detected.
8 MPAF 0 R Multi-Processor Address Frame Interrupt Flag
Set when a multi-processor address frame is detected.
7 FERR 0 R Framing Error Interrupt Flag
Set when a frame with a framing error is received while RXBLOCK is cleared.
6 PERR 0 R Parity Error Interrupt Flag
Set when a frame with a parity error is received while RXBLOCK is cleared.
5 TXOF 0 R TX Overflow Interrupt Flag
Set when a write is done to the transmit buffer while it is full. The data already in the transmit buffer is preserved.
4 RXUF 0 R RX Underflow Interrupt Flag
Set when trying to read from the receive buffer when it is empty.
3 RXOF 0 R RX Overflow Interrupt Flag
Set when data is incoming while the receive shift register is full. The data previously in shift register is overwritten by the
new data.
2 RXDATAV 0 R RX Data Valid Interrupt Flag
Set when data becomes available in the receive buffer.
1 TXBL 1 R TX Buffer Level Interrupt Flag
Set when space becomes available in the transmit buffer for a new frame.
0 TXC 0 R TX Complete Interrupt Flag
Set after a transmission when both the TX buffer and shift register are empty.
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19.5.13 LEUARTn_IFS - Interrupt Flag Set Register
Offset Bit Position
0x030
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
16
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
Reset
0
0
0
0
0
0
0
0
0
Access
W1
W1
W1
W1
W1
W1
W1
W1
W1
Name
SIGF
STARTF
MPAF
FERR
PERR
TXOF
RXUF
RXOF
TXC
Bit Name Reset Access Description
31:11 Reserved To ensure compatibility with future devices, always write bits to 0. More information in 2.1 Conven-
tions.
10 SIGF 0 W1 Set Signal Frame Interrupt Flag
Write to 1 to set the SIGF interrupt flag.
9 STARTF 0 W1 Set Start Frame Interrupt Flag
Write to 1 to set the STARTF interrupt flag.
8 MPAF 0 W1 Set Multi-Processor Address Frame Interrupt Flag
Write to 1 to set the MPAF interrupt flag.
7 FERR 0 W1 Set Framing Error Interrupt Flag
Write to 1 to set the FERR interrupt flag.
6 PERR 0 W1 Set Parity Error Interrupt Flag
Write to 1 to set the PERR interrupt flag.
5 TXOF 0 W1 Set TX Overflow Interrupt Flag
Write to 1 to set the TXOF interrupt flag.
4 RXUF 0 W1 Set RX Underflow Interrupt Flag
Write to 1 to set the RXUF interrupt flag.
3 RXOF 0 W1 Set RX Overflow Interrupt Flag
Write to 1 to set the RXOF interrupt flag.
2:1 Reserved To ensure compatibility with future devices, always write bits to 0. More information in 2.1 Conven-
tions.
0 TXC 0 W1 Set TX Complete Interrupt Flag
Write to 1 to set the TXC interrupt flag.
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19.5.14 LEUARTn_IFC - Interrupt Flag Clear Register
Offset Bit Position
0x034
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
16
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
Reset
0
0
0
0
0
0
0
0
0
Access
(R)W1
(R)W1
(R)W1
(R)W1
(R)W1
(R)W1
(R)W1
(R)W1
(R)W1
Name
SIGF
STARTF
MPAF
FERR
PERR
TXOF
RXUF
RXOF
TXC
Bit Name Reset Access Description
31:11 Reserved To ensure compatibility with future devices, always write bits to 0. More information in 2.1 Conven-
tions.
10 SIGF 0 (R)W1 Clear Signal-Frame Interrupt Flag
Write to 1 to clear the SIGF interrupt flag.
9 STARTF 0 (R)W1 Clear Start-Frame Interrupt Flag
Write to 1 to clear the STARTF interrupt flag.
8 MPAF 0 (R)W1 Clear Multi-Processor Address Frame Interrupt Flag
Write to 1 to clear the MPAF interrupt flag.
7 FERR 0 (R)W1 Clear Framing Error Interrupt Flag
Write to 1 to clear the FERR interrupt flag.
6 PERR 0 (R)W1 Clear Parity Error Interrupt Flag
Write to 1 to clear the PERR interrupt flag.
5 TXOF 0 (R)W1 Clear TX Overflow Interrupt Flag
Write to 1 to clear the TXOF interrupt flag.
4 RXUF 0 (R)W1 Clear RX Underflow Interrupt Flag
Write to 1 to clear the RXUF interrupt flag.
3 RXOF 0 (R)W1 Clear RX Overflow Interrupt Flag
Write to 1 to clear the RXOF interrupt flag.
2:1 Reserved To ensure compatibility with future devices, always write bits to 0. More information in 2.1 Conven-
tions.
0 TXC 0 (R)W1 Clear TX Complete Interrupt Flag
Write to 1 to clear the TXC interrupt flag.
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19.5.15 LEUARTn_IEN - Interrupt Enable Register
Offset Bit Position
0x038
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
16
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
Reset
0
0
0
0
0
0
0
0
0
0
0
Access
RW
RW
RW
RW
RW
RW
RW
RW
RW
RW
RW
Name
SIGF
STARTF
MPAF
FERR
PERR
TXOF
RXUF
RXOF
RXDATAV
TXBL
TXC
Bit Name Reset Access Description
31:11 Reserved To ensure compatibility with future devices, always write bits to 0. More information in 2.1 Conven-
tions.
10 SIGF 0 RW Signal Frame Interrupt Enable
Enable interrupt on signal frame.
9 STARTF 0 RW Start Frame Interrupt Enable
Enable interrupt on start frame.
8 MPAF 0 RW Multi-Processor Address Frame Interrupt Enable
Enable interrupt on multi-processor address frame.
7 FERR 0 RW Framing Error Interrupt Enable
Enable interrupt on framing error.
6 PERR 0 RW Parity Error Interrupt Enable
Enable interrupt on parity error.
5 TXOF 0 RW TX Overflow Interrupt Enable
Enable interrupt on TX overflow.
4 RXUF 0 RW RX Underflow Interrupt Enable
Enable interrupt on RX underflow.
3 RXOF 0 RW RX Overflow Interrupt Enable
Enable interrupt on RX overflow.
2 RXDATAV 0 RW RX Data Valid Interrupt Enable
Enable interrupt on RX data.
1 TXBL 0 RW TX Buffer Level Interrupt Enable
Enable interrupt on TX buffer level.
0 TXC 0 RW TX Complete Interrupt Enable
Enable interrupt on TX complete.
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19.5.16 LEUARTn_PULSECTRL - Pulse Control Register (Async Reg)
For more information about Asynchronous Registers, see 5.2.4 Access to Low Energy Peripherals (Asynchronous Registers).
Offset Bit Position
0x03C
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
16
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
Reset
0
0
0x0
Access
RW
RW
RW
Name
PULSEFILT
PULSEEN
PULSEW
Bit Name Reset Access Description
31:6 Reserved To ensure compatibility with future devices, always write bits to 0. More information in 2.1 Conven-
tions.
5 PULSEFILT 0 RW Pulse Filter
Enable a one-cycle pulse filter for pulse extender
Value Description
0 Filter is disabled. Pulses must be at least 2 cycles long for reliable de-
tection.
1 Filter is enabled. Pulses must be at least 3 cycles long for reliable de-
tection.
4 PULSEEN 0 RW Pulse Generator/Extender Enable
Filter LEUART output through pulse generator and the LEUART input through the pulse extender.
3:0 PULSEW 0x0 RW Pulse Width
Configure the pulse width of the pulse generator as a number of 32.768 kHz clock cycles.
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19.5.17 LEUARTn_FREEZE - Freeze Register
Offset Bit Position
0x040
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
16
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
Reset
0
Access
RW
Name
REGFREEZE
Bit Name Reset Access Description
31:1 Reserved To ensure compatibility with future devices, always write bits to 0. More information in 2.1 Conven-
tions.
0 REGFREEZE 0 RW Register Update Freeze
When set, the update of the LEUART is postponed until this bit is cleared. Use this bit to update several registers simulta-
neously.
Value Mode Description
0 UPDATE Each write access to a LEUART register is updated into the Low Fre-
quency domain as soon as possible.
1 FREEZE The LEUART is not updated with the new written value.
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19.5.18 LEUARTn_SYNCBUSY - Synchronization Busy Register
Offset Bit Position
0x044
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
16
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
Reset
0
0
0
0
0
0
0
0
Access
R
R
R
R
R
R
R
R
Name
PULSECTRL
TXDATA
TXDATAX
SIGFRAME
STARTFRAME
CLKDIV
CMD
CTRL
Bit Name Reset Access Description
31:8 Reserved To ensure compatibility with future devices, always write bits to 0. More information in 2.1 Conven-
tions.
7 PULSECTRL 0 R PULSECTRL Register Busy
Set when the value written to PULSECTRL is being synchronized.
6 TXDATA 0 R TXDATA Register Busy
Set when the value written to TXDATA is being synchronized.
5 TXDATAX 0 R TXDATAX Register Busy
Set when the value written to TXDATAX is being synchronized.
4 SIGFRAME 0 R SIGFRAME Register Busy
Set when the value written to SIGFRAME is being synchronized.
3 STARTFRAME 0 R STARTFRAME Register Busy
Set when the value written to STARTFRAME is being synchronized.
2 CLKDIV 0 R CLKDIV Register Busy
Set when the value written to CLKDIV is being synchronized.
1 CMD 0 R CMD Register Busy
Set when the value written to CMD is being synchronized.
0 CTRL 0 R CTRL Register Busy
Set when the value written to CTRL is being synchronized.
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19.5.19 LEUARTn_ROUTE - I/O Routing Register
Offset Bit Position
0x054
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
16
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
Reset
0x0
0
0
Access
RW
RW
RW
Name
LOCATION
TXPEN
RXPEN
Bit Name Reset Access Description
31:11 Reserved To ensure compatibility with future devices, always write bits to 0. More information in 2.1 Conven-
tions.
10:8 LOCATION 0x0 RW I/O Location
Decides the location of the LEUART I/O pins.
Value Mode Description
0 LOC0 Location 0
1 LOC1 Location 1
2 LOC2 Location 2
3 LOC3 Location 3
4 LOC4 Location 4
7:2 Reserved To ensure compatibility with future devices, always write bits to 0. More information in 2.1 Conven-
tions.
1 TXPEN 0 RW TX Pin Enable
When set, the TX pin of the LEUART is enabled.
Value Description
0 The LEUn_TX pin is disabled
1 The LEUn_TX pin is enabled
0 RXPEN 0 RW RX Pin Enable
When set, the RX pin of the LEUART is enabled.
Value Description
0 The LEUn_RX pin is disabled
1 The LEUn_RX pin is enabled
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19.5.20 LEUARTn_INPUT - LEUART Input Register
Offset Bit Position
0x0AC
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
16
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
Reset
0
0x0
Access
RW
RW
Name
RXPRS
RXPRSSEL
Bit Name Reset Access Description
31:5 Reserved To ensure compatibility with future devices, always write bits to 0. More information in 2.1 Conven-
tions.
4 RXPRS 0 RW PRS RX Enable
When set, the PRS channel selected as input to RX.
3:0 RXPRSSEL 0x0 RW RX PRS Channel Select
Select PRS channel as input to RX.
Value Mode Description
0 PRSCH0 PRS Channel 0 selected
1 PRSCH1 PRS Channel 1 selected
2 PRSCH2 PRS Channel 2 selected
3 PRSCH3 PRS Channel 3 selected
4 PRSCH4 PRS Channel 4 selected
5 PRSCH5 PRS Channel 5 selected
6 PRSCH6 PRS Channel 6 selected
7 PRSCH7 PRS Channel 7 selected
8 PRSCH8 PRS Channel 8 selected
9 PRSCH9 PRS Channel 9 selected
10 PRSCH10 PRS Channel 10 selected
11 PRSCH11 PRS Channel 11 selected
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20. TIMER - Timer/Counter
43210
TIMER
Counter
Capture values
Compare values
=
PRS
ADC
Output compare/PWM
Input capture
USART
Clock
Quick Facts
What?
The TIMER (Timer/Counter) keeps track of timing
and counts events, generates output waveforms and
triggers timed actions in other peripherals.
Why?
Most applications have activities that need to be
timed accurately with as little CPU intervention and
energy consumption as possible.
How?
The flexible 16-bit TIMER can be configured to pro-
vide PWM waveforms with optional dead-time inser-
tion for e.g. motor control, or work as a frequency
generator. The Timer can also count events and
control other peripherals through the PRS, which off-
loads the CPU and reduce energy consumption.
20.1 Introduction
The 16-bit general purpose Timer has 3 compare/capture channels for input capture and compare/Pulse- Width Modulation (PWM) out-
put. TIMER0 also includes a Dead-Time Insertion module suitable for motor control applications.
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TIMER - Timer/Counter
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20.2 Features
• 16-bit auto reload up/down counter
• Dedicated 16-bit reload register which serves as counter maximum
• 3 Compare/Capture channels
• Individual configurable as either input capture or output compare/PWM
• Multiple Counter modes
• Count up
• Count down
• Count up/down
• Quadrature Decoder
• Direction and count from external pins
• 2x Count Mode
• Counter control from PRS or external pin
• Start
• Stop
• Reload and start
• Inter-Timer connection
• Allows 32-bit counter mode
• Start/stop synchronization between several Timers
• Input Capture
• Period measurement
• Pulse width measurement
• Two capture registers for each capture channel
• Capture on either positive or negative edge
• Capture on both edges
• Optional digital noise filtering on capture inputs
• Output Compare
• Compare output toggle/pulse on compare match
• Immediate update of compare registers
• PWM
• Up-count PWM
• Up/down-count PWM
• Predictable initial PWM output state (configured by SW)
• Buffered compare register to ensure glitch-free update of compare values
• Clock sources
• HFPERCLKTIMERn
• 10-bit Prescaler
• External pin
• Peripheral Reflex System
• Debug mode
• Configurable to either run or stop when processor is stopped (break)
• Interrupts, PRS output and/or DMA request
• Underflow
• Overflow
• Compare/Capture event
• Dead-Time Insertion Unit (TIMER0 only)
• Complementary PWM outputs with programmable dead-time
• Dead-time is specified independently for rising and falling edge
• 10-bit prescaler
• 6-bit time value
• Outputs have configurable polarity
• Outputs can be set inactive individually by software.
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• Configurable action on fault
• Set outputs inactive
• Clear output
• Tristate output
• Individual fault sources
• One or two PRS signals
• Debugger
• Support for automatic restart
• Core lockup
• Configuration lock
20.3 Functional Description
An overview of the TIMER module is shown in the following figure. The Timer module consists of a 16 bit up/down counter with 3 Com-
pare/Capture channels connected to pins TIMn_CC0, TIMn_CC1, and TIMn_CC2.
==
Compare and
PWM config
Compare and
PWM config
Compare and
PWM config
=
TnCCR0[15:0
]
TnCCR1[15:0
]
Compare Match x
TIMERn_TOPTIMERn_CNT
TIMERn_CCx
Input Capture
Update
condition
Note: For simplicity, all
TIMERn_CCx registers are
grouped together in the figure,
but they all have individual Input
Capture Registers
=
= 0
CNTCLK
Counter
control
Overflow
Underflow
TIMn_CC0
Input logic Edge
detect
Quadrature
Decoder
Input logic
Input logic
Edge
detect
Edge
detect
PRS inputs
PRS inputs
PRS inputs
Prescaler
HFPERCLKTIMERn
TIMn_CC1
TIMn_CC2
TIMn_CC0
TIMn_CC1
TIMn_CC2
Figure 20.1. TIMER Block Overview
20.3.1 Counter Modes
The Timer consists of a counter that can be configured to the following modes:
1. Up-count: Counter counts up until it reaches the value in TIMERn_TOP, where it is reset to 0 before counting up again.
2. Down-count: The counter starts at the value in TIMERn_TOP and counts down. When it reaches 0, it is reloaded with the value in
TIMERn_TOP.
3. Up/Down-count: The counter starts at 0 and counts up. When it reaches the value in TIMERn_TOP, it counts down until it reaches
0 and starts counting up again.
4. Quadrature Decoder: Two input channels where one determines the count direction, while the other pin triggers a clock event.
In addition, to the TIMER modes listed above, the TIMER also supports a 2x Count Mode. In this mode the counter increments/decre-
ments by 2. The 2x Count Mode intended use is to generate 2x PWM frequency when the Compare/Capture channel is put in PWM
mode. The 2x Count Mode can be enabled by setting the X2CNT bitfield in the TIMERn_CTRL register.
The counter value can be read or written by software at any time by accessing the CNT field in TIMERn_CNT.
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20.3.1.1 Events
Overflow is set when the counter value shifts from TIMERn_TOP to the next value when counting up. In up-count mode the next value
is 0. In up/down-count mode, the next value is TIMERn_TOP-1.
Underflow is set when the counter value shifts from 0 to the next value when counting down. In downcount mode, the next value is
TIMERn_TOP. In up/down-count mode the next value is 1.
Update event is set on overflow in up-count mode and on underflow in down-count or up/down count mode. This event is used to time
updates of buffered values.
20.3.1.2 Operation
The following figure shows the hardware Timer/Counter control. Software can start or stop the counter by writing a 1 to the START or
STOP bits in TIMERn_CMD. The counter value (CNT in TIMERn_CNT) can always be written by software to any 16-bit value.
It is also possible to control the counter through either an external pin or PRS input. This is done through the input logic for the Com-
pare/Capture Channel 0. The Timer/Counter allows individual actions (start, stop, reload) to be taken for rising and falling input edges.
This is configured in the RISEA and FALLA fields in TIMERn_CTRL. The reload value is 0 in up-count and up/down-count mode and
TOP in downcount mode.
The RUNNING bit in TIMERn_STATUS indicates if the Timer is running or not. If the SYNC bit in TIMERn_CTRL is set, the Timer is
started/stopped/reloaded (external pin or PRS) when any of the other timers are started/stopped/reloaded.
The DIR bit in TIMERn_STATUS indicates the counting direction of the Timer at any given time. The counter value can be read or
written by software through the CNT field in TIMERn_CNT. In Up/Down- Count mode the count direction will be set to up if the CNT
value is written by software.
Counter
(Controlled by TIMERn_CTRL)
Compare/Capture channel 0
(Controlled by TIMERn_CC0_CTRL)
TIMn_CC0
PRS channels
PRSSEL
INSEL
Filter
FILT
ICEDGE
Input
Capture 0
Counter
RISEA FALLA
Start
Stop
Reload&Start
Figure 20.2. TIMER Hardware Timer/Counter Control
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20.3.1.3 Clock Source
The counter can be clocked from several sources, which are all synchronized with the peripheral clock (HFPERCLK). See the following
figure.
Counter
(Controlled by TIMERn_CTRL)
Compare/Capture channel 1
(Controlled by TIMERn_CC1_CTRL)
TIMn_CC1
PRS channels
PRSSEL
INSEL
Filter
FILT
ICEDGE
HFPERCLKTIMERn
CLKSEL
Prescaler
PRESC
Input
Capture 1
Counter
Figure 20.3. TIMER Clock Selection
20.3.1.3.1 Peripheral Clock (HFPERCLK)
The peripheral clock (HFPERCLK) can be used as a source with a configurable prescale factor of 2^PRESC, where PRESC is an inte-
ger between 0 and 10, which is set in PRESC in TIMERn_CTRL. However, if 2x Count Mode is enabled and the Compare/Capture
channels are put in PWM mode, the CC output is updated on both clock edges so prescaling the peripheral clock will result in incorrect
result. The prescaler is stopped and reset when the timer is stopped.
20.3.1.3.2 Compare/Capture Channel 1 Input
The Timer can also be clocked by positive and/or negative edges on the Compare/Capture channel 1 input. This input can either come
from the TIMn_CC1 pin or one of the PRS channels. The input signal must not have a higher frequency than fHFPERCLK/3 when running
from a pin input or a PRS input with FILT enabled in TIMERn_CCx_CTRL. When running from PRS without FILT, the frequency can be
as high as fHFPERCLK. Note that when clocking the Timer from the same pulse that triggers a start (through RISEA/FALLA in
TIMERn_CTRL), the starting pulse will not update the Counter Value.
20.3.1.3.3 Underflow/Overflow from Neighboring Timer
All Timers are linked together (see the following figure), allowing timers to count on overflow/underflow from the lower numbered neigh-
bouring timers to form a 32-bit or 48-bit timer. Note that all timers must be set to same count direction and less significant timer(s) can
only be set to count up or down.
TIMER0
TIMER1TIMER2 Overflow Overflow
Underflow Underflow
Figure 20.4. TIMER Connections
20.3.1.4 One-Shot Mode
By default, the counter counts continuously until it is stopped. If the OSMEN bit is set in the TIMERn_CTRL register, however, the coun-
ter is disabled by hardware on the first update event. Note that when the counter is running with CC1 as clock source (0b01 in CLKSEL
in TIMERn_CTRL) and OSMEN is set, a CC1 capture event will not take place on the update event (CC1 rising edge) that stops the
Timer.
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20.3.1.5 Top Value Buffer
The TIMERn_TOP register can be altered either by writing it directly or by writing to the TIMER_TOPB (buffer) register. When writing to
the buffer register the TIMERn_TOPB register will be written to TIMERn_TOP on the next update event. Buffering ensures that the TOP
value is not set below the actual count value. The TOPBV flag in TIMERn_STATUS indicates whether the TIMERn_TOPB register con-
tains data that have not yet been written to the TIMERn_TOP register (see the following figure).
TOP
APB Write (TOPB) TOPB
Load APB
Load APB
TOPBV
Set
Clear
APB Write (TOP)
Update event
Load TOPB
APB Data
Figure 20.5. TIMER TOP Value Update Functionality
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20.3.1.6 Quadrature Decoder
Quadrature Decoding mode is used to track motion and determine both rotation direction and position. The Quadrature Decoder uses
two input channels that are 90 degrees out of phase (see the following figure).
Channel A
Channel B
Forward rotation (Channel A leads Channel B)
90°
Channel A
Channel B
Backward rotation (Channel B leads Channel A)
90°
Figure 20.6. TIMER Quadrature Encoded Inputs
In the Timer these inputs are tapped from the Compare/Capture channel 0 (Channel A) and 1 (Channel B) inputs before edge detec-
tion. The Timer/Counter then increments or decrements the counter, based on the phase relation between the two inputs. The Quadra-
ture Decoder Mode supports two channels, but if a third channel (Z-terminal) is available, this can be connected to an external interrupt
and trigger a counter reset from the interrupt service routine. By connecting a periodic signal from another timer as input capture on
Compare/Capture Channel 2, it is also possible to calculate speed and acceleration.
Counter
(Controlled by TIMERn_CTRL)
Compare/Capture channel 1
(Controlled by TIMERn_CC1_CTRL)
Compare/Capture channel 0
(Controlled by TIMERn_CC0_CTRL)
TIMn_CC0
PRS channels
PRSSEL
INSEL
Filter
FILT
ICEDGE
Quadrature
Decoder
TIMn_CC1
PRS channels
PRSSEL
INSEL
Filter
FILT
ICEDGE
Input
Capture 0
Input
Capture 1
Counter
Inc
Dec
QDM MODE
Ch B
Ch A
Figure 20.7. TIMER Quadrature Decoder Configuration
The Quadrature Decoder can be set in either X2 or X4 mode, which is configured in the QDM bit in TIMERn_CTRL. See the previous
figure.
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I—\ r? m m I—\
J—l
11x1oxgxsx7xex5141312
2131415X6X7X81911UX11 I:
20.3.1.6.1 X2 Decoding Mode
In X2 Decoding mode, the counter increments or decrements on every edge of Channel A, see the following figure and table.
Table 20.1. TIMER Counter Response in X2 Decoding Mode
Channel B Channel A
Rising Falling
0 Increment Decrement
1 Decrement Increment
Channel A
Channel B
CNT 3 4 5 6 7 834567 28
Figure 20.8. TIMER X2 Decoding Mode
20.3.1.6.2 X4 Decoding Mode
In X4 Decoding mode, the counter increments or decrements on every edge of Channel A and Channel B, see the following table and
figure.
Table 20.2. TIMER Counter Response in X4 Decoding Mode
Opposite Channel Channel A Channel B
Rising Falling Rising Falling
Channel A = 0 Decrement Increment
Channel A = 1 Increment Decrement
Channel B = 0 Increment Decrement
Channel B = 1 Decrement Increment
Channel A
Channel B
34567891011
3 4 5 6 7 8 9 10 11 2
2
CNT
Figure 20.9. TIMER X4 Decoding Mode
20.3.1.6.3 TIMER Rotational Position
To calculate a position, the following equation can be used.
pos° = (CNT / X× N) × 360°
where X = Encoding type and N = Number of pulses per revolution.
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20.3.2 Compare/Capture Channels
The Timer contains 3 Compare/Capture channels, which can be configured in the following modes:
1. Input Capture
2. Output Compare
3. PWM
20.3.2.1 Input Pin Logic
Each Compare/Capture channel can be configured as an input source for the Capture Unit or as external clock source for the Timer
(see the following figure). Compare/Capture channels 0 and 1 are the inputs for the Quadrature Decoder Mode. The input channel can
be filtered before it is used, which requires the input to remain stable for 5 cycles in a row before the input is propagated to the output.
TIMn_CCx
PRS channels
PRSSEL
INSEL
Filter
FILT
ICEDGE
Input
Capture x
Figure 20.10. TIMER Input Pin Logic
20.3.2.2 Compare/Capture Registers
The Compare/Capture channel registers are prefixed with TIMERn_CCx_, where the x stands for the channel number. Since the Com-
pare/Capture channels serve three functions (input capture, compare, PWM), the behavior of the Compare/Capture registers
(TIMERn_CCx_CCV) and buffer registers (TIMERn_CCx_CCVB) change depending on the mode the channel is set in.
20.3.2.2.1 Input Capture Mode
When running in Input Capture mode, TIMERn_CCx_CCV and TIMERn_CCx_CCVB form a FIFO buffer, and new capture values are
added on a capture event, see the following figure. The first capture can always be read from TIMERn_CCx_CCV, and reading this
address will load the next capture value into TIMERn_CCx_CCV from TIMERn_CCx_CCVB if it contains valid data. The CC value can
be read without altering the FIFO contents by reading TIMERn_CCx_CCVP. TIMERn_CCx_CCVB can also be read without altering the
FIFO contents. The ICV flag in TIMERn_STATUS indicates if there is a valid unread capture in TIMERn_CCx_CCV.
In case a capture is triggered while both CCV and CCVB contain unread capture values, the buffer overflow interrupt flag (ICBOF in
TIMERn_IF) will be set. New capture values will on overflow overwrite the value in TIMERn_CCx_CCVB.
Note: In input capture mode, the timer will only trigger interrupts when it is running
FIFO
CNT
CCV
CCVB
APB Data
Figure 20.11. TIMER Input Capture Buffer Functionality
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20.3.2.2.2 Compare and PWM Mode
When running in Output Compare or PWM mode, the value in TIMERn_CCx_CCV will be compared against the count value. In Com-
pare mode the output can be configured to toggle, clear or set on compare match, overflow and underflow through the CMOA, COFOA
and CUFOA fields in TIMERn_CCx_CTRL. TIMERn_CCx_CCV can be accessed directly or through the buffer register
TIMERn_CCx_CCVB, see the following figure. When writing to the buffer register, the value in TIMERn_CCx_CCVB will be written to
TIMERn_CCx_CCV on the next update event. This functionality ensures glitch free PWM outputs. The CCVBV flag in TIMERn_STA-
TUS indicates whether the TIMERn_CCx_CCVB register contains data that have not yet been written to the TIMERn_CCx_CCV regis-
ter. Note that when writing 0 to TIMERn_CCx_CCVB the CCV value is updated when the timer counts from 0 to 1. Thus, the compare
match for the next period will not happen until the timer reaches 0 again on the way down.
CCV
APB Write (CCB) CCVB
Load APB
Load APB
CCVBV
Set
Clear
APB Write (CC)
Update event
Load CCB
APB Data
Figure 20.12. TIMER Output Compare/PWM Buffer Functionality
20.3.2.3 Input Capture
In Input Capture Mode, the counter value (TIMERn_CNT) can be captured in the Compare/Capture Register (TIMERn_CCx_CCV), see
the following figure. In this mode, TIMERn_CCx_CCV is read-only. Together with the Compare/Capture Buffer Register
(TIMERn_CCx_CCVB) the TIMERn_CCx_CCV form a double-buffered capture registers allowing two subsequent capture events to
take place before a read-out is required. The CCPOL bits in TIMERn_STATUS indicate the polarity the edge that triggered the capture
in TIMERn_CCx_CCV.
TIMERn_CCx_CCV m
m
n
y
z
TIMERn_CNT
Input
Read TIMERn_CCx_CCVB
TIMERn_CCx_CCVB m y
prev. val
prev. val
Figure 20.13. TIMER Input Capture
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period on either a la
F
>
T
_H; ‘ —,|Z
—>|Z
4
20.3.2.3.1 Period/Pulse-Width Capture
Period and/or pulse-width capture can be achieved by setting the RISEA field in TIMERn_CTRL to Clear&Start, and select the wanted
input from either external pin or PRS, see the following figure. For period capture, the Compare/Capture Channel should then be set to
input capture on a rising edge of the same input signal. To capture a the width of a high pulse, the Compare/Capture Channel should
be set to capture on a falling edge of the input signal. To start the measuring period on either a falling edge or measure the low pulse-
width of a signal, opposite polarities should be chosen.
0
Input
CNT
Clear&Start
Input Capture (frequency capture)
Input Capture (pulse-width capture)
Figure 20.14. TIMER Period and/or Pulse Width Capture
20.3.2.4 Compare
Each Compare/Capture channel contains a comparator which outputs a compare match if the contents of TIMERn_CCx_CCV matches
the counter value, see the following figure. In compare mode, each compare channel can be configured to either set, clear or toggle the
output on an event (compare match, overflow or underflow). The output from each channel is represented as an alternative function on
the port it is connected to, which needs to be enabled for the CC outputs to propagate to the pins.
TnCCR0[15:0
]
TnCCR1[15:0
]
Underflow
Compare Match x
TIMERn_TOPTIMERn_CNT
TIMERn_CCx
Update
Condition
Note: For simplicity, all
TIMERn_CCx registers are
grouped together in the figure,
but they all have individual
Compare Register and logic
=
= 0
==TIMn_CC0
Compare and
PWM config
Compare and
PWM config
Compare and
PWM config
=
TIMn_CC1
TIMn_CC2
CNTCLK
Overflow
Figure 20.15. TIMER Block Diagram Showing Comparison Functionality
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Emmi
If occurring in the same cycle, match action will have priority over overflow or underflow action.
The input selected (through PRSSEL, INSEL and FILTSEL in TIMERn_CCx_CTRL) for the CC channel will also be sampled on com-
pare match and the result is found in the CCPOL bits in TIMERn_STATUS. It is also possible to configure the CCPOL to always track
the inputs by setting ATI in TIMERn_CTRL.
The COIST bit in TIMERn_CCx_CTRL is the initial state of the compare/PWM output. The COIST bit can also be used as an initial
value to the compare outputs on a reload-start when RSSCOIST is set in TIMERn_CTRL. Also the resulting output can be inverted by
setting OUTINV in TIMERn_CCx_CTRL. It is recommended to turn off the CC channel before configuring the output state to avoid any
pulses on the output. The CC channel can be turned off by setting MODE to OFF in TIMER_CCx_CTRL.
TIMn_CCx
COIST
OUTINV
Output
Compare/
PWM x 0
1
Figure 20.16. TIMER Output Logic
20.3.2.4.1 Frequency Generation (FRG)
Frequency generation (see the following figure) can be achieved in compare mode by:
• Setting the counter in up-count mode
• Enabling buffering of the TOP value.
• Setting the CC channels overflow action to toggle
0
TIMERn_TOP
TIMERn_CCx_CCV
Figure 20.17. TIMER Up-Count Frequency Generation
The output frequency is given by the following equation.
fFRG =
fHFPERCLK
2(PRESC+1)× (TOP + 1)× 2
20.3.2.5 Pulse-Width Modulation (PWM)
In PWM mode, TIMERn_CCx_CCV is buffered to avoid glitches in the output. The settings in the Compare Output Action configuration
bits are ignored in PWM mode and PWM generation is only supported for up-count and up/down-count mode.
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20.3.2.6 Up-Count (Single-Slope) PWM
If the counter is set to up-count and the Compare/Capture channel is put in PWM mode, single slope PWM output will be generated
(see the following figure). In up-count mode the PWM period is TOP +1 cycles and the PWM output will be high for a number of cycles
equal to TIMERn_CCx_CCV. This means that a constant high output is achieved by setting TIMER_CCx to TOP+1 or higher. The PWM
resolution (in bits) is then given by the following equation.
0
TIMERn_TOP
TIMERn_CCx_CCV
TIMn_CCx
Overflow
Compare match
Buffer update
Figure 20.18. TIMER Up-Count PWM Generation
RPWMup =log(TOP + 1)
log(2)
The PWM frequency is given by the following equation:
fPWMup/down =
fHFPERCLK
2PRESC × (TOP + 1)
The high duty cycle is given by the following equation:
DSup = CCVx
/
TOP
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WW
0x2x4x0x2x4x0 0x2x4x0x2x4x0
20.3.2.6.1 2x Count Mode
When the Timer is set in 2x mode, the TIMER will count up by two. This will in effect make any odd Top value be rounded down to the
closest even number. Similarly, any odd CC value will generate a match on the closest lower even value as shown in the figure below.
2 4 0 2 40
Clock
CC Out
02 4 0 2 40 0
Top = 5
CC = 1
Top = 5
CC = 2
Figure 20.19. TIMER CC Out in 2x Mode
The mode is enabled by setting the X2CNT field in TIMERn_CTRL register. The intended use of the 2x mode is to generate 2x PWM
frequency when the Compare/Capture channel is put in PWM mode. Since the PWM output is updated on both edges of the clock,
frequency prescaling will result in incorrect result in this mode. The PWM resolution (in bits) is then given by the following equation.
RPWM2xmode =log(TOP / 2 + 1)
log(2)
The PWM frequency is given by the following equation:
fPWM2xmode =2×
fHFPERCLK
floor(TOP / 2)+ 1
The high duty cycle is given by the following equation:
DS2xmode = CCVx
/
TOP
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20.3.2.7 Up/Down-Count (Dual-Slope) PWM
If the counter is set to up-down count and the Compare/Capture channel is put in PWM mode, dual slope PWM output will be generated
by the following figure. The resolution (in bits) is given by the following equation.
0
TIMERn_TOP
TIMERn_CCx_CCV
TIMn_CCx
Overflow
Compare match
Buffer update
Figure 20.20. TIMER Up/Down-Count PWM Generation
RPWMup/down =log(TOP + 1)
log(2)
The PWM frequency is given by the following equation:
fPWMup/down =
fHFPERCLK
2PRESC+1 × TOP
The high duty cycle is given by the following equation:
DSup = CCVx
/
TOP
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J_|_|_|_|_|_|_|_|_|_|_|_|_LJ_|_|_|_|_|_|_|_|_|_|_|_|_L
0X2X4X2XoX2X4 OXZX4X2XOXZX4
20.3.2.7.1 2x Count Mode
When the Timer is set in 2x mode, the TIMER will count up/down by two. This will in effect make any odd Top value be rounded down
to the closest even number. Similarly, any odd CC value will generate a match on the closest lower even value as shown in the follow-
ing figure.
2 4 2 0 20
Clock
CC Out
42 4 2 0 20 4
Top = 5
CC = 1
Top = 5
CC = 2
Figure 20.21. TIMER CC Out in 2x Mode
The mode is enabled by setting the X2CNT field in TIMERn_CTRL register. The intended use of the 2x mode is to generate 2x PWM
frequency when the Compare/Capture channel is put in PWM mode. Since the PWM output is updated on both edges of the clock,
frequency prescaling will result in incorrect result in this mode. The PWM resolution (in bits) is then given by the following equation.
RPWM2xmode =log(TOP / 2 + 1)
log(2)
The PWM frequency is given by the following equation:
fPWM2xmode =
fHFPERCLK
TOP
The high duty cycle is given by the following equation:
DS2xmode = CCVx
/
TOP
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44,
20.3.3 Dead-Time Insertion Unit (TIMER0 only)
The Dead-Time Insertion Unit aims to make control of BLDC motors safer and more efficient by introducing complementary PWM out-
puts with dead-time insertion and fault handling, see the following figure.
Dead time
insertion
Original PWM (TIM0_CCx_pre) Fault
handling
Primary output (TIM0_CCx)
Complementary output (TIM0_CDTIx)
Fault sources
Figure 20.22. TIMER Dead-Time Insertion Unit Overview
When used for motor control, the PWM outputs TIM0_CC0, TIM0_CC1 and TIM0_CC2 are often connected to the high-side transistors
of a triple half-bridge setup (UH, VH and WH), and the complementary outputs connected to the respective low-side transistors (UL, VL,
WL shown in the following figure). Transistors used in such a bridge often do not open/close instantaneously, and using the exact com-
plementary inputs for the high and low side of a half-bridge may result in situations where both gates are open. This can give unneces-
sary current-draw and short circuit the power supply. The DTI unit provides dead-time insertion to deal with this problem.
UH VH WH
WLVLUL
W
V
U
Figure 20.23. TIMER Triple Half-Bridge
For each of the 3 compare-match outputs of TIMER0, an additional complementary output is provided by the DTI unit. These outputs,
named TIM0_CDTI0, TIM0_CDTI1 and TIM0_CDTI2 are provided to make control of e.g. 3-channel BLDC or PMAC motors possible
using only a single timer, see the following figure.
Clock control Counter
Select
DTFALLT DTRISET
=0
Original PWM (TIM0_CCx_pre)
HFPERCLKTIMERn
Primary output (TIM0_CCx)
Complementary Output (TIM0_CDTIx)
Figure 20.24. TIMER Overview of Dead-Time Insertion Block for a Single PWM Channel
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The DTI unit is enabled by setting DTEN in TIMER0_DTCTRL. In addition to providing the complementary outputs, the DTI unit then
also overrides the compare match outputs from the timer.
The DTI unit gives the rising edges of the PWM outputs and the rising edges of the complementary PWM outputs a configurable time
delay. By doing this, the DTI unit introduces a dead-time where both the primary and complementary outputs in a pair are inactive as
seen in the following figure.
Original PWM
TIM0_CC0
TIM0_CDTI0
dt1
dt2
Figure 20.25. TIMER Polarity of Both Signals are Set as Active-High
Dead-time is specified individually for the rising and falling edge of the original PWM. These values are shared across all the three
PWM channels of the DTI unit. A single prescaler value is provided for the DTI unit, meaning that both the rising and falling edge dead-
times share prescaler value. The prescaler divides the HFPERCLKTIMERn by a configurable factor between 1 and 1024, which is set in
the DTPRESC field in TIMER0_DTTIME. The rising and falling edge dead-times are configured in DTRISET and DTFALLT in TIM-
ER0_DTTIME to any number between 1-64 HFPERCLKTIMER0 cycles.
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20.3.3.1 Output Polarity
The value of the primary and complementary outputs in a pair will never be set active at the same time by the DTI unit. The polarity of
the outputs can be changed however, if this is required by the application. The active values of the primary and complementary outputs
are set by two the TIMER0_DTCTRL register. The DTIPOL bit of this register specifies the base polarity. If DTIPOL =0, then the outputs
are active-high, and if DTIPOL = 1 they are active-low. The relative phase of the primary and complementary outputs is not changed by
DTIPOL, as the polarity of both outputs is changed, see Figure 20.26 TIMER Output Polarities on page 689.
In some applications, it may be required that the primary outputs are active-high, while the complementary outputs are active-low. This
can be accomplished by manipulating the DTCINV bit of the TIMER0_DTCTRL register, which inverts the polarity of the complementary
outputs relative to the primary outputs.
TIMER DTI Example 1
DTIPOL = 0 and DTCINV = 0 results in outputs with opposite phase and active-high states.
TIMER DTI Example 2
DTIPOL = 1 and DTCINV = 1 results in outputs with equal phase. The primary output will be active-high, while the complementary will
be active-low.
Original PWM
TIM0_CC0
TIM0_CDTI0
TIM0_CC0
TIM0_CDTI0
TIM0_CC0
TIM0_CDTI0
TIM0_CC0
TIM0_CDTI0
DTIPOL = 0
DTCINV = 0
DTIPOL = 1
DTCINV = 0
DTIPOL = 0
DTCINV = 1
DTIPOL = 1
DTCINV = 1
Figure 20.26. TIMER Output Polarities
Output generation on the individual DTI outputs can be disabled by configuring TIMER0_DTOGEN. When output generation on an out-
put is disabled, it will go to and stay in its inactive state.
20.3.3.2 PRS Channel as Source
A PRS channel can optionally be used as input to the DTI module instead of the PWM output from the timer. Setting DTPRSEN in
TIMER0_DTCTRL will override the source of the first DTI channel, driving TIM0_CC0 and TIM0_CDTI0, with the value on the PRS
channel. The rest of the DTI channels will continue to be driven by the PWM output from the timer. The PRS channel to use is chosen
by configuring DTPRSSEL in TIMER0_DTCTRL. Note that the timer must be running even when PRS is used as DTI source.
The DTI prescaler, set by DTPRESC in TIMER0_DTTIME determines with which accuracy the DTI can insert dead-time into a PRS
signal. The maximum dead-time error equals 2DTPRESC clock cycles. With zero prescaling, the inserted dead-times are therefore accu-
rate, but they may be inaccurate for larger prescaler settings.
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20.3.3.3 Fault Handling
The fault handling system of the DTI unit allows the outputs of the DTI unit to be put in a well-defined state in case of a fault. This
hardware fault handling system makes a fast reaction to faults possible, reducing the possibility of damage to the system.
The fault sources which trigger a fault in the DTI module are determined by TIMER0_DTFSEN. Any combination of the available error
sources can be selected:
• PRS source 0, determined by DTPRS0FSEL in TIMER0_DTFC
• PRS source 1, determined by DTPRS1FSEL in TIMER0_DTFC
• Debugger
• Core Lockup
One or two PRS channels can be used as an error source. When PRS source 0 is selected as an error source, DTPRS0FSEL deter-
mines which PRS channel is used for this source. DTPRS1FSEL determines which PRS channel is selected as PRS source 1. Please
note that for Core Lockup, the LOCKUPRDIS in RMU_CTRL must be set. Otherwise this will generate a full reset of the EFM32.
20.3.3.3.1 Action on Fault
When a fault occurs, the bit representing the fault source is set in DTFS, and the outputs from the DTI unit are set to a well-defined
state. The following options are available, and can be enabled by configuring DTFACT in TIMER0_DTFC:
• Set outputs to inactive level
• Clear outputs
• Tristate outputs
With the first option enabled, the output state in case of a fault depends on the polarity settings for the individual outputs. An output set
to be active high will be set low if a fault is detected, while an output set to be active low will be driven high.
When a fault occurs, the fault source(s) can be read out of TIMER0_DTFS. TIMER0_DTFS is organized in the same way as DTFSEN,
with one bit for each source.
20.3.3.3.2 Exiting Fault State
When a fault is triggered by the PRS system, software intervention is required to re-enable the outputs of the DTI unit. This is done by
manually clearing TIMER0_DTFS. If the fault cause, determined by TIMER0_DTFS, is the debugger alone, the outputs can optionally
be re-enabled when the debugger exits and the processor resumes normal operation. The corresponding bit in TIMER0_DTFS will in
that case be cleared by hardware. The automatic start-up functionality can be enabled by setting DTDAS in TIMER0_DTCTRL. If more
bits are still set in DTFS when the automatic start-up functionality has cleared the debugger bit, the DTI module does not exit the fault
state. The fault state is only exited when all the bits in TIMER0_DTFS have been cleared.
20.3.3.4 Configuration Lock
To prevent software errors from making changes to the DTI configuration, a configuration lock is available. Writing any value but
0xCE80 to LOCKKEY in TIMER0_DTLOCK results in TIMER0_DTFC, TIMER0_DTCTRL, TIMER0_DTTIME and TIMER0_ROUTE be-
ing locked for writing. To unlock the registers, write 0xCE80 to LOCKKEY in TIMER0_DTLOCK. The value of TIMER0_DTLOCK is 1
when the lock is active, and 0 when the registers are unlocked.
20.3.4 Debug Mode
When the CPU is halted in debug mode, the timer can be configured to either continue to run or to be frozen. This is configured in
DBGHALT in TIMERn_CTRL.
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20.3.5 Interrupts, DMA and PRS Output
The Timer has 5 output events:
• Counter Underflow
• Counter Overflow
• Compare match or input capture (one per Compare/Capture channel)
Each of the events has its own interrupt flag. Also, there is one interrupt flag for each Compare/Capture channel which is set on buffer
overflow in capture mode. Buffer overflow happens when a new capture pushes an old unread capture out of the TIMERn_CCx_CCV/
TIMERn_CCx_CCVB register pair.
If the interrupt flags are set and the corresponding interrupt enable bits in TIMERn_IEN) are set high, the Timer will send out an inter-
rupt request. Each of the events will also lead to a one HFPERCLKTIMERn cycle high pulse on individual PRS outputs.
Each of the events will also set a DMA request when they occur. The different DMA requests are cleared when certain acknowledge
conditions are met, see the following table. If DMACLRACT is set in TIMERn_CTRL, the DMA request is cleared when the triggered
DMA channel is active, without having to access any timer registers.
Table 20.3. TIMER Events
Event Acknowledge
Underflow/Overflow Read or write to TIMERn_CNT or TIMERn_TOPB
CC 0 Read or write to TIMERn_CC0_CCV or TIMERn_CC0_CCVB
CC 1 Read or write to TIMERn_CC1_CCV or TIMERn_CC1_CCVB
CC 2 Read or write to TIMERn_CC2_CCV or TIMERn_CC2_CCVB
20.3.6 GPIO Input/Output
The TIMn_CCx inputs/outputs and TIM0_CDTIx outputs are accessible as alternate functions through GPIO. Each pin connection can
be enabled/disabled separately by setting the corresponding CCxPEN or CDTIxPEN bits in TIMERn_ROUTE. The LOCATION bits in
the same register can be used to move all enabled pins to alternate pins.
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20.4 Register Map
The offset register address is relative to the registers base address.
Offset Name Type Description
0x000 TIMERn_CTRL RW Control Register
0x004 TIMERn_CMD W1 Command Register
0x008 TIMERn_STATUS RStatus Register
0x00C TIMERn_IEN RW Interrupt Enable Register
0x010 TIMERn_IF RInterrupt Flag Register
0x014 TIMERn_IFS W1 Interrupt Flag Set Register
0x018 TIMERn_IFC (R)W1 Interrupt Flag Clear Register
0x01C TIMERn_TOP RWH Counter Top Value Register
0x020 TIMERn_TOPB RW Counter Top Value Buffer Register
0x024 TIMERn_CNT RWH Counter Value Register
0x028 TIMERn_ROUTE RW I/O Routing Register
0x030 TIMERn_CC0_CTRL RW CC Channel Control Register
0x034 TIMERn_CC0_CCV RWH CC Channel Value Register
0x038 TIMERn_CC0_CCVP RCC Channel Value Peek Register
0x03C TIMERn_CC0_CCVB RWH CC Channel Buffer Register
0x040 TIMERn_CC1_CTRL RW CC Channel Control Register
0x044 TIMERn_CC1_CCV RWH CC Channel Value Register
0x048 TIMERn_CC1_CCVP RCC Channel Value Peek Register
0x04C TIMERn_CC1_CCVB RWH CC Channel Buffer Register
0x050 TIMERn_CC2_CTRL RW CC Channel Control Register
0x054 TIMERn_CC2_CCV RWH CC Channel Value Register
0x058 TIMERn_CC2_CCVP RCC Channel Value Peek Register
0x05C TIMERn_CC2_CCVB RWH CC Channel Buffer Register
0x070 TIMERn_DTCTRL RW DTI Control Register
0x074 TIMERn_DTTIME RW DTI Time Control Register
0x078 TIMERn_DTFC RW DTI Fault Configuration Register
0x07C TIMERn_DTOGEN RW DTI Output Generation Enable Register
0x080 TIMERn_DTFAULT RDTI Fault Register
0x084 TIMERn_DTFAULTC W1 DTI Fault Clear Register
0x088 TIMERn_DTLOCK RW DTI Configuration Lock Register
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20.5 Register Description
20.5.1 TIMERn_CTRL - Control Register
Offset Bit Position
0x000
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
16
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
Reset
0
0
0x0
0x0
0
0x0
0x0
0
0
0
0
0
0x0
Access
RW
RW
RW
RW
RW
RW
RW
RW
RW
RW
RW
RW
RW
Name
RSSCOIST
ATI
PRESC
CLKSEL
X2CNT
FALLA
RISEA
DMACLRACT
DEBUGRUN
QDM
OSMEN
SYNC
MODE
Bit Name Reset Access Description
31:30 Reserved To ensure compatibility with future devices, always write bits to 0. More information in 2.1 Conven-
tions.
29 RSSCOIST 0 RW Reload-Start Sets Compare Output initial State
When enabled, compare output is set to COIST value at Reload-Start event
28 ATI 0 RW Always Track Inputs
Enable ATI makes CCPOL always track the polarity of the inputs
27:24 PRESC 0x0 RW Prescaler Setting
These bits select the prescaling factor.
Value Mode Description
0 DIV1 The HFPERCLK is undivided
1 DIV2 The HFPERCLK is divided by 2
2 DIV4 The HFPERCLK is divided by 4
3 DIV8 The HFPERCLK is divided by 8
4 DIV16 The HFPERCLK is divided by 16
5 DIV32 The HFPERCLK is divided by 32
6 DIV64 The HFPERCLK is divided by 64
7 DIV128 The HFPERCLK is divided by 128
8 DIV256 The HFPERCLK is divided by 256
9 DIV512 The HFPERCLK is divided by 512
10 DIV1024 The HFPERCLK is divided by 1024
23:18 Reserved To ensure compatibility with future devices, always write bits to 0. More information in 2.1 Conven-
tions.
17:16 CLKSEL 0x0 RW Clock Source Select
These bits select the clock source for the timer.
Value Mode Description
0 PRESCHFPERCLK Prescaled HFPERCLK
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Bit Name Reset Access Description
1 CC1 Compare/Capture Channel 1 Input
2 TIMEROUF Timer is clocked by underflow(down-count) or overflow(up-count) in the
lower numbered neighbor Timer
15:14 Reserved To ensure compatibility with future devices, always write bits to 0. More information in 2.1 Conven-
tions.
13 X2CNT 0 RW 2x Count Mode
Enable 2x count mode
12 Reserved To ensure compatibility with future devices, always write bits to 0. More information in 2.1 Conven-
tions.
11:10 FALLA 0x0 RW Timer Falling Input Edge Action
These bits select the action taken in the counter when a falling edge occurs on the input.
Value Mode Description
0 NONE No action
1 START Start counter without reload
2 STOP Stop counter without reload
3 RELOADSTART Reload and start counter
9:8 RISEA 0x0 RW Timer Rising Input Edge Action
These bits select the action taken in the counter when a rising edge occurs on the input.
Value Mode Description
0 NONE No action
1 START Start counter without reload
2 STOP Stop counter without reload
3 RELOADSTART Reload and start counter
7 DMACLRACT 0 RW DMA Request Clear on Active
When this bit is set, the DMA requests are cleared when the corresponding DMA channel is active. This enables the timer
DMA requests to be cleared without accessing the timer.
6 DEBUGRUN 0 RW Debug Mode Run Enable
Set this bit to enable timer to run in debug mode.
Value Description
0 Timer is frozen in debug mode
1 Timer is running in debug mode
5 QDM 0 RW Quadrature Decoder Mode Selection
This bit sets the mode for the quadrature decoder.
Value Mode Description
0 X2 X2 mode selected
1 X4 X4 mode selected
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Bit Name Reset Access Description
4 OSMEN 0 RW One-shot Mode Enable
Enable/disable one shot mode.
3 SYNC 0 RW Timer Start/Stop/Reload Synchronization
When this bit is set, the Timer is started/stopped/reloaded by start/stop/reload commands in the other timers
Value Description
0 Timer is not started/stopped/reloaded by other timers
1 Timer is started/stopped/reloaded by other timers
2 Reserved To ensure compatibility with future devices, always write bits to 0. More information in 2.1 Conven-
tions.
1:0 MODE 0x0 RW Timer Mode
These bit set the counting mode for the Timer. Note, when Quadrature Decoder Mode is selected (MODE = 'b11), the
CLKSEL is don't care. The Timer is clocked by the Decoder Mode clock output.
Value Mode Description
0 UP Up-count mode
1 DOWN Down-count mode
2 UPDOWN Up/down-count mode
3 QDEC Quadrature decoder mode
20.5.2 TIMERn_CMD - Command Register
Offset Bit Position
0x004
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
16
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
Reset
0
0
Access
W1
W1
Name
STOP
START
Bit Name Reset Access Description
31:2 Reserved To ensure compatibility with future devices, always write bits to 0. More information in 2.1 Conven-
tions.
1 STOP 0 W1 Stop Timer
Write a 1 to this bit to stop timer
0 START 0 W1 Start Timer
Write a 1 to this bit to start timer
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20.5.3 TIMERn_STATUS - Status Register
Offset Bit Position
0x008
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
16
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
Reset
0
0
0
0
0
0
0
0
0
0
0
0
Access
R
R
R
R
R
R
R
R
R
R
R
R
Name
CCPOL2
CCPOL1
CCPOL0
ICV2
ICV1
ICV0
CCVBV2
CCVBV1
CCVBV0
TOPBV
DIR
RUNNING
Bit Name Reset Access Description
31:27 Reserved To ensure compatibility with future devices, always write bits to 0. More information in 2.1 Conven-
tions.
26 CCPOL2 0 R CC2 Polarity
In Input Capture mode, this bit indicates the polarity of the edge that triggered capture in TIMERn_CC2_CCV. In
Compare/PWM mode, this bit indicates the polarity of the selected input to CC channel 2. These bits are cleared when
CCMODE is written to 0b00 (Off).
Value Mode Description
0 LOWRISE CC2 polarity low level/rising edge
1 HIGHFALL CC2 polarity high level/falling edge
25 CCPOL1 0 R CC1 Polarity
In Input Capture mode, this bit indicates the polarity of the edge that triggered capture in TIMERn_CC1_CCV. In
Compare/PWM mode, this bit indicates the polarity of the selected input to CC channel 1. These bits are cleared when
CCMODE is written to 0b00 (Off).
Value Mode Description
0 LOWRISE CC1 polarity low level/rising edge
1 HIGHFALL CC1 polarity high level/falling edge
24 CCPOL0 0 R CC0 Polarity
In Input Capture mode, this bit indicates the polarity of the edge that triggered capture in TIMERn_CC0_CCV. In
Compare/PWM mode, this bit indicates the polarity of the selected input to CC channel 0. These bits are cleared when
CCMODE is written to 0b00 (Off).
Value Mode Description
0 LOWRISE CC0 polarity low level/rising edge
1 HIGHFALL CC0 polarity high level/falling edge
23:19 Reserved To ensure compatibility with future devices, always write bits to 0. More information in 2.1 Conven-
tions.
18 ICV2 0 R CC2 Input Capture Valid
This bit indicates that TIMERn_CC2_CCV contains a valid capture value. These bits are only used in input capture mode
and are cleared when CCMODE is written to 0b00 (Off).
Value Description
0 TIMERn_CC2_CCV does not contain a valid capture value(FIFO emp-
ty)
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Bit Name Reset Access Description
1 TIMERn_CC2_CCV contains a valid capture value(FIFO not empty)
17 ICV1 0 R CC1 Input Capture Valid
This bit indicates that TIMERn_CC1_CCV contains a valid capture value. These bits are only used in input capture mode
and are cleared when CCMODE is written to 0b00 (Off).
Value Description
0 TIMERn_CC1_CCV does not contain a valid capture value(FIFO emp-
ty)
1 TIMERn_CC1_CCV contains a valid capture value(FIFO not empty)
16 ICV0 0 R CC0 Input Capture Valid
This bit indicates that TIMERn_CC0_CCV contains a valid capture value. These bits are only used in input capture mode
and are cleared when CCMODE is written to 0b00 (Off).
Value Description
0 TIMERn_CC0_CCV does not contain a valid capture value(FIFO emp-
ty)
1 TIMERn_CC0_CCV contains a valid capture value(FIFO not empty)
15:11 Reserved To ensure compatibility with future devices, always write bits to 0. More information in 2.1 Conven-
tions.
10 CCVBV2 0 R CC2 CCVB Valid
This field indicates that the TIMERn_CC2_CCVB registers contain data which have not been written to
TIMERn_CC2_CCV. These bits are only used in output compare/pwm mode and are cleared when CCMODE is written to
0b00 (Off).
Value Description
0 TIMERn_CC2_CCVB does not contain valid data
1 TIMERn_CC2_CCVB contains valid data which will be written to
TIMERn_CC2_CCV on the next update event
9 CCVBV1 0 R CC1 CCVB Valid
This field indicates that the TIMERn_CC1_CCVB registers contain data which have not been written to
TIMERn_CC1_CCV. These bits are only used in output compare/pwm mode and are cleared when CCMODE is written to
0b00 (Off).
Value Description
0 TIMERn_CC1_CCVB does not contain valid data
1 TIMERn_CC1_CCVB contains valid data which will be written to
TIMERn_CC1_CCV on the next update event
8 CCVBV0 0 R CC0 CCVB Valid
This field indicates that the TIMERn_CC0_CCVB registers contain data which have not been written to
TIMERn_CC0_CCV. These bits are only used in output compare/pwm mode and are cleared when CCMODE is written to
0b00 (Off).
Value Description
0 TIMERn_CC0_CCVB does not contain valid data
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Bit Name Reset Access Description
1 TIMERn_CC0_CCVB contains valid data which will be written to
TIMERn_CC0_CCV on the next update event
7:3 Reserved To ensure compatibility with future devices, always write bits to 0. More information in 2.1 Conven-
tions.
2 TOPBV 0 R TOPB Valid
This indicates that TIMERn_TOPB contains valid data that has not been written to TIMERn_TOP. This bit is also cleared
when TIMERn_TOP is written.
Value Description
0 TIMERn_TOPB does not contain valid data
1 TIMERn_TOPB contains valid data which will be written to
TIMERn_TOP on the next update event
1 DIR 0 R Direction
Indicates count direction.
Value Mode Description
0 UP Counting up
1 DOWN Counting down
0 RUNNING 0 R Running
Indicates if timer is running or not.
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20.5.4 TIMERn_IEN - Interrupt Enable Register
Offset Bit Position
0x00C
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
16
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
Reset
0
0
0
0
0
0
0
0
Access
RW
RW
RW
RW
RW
RW
RW
RW
Name
ICBOF2
ICBOF1
ICBOF0
CC2
CC1
CC0
UF
OF
Bit Name Reset Access Description
31:11 Reserved To ensure compatibility with future devices, always write bits to 0. More information in 2.1 Conven-
tions.
10 ICBOF2 0 RW CC Channel 2 Input Capture Buffer Overflow Interrupt Enable
Enable/disable Compare/Capture ch 2 input capture buffer overflow interrupt.
9 ICBOF1 0 RW CC Channel 1 Input Capture Buffer Overflow Interrupt Enable
Enable/disable Compare/Capture ch 1 input capture buffer overflow interrupt.
8 ICBOF0 0 RW CC Channel 0 Input Capture Buffer Overflow Interrupt Enable
Enable/disable Compare/Capture ch 0 input capture buffer overflow interrupt.
7 Reserved To ensure compatibility with future devices, always write bits to 0. More information in 2.1 Conven-
tions.
6 CC2 0 RW CC Channel 2 Interrupt Enable
Enable/disable Compare/Capture ch 2 interrupt.
5 CC1 0 RW CC Channel 1 Interrupt Enable
Enable/disable Compare/Capture ch 1 interrupt.
4 CC0 0 RW CC Channel 0 Interrupt Enable
Enable/disable Compare/Capture ch 0 interrupt.
3:2 Reserved To ensure compatibility with future devices, always write bits to 0. More information in 2.1 Conven-
tions.
1 UF 0 RW Underflow Interrupt Enable
Enable/disable underflow interrupt.
0 OF 0 RW Overflow Interrupt Enable
Enable/disable overflow interrupt.
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20.5.5 TIMERn_IF - Interrupt Flag Register
Offset Bit Position
0x010
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
16
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
Reset
0
0
0
0
0
0
0
0
Access
R
R
R
R
R
R
R
R
Name
ICBOF2
ICBOF1
ICBOF0
CC2
CC1
CC0
UF
OF
Bit Name Reset Access Description
31:11 Reserved To ensure compatibility with future devices, always write bits to 0. More information in 2.1 Conven-
tions.
10 ICBOF2 0 R CC Channel 2 Input Capture Buffer Overflow Interrupt Flag
This bit indicates that a new capture value has pushed an unread value out of the TIMERn_CC2_CCV/
TIMERn_CC2_CCVB register pair.
9 ICBOF1 0 R CC Channel 1 Input Capture Buffer Overflow Interrupt Flag
This bit indicates that a new capture value has pushed an unread value out of the TIMERn_CC1_CCV/
TIMERn_CC1_CCVB register pair.
8 ICBOF0 0 R CC Channel 0 Input Capture Buffer Overflow Interrupt Flag
This bit indicates that a new capture value has pushed an unread value out of the TIMERn_CC0_CCV/
TIMERn_CC0_CCVB register pair.
7 Reserved To ensure compatibility with future devices, always write bits to 0. More information in 2.1 Conven-
tions.
6 CC2 0 R CC Channel 2 Interrupt Flag
This bit indicates that there has been an interrupt event on Compare/Capture channel 2.
5 CC1 0 R CC Channel 1 Interrupt Flag
This bit indicates that there has been an interrupt event on Compare/Capture channel 1.
4 CC0 0 R CC Channel 0 Interrupt Flag
This bit indicates that there has been an interrupt event on Compare/Capture channel 0.
3:2 Reserved To ensure compatibility with future devices, always write bits to 0. More information in 2.1 Conven-
tions.
1 UF 0 R Underflow Interrupt Flag
This bit indicates that there has been an underflow.
0 OF 0 R Overflow Interrupt Flag
This bit indicates that there has been an overflow.
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20.5.6 TIMERn_IFS - Interrupt Flag Set Register
Offset Bit Position
0x014
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
16
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
Reset
0
0
0
0
0
0
0
0
Access
W1
W1
W1
W1
W1
W1
W1
W1
Name
ICBOF2
ICBOF1
ICBOF0
CC2
CC1
CC0
UF
OF
Bit Name Reset Access Description
31:11 Reserved To ensure compatibility with future devices, always write bits to 0. More information in 2.1 Conven-
tions.
10 ICBOF2 0 W1 CC Channel 2 Input Capture Buffer Overflow Interrupt Flag Set
Writing a 1 to this bit will set Compare/Capture channel 2 input capture buffer overflow interrupt flag.
9 ICBOF1 0 W1 CC Channel 1 Input Capture Buffer Overflow Interrupt Flag Set
Writing a 1 to this bit will set Compare/Capture channel 1 input capture buffer overflow interrupt flag.
8 ICBOF0 0 W1 CC Channel 0 Input Capture Buffer Overflow Interrupt Flag Set
Writing a 1 to this bit will set Compare/Capture channel 0 input capture buffer overflow interrupt flag.
7 Reserved To ensure compatibility with future devices, always write bits to 0. More information in 2.1 Conven-
tions.
6 CC2 0 W1 CC Channel 2 Interrupt Flag Set
Writing a 1 to this bit will set Compare/Capture channel 2 interrupt flag.
5 CC1 0 W1 CC Channel 1 Interrupt Flag Set
Writing a 1 to this bit will set Compare/Capture channel 1 interrupt flag.
4 CC0 0 W1 CC Channel 0 Interrupt Flag Set
Writing a 1 to this bit will set Compare/Capture channel 0 interrupt flag.
3:2 Reserved To ensure compatibility with future devices, always write bits to 0. More information in 2.1 Conven-
tions.
1 UF 0 W1 Underflow Interrupt Flag Set
Writing a 1 to this bit will set the underflow interrupt flag.
0 OF 0 W1 Overflow Interrupt Flag Set
Writing a 1 to this bit will set the overflow interrupt flag.
EFM32WG Reference Manual
TIMER - Timer/Counter
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20.5.7 TIMERn_IFC - Interrupt Flag Clear Register
Offset Bit Position
0x018
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
16
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
Reset
0
0
0
0
0
0
0
0
Access
(R)W1
(R)W1
(R)W1
(R)W1
(R)W1
(R)W1
(R)W1
(R)W1
Name
ICBOF2
ICBOF1
ICBOF0
CC2
CC1
CC0
UF
OF
Bit Name Reset Access Description
31:11 Reserved To ensure compatibility with future devices, always write bits to 0. More information in 2.1 Conven-
tions.
10 ICBOF2 0 (R)W1 CC Channel 2 Input Capture Buffer Overflow Interrupt Flag Clear
Writing a 1 to this bit will clear Compare/Capture channel 2 input capture buffer overflow interrupt flag.
9 ICBOF1 0 (R)W1 CC Channel 1 Input Capture Buffer Overflow Interrupt Flag Clear
Writing a 1 to this bit will clear Compare/Capture channel 1 input capture buffer overflow interrupt flag.
8 ICBOF0 0 (R)W1 CC Channel 0 Input Capture Buffer Overflow Interrupt Flag Clear
Writing a 1 to this bit will clear Compare/Capture channel 0 input capture buffer overflow interrupt flag.
7 Reserved To ensure compatibility with future devices, always write bits to 0. More information in 2.1 Conven-
tions.
6 CC2 0 (R)W1 CC Channel 2 Interrupt Flag Clear
Writing a 1 to this bit will clear Compare/Capture interrupt flag 2.
5 CC1 0 (R)W1 CC Channel 1 Interrupt Flag Clear
Writing a 1 to this bit will clear Compare/Capture interrupt flag 1.
4 CC0 0 (R)W1 CC Channel 0 Interrupt Flag Clear
Writing a 1 to this bit will clear Compare/Capture interrupt flag 0.
3:2 Reserved To ensure compatibility with future devices, always write bits to 0. More information in 2.1 Conven-
tions.
1 UF 0 (R)W1 Underflow Interrupt Flag Clear
Writing a 1 to this bit will clear the underflow interrupt flag.
0 OF 0 (R)W1 Overflow Interrupt Flag Clear
Writing a 1 to this bit will clear th overflow interrupt flag.
EFM32WG Reference Manual
TIMER - Timer/Counter
silabs.com | Building a more connected world. Rev. 1.1 | 702
20.5.8 TIMERn_TOP - Counter Top Value Register
Offset Bit Position
0x01C
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
16
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
Reset
0xFFFF
Access
RWH
Name
TOP
Bit Name Reset Access Description
31:16 Reserved To ensure compatibility with future devices, always write bits to 0. More information in 2.1 Conven-
tions.
15:0 TOP 0xFFFF RWH Counter Top Value
These bits hold the TOP value for the counter.
20.5.9 TIMERn_TOPB - Counter Top Value Buffer Register
Offset Bit Position
0x020
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
16
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
Reset
0x0000
Access
RW
Name
TOPB
Bit Name Reset Access Description
31:16 Reserved To ensure compatibility with future devices, always write bits to 0. More information in 2.1 Conven-
tions.
15:0 TOPB 0x0000 RW Counter Top Value Buffer
These bits hold the TOP buffer value.
EFM32WG Reference Manual
TIMER - Timer/Counter
silabs.com | Building a more connected world. Rev. 1.1 | 703
20.5.10 TIMERn_CNT - Counter Value Register
Offset Bit Position
0x024
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
16
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
Reset
0x0000
Access
RWH
Name
CNT
Bit Name Reset Access Description
31:16 Reserved To ensure compatibility with future devices, always write bits to 0. More information in 2.1 Conven-
tions.
15:0 CNT 0x0000 RWH Counter Value
These bits hold the counter value.
EFM32WG Reference Manual
TIMER - Timer/Counter
silabs.com | Building a more connected world. Rev. 1.1 | 704
20.5.11 TIMERn_ROUTE - I/O Routing Register
Offset Bit Position
0x028
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
16
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
Reset
0x0
0
0
0
0
0
0
Access
RW
RW
RW
RW
RW
RW
RW
Name
LOCATION
CDTI2PEN
CDTI1PEN
CDTI0PEN
CC2PEN
CC1PEN
CC0PEN
Bit Name Reset Access Description
31:19 Reserved To ensure compatibility with future devices, always write bits to 0. More information in 2.1 Conven-
tions.
18:16 LOCATION 0x0 RW I/O Location
Decides the location of the CC and CDTI pins.
Value Mode Description
0 LOC0 Location 0
1 LOC1 Location 1
2 LOC2 Location 2
3 LOC3 Location 3
4 LOC4 Location 4
5 LOC5 Location 5
15:11 Reserved To ensure compatibility with future devices, always write bits to 0. More information in 2.1 Conven-
tions.
10 CDTI2PEN 0 RW CC Channel 2 Complementary Dead-Time Insertion Pin Enable
Enable/disable CC channel 2 complementary dead-time insertion output connection to pin.
9 CDTI1PEN 0 RW CC Channel 1 Complementary Dead-Time Insertion Pin Enable
Enable/disable CC channel 1 complementary dead-time insertion output connection to pin.
8 CDTI0PEN 0 RW CC Channel 0 Complementary Dead-Time Insertion Pin Enable
Enable/disable CC channel 0 complementary dead-time insertion output connection to pin.
7:3 Reserved To ensure compatibility with future devices, always write bits to 0. More information in 2.1 Conven-
tions.
2 CC2PEN 0 RW CC Channel 2 Pin Enable
Enable/disable CC channel 2 output/input connection to pin.
1 CC1PEN 0 RW CC Channel 1 Pin Enable
Enable/disable CC channel 1 output/input connection to pin.
0 CC0PEN 0 RW CC Channel 0 Pin Enable
Enable/disable CC Channel 0 output/input connection to pin.
EFM32WG Reference Manual
TIMER - Timer/Counter
silabs.com | Building a more connected world. Rev. 1.1 | 705
20.5.12 TIMERn_CCx_CTRL - CC Channel Control Register
Offset Bit Position
0x030
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
16
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
Reset
0x0
0x0
0
0
0x0
0x0
0x0
0x0
0
0
0x0
Access
RW
RW
RW
RW
RW
RW
RW
RW
RW
RW
RW
Name
ICEVCTRL
ICEDGE
FILT
INSEL
PRSSEL
CUFOA
COFOA
CMOA
COIST
OUTINV
MODE
Bit Name Reset Access Description
31:28 Reserved To ensure compatibility with future devices, always write bits to 0. More information in 2.1 Conven-
tions.
27:26 ICEVCTRL 0x0 RW Input Capture Event Control
These bits control when a Compare/Capture PRS output pulse, interrupt flag and DMA request is set.
Value Mode Description
0 EVERYEDGE PRS output pulse, interrupt flag and DMA request set on every capture
1 EVERYSECONDEDGE PRS output pulse, interrupt flag and DMA request set on every second
capture
2 RISING PRS output pulse, interrupt flag and DMA request set on rising edge
only (if ICEDGE = BOTH)
3 FALLING PRS output pulse, interrupt flag and DMA request set on falling edge
only (if ICEDGE = BOTH)
25:24 ICEDGE 0x0 RW Input Capture Edge Select
These bits control which edges the edge detector triggers on. The output is used for input capture and external clock input.
Value Mode Description
0 RISING Rising edges detected
1 FALLING Falling edges detected
2 BOTH Both edges detected
3 NONE No edge detection, signal is left as it is
23:22 Reserved To ensure compatibility with future devices, always write bits to 0. More information in 2.1 Conven-
tions.
21 FILT 0 RW Digital Filter
Enable digital filter.
Value Mode Description
0 DISABLE Digital filter disabled
1 ENABLE Digital filter enabled
20 INSEL 0 RW Input Selection
Select Compare/Capture channel input.
EFM32WG Reference Manual
TIMER - Timer/Counter
silabs.com | Building a more connected world. Rev. 1.1 | 706
Bit Name Reset Access Description
Value Mode Description
0 PIN TIMERnCCx pin is selected
1 PRS PRS input (selected by PRSSEL) is selected
19:16 PRSSEL 0x0 RW Compare/Capture Channel PRS Input Channel Selection
Select PRS input channel for Compare/Capture channel.
Value Mode Description
0 PRSCH0 PRS Channel 0 selected as input
1 PRSCH1 PRS Channel 1 selected as input
2 PRSCH2 PRS Channel 2 selected as input
3 PRSCH3 PRS Channel 3 selected as input
4 PRSCH4 PRS Channel 4 selected as input
5 PRSCH5 PRS Channel 5 selected as input
6 PRSCH6 PRS Channel 6 selected as input
7 PRSCH7 PRS Channel 7 selected as input
8 PRSCH8 PRS Channel 8 selected as input
9 PRSCH9 PRS Channel 9 selected as input
10 PRSCH10 PRS Channel 10 selected as input
11 PRSCH11 PRS Channel 11 selected as input
15:14 Reserved To ensure compatibility with future devices, always write bits to 0. More information in 2.1 Conven-
tions.
13:12 CUFOA 0x0 RW Counter Underflow Output Action
Select output action on counter underflow.
Value Mode Description
0 NONE No action on counter underflow
1 TOGGLE Toggle output on counter underflow
2 CLEAR Clear output on counter underflow
3 SET Set output on counter underflow
11:10 COFOA 0x0 RW Counter Overflow Output Action
Select output action on counter overflow.
Value Mode Description
0 NONE No action on counter overflow
1 TOGGLE Toggle output on counter overflow
2 CLEAR Clear output on counter overflow
3 SET Set output on counter overflow
EFM32WG Reference Manual
TIMER - Timer/Counter
silabs.com | Building a more connected world. Rev. 1.1 | 707
Bit Name Reset Access Description
9:8 CMOA 0x0 RW Compare Match Output Action
Select output action on compare match.
Value Mode Description
0 NONE No action on compare match
1 TOGGLE Toggle output on compare match
2 CLEAR Clear output on compare match
3 SET Set output on compare match
7:5 Reserved To ensure compatibility with future devices, always write bits to 0. More information in 2.1 Conven-
tions.
4 COIST 0 RW Compare Output Initial State
This bit is only used in Output Compare and PWM mode. When this bit is set in compare mode,the output is set high when
the counter is disabled. When counting resumes, this value will represent the initial value for the output. If the bit is cleared,
the output will be cleared when the counter is disabled. In PWM mode, the output will always be low when disabled, regard-
less of this bit. However, this bit will represent the initial value of the output, once it is enabled.
3 Reserved To ensure compatibility with future devices, always write bits to 0. More information in 2.1 Conven-
tions.
2 OUTINV 0 RW Output Invert
Setting this bit inverts the output from the CC channel (Output compare,PWM).
1:0 MODE 0x0 RW CC Channel Mode
These bits select the mode for Compare/Capture channel.
Value Mode Description
0 OFF Compare/Capture channel turned off
1 INPUTCAPTURE Input capture
2 OUTPUTCOMPARE Output compare
3 PWM Pulse-Width Modulation
EFM32WG Reference Manual
TIMER - Timer/Counter
silabs.com | Building a more connected world. Rev. 1.1 | 708
20.5.13 TIMERn_CCx_CCV - CC Channel Value Register
Offset Bit Position
0x034
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
16
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
Reset
0x0000
Access
RWH
Name
CCV
Bit Name Reset Access Description
31:16 Reserved To ensure compatibility with future devices, always write bits to 0. More information in 2.1 Conven-
tions.
15:0 CCV 0x0000 RWH CC Channel Value
In input capture mode, this field holds the first unread capture value. When reading this register in input capture mode, then
contents of the TIMERn_CCx_CCVB register will be written to TIMERn_CCx_CCV in the next cycle. In compare mode, this
fields holds the compare value.
20.5.14 TIMERn_CCx_CCVP - CC Channel Value Peek Register
Offset Bit Position
0x038
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
16
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
Reset
0x0000
Access
R
Name
CCVP
Bit Name Reset Access Description
31:16 Reserved To ensure compatibility with future devices, always write bits to 0. More information in 2.1 Conven-
tions.
15:0 CCVP 0x0000 R CC Channel Value Peek
This field is used to read the CC value without pulling data through the FIFO in capture mode.
EFM32WG Reference Manual
TIMER - Timer/Counter
silabs.com | Building a more connected world. Rev. 1.1 | 709
20.5.15 TIMERn_CCx_CCVB - CC Channel Buffer Register
Offset Bit Position
0x03C
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
16
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
Reset
0x0000
Access
RWH
Name
CCVB
Bit Name Reset Access Description
31:16 Reserved To ensure compatibility with future devices, always write bits to 0. More information in 2.1 Conven-
tions.
15:0 CCVB 0x0000 RWH CC Channel Value Buffer
In Input Capture mode, this field holds the last capture value if the TIMERn_CCx_CCV register already contains an earlier
unread capture value. In Output Compare or PWM mode, this field holds the CC buffer value which will be written to
TIMERn_CCx_CCV on an update event if TIMERn_CCx_CCVB contains valid data.
EFM32WG Reference Manual
TIMER - Timer/Counter
silabs.com | Building a more connected world. Rev. 1.1 | 710
20.5.16 TIMERn_DTCTRL - DTI Control Register
Offset Bit Position
0x070
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
16
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
Reset
0
0x0
0
0
0
0
Access
RW
RW
RW
RW
RW
RW
Name
DTPRSEN
DTPRSSEL
DTCINV
DTIPOL
DTDAS
DTEN
Bit Name Reset Access Description
31:25 Reserved To ensure compatibility with future devices, always write bits to 0. More information in 2.1 Conven-
tions.
24 DTPRSEN 0 RW DTI PRS Source Enable
Enable/disable PRS as DTI input.
23:8 Reserved To ensure compatibility with future devices, always write bits to 0. More information in 2.1 Conven-
tions.
7:4 DTPRSSEL 0x0 RW DTI PRS Source Channel Select
Select which PRS channel to listen to.
Value Mode Description
0 PRSCH0 PRS Channel 0 selected as input
1 PRSCH1 PRS Channel 1 selected as input
2 PRSCH2 PRS Channel 2 selected as input
3 PRSCH3 PRS Channel 3 selected as input
4 PRSCH4 PRS Channel 4 selected as input
5 PRSCH5 PRS Channel 5 selected as input
6 PRSCH6 PRS Channel 6 selected as input
7 PRSCH7 PRS Channel 7 selected as input
8 PRSCH8 PRS Channel 8 selected as input
9 PRSCH9 PRS Channel 9 selected as input
10 PRSCH10 PRS Channel 10 selected as input
11 PRSCH11 PRS Channel 11 selected as input
3 DTCINV 0 RW DTI Complementary Output Invert.
Set to invert complementary outputs.
2 DTIPOL 0 RW DTI Inactive Polarity
Set inactive polarity for outputs.
1 DTDAS 0 RW DTI Automatic Start-up Functionality
Configure DTI restart on debugger exit.
Value Mode Description
EFM32WG Reference Manual
TIMER - Timer/Counter
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Bit Name Reset Access Description
0 NORESTART No DTI restart on debugger exit
1 RESTART DTI restart on debugger exit
0 DTEN 0 RW DTI Enable
Enable/disable DTI.
EFM32WG Reference Manual
TIMER - Timer/Counter
silabs.com | Building a more connected world. Rev. 1.1 | 712
20.5.17 TIMERn_DTTIME - DTI Time Control Register
Offset Bit Position
0x074
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
16
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
Reset
0x00
0x00
0x0
Access
RW
RW
RW
Name
DTFALLT
DTRISET
DTPRESC
Bit Name Reset Access Description
31:22 Reserved To ensure compatibility with future devices, always write bits to 0. More information in 2.1 Conven-
tions.
21:16 DTFALLT 0x00 RW DTI Fall-time
Set time span for the falling edge.
Value Description
DTFALLT Fall time of DTFALLT+1
prescaled HFPERCLK
cycles
15:14 Reserved To ensure compatibility with future devices, always write bits to 0. More information in 2.1 Conven-
tions.
13:8 DTRISET 0x00 RW DTI Rise-time
Set time span for the rising edge.
Value Description
DTRISET Rise time of DTRISET
+1 prescaled
HFPERCLK cycles
7:4 Reserved To ensure compatibility with future devices, always write bits to 0. More information in 2.1 Conven-
tions.
3:0 DTPRESC 0x0 RW DTI Prescaler Setting
Select prescaler for DTI.
Value Mode Description
0 DIV1 The HFPERCLK is undivided
1 DIV2 The HFPERCLK is divided by 2
2 DIV4 The HFPERCLK is divided by 4
3 DIV8 The HFPERCLK is divided by 8
4 DIV16 The HFPERCLK is divided by 16
5 DIV32 The HFPERCLK is divided by 32
6 DIV64 The HFPERCLK is divided by 64
7 DIV128 The HFPERCLK is divided by 128
EFM32WG Reference Manual
TIMER - Timer/Counter
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Bit Name Reset Access Description
8 DIV256 The HFPERCLK is divided by 256
9 DIV512 The HFPERCLK is divided by 512
10 DIV1024 The HFPERCLK is divided by 1024
EFM32WG Reference Manual
TIMER - Timer/Counter
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20.5.18 TIMERn_DTFC - DTI Fault Configuration Register
Offset Bit Position
0x078
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
16
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
Reset
0
0
0
0
0x0
0x0
0x0
Access
RW
RW
RW
RW
RW
RW
RW
Name
DTLOCKUPFEN
DTDBGFEN
DTPRS1FEN
DTPRS0FEN
DTFA
DTPRS1FSEL
DTPRS0FSEL
Bit Name Reset Access Description
31:28 Reserved To ensure compatibility with future devices, always write bits to 0. More information in 2.1 Conven-
tions.
27 DTLOCKUPFEN 0 RW DTI Lockup Fault Enable
Set this bit to 1 to enable core lockup as a fault source
26 DTDBGFEN 0 RW DTI Debugger Fault Enable
Set this bit to 1 to enable debugger as a fault source
25 DTPRS1FEN 0 RW DTI PRS 1 Fault Enable
Set this bit to 1 to enable PRS source 1(PRS channel determined by DTPRS1FSEL) as a fault source
24 DTPRS0FEN 0 RW DTI PRS 0 Fault Enable
Set this bit to 1 to enable PRS source 0(PRS channel determined by DTPRS0FSEL) as a fault source
23:18 Reserved To ensure compatibility with future devices, always write bits to 0. More information in 2.1 Conven-
tions.
17:16 DTFA 0x0 RW DTI Fault Action
Select fault action.
Value Mode Description
0 NONE No action on fault
1 INACTIVE Set outputs inactive
2 CLEAR Clear outputs
3 TRISTATE Tristate outputs
15:11 Reserved To ensure compatibility with future devices, always write bits to 0. More information in 2.1 Conven-
tions.
10:8 DTPRS1FSEL 0x0 RW DTI PRS Fault Source 1 Select
Select PRS channel for fault source 1.
Value Mode Description
0 PRSCH0 PRS Channel 0 selected as fault source 1
1 PRSCH1 PRS Channel 1 selected as fault source 1
2 PRSCH2 PRS Channel 2 selected as fault source 1
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TIMER - Timer/Counter
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Bit Name Reset Access Description
3 PRSCH3 PRS Channel 3 selected as fault source 1
4 PRSCH4 PRS Channel 4 selected as fault source 1
5 PRSCH5 PRS Channel 5 selected as fault source 1
6 PRSCH6 PRS Channel 6 selected as fault source 1
7 PRSCH7 PRS Channel 7 selected as fault source 1
7:3 Reserved To ensure compatibility with future devices, always write bits to 0. More information in 2.1 Conven-
tions.
2:0 DTPRS0FSEL 0x0 RW DTI PRS Fault Source 0 Select
Select PRS channel for fault source 0.
Value Mode Description
0 PRSCH0 PRS Channel 0 selected as fault source 0
1 PRSCH1 PRS Channel 1 selected as fault source 0
2 PRSCH2 PRS Channel 2 selected as fault source 0
3 PRSCH3 PRS Channel 3 selected as fault source 0
4 PRSCH4 PRS Channel 4 selected as fault source 0
5 PRSCH5 PRS Channel 5 selected as fault source 0
6 PRSCH6 PRS Channel 6 selected as fault source 0
7 PRSCH7 PRS Channel 7 selected as fault source 0
EFM32WG Reference Manual
TIMER - Timer/Counter
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20.5.19 TIMERn_DTOGEN - DTI Output Generation Enable Register
Offset Bit Position
0x07C
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
16
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
Reset
0
0
0
0
0
0
Access
RW
RW
RW
RW
RW
RW
Name
DTOGCDTI2EN
DTOGCDTI1EN
DTOGCDTI0EN
DTOGCC2EN
DTOGCC1EN
DTOGCC0EN
Bit Name Reset Access Description
31:6 Reserved To ensure compatibility with future devices, always write bits to 0. More information in 2.1 Conven-
tions.
5 DTOGCDTI2EN 0 RW DTI CDTI2 Output Generation Enable
This bit enables/disables output generation for the CDTI2 output from the DTI.
4 DTOGCDTI1EN 0 RW DTI CDTI1 Output Generation Enable
This bit enables/disables output generation for the CDTI1 output from the DTI.
3 DTOGCDTI0EN 0 RW DTI CDTI0 Output Generation Enable
This bit enables/disables output generation for the CDTI0 output from the DTI.
2 DTOGCC2EN 0 RW DTI CC2 Output Generation Enable
This bit enables/disables output generation for the CC2 output from the DTI.
1 DTOGCC1EN 0 RW DTI CC1 Output Generation Enable
This bit enables/disables output generation for the CC1 output from the DTI.
0 DTOGCC0EN 0 RW DTI CC0 Output Generation Enable
This bit enables/disables output generation for the CC0 output from the DTI.
EFM32WG Reference Manual
TIMER - Timer/Counter
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20.5.20 TIMERn_DTFAULT - DTI Fault Register
Offset Bit Position
0x080
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
16
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
Reset
0
0
0
0
Access
R
R
R
R
Name
DTLOCKUPF
DTDBGF
DTPRS1F
DTPRS0F
Bit Name Reset Access Description
31:4 Reserved To ensure compatibility with future devices, always write bits to 0. More information in 2.1 Conven-
tions.
3 DTLOCKUPF 0 R DTI Lockup Fault
This bit is set to 1 if a core lockup fault has occurred and DTLOCKUPFEN is set to 1. The TIMER0_DTFAULTC register
can be used to clear fault bits.
2 DTDBGF 0 R DTI Debugger Fault
This bit is set to 1 if a debugger fault has occurred and DTDBGFEN is set to 1. The TIMER0_DTFAULTC register can be
used to clear fault bits.
1 DTPRS1F 0 R DTI PRS 1 Fault
This bit is set to 1 if a PRS 1 fault has occurred and DTPRS1FEN is set to 1. The TIMER0_DTFAULTC register can be
used to clear fault bits.
0 DTPRS0F 0 R DTI PRS 0 Fault
This bit is set to 1 if a PRS 0 fault has occurred and DTPRS0FEN is set to 1. The TIMER0_DTFAULTC register can be
used to clear fault bits.
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20.5.21 TIMERn_DTFAULTC - DTI Fault Clear Register
Offset Bit Position
0x084
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
16
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
Reset
0
0
0
0
Access
W1
W1
W1
W1
Name
TLOCKUPFC
DTDBGFC
DTPRS1FC
DTPRS0FC
Bit Name Reset Access Description
31:4 Reserved To ensure compatibility with future devices, always write bits to 0. More information in 2.1 Conven-
tions.
3 TLOCKUPFC 0 W1 DTI Lockup Fault Clear
Write 1 to this bit to clear core lockup fault.
2 DTDBGFC 0 W1 DTI Debugger Fault Clear
Write 1 to this bit to clear debugger fault.
1 DTPRS1FC 0 W1 DTI PRS1 Fault Clear
Write 1 to this bit to clear PRS 1 fault.
0 DTPRS0FC 0 W1 DTI PRS0 Fault Clear
Write 1 to this bit to clear PRS 0 fault.
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20.5.22 TIMERn_DTLOCK - DTI Configuration Lock Register
Offset Bit Position
0x088
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
16
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
Reset
0x0000
Access
RW
Name
LOCKKEY
Bit Name Reset Access Description
31:16 Reserved To ensure compatibility with future devices, always write bits to 0. More information in 2.1 Conven-
tions.
15:0 LOCKKEY 0x0000 RW DTI Lock Key
Write any other value than the unlock code to lock TIMER0_ROUTE, TIMER0_DTCTRL, TIMER0_DTTIME and TIM-
ER0_DTFC from editing. Write the unlock code to unlock. When reading the register, bit 0 is set when the lock is enabled.
Mode Value Description
Read Operation
UNLOCKED 0 TIMER DTI registers are unlocked
LOCKED 1 TIMER DTI registers are locked
Write Operation
LOCK 0 Lock TIMER DTI registers
UNLOCK 0xCE80 Unlock TIMER DTI registers
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21. RTC - Real Time Counter
3210
Quick Facts
What?
The Real Time Counter (RTC) ensures timekeeping
in low energy modes. Combined with two low power
oscillators (XTAL or RC), the RTC can run in EM2
with total current consumption less than 0.95 μA,
and in EM3 with total current consumption less than
0.65 μA.
Why?
Timekeeping over long time periods is required in
many applications, while using as little power as
possible.
How?
Selectable 1 kHz and 32.768 Hz oscillators that can
be used as clock source and two different compare
registers that can trigger a wake-up. 24-bit resolution
and selectable prescaling allow the system to stay in
EM2 or EM3 for a long time and still maintain relia-
ble timekeeping.
21.1 Introduction
The Real Time Counter (RTC) contains a 24-bit counter and is clocked either by a 32.768 Hz crystal oscillator, a 32.768 Hz RC oscilla-
tor, or a 1 kHz RC oscillator . In addition to energy modes EM0 and EM1, the RTC is also available in EM2. This makes it ideal for
keeping track of time since the RTC is enabled in EM2 where most of the device is powered down. Using the 1 kHz ULFRCO as input
clock, the RTC can be used for timekeeping all the way down to EM3.
Two compare channels are available in the RTC. These can be used to trigger interrupts and to wake the device up from a low energy
mode. They can also be used with the LETIMER to generate various output waveforms.
21.2 Features
• 24-bit Real Time Counter.
• Prescaler
•32.768 kHz/2N, N = 0 - 15.
• Overflow @ 0.14 hours for prescaler setting = 0.
• Overflow @ 4660 hours (194 days) for prescaler setting = 15 (1 s tick).
• Two compare registers
• A compare match can potentially wake-up the device from low energy modes EM1 and EM2.
• Second compare register can be top value for RTC.
• Both compare channels can trigger LETIMER.
• Compare match events are available to other peripherals through the Peripheral Reflex System (PRS).
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21.3 Functional Description
The RTC is a 24-bit counter with two compare channels. The RTC is closely coupled with the LETIMER, and can be configured to trig-
ger it on a compare match on one or both compare channels. An overview of the RTC module is shown in the following figure.
Counter (CNT)
Peripheral bus
=
Compare match 1
Compare match 0
RTC Control and
Status
=
LFACLKRTC Compare 0
(COMP0)
Compare 1
(COMP1)
Clear
Figure 21.1. RTC Overview
21.3.1 Counter
The RTC is enabled by setting the EN bit in the RTC_CTRL register. It counts up as long as it is enabled, and will on an overflow simply
wrap around and continue counting. The RTC is cleared when it is disabled. The timer value is both readable and writable and the RTC
always starts counting from 0 when enabled. The value of the counter can be read or modified using the RTC_CNT register.
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21.3.1.1 Clock Source
The RTC clock source and its prescaler value are defined in the Register Description section of the Clock Management Unit (CMU).
The clock used by the RTC has a frequency given by the following equation.
fRTC =
fLFACLK
2RTC_PRESC
where fLFACLK is the LFACLK frequency (32.768 kHz) and RTC_PRESC is a 4 bit value. The following table shows the time of overflow
and resolution of the RTC at the available prescaler values.
To use this module, the LE interface clock must be enabled in CMU_HFCORECLKEN0 in addition to the module clock.
Table 21.1. RTC Resolution vs Overflow
RTC_PRESC Resolution Overflow
0 30.5 μs 512 s
1 61.0 μs 1024 s
2 122 μs 2048 s
3 244 μs 1.14 hours
4 488 μs 2.28 hours
5 977 μs 4.55 hours
6 1.95 ms 9.10 hours
7 3.91 ms 18.2 hours
8 7.81 ms 1.52 days
9 15.6 ms 3.03 days
10 31.25 ms 6.07 days
11 62.5 ms 12.1 days
12 0.125 s 24.3 days
13 0.25 s 48.5 days
14 0.5 s 97.1 days
15 1 s 194 days
21.3.2 Compare Channels
Two compare channels are available in the RTC. The compare values can be set by writing to the RTC compare channel registers
RTC_COMPn, and when RTC_CNT is equal to one of these, the respective compare interrupt flag COMPn is set.
If COMP0TOP is set, the compare value set for compare channel 0 is used as a top value for the RTC, and the timer is cleared on a
compare match with compare channel 0. If using the COMP0TOP setting, make sure to set this bit prior to or at the same time the EN
bit is set. Setting COMP0TOP after the EN bit is set may cause unintended operation (i.e. if CNT > COMP0).
21.3.2.1 LETIMER Triggers
A compare event on either of the compare channels can start the LETIMER. See the LETIMER documentation for more information on
this feature.
21.3.2.2 PRS Sources
Both the compare channels of the RTC can be used as PRS sources. They will generate a pulse lasting one RTC clock cycle on a
compare match.
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21.3.3 Interrupts
The interrupts generated by the RTC are combined into one interrupt vector. If interrupts for the RTC is enabled, an interrupt will be
made if one or more of the interrupt flags in RTC_IF and their corresponding bits in RTC_IEN are set. Interrupt events are overflow and
compare match on either compare channels. Clearing of an interrupt flag is performed by writing to the corresponding bit in the
RTC_IFC register.
21.3.4 DEBUGRUN
By default, the RTC is halted when code execution is halted from the debugger. By setting the DEBUGRUN bit in the RTC_CTRL regis-
ter, the RTC will continue to run even when the debugger is halted.
21.3.5 Using the RTC in EM3
The RTC can be enabled all the way down to EM3 by using the ULFRCO as clock source. This is done by clearing
CMU_LFCLKSEL_LFA and setting CMU_LFCLKSEL_LFAE to 1. This will make the RTC use the internal 1 kHz ultra low frequency RC
oscillator (ULFRCO), consuming very little energy. Please note that the ULFRCO is not accurate over temperature and voltage, and it
should be verified that the ULFRCO fulfills the timekeeping needs of the application before using this in the design.
21.3.6 Register Access
This module is a Low Energy Peripheral, and supports immediate synchronization. For description regarding immediate synchroniza-
tion, refer to 5.2.4.1.1 Writing .
21.4 Register Map
The offset register address is relative to the registers base address.
Offset Name Type Description
0x000 RTC_CTRL RW Control Register
0x004 RTC_CNT RWH Counter Value Register
0x008 RTC_COMP0 RW Compare Value Register 0
0x00C RTC_COMP1 RW Compare Value Register 1
0x010 RTC_IF RInterrupt Flag Register
0x014 RTC_IFS W1 Interrupt Flag Set Register
0x018 RTC_IFC (R)W1 Interrupt Flag Clear Register
0x01C RTC_IEN RW Interrupt Enable Register
0x020 RTC_FREEZE RW Freeze Register
0x024 RTC_SYNCBUSY RSynchronization Busy Register
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21.5 Register Description
21.5.1 RTC_CTRL - Control Register (Async Reg)
For more information about Asynchronous Registers, see 5.2.4 Access to Low Energy Peripherals (Asynchronous Registers).
Offset Bit Position
0x000
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
16
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
Reset
0
0
0
Access
RW
RW
RW
Name
COMP0TOP
DEBUGRUN
EN
Bit Name Reset Access Description
31:3 Reserved To ensure compatibility with future devices, always write bits to 0. More information in 2.1 Conven-
tions.
2 COMP0TOP 0 RW Compare Channel 0 is Top Value
When set, the counter is cleared in the clock cycle after a compare match with compare channel 0.
Value Mode Description
0 DISABLE The top value of the RTC is 16777215 (0xFFFFFF)
1 ENABLE The top value of the RTC is given by COMP0
1 DEBUGRUN 0 RW Debug Mode Run Enable
Set this bit to enable the RTC to keep running in debug.
Value Description
0 RTC is frozen in debug mode
1 RTC is running in debug mode
0 EN 0 RW RTC Enable
When this bit is set, the RTC is enabled and counts up. When cleared, the counter register CNT is reset.
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21.5.2 RTC_CNT - Counter Value Register
Offset Bit Position
0x004
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
16
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
Reset
0x000000
Access
RWH
Name
CNT
Bit Name Reset Access Description
31:24 Reserved To ensure compatibility with future devices, always write bits to 0. More information in 2.1 Conven-
tions.
23:0 CNT 0x000000 RWH Counter Value
Gives access to the counter value of the RTC.
21.5.3 RTC_COMP0 - Compare Value Register 0 (Async Reg)
For more information about Asynchronous Registers, see 5.2.4 Access to Low Energy Peripherals (Asynchronous Registers).
Offset Bit Position
0x008
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
16
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
Reset
0x000000
Access
RW
Name
COMP0
Bit Name Reset Access Description
31:24 Reserved To ensure compatibility with future devices, always write bits to 0. More information in 2.1 Conven-
tions.
23:0 COMP0 0x000000 RW Compare Value 0
A compare match event occurs when CNT is equal to this value. This event sets the COMP0 interrupt flag, and can be
used to start the LETIMER. It is also available as a PRS signal.
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21.5.4 RTC_COMP1 - Compare Value Register 1 (Async Reg)
For more information about Asynchronous Registers, see 5.2.4 Access to Low Energy Peripherals (Asynchronous Registers).
Offset Bit Position
0x00C
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
16
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
Reset
0x000000
Access
RW
Name
COMP1
Bit Name Reset Access Description
31:24 Reserved To ensure compatibility with future devices, always write bits to 0. More information in 2.1 Conven-
tions.
23:0 COMP1 0x000000 RW Compare Value 1
A compare match event occurs when CNT is equal to this value. This event sets COMP1 interrupt flag, and can be used to
start the LETIMER. It is also available as a PRS signal.
21.5.5 RTC_IF - Interrupt Flag Register
Offset Bit Position
0x010
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
16
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
Reset
0
0
0
Access
R
R
R
Name
COMP1
COMP0
OF
Bit Name Reset Access Description
31:3 Reserved To ensure compatibility with future devices, always write bits to 0. More information in 2.1 Conven-
tions.
2 COMP1 0 R Compare Match 1 Interrupt Flag
Set on a compare match between CNT and COMP1.
1 COMP0 0 R Compare Match 0 Interrupt Flag
Set on a compare match between CNT and COMP0.
0 OF 0 R Overflow Interrupt Flag
Set on a CNT value overflow.
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21.5.6 RTC_IFS - Interrupt Flag Set Register
Offset Bit Position
0x014
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
16
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
Reset
0
0
0
Access
W1
W1
W1
Name
COMP1
COMP0
OF
Bit Name Reset Access Description
31:3 Reserved To ensure compatibility with future devices, always write bits to 0. More information in 2.1 Conven-
tions.
2 COMP1 0 W1 Set Compare match 1 Interrupt Flag
Write to 1 to set the COMP1 interrupt flag.
1 COMP0 0 W1 Set Compare match 0 Interrupt Flag
Write to 1 to set the COMP0 interrupt flag.
0 OF 0 W1 Set Overflow Interrupt Flag
Write to 1 to set the OF interrupt flag.
21.5.7 RTC_IFC - Interrupt Flag Clear Register
Offset Bit Position
0x018
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
16
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
Reset
0
0
0
Access
(R)W1
(R)W1
(R)W1
Name
COMP1
COMP0
OF
Bit Name Reset Access Description
31:3 Reserved To ensure compatibility with future devices, always write bits to 0. More information in 2.1 Conven-
tions.
2 COMP1 0 (R)W1 Clear Compare match 1 Interrupt Flag
Write to 1 to clear the COMP1 interrupt flag.
1 COMP0 0 (R)W1 Clear Compare match 0 Interrupt Flag
Write to 1 to clear the COMP0 interrupt flag.
0 OF 0 (R)W1 Clear Overflow Interrupt Flag
Write to 1 to clear the OF interrupt flag.
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21.5.8 RTC_IEN - Interrupt Enable Register
Offset Bit Position
0x01C
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
16
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
Reset
0
0
0
Access
RW
RW
RW
Name
COMP1
COMP0
OF
Bit Name Reset Access Description
31:3 Reserved To ensure compatibility with future devices, always write bits to 0. More information in 2.1 Conven-
tions.
2 COMP1 0 RW Compare Match 1 Interrupt Enable
Enable interrupt on compare match 1.
1 COMP0 0 RW Compare Match 0 Interrupt Enable
Enable interrupt on compare match 0.
0 OF 0 RW Overflow Interrupt Enable
Enable interrupt on overflow.
21.5.9 RTC_FREEZE - Freeze Register
Offset Bit Position
0x020
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
16
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
Reset
0
Access
RW
Name
REGFREEZE
Bit Name Reset Access Description
31:1 Reserved To ensure compatibility with future devices, always write bits to 0. More information in 2.1 Conven-
tions.
0 REGFREEZE 0 RW Register Update Freeze
When set, the update of the RTC is postponed until this bit is cleared. Use this bit to update several registers simultaneous-
ly.
Value Mode Description
0 UPDATE Each write access to an RTC register is updated into the Low Frequen-
cy domain as soon as possible.
1 FREEZE The RTC is not updated with the new written value until the freeze bit is
cleared.
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21.5.10 RTC_SYNCBUSY - Synchronization Busy Register
Offset Bit Position
0x024
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
16
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
Reset
0
0
0
Access
R
R
R
Name
COMP1
COMP0
CTRL
Bit Name Reset Access Description
31:3 Reserved To ensure compatibility with future devices, always write bits to 0. More information in 2.1 Conven-
tions.
2 COMP1 0 R COMP1 Register Busy
Set when the value written to COMP1 is being synchronized.
1 COMP0 0 R COMP0 Register Busy
Set when the value written to COMP0 is being synchronized.
0 CTRL 0 R CTRL Register Busy
Set when the value written to CTRL is being synchronized.
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22. BURTC - Backup Real Time Counter
4
3210
Quick Facts
What?
The Backup Real Time Counter (BURTC) allows
timekeeping in all energy modes. Running on the
LFXO, LFRCO, or ULFRCO, the BURTC can run in
EM4 with a total current consumption less than
0.5uA. The Backup RTC is also available when the
system is in backup mode.
Why?
Timekeeping over long time periods is required in
many applications, while using as little power as
possible.
How?
The 32-bit Backup RTC is available in all energy
modes and selectable prescaling allows the system
to stay in low energy modes for long a time and still
maintain reliable timekeeping. The BURTC also in-
cludes a feature allowing seamless switching of
clock frequency, while maintaining resolution of the
counter.
22.1 Introduction
The Backup Real Time Counter (BURTC) contains a 32-bit counter and is clocked either by a 32.768 kHz crystal oscillator, a 32.768
kHz RC oscillator, a 2kHz RC oscillator, or a 1kHz RC oscillator. A variety of prescaler settings are also available for the 32.768 kHz
oscillators. The Backup RTC is available in all energy modes, making it ideal for time keeping with minimal energy consumption. The
ability to keep running while the system is in backup mode allows the Backup RTC to keep track of time, even if the main power should
drain out.
22.2 Features
• 32-bit Real Time Counter
•Prescaler for LFXO and LFRCO, 32.768 kHz/2N, N = 0-7
• Available in all energy modes and backup mode.
• Timestamp and optionally switch to low power mode upon entry to backup mode.
• Oscillator failure detection.
• EM4 operation and wake-up.
• Not reset by system reset, only by software, pin reset, or power loss.
• Seamless frequency shifting while keeping track of time.
• 512 bytes of general purpose data retention.
• Detection of corrupt writes to retention registers when losing main power.
• PRS producer.
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L;
22.3 Functional Description
The Backup RTC is a 32-bit counter with one compare channel. The Backup RTC resides in a power domain which can be configured
to always be on, in EM0 through EM4. This domain also has the possibility to be powered by a backup battery. For further details on the
backup power domain, refer to 10.3.4 Backup Power Domain. Available in all energy modes, the Backup RTC is ideal for applications
where keeping track of time in combination with extremely low energy consumption is essential. An overview of the backup RTC is
shown in the following figure.
Counter (CNT)
Peripheral bus
Compare match
COMP0
Clear
COMP0TOP
LFXO
LFRCO
CLKSEL
RTC control and status
CNT = COMP0 *
* Number of bits evaluated
varies in low power mode
ULFRCO
2-PRESC
Figure 22.1. BURTC Overview
22.3.1 Counter
The Backup RTC is enabled by configuring MODE in the BURTC_CTRL register. This configuration of MODE determines in which en-
ergy modes the backup RTC is operational. It will always be operational in EM0-EM2, and optionally in EM3 and EM4. The Backup
RTC is available when the system is in backup mode if MODE is set to EM4EN. The counter is cleared by setting RSTEN in the control
register. A system reset will not clear the counter. The counter value can be read through the CNT register.
22.3.2 Clock Source
The Backup RTC is clocked by LFXO, LFRCO, or ULFRCO, depending on the configuration of CLKSEL in BURTC_CTRL. The PRESC
bit-field in BURTC_CTRL controls the clock prescaling factor. Prescaler is only available for LFXO and LFRCO. When using the ULFR-
CO as clock source, only two frequency options are available; 2kHz and 1kHz. The 2kHz clock is selected when PRESC in
BURTC_CTRL is set to DIV1, and the 1kHz clock is selected when PRESC is set to any other value. Available frequencies when using
LFXO or LFRCO are given in the following equation. CLKSEL should not be changed while the backup RTC is running.
fBURTC =32768
2PRESC Hz, PRESC = 0 to 7
When the LFXO or LFRCO is enabled, the Backup RTC will not use the clock until the timeout defined in the CMU has run out, i.e. the
LFXORDY/LFRCORDY flag in CMU_STATUS is set. When an oscillator first has been enabled and is used by the Backup RTC, the
Backup RTC will keep the selected clock source enabled, independent of both energy mode and CMU settings.
22.3.3 Compare Channel
The backup RTC has one compare channel. The compare value is set by writing to the COMP0 register. When the value of CNT equals
the value of COMP0, the COMP0 interrupt flag is set. If COMP0TOP in CTRL is set, the counter will wrap around when reaching the
value in the compare register, COMP.
If COMP0TOP is cleared, the counter will continue counting, wrapping around when it overflows. On overflow, the OF interrupt flag is
set.
22.3.4 PRS Sources
The compare channel of the Backup RTC can be used as PRS source. A pulse lasting one clock cycle will be generated on a compare
match. A PRS pulse will also be generated on overflow.
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22.3.5 Debug Run
By default, the backup RTC is halted when code execution is halted by the debugger. By setting the DEBUGRUN bit in the CTRL regis-
ter, the backup RTC will continue to run even when the system is halted.
22.3.6 Low Power Mode
The Backup RTC has a low power mode which lowers the power consumption at the expense of decreased resolution on compare
matches. The low power mode is enabled by configuring the LPMODE bit-field in BURTC_CTRL. When LPMODE is set to ENABLE,
low power mode is always enabled, if LPMODE is set to BUEN, the Backup RTC operates in normal mode until the system enters
backup mode, refer to 10.3.4 Backup Power Domain for details on backup mode. When the Backup RTC operates in low power mode,
a configurable number of the LSBs of COMP0 are ignored for compare match evaluation. The number of bits ignored is configured in
the LPCOMP bit-field in the BURTC_CTRL register. The following equation is used to calculate compare match resolution in low power
mode.
In low power mode, the Backup RTC will decrease its frequency by a factor of 2-LPCOMP, and start incrementing with 2LPCOMP instead
of 1. When reading the counter value from software, full resolution is maintained, the decrease in frequency will only affect the resolu-
tion on compare matches. Low power mode can be entered and exited while the Backup RTC is running. When the Backup RTC is
operating in low power mode, LPMODEACT in BURTC_STATUS is set.
CMresolution =2PRESC+LPCOMP+1
FCLK
, PRESC + LPCOMP + 1 < 9
Table 22.1. Resolution and Overflow
PRESC
Normal Mode Low Power Mode
Compare Match Resolution Overflow Compare Match Resolution Overflow
0 30.5 μs 1.52 days Previous equation 1.52 days
1 61 μs 3.03 days Previous equation 3.03 days
2 122 μs 6.07 days Previous equation 6.07 days
3 244 μs 12.14 days Previous equation 12.14 days
4 488 μs 24.27 days Previous equation 24.27 days
5 977 μs 48.54 days Previous equation 48.54 days
6 1.95 ms 97.09 days Previous equation 97.09 days
7 3.91 ms 194.18 days Previous equation 194.18 days
Note: Low power mode is only available when using LFXO or LFRCO.
22.3.7 Retention Registers
The Backup RTC includes 128 x 32 bit registers with possible retention in all energy modes. The registers are accessible through the
RETx_REG registers. Retention is by default enabled in EM0 through EM4. The registers can be shut off to save power by setting RAM
in BURTC_POWERDOWN. Note that the retention registers cannot be accessed when RSTEN in BURTC_CTRL is set.
Note: The retention registers are mapped to a RAM instance and have undefined state out of reset.
If the system should lose main power and enter backup mode while writing to the retention registers, the RAM write error flag, RAM-
WERR, in BURTC_STATUS will be set, and the attempted write will be canceled. The RAMWERR flag is cleared by writing a 1 to
CLRSTATUS in BURTC_CMD.
22.3.8 Backup Operation
The Backup RTC and the retention registers reside in a separate power domain, which in addition to being available in EM4 has the
possibility to be powered by a backup battery. Refer to 10.3.4 Backup Power Domain for further details on this power domain.
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22.3.9 Backup Mode Timestamp
The Backup RTC includes functionality for storing a timestamp when the system enters backup mode. The timestamp is stored in the
BURTC_TIMESTAMP register and is stored two cycles after entering backup mode. If Low Power mode is enabled, ignored bits will not
be stored in the timestamp register. Timestamping is enabled by setting BUMODETSEN in BURTC_CTRL. When a timestamp is stor-
ed, the BUMODETS bit in BUCTRL_STATUS is set. To prevent uncontrolled time stamping when entering and exiting backup mode,
this status bit has to be cleared before a new timestamp can be stored, by writing a 1 to CLRSTATUS in BURTC_CMD. Note that upon
clearing this bit, the data in BURTC_TIMESTAMP is no longer valid.
22.3.10 LFXO Failure Detection
To be able to detect LFXO failure, the Backup RTC includes a five bit down counter with configurable top value. The top value is config-
ured in TOP in BURTC_LFXOFDET. The counter starts at the top value and counts downwards on either LFRCO or ULFRCO, depend-
ing on the configuration of OSC in BURTC_LFXOFDET. When LFRCO is selected as clock for the down counter, it will be prescaled
with a factor of 2PRESC + LPCOMP. The counter wraps to TOP when it reaches zero. If no LFXO clock has arrived since the last time the
counter reached zero , the BURTC clock is changed to the clock source configured in OSC and the LFXOFAIL interrupt flag is set. Note
that due to synchronization, the LFXO clock needs to arrive at least two cycles before the counter reaches zero.
22.3.11 Register Access
Most Backup RTC configuration should not be changed while the counter is running, i.e. they should only be changed while RSTEN in
BURTC_CTRL is set.
Registers allowed to change run-time are BURTC_COMP0, BURTC_LPMODE, and DEBUGRUN in BURTC_CTRL. For further details
on access to these registers, refer to 5.2.4 Access to Low Energy Peripherals (Asynchronous Registers).
Note: The Backup domain has its own reset signal which is active when the device powers up for the first time. The reset is deactivated
by clearing BURSTEN in RMU_CTRL. This has to be done before any registers in the Backup RTC can be accessed.
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22.4 Register Map
The offset register address is relative to the registers base address.
Offset Name Type Description
0x000 BURTC_CTRL RW Control Register
0x004 BURTC_LPMODE RW Low power mode configuration
0x008 BURTC_CNT RCounter Value Register
0x00C BURTC_COMP0 RW Counter Compare Value
0x010 BURTC_TIMESTAMP RBackup mode timestamp
0x014 BURTC_LFXOFDET RW LFXO
0x018 BURTC_STATUS RStatus Register
0x01C BURTC_CMD W1 Command Register
0x020 BURTC_POWERDOWN RW Retention RAM power-down Register
0x024 BURTC_LOCK RW Configuration Lock Register
0x028 BURTC_IF RInterrupt Flag Register
0x02C BURTC_IFS W1 Interrupt Flag Set Register
0x030 BURTC_IFC (R)W1 Interrupt Flag Clear Register
0x034 BURTC_IEN RW Interrupt Enable Register
0x038 BURTC_FREEZE RW Freeze Register
0x03C BURTC_SYNCBUSY RSynchronization Busy Register
0x100 RET0_REG RW Retention Register
... RETx_REG RW Retention Register
0x2FC RET127_REG RW Retention Register
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22.5 Register Description
22.5.1 BURTC_CTRL - Control Register
Offset Bit Position
0x000
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
16
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
Reset
0
0x0
0x0
0x0
0
1
0
0x0
Access
RW
RW
RW
RW
RW
RW
RW
RW
Name
BUMODETSEN
CLKSEL
PRESC
LPCOMP
COMP0TOP
RSTEN
DEBUGRUN
MODE
Bit Name Reset Access Description
31:15 Reserved To ensure compatibility with future devices, always write bits to 0. More information in 2.1 Conven-
tions.
14 BUMODETSEN 0 RW Backup mode timestamp enable
When set, the BURTC will store its counter value in the BURTC_TIMESTAMP register upon backup mode entry.
13:12 CLKSEL 0x0 RW Select BURTC clock source
Value Mode Description
0 NONE No clock source selected for BURTC.
1 LFRCO LFRCO selected as BURTC clock source.
2 LFXO LFXO selected as BURTC clock source.
3 ULFRCO ULFRCO selected as BURTC clock source.
11 Reserved To ensure compatibility with future devices, always write bits to 0. More information in 2.1 Conven-
tions.
10:8 PRESC 0x0 RW Select BURTC prescaler factor
The BURTC will be prescaled by a factor of 2PRESC
Value Mode Description
0 DIV1 No prescaling.
1 DIV2 Prescaling factor of 2
2 DIV4 Prescaling factor of 4
3 DIV8 Prescaling factor of 8
4 DIV16 Prescaling factor of 16
5 DIV32 Prescaling factor of 32
6 DIV64 Prescaling factor of 64
7 DIV128 Prescaling factor of 128
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Bit Name Reset Access Description
7:5 LPCOMP 0x0 RW Low power mode compare configuration
This bit-field configures which bits to be evaluated for compare match in low power mode.
Value Mode Description
0 IGN0LSB Do not ignore any bits for compare match evaluation.
1 IGN1LSB The LSB of the counter is ignored for compare match evaluation.
2 IGN2LSB The two LSBs of the counter are ignored for compare match evalua-
tion.
3 IGN3LSB The three LSBs of the counter are ignored for compare match evalua-
tion.
4 IGN4LSB The four LSBs of the counter are ignored for compare match evalua-
tion.
5 IGN5LSB The five LSBs of the counter are ignored for compare match evalua-
tion.
6 IGN6LSB The six LSBs of the counter are ignored for compare match evaluation.
7 IGN7LSB The seven LSBs of the counter are ignored for compare match evalua-
tion.
4 COMP0TOP 0 RW Compare clear enable
When set, the counter wraps around when CNT equals COMP0
3 RSTEN 1 RW Enable BURTC reset
Reset the BURTC_CNT and BURTC_TIMESTAMP registers.
2 DEBUGRUN 0 RW Debug Mode Run Enable
Set this bit to keep the BURTC running during a debug halt.
Value Description
0 RTC is frozen in debug mode
1 RTC is running in debug mode
1:0 MODE 0x0 RW BURTC Enable
Configure in which energy modes the BURTC should keep running.
Value Mode Description
0 DISABLE The BURTC is disabled.
1 EM2EN The BURTC is in normal operating mode, operating in EM0-EM2. Os-
cillators must be enabled in CMU for use.
2 EM3EN The BURTC is enabled in EM0-EM3. Will prevent CMU from disabling
used oscillators all the way down to EM3.
3 EM4EN The BURTC is enabled in EM0-EM4. Will prevent CMU from disabling
used oscillators all the way down to EM4.
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22.5.2 BURTC_LPMODE - Low power mode configuration (Async Reg)
For more information about Asynchronous Registers, see 5.2.4 Access to Low Energy Peripherals (Asynchronous Registers).
Offset Bit Position
0x004
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
16
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
Reset
0x0
Access
RW
Name
LPMODE
Bit Name Reset Access Description
31:2 Reserved To ensure compatibility with future devices, always write bits to 0. More information in 2.1 Conven-
tions.
1:0 LPMODE 0x0 RW Low power mode configuration.
Value Mode Description
0 DISABLE Low power mode is disabled.
1 ENABLE Low power mode always enabled.
2 BUEN Low power mode enabled in backup mode.
22.5.3 BURTC_CNT - Counter Value Register
Offset Bit Position
0x008
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
16
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
Reset
0x00000000
Access
R
Name
CNT
Bit Name Reset Access Description
31:0 CNT 0x00000000 R Counter Value
Gives access to the BURTC counter value.
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22.5.4 BURTC_COMP0 - Counter Compare Value (Async Reg)
For more information about Asynchronous Registers, see 5.2.4 Access to Low Energy Peripherals (Asynchronous Registers).
Offset Bit Position
0x00C
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
16
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
Reset
0x00000000
Access
RW
Name
COMP0
Bit Name Reset Access Description
31:0 COMP0 0x00000000 RW Compare match value
Gives access to the BURTC compare value.
22.5.5 BURTC_TIMESTAMP - Backup mode timestamp
Offset Bit Position
0x010
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
16
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
Reset
0x00000000
Access
R
Name
TIMESTAMP
Bit Name Reset Access Description
31:0 TIMESTAMP 0x00000000 R Backup mode timestamp.
Contains the timestamp stored upon backup mode entry.
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22.5.6 BURTC_LFXOFDET - LFXO
Offset Bit Position
0x014
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
16
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
Reset
0x00
0x0
Access
RW
RW
Name
TOP
OSC
Bit Name Reset Access Description
31:9 Reserved To ensure compatibility with future devices, always write bits to 0. More information in 2.1 Conven-
tions.
8:4 TOP 0x00 RW LFXO failure counter top value.
LFXO failure counter will wrap to this value when reaching zero.
3:2 Reserved To ensure compatibility with future devices, always write bits to 0. More information in 2.1 Conven-
tions.
1:0 OSC 0x0 RW LFXO failure detection configuration.
Select oscillator for LFXO failure detection.
Value Mode Description
0 DISABLE LFXO failure detection disabled.
1 LFRCO LFRCO used for LFXO failure detection.
2 ULFRCO ULFRCO used for LFXO failure detection.
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22.5.7 BURTC_STATUS - Status Register
Offset Bit Position
0x018
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
16
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
Reset
0
0
0
Access
R
R
R
Name
RAMWERR
BUMODETS
LPMODEACT
Bit Name Reset Access Description
31:3 Reserved To ensure compatibility with future devices, always write bits to 0. More information in 2.1 Conven-
tions.
2 RAMWERR 0 R RAM write error.
Set if backup mode is entered during a write to the retention RAM.
1 BUMODETS 0 R Timestamp for backup mode entry stored.
Set when a timestamp has been stored in BURTC_TIMESTAMP.
0 LPMODEACT 0 R Low power mode active
Set when the BURTC is in low power mode
22.5.8 BURTC_CMD - Command Register
Offset Bit Position
0x01C
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
16
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
Reset
0
Access
W1
Name
CLRSTATUS
Bit Name Reset Access Description
31:1 Reserved To ensure compatibility with future devices, always write bits to 0. More information in 2.1 Conven-
tions.
0 CLRSTATUS 0 W1 Clear BURTC_STATUS register.
Clear RAMWERR and BUMODETS in BURTC_STATUS.
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22.5.9 BURTC_POWERDOWN - Retention RAM power-down Register
Offset Bit Position
0x020
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
16
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
Reset
0
Access
RW
Name
RAM
Bit Name Reset Access Description
31:1 Reserved To ensure compatibility with future devices, always write bits to 0. More information in 2.1 Conven-
tions.
0 RAM 0 RW Retention RAM power-down
Shut off power to the Retention RAM. Once it is powered down, it cannot be powered up again
22.5.10 BURTC_LOCK - Configuration Lock Register
Offset Bit Position
0x024
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
16
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
Reset
0x0000
Access
RW
Name
LOCKKEY
Bit Name Reset Access Description
31:16 Reserved To ensure compatibility with future devices, always write bits to 0. More information in 2.1 Conven-
tions.
15:0 LOCKKEY 0x0000 RW Configuration Lock Key
Write any other value than the unlock code to lock BURTC_POWERDOWN, BURTC_CTRL, BURTC_LFXOFDET, and
BURTC_IEN registers from editing. Write the unlock code to unlock. When reading the register, bit 0 is set when the lock is
enabled.
Mode Value Description
Read Operation
UNLOCKED 0 BURTC_POWERDOWN, BURTC_CTRL, BURTC_LFXOFDET, and
BURTC_IEN registers are unlocked
LOCKED 1 BURTC_POWERDOWN, BURTC_CTRL, BURTC_LFXOFDET, and
BURTC_IEN registers are locked
Write Operation
LOCK 0 Lock BURTC_POWERDOWN, BURTC_CTRL, BURTC_LFXOFDET,
and BURTC_IEN registers
UNLOCK 0xAEE8 Unlock BURTC registers
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22.5.11 BURTC_IF - Interrupt Flag Register
Offset Bit Position
0x028
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
16
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
Reset
0
0
0
Access
R
R
R
Name
LFXOFAIL
COMP0
OF
Bit Name Reset Access Description
31:3 Reserved To ensure compatibility with future devices, always write bits to 0. More information in 2.1 Conven-
tions.
2 LFXOFAIL 0 R LFXO failure Interrupt Flag
Set on LFXO failure.
1 COMP0 0 R Compare match Interrupt Flag
Set on BURTC compare match.
0 OF 0 R Overflow Interrupt Flag
Set on BURTC overflow.
22.5.12 BURTC_IFS - Interrupt Flag Set Register
Offset Bit Position
0x02C
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
16
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
Reset
0
0
0
Access
W1
W1
W1
Name
LFXOFAIL
COMP0
OF
Bit Name Reset Access Description
31:3 Reserved To ensure compatibility with future devices, always write bits to 0. More information in 2.1 Conven-
tions.
2 LFXOFAIL 0 W1 Set LFXO fail Interrupt Flag
Write to 1 to set the LFXOFAIL interrupt flag
1 COMP0 0 W1 Set compare match Interrupt Flag
Write to 1 to set the COMP0 interrupt flag
0 OF 0 W1 Set Overflow Interrupt Flag
Write to 1 to set the OF interrupt flag
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22.5.13 BURTC_IFC - Interrupt Flag Clear Register
Offset Bit Position
0x030
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
16
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
Reset
0
0
0
Access
(R)W1
(R)W1
(R)W1
Name
LFXOFAIL
COMP0
OF
Bit Name Reset Access Description
31:3 Reserved To ensure compatibility with future devices, always write bits to 0. More information in 2.1 Conven-
tions.
2 LFXOFAIL 0 (R)W1 Clear LFXO failure Interrupt Flag
Write to 1 to clear the LFXOFAIL interrupt flag
1 COMP0 0 (R)W1 Clear compare match Interrupt Flag
Write to 1 to clear the COMP0 interrupt flag
0 OF 0 (R)W1 Clear Overflow Interrupt Flag
Write to 1 to clear the OF interrupt flag
22.5.14 BURTC_IEN - Interrupt Enable Register
Offset Bit Position
0x034
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
16
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
Reset
0
0
0
Access
RW
RW
RW
Name
LFXOFAIL
COMP0
OF
Bit Name Reset Access Description
31:3 Reserved To ensure compatibility with future devices, always write bits to 0. More information in 2.1 Conven-
tions.
2 LFXOFAIL 0 RW LFXO failure Interrupt Enable
Enable interrupt on LFXO failure
1 COMP0 0 RW Compare match Interrupt Enable
Enable interrupt on compare match
0 OF 0 RW Overflow Interrupt Enable
Enable interrupt on overflow
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22.5.15 BURTC_FREEZE - Freeze Register
Offset Bit Position
0x038
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
16
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
Reset
0
Access
RW
Name
REGFREEZE
Bit Name Reset Access Description
31:1 Reserved To ensure compatibility with future devices, always write bits to 0. More information in 2.1 Conven-
tions.
0 REGFREEZE 0 RW Register Update Freeze
When set, the update of the BURTC is postponed until this bit is cleared. Use this bit to update several registers simultane-
ously.
Value Mode Description
0 UPDATE Each write access to an BURTC register is updated into the Low Fre-
quency domain as soon as possible.
1 FREEZE The BURTC is not updated with the new written value until the freeze
bit is cleared.
22.5.16 BURTC_SYNCBUSY - Synchronization Busy Register
Offset Bit Position
0x03C
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
16
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
Reset
0
0
Access
R
R
Name
COMP0
LPMODE
Bit Name Reset Access Description
31:2 Reserved To ensure compatibility with future devices, always write bits to 0. More information in 2.1 Conven-
tions.
1 COMP0 0 R COMP0 Register Busy
Set when the value written to COMP0 is being synchronized.
0 LPMODE 0 R LPMODE Register Busy
Set when the value written to LPMODE is being synchronized.
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22.5.17 RETx_REG - Retention Register
Offset Bit Position
0x100
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
16
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
Reset
0xXXXXXXXX
Access
RW
Name
REG
Bit Name Reset Access Description
31:0 REG 0xXXXXXXX
X
RW General Purpose Retention Register
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23. LETIMER - Low Energy Timer
43210
RTC
LETIMER
Quick Facts
What?
The LETIMER is a down-counter that can keep track
of time and output configurable waveforms. Running
on a 32.768 Hz clock the LETIMER is available in
EM2, while using a 1 kHz clock the LETIMER is
available also in EM3, all this with sub μA current
consumption.
Why?
The LETIMER can be used to provide repeatable
waveforms to external components while remaining
in EM2. It is well suited for e.g. metering systems or
to provide more compare values than available in
the RTC.
How?
With buffered repeat and top value registers,the LE-
TIMER can provide glitch-freewaveforms at frequen-
cies up to 16 kHz. It is tightly coupled to the RTC,
which allows advanced time-keeping and wake-up-
functions in EM2 and EM3.
23.1 Introduction
The unique LETIMERTM, the Low Energy Timer, is a 16-bit timer that is available in energy mode EM2 and EM3, in addition to EM1 and
EM0. Because of this, it can be used for timing and output generation when most of the device is powered down, allowing simple tasks
to be performed while the power consumption of the system is kept at an absolute minimum.
The LETIMER can be used to output a variety of waveforms with minimal software intervention. It is also connected to the Real Time
Counter (RTC), and can be configured to start counting on compare matches from the RTC.
23.2 Features
• 16-bit down count timer
• 2 Compare match registers
• Compare register 0 can be top timer top value
• Compare registers can be double buffered
• Double buffered 8-bit Repeat Register
• Same clock source as the Real Time Counter
• LETIMER can be triggered (started) by an RTC event or by software
• 2 output pins can optionally be configured to provide different waveforms on timer underflow:
• Toggle output pin
• Apply a positive pulse (pulse width of one LFACLKLETIMER period)
• PWM
• Interrupt on:
• Compare matches
• Timer underflow
• Repeat done
• Optionally runs during debug
• PRS Output
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i
23.3 Functional Description
An overview of the LETIMER module is shown in the following figure. The LETIMER is a 16-bit down-counter with two compare regis-
ters, LETIMERn_COMP0 and LETIMERn_COMP1. The LETIMERn_COMP0 register can optionally act as a top value for the counter.
The repeat counter LETIMERn_REP0 allows the timer to count a specified number of times before it stops. Both the LETI-
MERn_COMP0 and LETIMERn_REP0 registers can be double buffered by the LETIMERn_COMP1 and LETIMERn_REP1 registers to
allow continuous operation. The timer can generate a single pin output, or two linked outputs.
Peripheral bus
= 0
COMP1
(Top Buffer)
COMP0
(Top)
CNT (Counter)
REP0
(Repeat)
REP1
(Repeat Buffer)
=1
LETIMER
Control and
Status
Reload
Update
Update
Stop 0
LFACLKLETIMERn
Start
RTC event
SW
pin
ctrl LETn_O0
Pulse
Control
Buffer
Written
Repeat
load logic
pin
ctrl LETn_O1
Pulse
Control
Top load
logic
=1
=
=
COMP0 Match
(COMP0 interrupt flag)
COMP1 Match
(COMP1 interrupt flag)
Underflow
(UF interrupt flag)
REP0
(REP0 interrupt flag)
REP1 Zero
(REP1 interrupt flag)
Figure 23.1. LETIMER Overview
23.3.1 Timer
The timer is started by setting command bit START in LETIMERn_CMD, and stopped by setting the STOP command bit in the same
register. RUNNING in LETIMERn_STATUS is set as long as the timer is running. The timer can also be started on external signals,
such as a compare match from the Real Time Counter. If START and STOP are set at the same time, STOP has priority, and the timer
will be stopped.
The timer value can be read using the LETIMERn_CNT register. The value cannot be written, but it can be cleared by setting the
CLEAR command bit in LETIMERn_CMD. If the CLEAR and START commands are issued at the same time, the timer will be cleared,
then start counting at the top value.
23.3.2 Compare Registers
The LETIMER has two compare match registers, LETIMERn_COMP0 and LETIMERn_COMP1. Each of these compare registers are
capable of generating an interrupt when the counter value LETIMERn_CNT becomes equal to their value. When LETIMERn_CNT be-
comes equal to the value of LETIMERn_COMP0, the interrupt flag COMP0 in LETIMERn_IF is set, and when LETIMERn_CNT be-
comes equal to the value of LETIMERn_COMP1, the interrupt flag COMP1 in LETIMERn_IF is set.
23.3.3 Top Value
If COMP0TOP in LETIMERn_CTRL is set, the value of LETIMERn_COMP0 acts as the top value of the timer, and LETIMERn_COMP0
is loaded into LETIMERn_CNT on timer underflow. Else, the timer wraps around to 0xFFFF. The underflow interrupt flag UF in LETI-
MERn_IF is set when the timer reaches zero.
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23.3.3.1 Buffered Top Value
If BUFTOP in LETIMERn_CTRL is set, the value of LETIMERn_COMP0 is buffered by LETIMERn_COMP1. In this mode, the value of
LETIMERn_COMP1 is loaded into LETIMERn_COMP0 every time LETIMERn_REP0 is about to decrement to 0. This can for instance
be used in conjunction with the buffered repeat mode to generate continually changing output waveforms.
Write operations to LETIMERn_COMP0 have priority over buffer loads.
23.3.3.2 Repeat Modes
By default, the timer wraps around to the top value or 0xFFFF on each underflow, and continues counting. The repeat counters can be
used to get more control of the operation of the timer, including defining the number of times the counter should wrap around. Four
different repeat modes are available, see the following table.
Table 23.1. LETIMER Repeat Modes
REPMODE Mode Description
00 Free The timer runs until it is stopped
01 One-shot The timer runs as long as LETIMERn_REP0 != 0. LETI-
MERn_REP0 is decremented at each timer underflow.
10 Buffered The timer runs as long as LETIMERn_REP0 != 0. LETI-
MERn_REP0 is decremented on each timer underflow. If LETI-
MERn_REP1 has been written, it is loaded into LETIMERn_REP0
when LETIMERn_REP0 is about to be decremented to 0.
11 Double The timer runs as long as LETIMERn_REP0 != 0 or LETI-
MERn_REP1 != 0. Both LETIMERn_REP0 and LETIMERn_REP1
are decremented at each timer underflow.
The interrupt flags REP0 and REP1 in LETIMERn_IF are set whenever LETIMERn_REP0 or LETIMERn_REP1 are decremented to 0
respectively. REP0 is also set when the value of LETIMERn_REP1 is loaded into LETIMERn_REP0 in buffered mode.
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C)
23.3.3.2.1 Free Mode
In the free running mode, the LETIMER acts as a regular timer, and the repeat counter is disabled. When started, the timer runs until it
is stopped using the STOP command bit in LETIMERn_CMD. A state machine for this mode is shown in the following figure.
Wait for positive clock edge
(RUNNING or START)
and !STOP
CNT == 0 CNT = CNT - 1
CNT = TOP* If (COMP0TOP)
TOP* = COMP0
Else
TOP* = 0xFFFF
TOP*
If (STOP)
RUNNING = 0
Else if (START)
RUNNING = 1
End if
START = 0
STOP = 0
NO
YES
NO
YES
Figure 23.2. LETIMER State Machine for Free-Running Mode
Note that the CLEAR command bit in LETIMERn_CMD always has priority over other changes to LETIMERn_CNT. When the clear
command is used, LETIMERn_CNT is set to 0 and an underflow event will not be generated when LETIMERn_CNT wraps around to
the top value or 0xFFFF. Since no underflow event is generated, no output action is performed. LETIMERn_REP0, LETIMERn_REP1,
LETIMERn_COMP0 and LETIMERn_COMP1 are also left untouched.
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23.3.3.2.2 One-shot Mode
The one-shot repeat mode is the most basic repeat mode. In this mode, the repeat register LETIMERn_REP0 is decremented every
time the timer underflows, and the timer stops when LETIMERn_REP0 goes from 1 to 0. In this mode, the timer counts down LETI-
MERn_REP0 times, i.e. the timer underflows LETIMERn_REP0 times.
Note: Note that write operations to LETIMERn_REP0 have priority over the decrementation operation. So if LETIMERn_REP0 is as-
signed a new value in the same cycle it was supposed to be decremented, it is assigned the new value instead of being decremented.
LETIMERn_REP0 can be written while the timer is running to allow the timer to run for longer periods at a time without stopping. See
the following figure.
Wait for positive clock edge
RUNNING
CNT = TOP*
If (!START)
REP0 = REP0 - 1
NO
YES
NO
REP0 < 2
YES
START
REP0 == 0
CNT = TOP*
STOP = 1
REP0 = 0
YES
NO
NO
YES
YES
YES
NO
NO
If (COMP0TOP)
TOP* = COMP0
Else
TOP* = 0xFFFF
TOP**
If (COMP0TOP)
TOP* = COMP0
Else
TOP* = 0xFFFF
TOP*
CNT == 0 CNT = CNT - 1
If (STOP)
RUNNING = 0
Else if (START)
RUNNING = 1
End if
START = 0
STOP = 0
CNT == 0
CNT = CNT - 1
Figure 23.3. LETIMER One-Shot Repeat State Machine
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23.3.3.2.3 Buffered Mode
The Buffered repeat mode allows buffered timer operation. When started, the timer runs LETIMERn_REP0 number of times. If LETI-
MERn_REP1 has been written since the last time it was used and it is nonzero, LETIMERn_REP1 is then loaded into LETI-
MERn_REP0, and counting continues the new number of times. The timer keeps going as long as LETIMERn_REP1 is updated with a
nonzero value before LETIMERn_REP0 is finished counting down.
If the timer is started when both LETIMERn_CNT and LETIMERn_REP0 are zero but LETIMERn_REP1 is non-zero, LETIMERn_REP1
is loaded into LETIMERn_REP0, and the counter counts the loaded number of times. The state machine for the one-shot repeat mode
is shown in the following figure.
Used in conjunction with a buffered top value, enabled by setting BUFTOP in LETIMERn_CTRL, the buffered mode allows buffered
values of both the top and repeat values of the timer, and the timer can for instance be set to run 4 times with period 7 (top value 6), 6
times with period 200, then 3 times with period 50.
A state machine for the buffered repeat mode is shown in the following figure. REP1USED shown in the state machine is an internal
variable that keeps track of whether the value in LETIMERn_REP1 has been loaded into LETIMERn_REP0 or not. The purpose of this
is that a value written to LETIMERn_REP1 should only be counted once. REP1USED is cleared whenever LETIMERn_REP1 is written.
Wait for positive clock edge
RUNNING
CNT = TOP*
If (!START)
REP0 = REP0 - 1
NO
YES
NO
REP0 < 2
YES
START
REP0 == 0
CNT = TOP*
YES
NO
NO
YES
YES
YES
NO
NO
If (!COMP0TOP)
TOP** = 0xFFFF
Else if (BUFTOP)
TOP** = COMP1
Else
TOP** = COMP0
TOP**
If (COMP0TOP)
TOP* = COMP0
Else
TOP* = 0xFFFF
TOP*
CNT == 0 CNT = CNT - 1
If (STOP)
RUNNING = 0
Else if (START)
RUNNING = 1
End if
START = 0
STOP = 0
CNT == 0
CNT = CNT - 1
REP1 == 0
STOP = 1
REP0 = 0
!REP1USED and
!REP1 != 0
CNT = TOP*
If (BUFTOP)
COMP0 = COMP1
REP0 = REP1
REP1USED = 1
YES
NO
YES
CNT = TOP**
If (BUFTOP)
COMP0 = COMP1
REP0 = REP1
REP1USED = 1
NO
Figure 23.4. LETIMER Buffered Repeat State Machine
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23.3.3.2.4 Double Mode
The Double repeat mode works much like the one-shot repeat mode. The difference is that, where the one-shot mode counts as long
as LETIMERn_REP0 is larger than 0, the double mode counts as long as either LETIMERn_REP0 or LETIMERn_REP1 is larger than
0. As an example, say LETIMERn_REP0 is 3 and LETIMERn_REP1 is 10 when the timer is started. If no further interaction is done with
the timer, LETIMERn_REP0 will now be decremented 3 times, and LETIMERn_REP1 will be decremented 10 times. The timer counts a
total of 10 times, and LETIMERn_REP0 is 0 after the first three timer underflows and stays at 0. LETIMERn_REP0 and LETI-
MERn_REP1 can be written at any time. After a write to either of these, the timer is guaranteed to underflow at least the written number
of times if the timer is running. Use the Double repeat mode to generate output on both the LETIMER outputs at the same time. The
state machine for this repeat mode can be seen in the following figure.
Wait for positive clock edge
RUNNING
CNT = TOP*
If (REP0 > 0)
REP0 = REP0 - 1
If (REP1 > 0)
REP1 = REP1 - 1
NO
YES
NO
REP0 < 2 and
REP1 < 2
YES
START
REP0 == 0 and
REP1 == 0
CNT = TOP*
STOP = 1
REP0 = 0
YES
NO
NO
YES
YES
YES
NO
NO
If (COMP0TOP)
TOP* = COMP0
Else
TOP* = 0xFFFF
TOP*
CNT == 0 CNT = CNT - 1
If (STOP)
RUNNING = 0
Else if (START)
RUNNING = 1
End if
START = 0
STOP = 0
CNT == 0
CNT = CNT - 1
Figure 23.5. LETIMER Double Repeat State Machine
23.3.3.3 Clock Source
Clock Source The LETIMER clock source and its prescaler value are defined in the Clock Management Unit (CMU). The LFACLKLETI-
MERn has a frequency given by the following equation.
fLFACLK_LETIMERn =32.768
2LETIMERn
where the exponent LETIMERn is a 4 bit value in the CMU_LFAPRESC0 register.
To use this module, the LE interface clock must be enabled in CMU_HFCORECLKEN0, in addition to the module clock.
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23.3.3.4 RTC Trigger
The LETIMER can be configured to start on compare match events from the Real Time Counter (RTC). If RTCC0TEN in LETI-
MERn_CTRL is set, the LETIMER will start on a compare match on RTC compare channel 0. In the same way, RTCC1TEN in LETI-
MERn_CTRL enables the LETIMER to start on a compare match with RTC compare channel 1.
Note: The LETIMER can only use compare match events from the RTC if the LETIMER runs at a higher than or equal frequency than
the RTC. Also, if the LETIMER runs at twice the frequency of the RTC, a compare match event in the RTC will trigger the LETIMER
twice. Four times the frequency gives four consecutive triggers, etc. The LETIMER will only continue running if triggered while it is run-
ning, so the multiple-triggering will only have an effect if you try to disable the RTC when it is being triggered.
23.3.3.5 Debug
If DEBUGRUN in LETIMERn_CTRL is cleared, the LETIMER automatically stops counting when the CPU is halted during a debug ses-
sion, and resumes operation when the CPU continues. Because of synchronization, the LETIMER is halted two clock cycles after the
CPU is halted, and continues running two clock cycles after the CPU continues. RUNNING in LETIMERn_STATUS is not cleared when
the LETIMER stops because of a debug-session.
Set DEBUGRUN in LETIMERn_CTRL to allow the LETIMER to continue counting even when the CPU is halted in debug mode.
23.3.4 Underflow Output Action
For each of the repeat registers, an underflow output action can be set. The configured output action is performed every time the coun-
ter underflows while the respective repeat register is nonzero. In PWM mode, the output is similarly only changed on COMP1 match if
the repeat register is nonzero. As an example, the timer will perform 7 output actions if LETIMERn_REP0 is set to 7 when starting the
timer in one-shot mode and leaving it untouched for a while.
The output actions can be set by configuring UFOA0 and UFOA1 in LETIMERn_CTRL. UFOA0 defines the action on output 0, and is
connected to LETIMERn_REP0, while UFOA1 defines the action on output 1 and is connected to LETIMERn_REP1. The possible ac-
tions are defined in the following table.
Table 23.2. LETIMER Underflow Output Actions
UF0A0/UF0A1 Mode Description
00 Idle The output is held at its idle value
01 Toggle The output is toggled on LETIMERn_CNT underflow if LEI-
MERn_REPx is nonzero
10 Pulse The output is held active for one clock cycle on LETIMERn_CNT
underflow if LETIMERn_REPx is nonzero. It then returns to its idle
value
11 PWM The output is set idle on LETIMERn_CNT underflow and active on
compare match with LETIMERn_COMP1 if LETIMERn_REPx is
nonzero.
Note: For the Pulse and PWM modes, the outputs will return to their idle states regardless of the state of the corresponding LETI-
MERn_REPx registers. They will only be set active if the LETIMERn_REPx registers are nonzero however.
The polarity of the outputs can be set individually by configuring OPOL0 and OPOL1 in LETIMERn_CTRL. When these are cleared,
their respective outputs have a low idle value and a high active value. When they are set, the idle value is high, and the active value is
low.
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When using the toggle action, the outputs can be driven to their idle values by setting their respective CTO0/CTO1 command bits in
LETIMERn_CTRL. This can be used to put the output in a well-defined state before beginning to generate toggle output, which may be
important in some applications. The command bit can also be used while the timer is running.
Some simple waveforms generated with the different output modes are shown in the following figure. For the example, REPMODE in
LETIMERn_CTRL has been cleared, COMP0TOP also in LETIMERn_CTRL has been set and LETIMERn_COMP0 has been written to
3. As seen in the figure, LETIMERn_COMP0 now decides the length of the signal periods. For the toggle mode, the period of the output
signal is 2(LETIMERn_COMP0 + 1), and for the pulse modes, the periods of the output signals are LETIMERn_COMP0+1. Note that
the pulse outputs are delayed by one period relative to the toggle output. The pulses come at the end of their periods.
CNT
COMP0 3
3
3
2
3
1
3
0
3
3
3
2
3
1
3
0
3
3
3
2
3
1
3
0
3
3
3
2
3
1
3
0
3
3
3
2
3
1
3
0
3
3
3
2
3
1
Initial configuration
UFIFUFIF UFIF UFIF UFIF
Int. flags set
LFACLKLETIMERn
LETn_O0
UFOA0 = 01
LETn_O0
UFOA0 = 10
LETn_O0
UFOA0 = 00
3
0
UFIF
3
0
Figure 23.6. LETIMER Simple Waveforms Output
For the example in the following figure , the One-shot repeat mode has been selected, and LETIMERn_REP0 has been written to 3.
The resulting behavior is pretty similar to that shown in Figure 6, but in this case, the timer stops after counting to zero LETI-
MERn_REP0 times. By using LETIMERn_REP0 the user has full control of the number of pulses/toggles generated on the output.
CNT
COMP0 3
3
3
2
3
1
3
0
3
3
3
2
3
1
3
0
3
3
3
2
3
1
3
0
Initial configuration
UFIFUFIF UFIF
Int. flags set
LFACLKLETIMERn
LETn_O0
UFOA0 = 01
LETn_O0
UFOA0 = 10
LETn_O0
UFOA0 = 00
REP0 33 3 3 22 2 2 11 1 1
Stop
REP0IF
3
0
0
3
0
0
3
0
0
3
0
0
3
0
0
3
0
0
3
0
0
3
0
0
3
0
0
3
0
0
3
0
0
3
0
0
3
0
3
Figure 23.7. LETIMER Repeated Counting
Using the Double repeat mode, output can be generated on both the LETIMER outputs. The following figure shows an example of this.
UFOA0 and UFOA1 in LETIMERn_CTRL are configured for pulse output and the outputs are configured for low idle polarity. As seen in
the figure, the number written to the repeat registers determine the number of pulses generated on each of the outputs.
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UFO/w = 10
UFOAl = 10
Elm = 2 EP0 = 2
EP1=7 EPD=3 EP1=3
START START START
LETn_O0
LETn_O1
UFOA0 = 10
UFOA1 = 10
REP0 = 2
REP1 = 7
START
REP0 = 3
START
REP0 = 2
REP1 = 3
START
Figure 23.8. LETIMER Dual Output
23.3.5 PRS Output
The LETIMER outputs can be routed out onto the PRS system. LETn_O0 can be routed to PRS channel 0, and LETn_1O can be rout-
ed to PRS channel 1. Enabling the RRS connection can be done by setting SOURCESEL to LETIMERx and SIGSEL to LETIMERxCHn
in PRS_CHx_CTRL. The PRS register description can be found in 13. PRS - Peripheral Reflex System.
23.3.6 Examples
This section presents a couple of usage examples for the LETIMER.
23.3.6.1 Triggered Output Generation
If both LETIMERn_CNT and LETIMERn_REP0 are 0 in buffered mode, and COMP0TOP and BUFTOP in LETIMERn_CTRL are set,
the values of LETIMERn_COMP1 and LETIMERn_REP1 are loaded into LETIMERn_CNT and LETIMERn_REP0 respectively when
the timer is started. If no additional writes to LETIMERn_REP1 are done before the timer stops, LETIMERn_REP1 determines the num-
ber of pulses/ toggles generated on the output, and LETIMERn_COMP1 determines the period lengths.
As the RTC can be used to start the LETIMER, the RTC and LETIMER can thus be combined to generate specific pulse-trains at given
intervals. Software can update LETIMERn_COMP1 and LETIMERn_REP1 to change the number of pulses and pulse-period in each
train, but if changes are not required, software does not have to update the registers between each pulse train.
For the example in the following figure, the initial values cause the LETIMER to generate two pulses with 3 cycle periods, or a single
pulse 3 cycles wide every time the LETIMER is started. After the output has been generated, the LETIMER stops, and is ready to be
triggered again.
CNT
TOP0
TOP1
REP0
REP1
2
X
0
0
2
2
2
2
2
2
2
1
2
2
2
0
2
2
2
2
1
2
2
1
1
2
2
0
1
2
2
2
2
2
2
1
2
2
2
0
2
2
2
2
1
2
2
1
1
2
2
0
1
Initial configuration,
REP1 just written
UFIF
REP0IF
UFIF UFIF UFIF
REP0IF
Int. flags set
LFACLKLETIMERn
2u2u2u
Stop
Write START=1
2
2
0
0
2u
Stop
2
2
2
2
2
2
1
2
2
2
0
2
UFIF
Write START=1
2
2
0
0
2u
LETn_O0
UFOA0 = 01
LETn_O1
UFOA0 = 10
2u2u2u2u2u2u2u2u2u2u2u2u
2
2
0
0
2u
2
2
0
0
2u
2
2
0
0
2u
2
2
0
0
2u
2
2
0
0
2u
2
2
0
0
2u
Figure 23.9. LETIMER Triggered Operation
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23.3.6.2 Continuous Output Generation
In some scenarios, it might be desired to make LETIMER generate a continuous waveform. Very simple constant waveforms can be
generated without the repeat counter as shown in Figure 23.6 LETIMER Simple Waveforms Output on page 755, but to generate
changing waveforms, using the repeat counter and buffer registers can prove advantageous.
For the example in the following figure, the goal is to produce a pulse train consisting of 3 sequences with the following properties:
• 3 pulses with periods of 3 cycles
• 4 pulses with periods of 2 cycles
• 2 pulses with periods of 3 cycles
CNT
COMP0
COMP1
REP0
REP1
1
2
0
3
1
2
2
3
1
2
1
3
1
2
0
3
1
2
2
2
1
2
1
2
1
2
0
2
1
2
2
1
1
2
1
1
1
2
0
1
1
1
1
4
1
1
0
4
1
1
1
3
2
1
0
3
2
1
1
2
2
1
0
2
2
1
1
1
2
1
0
1
2
2
2
2
2
2
1
2
2
2
0
2
2
2
2
1
Initial configuration,
REPB just written
UFIF
REP0IF
UFIF UFIF UFIF UFIF
Int. flags set
Stop,
final values
Write
COMP1 = 2
REP1 = 2
UFIF UFIF UFIF
REP0IF
4444 4u4u4u22 2u2u2u2u
2
2
1
1
2
2
0
1
2u2u
REP0IF
LFACLKLETIMERn
LETn_O0
UFOA0 = 01
LETn_O1
UFOA0 = 10
Pulse Seq. 1 Pulse Seq. 2 Pulse Seq. 3
444444 2 2 2
2
2
0
0
2u
Figure 23.10. LETIMER Continuous Operation
The first two sequences are loaded into the LETIMER before the timer is started.
LETIMERn_COMP0 is set to 2 (cycles – 1), and LETIMERn_REP0 is set to 3 for the first sequence, and the second sequence is loaded
into the buffer registers, i.e. COMP1 is set to 1 and LETIMERn_REP1 is set to 4.
The LETIMER is set to trigger an interrupt when LETIMERn_REP0 is done by setting REP0 in LETIMERn_IEN. This interrupt is a good
place to update the values of the buffers. Last but not least REPMODE in LETIMERn_CTRL is set to buffered mode, and the timer is
started.
In the interrupt routine the buffers are updated with the values for the third sequence. If this had not been done, the timer would have
stopped after the second sequence.
The final result is shown in the previous figure. The pulse output is grouped to show which sequence generated which output. Toggle
output is also shown in the figure. Note that the toggle output is not aligned with the pulse outputs.
Note: Multiple LETIMER cycles are required to write a value to the LETIMER registers. The example in the previous figure assumes
that writes are done in advance so they arrive in the LETIMER as described in the figure.
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The following figure shows an example where the LETIMER is started while LETIMERn_CNT is nonzero. In this case the length of the
first repetition is given by the value in LETIMERn_CNT.
Figure 23.11. LETIMER LETIMERn_CNT Not Initialized to 0
CNT
TOP0
TOP1
REP0
REP1
3
2
4
3
3
3
2
3
3
3
2
2
3
3
2
1
3
3
2
0
3
3
2
2
2
3
2
1
2
3
2
0
2
3
2
2
1
3
2
1
1
3
2
0
1
3
3
3
3
3
3
2
3
3
3
1
3
3
3
0
3
3
3
3
2
3
3
2
2
3
3
1
2
3
3
0
2
3
3
3
1
3
3
2
1
3
3
1
1
3
3
0
Initial configuration,
REP1 just written
UFIF
REP0IF
UFIF UFIF UFIF UFIF UFIF
REP0IF
Int. flags set
Stop,
final values
LFACLKLETIMERn
LETn_O0
UFOA0 = 01
LETn_O1
UFOA0 = 10
3 3 3 3 3 3 3 3u3u3u3u3u3u3u
3 3 3 3u3u3u
1
3u
3u
3
3
0
0
3u
23.3.6.3 PWM Output
There are several ways of generating PWM output with the LETIMER, but the most straight-forward way is using the PWM output
mode. This mode is enabled by setting UFOA0 or OFUA1 in LETIMERn_CTRL to 3. In PWM mode, the output is set idle on timer un-
derflow, and active on LETIMERn_COMP1 match, so if for instance COMP0TOP = 1 and OPOL0 = 0 in LETIMERn_CTRL, LETI-
MERn_COMP0 determines the PWM period, and LETIMERn_LETIMERn_COMP1 determines the active period.
The PWM period in PWM mode is LETIMERn_COMP0 + 1. There is no special handling of the case where LETIMERn_COMP1 > LE-
TIMERn_COMP0, so if LETIMERn_COMP1 > LETIMERn_COMP0, the PWM output is given by the idle output value. This means that
for OPOLx = 0 in LETIMERn_CTRL, the PWM output will always be 0 for at least one clock cycle, and for OPOLx = 1 LETI-
MERn_CTRL, the PWM output will always be 1 for at least one clock cycle.
To generate a PWM signal using the full PWM range, invert OPOLx when LETIMERn_COMP1 is set to a value larger than LETI-
MERn_COMP0.
23.3.6.4 Interrupts
The interrupts generated by the LETIMER are combined into one interrupt vector. If the interrupt for the LETIMER is enabled, an inter-
rupt will be made if one or more of the interrupt flags in LETIMERn_IF and their corresponding bits in LETIMER_IEN are set.
23.3.7 Using the LETIMER in EM3
The LETIMER can be enabled all the way down to EM3 by using the ULFRCO as clock source. This is done by clearing
CMU_LFCLKSEL_LFA and setting CMU_LFCLKSEL_LFAE to 1. This will make the RTC use the internal 1 kHz ultra low frequency RC
oscillator (ULFRCO), consuming very little energy. Please note that the ULFRCO is not accurate over temperature and voltage, and it
should be verified that the ULFRCO fulfills the timekeeping needs of the application before using this in the design.
23.3.8 Register Access
This module is a Low Energy Peripheral, and supports immediate synchronization. For description regarding immediate synchroniza-
tion, refer to 5.2.4.1.1 Writing.
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23.4 Register Map
The offset register address is relative to the registers base address.
Offset Name Type Description
0x000 LETIMERn_CTRL RW Control Register
0x004 LETIMERn_CMD W1 Command Register
0x008 LETIMERn_STATUS RStatus Register
0x00C LETIMERn_CNT RWH Counter Value Register
0x010 LETIMERn_COMP0 RW Compare Value Register 0
0x014 LETIMERn_COMP1 RW Compare Value Register 1
0x018 LETIMERn_REP0 RW Repeat Counter Register 0
0x01C LETIMERn_REP1 RW Repeat Counter Register 1
0x020 LETIMERn_IF RInterrupt Flag Register
0x024 LETIMERn_IFS W1 Interrupt Flag Set Register
0x028 LETIMERn_IFC (R)W1 Interrupt Flag Clear Register
0x02C LETIMERn_IEN RW Interrupt Enable Register
0x030 LETIMERn_FREEZE RW Freeze Register
0x034 LETIMERn_SYNCBUSY RSynchronization Busy Register
0x040 LETIMERn_ROUTE RW I/O Routing Register
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23.5 Register Description
23.5.1 LETIMERn_CTRL - Control Register (Async Reg)
For more information about Asynchronous Registers, see 5.2.4 Access to Low Energy Peripherals (Asynchronous Registers).
Offset Bit Position
0x000
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
16
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
Reset
0
0
0
0
0
0
0
0x0
0x0
0x0
Access
RW
RW
RW
RW
RW
RW
RW
RW
RW
RW
Name
DEBUGRUN
RTCC1TEN
RTCC0TEN
COMP0TOP
BUFTOP
OPOL1
OPOL0
UFOA1
UFOA0
REPMODE
Bit Name Reset Access Description
31:13 Reserved To ensure compatibility with future devices, always write bits to 0. More information in 2.1 Conven-
tions.
12 DEBUGRUN 0 RW Debug Mode Run Enable
Set to keep the LETIMER running in debug mode.
Value Description
0 LETIMER is frozen in debug mode
1 LETIMER is running in debug mode
11 RTCC1TEN 0 RW RTC Compare 1 Trigger Enable
Allows the LETIMER to be started on a compare match on RTC compare channel 1.
Value Description
0 LETIMER is not affected by RTC compare channel 1
1 A compare match on RTC compare channel 1 starts the LETIMER if
the LETIMER is not already started
10 RTCC0TEN 0 RW RTC Compare 0 Trigger Enable
Allows the LETIMER to be started on a compare match on RTC compare channel 0.
Value Description
0 LETIMER is not affected by RTC compare channel 0
1 A compare match on RTC compare channel 0 starts the LETIMER if
the LETIMER is not already started
9 COMP0TOP 0 RW Compare Value 0 Is Top Value
When set, the counter is cleared in the clock cycle after a compare match with compare channel 0.
Value Description
0 The top value of the LETIMER is 65535 (0xFFFF)
1 The top value of the LETIMER is given by COMP0
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Bit Name Reset Access Description
8 BUFTOP 0 RW Buffered Top
Set to load COMP1 into COMP0 when REP0 reaches 0, allowing a buffered top value
Value Description
0 COMP0 is only written by software
1 COMP0 is set to COMP1 when REP0 reaches 0
7 OPOL1 0 RW Output 1 Polarity
Defines the idle value of output 1.
6 OPOL0 0 RW Output 0 Polarity
Defines the idle value of output 0.
5:4 UFOA1 0x0 RW Underflow Output Action 1
Defines the action on LETn_O1 on a LETIMER underflow.
Value Mode Description
0 NONE LETn_O1 is held at its idle value as defined by OPOL1.
1 TOGGLE LETn_O1 is toggled on CNT underflow.
2 PULSE LETn_O1 is held active for one LFACLKLETIMER0 clock cycle on CNT
underflow. The output then returns to its idle value as defined by
OPOL1.
3 PWM LETn_O1 is set idle on CNT underflow, and active on compare match
with COMP1
3:2 UFOA0 0x0 RW Underflow Output Action 0
Defines the action on LETn_O0 on a LETIMER underflow.
Value Mode Description
0 NONE LETn_O0 is held at its idle value as defined by OPOL0.
1 TOGGLE LETn_O0 is toggled on CNT underflow.
2 PULSE LETn_O0 is held active for one LFACLKLETIMER0 clock cycle on CNT
underflow. The output then returns to its idle value as defined by
OPOL0.
3 PWM LETn_O0 is set idle on CNT underflow, and active on compare match
with COMP1
1:0 REPMODE 0x0 RW Repeat Mode
Allows the repeat counter to be enabled and disabled.
Value Mode Description
0 FREE When started, the LETIMER counts down until it is stopped by soft-
ware.
1 ONESHOT The counter counts REP0 times. When REP0 reaches zero, the coun-
ter stops.
2 BUFFERED The counter counts REP0 times. If REP1 has been written, it is loaded
into REP0 when REP0 reaches zero. Else the counter stops
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Bit Name Reset Access Description
3 DOUBLE Both REP0 and REP1 are decremented when the LETIMER wraps
around. The LETIMER counts until both REP0 and REP1 are zero
23.5.2 LETIMERn_CMD - Command Register
Offset Bit Position
0x004
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
16
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
Reset
0
0
0
0
0
Access
W1
W1
W1
W1
W1
Name
CTO1
CTO0
CLEAR
STOP
START
Bit Name Reset Access Description
31:5 Reserved To ensure compatibility with future devices, always write bits to 0. More information in 2.1 Conven-
tions.
4 CTO1 0 W1 Clear Toggle Output 1
Set to drive toggle output 1 to its idle value
3 CTO0 0 W1 Clear Toggle Output 0
Set to drive toggle output 0 to its idle value
2 CLEAR 0 W1 Clear LETIMER
Set to clear LETIMER
1 STOP 0 W1 Stop LETIMER
Set to stop LETIMER
0 START 0 W1 Start LETIMER
Set to start LETIMER
23.5.3 LETIMERn_STATUS - Status Register
Offset Bit Position
0x008
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
16
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
Reset
0
Access
R
Name
RUNNING
Bit Name Reset Access Description
31:1 Reserved To ensure compatibility with future devices, always write bits to 0. More information in 2.1 Conven-
tions.
0 RUNNING 0 R LETIMER Running
Set when LETIMER is running.
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23.5.4 LETIMERn_CNT - Counter Value Register
Offset Bit Position
0x00C
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
16
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
Reset
0x0000
Access
RWH
Name
CNT
Bit Name Reset Access Description
31:16 Reserved To ensure compatibility with future devices, always write bits to 0. More information in 2.1 Conven-
tions.
15:0 CNT 0x0000 RWH Counter Value
Use to read the current value of the LETIMER.
23.5.5 LETIMERn_COMP0 - Compare Value Register 0 (Async Reg)
For more information about Asynchronous Registers, see 5.2.4 Access to Low Energy Peripherals (Asynchronous Registers).
Offset Bit Position
0x010
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
16
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
Reset
0x0000
Access
RW
Name
COMP0
Bit Name Reset Access Description
31:16 Reserved To ensure compatibility with future devices, always write bits to 0. More information in 2.1 Conven-
tions.
15:0 COMP0 0x0000 RW Compare Value 0
Compare and optionally top value for LETIMER
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23.5.6 LETIMERn_COMP1 - Compare Value Register 1 (Async Reg)
For more information about Asynchronous Registers, see 5.2.4 Access to Low Energy Peripherals (Asynchronous Registers).
Offset Bit Position
0x014
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
16
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
Reset
0x0000
Access
RW
Name
COMP1
Bit Name Reset Access Description
31:16 Reserved To ensure compatibility with future devices, always write bits to 0. More information in 2.1 Conven-
tions.
15:0 COMP1 0x0000 RW Compare Value 1
Compare and optionally buffered top value for LETIMER
23.5.7 LETIMERn_REP0 - Repeat Counter Register 0 (Async Reg)
For more information about Asynchronous Registers, see 5.2.4 Access to Low Energy Peripherals (Asynchronous Registers).
Offset Bit Position
0x018
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
16
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
Reset
0x00
Access
RW
Name
REP0
Bit Name Reset Access Description
31:8 Reserved To ensure compatibility with future devices, always write bits to 0. More information in 2.1 Conven-
tions.
7:0 REP0 0x00 RW Repeat Counter 0
Optional repeat counter.
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23.5.8 LETIMERn_REP1 - Repeat Counter Register 1 (Async Reg)
For more information about Asynchronous Registers, see 5.2.4 Access to Low Energy Peripherals (Asynchronous Registers).
Offset Bit Position
0x01C
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
16
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
Reset
0x00
Access
RW
Name
REP1
Bit Name Reset Access Description
31:8 Reserved To ensure compatibility with future devices, always write bits to 0. More information in 2.1 Conven-
tions.
7:0 REP1 0x00 RW Repeat Counter 1
Optional repeat counter or buffer for REP0
23.5.9 LETIMERn_IF - Interrupt Flag Register
Offset Bit Position
0x020
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
16
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
Reset
0
0
0
0
0
Access
R
R
R
R
R
Name
REP1
REP0
UF
COMP1
COMP0
Bit Name Reset Access Description
31:5 Reserved To ensure compatibility with future devices, always write bits to 0. More information in 2.1 Conven-
tions.
4 REP1 0 R Repeat Counter 1 Interrupt Flag
Set when repeat counter 1 reaches zero.
3 REP0 0 R Repeat Counter 0 Interrupt Flag
Set when repeat counter 0 reaches zero or when the REP1 interrupt flag is loaded into the REP0 interrupt flag.
2 UF 0 R Underflow Interrupt Flag
Set on LETIMER underflow.
1 COMP1 0 R Compare Match 1 Interrupt Flag
Set when LETIMER reaches the value of COMP1
0 COMP0 0 R Compare Match 0 Interrupt Flag
Set when LETIMER reaches the value of COMP0
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23.5.10 LETIMERn_IFS - Interrupt Flag Set Register
Offset Bit Position
0x024
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
16
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
Reset
0
0
0
0
0
Access
W1
W1
W1
W1
W1
Name
REP1
REP0
UF
COMP1
COMP0
Bit Name Reset Access Description
31:5 Reserved To ensure compatibility with future devices, always write bits to 0. More information in 2.1 Conven-
tions.
4 REP1 0 W1 Set Repeat Counter 1 Interrupt Flag
Write to 1 to set the REP1 interrupt flag.
3 REP0 0 W1 Set Repeat Counter 0 Interrupt Flag
Write to 1 to set the REP0 interrupt flag.
2 UF 0 W1 Set Underflow Interrupt Flag
Write to 1 to set the UF interrupt flag.
1 COMP1 0 W1 Set Compare Match 1 Interrupt Flag
Write to 1 to set the COMP1 interrupt flag.
0 COMP0 0 W1 Set Compare Match 0 Interrupt Flag
Write to 1 to set the COMP0 interrupt flag.
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23.5.11 LETIMERn_IFC - Interrupt Flag Clear Register
Offset Bit Position
0x028
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
16
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
Reset
0
0
0
0
0
Access
(R)W1
(R)W1
(R)W1
(R)W1
(R)W1
Name
REP1
REP0
UF
COMP1
COMP0
Bit Name Reset Access Description
31:5 Reserved To ensure compatibility with future devices, always write bits to 0. More information in 2.1 Conven-
tions.
4 REP1 0 (R)W1 Clear Repeat Counter 1 Interrupt Flag
Write to 1 to clear the REP1 interrupt flag.
3 REP0 0 (R)W1 Clear Repeat Counter 0 Interrupt Flag
Write to 1 to clear the REP0 interrupt flag.
2 UF 0 (R)W1 Clear Underflow Interrupt Flag
Write to 1 to clear the UF interrupt flag.
1 COMP1 0 (R)W1 Clear Compare Match 1 Interrupt Flag
Write to 1 to clear the COMP1 interrupt flag.
0 COMP0 0 (R)W1 Clear Compare Match 0 Interrupt Flag
Write to 1 to clear the COMP0 interrupt flag.
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23.5.12 LETIMERn_IEN - Interrupt Enable Register
Offset Bit Position
0x02C
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
16
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
Reset
0
0
0
0
0
Access
RW
RW
RW
RW
RW
Name
REP1
REP0
UF
COMP1
COMP0
Bit Name Reset Access Description
31:5 Reserved To ensure compatibility with future devices, always write bits to 0. More information in 2.1 Conven-
tions.
4 REP1 0 RW Repeat Counter 1 Interrupt Enable
Set to enable interrupt on the REP1 interrupt flag.
3 REP0 0 RW Repeat Counter 0 Interrupt Enable
Set to enable interrupt on the REP0 interrupt flag.
2 UF 0 RW Underflow Interrupt Enable
Set to enable interrupt on the UF interrupt flag.
1 COMP1 0 RW Compare Match 1 Interrupt Enable
Set to enable interrupt on the COMP1 interrupt flag.
0 COMP0 0 RW Compare Match 0 Interrupt Enable
Set to enable interrupt on the COMP0 interrupt flag.
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23.5.13 LETIMERn_FREEZE - Freeze Register
Offset Bit Position
0x030
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
16
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
Reset
0
Access
RW
Name
REGFREEZE
Bit Name Reset Access Description
31:1 Reserved To ensure compatibility with future devices, always write bits to 0. More information in 2.1 Conven-
tions.
0 REGFREEZE 0 RW Register Update Freeze
With the immediate write synchronization scheme the REGFREEZE register is no longer used.
Value Mode Description
0 UPDATE Each write access to a LETIMER register is updated into the Low Fre-
quency domain as soon as possible.
1 FREEZE The LETIMER is not updated with the new written value.
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23.5.14 LETIMERn_SYNCBUSY - Synchronization Busy Register
Offset Bit Position
0x034
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
16
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
Reset
0
0
0
0
0
0
Access
R
R
R
R
R
R
Name
REP1
REP0
COMP1
COMP0
CMD
CTRL
Bit Name Reset Access Description
31:6 Reserved To ensure compatibility with future devices, always write bits to 0. More information in 2.1 Conven-
tions.
5 REP1 0 R REP1 Register Busy
Set when the value written to REP1 is being synchronized.
4 REP0 0 R REP0 Register Busy
Set when the value written to REP0 is being synchronized.
3 COMP1 0 R COMP1 Register Busy
Set when the value written to COMP1 is being synchronized.
2 COMP0 0 R COMP0 Register Busy
Set when the value written to COMP0 is being synchronized.
1 CMD 0 R CMD Register Busy
Set when the value written to CMD is being synchronized.
0 CTRL 0 R CTRL Register Busy
Set when the value written to CTRL is being synchronized.
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23.5.15 LETIMERn_ROUTE - I/O Routing Register
Offset Bit Position
0x040
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
16
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
Reset
0x0
0
0
Access
RW
RW
RW
Name
LOCATION
OUT1PEN
OUT0PEN
Bit Name Reset Access Description
31:11 Reserved To ensure compatibility with future devices, always write bits to 0. More information in 2.1 Conven-
tions.
10:8 LOCATION 0x0 RW I/O Location
Decides the location of the LETIMER I/O pins
Value Mode Description
0 LOC0 Location 0
1 LOC1 Location 1
2 LOC2 Location 2
3 LOC3 Location 3
7:2 Reserved To ensure compatibility with future devices, always write bits to 0. More information in 2.1 Conven-
tions.
1 OUT1PEN 0 RW Output 1 Pin Enable
When set, output 1 of the LETIMER is enabled
Value Description
0 The LETn_O1 pin is disabled
1 The LETn_O1 pin is enabled
0 OUT0PEN 0 RW Output 0 Pin Enable
When set, output 0 of the LETIMER is enabled
Value Description
0 The LETn_O0 pin is disabled
1 The LETn_O0 pin is enabled
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24. PCNT - Pulse Counter
43210
Reload value
Interrupt
Quadrature code
0
Quick Facts
What?
The Pulse Counter (PCNT) decodes incoming pul-
ses. The module has a quadrature mode which may
be used to decode the speed and direction of a me-
chanical shaft. PCNT can operate in EM0- EM3.
Why?
The PCNT generates an interrupt after a specific
number of pulses (or rotations), eliminating the need
for timing- or I/O interrupts and CPU processing to
measure pulse widths, etc.
How?
PCNT uses the LFACLK or may be externally
clocked from a pin. The module incorporates an
8/16-bit up/down-counter to keep track of incoming
pulses or rotations.
24.1 Introduction
The Pulse Counter (PCNT) can be used for counting incoming pulses on a single input or to decode quadrature encoded inputs. It can
run from the internal LFACLK (EM0-EM2) while counting pulses on the PCNTn_S0IN pin or using this pin as an external clock source
(EM0-EM3) that runs both the PCNT counter and register access.
24.2 Features
• 16/8-bit counter with reload register
• Auxiliary counter for counting a single direction
• Single input oversampling up/down counter mode (EM0-EM2)
• Externally clocked single input pulse up/down counter mode (EM0-EM3)
• Externally clocked quadrature decoder mode (EM0-EM3)
• Interrupt on counter underflow and overflow
• Interrupt when a direction change is detected (quadrature decoder mode only)
• Optional pulse width filter
• Optional input inversion/edge detect select
• PRS S0IN and S1IN input
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24.3 Functional Description
An overview of the PCNT module is shown in the following figure.
Peripheral bus
CNT
PCNTn_S0IN
Pulse
Width
Filter
Inverter
PCNTn_S1IN
Inverter
Count
Enable
1
LFACLK
CMU (conseptual)
TOPB
Quadrature
decoder
Edge
detector
OVR_SINGLE
EXTCLK_SINGLE
EXTCLK_QUAD
TOP
S0PRS Input
S1PRS Input
CLKPCNT
Clock
switch
Analog de-glitch filter
Figure 24.1. PCNT Overview
24.3.1 Pulse Counter Modes
The pulse counter can operate in single input oversampling mode (OVSSINGLE), externally clocked single input counter mode (EX-
TCLKSINGLE) and externally clocked quadrature decoder mode (EXTCLKQUAD). The following sections describe operation of each of
the three modes and how they are enabled. Input timing constraints are described in 24.3.5 Clock Sources and 24.3.6 Input Filter.
24.3.1.1 Single Input Oversampling Mode
This mode is enabled by writing OVSSINGLE to the MODE field in the PCNTn_CTRL register and disabled by writing DISABLE to the
same field. LFACLK is configured from the registers in 11. CMU - Clock Management Unit .
The optional pulse width filter is enabled by setting the FILT bit in the PCNTn_CTRL register. Additionally, the PCNTn_S0IN input may
be inverted, so that falling edges are counted, by setting the EDGE bit in the PCNTn_CTRL register.
If S1CDIR is cleared, PCNTn_S0IN is the only observed input in this mode. The PCNTn_S0IN input is sampled by the LFACLK and the
number of detected positive or negative edges on PCNTn_S0IN appears in PCNTn_CNT. The counter may be configured to count
down by setting the CNTDIR bit in PCNTn_CTRL. Default is to count up.
The counting direction can also be controlled externally in this mode by setting S1CDIR in PCNTn_CTRL. This will make the input value
on PCNTn_S1IN decide the direction counted on a PCNTn_S0IN edge. If PCNTn_S1IN is high, the count is done according to CNTDIR
in PCNTn_CTRL. If low, the count direction is opposite.
24.3.1.2 Externally Clocked Single Input Counter Mode
This mode is enabled by writing EXTCLKSINGLE to the MODE field in the PCNTn_CTRL register and disabled by writing DISABLE to
the same field. The external pin clock source must be configured from the registers in 11. CMU - Clock Management Unit.
Positive edges on PCNTn_S0IN are used to clock the counter. Similar to the oversampled mode, PCNTn_S1IN is used to determine
the count direction if S1CDIR in PCNTn_CTRL is set. If not, CNTDIR in PCNTn_CTRL solely defines count direction. As the LFACLK is
not used in this mode, the PCNT module can operate in EM3.
The digital pulse width filter is not available in this mode. The analog de-glitch filter in the GPIO pads is capable of removing some
unwanted noise. However, this mode may be susceptible to spikes and unintended pulses from devices such as mechanical switches,
and is therefore most suited to take input from electronic sensors etc. that generate single wire pulses.
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24.3.1.3 Externally Clocked Quadrature Decoder Mode
This mode is enabled by writing EXTCLKQUAD to the MODE field in PCNTn_CTRL and disabled by writing DISABLE to the same field.
The external pin clock source must be configured from the registers in 11. CMU - Clock Management Unit.
Both edges on PCNTn_S0IN pin are used to sample PCNTn_S1IN pin to decode the quadrature code. Consequently, this mode does
not depend on the internal LFACLK and may be operated in EM3. A quadrature coded signal contains information about the relative
speed and direction of a rotating shaft as illustrated by the following figure, hence the direction of the counter register PCNTn_CNT is
controlled automatically.
X X
1 cycle/sector, 4 states
01 11 10
00
X X
1 cycle/sector, 4 states
00 10 11 01
X = sensor position
Clockwise direction
Counter clockwise
direction
PCNTn_S0IN
PCNTn_S1IN
PCNTn_S0IN
PCNTn_S1IN
PCNTn_CNT
Reset
0 0 12
PCNTn_CNT 0 0 PCNTn_TOP PCNTn_TOP-1
Figure 24.2. PCNT Quadrature Coding
If PCNTn_S0IN leads PCNTn_S1IN in phase, the direction is clockwise, and if it lags in phase the direction is counter-clockwise. Al-
though the direction is automatically detected, the detected direction may be inverted by writing 1 to the EDGE bit in the PCNTn_CTRL
register. Default behavior is illustrated by the previous figure.
The counter direction may be read from the DIR bit in the PCNTn_STATUS register. Additionally, the DIRCNG interrupt in the
PCNTn_IF register is generated when a direction change is detected. When a change is detected, the DIR bit in the PCNTn_STATUS
register must be read to determine the current new direction.
Note: The sector disc illustrated in the figure may be finer grained in some systems. Typically, they may generate 2-4 PCNTn_S0IN
wave periods per 360° rotation.
The direction of the quadrature code and control of the counter is generated by the simple binary function outlined by the following
table. Note that this function also filters some invalid inputs that may occur when the shaft changes direction or temporarily toggles
direction.
Table 24.1. PCNT QUAD Mode Counter Control Function
Inputs Control/Status
S1IN posedge S1IN negedge Count Enable CNTDIR status bit
0 0 0 0
0 1 1 0
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Inputs Control/Status
S1IN posedge S1IN negedge Count Enable CNTDIR status bit
1 0 1 1
1 1 0 0
Note: PCNTn_S1IN is sampled on both edges of PCNTn_S0IN.
24.3.2 Hysteresis
By default the pulse counter wraps to 0 when passing the configured top value, and wraps to the top value when counting down from 0.
On these events, a system will likely want to wake up to store and track the overflow count. This is fine if the pulse counter is tracking a
monotonic value or a value that does not change directions frequently. If you have the latter however, and the counter changes direc-
tions around the overflow/underflow point, the system will have to wake up a lot to keep track of the rotations, causing high current
consumptions
To solve this, the pulse counter has a way of introducing hysteresis to the counter. When HYST in PCNTn_CTRL is set, the pulse coun-
ter will always wrap to TOP/2 on underflows and overflows. This takes the counter away from the area where it might overflow or under-
flow, removing the problem.
Given a starting value of 0 for the counter, the absolute count value when hysteresis is enabled can be calculated with the following
equations, depending on whether the TOP value is even or odd.
Absolute position with hysteresis and even TOP value
CNTabs = CNT - UFCNT ×(TOP
2+ 1)+ OFCNT ×(TOP
2+ 1)
Absolute position with hysteresis and odd TOP value
CNTabs = CNT - UFCNT ×(TOP
2+ 1)+ OFCNT ×(TOP
2+ 2)
24.3.3 Auxiliary Counter
To be able to keep explicit track of counting in one direction in addition to the regular counter which counts both up and down, the
auxiliary counter can be used. The pulse counter can for instance be configured to keep track of the absolute rotation of the wheel, and
at the same time the auxiliary counter can keep track of how much the wheel has reversed.
The auxiliary counter is enabled by configuring AUXCNTEV in PCNTn_CTRL. It will always count up, but it can be configured whether it
should count up on up-events, down-events or both, keeping track of rotation either way or general movement. The value of the auxili-
ary counter can be read from the PCNTn_AUXCNT register.
Overflows on the auxiliary counter happen when the auxiliary counter passes the top value of the pulse counter, configured in
PCNTn_TOP. In that event, the AUXOF interrupt flag is set, and the auxiliary counter wraps to 0.
As the auxiliary counter, the main counter can be configured to count only on certain events. This is done through CNTEV in
PCNTn_CTRL, and it is possible like for the auxiliary counter, to make the main counter count on only up and down events. The differ-
ence between the counters is that where the auxiliary counter will only count up, the main counter will count up or down depending on
the direction of the count event.
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24.3.4 Register Access
The counter-clock domain may be clocked externally. To update the counter-clock domain registers from software in this mode, 2-3
clock pulses on the external clock are needed to synchronize accesses to the externally clocked domain. Clock source switching is
controlled from the registers in 11. CMU - Clock Management Unit.
When the RSTEN bit in the PCNTn_CTRL register is set to 1, the PCNT clock domain is asynchronously held in reset. The reset is
synchronously released two PCNT clock edges after the RSTEN bit in the PCNTn_CTRL register is cleared by software. This asynchro-
nous reset restores the reset values in PCNTn_TOP, PCNTn_CNT and other control registers in the PCNT clock domain.
Since this module is a Low Energy Peripheral, and runs off a clock which is asynchronous to the HFCORECLK, special considerations
must be taken when accessing registers. Please refer to 5.2.4 Access to Low Energy Peripherals (Asynchronous Registers) for a de-
scription on how to perform register accesses to Low Energy Peripherals.
Note: PCNTn_TOP and PCNTn_CNT are read-only registers. When writing to PCNTn_TOPB, make sure that the counter value,
PCNTn_CNT, can not exceed the value written to PCNTn_TOPB within two clock cycles.
24.3.5 Clock Sources
The 32 kHz LFACLK is one of two possible clock sources. The clock select register is described in 11. CMU - Clock Management Unit.
The default clock source is the LFACLK.
This PCNT module may also use PCNTn_S0IN as an external clock to clock the counter (EXTCLKSINGLE mode) and to sample
PCNTn_S1IN (EXTCLKQUAD mode). Setup, hold and max frequency constraints for PCNTn_S0IN and PCNTn_S1IN for these modes
are specified in the device datasheet.
To use this module, the LE interface clock must be enabled in CMU_HFCORECLKEN0, in addition to the module clock.
Note: PCNT Clock Domain Reset, RSTEN, should be set when changing clock source for PCNT. If changing to an external clock
source, the clock pin has to be enabled as input prior to deasserting RSTEN. Changing clock source without asserting RSTEN results
in undefined behaviour.
24.3.6 Input Filter
An optional pulse width filter is available in OVSSINGLE mode. The filter is enabled by writing 1 to the FILT bit in the PCNTn_CTRL
register. When enabled, the high and low periods of PCNTn_S0IN must be stable for 5 consecutive clock cycles before the edge is
passed to the edge detector.
In EXTCLKSINGLE and EXTCLKQUAD mode, there is no digital pulse width filter available.
24.3.7 Edge Polarity
The edge polarity can be set by configuring the EDGE bit in the PCNTn_CTRL register. When this bit is cleared, the pulse counter
counts positive edges in OVSSINGLE mode and negative edges if the bit is set.
In EXTCLKQUAD mode, the EDGE bit in PCNTn_CTRL inverts the direction of the counter (which is automatically detected).
Note: The EDGE bit in PCNTn_CTRL has no effect in EXTCLKSINGLE mode.
24.3.8 PRS S0IN and S1IN Input
It is possible to receive input from PRS on both SOIN and S1IN by setting S0PRSEN or S1PRSEN in PCNTn_INPUT. The PRS chan-
nel used can be selected using S0PRSSEL in PCNTn_INPUT.
24.3.9 Interrupts
The interrupt generated by PCNT uses the PCNTn_INT interrupt vector. Software must read the PCNTn_IF register to determine which
module interrupt that generated the vector invocation.
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24.3.9.1 Underflow and Overflow Interrupts
The underflow interrupt flag (UF) is set when the counter counts down from 0. I.e. when the value of the counter is 0 and a new pulse is
received. The PCNTn_CNT register is loaded with the PCNTn_TOP value after this event.
The overflow interrupt flag (OF) is set when the counter counts up from the PCNTn_TOP (reload) value. I.e. if PCNTn_CNT =
PCNTn_TOP and a new pulse is received. The PCNTn_CNT register is loaded with the value 0 after this event.
24.3.9.2 Direction Change Interrupt
The PCNTn_PCNT module sets the DIRCNG interrupt flag (PCNTn_IF register) when the direction of the quadrature code changes.
The behavior of this interrupt is illustrated by the following figure.
Standard async
handshake
interface
PCNTn_S0IN
PCNTn_S1IN
Interrupt
X X
Invalid pulse generated when
the shaft changes direction
n+1 n+2 n+3 n+2
PCNTn_CNT n
Delay from the shaft physically
changed direction until the
counter direction is changed
and the interrupt is generated
Figure 24.3. PCNT Direction Change Interrupt (DIRCNG) Generation
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24.4 Register Map
The offset register address is relative to the registers base address.
Offset Name Type Description
0x000 PCNTn_CTRL RW Control Register
0x004 PCNTn_CMD W1 Command Register
0x008 PCNTn_STATUS RStatus Register
0x00C PCNTn_CNT RCounter Value Register
0x010 PCNTn_TOP RTop Value Register
0x014 PCNTn_TOPB RW Top Value Buffer Register
0x018 PCNTn_IF RInterrupt Flag Register
0x01C PCNTn_IFS W1 Interrupt Flag Set Register
0x020 PCNTn_IFC (R)W1 Interrupt Flag Clear Register
0x024 PCNTn_IEN RW Interrupt Enable Register
0x028 PCNTn_ROUTE RW I/O Routing Register
0x02C PCNTn_FREEZE RW Freeze Register
0x030 PCNTn_SYNCBUSY RSynchronization Busy Register
0x038 PCNTn_AUXCNT RWH Auxiliary Counter Value Register
0x03C PCNTn_INPUT RW PCNT Input Register
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24.5 Register Description
24.5.1 PCNTn_CTRL - Control Register (Async Reg)
For more information about Asynchronous Registers, see 5.2.4 Access to Low Energy Peripherals (Asynchronous Registers).
Offset Bit Position
0x000
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
16
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
Reset
0x0
0x0
0
0
0
0
0
0
0x0
Access
RW
RW
RW
RW
RW
RW
RW
RW
RW
Name
AUXCNTEV
CNTEV
S1CDIR
HYST
RSTEN
FILT
EDGE
CNTDIR
MODE
Bit Name Reset Access Description
31:16 Reserved To ensure compatibility with future devices, always write bits to 0. More information in 2.1 Conven-
tions.
15:14 AUXCNTEV 0x0 RW Controls when the auxiliary counter counts
Selects whether the auxiliary counter responds to up-count events, down-count events or both
Value Mode Description
0 NONE Never counts.
1 UP Counts up on up-count events.
2 DOWN Counts up on down-count events.
3 BOTH Counts up on both up-count and down-count events.
13:12 Reserved To ensure compatibility with future devices, always write bits to 0. More information in 2.1 Conven-
tions.
11:10 CNTEV 0x0 RW Controls when the counter counts
Selects whether the regular counter responds to up-count events, down-count events or both
Value Mode Description
0 BOTH Counts up on up-count and down on down-count events.
1 UP Only counts up on up-count events.
2 DOWN Only counts down on down-count events.
3 NONE Never counts.
9 S1CDIR 0 RW Count direction determined by S1
S1 gives the direction of counting when in the OVSSINGLE or EXTCLKSINGLE modes. When S1 is high, the count direc-
tion is given by CNTDIR, and when S1 is low, the count direction is the opposite
8 HYST 0 RW Enable Hysteresis
When hysteresis is enabled, the PCNT will always overflow and underflow to TOP/2.
7:6 Reserved To ensure compatibility with future devices, always write bits to 0. More information in 2.1 Conven-
tions.
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Bit Name Reset Access Description
5 RSTEN 0 RW Enable PCNT Clock Domain Reset
The PCNT clock domain is asynchronously held in reset when this bit is set. The reset is synchronously released two PCNT
clock edges after this bit is cleared. If external clock used the reset should be performed by setting and clearing the bit
without pending for SYNCBUSY bit.
4 FILT 0 RW Enable Digital Pulse Width Filter
The filter passes all high and low periods that are at least 5 clock cycles long. This filter is only available in OVSSINGLE
mode.
3 EDGE 0 RW Edge Select
Determines the polarity of the incoming edges. This bit should be written when PCNT is in DISABLE mode, otherwise the
behavior is unpredictable. This bit is ignored in EXTCLKSINGLE mode.
Value Mode Description
0 POS Positive edges on the PCNTn_S0IN inputs are counted in OVSSINGLE
mode.
1 NEG Negative edges on the PCNTn_S0IN inputs are counted in OVSSIN-
GLE mode, and the counter direction is inverted in EXTCLKQUAD
mode.
2 CNTDIR 0 RW Non-Quadrature Mode Counter Direction Control
The direction of the counter must be set in the OVSSINGLE and EXTCLKSINGLE modes. This bit is ignored in EX-
TCLKQUAD mode as the direction is automatically detected.
Value Mode Description
0 UP Up counter mode.
1 DOWN Down counter mode.
1:0 MODE 0x0 RW Mode Select
Selects the mode of operation. The corresponding clock source must be selected from the CMU.
Value Mode Description
0 DISABLE The module is disabled.
1 OVSSINGLE Single input LFACLK oversampling mode (available in EM0-EM2).
2 EXTCLKSINGLE Externally clocked single input counter mode (available in EM0-EM3).
3 EXTCLKQUAD Externally clocked quadrature decoder mode (available in EM0-EM3).
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24.5.2 PCNTn_CMD - Command Register (Async Reg)
For more information about Asynchronous Registers, see 5.2.4 Access to Low Energy Peripherals (Asynchronous Registers).
Offset Bit Position
0x004
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
16
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
Reset
0
0
Access
W1
W1
Name
LTOPBIM
LCNTIM
Bit Name Reset Access Description
31:2 Reserved To ensure compatibility with future devices, always write bits to 0. More information in 2.1 Conven-
tions.
1 LTOPBIM 0 W1 Load TOPB Immediately
This bit has no effect since TOPB is not buffered and it is loaded directly into TOP.
0 LCNTIM 0 W1 Load CNT Immediately
Load PCNTn_TOP into PCNTn_CNT on the next counter clock cycle.
24.5.3 PCNTn_STATUS - Status Register
Offset Bit Position
0x008
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
16
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
Reset
0
Access
R
Name
DIR
Bit Name Reset Access Description
31:1 Reserved To ensure compatibility with future devices, always write bits to 0. More information in 2.1 Conven-
tions.
0 DIR 0 R Current Counter Direction
Current direction status of the counter. This bit is valid in EXTCLKQUAD mode only.
Value Mode Description
0 UP Up counter mode (clockwise in EXTCLKQUAD mode with the NEDGE
bit in PCNTn_CTRL set to 0).
1 DOWN Down counter mode.
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24.5.4 PCNTn_CNT - Counter Value Register
Offset Bit Position
0x00C
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
16
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
Reset
0x0000
Access
R
Name
CNT
Bit Name Reset Access Description
31:16 Reserved To ensure compatibility with future devices, always write bits to 0. More information in 2.1 Conven-
tions.
15:0 CNT 0x0000 R Counter Value
Gives read access to the counter.
24.5.5 PCNTn_TOP - Top Value Register
Offset Bit Position
0x010
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
16
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
Reset
0x00FF
Access
R
Name
TOP
Bit Name Reset Access Description
31:16 Reserved To ensure compatibility with future devices, always write bits to 0. More information in 2.1 Conven-
tions.
15:0 TOP 0x00FF R Counter Top Value
When counting down, this value is reloaded into PCNTn_CNT when counting past 0. When counting up, 0 is written to the
PCNTn_CNT register when counting past this value.
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24.5.6 PCNTn_TOPB - Top Value Buffer Register (Async Reg)
For more information about Asynchronous Registers, see 5.2.4 Access to Low Energy Peripherals (Asynchronous Registers).
Offset Bit Position
0x014
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
16
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
Reset
0x00FF
Access
RW
Name
TOPB
Bit Name Reset Access Description
31:16 Reserved To ensure compatibility with future devices, always write bits to 0. More information in 2.1 Conven-
tions.
15:0 TOPB 0x00FF RW Counter Top Buffer
Loaded automatically to TOP when written.
24.5.7 PCNTn_IF - Interrupt Flag Register
Offset Bit Position
0x018
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
16
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
Reset
0
0
0
0
Access
R
R
R
R
Name
AUXOF
DIRCNG
OF
UF
Bit Name Reset Access Description
31:4 Reserved To ensure compatibility with future devices, always write bits to 0. More information in 2.1 Conven-
tions.
3 AUXOF 0 R Overflow Interrupt Read Flag
Set when an Auxiliary CNT overflow occurs
2 DIRCNG 0 R Direction Change Detect Interrupt Flag
Set when the count direction changes. Set in EXTCLKQUAD mode only.
1 OF 0 R Overflow Interrupt Read Flag
Set when a CNT overflow occurs
0 UF 0 R Underflow Interrupt Read Flag
Set when a CNT underflow occurs
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24.5.8 PCNTn_IFS - Interrupt Flag Set Register
Offset Bit Position
0x01C
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
16
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
Reset
0
0
0
0
Access
W1
W1
W1
W1
Name
AUXOF
DIRCNG
OF
UF
Bit Name Reset Access Description
31:4 Reserved To ensure compatibility with future devices, always write bits to 0. More information in 2.1 Conven-
tions.
3 AUXOF 0 W1 Auxiliary Overflow Interrupt Set
Write to 1 to set the auxiliary overflow interrupt flag
2 DIRCNG 0 W1 Direction Change Detect Interrupt Set
Write to 1 to set the direction change interrupt flag
1 OF 0 W1 Overflow Interrupt Set
Write to 1 to set the overflow interrupt flag
0 UF 0 W1 Underflow interrupt set
Write to 1 to set the underflow interrupt flag
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24.5.9 PCNTn_IFC - Interrupt Flag Clear Register
Offset Bit Position
0x020
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
16
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
Reset
0
0
0
0
Access
(R)W1
(R)W1
(R)W1
(R)W1
Name
AUXOF
DIRCNG
OF
UF
Bit Name Reset Access Description
31:4 Reserved To ensure compatibility with future devices, always write bits to 0. More information in 2.1 Conven-
tions.
3 AUXOF 0 (R)W1 Auxiliary Overflow Interrupt Clear
Write to 1 to clear the auxiliary overflow interrupt flag
2 DIRCNG 0 (R)W1 Direction Change Detect Interrupt Clear
Write to 1 to clear the direction change detect interrupt flag
1 OF 0 (R)W1 Overflow Interrupt Clear
Write to 1 to clear the overflow interrupt flag
0 UF 0 (R)W1 Underflow Interrupt Clear
Write to 1 to clear the underflow interrupt flag
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24.5.10 PCNTn_IEN - Interrupt Enable Register
Offset Bit Position
0x024
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
16
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
Reset
0
0
0
0
Access
RW
RW
RW
RW
Name
AUXOF
DIRCNG
OF
UF
Bit Name Reset Access Description
31:4 Reserved To ensure compatibility with future devices, always write bits to 0. More information in 2.1 Conven-
tions.
3 AUXOF 0 RW Auxiliary Overflow Interrupt Enable
Enable the auxiliary overflow interrupt
2 DIRCNG 0 RW Direction Change Detect Interrupt Enable
Enable the direction change detect interrupt.
1 OF 0 RW Overflow Interrupt Enable
Enable the overflow interrupt
0 UF 0 RW Underflow Interrupt Enable
Enable the underflow interrupt
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24.5.11 PCNTn_ROUTE - I/O Routing Register
Offset Bit Position
0x028
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
16
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
Reset
0x0
Access
RW
Name
LOCATION
Bit Name Reset Access Description
31:11 Reserved To ensure compatibility with future devices, always write bits to 0. More information in 2.1 Conven-
tions.
10:8 LOCATION 0x0 RW I/O Location
Defines the location of the PCNT input pins. E.g. PCNTn_S0#0, #1 or #2.
Value Mode Description
0 LOC0 Location 0
1 LOC1 Location 1
2 LOC2 Location 2
3 LOC3 Location 3
7:0 Reserved To ensure compatibility with future devices, always write bits to 0. More information in 2.1 Conven-
tions.
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24.5.12 PCNTn_FREEZE - Freeze Register
Offset Bit Position
0x02C
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
16
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
Reset
0
Access
RW
Name
REGFREEZE
Bit Name Reset Access Description
31:1 Reserved To ensure compatibility with future devices, always write bits to 0. More information in 2.1 Conven-
tions.
0 REGFREEZE 0 RW Register Update Freeze
When set, the update of the PCNT clock domain is postponed until this bit is cleared. Use this bit to update several regis-
ters simultaneously.
Value Mode Description
0 UPDATE Each write access to a PCNT register is updated into the Low Frequen-
cy domain as soon as possible.
1 FREEZE The PCNT clock domain is not updated with the new written value.
24.5.13 PCNTn_SYNCBUSY - Synchronization Busy Register
Offset Bit Position
0x030
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
16
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
Reset
0
0
0
Access
R
R
R
Name
TOPB
CMD
CTRL
Bit Name Reset Access Description
31:3 Reserved To ensure compatibility with future devices, always write bits to 0. More information in 2.1 Conven-
tions.
2 TOPB 0 R TOPB Register Busy
Set when the value written to TOPB is being synchronized.
1 CMD 0 R CMD Register Busy
Set when the value written to CMD is being synchronized.
0 CTRL 0 R CTRL Register Busy
Set when the value written to CTRL is being synchronized.
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24.5.14 PCNTn_AUXCNT - Auxiliary Counter Value Register
Offset Bit Position
0x038
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
16
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
Reset
0x0000
Access
RWH
Name
AUXCNT
Bit Name Reset Access Description
31:16 Reserved To ensure compatibility with future devices, always write bits to 0. More information in 2.1 Conven-
tions.
15:0 AUXCNT 0x0000 RWH Auxiliary Counter Value
Gives read access to the auxiliary counter.
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24.5.15 PCNTn_INPUT - PCNT Input Register
Offset Bit Position
0x03C
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
16
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
Reset
0
0x0
0
0x0
Access
RW
RW
RW
RW
Name
S1PRSEN
S1PRSSEL
S0PRSEN
S0PRSSEL
Bit Name Reset Access Description
31:11 Reserved To ensure compatibility with future devices, always write bits to 0. More information in 2.1 Conven-
tions.
10 S1PRSEN 0 RW S1IN PRS Enable
When set, the PRS channel is selected as input to S1IN.
9:6 S1PRSSEL 0x0 RW S1IN PRS Channel Select
Select PRS channel as input to S1IN.
Value Mode Description
0 PRSCH0 PRS Channel 0 selected.
1 PRSCH1 PRS Channel 1 selected.
2 PRSCH2 PRS Channel 2 selected.
3 PRSCH3 PRS Channel 3 selected.
4 PRSCH4 PRS Channel 4 selected.
5 PRSCH5 PRS Channel 5 selected.
6 PRSCH6 PRS Channel 6 selected.
7 PRSCH7 PRS Channel 7 selected.
8 PRSCH8 PRS Channel 8 selected.
9 PRSCH9 PRS Channel 9 selected.
10 PRSCH10 PRS Channel 10 selected.
11 PRSCH11 PRS Channel 11 selected.
5 Reserved To ensure compatibility with future devices, always write bits to 0. More information in 2.1 Conven-
tions.
4 S0PRSEN 0 RW S0IN PRS Enable
When set, the PRS channel is selected as input to S0IN.
3:0 S0PRSSEL 0x0 RW S0IN PRS Channel Select
Select PRS channel as input to S0IN.
Value Mode Description
0 PRSCH0 PRS Channel 0 selected.
1 PRSCH1 PRS Channel 1 selected.
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Bit Name Reset Access Description
2 PRSCH2 PRS Channel 2 selected.
3 PRSCH3 PRS Channel 3 selected.
4 PRSCH4 PRS Channel 4 selected.
5 PRSCH5 PRS Channel 5 selected.
6 PRSCH6 PRS Channel 6 selected.
7 PRSCH7 PRS Channel 7 selected.
8 PRSCH8 PRS Channel 8 selected.
9 PRSCH9 PRS Channel 9 selected.
10 PRSCH10 PRS Channel 10 selected.
11 PRSCH11 PRS Channel 11 selected.
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25. LESENSE - Low Energy Sensor Interface
43210
Device
ZZZZZ
Quick Facts
What?
LESENSE is a low energy sensor interface capable
of autonomously collecting and processing data from
multiple sensors even when in EM2. Flexible config-
uration makes LESENSE a versatile sensor inter-
face compatible with a wide range of sensors and
measurement schemes.
Why?
Capability to autonomously monitor sensors allows
the EFM32WG to reside in a low energy mode for
long periods of time while keeping track of sensor
status and sensor events.
How?
LESENSE is highly configurable and is capable of
collecting data from a wide range of sensor types.
Once the data is collected, the programmable state
machine, LESENSE decoder, is capable of process-
ing sensor data without CPU intervention. A large re-
sult buffer allows the chip to remain in EM2 for long
periods of time while autonomously collecting data.
25.1 Introduction
LESENSE is a low energy sensor interface which utilizes on-chip peripherals to perform measurement of a configurable set of sensors.
The results from sensor measurements can be processed by the LESENSE decoder, which is a configurable state machine with up to
16 states. The results can also be stored in a result buffer to be collected by CPU or DMA for further processing.
LESENSE operates in EM2, in addition to EM1 and EM0, and can wake up the CPU on configurable events.
25.2 Features
• Up to 16 sensors
• Autonomous sensor monitoring in EM0, EM1, and EM2
• Highly configurable decoding of sensor results
• Interrupt on sensor events
• Configurable enable signals to external sensors
• Circular buffer for storage of up to 16 sensor results.
• Support for multiple sensor types
• LC sensors
• Capacitive sensing
• General analog sensors
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25.3 Functional Description
LESENSE is a module capable of controlling on-chip peripherals in order to perform monitoring of different sensors with little or no CPU
intervention. LESENSE uses the analog comparators, ACMP, for measurement of sensor signals. LESENSE can also control the DAC
to generate accurate reference voltages. The following figure shows an overview of the LESENSE module. LESENSE consists of a
sequencer, count and compare block, a decoder, and a RAM block used for configuration and result storage. The sequencer handles
interaction with other peripherals as well as timing of sensor measurements. The count and compare block is used to count pulses from
ACMP outputs before comparing with a configurable threshold. To autonomously analyze sensor results, the LESENSE decoder pro-
vides possibility to define a finite state machine with up to 16 states, and programmable actions upon state transitions. This allows the
decoder to implement a wide range of decoding schemes, for instance quadrature decoding. A RAM block is used for storage of config-
uration and measurement results. This allows LESENSE to have a relatively large result buffer enabling the chip to remain in a low
energy mode for long periods of time while collecting sensor data.
LESENSE
Counter
Compare
Decoder
PRS input
DAC0
AUXHFRCO
ACMP1
ACMP1_CHn
LES_ALTEXn
Register bitfields
overridden by LESENSE
Scaler
1.25 V
2.5 V
VDD
VSS
ACMP0
ACMP0_CHn
PRS
CH0 CH1
DAC0_CH0
DAC0_CH1
DAC0_CH0
DAC0_CH1
DAC0_CH0
DAC0_CH1
Scaler
1.25 V
2.5 V
VDD
VSS
DAC0_CH0
DAC0_CH1
ACMP0INV
ACMP1INV
VDDLEVEL
POSSEL
POSSEL
VDDLEVEL
RAMSequencer
ACMP sample reg
CONVMODE*
OUTMODE*
CHxCTRL_EN
CHxDATA
DAC
interface
* LESENSE controls CONVMODE and
OUTMODE individually for the DAC
channels
Figure 25.1. LESENSE Block Diagram
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25.3.1 Channel Configuration
LESENSE has 16 individually configurable channels, the first eight are mapped to the channels of ACMP0, while the last eight are map-
ped to the channels of ACMP1. Each LESENSE channel has its own set of configuration registers. Channel configuration is split into
three registers; CHx_TIMING, CHx_INTERACT, and CHx_EVAL. Individual timing for each sensor is configured in CHx_TIMING, sen-
sor interaction is configured in CHx_INTERACT, and configurations regarding evaluation of the measurements are done in CHx_EVAL.
For improved readability, CHx_CONF will be used to address the channel configuration registers, CHx_TIMING, CHx_INTERACT, and
CHx_EVAL, throughout this chapter.
By default, the channel configuration registers are directly mapped to the channel number. Configuring SCANCONF in CTRL makes it
possible to alter this mapping.
Configuring SCANCONF to INVMAP will make channels 0-7 use the channel configuration registers for channels 8-15, and vice versa.
This feature allows an application to quickly and easily switch configuration set for the channels.
Setting SCANCONF to TOGGLE will make channel x alternate between using CHX_CONF and CHX +8_CONF. The configuration used
is decided by the state of the corresponding bit in SCANRES. For instance, if channel 3 is performing a scan and bit 3 in SCANRES is
set, CH11_CONF will be used. Channels 8 through 15 will toggle between CHX_CONF and CHX-8_CONF. This mode provides an easy
way for implementation of hysteresis on channel events as threshold values can be changed depending on sensor status.
Setting SCANCONF to DECDEF will make the state of the decoder define which scan configuration to be used. If the decoder state is
at index 8 or higher, channel x will use CHX+8_CONF, otherwise it will use CHX configuration. Similarly, channels 8 through 15 will use
CHX configuration when decoder state index is less than 8 and CHX-8_CONF when decoder state index is higher than 7. Allowing the
decoder state to define which configuration to use, enables easy implementation of for instance hysteresis, as different threshold values
can be used for the same channel, depending on the state of the application. The table below summarizes how channel configuration is
selected for different setting of SCANCONF.
Table 25.1. LESENSE Scan Configuration Selection
LESENSE chan-
nel x
SCANCONF
DIRMAP INVMAP TOGGLE DECDEF
SCANRES[n] = 0 SCANRES[n] = 1 DECSTATE < 8 DECSTATE >= 8
0 <= x < 8 CHx_CONF CHx +8_CONF CHx_CONF CHx+8_CONF CHx_CONF CHx+8_CONF
8 <= x < 16 CHx_CONF CHx-8_CONF CHx_CONF CHx-8_CONF CHx_CONF CHx-8_CONF
Channels are enabled in the CHEN register, where bit x enables channel x. During a scan, all enabled channels are measured, starting
with the lowest indexed channel. The following figure illustrates a scan sequence with channels 3, 5, and 9 enabled.
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25.3.2 Scan Sequence
LESENSE runs on LFACLKLESENSE, which is a prescaled version of LFACLK. The prescaling factor for LFACLKLESENSE is selected
in the CMU, available prescaling factors are:
• DIV1: LFACLKLESENSE = LFACLK/1
• DIV2: LFACLKLESENSE = LFACLK/2
• DIV4: LFACLKLESENSE = LFACLK/4
• DIV8: LFACLKLESENSE = LFACLK/8
Note: LFACLKLESENSE should not exceed 50kHz.
All enabled channels are scanned each scan period. How a new scan is started is configured in the SCANMODE bit field in CTRL. If set
to PERIODIC, the scan frequency is generated using a counter which is clocked by LFACLKLESENSE. This counter has its own prescal-
er. This prescaling factor is configured in PCPRESC in TIMCTRL. A new scan sequence is started each time the counter reaches the
top value, PCTOP. The scan frequency is calculated using the following equation. If SCANMODE is set to ONESHOT, a single scan will
be made when START in CMD is set. To start a new scan on a PRS event, set START in CMD, set SCANMODE to PRS and configure
PRS channel in PRSSEL. The PRS start signal needs to be active for at least one LFACLKLESENSE cycle to make sure LESENSE is
able to register it.
Fscan =
LFACLKLESENSE
(1 + PCTOP) × 2PCPRESC
It is possible to interleave additional sensor measurements in between the periodic scans. Issuing a start command when LESENSE is
idle will immediately start a new scan, without disrupting the frequency of the periodic scans. If the period counter overflows during the
interleaved scan, the periodically scheduled scan will start immediately after the interleaved scan completes.
CH3 CH5 CH9 CH3 CH5 CH9
START START
Scan period
Figure 25.2. Scan Sequence
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25.3.3 Sensor Timing
For each channel in the scan sequence, the LESENSE interface goes through three phases: Idle phase, excite phase, and measure
phase. The durations of the excite and measure phases are configured in the CHx_TIMING registers. LESENSE includes two timers: A
low frequency timer, running on LFACLKLESENSE, and a high frequency timer, running on AUXHFRCO. Timing of the excite phase is
done using these timers and can be either a number of prescaled AUXHFRCO cycles or a number of prescaled LFACLKLESENSE cy-
cles, depending on which one is selected in EXCLK. The prescaling can be done by configuring LFPRESC in TIMCTRL for the low
frequency timer, and the high frequency timer prescaling factor is configured in AUXPRESC in the same register. The duration of the
measure phase is programmed via MEASUREDLY and SAMPLEDLY. The output of the ACMP will be inactive for MEASUREDLY
EXCLK cycles after start of the sensor measurement. Sampling of the sensor will happen after SAMPLEDLY LFACLKLESENSE, or
AUXHFRCO cycles, depending on the configuration of SAMPLECLK. The following figure depicts a sensor sequence where excitation
and measure delay is timed using AUXHFRCO and the sample delay is timed using LFACLKLESENSE. The configurable measure- and
sample delays enables LESENSE to easily define exact time windows for sensor measurements. A start delay can be inserted before
sensor measurement begin by configuring STARTDLY in TIMCTRL. This delay can be used to ensure that the DAC is done and voltag-
es have stabilized before sensor measurement begins.
EXCITE
SAMPLE
LFACLKLESENSE
Idle phase Excite phase Idle phase
Sample delay
Measure phase
START
AUXHFRCO
INIT
Start delay
Measure delay
DAC refresh start
Figure 25.3. Timing Diagram, Short Excitation
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25.3.4 Sensor Interaction
Many sensor types require some type of excitation in order to work. LESENSE can generate a variety of sensor stimuli, both on the
same pin as the measurement is to be made on, and on alternative pins.
By default, excitation is performed on the pin associated with the channel, i.e. excitation and sensor measurement is performed on the
same pin. The mode of the pin during the excitation phase is configured in EXMODE in CHx_INTERACT. The available modes during
the excite phase are:
• DISABLED: The pin is disabled.
• HIGH: The pin is driven high.
• LOW: The pin is driven low.
• DACOUT: The pin is connected to the output of a DAC channel.
Note: Excitation with DAC output is only available on channels 0, 1, 2, and 3 (DAC0_CH0) and channels 12, 13, 14, and 15
(DAC0_CH1).
If the DAC is in opamp-mode, setting EXMODE to DACOUT will result in excitation with output from the opamp.
LESENSE is able to perform sensor excitation on another pin than the one to be measured. When ALTEX in CHx_INTERACT is set,
the excitation will occur on the alternative excite pin associated with the given channel. All LESENSE channels mapped to ACMP0 have
their alternative channel mapped to the corresponding channel on ACMP1, and vice versa. Alternatively, the alternative excite pins can
be routed to the LES_ALTEX pins. Mapping of the alternative excite pins is configured in ALTEXMAP in CTRL. The following table
summarizes the mapping of excitation pins for different configurations.
Table 25.2. LESENSE Excitation Pin Mapping
LESENSE channel ALTEX = 0 ALTEX = 1
ALTEXMAP = ACMP ALTEXMAP = ALTEX
0 ACMP0_CH0 ACMP1_CH0 LES_ALTEX0
1 ACMP0_CH1 ACMP1_CH1 LES_ALTEX1
2 ACMP0_CH2 ACMP1_CH2 LES_ALTEX2
3 ACMP0_CH3 ACMP1_CH3 LES_ALTEX3
4 ACMP0_CH4 ACMP1_CH4 LES_ALTEX4
5 ACMP0_CH5 ACMP1_CH5 LES_ALTEX5
6 ACMP0_CH6 ACMP1_CH6 LES_ALTEX6
7 ACMP0_CH7 ACMP1_CH7 LES_ALTEX7
8 ACMP1_CH0 ACMP0_CH0 LES_ALTEX0
9 ACMP1_CH1 ACMP0_CH1 LES_ALTEX1
10 ACMP1_CH2 ACMP0_CH2 LES_ALTEX2
11 ACMP1_CH3 ACMP0_CH3 LES_ALTEX3
12 ACMP1_CH4 ACMP0_CH4 LES_ALTEX4
13 ACMP1_CH5 ACMP0_CH5 LES_ALTEX5
14 ACMP1_CH6 ACMP0_CH6 LES_ALTEX6
15 ACMP1_CH7 ACMP0_CH7 LES_ALTEX7
The following figure illustrates the sequencing of the pin associated with the active channel and its alternative excite pin.
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EXCITE
LFACLKLESENSE
Idle phase Excite phase Idle phaseMeasure phase
IDLECONF EXMODE Z IDLECONF
Channel pin
IDLECONF
Alternate excite pin
IDLECONF EXMODE IDLECONF
Alternate excite pin
IDLECONF Z IDLECONF
Channel pin
ALTEX=1
ALTEX=0
Figure 25.4. Pin Sequencing
The alternative excite pins, LES_ALTEXn, have the possibility to excite regardless of what channel is active. Setting AEXn in ALTEX-
CONF will make LES_ALTEXn excite for all channels using alternative excitation, i.e. ALTEX in CHx_INTERACT is set.
Note: When exciting on the pin associated with the active channel, the pin will go through a tristated phase before returning to the idle
configuration. This will not happen on pins used as alternative excitation pins.
The pin configuration for the idle phase can be configured individually for each LESENSE channel and alternative excite pin in the
IDLECONF and ALTEXCONF registers. The modes available are the same as the modes available in the excitation phase. In the
measure phase, the pin mode on the active channel is always disabled (analog input).
To enable LESENSE to control GPIO, the pin has to be enabled in the ROUTE register. In addition, the given pin must be configured as
push-pull. IDLECONF configuration should not be altered when pin enable for the given pin is set in ROUTE.
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25.3.5 Sensor Evaluation
Sensor evaluation can be based on either analog comparator outputs, or the counter output. This is configured in the SAMPLE bit-field
in CHx_INTERACT. The LESENSE counter is used to count pulses on the ACMP output in the measurement phase. When a measure-
ment phase is completed, the counter value is compared to the value configured in COMPTHRES in CHx_EVAL. By configuring
COMP, it is possible to choose comparison mode: Less than, or greater than or equal. If a comparison for a channel triggers, the corre-
sponding bit in the result register, SCANRES, is set. To set an interrupt flag on a sensor event, configure SETIF in CHx_INTERACT.
The following figure illustrates how the counter value or ACMP sample is used for evaluation and interrupt generation.
ACMP
sample
LESENSE
counter
ACMP
COUNTER
CHx_EVAL_SCANRESINV
COUNTER >= COMPTHRES
COUNTER < COMPTHRES
GE
LESS
CHx_EVAL_COMP
CHx_INTERACT_SAMPLE NONE
LEVEL
POSEDGE
NEGEDGE
CHx_INTERACT_SETIF
0
Set
interrupt
flag
SCANRES[x]
SENSORSTATE
Figure 25.5. Scan Result and Interrupt Generation
LESENSE includes the possibility to sample both analog comparators simultaneously, effectively cutting the time spent on sensor inter-
action in some applications in half. Setting DUALSAMPLE in CTRL enables this mode. In dual sample mode, the channels of ACMP0
are paired together with the corresponding channel on ACMP1, i.e. channel x on ACMP0 and channel x on ACMP1 are sampled simul-
taneously. The results from sensor measurements can be fed into the decoder register and/or stored in the result buffer. In this mode,
the samples from the AMCPs are placed in the two LSBs of the result stored in the result buffer. Results from both ACMPs will be
evaluated for interrupt generation.
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1....
25.3.6 Decoder
Many applications require some sort of processing of the sensor readings, for instance in the case of quadrature decoding. In quadra-
ture decoding, the sensors repeatedly pass through a set of states which corresponds to the position of the sensors. This sequence,
and many other decoding schemes, can be described as a finite state machine. To support this type of decoding without CPU interven-
tion, LESENSE includes a highly configurable decoder, capable of decoding input from up to four sensors. The decoder is implemented
as a programmable state machine with up to 16 states. When doing a sensor scan, the results from the sensors are placed in the de-
coder input register, SENSORSTATE, if DECODE in CHx_INTERACT is set. The resulting position after a scan is illustrated in the fol-
lowing figure, where the bottom blocks show how the SENSORSTATE register is filled. When the scan sequence is complete, the de-
coder evaluates the state of the sensors chosen for decoding, as depicted in the following figure.
CH0 CH1
START START
Scan period
Decode
CH2 CH3 CH0 CH1 Decode
CH2 CH3
CH0
result
-
-
-
CH0
result
CH1
result
-
-
CH0
result
CH1
result
CH2
result
-
CH0
result
CH1
result
CH2
result
CH3
result
SENSORSTATE[0]
SENSORSTATE[3]
CH0
result
CH1
result
CH2
result
CH3
result
CH0
result
CH1
result
CH2
result
CH3
result
CH0
result
CH1
result
CH2
result
CH3
result
CH0
result
CH1
result
CH2
result
CH3
result
Figure 25.6. Sensor Scan and Decode Sequence
The decoder is a programmable state machine with support for up to 16 states. The behavior of each state is individually configured in
the STx_TCONFA and STx_TCONFB registers. The registers define possible transitions from the present state. If the sensor state
matches COMP in either STx_TCONFA or STx_TCONFB, a transition to the state defined in NEXTSTATE will be made. It is also possi-
ble to mask out one or more sensors using the MASK bit field. The state of a masked sensor is interpreted as don't care.
Upon a state transition, LESENSE can generate a pulse on one or more of the decoder PRS channels. Which channel to generate a
pulse on is configured in the PRSACT bit field. If PRSCNT in DECCTRL is set, count signals will be generated on decoder PRS chan-
nels 0 and 1 according to the PRSACT configuration. In this mode, channel 0 will pulse each time a count event occurs while channel 1
indicates the count direction, 1 being up and 0 being down. The count direction will be kept at its previous state in between count
events. The EFM32WG pulse counter may be used to keep track of events based on these PRS outputs.
If SETIF is set, the DECODER interrupt flag will be set when the transition occurs. If INTMAP in DECCTRL and SETIF is set, a transi-
tion from state x will set the CHx interrupt flag in addition to the DECODER flag.
Setting CHAIN in STx_TCONFA enables the decoder to evaluate more than two possible transitions for each state. If none of the transi-
tions defined in STx_TCONFA or STx_TCONFB matches, the decoder will jump to the next descriptor pair and evaluate the transitions
defined there. The decoder uses two LFACLKLESENSE cycles for each descriptor pair to be evaluated. If ERRCHK in CTRL is set, the
decoder will check that the sensor state has not changed if none of the defined transitions match. The DECERR interrupt flag will be set
if none of the transitions match and the sensor state has changed. The following figure illustrates state transitions. The "Generate PRS
signals and set interrupt flag" blocks will perform actions according to the configuration in STx_TCONFA and STx_TCONFB.
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STi_TCONF
STi+1_TCONF
STATEi
SENSORSTATE &
~MASKAi = COMPAi &
~MASKAi
Generate PRS
signals and set
interrupt flag
NEXTSTATEAi
SENSORSTATE &
~MASKBi = COMPBi &
~MASKBi
Generate PRS
signals and set
interrupt flag
NEXTSTATEBi
CHAINi = 1
SENSORSTATE changed
&& ERRCHK=1
Set DECERR
interrupt flag
SENSORSTATE &
~MASKAi+1 = COMPAi+1 &
~MASKAi+1
SENSORSTATE &
~MASKBi+1 = COMPBi+1 &
~MASKBi+1
Generate PRS
signals and set
interrupt flag
NEXTSTATEAi+1
Generate PRS
signals and set
interrupt flag
NEXTSTATEBi+1
CHAINi+1 = 1
YES NO
YES
NO
YES NO
NOYES
YES NO
YES
NO
Figure 25.7. Decoder State Transition Evaluation
Note: If only one transition from a state is used, STx_TCONFA and STx_TCONFB should be configured equally.
To prevent unnecessary interrupt requests or PRS outputs when the decoder toggles back and forth between two states, a hysteresis
option is available. The hysteresis function is triggered if a type A transition is preceded by a type B transition, and vice versa. A type A
transition is a transition defined in STx_TCONFA, and a type B transition is a transition defined in STx_TCONFB. When descriptor
chaining is used, a jump to another descriptor will cancel out the hysteresis effect. The following figure illustrates how the hysteresis
triggers upon state transitions.
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4: A transition,
hysteresis
State 1
State 0
State 1
State 1
1: B transition,
no hysteresis
2: A transition,
hysteresis
3: B transition,
hysteresis
5: A transition,
no hysteresis
A transition—Transition defined in TCONFA
B transition—Transition defined in TCONFB
Figure 25.8. Decoder Hysteresis
The events suppressed by the hysteresis are configured in bit fields HYSTPRS0-2 and HYSTIRQ in DECCTRL.
• When HYSTPRSx is set, PRS signal x is suppressed when the hysteresis triggers.
• When HYSTIRQ is set, interrupt requests are suppressed when the hysteresis triggers.
Note: The decoder error interrupt flag, DECERR, is not affected by the hysteresis.
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fl______=
25.3.7 Measurement Results
Part of the LESENSE RAM is treated as a circular buffer for storage of up to 16 results from sensor measurements. Each time LE-
SENSE writes data to the result buffer, the result write pointer, PTR_WR, is incremented. Each time a new result is read through the
BUFDATA register, the result read pointer, PTR_RD, is incremented. The read pointer will not be incremented if there is no valid, un-
read data in the result buffer. By default LESENSE will not write additional data to a full result buffer until the data is read by software or
DMA. Setting BUFOW in CTRL enables LESENSE to write to the result buffer, even if it is full. In this mode, the result read pointer will
follow the write pointer if the buffer is full. The result of this is that data read from the result read register, BUFDATA, is the oldest un-
read result. The location pointers are available in PTR. The result buffer has three status flags; BUFDATAV, BUFHALFFULL, and BUF-
FULL. The flags indicate when new data is available, when the buffer is half full, and when it is full, respectively. The interrupt flag
BUFDATAV is set when data is available in the buffer. BUFLEVEL is set when the buffer is either full or half-full, depending on the
configuration of BUFIDL in CTRL. If the result buffer overflows, the BUFOF interrupt flag will be set.
During a scan, the state of each sensor is stored in SCANRES. If a sensor triggers, a 1 is stored in SCANRES, else a 0 is stored in
SCANRES. Whether or not a sensor is said to be triggered depends of the configuration for the given channel. If SAMPLE is set to
ACMP, the sensor is said to be triggered if the output from the analog comparator is 1 when sensor sampling is performed. If SAMPLE
is set to COUNTER, a sensor is said to be triggered if the LESENSE counter value is greater than or equal, or less than COMPTHRES,
depending on the configuration of COMP. If STRSAMPLE in CHx_EVAL is set, the counter value or ACMP sample for each channel will
be stored in the LESENSE result buffer. If STRSCANRES in CTRL is set, the result vector, SCANRES, will also be stored in the result
buffer. This will be stored after each scan and will be interleaved with the counter values. The contents of the result buffer can be read
from BUFDATA or from BUF[x]_DATA. When reading from BUF[x]_DATA, neither the result read pointer or the status flags BUFDA-
TAV, BUFHALFFULL, or BUFFULL will be updated. When reading through the BUFDATA register, the oldest unread result will be read.
BUF0_DATA
BUF1_DATA
BUF2_DATA
BUF3_DATA
BUF12_DATA
BUF13_DATA
BUF14_DATA
BUF15_DATA
BUFDATA
LESENSE
CH3 result
CH5 result
CH9 result
SCANRES
CH3 result
CH5 result
CH9 result
SCANRES
PTR_WR
PTR_RD
Figure 25.9. Circular Result Buffer
The right hand side of the previous figure illustrates how the result buffer would be filled when channels 3,5, and 9 are enabled and
have STRSAMPLE in CHx_EVAL set, in addition to STRSCANRES in CTRL. The measurement result from the three channels will be
sequentially written during the scan, while SCANRES is written to the result buffer upon scan completion.
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25.3.8 DAC Interface
LESENSE is able to drive the DAC for generation of accurate reference voltages. DAC channels 0 and 1 are individually configured in
the PERCTRL register. The conversion mode can be set to either continuous, sample/hold or sample/off. For further details about these
modes, refer to 28.3.2 Conversions. Both DAC channels are refreshed prior to each sensor measurement, as depicted in Figure
25.3 Timing Diagram, Short Excitation on page 796. The conversion data is either taken from the data registers in the EFM32WG DAC
interface (DAC0_CH0DATA and DAC0_CH1DATA) or from the ACMPTHRES bitfield in the CHx_INTERACT register for the active LE-
SENSE channel. DAC data used is configured in DACCHxDATA in PERCTRL.
The DAC interface runs on AUXHFRCO and will enable this when it is needed. The DACPRESC bit-field in PERCTRL is used to pre-
scale the AUXHFRCO to achieve wanted clock frequency for the LESENSE DAC interface. The frequency should not exceed 500kHz,
i.e. DACPRESC has to be set to at least 1. The prescaler may also be used to tune how long the DAC should drive its outputs in sam-
ple/off mode.
Bias configuration, calibration and reference selection is done in the EFM32WG DAC module and LESENSE will not override these
configurations. If a bandgap reference is selected for the DAC, the DACREF bit in PERCTRL should be set to BANDGAP.
LESENSE has the possibility to control switches that connect the DAC outputs to the pins associated with ACMP0_CH0-3 and
ACMP1_CH12-15. This makes LESENSE able to excite sensors with output from the DAC channels.
The DAC may be chosen as reference to the analog comparators for accurate reference generation. If the DAC is configured in continu-
ous or sample/hold mode this does not require any external components. If sample/off mode is used, an external capacitor is needed to
keep the voltage in between samples. To connect the input from the DAC to the ACMP to this external capacitor, connect the capacitor
to the DAC pin for the given channel and set OPAxSHORT in DAC_OPACTRL.
Note: The DAC mode should not be altered while DACACTIVE in STATUS is set
25.3.9 ACMP Interface
The ACMPs are used to measure the sensors, and have to be configured according to the application in order for LESENSE to work
properly. Depending on the configuration in the ACMP0MODE and ACMP1MODE bit-fields in PERCTRL, LESENSE will take control of
the positive input mux and the Vdd scaling factor (VDDLEVEL) for ACMP0 and ACMP1. The remaining configuration of the analog
comparators are done in the ACMP register interface. It is recommended to set the MUXEN bit in ACMPn_CTRL for the ACMPs used
by LESENSE. Each channel has the possibility to control the value of the Vdd scaling factor on the negative input of the ACMP,
VDDLEVEL in ACMP_INPUTSEL. This is done in the 6 LSBs of ACMPTHRES in CHx_INTERACT. LESENSE automatically controls
the ACMP mux to connect the correct channel.
25.3.10 ACMP and DAC Duty Cycling
By default, the analog comparators and DAC are shut down in between LESENSE scans to save energy. If this is not wanted, WAR-
MUPMODE in PERCTRL can be configured to prevent them from being shut down.
Both the DAC and analog comparators rely on a bias module for correct operation. This bias module has a low power mode which
consumes less energy at the cost of reduced accuracy. BIASMODE in BIASCTRL configures how the bias module is controlled by LE-
SENSE. When set to DUTYCYCLE, LESENSE will set the bias module in high accuracy mode whenever LESENSE is active, and keep
it in the low power mode otherwise. When BIASMODE is set to HIGHACC, the high accuracy mode is always selected. When set to
DONTTOUCH, LESENSE will not control the bias module.
25.3.11 DMA Requests
LESENSE issues a DMA request when the result buffer is either full or half full, depending on the configuration of BUFIDL in CTRL. The
request is cleared when the buffer level drops below the threshold defined in BUFIDL. A single DMA request is also set whenever there
is unread data in the buffer. DMAWU in CTRL configures at which buffer level LESENSE should wake-up the DMA when in EM2.
Note: The DMA controller should always fetch data from the BUFDATA register.
25.3.12 PRS Output
LESENSE is an asynchronous PRS producer and has nineteen PRS outputs. The decoder has three outputs and in addition, all bits in
the SCANRES register are available as PRS outputs. For further information on the decoder PRS output, refer to 25.3.6 Decoder.
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25.3.13 RAM
LESENSE includes a RAM block used for storage of configuration and results. If LESENSE is not used, this RAM block can be pow-
ered down eliminating its current consumption due to leakage. The RAM is powered down by setting the RAM bit in the POWERDOWN
register. Once the RAM has been shut down it cannot be turned back on without a reset of the chip. Registers mapped to the RAM
include: STx_TCONFA, STx_TCONFB, BUFx_DATA, BUFDATA, CHx_TIMING, CHx_INTERACT, and CHx_EVAL. These registers
have unknown value out of reset and have to be initialized before use.
Note: Read-modify-write operations on uninitialized RAM register produces undefined values.
25.3.14 Application Examples
25.3.14.1 Capacitive Sense
The following figure illustrates how the EFM32WG can be configured to monitor four capacitive buttons.
EFM32
ACMP0_CH0
ACMP0_CH1
ACMP0_CH2
ACMP0_CH3
Figure 25.10. Capacitive Sense Setup
The following steps show how to configure LESENSE to scan through the four buttons 100 times per second, issuing an interrupt if one
of them is pressed.
1. Assuming LFACLKLESENSE is 32kHz, set PCPRESC to 3 and PCTOP to 39 in CTRL. This will make the LESENSE scan frequency
100Hz.
2. Enable channels 0 through 3 in CHEN and set IDLECONF for these channels to DISABLED. In capacitive sense mode, the GPIO
should always be disabled (analog input).
3. Configure the ACMP to operate in CAPSENSE mode, refer to 26.3.5 Capacitive Sense Mode for details.
4. Configure the following bit fields in CHx_CONF, for channels 0 through 3:
a. Set EXTIME to 0. No excitation is needed in this mode.
b. Set SAMPLE to COUNTER and COMP to LESS. This makes LESENSE interpret a sensor as active if the frequency on a
channel drops below the threshold, i.e. the button is pressed.
c. Set SAMPLEDLY to an appropriate value, each sensor will be measured for SAMPLEDLY/ LFACLKLESENSE seconds. MEAS-
UREDLY should be set to 0
5. Set CTRTHRESHOLD to an appropriate value. An interrupt will be issued if the counter value for a sensor is below this threshold
after the measurement phase.
6. Enable interrupts on channels 0 through 3.
7. Start scan sequence by writing a 1 to START in CMD.
In a capacitive sense application, it might be required to calibrate the threshold values on a periodic basis, this is done in order to com-
pensate for humidity and other physical variations. LESENSE is able to store up to 16 counter values from a configurable number of
channels, making it possible to collect sample data while in EM2. When calibration is to be performed, the CPU only has to be woken
up for a short period of time as the data to be processed already lies in the result registers. To enable storing of the count value for a
channel, set STRSAMPLE in the CHx_INTERACT register.
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25.3.14.2 LC Sensor
The following figure below illustrates how the EFM32WG can be set up to monitor four LC sensors.
EFM32
ACMP0_CH0
ACMP0_CH1
ACMP0_CH2
DAC0_OUT0
X
XX
X
ACMP0_CH3
Figure 25.11. LC Sensor Setup
LESENSE can be used to excite and measure the damping factor in LC sensor oscillations. To measure the damping factor, the ACMP
can be used to generate a high output each time the sensor voltage exceeds a certain level. These pulses are counted using an asyn-
chronous counter and compared with the threshold in COMPTHRES in the CHx_EVAL register. If the number of pulses exceeds the
threshold level, the sensor is said to be active, otherwise it is inactive. The following figure illustrates how the output pulses from the
ACMP correspond to damping of the oscillations. The results from sensor evaluation can automatically be fed into the decoder in order
to keep track of rotations.
Figure 25.12. LC Sensor Oscillations
The following steps show how to configure LESENSE to scan through the four LC sensors 100 times per second.
1. Assuming LFACLKLESENSE is 32kHz, set PCPRESC to 3 and PCTOP to 39 in CTRL. This will make the LESENSE scan frequency
100Hz.
2. Enable the DAC and configure it to produce a voltage of Vdd/2.
3. Enable channels 0 through 3 in CHEN. Set IDLECONF for the active channels to DACOUT. The channel pins should be set to
Vdd/2 in the idle phase to damp the oscillations.
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4. Configure the ACMP to use scaled Vdd as negative input, refer to ACMP chapter for details.
5. Enable and configure PCNT and asynchronous PRS.
6. Configure the GPIOs used as PUSHPULL
7. Configure the following bit fields in CHx_CONF, for channels 0 through 3:
a. Set EXCLK to AUXHFRCO. AUXHFRCO is needed to achieve short excitation time.
b. Set EXTIME to an appropriate value. Excitation will last for EXTIME/AUXHFRCO seconds (prescalar value in AUXPRESC in
TIMCTRL is 0).
c. Set EXMODE to LOW. The LC sensors are excited by pulling the excitation pin low.
d. Set SAMPLE to COUNTER and COMP to LESS. Status of each sensor is evaluated based on the number of pulses generated
by the ACMP. If they are less than the threshold value, the sensor is said to be active.
e. Set SAMPLEDLY to an appropriate value, each sensor will be measured for SAMPLEDLY/ LFACLKLESENSE seconds.
8. Set CTRTHRESHOLD to an appropriate value. If the sensor is active, the counter value after the measurement phase should be
less than the threshold. If it inactive, the counter value should be greater than the threshold.
9. Start scan sequence by writing a 1 to START in CMD.
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25.3.14.3 LESENSE Decoder 1
The example below illustrates how the LESENSE module can be used for decoding using three sensors.
0 1 2 3
7 6 5 4
001
000
011
001
010
011
110
111
111
101
101
100
010 110
000 100
xxx
State Index
Sensor value
Figure 25.13. FSM Example 1
To set up the decoder to decode rotation using the encoding scheme seen in the previous figure, configure the following LESENSE
registers:
1. Configure the channels to be used, be sure to set DECODE in CHx_EVAL.
2. Set PRSCNT to enable generation of count waveforms on PRS. Also configure a PCNT to listen to the PRS channels and count
accordingly.
3. Configure the following in STx_TCONFA and STx_TCONFB:
a. Set MASK = 0b1000 in STx_TCONFA and STx_TCONFB for all used states. This enables three sensors to be evaluated by
the decoder.
b. Configure the remaining bit fields in STx_TCONFA and STx_TCONFB as described in the following table.
Table 25.3. LESENSE Decoder Configuration
Register TCON-
FA_NEXT
TCAOTNE-
FA_COMP
TCON-
FA_PRSACT
TCONFB_NE
XT
TTCAOT-
NEFB_COMP
TCONFB_PR
SACT
ST0 1 0b001 UP 7 0b100 DOWN
ST1 2 0b011 UP 0 0b000 DOWN
ST2 3 0b010 UP 1 0b001 DOWN
ST3 4 0b110 UP 2 0b011 DOWN
ST4 5 0b111 UP 3 0b010 DOWN
ST5 6 0b101 UP 4 0b110 DOWN
ST6 7 0b100 UP 5 0b111 DOWN
ST7 0 0b000 UP 6 0b101 DOWN
4. To initialize the decoder, run one scan, and read the present sensor status from SENSORSTATE. Then write the index of this state
to DECSTATE.
5. Write to START in CMD to start scanning of sensors and decoding.
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< :="" 0000="" 0011="" 0010="" 0001="" 0000="" 1xx="" \="" 1="" 0011="">25.3.14.4 LESENSE Decoder 2
The example below illustrates how the LESENSE decoder can be used to implement the state machine seen in the following figure.
0
2
4
6
8
0010
0000
0001
0000
0001
0011
0011
0010 1XXX
1XXX
1XXX
1XXX
State Index
Sensor value
Figure 25.14. FSM Example 2
1. Configure STx_TCONFA and STx_TCONFB as described in the following table.
Table 25.4. LESENSE Decoder Configuration
Register NEXTSTATE COMP MASK CHAIN
ST0_TCONFA 8 0b1000 0b0111 1
ST0_TCONFB 2 0b0001 0b1000 –
ST1_TCONFA 6 0b0010 0b1000 0
ST1_TCONFB 6 0b0010 0b1000 –
ST2_TCONFA 8 0b1000 0b0111 1
ST2_TCONFB 4 0b0011 0b1000 –
ST3_TCONFA 0 0b0000 0b1000 0
ST3_TCONFB 0 0b0000 0b1000 –
ST4_TCONFA 8 0b1000 0b0111 1
ST4_TCONFB 6 0b0010 0b1000 –
ST5_TCONFA 2 0b0001 0b1000 0
ST5_TCONFB 2 0b0001 0b1000 –
ST6_TCONFA 8 0b1000 0b0111 1
ST6_TCONFB 0 0b0000 0b1000 –
ST7_TCONFA 4 0b0011 0b1000 0
ST7_TCONFB 4 0b0011 0b1000 –
2. To initialize the decoder, run one scan, and read the present sensor status from SENSORSTATE. Then write the index of this state
to DECSTATE.
3. Write to START in CMD to start scanning of sensors and decoding.
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25.4 Register Map
The offset register address is relative to the registers base address.
Offset Name Type Description
0x000 LESENSE_CTRL RW Control Register
0x004 LESENSE_TIMCTRL RW Timing Control Register
0x008 LESENSE_PERCTRL RW Peripheral Control Register
0x00C LESENSE_DECCTRL RW Decoder control Register
0x010 LESENSE_BIASCTRL RW Bias Control Register
0x014 LESENSE_CMD W1 Command Register
0x018 LESENSE_CHEN RW Channel enable Register
0x01C LESENSE_SCANRES RScan result register
0x020 LESENSE_STATUS RStatus Register
0x024 LESENSE_PTR RResult buffer pointers
0x028 LESENSE_BUFDATA R(a) Result buffer data register
0x02C LESENSE_CURCH RCurrent channel index
0x030 LESENSE_DECSTATE RWH Current decoder state
0x034 LESENSE_SENSORSTATE RWH Decoder input register
0x038 LESENSE_IDLECONF RW GPIO Idle phase configuration
0x03C LESENSE_ALTEXCONF RW Alternative excite pin configuration
0x040 LESENSE_IF RInterrupt Flag Register
0x044 LESENSE_IFC (R)W1 Interrupt Flag Clear Register
0x048 LESENSE_IFS W1 Interrupt Flag Set Register
0x04C LESENSE_IEN RW Interrupt Enable Register
0x050 LESENSE_SYNCBUSY RSynchronization Busy Register
0x054 LESENSE_ROUTE RW I/O Routing Register
0x058 LESENSE_POWERDOWN RW LESENSE RAM power-down register
0x200 LESENSE_ST0_TCONFA RW State transition configuration A
0x204 LESENSE_ST0_TCONFB RW State transition configuration B
... LESENSE_STx_TCONFA RW State transition configuration A
... LESENSE_STx_TCONFB RW State transition configuration B
0x278 LESENSE_ST15_TCONFA RW State transition configuration A
0x27C LESENSE_ST15_TCONFB RW State transition configuration B
0x280 LESENSE_BUF0_DATA RW Scan results
... LESENSE_BUFx_DATA RW Scan results
0x2BC LESENSE_BUF15_DATA RW Scan results
0x2C0 LESENSE_CH0_TIMING RW Scan configuration
0x2C4 LESENSE_CH0_INTERACT RW Scan configuration
0x2C8 LESENSE_CH0_EVAL RW Scan configuration
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Offset Name Type Description
... LESENSE_CHx_TIMING RW Scan configuration
... LESENSE_CHx_INTERACT RW Scan configuration
... LESENSE_CHx_EVAL RW Scan configuration
0x3B0 LESENSE_CH15_TIMING RW Scan configuration
0x3B4 LESENSE_CH15_INTERACT RW Scan configuration
0x3B8 LESENSE_CH15_EVAL RW Scan configuration
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25.5 Register Description
25.5.1 LESENSE_CTRL - Control Register (Async Reg)
For more information about Asynchronous Registers, see 5.2.4 Access to Low Energy Peripherals (Asynchronous Registers).
Offset Bit Position
0x000
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
16
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
Reset
0
0x0
0
0
0
0
0
0
0
0x0
0x0
0x0
Access
RW
RW
RW
RW
RW
RW
RW
RW
RW
RW
RW
RW
Name
DEBUGRUN
DMAWU
BUFIDL
STRSCANRES
BUFOW
DUALSAMPLE
ALTEXMAP
ACMP1INV
ACMP0INV
SCANCONF
PRSSEL
SCANMODE
Bit Name Reset Access Description
31:23 Reserved To ensure compatibility with future devices, always write bits to 0. More information in 2.1 Conven-
tions.
22 DEBUGRUN 0 RW Debug Mode Run Enable
Set to keep LESENSE running in debug mode.
Value Description
0 LESENSE can not start new scans in debug mode
1 LESENSE can start new scans in debug mode
21:20 DMAWU 0x0 RW DMA wake-up from EM2
Value Mode Description
0 DISABLE No DMA wake-up from EM2
1 BUFDATAV DMA wake-up from EM2 when data is valid in the result buffer
2 BUFLEVEL DMA wake-up from EM2 when the result buffer is full/half-full depend-
ing on BUFIDL configuration
19 Reserved To ensure compatibility with future devices, always write bits to 0. More information in 2.1 Conven-
tions.
18 BUFIDL 0 RW Result buffer interrupt and DMA trigger level
Value Mode Description
0 HALFFULL DMA and interrupt flags set when result buffer is half-full
1 FULL DMA and interrupt flags set when result buffer is full
17 STRSCANRES 0 RW Enable storing of SCANRES
When set, SCANRES will be stored in the result buffer after each scan
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Bit Name Reset Access Description
16 BUFOW 0 RW Result buffer overwrite
If set, LESENSE will always write to the result buffer, even if it is full
15:14 Reserved To ensure compatibility with future devices, always write bits to 0. More information in 2.1 Conven-
tions.
13 DUALSAMPLE 0 RW Enable dual sample mode
When set, both ACMPs will be sampled simultaneously.
12 Reserved To ensure compatibility with future devices, always write bits to 0. More information in 2.1 Conven-
tions.
11 ALTEXMAP 0 RW Alternative excitation map
Value Mode Description
0 ALTEX Alternative excitation is mapped to the LES_ALTEX pins.
1 ACMP Alternative excitation is mapped to the pins of the other ACMP.
10 ACMP1INV 0 RW Invert analog comparator 1 output
9 ACMP0INV 0 RW Invert analog comparator 0 output
8 Reserved To ensure compatibility with future devices, always write bits to 0. More information in 2.1 Conven-
tions.
7:6 SCANCONF 0x0 RW Select scan configuration
These bits control which CHx_CONF registers to be used.
Value Mode Description
0 DIRMAP The channel configuration register registers used are directly mapped
to the channel number.
1 INVMAP The channel configuration register registers used are CHX+8_CONF for
channels 0-7 and CHX-8_CONF for channels 8-15.
2 TOGGLE The channel configuration register registers used toggles between
CHX_CONF and CHX+8_CONF when channel x triggers
3 DECDEF The decoder state defines the CONF registers to be used.
5:2 PRSSEL 0x0 RW Scan start PRS select
Select PRS source for scan start if SCANMODE is set to PRS.
Value Mode Description
0 PRSCH0 PRS Channel 0 selected as input
1 PRSCH1 PRS Channel 1 selected as input
2 PRSCH2 PRS Channel 2 selected as input
3 PRSCH3 PRS Channel 3 selected as input
4 PRSCH4 PRS Channel 4 selected as input
5 PRSCH5 PRS Channel 5 selected as input
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Bit Name Reset Access Description
6 PRSCH6 PRS Channel 6 selected as input
7 PRSCH7 PRS Channel 7 selected as input
8 PRSCH8 PRS Channel 8 selected as input
9 PRSCH9 PRS Channel 9 selected as input
10 PRSCH10 PRS Channel 10 selected as input
11 PRSCH11 PRS Channel 11 selected as input
1:0 SCANMODE 0x0 RW Configure scan mode
These bits control how the scan frequency is decided
Value Mode Description
0 PERIODIC A new scan is started each time the period counter overflows
1 ONESHOT A single scan is performed when START in CMD is set
2 PRS Pulse on PRS channel
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25.5.2 LESENSE_TIMCTRL - Timing Control Register (Async Reg)
For more information about Asynchronous Registers, see 5.2.4 Access to Low Energy Peripherals (Asynchronous Registers).
Offset Bit Position
0x004
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
16
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
Reset
0x0
0x00
0x0
0x0
0x0
Access
RW
RW
RW
RW
RW
Name
STARTDLY
PCTOP
PCPRESC
LFPRESC
AUXPRESC
Bit Name Reset Access Description
31:24 Reserved To ensure compatibility with future devices, always write bits to 0. More information in 2.1 Conven-
tions.
23:22 STARTDLY 0x0 RW Start delay configuration
Delay sensor interaction STARTDELAY LFACLKLESENSE cycles for each channel
21:20 Reserved To ensure compatibility with future devices, always write bits to 0. More information in 2.1 Conven-
tions.
19:12 PCTOP 0x00 RW Period counter top value
These bits contain the top value for the period counter.
11 Reserved To ensure compatibility with future devices, always write bits to 0. More information in 2.1 Conven-
tions.
10:8 PCPRESC 0x0 RW Period counter prescaling
Value Mode Description
0 DIV1 The period counter clock frequency is LFACLKLESENSE/1
1 DIV2 The period counter clock frequency is LFACLKLESENSE/2
2 DIV4 The period counter clock frequency is LFACLKLESENSE/4
3 DIV8 The period counter clock frequency is LFACLKLESENSE/8
4 DIV16 The period counter clock frequency is LFACLKLESENSE/16
5 DIV32 The period counter clock frequency is LFACLKLESENSE/32
6 DIV64 The period counter clock frequency is LFACLKLESENSE/64
7 DIV128 The period counter clock frequency is LFACLKLESENSE/128
7 Reserved To ensure compatibility with future devices, always write bits to 0. More information in 2.1 Conven-
tions.
6:4 LFPRESC 0x0 RW Prescaling factor for low frequency timer
Value Mode Description
0 DIV1 Low frequency timer is clocked with LFACLKLESENSE/1
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Bit Name Reset Access Description
1 DIV2 Low frequency timer is clocked with LFACLKLESENSE/2
2 DIV4 Low frequency timer is clocked with LFACLKLESENSE/4
3 DIV8 Low frequency timer is clocked with LFACLKLESENSE/8
4 DIV16 Low frequency timer is clocked with LFACLKLESENSE/16
5 DIV32 Low frequency timer is clocked with LFACLKLESENSE/32
6 DIV64 Low frequency timer is clocked with LFACLKLESENSE/64
7 DIV128 Low frequency timer is clocked with LFACLKLESENSE/128
3:2 Reserved To ensure compatibility with future devices, always write bits to 0. More information in 2.1 Conven-
tions.
1:0 AUXPRESC 0x0 RW Prescaling factor for high frequency timer
Value Mode Description
0 DIV1 High frequency timer is clocked with AUXHFRCO/1
1 DIV2 High frequency timer is clocked with AUXHFRCO/2
2 DIV4 High frequency timer is clocked with AUXHFRCO/4
3 DIV8 High frequency timer is clocked with AUXHFRCO/8
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25.5.3 LESENSE_PERCTRL - Peripheral Control Register (Async Reg)
For more information about Asynchronous Registers, see 5.2.4 Access to Low Energy Peripherals (Asynchronous Registers).
Offset Bit Position
0x008
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
16
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
Reset
0x0
0x0
0x0
0
0x00
0x0
0x0
0x0
0x0
0
0
Access
RW
RW
RW
RW
RW
RW
RW
RW
RW
RW
RW
Name
WARMUPMODE
ACMP1MODE
ACMP0MODE
DACREF
DACPRESC
DACCH1OUT
DACCH0OUT
DACCH1CONV
DACCH0CONV
DACCH1DATA
DACCH0DATA
Bit Name Reset Access Description
31:28 Reserved To ensure compatibility with future devices, always write bits to 0. More information in 2.1 Conven-
tions.
27:26 WARMUPMODE 0x0 RW ACMP and DAC duty cycle mode
Value Mode Description
0 NORMAL The analog comparators and DAC are shut down when LESENSE is
idle
1 KEEPACMPWARM The analog comparators are kept powered up when LESENSE is idle
2 KEEPDACWARM The DAC is kept powered up when LESENSE is idle
3 KEEPACMPDACWARM The analog comparators and DAC are kept powered up when LE-
SENSE is idle
25:24 Reserved To ensure compatibility with future devices, always write bits to 0. More information in 2.1 Conven-
tions.
23:22 ACMP1MODE 0x0 RW ACMP1 mode
Configure how LESENSE controls ACMP1
Value Mode Description
0 DISABLE LESENSE does not control ACMP1
1 MUX LESENSE controls the input mux (POSSEL) of ACMP1
2 MUXTHRES LESENSE controls the input mux and the threshold value (VDDLEVEL)
of ACMP1
21:20 ACMP0MODE 0x0 RW ACMP0 mode
Configure how LESENSE controls ACMP0
Value Mode Description
0 DISABLE LESENSE does not control ACMP0
1 MUX LESENSE controls the input mux (POSSEL) of ACMP0
2 MUXTHRES LESENSE controls the input mux (POSSEL) and the threshold value
(VDDLEVEL) of ACMP0
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Bit Name Reset Access Description
19 Reserved To ensure compatibility with future devices, always write bits to 0. More information in 2.1 Conven-
tions.
18 DACREF 0 RW DAC bandgap reference used
Set to BANDGAP if the DAC is configured to use bandgap reference
Value Mode Description
0 VDD DAC uses VDD reference
1 BANDGAP DAC uses bandgap reference
17:15 Reserved To ensure compatibility with future devices, always write bits to 0. More information in 2.1 Conven-
tions.
14:10 DACPRESC 0x00 RW DAC prescaler configuration.
Prescaling factor of DACPRESC+1 for the LESENSE DAC interface
9:8 DACCH1OUT 0x0 RW DAC channel 1 output mode
Value Mode Description
0 DISABLE DAC CH1 output to pin and ACMP/ADC disabled
1 PIN DAC CH1 output to pin enabled, output to ADC and ACMP disabled
2 ADCACMP DAC CH1 output to pin disabled, output to ADC and ACMP enabled
3 PINADCACMP DAC CH1 output to pin, ADC, and ACMP enabled.
7:6 DACCH0OUT 0x0 RW DAC channel 0 output mode
Value Mode Description
0 DISABLE DAC CH0 output to pin and ACMP/ADC disabled
1 PIN DAC CH0 output to pin enabled, output to ADC and ACMP disabled
2 ADCACMP DAC CH0 output to pin disabled, output to ADC and ACMP enabled
3 PINADCACMP DAC CH0 output to pin, ADC, and ACMP enabled.
5:4 DACCH1CONV 0x0 RW DAC channel 1 conversion mode
Value Mode Description
0 DISABLE LESENSE does not control DAC CH1.
1 CONTINUOUS DAC channel 1 is driven in continuous mode.
2 SAMPLEHOLD DAC channel 1 is driven in sample hold mode.
3 SAMPLEOFF DAC channel 1 is driven in sample off mode.
3:2 DACCH0CONV 0x0 RW DAC channel 0 conversion mode
Value Mode Description
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Bit Name Reset Access Description
0 DISABLE LESENSE does not control DAC CH0.
1 CONTINUOUS DAC channel 0 is driven in continuous mode.
2 SAMPLEHOLD DAC channel 0 is driven in sample hold mode.
3 SAMPLEOFF DAC channel 0 is driven in sample off mode.
1 DACCH1DATA 0 RW DAC CH1 data selection.
Configure DAC data control.
Value Mode Description
0 DACDATA DAC data is defined by CH1DATA in the DAC interface.
1 ACMPTHRES DAC data is defined by ACMPTHRES in CHx_INTERACT.
0 DACCH0DATA 0 RW DAC CH0 data selection.
Value Mode Description
0 DACDATA DAC data is defined by CH0DATA in the DAC interface.
1 ACMPTHRES DAC data is defined by ACMPTHRES in CHx_INTERACT.
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25.5.4 LESENSE_DECCTRL - Decoder control Register (Async Reg)
For more information about Asynchronous Registers, see 5.2.4 Access to Low Energy Peripherals (Asynchronous Registers).
Offset Bit Position
0x00C
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
16
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
Reset
0x0
0x0
0x0
0x0
0
0
0
0
0
0
0
0
0
Access
RW
RW
RW
RW
RW
RW
RW
RW
RW
RW
RW
RW
RW
Name
PRSSEL3
PRSSEL2
PRSSEL1
PRSSEL0
INPUT
PRSCNT
HYSTIRQ
HYSTPRS2
HYSTPRS1
HYSTPRS0
INTMAP
ERRCHK
DISABLE
Bit Name Reset Access Description
31:26 Reserved To ensure compatibility with future devices, always write bits to 0. More information in 2.1 Conven-
tions.
25:22 PRSSEL3 0x0 RW
Select PRS input for bit 3 of the LESENSE decoder
Value Mode Description
0 PRSCH0 PRS Channel 0 selected as input
1 PRSCH1 PRS Channel 1 selected as input
2 PRSCH2 PRS Channel 2 selected as input
3 PRSCH3 PRS Channel 3 selected as input
4 PRSCH4 PRS Channel 4 selected as input
5 PRSCH5 PRS Channel 5 selected as input
6 PRSCH6 PRS Channel 6 selected as input
7 PRSCH7 PRS Channel 7 selected as input
8 PRSCH8 PRS Channel 8 selected as input
9 PRSCH9 PRS Channel 9 selected as input
10 PRSCH10 PRS Channel 10 selected as input
11 PRSCH11 PRS Channel 11 selected as input
21:18 PRSSEL2 0x0 RW
Select PRS input for bit 2 of the LESENSE decoder
Value Mode Description
0 PRSCH0 PRS Channel 0 selected as input
1 PRSCH1 PRS Channel 1 selected as input
2 PRSCH2 PRS Channel 2 selected as input
3 PRSCH3 PRS Channel 3 selected as input
4 PRSCH4 PRS Channel 4 selected as input
5 PRSCH5 PRS Channel 5 selected as input
6 PRSCH6 PRS Channel 6 selected as input
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Bit Name Reset Access Description
7 PRSCH7 PRS Channel 7 selected as input
8 PRSCH8 PRS Channel 8 selected as input
9 PRSCH9 PRS Channel 9 selected as input
10 PRSCH10 PRS Channel 10 selected as input
11 PRSCH11 PRS Channel 11 selected as input
17:14 PRSSEL1 0x0 RW
Select PRS input for the bit 1 of the LESENSE decoder
Value Mode Description
0 PRSCH0 PRS Channel 0 selected as input
1 PRSCH1 PRS Channel 1 selected as input
2 PRSCH2 PRS Channel 2 selected as input
3 PRSCH3 PRS Channel 3 selected as input
4 PRSCH4 PRS Channel 4 selected as input
5 PRSCH5 PRS Channel 5 selected as input
6 PRSCH6 PRS Channel 6 selected as input
7 PRSCH7 PRS Channel 7 selected as input
8 PRSCH8 PRS Channel 8 selected as input
9 PRSCH9 PRS Channel 9 selected as input
10 PRSCH10 PRS Channel 10 selected as input
11 PRSCH11 PRS Channel 11 selected as input
13:10 PRSSEL0 0x0 RW
Select PRS input for the bit 0 of the LESENSE decoder
Value Mode Description
0 PRSCH0 PRS Channel 0 selected as input
1 PRSCH1 PRS Channel 1 selected as input
2 PRSCH2 PRS Channel 2 selected as input
3 PRSCH3 PRS Channel 3 selected as input
4 PRSCH4 PRS Channel 4 selected as input
5 PRSCH5 PRS Channel 5 selected as input
6 PRSCH6 PRS Channel 6 selected as input
7 PRSCH7 PRS Channel 7 selected as input
8 PRSCH8 PRS Channel 8 selected as input
9 PRSCH9 PRS Channel 9 selected as input
10 PRSCH10 PRS Channel 10 selected as input
11 PRSCH11 PRS Channel 11 selected as input
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Bit Name Reset Access Description
9 Reserved To ensure compatibility with future devices, always write bits to 0. More information in 2.1 Conven-
tions.
8 INPUT 0 RW
Select input to the LESENSE decoder
Value Mode Description
0 SENSORSTATE The SENSORSTATE register is used as input to the decoder.
1 PRS PRS channels are used as input to the decoder.
7 PRSCNT 0 RW Enable count mode on decoder PRS channels 0 and 1
When set, decoder PRS0 and PRS1 will be used to produce output which can be used by a PCNT to count up or down.
6 HYSTIRQ 0 RW Enable decoder hysteresis on interrupt requests
When set, hysteresis is enabled in the decoder, suppressing interrupt requests.
5 HYSTPRS2 0 RW Enable decoder hysteresis on PRS2 output
When set, hysteresis is enabled in the decoder, suppressing changes on PRS channel 2
4 HYSTPRS1 0 RW Enable decoder hysteresis on PRS1 output
When set, hysteresis is enabled in the decoder, suppressing changes on PRS channel 1
3 HYSTPRS0 0 RW Enable decoder hysteresis on PRS0 output
When set, hysteresis is enabled in the decoder, suppressing changes on PRS channel 0
2 INTMAP 0 RW Enable decoder to channel interrupt mapping
When set, a transition from state x in the decoder will set interrupt flag CHx
1 ERRCHK 0 RW Enable check of current state
When set, the decoder checks the current state in addition to the states defined in TCONF
0 DISABLE 0 RW Disable the decoder
When set, the decoder is disabled. When disabled the decoder will keep its current state
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25.5.5 LESENSE_BIASCTRL - Bias Control Register (Async Reg)
For more information about Asynchronous Registers, see 5.2.4 Access to Low Energy Peripherals (Asynchronous Registers).
Offset Bit Position
0x010
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
16
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
Reset
0x0
Access
RW
Name
BIASMODE
Bit Name Reset Access Description
31:2 Reserved To ensure compatibility with future devices, always write bits to 0. More information in 2.1 Conven-
tions.
1:0 BIASMODE 0x0 RW Select bias mode
Value Mode Description
0 DUTYCYCLE Bias module duty cycled between low power and high accuracy mode
1 HIGHACC Bias module always in high accuracy mode
2 DONTTOUCH Bias module not affected by LESENSE
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25.5.6 LESENSE_CMD - Command Register
Offset Bit Position
0x014
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
16
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
Reset
0
0
0
0
Access
W1
W1
W1
W1
Name
CLEARBUF
DECODE
STOP
START
Bit Name Reset Access Description
31:4 Reserved To ensure compatibility with future devices, always write bits to 0. More information in 2.1 Conven-
tions.
3 CLEARBUF 0 W1 Clear result buffer
2 DECODE 0 W1 Start decoder
1 STOP 0 W1 Stop scanning of sensors
If issued during a scan, the command will take effect after scan completion.
0 START 0 W1 Start scanning of sensors.
25.5.7 LESENSE_CHEN - Channel enable Register (Async Reg)
For more information about Asynchronous Registers, see 5.2.4 Access to Low Energy Peripherals (Asynchronous Registers).
Offset Bit Position
0x018
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
16
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
Reset
0x0000
Access
RW
Name
CHEN
Bit Name Reset Access Description
31:16 Reserved To ensure compatibility with future devices, always write bits to 0. More information in 2.1 Conven-
tions.
15:0 CHEN 0x0000 RW Enable scan channel
Set bit X to enable channel X
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25.5.8 LESENSE_SCANRES - Scan result register (Async Reg)
For more information about Asynchronous Registers, see 5.2.4 Access to Low Energy Peripherals (Asynchronous Registers).
Offset Bit Position
0x01C
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
16
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
Reset
0x0000
Access
R
Name
SCANRES
Bit Name Reset Access Description
31:16 Reserved To ensure compatibility with future devices, always write bits to 0. More information in 2.1 Conven-
tions.
15:0 SCANRES 0x0000 R Scan results
Bit X will be set depending on channel X evaluation
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25.5.9 LESENSE_STATUS - Status Register (Async Reg)
For more information about Asynchronous Registers, see 5.2.4 Access to Low Energy Peripherals (Asynchronous Registers).
Offset Bit Position
0x020
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
16
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
Reset
0
0
0
0
0
0
Access
R
R
R
R
R
R
Name
DACACTIVE
SCANACTIVE
RUNNING
BUFFULL
BUFHALFFULL
BUFDATAV
Bit Name Reset Access Description
31:6 Reserved To ensure compatibility with future devices, always write bits to 0. More information in 2.1 Conven-
tions.
5 DACACTIVE 0 R LESENSE DAC interface is active
4 SCANACTIVE 0 R LESENSE is currently interfacing sensors.
3 RUNNING 0 R LESENSE is active
2 BUFFULL 0 R Result buffer full
Set when the result buffer is full
1 BUFHALFFULL 0 R Result buffer half full
Set when the result buffer is half full
0 BUFDATAV 0 R Result data valid
Set when data is available in the result buffer. Cleared when the buffer is empty.
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25.5.10 LESENSE_PTR - Result buffer pointers (Async Reg)
For more information about Asynchronous Registers, see 5.2.4 Access to Low Energy Peripherals (Asynchronous Registers).
Offset Bit Position
0x024
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
16
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
Reset
0x0
0x0
Access
R
R
Name
WR
RD
Bit Name Reset Access Description
31:9 Reserved To ensure compatibility with future devices, always write bits to 0. More information in 2.1 Conven-
tions.
8:5 WR 0x0 R Result buffer write pointer.
These bits show the next index in the result buffer to be written to. Incremented when LESENSE writes to result buffer
4 Reserved To ensure compatibility with future devices, always write bits to 0. More information in 2.1 Conven-
tions.
3:0 RD 0x0 R Result buffer read pointer.
These bits show the index of the oldest unread data in the result buffer. Incremented on read from BUFDATA.
25.5.11 LESENSE_BUFDATA - Result buffer data register (Async Reg) (Actionable Reads)
For more information about Asynchronous Registers, see 5.2.4 Access to Low Energy Peripherals (Asynchronous Registers).
Offset Bit Position
0x028
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
16
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
Reset
0xXXXX
Access
R
Name
BUFDATA
Bit Name Reset Access Description
31:16 Reserved To ensure compatibility with future devices, always write bits to 0. More information in 2.1 Conven-
tions.
15:0 BUFDATA 0xXXXX R Result data
This register can be used to read the oldest unread data from the result buffer.
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25.5.12 LESENSE_CURCH - Current channel index (Async Reg)
For more information about Asynchronous Registers, see 5.2.4 Access to Low Energy Peripherals (Asynchronous Registers).
Offset Bit Position
0x02C
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
16
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
Reset
0x0
Access
R
Name
CURCH
Bit Name Reset Access Description
31:4 Reserved To ensure compatibility with future devices, always write bits to 0. More information in 2.1 Conven-
tions.
3:0 CURCH 0x0 R Shows the index of the current channel
25.5.13 LESENSE_DECSTATE - Current decoder state (Async Reg)
For more information about Asynchronous Registers, see 5.2.4 Access to Low Energy Peripherals (Asynchronous Registers).
Offset Bit Position
0x030
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
16
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
Reset
0x0
Access
RWH
Name
DECSTATE
Bit Name Reset Access Description
31:4 Reserved To ensure compatibility with future devices, always write bits to 0. More information in 2.1 Conven-
tions.
3:0 DECSTATE 0x0 RWH Shows the current decoder state
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25.5.14 LESENSE_SENSORSTATE - Decoder input register (Async Reg)
For more information about Asynchronous Registers, see 5.2.4 Access to Low Energy Peripherals (Asynchronous Registers).
Offset Bit Position
0x034
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
16
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
Reset
0x0
Access
RWH
Name
SENSORSTATE
Bit Name Reset Access Description
31:4 Reserved To ensure compatibility with future devices, always write bits to 0. More information in 2.1 Conven-
tions.
3:0 SENSORSTATE 0x0 RWH Shows the status of sensors chosen as input to the decoder
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25.5.15 LESENSE_IDLECONF - GPIO Idle phase configuration (Async Reg)
For more information about Asynchronous Registers, see 5.2.4 Access to Low Energy Peripherals (Asynchronous Registers).
Offset Bit Position
0x038
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
16
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
Reset
0x0
0x0
0x0
0x0
0x0
0x0
0x0
0x0
0x0
0x0
0x0
0x0
0x0
0x0
0x0
0x0
Access
RW
RW
RW
RW
RW
RW
RW
RW
RW
RW
RW
RW
RW
RW
RW
RW
Name
CH15
CH14
CH13
CH12
CH11
CH10
CH9
CH8
CH7
CH6
CH5
CH4
CH3
CH2
CH1
CH0
Bit Name Reset Access Description
31:30 CH15 0x0 RW Channel 15 idle phase configuration
Value Mode Description
0 DISABLE CH15 output is disabled in idle phase
1 HIGH CH15 output is high in idle phase
2 LOW CH15 output is low in idle phase
3 DACCH1 CH15 output is connected to DAC CH1 output in idle phase
29:28 CH14 0x0 RW Channel 14 idle phase configuration
Value Mode Description
0 DISABLE CH14 output is disabled in idle phase
1 HIGH CH14 output is high in idle phase
2 LOW CH14 output is low in idle phase
3 DACCH1 CH14 output is connected to DAC CH1 output in idle phase
27:26 CH13 0x0 RW Channel 13 idle phase configuration
Value Mode Description
0 DISABLE CH13 output is disabled in idle phase
1 HIGH CH13 output is high in idle phase
2 LOW CH13 output is low in idle phase
3 DACCH1 CH13 output is connected to DAC CH1 output in idle phase
25:24 CH12 0x0 RW Channel 12 idle phase configuration
Value Mode Description
0 DISABLE CH12 output is disabled in idle phase
1 HIGH CH12 output is high in idle phase
2 LOW CH12 output is low in idle phase
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Bit Name Reset Access Description
3 DACCH1 CH12 output is connected to DAC CH1 output in idle phase
23:22 CH11 0x0 RW Channel 11 idle phase configuration
Value Mode Description
0 DISABLE CH11 output is disabled in idle phase
1 HIGH CH11 output is high in idle phase
2 LOW CH11 output is low in idle phase
21:20 CH10 0x0 RW Channel 10 idle phase configuration
Value Mode Description
0 DISABLE CH10 output is disabled in idle phase
1 HIGH CH10 output is high in idle phase
2 LOW CH10 output is low in idle phase
19:18 CH9 0x0 RW Channel 9 idle phase configuration
Value Mode Description
0 DISABLE CH9 output is disabled in idle phase
1 HIGH CH9 output is high in idle phase
2 LOW CH9 output is low in idle phase
17:16 CH8 0x0 RW Channel 8 idle phase configuration
Value Mode Description
0 DISABLE CH8 output is disabled in idle phase
1 HIGH CH8 output is high in idle phase
2 LOW CH8 output is low in idle phase
15:14 CH7 0x0 RW Channel 7 idle phase configuration
Value Mode Description
0 DISABLE CH7 output is disabled in idle phase
1 HIGH CH7 output is high in idle phase
2 LOW CH7 output is low in idle phase
13:12 CH6 0x0 RW Channel 6 idle phase configuration
Value Mode Description
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Bit Name Reset Access Description
0 DISABLE CH6 output is disabled in idle phase
1 HIGH CH6 output is high in idle phase
2 LOW CH6 output is low in idle phase
11:10 CH5 0x0 RW Channel 5 idle phase configuration
Value Mode Description
0 DISABLE CH5 output is disabled in idle phase
1 HIGH CH5 output is high in idle phase
2 LOW CH5 output is low in idle phase
9:8 CH4 0x0 RW Channel 4 idle phase configuration
Value Mode Description
0 DISABLE CH4 output is disabled in idle phase
1 HIGH CH4 output is high in idle phase
2 LOW CH4 output is low in idle phase
7:6 CH3 0x0 RW Channel 3 idle phase configuration
Value Mode Description
0 DISABLE CH3 output is disabled in idle phase
1 HIGH CH3 output is high in idle phase
2 LOW CH3 output is low in idle phase
3 DACCH0 CH3 output is connected to DAC CH0 output in idle phase
5:4 CH2 0x0 RW Channel 2 idle phase configuration
Value Mode Description
0 DISABLE CH2 output is disabled in idle phase
1 HIGH CH2 output is high in idle phase
2 LOW CH2 output is low in idle phase
3 DACCH0 CH2 output is connected to DAC CH0 output in idle phase
3:2 CH1 0x0 RW Channel 1 idle phase configuration
Value Mode Description
0 DISABLE CH1 output is disabled in idle phase
1 HIGH CH1 output is high in idle phase
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Bit Name Reset Access Description
2 LOW CH1 output is low in idle phase
3 DACCH0 CH1 output is connected to DAC CH0 output in idle phase
1:0 CH0 0x0 RW Channel 0 idle phase configuration
Value Mode Description
0 DISABLE CH0 output is disabled in idle phase
1 HIGH CH0 output is high in idle phase
2 LOW CH0 output is low in idle phase
3 DACCH0 CH0 output is connected to DAC CH0 output in idle phase
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25.5.16 LESENSE_ALTEXCONF - Alternative excite pin configuration (Async Reg)
For more information about Asynchronous Registers, see 5.2.4 Access to Low Energy Peripherals (Asynchronous Registers).
Offset Bit Position
0x03C
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
16
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
Reset
0
0
0
0
0
0
0
0
0x0
0x0
0x0
0x0
0x0
0x0
0x0
0x0
Access
RW
RW
RW
RW
RW
RW
RW
RW
RW
RW
RW
RW
RW
RW
RW
RW
Name
AEX7
AEX6
AEX5
AEX4
AEX3
AEX2
AEX1
AEX0
IDLECONF7
IDLECONF6
IDLECONF5
IDLECONF4
IDLECONF3
IDLECONF2
IDLECONF1
IDLECONF0
Bit Name Reset Access Description
31:24 Reserved To ensure compatibility with future devices, always write bits to 0. More information in 2.1 Conven-
tions.
23 AEX7 0 RW ALTEX7 always excite enable
22 AEX6 0 RW ALTEX6 always excite enable
21 AEX5 0 RW ALTEX5 always excite enable
20 AEX4 0 RW ALTEX4 always excite enable
19 AEX3 0 RW ALTEX3 always excite enable
18 AEX2 0 RW ALTEX2 always excite enable
17 AEX1 0 RW ALTEX1 always excite enable
16 AEX0 0 RW ALTEX0 always excite enable
15:14 IDLECONF7 0x0 RW ALTEX7 idle phase configuration
Value Mode Description
0 DISABLE ALTEX7 output is disabled in idle phase
1 HIGH ALTEX7 output is high in idle phase
2 LOW ALTEX7 output is low in idle phase
13:12 IDLECONF6 0x0 RW ALTEX6 idle phase configuration
Value Mode Description
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Bit Name Reset Access Description
0 DISABLE ALTEX6 output is disabled in idle phase
1 HIGH ALTEX6 output is high in idle phase
2 LOW ALTEX6 output is low in idle phase
11:10 IDLECONF5 0x0 RW ALTEX5 idle phase configuration
Value Mode Description
0 DISABLE ALTEX5 output is disabled in idle phase
1 HIGH ALTEX5 output is high in idle phase
2 LOW ALTEX5 output is low in idle phase
9:8 IDLECONF4 0x0 RW ALTEX4 idle phase configuration
Value Mode Description
0 DISABLE ALTEX4 output is disabled in idle phase
1 HIGH ALTEX4 output is high in idle phase
2 LOW ALTEX4 output is low in idle phase
7:6 IDLECONF3 0x0 RW ALTEX3 idle phase configuration
Value Mode Description
0 DISABLE ALTEX3 output is disabled in idle phase
1 HIGH ALTEX3 output is high in idle phase
2 LOW ALTEX3 output is low in idle phase
5:4 IDLECONF2 0x0 RW ALTEX2 idle phase configuration
Value Mode Description
0 DISABLE ALTEX2 output is disabled in idle phase
1 HIGH ALTEX2 output is high in idle phase
2 LOW ALTEX2 output is low in idle phase
3:2 IDLECONF1 0x0 RW ALTEX1 idle phase configuration
Value Mode Description
0 DISABLE ALTEX1 output is disabled in idle phase
1 HIGH ALTEX1 output is high in idle phase
2 LOW ALTEX1 output is low in idle phase
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Bit Name Reset Access Description
1:0 IDLECONF0 0x0 RW ALTEX0 idle phase configuration
Value Mode Description
0 DISABLE ALTEX0 output is disabled in idle phase
1 HIGH ALTEX0 output is high in idle phase
2 LOW ALTEX0 output is low in idle phase
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25.5.17 LESENSE_IF - Interrupt Flag Register
Offset Bit Position
0x040
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
16
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
Reset
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
Access
R
R
R
R
R
R
R
R
R
R
R
R
R
R
R
R
R
R
R
R
R
R
R
Name
CNTOF
BUFOF
BUFLEVEL
BUFDATAV
DECERR
DEC
SCANCOMPLETE
CH15
CH14
CH13
CH12
CH11
CH10
CH9
CH8
CH7
CH6
CH5
CH4
CH3
CH2
CH1
CH0
Bit Name Reset Access Description
31:23 Reserved To ensure compatibility with future devices, always write bits to 0. More information in 2.1 Conven-
tions.
22 CNTOF 0 R
Set when the LESENSE counter overflows.
21 BUFOF 0 R
Set when the result buffer overflows
20 BUFLEVEL 0 R
Set when the data buffer is full.
19 BUFDATAV 0 R
Set when data is available in the result buffer.
18 DECERR 0 R
Set when the decoder detects an error
17 DEC 0 R
Set when the decoder has issued and interrupt request
16 SCANCOMPLETE 0 R
Set when a scan sequence is completed
15 CH15 0 R
Set when channel 15 triggers
14 CH14 0 R
Set when channel 14 triggers
13 CH13 0 R
Set when channel 13 triggers
12 CH12 0 R
Set when channel 12 triggers
11 CH11 0 R
Set when channel 11 triggers
10 CH10 0 R
Set when channel 10 triggers
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Bit Name Reset Access Description
9 CH9 0 R
Set when channel 9 triggers
8 CH8 0 R
Set when channel 8 triggers
7 CH7 0 R
Set when channel 7 triggers
6 CH6 0 R
Set when channel 6 triggers
5 CH5 0 R
Set when channel 5 triggers
4 CH4 0 R
Set when channel 4 triggers
3 CH3 0 R
Set when channel 3 triggers
2 CH2 0 R
Set when channel 2 triggers
1 CH1 0 R
Set when channel 1 triggers
0 CH0 0 R
Set when channel 0 triggers
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25.5.18 LESENSE_IFC - Interrupt Flag Clear Register
Offset Bit Position
0x044
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
16
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
Reset
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
Access
(R)W1
(R)W1
(R)W1
(R)W1
(R)W1
(R)W1
(R)W1
(R)W1
(R)W1
(R)W1
(R)W1
(R)W1
(R)W1
(R)W1
(R)W1
(R)W1
(R)W1
(R)W1
(R)W1
(R)W1
(R)W1
(R)W1
(R)W1
Name
CNTOF
BUFOF
BUFLEVEL
BUFDATAV
DECERR
DEC
SCANCOMPLETE
CH15
CH14
CH13
CH12
CH11
CH10
CH9
CH8
CH7
CH6
CH5
CH4
CH3
CH2
CH1
CH0
Bit Name Reset Access Description
31:23 Reserved To ensure compatibility with future devices, always write bits to 0. More information in 2.1 Conven-
tions.
22 CNTOF 0 (R)W1
Write to 1 to clear CNTOF interrupt flag
21 BUFOF 0 (R)W1
Write to 1 to clear BUFOF interrupt flag
20 BUFLEVEL 0 (R)W1
Write to 1 to clear BUFLEVEL interrupt flag
19 BUFDATAV 0 (R)W1
Write to 1 to clear BUFDATAV interrupt flag
18 DECERR 0 (R)W1
Write to 1 to clear DECERR interrupt flag
17 DEC 0 (R)W1
Write to 1 to clear DEC interrupt flag
16 SCANCOMPLETE 0 (R)W1
Write to 1 to clear SCANCOMPLETE interrupt flag
15 CH15 0 (R)W1
Write to 1 to clear CH15 interrupt flag
14 CH14 0 (R)W1
Write to 1 to clear CH14 interrupt flag
13 CH13 0 (R)W1
Write to 1 to clear CH13 interrupt flag
12 CH12 0 (R)W1
Write to 1 to clear CH12 interrupt flag
11 CH11 0 (R)W1
Write to 1 to clear CH11 interrupt flag
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Bit Name Reset Access Description
10 CH10 0 (R)W1
Write to 1 to clear CH10 interrupt flag
9 CH9 0 (R)W1
Write to 1 to clear CH9 interrupt flag
8 CH8 0 (R)W1
Write to 1 to clear CH8 interrupt flag
7 CH7 0 (R)W1
Write to 1 to clear CH7 interrupt flag
6 CH6 0 (R)W1
Write to 1 to clear CH6 interrupt flag
5 CH5 0 (R)W1
Write to 1 to clear CH5 interrupt flag
4 CH4 0 (R)W1
Write to 1 to clear CH4 interrupt flag
3 CH3 0 (R)W1
Write to 1 to clear CH3 interrupt flag
2 CH2 0 (R)W1
Write to 1 to clear CH2 interrupt flag
1 CH1 0 (R)W1
Write to 1 to clear CH1 interrupt flag
0 CH0 0 (R)W1
Write to 1 to clear CH0 interrupt flag
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25.5.19 LESENSE_IFS - Interrupt Flag Set Register
Offset Bit Position
0x048
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
16
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
Reset
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
Access
W1
W1
W1
W1
W1
W1
W1
W1
W1
W1
W1
W1
W1
W1
W1
W1
W1
W1
W1
W1
W1
W1
W1
Name
CNTOF
BUFOF
BUFLEVEL
BUFDATAV
DECERR
DEC
SCANCOMPLETE
CH15
CH14
CH13
CH12
CH11
CH10
CH9
CH8
CH7
CH6
CH5
CH4
CH3
CH2
CH1
CH0
Bit Name Reset Access Description
31:23 Reserved To ensure compatibility with future devices, always write bits to 0. More information in 2.1 Conven-
tions.
22 CNTOF 0 W1
Write to 1 to set the CNTOF interrupt flag
21 BUFOF 0 W1
Write to 1 to set the BUFOF interrupt flag
20 BUFLEVEL 0 W1
Write to 1 to set the BUFLEVEL interrupt flag
19 BUFDATAV 0 W1
Write to 1 to set the BUFDATAV interrupt flag
18 DECERR 0 W1
Write to 1 to set the DECERR interrupt flag
17 DEC 0 W1
Write to 1 to set the DEC interrupt flag
16 SCANCOMPLETE 0 W1
Write to 1 to set the SCANCOMPLETE interrupt flag
15 CH15 0 W1
Write to 1 to set the CH15 interrupt flag
14 CH14 0 W1
Write to 1 to set the CH14 interrupt flag
13 CH13 0 W1
Write to 1 to set the CH13 interrupt flag
12 CH12 0 W1
Write to 1 to set the CH12 interrupt flag
11 CH11 0 W1
Write to 1 to set the CH11 interrupt flag
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Bit Name Reset Access Description
10 CH10 0 W1
Write to 1 to set the CH10 interrupt flag
9 CH9 0 W1
Write to 1 to set the CH9 interrupt flag
8 CH8 0 W1
Write to 1 to set the CH8 interrupt flag
7 CH7 0 W1
Write to 1 to set the CH7 interrupt flag
6 CH6 0 W1
Write to 1 to set the CH6 interrupt flag
5 CH5 0 W1
Write to 1 to set the CH5 interrupt flag
4 CH4 0 W1
Write to 1 to set the CH4 interrupt flag
3 CH3 0 W1
Write to 1 to set the CH3 interrupt flag
2 CH2 0 W1
Write to 1 to set the CH2 interrupt flag
1 CH1 0 W1
Write to 1 to set the CH1 interrupt flag
0 CH0 0 W1
Write to 1 to set the CH0 interrupt flag
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25.5.20 LESENSE_IEN - Interrupt Enable Register
Offset Bit Position
0x04C
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
16
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
Reset
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
Access
RW
RW
RW
RW
RW
RW
RW
RW
RW
RW
RW
RW
RW
RW
RW
RW
RW
RW
RW
RW
RW
RW
RW
Name
CNTOF
BUFOF
BUFLEVEL
BUFDATAV
DECERR
DEC
SCANCOMPLETE
CH15
CH14
CH13
CH12
CH11
CH10
CH9
CH8
CH7
CH6
CH5
CH4
CH3
CH2
CH1
CH0
Bit Name Reset Access Description
31:23 Reserved To ensure compatibility with future devices, always write bits to 0. More information in 2.1 Conven-
tions.
22 CNTOF 0 RW
Set to enable interrupt on the CNTOF interrupt flag
21 BUFOF 0 RW
Set to enable interrupt on the BUFOF interrupt flag
20 BUFLEVEL 0 RW
Set to enable interrupt on the BUFLEVEL interrupt flag
19 BUFDATAV 0 RW
Set to enable interrupt on the BUFDATAV interrupt flag
18 DECERR 0 RW
Set to enable interrupt on the DECERR interrupt flag
17 DEC 0 RW
Set to enable interrupt on the DEC interrupt flag
16 SCANCOMPLETE 0 RW
Set to enable interrupt on the SCANCOMPLETE interrupt flag
15 CH15 0 RW
Set to enable interrupt on the CH15 interrupt flag
14 CH14 0 RW
Set to enable interrupt on the CH14 interrupt flag
13 CH13 0 RW
Set to enable interrupt on the CH13 interrupt flag
12 CH12 0 RW
Set to enable interrupt on the CH12 interrupt flag
11 CH11 0 RW
Set to enable interrupt on the CH11 interrupt flag
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Bit Name Reset Access Description
10 CH10 0 RW
Set to enable interrupt on the CH10 interrupt flag
9 CH9 0 RW
Set to enable interrupt on the CH9 interrupt flag
8 CH8 0 RW
Set to enable interrupt on the CH8 interrupt flag
7 CH7 0 RW
Set to enable interrupt on the CH7 interrupt flag
6 CH6 0 RW
Set to enable interrupt on the CH6 interrupt flag
5 CH5 0 RW
Set to enable interrupt on the CH5 interrupt flag
4 CH4 0 RW
Set to enable interrupt on the CH4 interrupt flag
3 CH3 0 RW
Set to enable interrupt on the CH3 interrupt flag
2 CH2 0 RW
Set to enable interrupt on the CH2 interrupt flag
1 CH1 0 RW
Set to enable interrupt on the CH1 interrupt flag
0 CH0 0 RW
Set to enable interrupt on the CH0 interrupt flag
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25.5.21 LESENSE_SYNCBUSY - Synchronization Busy Register
Offset Bit Position
0x050
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
16
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
Reset
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
Access
R
R
R
R
R
R
R
R
R
R
R
R
R
R
R
R
R
R
R
R
R
R
R
R
Name
EVAL
INTERACT
TIMING
DATA
TCONFB
TCONFA
POWERDOWN
ROUTE
ALTEXCONF
IDLECONF
SENSORSTATE
DECSTATE
CURCH
BUFDATA
PTR
STATUS
SCANRES
CHEN
CMD
BIASCTRL
DECCTRL
PERCTRL
TIMCTRL
CTRL
Bit Name Reset Access Description
31:27 Reserved To ensure compatibility with future devices, always write bits to 0. More information in 2.1 Conven-
tions.
26 EVAL 0 R LESENSE_CHx_EVAL Register Busy
Set when the value written to LESENSE_CHx_EVAL is being synchronized.
25 INTERACT 0 R LESENSE_CHx_INTERACT Register Busy
Set when the value written to LESENSE_CHx_INTERACT is being synchronized.
24 TIMING 0 R LESENSE_CHx_TIMING Register Busy
Set when the value written to LESENSE_CHx_TIMING is being synchronized.
23 DATA 0 R LESENSE_BUFx_DATA Register Busy
Set when the value written to LESENSE_BUFx_DATA is being synchronized.
22 TCONFB 0 R LESENSE_STx_TCONFB Register Busy
Set when the value written to LESENSE_STx_TCONFB is being synchronized.
21 TCONFA 0 R LESENSE_STx_TCONFA Register Busy
Set when the value written to LESENSE_STx_TCONFA is being synchronized.
20:18 Reserved To ensure compatibility with future devices, always write bits to 0. More information in 2.1 Conven-
tions.
17 POWERDOWN 0 R LESENSE_POWERDOWN Register Busy
Set when the value written to LESENSE_POWERDOWN is being synchronized.
16 ROUTE 0 R LESENSE_ROUTE Register Busy
Set when the value written to LESENSE_ROUTE is being synchronized.
15 ALTEXCONF 0 R LESENSE_ALTEXCONF Register Busy
Set when the value written to LESENSE_ALTEXCONF is being synchronized.
14 IDLECONF 0 R LESENSE_IDLECONF Register Busy
Set when the value written to LESENSE_IDLECONF is being synchronized.
13 SENSORSTATE 0 R LESENSE_SENSORSTATE Register Busy
Set when the value written to LESENSE_SENSORSTATE is being synchronized.
12 DECSTATE 0 R LESENSE_DECSTATE Register Busy
Set when the value written to LESENSE_DECSTATE is being synchronized.
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Bit Name Reset Access Description
11 CURCH 0 R LESENSE_CURCH Register Busy
Set when the value written to LESENSE_CURCH is being synchronized.
10 BUFDATA 0 R LESENSE_BUFDATA Register Busy
Set when the value written to LESENSE_BUFDATA is being synchronized.
9 PTR 0 R LESENSE_PTR Register Busy
Set when the value written to LESENSE_PTR is being synchronized.
8 STATUS 0 R LESENSE_STATUS Register Busy
Set when the value written to LESENSE_STATUS is being synchronized.
7 SCANRES 0 R LESENSE_SCANRES Register Busy
Set when the value written to LESENSE_SCANRES is being synchronized.
6 CHEN 0 R LESENSE_CHEN Register Busy
Set when the value written to LESENSE_CHEN is being synchronized.
5 CMD 0 R LESENSE_CMD Register Busy
Set when the value written to LESENSE_CMD is being synchronized.
4 BIASCTRL 0 R LESENSE_BIASCTRL Register Busy
Set when the value written to LESENSE_BIASCTRL is being synchronized.
3 DECCTRL 0 R LESENSE_DECCTRL Register Busy
Set when the value written to LESENSE_DECCTRL is being synchronized.
2 PERCTRL 0 R LESENSE_PERCTRL Register Busy
Set when the value written to LESENSE_PERCTRL is being synchronized.
1 TIMCTRL 0 R LESENSE_TIMCTRL Register Busy
Set when the value written to LESENSE_TIMCTRL is being synchronized.
0 CTRL 0 R LESENSE_CTRL Register Busy
Set when the value written to LESENSE_CTRL is being synchronized.
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25.5.22 LESENSE_ROUTE - I/O Routing Register (Async Reg)
For more information about Asynchronous Registers, see 5.2.4 Access to Low Energy Peripherals (Asynchronous Registers).
Offset Bit Position
0x054
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
16
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
Reset
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
Access
RW
RW
RW
RW
RW
RW
RW
RW
RW
RW
RW
RW
RW
RW
RW
RW
RW
RW
RW
RW
RW
RW
RW
RW
Name
ALTEX7PEN
ALTEX6PEN
ALTEX5PEN
ALTEX4PEN
ALTEX3PEN
ALTEX2PEN
ALTEX1PEN
ALTEX0PEN
CH15PEN
CH14PEN
CH13PEN
CH12PEN
CH11PEN
CH10PEN
CH9PEN
CH8PEN
CH7PEN
CH6PEN
CH5PEN
CH4PEN
CH3PEN
CH2PEN
CH1PEN
CH0PEN
Bit Name Reset Access Description
31:24 Reserved To ensure compatibility with future devices, always write bits to 0. More information in 2.1 Conven-
tions.
23 ALTEX7PEN 0 RW ALTEX7 Pin Enable
22 ALTEX6PEN 0 RW ALTEX6 Pin Enable
21 ALTEX5PEN 0 RW ALTEX5 Pin Enable
20 ALTEX4PEN 0 RW ALTEX4 Pin Enable
19 ALTEX3PEN 0 RW ALTEX3 Pin Enable
18 ALTEX2PEN 0 RW ALTEX2 Pin Enable
17 ALTEX1PEN 0 RW ALTEX1 Pin Enable
16 ALTEX0PEN 0 RW ALTEX0 Pin Enable
15 CH15PEN 0 RW CH15 Pin Enable
14 CH14PEN 0 RW CH14 Pin Enable
13 CH13PEN 0 RW CH13 Pin Enable
12 CH12PEN 0 RW CH12 Pin Enable
11 CH11PEN 0 RW CH11 Pin Enable
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Bit Name Reset Access Description
10 CH10PEN 0 RW CH10 Pin Enable
9 CH9PEN 0 RW CH9 Pin Enable
8 CH8PEN 0 RW CH8 Pin Enable
7 CH7PEN 0 RW CH7 Pin Enable
6 CH6PEN 0 RW CH6 Pin Enable
5 CH5PEN 0 RW CH5 Pin Enable
4 CH4PEN 0 RW CH4 Pin Enable
3 CH3PEN 0 RW CH3 Pin Enable
2 CH2PEN 0 RW CH2 Pin Enable
1 CH1PEN 0 RW CH0 Pin Enable
0 CH0PEN 0 RW CH0 Pin Enable
25.5.23 LESENSE_POWERDOWN - LESENSE RAM power-down register (Async Reg)
For more information about Asynchronous Registers, see 5.2.4 Access to Low Energy Peripherals (Asynchronous Registers).
Offset Bit Position
0x058
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
16
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
Reset
0
Access
RW
Name
RAM
Bit Name Reset Access Description
31:1 Reserved To ensure compatibility with future devices, always write bits to 0. More information in 2.1 Conven-
tions.
0 RAM 0 RW LESENSE RAM power-down
Shut off power to the LESENSE RAM. Once it is powered down, it cannot be powered up again
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25.5.24 LESENSE_STx_TCONFA - State transition configuration A (Async Reg)
For more information about Asynchronous Registers, see 5.2.4 Access to Low Energy Peripherals (Asynchronous Registers).
Offset Bit Position
0x200
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
16
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
Reset
X
X
0xX
0xX
0xX
0xX
Access
RW
RW
RW
RW
RW
RW
Name
CHAIN
SETIF
PRSACT
NEXTSTATE
MASK
COMP
Bit Name Reset Access Description
31:19 Reserved To ensure compatibility with future devices, always write bits to 0. More information in 2.1 Conven-
tions.
18 CHAIN X RW Enable state descriptor chaining
When set, descriptor in the next location will also be evaluated
17 Reserved To ensure compatibility with future devices, always write bits to 0. More information in 2.1 Conven-
tions.
16 SETIF X RW Set interrupt flag enable
Set interrupt flag when sensor state equals COMP
15 Reserved To ensure compatibility with future devices, always write bits to 0. More information in 2.1 Conven-
tions.
14:12 PRSACT 0xX RW Configure transition action
Configure which action to perform when sensor state equals COMP
DECCTRL_PRSCNT
= 0
Mode Value Description
NONE 0 No PRS pulses generated
PRS0 1 Generate pulse on LESPRS0
PRS1 2 Generate pulse on LESPRS1
PRS01 3 Generate pulse on LESPRS0 and LESPRS1
PRS2 4 Generate pulse on LESPRS2
PRS02 5 Generate pulse on LESPRS0 and LESPRS2
PRS12 6 Generate pulse on LESPRS1 and LESPRS2
PRS012 7 Generate pulse on LESPRS0, LESPRS1 and LESPRS2
DECCTRL_PRSCNT
= 1
NONE 0 Do not count
UP 1 Count up
DOWN 2 Count down
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Bit Name Reset Access Description
PRS2 4 Generate pulse on LESPRS2
UPANDPRS2 5 Count up and generate pulse on LESPRS2.
DOWNANDPRS2 6 Count down and generate pulse on LESPRS2.
11:8 NEXTSTATE 0xX RW Next state index
Index of next state to be entered if the sensor state equals COMP
7:4 MASK 0xX RW Sensor mask
Set bit X to exclude sensor X from evaluation.
3:0 COMP 0xX RW Sensor compare value
State transition is triggered when sensor state equals COMP
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25.5.25 LESENSE_STx_TCONFB - State transition configuration B (Async Reg)
For more information about Asynchronous Registers, see 5.2.4 Access to Low Energy Peripherals (Asynchronous Registers).
Offset Bit Position
0x204
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
16
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
Reset
X
0xX
0xX
0xX
0xX
Access
RW
RW
RW
RW
RW
Name
SETIF
PRSACT
NEXTSTATE
MASK
COMP
Bit Name Reset Access Description
31:17 Reserved To ensure compatibility with future devices, always write bits to 0. More information in 2.1 Conven-
tions.
16 SETIF X RW Set interrupt flag
Set interrupt flag when sensor state equals COMP
15 Reserved To ensure compatibility with future devices, always write bits to 0. More information in 2.1 Conven-
tions.
14:12 PRSACT 0xX RW Configure transition action
Configure which action to perform when sensor state equals COMP
DECCTRL_PRSCNT
= 0
Mode Value Description
NONE 0 No PRS pulses generated
PRS0 1 Generate pulse on PRS0
PRS1 2 Generate pulse on PRS1
PRS01 3 Generate pulse on PRS0 and PRS1
PRS2 4 Generate pulse on PRS2
PRS02 5 Generate pulse on PRS0 and PRS2
PRS12 6 Generate pulse on PRS1 and PRS2
PRS012 7 Generate pulse on PRS0, PRS1 and PRS2
DECCTRL_PRSCNT
= 1
NONE 0 Do not count
UP 1 Count up
DOWN 2 Count down
PRS2 4 Generate pulse on PRS2
UPANDPRS2 5 Count up and generate pulse on PRS2.
DOWNANDPRS2 6 Count down and generate pulse on PRS2.
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Bit Name Reset Access Description
11:8 NEXTSTATE 0xX RW Next state index
Index of next state to be entered if the sensor state equals COMP
7:4 MASK 0xX RW Sensor mask
Set bit X to exclude sensor X from evaluation.
3:0 COMP 0xX RW Sensor compare value
State transition is triggered when sensor state equals COMP
25.5.26 LESENSE_BUFx_DATA - Scan results (Async Reg)
For more information about Asynchronous Registers, see 5.2.4 Access to Low Energy Peripherals (Asynchronous Registers).
Offset Bit Position
0x280
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
16
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
Reset
0xXXXX
Access
RW
Name
DATA
Bit Name Reset Access Description
31:16 Reserved To ensure compatibility with future devices, always write bits to 0. More information in 2.1 Conven-
tions.
15:0 DATA 0xXXXX RW Scan result buffer
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25.5.27 LESENSE_CHx_TIMING - Scan configuration (Async Reg)
For more information about Asynchronous Registers, see 5.2.4 Access to Low Energy Peripherals (Asynchronous Registers).
Offset Bit Position
0x2C0
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
16
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
Reset
0xXX
0xXX
0xXX
Access
RW
RW
RW
Name
MEASUREDLY
SAMPLEDLY
EXTIME
Bit Name Reset Access Description
31:20 Reserved To ensure compatibility with future devices, always write bits to 0. More information in 2.1 Conven-
tions.
19:13 MEASUREDLY 0xXX RW Set measure delay
Configure measure delay. Sensor measuring is delayed for MEASUREDLY+1 EXCLK cycles.
12:6 SAMPLEDLY 0xXX RW Set sample delay
Configure sample delay. Sampling will occur after SAMPLEDLY+1 SAMPLECLK cycles.
5:0 EXTIME 0xXX RW Set excitation time
Configure excitation time. Excitation will last EXTIME+1 EXCLK cycles.
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25.5.28 LESENSE_CHx_INTERACT - Scan configuration (Async Reg)
For more information about Asynchronous Registers, see 5.2.4 Access to Low Energy Peripherals (Asynchronous Registers).
Offset Bit Position
0x2C4
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
16
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
Reset
X
X
X
0xX
0xX
X
0xXXX
Access
RW
RW
RW
RW
RW
RW
RW
Name
ALTEX
SAMPLECLK
EXCLK
EXMODE
SETIF
SAMPLE
ACMPTHRES
Bit Name Reset Access Description
31:20 Reserved To ensure compatibility with future devices, always write bits to 0. More information in 2.1 Conven-
tions.
19 ALTEX X RW Use alternative excite pin
If set, alternative excite pin will be used for excitation
18 SAMPLECLK X RW Select clock used for timing of sample delay
Value Mode Description
0 LFACLK LFACLK will be used for timing
1 AUXHFRCO AUXHFRCO will be used for timing
17 EXCLK X RW Select clock used for excitation timing
Value Mode Description
0 LFACLK LFACLK will be used for timing
1 AUXHFRCO AUXHFRCO will be used for timing
16:15 EXMODE 0xX RW Set GPIO mode
GPIO mode for the excitation phase of the scan sequence. Note that DACOUT is only available on channels 0, 1, 2, 3, 12,
13, 14, and 15.
Value Mode Description
0 DISABLE Disabled
1 HIGH Push Pull, GPIO is driven high
2 LOW Push Pull, GPIO is driven low
3 DACOUT DAC output
14:13 SETIF 0xX RW Enable interrupt generation
Select interrupt generation mode for CHx interrupt flag.
Value Mode Description
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Bit Name Reset Access Description
0 NONE No interrupt is generated
1 LEVEL Set interrupt flag if the sensor triggers.
2 POSEDGE Set interrupt flag on positive edge on the sensor state
3 NEGEDGE Set interrupt flag on negative edge on the sensor state
12 SAMPLE X RW Select sample mode
Select if ACMP output or counter output should be used in comparison
Value Mode Description
0 COUNTER Counter output will be used in comparison
1 ACMP ACMP output will be used in comparison
11:0 ACMPTHRES 0xXXX RW Set ACMP threshold
Select ACMP threshold.
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25.5.29 LESENSE_CHx_EVAL - Scan configuration (Async Reg)
For more information about Asynchronous Registers, see 5.2.4 Access to Low Energy Peripherals (Asynchronous Registers).
Offset Bit Position
0x2C8
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
16
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
Reset
X
X
X
X
0xXXXX
Access
RW
RW
RW
RW
RW
Name
SCANRESINV
STRSAMPLE
DECODE
COMP
COMPTHRES
Bit Name Reset Access Description
31:20 Reserved To ensure compatibility with future devices, always write bits to 0. More information in 2.1 Conven-
tions.
19 SCANRESINV X RW Enable inversion of result
If set, the bit stored in SCANRES will be inverted.
18 STRSAMPLE X RW Select if counter result should be stored
If set, the counter value will be stored and available in the result buffer
17 DECODE X RW Send result to decoder
If set, the result from this channel will be shifted into the decoder register.
16 COMP X RW Select mode for counter comparison
Set compare mode
CH_INTER-
ACT_SAMPLE =
COUNTER
Mode Value Description
LESS 0 Comparison evaluates to 1 if counter value is less than COMPTHRES.
GE 1 Comparison evaluates to 1 if counter value is greater than, or equal to
COMPTHRES.
CH_INTER-
ACT_SAMPLE =
ACMP
LESS 0 Comparison evaluates to 1 if the ACMP output is 0.
GE 1 Comparison evaluates to 1 if the ACMP output is 1.
15:0 COMPTHRES 0xXXXX RW Decision threshold for counter
Set counter threshold
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26. ACMP - Analog Comparator
43210
Quick Facts
What?
The ACMP (Analog Comparator) compares two ana-
log signals and returns a digital value telling which is
greater.
Why?
Applications often do not need to know the exact
value of an analog signal, only if it has passed a cer-
tain threshold. Often the voltage must be monitored
continuously, which requires extremely low power
consumption.
How?
Available down to Energy Mode 3 and using as little
as 100 nA, the ACMP can wake up the system when
input signals pass the threshold. The analog compa-
rator can compare two analog signals or one analog
signal and a highly configurable internal reference.
26.1 Introduction
The Analog Comparator is used to compare the voltage of two analog inputs, with a digital output indicating which input voltage is high-
er. Inputs can either be one of the selectable internal references or from external pins. Response time and thereby also the current
consumption can be configured by altering the current supply to the comparator.
26.2 Features
• 8 selectable external positive inputs
• 8 selectable external negative inputs
• 5 selectable internal negative inputs
• Internal 1.25 V bandgap
• Internal 2.5 V bandgap
• VDD scaled by 64 selectable factors
• DAC channel 0 and 1
• Low power mode for internal VDD and bandgap references
• Selectable hysteresis
• 8 levels between 0 and ±70 mV
• Selectable response time
• Asynchronous interrupt generation on selectable edges
• Rising edge
• Falling edge
• Both edges
• Operational in EM0-EM3
• Dedicated capacitive sense mode with up to 8 inputs
• Adjustable internal resistor
• Configurable inversion of comparator output
• Configurable output when inactive
• Comparator output direct on PRS
• Comparator output on GPIO through alternate functionality
• Output inversion available
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26.3 Functional Description
An overview of the ACMP is shown in the following figure.
Scaler
1.25 V
2.5 V
ACMPn_CH7
ACMPn_CH0
ACMPn_CH6
ACMPn_CH5
ACMPn_CH4
ACMPn_CH3
ACMPn_CH2
ACMPn_CH1
Output to PRS
Output to GPIO
VDDLEVELNEGSEL
POSSEL
BIASPROG
HYSTSEL
EN ACMPACT
ACMPOUT
INACTVAL
Warm-up
counter
GPIOINV
000 -
111
0000
-
1011
VDD
1
0
Read only registers
Read/Write registers
LPREF
Edge interrupt
Warmup interrupt
HALFBIAS
FULLBIAS
VDD_SCALED
Figure 26.1. ACMP Overview
The comparator has two analog inputs, one positive and one negative. When the comparator is active, the output indicates which of the
two input voltages is higher. When the voltage on the positive input is higher than the voltage on the negative input, the digital output is
high and vice versa.
The output of the comparator can be read in the ACMPOUT bit in ACMPn_STATUS. It is possible to switch inputs while the comparator
is enabled, but all other configuration should only be changed while the comparator is disabled.
26.3.1 Warm-up Time
The analog comparator is enabled by setting the EN bit in ACMPn_CTRL. When this bit is set, the comparator must stabilize before
becoming active and the outputs can be used. This time period is called the warm-up time. The warm-up time is a configurable number
of peripheral clock (HFPERCLK) cycles, set in WARMTIME, which should be set to at least 10 µs but lengthens to up to 1ms if LPREF
is enabled. The ACMP should always start in active mode and then enable the LPREF after warm-up time. When the comparator is
enabled and warmed up, the ACMPACT bit in ACMPn_STATUS will indicate that the comparator is active. The output value when the
comparator is inactive is set to the value in INACTVAL in ACMPn_CTRL (see previous figure).
An edge interrupt will be generated after the warm-up time if edge interrupt is enabled and the value set in INACTVAL is different from
ACMPOUT after warm-up.
One should wait until the warm-up period is over before entering EM2 or EM3, otherwise no comparator interrupts will be detected.
EM1 can still be entered during warm-up. After the warm-up period is completed, interrupts will be detected in EM2 and EM3.
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26.3.2 Response Time
There is a delay from when the actual input voltage changes polarity, to when the output toggles. This period is called the response
time and can be altered by increasing or decreasing the bias current to the comparator through the BIASPROG, FULLBIASPROG and
HALFBIAS fields in the ACMPn_CTRL register, as illustrated in the following table. Setting the HALFBIAS bit in ACMPn_CTRL effec-
tively halves the current. Setting a lower bias current will result in lower power consumption, but a longer response time.
If the FULLBIAS bit is set, the highest hysteresis level should be used to avoid glitches on the output.
Table 26.1. Bias Configuration
BIASPROG Bias Current (µA), HYSTSEL=0
FULLBIAS=0, HALFBIAS=1 FULLBIAS=0, HALFBIAS=0 FULLBIAS=1, HALFBIAS=1 FULLBIAS=1, HALFBIAS=0
0b0000 0.05 0.1 3.3 6.5
0b0001 0.1 0.2 6.5 13
0b0010 0.2 0.4 13 26
0b0011 0.3 0.6 20 39
0b0100 0.4 0.8 26 52
0b0101 0.5 1.0 33 65
0b0110 0.6 1.2 39 78
0b0111 0.7 1.4 46 91
0b1000 1.0 2.0 65 130
0b1001 1.1 2.2 72 143
0b1010 1.2 2.4 78 156
0b1011 1.3 2.6 85 169
0b1100 1.4 2.8 91 182
0b1101 1.5 3.0 98 195
0b1110 1.6 3.2 104 208
0b1111 1.7 3.4 111 221
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26.3.3 Hysteresis
In the analog comparator, hysteresis can be configured to 8 different levels, including off which is level 0, through the HYSTSEL field in
ACMPn_CTRL. When the hysteresis level is set above 0, the digital output will not toggle until the positive input voltage is at a voltage
equal to the hysteresis level above or below the negative input voltage (see the following figure). This feature can be used to filter out
uninteresting input fluctuations around zero and only show changes that are big enough to breach the hysteresis threshold. Note that
the ACMP current consumption will be influenced by the selected hysteresis level and in general decrease with increasing HYSTSEL
values.
InNEG
ACMPOUT with hysteresis
InNEG +20mV
InNEG -20mV
ACMPOUT without hysteresis
Time
InPOS
Figure 26.2. 20 mV Hysteresis Selected
26.3.4 Input Selection
The POSSEL and NEGSEL fields in ACMPn_INPUTSEL controls which signals are connected to the two inputs of the comparator. 8
external pins are available for both the negative and positive input. For the negative input, 5 additional internal reference sources are
available; 1.25 V bandgap, 2.5V bandgap, DAC channel 0, DAC channel 1, and VDD. The VDD reference can be scaled by a configura-
ble factor, which is set in VDDLEVEL (in ACMPn_INPUTSEL) according to the following formula:
VDD_SCALED =VDD × VDDLEVEL
/
63
A low power reference mode can be enabled by setting the LPREF bit in ACMPn_INPUTSEL. In this mode, the power consumption in
the reference buffer (VDD and bandgap) is lowered at the cost of accuracy. Low power mode will only save power if VDD with VDDLE-
VEL higher than 0 or a bandgap reference is selected.
Normally the analog comparator input mux is disabled when the EN (in ACMPn_CTRL) bit is set low. However if the MUXEN bit in
ACMPn_CTRL is set, the mux is enabled regardless of the EN bit. This will minimize kickback noise on the mux inputs when the EN bit
is toggled.
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26.3.5 Capacitive Sense Mode
The analog comparator includes specialized hardware for capacitive sensing of passive push buttons. Such buttons are traces on PCB
laid out in a way that creates a parasitic capacitor between the button and the ground node. Because a human finger will have a small
intrinsic capacitance to ground, the capacitance of the button will increase when the button is touched. The capacitance is measured by
including the capacitor in a free-running RC oscillator (see the following figure). The frequency produced will decrease when the button
is touched compared to when it is not touched. By measuring the output frequency with a timer (e.g. through PRS), the change in ca-
pacitance can be calculated.
The analog comparator contains a complete feedback loop including an optional internal resistor. This resistor is enabled by setting the
CSRESEN bit in ACMPn_INPUTSEL. The resistance can be set to one of four values by configuring the CSRESSEL bits in
ACMPn_INPUTSEL. If the internal resistor is not enabled, the circuit will be open. The capacitive sense mode is enabled by setting the
NEGSEL field in ACMPn_INPUTSEL to CAPSENSE. The input pin is selected through the POSSEL bits in ACMPn_INPUTSEL. The
scaled VDD in the following figure can be altered by configuring the VDDLEVEL in ACMPn_INPUTSEL. It is recommended to set the
hysteresis (HYSTSEL in ACMPn_CTRL) higher than the lowest level when using the analog comparator in capacitive sense mode.
VDD/4
VDD_SCALED
Buttons
POSSEL
Figure 26.3. Capacitive Sensing Setup
26.3.6 Interrupts and PRS Output
The analog comparator includes an edge triggered interrupt flag (EDGE in ACMPn_IF). If either IRISE and/or IFALL in ACMPn_CTRL
is set, the EDGE interrupt flag will be set on rising and/or falling edge of the comparator output, respectively. An interrupt request will be
sent if the EDGE interrupt flag in ACMPn_IF is set and enabled through the EDGE bit in ACMPn_IEN. The edge interrupt can also be
used to wake up the device from EM3-EM1.
The analog comparator also includes an interrupt flag, WARMUP in ACMPn_IF, which is set when a warm-up sequence has finished.
An interrupt request will be sent if the WARMUP interrupt flag in ACMPn_IF is set and enabled through the WARMUP bit in
ACMPn_IEN.
The comparator output is also available as a PRS signal.
26.3.7 Output to GPIO
The output from the comparator is available as alternate function to the GPIO pins. Set the ACMPPEN bit in ACMPn_ROUTE to enable
output to pin, and the LOCATION bits to select output location. The GPIO-pin must also be set as output. The output to the GPIO can
be inverted by setting the GPIOINV bit in ACMPn_CTRL.
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26.4 Register Map
The offset register address is relative to the registers base address.
Offset Name Type Description
0x000 ACMPn_CTRL RW Control Register
0x004 ACMPn_INPUTSEL RW Input Selection Register
0x008 ACMPn_STATUS RStatus Register
0x00C ACMPn_IEN RW Interrupt Enable Register
0x010 ACMPn_IF RInterrupt Flag Register
0x014 ACMPn_IFS W1 Interrupt Flag Set Register
0x018 ACMPn_IFC (R)W1 Interrupt Flag Clear Register
0x01C ACMPn_ROUTE RW I/O Routing Register
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26.5 Register Description
26.5.1 ACMPn_CTRL - Control Register
Offset Bit Position
0x000
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
16
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
Reset
0
1
0x7
0
0
0x0
0x0
0
0
0
0
Access
RW
RW
RW
RW
RW
RW
RW
RW
RW
RW
RW
Name
FULLBIAS
HALFBIAS
BIASPROG
IFALL
IRISE
WARMTIME
HYSTSEL
GPIOINV
INACTVAL
MUXEN
EN
Bit Name Reset Access Description
31 FULLBIAS 0 RW Full Bias Current
Set this bit to 1 for full bias current in accordance with Table 26.1 Bias Configuration on page 859.
30 HALFBIAS 1 RW Half Bias Current
Set this bit to 1 to halve the bias current in accordance with Table 26.1 Bias Configuration on page 859.
29:28 Reserved To ensure compatibility with future devices, always write bits to 0. More information in 2.1 Conven-
tions.
27:24 BIASPROG 0x7 RW Bias Configuration
These bits control the bias current level in accordance with Table 26.1 Bias Configuration on page 859.
23:18 Reserved To ensure compatibility with future devices, always write bits to 0. More information in 2.1 Conven-
tions.
17 IFALL 0 RW Falling Edge Interrupt Sense
Set this bit to 1 to set the EDGE interrupt flag on falling edges of comparator output.
Value Mode Description
0 DISABLED Interrupt flag is not set on falling edges.
1 ENABLED Interrupt flag is set on falling edges.
16 IRISE 0 RW Rising Edge Interrupt Sense
Set this bit to 1 to set the EDGE interrupt flag on rising edges of comparator output.
Value Mode Description
0 DISABLED Interrupt flag is not set on rising edges.
1 ENABLED Interrupt flag is set on rising edges.
15:11 Reserved To ensure compatibility with future devices, always write bits to 0. More information in 2.1 Conven-
tions.
10:8 WARMTIME 0x0 RW Warm-up Time
Set analog comparator warm-up time.
Value Mode Description
0 4CYCLES 4 HFPERCLK cycles.
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Bit Name Reset Access Description
1 8CYCLES 8 HFPERCLK cycles.
2 16CYCLES 16 HFPERCLK cycles.
3 32CYCLES 32 HFPERCLK cycles.
4 64CYCLES 64 HFPERCLK cycles.
5 128CYCLES 128 HFPERCLK cycles.
6 256CYCLES 256 HFPERCLK cycles.
7 512CYCLES 512 HFPERCLK cycles.
7 Reserved To ensure compatibility with future devices, always write bits to 0. More information in 2.1 Conven-
tions.
6:4 HYSTSEL 0x0 RW Hysteresis Select
Select hysteresis level. The hysteresis levels can vary, please see the electrical characteristics for the device for more infor-
mation.
Value Mode Description
0 HYST0 No hysteresis.
1 HYST1 ~15 mV hysteresis.
2 HYST2 ~22 mV hysteresis.
3 HYST3 ~29 mV hysteresis.
4 HYST4 ~36 mV hysteresis.
5 HYST5 ~43 mV hysteresis.
6 HYST6 ~50 mV hysteresis.
7 HYST7 ~57 mV hysteresis.
3 GPIOINV 0 RW Comparator GPIO Output Invert
Set this bit to 1 to invert the comparator alternate function output to GPIO.
Value Mode Description
0 NOTINV The comparator output to GPIO is not inverted.
1 INV The comparator output to GPIO is inverted.
2 INACTVAL 0 RW Inactive Value
The value of this bit is used as the comparator output when the comparator is inactive.
Value Mode Description
0 LOW The inactive value is 0.
1 HIGH The inactive state is 1.
1 MUXEN 0 RW Input Mux Enable
Enable Input Mux. Setting the EN bit will also enable the input mux.
0 EN 0 RW Analog Comparator Enable
Enable/disable analog comparator.
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26.5.2 ACMPn_INPUTSEL - Input Selection Register
Offset Bit Position
0x004
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
16
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
Reset
0x0
0
1
0x00
0x8
0x0
Access
RW
RW
RW
RW
RW
RW
Name
CSRESSEL
CSRESEN
LPREF
VDDLEVEL
NEGSEL
POSSEL
Bit Name Reset Access Description
31:30 Reserved To ensure compatibility with future devices, always write bits to 0. More information in 2.1 Conven-
tions.
29:28 CSRESSEL 0x0 RW Capacitive Sense Mode Internal Resistor Select
These bits select the resistance value for the internal capacitive sense resistor. Resulting actual resistor values are given in
the device datasheets.
Value Mode Description
0 RES0 Internal capacitive sense resistor value 0.
1 RES1 Internal capacitive sense resistor value 1.
2 RES2 Internal capacitive sense resistor value 2.
3 RES3 Internal capacitive sense resistor value 3.
27:25 Reserved To ensure compatibility with future devices, always write bits to 0. More information in 2.1 Conven-
tions.
24 CSRESEN 0 RW Capacitive Sense Mode Internal Resistor Enable
Enable/disable the internal capacitive sense resistor.
23:17 Reserved To ensure compatibility with future devices, always write bits to 0. More information in 2.1 Conven-
tions.
16 LPREF 1 RW Low Power Reference Mode
Enable low power mode for VDD and bandgap references.
Value Description
0 Low power mode disabled.
1 Low power mode enabled.
15:14 Reserved To ensure compatibility with future devices, always write bits to 0. More information in 2.1 Conven-
tions.
13:8 VDDLEVEL 0x00 RW VDD Reference Level
Select scaling factor for VDD reference level.VDD_SCALED = VDD×VDDLEVEL/63.
7:4 NEGSEL 0x8 RW Negative Input Select
Select negative input.
Value Mode Description
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Bit Name Reset Access Description
0 CH0 Channel 0 as negative input.
1 CH1 Channel 1 as negative input.
2 CH2 Channel 2 as negative input.
3 CH3 Channel 3 as negative input.
4 CH4 Channel 4 as negative input.
5 CH5 Channel 5 as negative input.
6 CH6 Channel 6 as negative input.
7 CH7 Channel 7 as negative input.
8 1V25 1.25 V as negative input.
9 2V5 2.5 V as negative input.
10 VDD Scaled VDD as negative input.
11 CAPSENSE Capacitive sense mode.
12 DAC0CH0 DAC0 channel 0.
13 DAC0CH1 DAC0 channel 1.
3 Reserved To ensure compatibility with future devices, always write bits to 0. More information in 2.1 Conven-
tions.
2:0 POSSEL 0x0 RW Positive Input Select
Select positive input.
Value Mode Description
0 CH0 Channel 0 as positive input.
1 CH1 Channel 1 as positive input.
2 CH2 Channel 2 as positive input.
3 CH3 Channel 3 as positive input.
4 CH4 Channel 4 as positive input.
5 CH5 Channel 5 as positive input.
6 CH6 Channel 6 as positive input.
7 CH7 Channel 7 as positive input.
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26.5.3 ACMPn_STATUS - Status Register
Offset Bit Position
0x008
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
16
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
Reset
0
0
Access
R
R
Name
ACMPOUT
ACMPACT
Bit Name Reset Access Description
31:2 Reserved To ensure compatibility with future devices, always write bits to 0. More information in 2.1 Conven-
tions.
1 ACMPOUT 0 R Analog Comparator Output
Analog comparator output value.
0 ACMPACT 0 R Analog Comparator Active
Analog comparator active status.
26.5.4 ACMPn_IEN - Interrupt Enable Register
Offset Bit Position
0x00C
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
16
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
Reset
0
0
Access
RW
RW
Name
WARMUP
EDGE
Bit Name Reset Access Description
31:2 Reserved To ensure compatibility with future devices, always write bits to 0. More information in 2.1 Conven-
tions.
1 WARMUP 0 RW Warm-up Interrupt Enable
Enable/disable interrupt on finished warm-up.
0 EDGE 0 RW Edge Trigger Interrupt Enable
Enable/disable edge triggered interrupt.
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26.5.5 ACMPn_IF - Interrupt Flag Register
Offset Bit Position
0x010
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
16
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
Reset
0
0
Access
R
R
Name
WARMUP
EDGE
Bit Name Reset Access Description
31:2 Reserved To ensure compatibility with future devices, always write bits to 0. More information in 2.1 Conven-
tions.
1 WARMUP 0 R Warm-up Interrupt Flag
Indicates that the analog comparator warm-up period is finished.
0 EDGE 0 R Edge Triggered Interrupt Flag
Indicates that there has been a rising or falling edge on the analog comparator output.
26.5.6 ACMPn_IFS - Interrupt Flag Set Register
Offset Bit Position
0x014
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
16
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
Reset
0
0
Access
W1
W1
Name
WARMUP
EDGE
Bit Name Reset Access Description
31:2 Reserved To ensure compatibility with future devices, always write bits to 0. More information in 2.1 Conven-
tions.
1 WARMUP 0 W1 Warm-up Interrupt Flag Set
Write to 1 to set warm-up finished interrupt flag.
0 EDGE 0 W1 Edge Triggered Interrupt Flag Set
Write to 1 to set edge triggered interrupt flag.
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26.5.7 ACMPn_IFC - Interrupt Flag Clear Register
Offset Bit Position
0x018
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
16
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
Reset
0
0
Access
(R)W1
(R)W1
Name
WARMUP
EDGE
Bit Name Reset Access Description
31:2 Reserved To ensure compatibility with future devices, always write bits to 0. More information in 2.1 Conven-
tions.
1 WARMUP 0 (R)W1 Warm-up Interrupt Flag Clear
Write to 1 to clear warm-up finished interrupt flag.
0 EDGE 0 (R)W1 Edge Triggered Interrupt Flag Clear
Write to 1 to clear edge triggered interrupt flag.
26.5.8 ACMPn_ROUTE - I/O Routing Register
Offset Bit Position
0x01C
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
16
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
Reset
0x0
0
Access
RW
RW
Name
LOCATION
ACMPPEN
Bit Name Reset Access Description
31:11 Reserved To ensure compatibility with future devices, always write bits to 0. More information in 2.1 Conven-
tions.
10:8 LOCATION 0x0 RW I/O Location
Decides the location of the ACMP I/O pin.
Value Mode Description
0 LOC0 Location 0
1 LOC1 Location 1
2 LOC2 Location 2
7:1 Reserved To ensure compatibility with future devices, always write bits to 0. More information in 2.1 Conven-
tions.
0 ACMPPEN 0 RW ACMP Output Pin Enable
Enable/disable analog comparator output to pin.
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27. VCMP - Voltage Comparator
43210
VCMP
Interrupts
VDD > X ?
Battery
VDD < X ?
VDD
GND
Quick Facts
What?
The Voltage Supply Comparator (VCMP) monitors
the input voltage supply and generates software in-
terrupts on events using as little as 100 nA.
Why?
The VCMP can be used for simple power supply
monitoring, e.g. for a battery level indicator.
How?
The scaled power supply is compared to a program-
mable reference voltage, and an interrupt can be
generated when the supply is higher or lower than
the reference. The VCMP can also be duty-cycled
by software to further reduce the energy consump-
tion.
27.1 Introduction
The Voltage Supply Comparator is used to monitor the supply voltage from software. An interrupt can be generated when the supply
falls below or rises above a programmable threshold.
Note: Note that VCMP comes in addition to the Power-on Reset and Brown-out Detector peripherals, that both generate reset signals
when the voltage supply is insufficient for reliable operation. VCMP does not generate reset, only interrupt. Also note that the ADC is
capable of sampling the input voltage supply.
27.2 Features
• Voltage supply monitoring
• Scalable VDD in 64 steps selectable as positive comparator input
• Internal 1.25 V bandgap reference
• Low power mode for internal VDD and bandgap references
• Selectable hysteresis (two settings)
• Selectable response time
• Asynchronous interrupt generation on selectable edges
• Rising edge
• Falling edge
• Rising and Falling edges
• Operational in EM0-EM3
• Comparator output direct on PRS
• Configurable output when inactive to avoid unwanted interrupts
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.1.
’::f
—
HALFBIAS
HYSTEN
.R
.R
27.3 Functional Description
An overview of the VCMP is shown in the following figure.
1.25V
BIASPROG
HYSTEN
EN Warm-up
counter
Read only register
Read/Write registers
LPREF
Scaler
TRIGLEVEL
VDD
VCMPACT
VCMPOUT
INACTVAL
1
0
Edge interrupt
Warmup interrupt
PRS
HALFBIAS
Figure 27.1. VCMP Overview
The comparator has two analog inputs, one positive and one negative. When the comparator is active, the output indicates which of the
two input voltages is higher. When the voltage on the positive input is higher than the negative input voltage, the digital output is high
and vice versa.
The output of the comparator can be read in the VCMPOUT bit in VCMP_STATUS. Configuration registers should only be changed
while the comparator is disabled.
27.3.1 Warm-Up Time
VCMP is enabled by setting the EN bit in VCMP_CTRL. When this bit is set, the comparator must stabilize before becoming active and
the outputs can be used. This time period is called the warm-up time. The warm-up time is a configurable number of HFPERCLK cy-
cles, set in WARMTIME, which should be set to at least 10 μs. When the comparator is enabled and warmed up, the VCMPACT bit in
VCMP_STATUS will be set to indicate that the comparator is active.
As long as the comparator is not enabled or not warmed up, VCMPACT will be cleared and the comparator output value is set to the
value in INACTVAL in VCMP_CTRL.
One should wait until the warm-up period is over before entering EM2 or EM3, otherwise no comparator interrupts will be detected.
EM1 can still be entered during warm-up. After the warm-up period is completed, interrupts will be detected in EM2 and EM3.
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27.3.2 Response Time
There is a delay from when the actual input voltage changes polarity, to when the output toggles. This period is called the response
time and can be altered by increasing or decreasing the bias current to the comparator through the BIAS and HALFBIAS fields in
VCMP_CTRL as shown in the following table. Setting a lower bias current will result in lower power consumption, but a longer response
time.
Table 27.1. Bias Configuration
BIAS Bias Current (μA)
HALFBIAS=0 HALFBIAS=1
0b0000 0.1 0.05
0b0001 0.2 0.1
0b0010 0.4 0.2
0b0011 0.6 0.3
0b0100 0.8 0.4
0b0101 1.0 0.5
0b0110 1.2 0.6
0b0111 1.4 0.7
0b1000 2.0 1.0
0b1001 2.2 1.1
0b1010 2.4 1.2
0b1011 2.6 1.3
0b1100 2.8 1.4
0b1101 3.0 1.5
0b1110 3.2 1.6
0b1111 3.4 1.7
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27.3.3 Hysteresis
In the voltage supply comparator, hysteresis can be enabled by setting HYSTEN in VCMP_CTRL. When HYSTEN is set, the digital
output will not toggle until the positive input voltage is some magnitude above or below the negative input voltage. This feature can be
used to filter out uninteresting input fluctuations around zero and only show changes that are big enough to breach the hysteresis
threshold.
See the specific device data sheet for more information on the magnitude of the hysteresis.
InNEG
VCMPOUT with hysteresis
InNEG + X
InNEG - X
VCMPOUT without hysteresis
Time
InPOS
Figure 27.2. VCMP Hysteresis Enabled
27.3.4 Input Selection
The positive comparator input is always connected to the scaled power supply input. The negative comparator input is connected to the
internal 1.25 V bandgap reference. The VDD trigger level can be configured by setting the TRIGLEVEL field in VCMP_CTRL according
to the following formula:
VDD Trigger Level = 1.667V+ 0.034V× TRIGLEVEL
A low power reference mode can be enabled by setting the LPREF bit in VCMP_INPUTSEL. In this mode, the power consumption in
the reference buffer (VDD and bandgap) is lowered at the cost of accuracy.
27.3.5 Interrupts and PRS Output
The VCMP includes an edge triggered interrupt flag (EDGE in VCMP_IF). If either IRISE and/or IFALL in VCMPn_CTRL is set, the
EDGE interrupt flag will be set on rising and/or falling edge of the comparator output respectively. An interrupt request will be sent if the
EDGE interrupt flag in VCMP_IF is set and enabled through the EDGE bit in VCMPn_IEN. The edge interrupt can also be used to wake
up the device from EM3-EM1. VCMP also includes an interrupt flag, WARMUP in VCMP_IF, which is set when a warm-up sequence
has finished. An interrupt request will be sent if the WARMUP interrupt flag in VCMP_IF is set and enabled through the WARMUP bit in
VCMPn_IEN. The synchronized comparator output is also available as a PRS output signal.
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27.4 Register Map
The offset register address is relative to the registers base address.
Offset Name Type Description
0x000 VCMP_CTRL RW Control Register
0x004 VCMP_INPUTSEL RW Input Selection Register
0x008 VCMP_STATUS RStatus Register
0x00C VCMP_IEN RW Interrupt Enable Register
0x010 VCMP_IF RInterrupt Flag Register
0x014 VCMP_IFS W1 Interrupt Flag Set Register
0x018 VCMP_IFC (R)W1 Interrupt Flag Clear Register
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27.5 Register Description
27.5.1 VCMP_CTRL - Control Register
Offset Bit Position
0x000
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
16
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
Reset
1
0x7
0
0
0x0
0
0
0
Access
RW
RW
RW
RW
RW
RW
RW
RW
Name
HALFBIAS
BIASPROG
IFALL
IRISE
WARMTIME
HYSTEN
INACTVAL
EN
Bit Name Reset Access Description
31 Reserved To ensure compatibility with future devices, always write bits to 0. More information in 2.1 Conven-
tions.
30 HALFBIAS 1 RW Half Bias Current
Set this bit to 1 to halve the bias current. See Table 27.1 Bias Configuration on page 872.
29:28 Reserved To ensure compatibility with future devices, always write bits to 0. More information in 2.1 Conven-
tions.
27:24 BIASPROG 0x7 RW VCMP Bias Programming Value
These bits control the bias current level. See Table 27.1 Bias Configuration on page 872.
23:18 Reserved To ensure compatibility with future devices, always write bits to 0. More information in 2.1 Conven-
tions.
17 IFALL 0 RW Falling Edge Interrupt Sense
Set this bit to 1 to set the EDGE interrupt flag on falling edges of comparator output.
16 IRISE 0 RW Rising Edge Interrupt Sense
Set this bit to 1 to set the EDGE interrupt flag on rising edges of comparator output.
15:11 Reserved To ensure compatibility with future devices, always write bits to 0. More information in 2.1 Conven-
tions.
10:8 WARMTIME 0x0 RW Warm-Up Time
Set warm-up time
Value Mode Description
0 4CYCLES 4 HFPERCLK cycles
1 8CYCLES 8 HFPERCLK cycles
2 16CYCLES 16 HFPERCLK cycles
3 32CYCLES 32 HFPERCLK cycles
4 64CYCLES 64 HFPERCLK cycles
5 128CYCLES 128 HFPERCLK cycles
6 256CYCLES 256 HFPERCLK cycles
7 512CYCLES 512 HFPERCLK cycles
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Bit Name Reset Access Description
7:5 Reserved To ensure compatibility with future devices, always write bits to 0. More information in 2.1 Conven-
tions.
4 HYSTEN 0 RW Hysteresis Enable
Enable hysteresis.
Value Description
0 No hysteresis
1 +- Some hysteresis (see the device datasheet for more information on
the magnitude)
3 Reserved To ensure compatibility with future devices, always write bits to 0. More information in 2.1 Conven-
tions.
2 INACTVAL 0 RW Inactive Value
Configure the output value when the comparator is inactive.
1 Reserved To ensure compatibility with future devices, always write bits to 0. More information in 2.1 Conven-
tions.
0 EN 0 RW Voltage Supply Comparator Enable
Enable/disable voltage supply comparator.
27.5.2 VCMP_INPUTSEL - Input Selection Register
Offset Bit Position
0x004
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
16
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
Reset
0
0x00
Access
RW
RW
Name
LPREF
TRIGLEVEL
Bit Name Reset Access Description
31:9 Reserved To ensure compatibility with future devices, always write bits to 0. More information in 2.1 Conven-
tions.
8 LPREF 0 RW Low Power Reference
Enable/disable low power mode for VDD and bandgap reference. When using this bit, always leave it as 0 during warm-up
and then set it to 1 if desired when the warm-up is done.
7:6 Reserved To ensure compatibility with future devices, always write bits to 0. More information in 2.1 Conven-
tions.
5:0 TRIGLEVEL 0x00 RW Trigger Level
Select VDD trigger level. Vtrig = 1.667V+0.034V×TRIGLEVEL.
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27.5.3 VCMP_STATUS - Status Register
Offset Bit Position
0x008
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
16
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
Reset
0
0
Access
R
R
Name
VCMPOUT
VCMPACT
Bit Name Reset Access Description
31:2 Reserved To ensure compatibility with future devices, always write bits to 0. More information in 2.1 Conven-
tions.
1 VCMPOUT 0 R Voltage Supply Comparator Output
Voltage supply comparator output value
0 VCMPACT 0 R Voltage Supply Comparator Active
Voltage supply comparator active status.
27.5.4 VCMP_IEN - Interrupt Enable Register
Offset Bit Position
0x00C
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
16
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
Reset
0
0
Access
RW
RW
Name
WARMUP
EDGE
Bit Name Reset Access Description
31:2 Reserved To ensure compatibility with future devices, always write bits to 0. More information in 2.1 Conven-
tions.
1 WARMUP 0 RW Warm-up Interrupt Enable
Enable/disable interrupt on finished warm-up.
0 EDGE 0 RW Edge Trigger Interrupt Enable
Enable/disable edge triggered interrupt.
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27.5.5 VCMP_IF - Interrupt Flag Register
Offset Bit Position
0x010
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
16
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
Reset
0
0
Access
R
R
Name
WARMUP
EDGE
Bit Name Reset Access Description
31:2 Reserved To ensure compatibility with future devices, always write bits to 0. More information in 2.1 Conven-
tions.
1 WARMUP 0 R Warm-up Interrupt Flag
Indicates that warm-up has finished.
0 EDGE 0 R Edge Triggered Interrupt Flag
Indicates that there has been a rising and/or falling edge on the VCMP output.
27.5.6 VCMP_IFS - Interrupt Flag Set Register
Offset Bit Position
0x014
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
16
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
Reset
0
0
Access
W1
W1
Name
WARMUP
EDGE
Bit Name Reset Access Description
31:2 Reserved To ensure compatibility with future devices, always write bits to 0. More information in 2.1 Conven-
tions.
1 WARMUP 0 W1 Warm-up Interrupt Flag Set
Write to 1 to set warm-up finished interrupt flag
0 EDGE 0 W1 Edge Triggered Interrupt Flag Set
Write to 1 to set edge triggered interrupt flag
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27.5.7 VCMP_IFC - Interrupt Flag Clear Register
Offset Bit Position
0x018
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
16
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
Reset
0
0
Access
(R)W1
(R)W1
Name
WARMUP
EDGE
Bit Name Reset Access Description
31:2 Reserved To ensure compatibility with future devices, always write bits to 0. More information in 2.1 Conven-
tions.
1 WARMUP 0 (R)W1 Warm-up Interrupt Flag Clear
Write to 1 to clear warm-up finished interrupt flag
0 EDGE 0 (R)W1 Edge Triggered Interrupt Flag Clear
Write to 1 to clear edge triggered interrupt flag
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28. ADC - Analog to Digital Converter
43210
ADC ...0101110...
+
-
Quick Facts
What?
The ADC is used to convert analog signals into a
digital representation and features 8 external input
channels
Why?
In many applications there is a need to measure an-
alog signals and record them in a digital representa-
tion, without exhausting your energy source.
How?
A low power Successive Approximation Register
ADC samples up to 8 input channels in a program-
mable sequence. With the help of PRS and DMA,
the ADC can operate without CPU intervention, mini-
mizing the number of powered up resources. The
ADC can further be duty-cycled to reduce the energy
consumption.
28.1 Introduction
The ADC is a Successive Approximation Register (SAR) architecture, with a resolution of up to 12 bits at up to one million samples per
second. The integrated input mux can select inputs from 8 external pins and 6 internal signals.
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28.2 Features
• Programmable resolution (6/8/12-bit)
• 13 prescaled clock (ADC_CLK) cycles per conversion
• Maximum 1 MSPS @ 12-bit
• Maximum 1.86 MSPS @ 6-bit
• Configurable acquisition time
• Integrated prescaler
• Selectable clock division factor from 1 to 128
• 13 MHz to 32 kHz allowed for ADC_CLK
• 18 input channels
• 8 external single ended channels
• 6 internal single ended channels
• Including temperature sensor
• 4 external differential channels
• Integrated input filter
• Low pass RC filter
• Decoupling capacitor
• Left or right adjusted results
• Results in 2’s complement representation
• Differential results sign extended to 32-bit results
• Programmable scan sequence
• Up to 8 configurable samples in scan sequence
• Mask to select which pins are included in the sequence
• Triggered by software or PRS input
• One shot or repetitive mode
• Oversampling available
• Overflow interrupt flag set when overwriting unread results
• Conversion tailgating support for predictable periodic scans
• Programmable single conversion
• Triggered by software or PRS input
• Can be interleaved between two scan sequences
• One shot or repetitive mode
• Oversampling available
• Overflow interrupt flag set when overwriting unread results
• Hardware oversampling support
• 1st order accumulate and dump filt
• From 2 to 4096 oversampling ratio (OSR)
• Results in 16-bit representation
• Enabled individually for scan sequence and single sample mode
• Common OSR select
• Individually selectable voltage reference for scan and single mode
• Internal 1.25V reference
• Internal 2.5V reference
• VDD
• Internal 5 V differential reference
• Single ended external reference
• Differential external reference
• Unbuffered 2xVDD
• Support for offset and gain calibration
• Interrupt generation and/or DMA request
• Finished single conversion
• Finished scan conversion
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___—
\V\
c
Emmi»:
• Single conversion results overflow
• Scan sequence results overflow
• Loopback configuration with DAC output measurement
28.3 Functional Description
An overview of the ADC is shown in the following figure.
SAR
ADCn_CH0
ADCn_CH7
Temp
VSS
VDD
VDD/3
DAC0
ADCn_CH1
ADCn_CH2
ADCn_CH3
ADCn_CH4
ADCn_CH5
ADCn_CH6
2.5 V
1.25 V
VDD
Sequencer Result
buffer
+
-
Control
ADCn_SINGLEDAT
A
ADCn_SCANDATA
ADCn_SCANCTRL
ADCn_CTRL
ADCn_SINGLECTRL
Prescaler ADC_CLKHFPERCLKADCn
DAC1
Oversampling
filter
ADCn_CMD
ADCn_STATUS
2x(VDD-VSS)
5 V differential
Vref/2
Figure 28.1. ADC Overview
28.3.1 Clock Selection
The ADC has an internal prescaler (PRESC bits in ADCn_CTRL) which can divide the peripheral clock (HFPERCLK) by any factor be-
tween 1 and 128. Note that the resulting ADC_CLK should not be set to a higher frequency than 13 MHz and not lower than 32 kHz.
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28.3.2 Conversions
A conversion consists of two phases. The input is sampled in the acquisition phase before it is converted to digital representation during
the approximation phase. The acquisition time can be configured independently for scan and single conversions (see 28.3.7 ADC
Modes ) by setting AT in ADCn_SINGLECTRL/ADCn_SCANCTRL. The acquisition times can be set to any integer power of 2 from 1 to
256 ADC_CLK cycles.
Note: For high impedance sources the acquisition time should be adjusted to allow enough time for the internal sample capacitor to
fully charge. The minimum acquisition time for the internal temperature sensor and Vdd/3 is given in the electrical characteristics for the
device.
The analog to digital converter core uses one clock cycle per output bit in the approximation phase.
Tconv = (TA+ N) × OSR
TA equals the number of acquisition cycles and N is the resolution. OSR is the oversampling ratio (see 28.3.7.7 Oversampling ). The
minimum conversion time is 7 ADC_CYCLES with 6 bit resolution and 13 ADC_CYCLES with 12 bit resolution. The maximum conver-
sion time is 1097728 ADC_CYCLES with the longest acquisition time, 12 bit resolution and highest oversampling rate.
Bit 11 Bit 10 Bit 9 Bit 8 Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0
SINGLEAT/
SCANAT
6-bit value ready 8-bit value ready 12-bit value ready
HFPERCLKADCn
Prescaled clock (4x)
ADC action
Figure 28.2. ADC Conversion Timing
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28.3.3 Warm-Up Time
The ADC needs to be warmed up some time before a conversion can take place. This time period is called the warm-up time. When
enabling the ADC or changing references between samples, the ADC is automatically warmed up for 1 μs and an additional 5 μs if the
bandgap is selected as reference.
Normally, the ADC will be warmed up only when samples are requested and is shut off when there are no more samples waiting. How-
ever, if lower latency is needed, configuring the WARMUPMODE field in ADCn_CTRL allows the ADC and/or reference to stay warm
between samples, eliminating the need for warm-up. The following figure shows the analog power consumption in scenarios using the
different WARMUPMODE settings.
Only the bandgap reference selected for scan mode can be kept warm. If a different bandgap reference is selected for single mode, the
warm-up time still applies.
• NORMAL: ADC and references are shut off when there are no samples waiting. a) the following figure shows this mode used with an
internal bandgap reference. Figure d) shows this mode when using VDD or an external reference.
• FASTBG: Bandgap warm-up is eliminated, but with reduced reference accuracy. d) the following figure shows this mode used with
an internal bandgap reference.
• KEEPSCANREFWARM: The reference selected for scan mode is kept warm. The ADC will still need to be warmed up before con-
version. b) the following figure shows this mode used with an internal bandgap reference.
• KEEPADCWARM: The ADC and the reference selected for scan mode is kept warm. c) the following figure shows this mode used
with an internal bandgap reference.
The minimum warm-up times are given in μs. The timing is done automatically by the ADC, given that a proper time base is given in the
TIMEBASE bits in ADCn_CTRL. The TIMEBASE must be set to the number of HFPERCLK which corresponds to at least 1 μs. The
TIMEBASE only affects the timing of the warm-up sequence and not the ADC_CLK.
When entering Energy Modes 2 or 3, the ADC must be stopped and WARMUPMODE in ADCn_CTRL written to 0.
ADC enabled Conversion trigger Conversion trigger
Power
Power
Power
Time
Time
ADC warm-up
ADC conversion
Bandgap reference warm-up
5 µs
1 µs 1 µs
5 µs5 µs
5 µs
NORMAL
KEEPSCANREFWARM
(w SCANREF = internal bandgap)
KEEPADCWARM
(w SCANREF = internal bandgap)
Power
Time
FASTBG
(w SCANREF = any)
or
NORMAL
(w SCANREF = external or VDD)
a)
b)
c)
d)
Figure 28.3. ADC Analog Power Consumption With Different WARMUPMODE Settings
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“H
28.3.4 Input Selection
The ADC is connected to 8 external input pins, which can be selected as 8 different single ended inputs or 4 differential inputs. In addi-
tion, 6 single ended internal inputs can be selected. The available selections are given in the register description for ADCn_SIN-
GLECTRL and ADCn_SCANCTRL.
For offset calibration purposes it is possible to internally short the differential ADC inputs and thereby measure a 0 V differential. Differ-
ential 0 V is selected by writing the DIFF bit to 1 and INPUTSEL to 4 in ADCn_SINGLECTRL. Calibration is described in detail in
28.3.10 Calibration.
Note: When VDD/3 is sampled, the acquisition time should be above a lower limit. The reader is referred to the datasheet for minimum
VDD/3 acquisition time.
28.3.4.1 Input Filtering
The selected input signal can be filtered, either through an internal low pass RC filter or an internal decoupling capacitor. The different
filter configurations can be enabled through the LPFMODE bits in ADCn_CTRL. For maximum SNR, LPFMODE is recommended set to
DECAP, with a cutoff frequency of 31.5 MHz.
The RC input filter configuration is given in the following figure. The resistance and capacitance values are given in the electrical char-
acteristics for the device, named RADCFILT and CADCFILT respectively.
ADC
Input
R
C
Figure 28.4. ADC RC Input Filter Configuration
28.3.4.2 Temperature Measurement
The ADC includes an internal temperature sensor. This sensor is characterized during production and the temperature readout from the
ADC at production temperature, ADC0_TEMP_0_READ_1V25, is given in the Device Information (DI) page. The production tempera-
ture, CAL_TEMP_0, is also given in this page. The temperature gradient, TGRAD_ADCTH (mV/degree Celsius), for the sensor is found
in the datasheet for the devices. By selecting 1.25 V internal reference and measuring the internal temperature sensor with 12 bit reso-
lution, the temperature can be calculated according to the following formula:
TCELSIUS = CAL_TEMP_0 - (ADC0_TEMP_0_READ_1V25 - ADC_result) × Vref
4096 × TGRAD_ADCTH
Note: The minimum acquisition time for the temperature reference is found in the electrical characteristics for the device.
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28.3.5 Reference Selection
The reference voltage can be selected from these sources:
• 1.25 V internal bandgap
• 2.5 V internal bandgap
• VDD
• 5 V internal differential bandgap
• External single ended input from Ch. 6
• Differential input, 2x(Ch. 6 - Ch. 7)
• Unbuffered 2xVDD
• The 2.5 V reference needs a supply voltage higher than 2.5 V
• The differential 5 V reference needs a supply voltage higher than 2.75 V
Since the 2xVDD differential reference is unbuffered, it is directly connected to the ADC supply voltage and more susceptible to supply
noise. The VDD reference is buffered both in single ended and differential mode.
If a differential reference with a larger range than the supply voltage is combined with single ended measurements, for instance the 5 V
internal reference, the full ADC range will not be available because the maximum input voltage is limited by the maximum electrical
ratings.
Note: Single ended measurements with the external differential reference are not supported.
28.3.6 Programming of Bias Current
The bias current of the bandgap reference and the ADC comparator can be scaled by the BIASPROG, HALFBIAS and COMPBIAS bit
fields of the ADCn_BIASPROG register. The BIASPROG and HALFBIAS bitfields scale the current of ADC bandgap reference, and the
COMPBIAS bits provide an additional bias programming for the ADC comparator as illustrated in the following figure. The electrical
characteristics given in the datasheet require the bias configuration to be set to the default values, where no other bias values are giv-
en.
COMPBIAS
BIASPROG
HALFBIAS
Reference
Current
Internal bandgap
reference
ADC
Comparator
Figure 28.5. ADC Bias Programming
The minimum value of the BIASPROG and COMPBIAS bitfields of the ADCn_BIASPROG register (i.e. BIASPROG=0b0000, COMP-
BIAS=0b0000) represent the minimum bias currents. Similarly BIASPROG=0b1111 and COMPBIAS=0b1111 represent the maximum
bias currents. Additionally, the bias current defined by the BIASPROG setting can be halved by setting the HALFBIAS bit of the
ADCn_BIASPROG register.
The bias current settings should only be changed while the ADC is disabled.
28.3.7 ADC Modes
The ADC contains two separate programmable modes, one single sample mode and one scan mode. Both modes have separate con-
figuration and result registers and can be set up to run only once per trigger or repetitively. The scan mode has priority over the single
sample mode. However, if scan sequence is running, a triggered single sample will be interleaved between two scan samples.
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28.3.7.1 Single Sample Mode
The single sample mode can be used to convert a single sample either once per trigger or repetitively. The configuration of the single
sample mode is done in the ADCn_SINGLECTRL register and the results are found in the ADCn_SINGLEDATA register. The SIN-
GLEDV bit in ADCn_STATUS is set high when there is valid data in the result register and is cleared when the data is read. The single
mode results can also be read through ADCn_SINGLEDATAP without SINGLEDV being cleared. DIFF in ADCn_SINGLECTRL selects
whether differential or single ended inputs are used and INPUTSEL selects input pin(s).
28.3.7.2 Scan Mode
The scan mode is used to perform sweeps of the inputs. The configuration of the scan sequence is done in the ADCn_SCANCTRL
register and the results are found in the ADCn_SCANDATA register. The SCANDV bit in ADCn_STATUS is set high when there is valid
data in the result register and is cleared when the data is read. The scan mode results can also be read through ADCn_SCANDATAP
without SCANDV being cleared. The inputs included in the sequence are defined by a the mask in INPUTMASK in ADCn_SCANCTRL.
When the scan sequence is triggered, the sequence samples all inputs that are included in the mask, starting at the lowest pin number.
DIFF in ADCn_SCANCTRL selects whether single ended or differential inputs are used.
28.3.7.3 Conversion Tailgating
The scan sequence has priority over the single sample mode. However, a scan trigger will not interrupt in the middle of a single conver-
sion. If a scan sequence is triggered by a timer on a periodic basis, single sample just before a scan trigger can delay the start of the
scan sequence, thus causing jitter in sample rate. To solve this, conversion tailgating can be chosen by setting TAILGATE in
ADCn_CTRL. When this bit is set, any triggered single samples will wait for the next scan sequence to finish before activating (see the
following figure). The single sample will then follow immediately after the scan sequence. In this way, the scan sequence will always
start immediately when triggered, if the period between the scan triggers is big enough to allow any single samples that might be trig-
gered to finish in between the scan sequences.
SINGLESTART
SCANSTART
SCANACT
ADC action
SINGLEACT
Scan Single Scan Single Scan
Figure 28.6. ADC Conversion Tailgating
28.3.7.4 Conversion Trigger
The conversion modes can be activated by writing a 1 to the SINGLESTART or SCANSTART bit in the ADCn_CMD register. The con-
versions can be stopped by writing a 1 to the SINGLESTOP or SCANSTOP bit in the ADCn_CMD register. A START command will
have priority over a stop command. When the ADC is stopped in the middle of a conversion, the result buffer is cleared. The SINGLE-
ACT and SCANACT bits in ADCn_STATUS are set high when the modes are actively converting or have pending conversions.
It is also possible to trigger conversions from PRS signals. The system requires one HFPERCLK cycle pulses to trigger conversions.
Setting PRSEN in ADCn_SINGLECTRL/ADCn_SCANCTRL enables triggering from PRS input. Which PRS channel to listen to is de-
fined by PRSSEL in ADCn_SINGLECTRL/ADCn_SCANCTRL. When PRS trigger is selected, it is still possible to trigger the conversion
from software. The reader is referred to the PRS datasheet for more information on how to set up the PRS channels.
Note: The conversion settings should not be changed while the ADC is running as this can lead to unpredictable behavior.
The prescaled clock phase is always reset by a triggered conversion as long as a conversion is not ongoing. This gives predictable
latency from the time of the trigger to the time the conversion starts, regardless of when in the prescaled clock cycle the trigger occur.
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28.3.7.5 Results
The results are presented in 2’s complement form and the format for differential and single ended mode is given in the following tables.
If differential mode is selected, the results are sign extended up to 32-bit (shown in Table 28.4 ADC Results Representation on page
890).
Table 28.1. ADC Single Ended Conversion
Input/Reference Results
Binary Hex Value
1 111111111111 FFF
0.5 011111111111 7FF
1/4096 000000000001 001
0 000000000000 000
Table 28.2. ADC Differential Conversion
Input/Reference Results
Binary Hex Value
0.5 011111111111 7FF
0.25 001111111111 3FF
1/2048 000000000001 001
0 000000000000 000
-1/2048 111111111111 FFF
-0.25 101111111111 BFF
-0.5 100000000000 800
28.3.7.6 Resolution
The ADC gives out 12-bit results, by default. However, if full 12-bit resolution is not needed, it is possible to speed up the conversion by
selecting a lower resolution (N = 6 or 8 bits). For more information on the accuracy of the ADC, the reader is referred to the electrical
characteristics section for the device.
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28.3.7.7 Oversampling
To achieve higher accuracy, hardware oversampling can be enabled individually for each mode (Set RES in ADCn_SINGLECTRL/
ADCn_SCANCTRL to 0x3). The oversampling rate (OVSRSEL in ADCn_CTRL) can be set to any integer power of 2 from 2 to 4096
and the configuration is shared between the scan and single sample mode (OVSRSEL field in ADCn_CTRL).
With oversampling, each selected input is sampled a number (given by the OVSR) of times, and the results are filtered by a first order
accumulate and dump filter to form the end result. The data presented in the ADCn_SINGLEDATA and ADCn_SCANDATA registers
are the direct contents of the accumulation register (sum of samples). However, if the oversampling ratio is set higher than 16x, the
accumulated results are shifted to fit the MSB in bit 15 as shown in the following table.
Table 28.3. Oversampling Result Shifting and Resolution
Oversampling Setting # Right Shifts Result Resolution # Bits
2x 0 13
4x 0 14
8x 0 15
16x 0 16
32x 1 16
64x 2 16
128x 3 16
256x 4 16
512x 5 16
1024x 6 16
2048x 7 16
4096x 8 16
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28.3.7.8 Adjustment
By default, all results are right adjusted, with the LSB of the result in bit position 0 (zero). In differential mode the signed bit is extended
up to bit 31, but in single ended mode the bits above the result are read as 0. By setting ADJ in ADCn_SINGLECTRL/
ADCn_SCANCTRL, the results are left adjusted as shown in the table below. When left adjusted, the MSB is always placed on bit 15
and sign extended to bit 31. All bits below the conversion result are read as 0 (zero).
Table 28.4. ADC Results Representation
Adjustment
Resolution
Bit
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
16
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
Right
12
11
11
11
11
11
11
11
11
11
11
11
11
11
11
11
11
11
11
11
11
11
10
9
8
7
6
5
4
3
2
1
0
8
7
7
7
7
7
7
7
7
7
7
7
7
7
7
7
7
7
7
7
7
7
7
7
7
7
6
5
4
3
2
1
0
6
5
5
5
5
5
5
5
5
5
5
5
5
5
5
5
5
5
5
5
5
5
5
5
5
5
5
5
4
3
2
1
0
OVS
15
15
15
15
15
15
15
15
15
15
15
15
15
15
15
15
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
Left
12
11
11
11
11
11
11
11
11
11
11
11
11
11
11
11
11
11
10
9
8
7
6
5
4
3
2
1
0
—
—
—
—
8
7
7
7
7
7
7
7
7
7
7
7
7
7
7
7
7
7
6
5
4
3
2
1
0
—
—
—
—
—
—
—
—
6
5
5
5
5
5
5
5
5
5
5
5
5
5
5
5
5
5
4
3
2
1
0
—
—
—
—
—
—
—
—
—
—
OVS
15
15
15
15
15
15
15
15
15
15
15
15
15
15
15
15
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
28.3.8 Interrupts, PRS Output
The single and scan modes have separate interrupt flags indicating finished conversions. Setting one of these flags will result in an
ADC interrupt if the corresponding interrupt enable bit is set in ADCn_IEN.
In addition to the finished conversion flags, there is a scan and single sample result overflow flag which signalizes that a result from a
scan sequence or single sample has been overwritten before being read.
A finished conversion will result in a one HFPERCLK cycle pulse which is output to the Peripheral Reflex System (PRS).
28.3.9 DMA Request
The ADC has two DMA request lines, SINGLE and SCAN, which are set when a single or scan conversion has completed. The request
are cleared when the corresponding single or scan result register is read.
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28.3.10 Calibration
The ADC supports offset and gain calibration to correct errors due to process and temperature variations. This must be done individual-
ly for each reference used. The ADC calibration (ADCn_CAL) register contains four register fields for calibrating offset and gain for both
single and scan mode. The gain and offset calibration are done in single mode, but the resulting calibration values can be used for both
single and scan mode.
Gain and offset for the 1V25, 2V5 and VDD references are calibrated during production and the calibration values for these can be
found in the Device Information page. During reset, the gain and offset calibration registers are loaded with the production calibration
values for the 1V25 reference.
The SCANGAIN and SINGLEGAIN calibration fields are not used when the unbuffered differential 2xVDD reference is selected.
The effects of changing the calibration register values are given in the following table. Step by step calibration procedures for offset and
gain are given in 28.3.10.1 Offset Calibration and 28.3.10.2 Gain Calibration.
Table 28.5. Calibration Register Effect
Calibration Register ADC Result Calibration Binary Value Calibration Hex Value
Offset Lowest Output 0111111 3F
Highest Output 1000000 40
Gain Lowest Output 0000000 00
Highest Output 1111111 7F
The offset calibration register expects a signed 2’s complement value with negative effect. A high value gives a low ADC reading.
The gain calibration register expects an unsigned value with positive effect. A high value gives a high ADC reading.
28.3.10.1 Offset Calibration
Offset calibration must be performed prior to gain calibration. Follow these steps for the offset calibration in single mode:
1. Select wanted reference by setting the REF bitfield of the ADCn_SINGLECTRL register.
2. Set the AT bitfield of the ADCn_SINGLECTRL register to 16CYCLES.
3. Set the INPUTSEL bitfield of the ADCn_SINGLECTRL register to DIFF0, and set the DIFF bitfield to 1 for enabling differential in-
put. Since the input voltage is 0, the expected ADC output is the half of the ADC code range as it is in differential mode.
4. A binary search is used to find the offset calibration value. Set the SINGLESTART bit in the ADCn_CMD register and read the
ADCn_SINGLEDATA register. The result of the binary search is written to the SINGLEOFFSET field of the ADCn_CAL register.
28.3.10.2 Gain Calibration
Offset calibration must be performed prior to gain calibration. The Gain Calibration is done in the following manner:
1. Select an external ADC channel (a differential channel can also be used).
2. Apply an external voltage on the selected ADC input channel. This voltage should correspond to the top of the ADC range.
3. A binary search is used to find the gain calibration value. Set the SINGLESTART bit in the ADCn_CTRL register and read the
ADCn_SINGLEDATA register. The target value is ideally the top of the ADC range, but it is recommended to use a value a couple
of LSBs below in order to avoid overshooting. The result of the binary search is written to the SINGLEGAIN field of the ADCn_CAL
register.
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28.4 Register Map
The offset register address is relative to the registers base address.
Offset Name Type Description
0x000 ADCn_CTRL RW Control Register
0x004 ADCn_CMD W1 Command Register
0x008 ADCn_STATUS RStatus Register
0x00C ADCn_SINGLECTRL RW Single Sample Control Register
0x010 ADCn_SCANCTRL RW Scan Control Register
0x014 ADCn_IEN RW Interrupt Enable Register
0x018 ADCn_IF RInterrupt Flag Register
0x01C ADCn_IFS W1 Interrupt Flag Set Register
0x020 ADCn_IFC (R)W1 Interrupt Flag Clear Register
0x024 ADCn_SINGLEDATA R(a) Single Conversion Result Data
0x028 ADCn_SCANDATA R(a) Scan Conversion Result Data
0x02C ADCn_SINGLEDATAP RSingle Conversion Result Data Peek Register
0x030 ADCn_SCANDATAP RScan Sequence Result Data Peek Register
0x034 ADCn_CAL RW Calibration Register
0x03C ADCn_BIASPROG RW Bias Programming Register
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28.5 Register Description
28.5.1 ADCn_CTRL - Control Register
Offset Bit Position
0x000
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
16
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
Reset
0x0
0x1F
0x00
0x0
0
0x0
Access
RW
RW
RW
RW
RW
RW
Name
OVSRSEL
TIMEBASE
PRESC
LPFMODE
TAILGATE
WARMUPMODE
Bit Name Reset Access Description
31:28 Reserved To ensure compatibility with future devices, always write bits to 0. More information in 2.1 Conven-
tions.
27:24 OVSRSEL 0x0 RW Oversample Rate Select
Select oversampling rate. Oversampling must be enabled for each mode for this setting to take effect.
Value Mode Description
0 X2 2 samples for each conversion result
1 X4 4 samples for each conversion result
2 X8 8 samples for each conversion result
3 X16 16 samples for each conversion result
4 X32 32 samples for each conversion result
5 X64 64 samples for each conversion result
6 X128 128 samples for each conversion result
7 X256 256 samples for each conversion result
8 X512 512 samples for each conversion result
9 X1024 1024 samples for each conversion result
10 X2048 2048 samples for each conversion result
11 X4096 4096 samples for each conversion result
23 Reserved To ensure compatibility with future devices, always write bits to 0. More information in 2.1 Conven-
tions.
22:16 TIMEBASE 0x1F RW Time Base
Set time base used for ADC warm up sequence according to the HFPERCLK frequency. The time base is defined as a
number of HFPERCLK cycles which should be set equal to or higher than 1us.
Value Description
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Bit Name Reset Access Description
TIMEBASE ADC warm-up is set to
TIMEBASE+1
HFPERCLK clock cy-
cles and bandgap
warm-up is set to
5x(TIMEBASE+1)
HFPERCLK cycles.
15 Reserved To ensure compatibility with future devices, always write bits to 0. More information in 2.1 Conven-
tions.
14:8 PRESC 0x00 RW Prescaler Setting
Select clock division factor.
Value Description
PRESC Clock division factor of
PRESC+1.
7:6 Reserved To ensure compatibility with future devices, always write bits to 0. More information in 2.1 Conven-
tions.
5:4 LPFMODE 0x0 RW Low Pass Filter Mode
These bits control the filtering of the ADC input. Details on the filter characteristics can be found in the device datasheets.
Value Mode Description
0 BYPASS No filter or decoupling capacitor
1 DECAP On chip decoupling capacitor selected
2 RCFILT On chip RC filter selected
3 TAILGATE 0 RW Conversion Tailgating
Enable/disable conversion tailgating.
Value Description
0 Scan sequence has priority, but can be delayed by ongoing single
samples.
1 Scan sequence has priority and single samples will only start immedi-
ately after scan sequence.
2 Reserved To ensure compatibility with future devices, always write bits to 0. More information in 2.1 Conven-
tions.
1:0 WARMUPMODE 0x0 RW Warm-up Mode
Select Warm-up Mode for ADC
Value Mode Description
0 NORMAL ADC is shut down after each conversion
1 FASTBG Bandgap references do not need warm up, but have reduced accuracy.
2 KEEPSCANREFWARM Reference selected for scan mode is kept warm.
3 KEEPADCWARM ADC is kept warmed up and scan reference is kept warm
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28.5.2 ADCn_CMD - Command Register
Offset Bit Position
0x004
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
16
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
Reset
0
0
0
0
Access
W1
W1
W1
W1
Name
SCANSTOP
SCANSTART
SINGLESTOP
SINGLESTART
Bit Name Reset Access Description
31:4 Reserved To ensure compatibility with future devices, always write bits to 0. More information in 2.1 Conven-
tions.
3 SCANSTOP 0 W1 Scan Sequence Stop
Write a 1 to stop scan sequence.
2 SCANSTART 0 W1 Scan Sequence Start
Write a 1 to start scan sequence.
1 SINGLESTOP 0 W1 Single Conversion Stop
Write a 1 to stop single conversion.
0 SINGLESTART 0 W1 Single Conversion Start
Write to 1 to start single conversion.
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28.5.3 ADCn_STATUS - Status Register
Offset Bit Position
0x008
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
16
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
Reset
0x0
0
0
0
0
0
0
0
Access
R
R
R
R
R
R
R
R
Name
SCANDATASRC
SCANDV
SINGLEDV
WARM
SCANREFWARM
SINGLEREFWARM
SCANACT
SINGLEACT
Bit Name Reset Access Description
31:27 Reserved To ensure compatibility with future devices, always write bits to 0. More information in 2.1 Conven-
tions.
26:24 SCANDATASRC 0x0 R Scan Data Source
This value indicates from which input channel the results in the ADCn_SCANDATA register originates.
Value Mode Description
0 CH0 Single ended mode: SCANDATA result originates from ADCn_CH0.
Differential mode: SCANDATA result originates from ADCn_CH0-
ADCn_CH1
1 CH1 Single ended mode: SCANDATA result originates from ADCn_CH1.
Differential mode: SCANDATA result originates from
ADCn_CH2_ADCn_CH3
2 CH2 Single ended mode: SCANDATA result originates from ADCn_CH2.
Differential mode: SCANDATA result originates from ADCn_CH4-
ADCn_CH5
3 CH3 Single ended mode: SCANDATA result originates from ADCn_CH3.
Differential mode: SCANDATA result originates from ADCn_CH6-
ADCn_CH7
4 CH4 SCANDATA result originates from ADCn_CH4
5 CH5 SCANDATA result originates from ADCn_CH5
6 CH6 SCANDATA result originates from ADCn_CH6
7 CH7 SCANDATA result originates from ADCn_CH7
23:18 Reserved To ensure compatibility with future devices, always write bits to 0. More information in 2.1 Conven-
tions.
17 SCANDV 0 R Scan Data Valid
Scan conversion data is valid.
16 SINGLEDV 0 R Single Sample Data Valid
Single conversion data is valid.
15:13 Reserved To ensure compatibility with future devices, always write bits to 0. More information in 2.1 Conven-
tions.
12 WARM 0 R ADC Warmed Up
ADC is warmed up.
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Bit Name Reset Access Description
11:10 Reserved To ensure compatibility with future devices, always write bits to 0. More information in 2.1 Conven-
tions.
9 SCANREFWARM 0 R Scan Reference Warmed Up
Reference selected for scan mode is warmed up.
8 SINGLEREFWARM 0 R Single Reference Warmed Up
Reference selected for single mode is warmed up.
7:2 Reserved To ensure compatibility with future devices, always write bits to 0. More information in 2.1 Conven-
tions.
1 SCANACT 0 R Scan Conversion Active
Scan sequence is active or has pending conversions.
0 SINGLEACT 0 R Single Conversion Active
Single conversion is active or has pending conversions.
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28.5.4 ADCn_SINGLECTRL - Single Sample Control Register
Offset Bit Position
0x00C
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
16
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
Reset
0x0
0
0x0
0x0
0x0
0x0
0
0
0
Access
RW
RW
RW
RW
RW
RW
RW
RW
RW
Name
PRSSEL
PRSEN
AT
REF
INPUTSEL
RES
ADJ
DIFF
REP
Bit Name Reset Access Description
31:28 PRSSEL 0x0 RW Single Sample PRS Trigger Select
Select PRS trigger for single sample.
Value Mode Description
0 PRSCH0 PRS ch 0 triggers single sample
1 PRSCH1 PRS ch 1 triggers single sample
2 PRSCH2 PRS ch 2 triggers single sample
3 PRSCH3 PRS ch 3 triggers single sample
4 PRSCH4 PRS ch 4 triggers single sample
5 PRSCH5 PRS ch 5 triggers single sample
6 PRSCH6 PRS ch 6 triggers single sample
7 PRSCH7 PRS ch 7 triggers single sample
8 PRSCH8 PRS ch 8 triggers single sample
9 PRSCH9 PRS ch 9 triggers single sample
10 PRSCH10 PRS ch 10 triggers single sample
11 PRSCH11 PRS ch 11 triggers single sample
27:25 Reserved To ensure compatibility with future devices, always write bits to 0. More information in 2.1 Conven-
tions.
24 PRSEN 0 RW Single Sample PRS Trigger Enable
Enabled/disable PRS trigger of single sample.
Value Description
0 Single sample is not triggered by PRS input
1 Single sample is triggered by PRS input selected by PRSSEL
23:20 AT 0x0 RW Single Sample Acquisition Time
Select the acquisition time for single sample.
Value Mode Description
0 1CYCLE 1 ADC_CLK cycle acquisition time for single sample
1 2CYCLES 2 ADC_CLK cycles acquisition time for single sample
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Bit Name Reset Access Description
2 4CYCLES 4 ADC_CLK cycles acquisition time for single sample
3 8CYCLES 8 ADC_CLK cycles acquisition time for single sample
4 16CYCLES 16 ADC_CLK cycles acquisition time for single sample
5 32CYCLES 32 ADC_CLK cycles acquisition time for single sample
6 64CYCLES 64 ADC_CLK cycles acquisition time for single sample
7 128CYCLES 128 ADC_CLK cycles acquisition time for single sample
8 256CYCLES 256 ADC_CLK cycles acquisition time for single sample
19 Reserved To ensure compatibility with future devices, always write bits to 0. More information in 2.1 Conven-
tions.
18:16 REF 0x0 RW Single Sample Reference Selection
Select reference to ADC single sample mode.
Value Mode Description
0 1V25 Internal 1.25 V reference
1 2V5 Internal 2.5 V reference
2 VDD Buffered VDD
3 5VDIFF Internal differential 5 V reference
4 EXTSINGLE Single ended external reference from ADCn_CH6
5 2XEXTDIFF Differential external reference, 2x(ADCn_CH6 - ADCn_CH7)
6 2XVDD Unbuffered 2xVDD
15:12 Reserved To ensure compatibility with future devices, always write bits to 0. More information in 2.1 Conven-
tions.
11:8 INPUTSEL 0x0 RW Single Sample Input Selection
Select input to ADC single sample mode in either single ended mode or differential mode.
DIFF = 0
Mode Value Description
CH0 0 ADCn_CH0
CH1 1 ADCn_CH1
CH2 2 ADCn_CH2
CH3 3 ADCn_CH3
CH4 4 ADCn_CH4
CH5 5 ADCn_CH5
CH6 6 ADCn_CH6
CH7 7 ADCn_CH7
TEMP 8 Temperature reference
VDDDIV3 9 VDD/3
VDD 10 VDD
VSS 11 VSS
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Bit Name Reset Access Description
VREFDIV2 12 VREF/2
DAC0OUT0 13 DAC0 output 0
DAC0OUT1 14 DAC0 output 1
DIFF = 1
Mode Value Description
CH0CH1 0 Positive input: ADCn_CH0 Negative input: ADCn_CH1
CH2CH3 1 Positive input: ADCn_CH2 Negative input: ADCn_CH3
CH4CH5 2 Positive input: ADCn_CH4 Negative input: ADCn_CH5
CH6CH7 3 Positive input: ADCn_CH6 Negative input: ADCn_CH7
DIFF0 4 Differential 0 (Short between positive and negative inputs)
7:6 Reserved To ensure compatibility with future devices, always write bits to 0. More information in 2.1 Conven-
tions.
5:4 RES 0x0 RW Single Sample Resolution Select
Select single sample conversion resolution.
Value Mode Description
0 12BIT 12-bit resolution
1 8BIT 8-bit resolution
2 6BIT 6-bit resolution
3 OVS Oversampling enabled. Oversampling rate is set in OVSRSEL
3 Reserved To ensure compatibility with future devices, always write bits to 0. More information in 2.1 Conven-
tions.
2 ADJ 0 RW Single Sample Result Adjustment
Select single sample result adjustment.
Value Mode Description
0 RIGHT Results are right adjusted
1 LEFT Results are left adjusted
1 DIFF 0 RW Single Sample Differential Mode
Select single ended or differential input.
Value Description
0 Single ended input
1 Differential input
0 REP 0 RW Single Sample Repetitive Mode
Enable/disable repetitive single samples.
Value Description
0 Single conversion mode is deactivated after one conversion
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Bit Name Reset Access Description
1 Single conversion mode is converting continuously until SINGLESTOP
is written
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28.5.5 ADCn_SCANCTRL - Scan Control Register
Offset Bit Position
0x010
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
16
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
Reset
0x0
0
0x0
0x0
0x00
0x0
0
0
0
Access
RW
RW
RW
RW
RW
RW
RW
RW
RW
Name
PRSSEL
PRSEN
AT
REF
INPUTMASK
RES
ADJ
DIFF
REP
Bit Name Reset Access Description
31:28 PRSSEL 0x0 RW Scan Sequence PRS Trigger Select
Select PRS trigger for scan sequence.
Value Mode Description
0 PRSCH0 PRS ch 0 triggers scan sequence
1 PRSCH1 PRS ch 1 triggers scan sequence
2 PRSCH2 PRS ch 2 triggers scan sequence
3 PRSCH3 PRS ch 3 triggers scan sequence
4 PRSCH4 PRS ch 4 triggers scan sequence
5 PRSCH5 PRS ch 5 triggers scan sequence
6 PRSCH6 PRS ch 6 triggers scan sequence
7 PRSCH7 PRS ch 7 triggers scan sequence
8 PRSCH8 PRS ch 8 triggers scan sequence
9 PRSCH9 PRS ch 9 triggers scan sequence
10 PRSCH10 PRS ch 10 triggers scan sequence
11 PRSCH11 PRS ch 11 triggers scan sequence
27:25 Reserved To ensure compatibility with future devices, always write bits to 0. More information in 2.1 Conven-
tions.
24 PRSEN 0 RW Scan Sequence PRS Trigger Enable
Enabled/disable PRS trigger of scan sequence.
Value Description
0 Scan sequence is not triggered by PRS input
1 Scan sequence is triggered by PRS input selected by PRSSEL
23:20 AT 0x0 RW Scan Sample Acquisition Time
Select the acquisition time for scan samples.
Value Mode Description
0 1CYCLE 1 ADC_CLK cycle acquisition time for scan samples
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Bit Name Reset Access Description
1 2CYCLES 2 ADC_CLK cycles acquisition time for scan samples
2 4CYCLES 4 ADC_CLK cycles acquisition time for scan samples
3 8CYCLES 8 ADC_CLK cycles acquisition time for scan samples
4 16CYCLES 16 ADC_CLK cycles acquisition time for scan samples
5 32CYCLES 32 ADC_CLK cycles acquisition time for scan samples
6 64CYCLES 64 ADC_CLK cycles acquisition time for scan samples
7 128CYCLES 128 ADC_CLK cycles acquisition time for scan samples
8 256CYCLES 256 ADC_CLK cycles acquisition time for scan samples
19 Reserved To ensure compatibility with future devices, always write bits to 0. More information in 2.1 Conven-
tions.
18:16 REF 0x0 RW Scan Sequence Reference Selection
Select reference to ADC scan sequence.
Value Mode Description
0 1V25 Internal 1.25 V reference
1 2V5 Internal 2.5 V reference
2 VDD VDD
3 5VDIFF Internal differential 5 V reference
4 EXTSINGLE Single ended external reference from ADCn_CH6
5 2XEXTDIFF Differential external reference, 2x(ADCn_CH6 - ADCn_CH7)
6 2XVDD Unbuffered 2xVDD
15:8 INPUTMASK 0x00 RW Scan Sequence Input Mask
Set one or more bits in this mask to select which inputs are included the scan sequence in either single ended or differential
mode.
DIFF = 0
Mode Value Description
CH0 00000001 ADCn_CH0 included in mask
CH1 00000010 ADCn_CH1 included in mask
CH2 00000100 ADCn_CH2 included in mask
CH3 00001000 ADCn_CH3 included in mask
CH4 00010000 ADCn_CH4 included in mask
CH5 00100000 ADCn_CH5 included in mask
CH6 01000000 ADCn_CH6 included in mask
CH7 10000000 ADCn_CH7 included in mask
DIFF = 1
Mode Value Description
CH0CH1 00000001 (Positive input: ADCn_CH0 Negative input: ADCn_CH1) included in
mask
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Bit Name Reset Access Description
CH2CH3 00000010 (Positive input: ADCn_CH2 Negative input: ADCn_CH3) included in
mask
CH4CH5 00000100 (Positive input: ADCn_CH4 Negative input: ADCn_CH5) included in
mask
CH6CH7 00001000 (Positive input: ADCn_CH6 Negative input: ADCn_CH7) included in
mask
0001xxxx-1111xxxx Reserved
7:6 Reserved To ensure compatibility with future devices, always write bits to 0. More information in 2.1 Conven-
tions.
5:4 RES 0x0 RW Scan Sequence Resolution Select
Select scan sequence conversion resolution.
Value Mode Description
0 12BIT 12-bit resolution
1 8BIT 8-bit resolution
2 6BIT 6-bit resolution
3 OVS Oversampling enabled. Oversampling rate is set in OVSRSEL
3 Reserved To ensure compatibility with future devices, always write bits to 0. More information in 2.1 Conven-
tions.
2 ADJ 0 RW Scan Sequence Result Adjustment
Select scan sequence result adjustment.
Value Mode Description
0 RIGHT Results are right adjusted
1 LEFT Results are left adjusted
1 DIFF 0 RW Scan Sequence Differential Mode
Select single ended or differential input.
Value Description
0 Single ended input
1 Differential input
0 REP 0 RW Scan Sequence Repetitive Mode
Enable/disable repetitive scan sequence.
Value Description
0 Scan conversion mode is deactivated after one sequence
1 Scan conversion mode is converting continuously until SCANSTOP is
written
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28.5.6 ADCn_IEN - Interrupt Enable Register
Offset Bit Position
0x014
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
16
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
Reset
0
0
0
0
Access
RW
RW
RW
RW
Name
SCANOF
SINGLEOF
SCAN
SINGLE
Bit Name Reset Access Description
31:10 Reserved To ensure compatibility with future devices, always write bits to 0. More information in 2.1 Conven-
tions.
9 SCANOF 0 RW Scan Result Overflow Interrupt Enable
Enable/disable scan result overflow interrupt.
8 SINGLEOF 0 RW Single Result Overflow Interrupt Enable
Enable/disable single result overflow interrupt.
7:2 Reserved To ensure compatibility with future devices, always write bits to 0. More information in 2.1 Conven-
tions.
1 SCAN 0 RW Scan Conversion Complete Interrupt Enable
Enable/disable scan conversion complete interrupt.
0 SINGLE 0 RW Single Conversion Complete Interrupt Enable
Enable/disable single conversion complete interrupt.
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28.5.7 ADCn_IF - Interrupt Flag Register
Offset Bit Position
0x018
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
16
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
Reset
0
0
0
0
Access
R
R
R
R
Name
SCANOF
SINGLEOF
SCAN
SINGLE
Bit Name Reset Access Description
31:10 Reserved To ensure compatibility with future devices, always write bits to 0. More information in 2.1 Conven-
tions.
9 SCANOF 0 R Scan Result Overflow Interrupt Flag
Indicates scan result overflow when this bit is set.
8 SINGLEOF 0 R Single Result Overflow Interrupt Flag
Indicates single result overflow when this bit is set.
7:2 Reserved To ensure compatibility with future devices, always write bits to 0. More information in 2.1 Conven-
tions.
1 SCAN 0 R Scan Conversion Complete Interrupt Flag
Indicates scan conversion complete when this bit is set.
0 SINGLE 0 R Single Conversion Complete Interrupt Flag
Indicates single conversion complete when this bit is set.
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28.5.8 ADCn_IFS - Interrupt Flag Set Register
Offset Bit Position
0x01C
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
16
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
Reset
0
0
0
0
Access
W1
W1
W1
W1
Name
SCANOF
SINGLEOF
SCAN
SINGLE
Bit Name Reset Access Description
31:10 Reserved To ensure compatibility with future devices, always write bits to 0. More information in 2.1 Conven-
tions.
9 SCANOF 0 W1 Scan Result Overflow Interrupt Flag Set
Write to 1 to set scan result overflow interrupt flag
8 SINGLEOF 0 W1 Single Result Overflow Interrupt Flag Set
Write to 1 to set single result overflow interrupt flag.
7:2 Reserved To ensure compatibility with future devices, always write bits to 0. More information in 2.1 Conven-
tions.
1 SCAN 0 W1 Scan Conversion Complete Interrupt Flag Set
Write to 1 to set scan conversion complete interrupt flag.
0 SINGLE 0 W1 Single Conversion Complete Interrupt Flag Set
Write to 1 to set single conversion complete interrupt flag.
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28.5.9 ADCn_IFC - Interrupt Flag Clear Register
Offset Bit Position
0x020
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
16
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
Reset
0
0
0
0
Access
(R)W1
(R)W1
(R)W1
(R)W1
Name
SCANOF
SINGLEOF
SCAN
SINGLE
Bit Name Reset Access Description
31:10 Reserved To ensure compatibility with future devices, always write bits to 0. More information in 2.1 Conven-
tions.
9 SCANOF 0 (R)W1 Scan Result Overflow Interrupt Flag Clear
Write to 1 to clear scan result overflow interrupt flag.
8 SINGLEOF 0 (R)W1 Single Result Overflow Interrupt Flag Clear
Write to 1 to clear single result overflow interrupt flag.
7:2 Reserved To ensure compatibility with future devices, always write bits to 0. More information in 2.1 Conven-
tions.
1 SCAN 0 (R)W1 Scan Conversion Complete Interrupt Flag Clear
Write to 1 to clear scan conversion complete interrupt flag.
0 SINGLE 0 (R)W1 Single Conversion Complete Interrupt Flag Clear
Write to 1 to clear single conversion complete interrupt flag.
28.5.10 ADCn_SINGLEDATA - Single Conversion Result Data (Actionable Reads)
Offset Bit Position
0x024
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
16
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
Reset
0x00000000
Access
R
Name
DATA
Bit Name Reset Access Description
31:0 DATA 0x00000000 R Single Conversion Result Data
The register holds the results from the last single conversion. Reading this field clears the SINGLEDV bit in the
ADCn_STATUS register.
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28.5.11 ADCn_SCANDATA - Scan Conversion Result Data (Actionable Reads)
Offset Bit Position
0x028
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
16
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
Reset
0x00000000
Access
R
Name
DATA
Bit Name Reset Access Description
31:0 DATA 0x00000000 R Scan Conversion Result Data
The register holds the results from the last scan conversion. Reading this field clears the SCANDV bit in the ADCn_STA-
TUS register.
28.5.12 ADCn_SINGLEDATAP - Single Conversion Result Data Peek Register
Offset Bit Position
0x02C
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
16
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
Reset
0x00000000
Access
R
Name
DATAP
Bit Name Reset Access Description
31:0 DATAP 0x00000000 R Single Conversion Result Data Peek
The register holds the results from the last single conversion. Reading this field will not clear SINGLEDV in ADCn_STATUS
or SINGLE DMA request.
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28.5.13 ADCn_SCANDATAP - Scan Sequence Result Data Peek Register
Offset Bit Position
0x030
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
16
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
Reset
0x00000000
Access
R
Name
DATAP
Bit Name Reset Access Description
31:0 DATAP 0x00000000 R Scan Conversion Result Data Peek
The register holds the results from the last scan conversion. Reading this field will not clear SCANDV in ADCn_STATUS or
single DMA request.
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28.5.14 ADCn_CAL - Calibration Register
Offset Bit Position
0x034
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
16
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
Reset
0x3F
0x00
0x3F
0x00
Access
RW
RW
RW
RW
Name
SCANGAIN
SCANOFFSET
SINGLEGAIN
SINGLEOFFSET
Bit Name Reset Access Description
31 Reserved To ensure compatibility with future devices, always write bits to 0. More information in 2.1 Conven-
tions.
30:24 SCANGAIN 0x3F RW Scan Mode Gain Calibration Value
This register contains the gain calibration value used with scan conversions. This field is set to the production gain calibra-
tion value for the 1V25 internal reference during reset, hence the reset value might differ from device to device. The field is
unsigned. Higher values lead to higher ADC results.
23 Reserved To ensure compatibility with future devices, always write bits to 0. More information in 2.1 Conven-
tions.
22:16 SCANOFFSET 0x00 RW Scan Mode Offset Calibration Value
This register contains the offset calibration value used with scan conversions. This field is set to the production offset cali-
bration value for the 1V25 internal reference during reset, hence the reset value might differ from device to device. The field
is encoded as a signed 2's complement number. Higher values lead to lower ADC results.
15 Reserved To ensure compatibility with future devices, always write bits to 0. More information in 2.1 Conven-
tions.
14:8 SINGLEGAIN 0x3F RW Single Mode Gain Calibration Value
This register contains the gain calibration value used with single conversions. This field is set to the production gain calibra-
tion value for the 1V25 internal reference during reset, hence the reset value might differ from device to device. The field is
unsigned. Higher values lead to higher ADC results.
7 Reserved To ensure compatibility with future devices, always write bits to 0. More information in 2.1 Conven-
tions.
6:0 SINGLEOFFSET 0x00 RW Single Mode Offset Calibration Value
This register contains the offset calibration value used with single conversions. This field is set to the production offset cali-
bration value for the 1V25 internal reference during reset, hence the reset value might differ from device to device. The field
is encoded as a signed 2's complement number. Higher values lead to lower ADC results.
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28.5.15 ADCn_BIASPROG - Bias Programming Register
Offset Bit Position
0x03C
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
16
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
Reset
0x7
1
0x7
Access
RW
RW
RW
Name
COMPBIAS
HALFBIAS
BIASPROG
Bit Name Reset Access Description
31:12 Reserved To ensure compatibility with future devices, always write bits to 0. More information in 2.1 Conven-
tions.
11:8 COMPBIAS 0x7 RW Comparator Bias Value
These bits are used to adjust the bias current to the ADC Comparator.
7 Reserved To ensure compatibility with future devices, always write bits to 0. More information in 2.1 Conven-
tions.
6 HALFBIAS 1 RW Half Bias Current
Set this bit to halve the bias current.
5:4 Reserved To ensure compatibility with future devices, always write bits to 0. More information in 2.1 Conven-
tions.
3:0 BIASPROG 0x7 RW Bias Programming Value
These bits are used to adjust the bias current.
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29. DAC - Digital to Analog Converter
43210
DAC
...0100010...
...0101110...
Quick Facts
What?
The DAC is designed for low energy consumption,
but can also provide very good performance. It can
convert digital values to analog signals at up to 500
kilo samples/ second and with 12-bit accuracy.
Why?
The DAC is able to generate accurate analog sig-
nals using only a limited amount of energy.
How?
The DAC can generate high-resolution analog sig-
nals while the MCU is operating at low frequencies
and with low total power consumption. Using DMA
and a timer, the DAC can be used to generate wave-
forms without any CPU intervention.
29.1 Introduction
The Digital to Analog Converter (DAC) can convert a digital value to an analog output voltage. The DAC is fully differential rail-to-rail,
with 12-bit resolution. It has two single ended output buffers which can be combined into one differential output. The DAC may be used
for a number of different applications such as sensor interfaces or sound output.
29.2 Features
• 500 ksamples/s operation
• Two single ended output channels
• Can be combined into one differential output
• Integrated prescaler with division factor selectable between 1-128
• Selectable voltage reference
• Internal 2.5V
• Internal 1.25V
• VDD
• Conversion triggers
• Data write
• PRS input
• Automatic refresh timer
• Selection from 16-64 prescaled HFPERCLK cycles
• Individual refresh enable for each channel
• Interrupt generation on finished conversion
• Separate interrupt flag for each channel
• PRS output pulse on finished conversion
• Separate line for each channel
• DMA request on finished conversion
• Separate request for each channel
• Support for offset and gain calibration
• Output to ADC
• Sine generation mode
• Optional high strength line driver
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29.3 Functional Description
An overview of the DAC module is shown in the following figure.
DACn_OUT0
DACn_OUT1
Ch 1
VDD
1.25 V
2.5 V
CH0DATA
CH1DATA
ADC and ACMP
REFSEL
Ch 0
Figure 29.1. DAC Overview
29.3.1 Conversions
The DAC consists of two channels (Channel 0 and 1) with separate 12-bit data registers (DACn_CH0DATA and DACn_CH1DATA).
These can be used to produce two independent single ended outputs or the channel 0 register can be used to drive both outputs in
differential mode. The DAC supports three conversion modes, continuous, sample/hold, sample/off.
29.3.1.1 Continuous Mode
In continuous mode the DAC channels will drive their outputs continuously with the data in the DACn_CHxDATA registers. This mode
will maintain the output voltage and refresh is therefore not needed.
29.3.1.2 Sample/Hold Mode
In sample/hold mode, the DAC core converts data on a triggered conversion and then holds the output in a sample/hold element. When
not converting, the DAC core is turned off between samples, which reduces the power consumption. Because of output voltage drift the
sample/hold element will only hold the output for a certain period without a refresh conversion. The reader is referred to the electrical
characteristics for the details on the voltage drift. The sampling period in this mode is set to the length of one prescaled clock cycle.
29.3.1.3 Sample/Off Mode
In sample/off mode the DAC and the sample/hold element is turned completely off between samples, tri-stating the DAC output. This
requires the DAC output voltage to be held externally. The references are also turned off between samples, which means that a new
warm-up period is needed before each conversion. The sampling period in this mode is set to the length of one prescaled clock cycle.
29.3.1.4 Conversion Start
The DAC channel must be enabled before it can be used. When the channel is enabled, a conversion can be started by writing to the
DACn_CHxDATA register. These data registers are also mapped into a combined data register, DACn_COMBDATA, where the data
values for both channels can be written simultaneously. Writing to this register will start all enabled channels.
If the PRSEN bit in DACn_CHxCTRL is set, a DAC conversion on channel x will not be started by data write, but when a positive one
HFPERCLK cycle pulse is received on the PRS input selected by PRSSEL in DACn_CHxCTRL.
The CH0DV and CH1DV bits in DACn_STATUS indicate that the corresponding channel contains data that has not yet been converted.
When entering Energy Mode 4, both DAC channels must be stopped.
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29.3.1.5 Clock Prescaling
The DAC has an internal clock prescaler, which can divide the HFPERCLK by any factor between 1 and 128, by setting the PRESC bits
in DACnCTRL. The resulting DAC_CLK is used by the converter core and the frequency is given by the following equation:
fDAC_CLK =
fHFPERCLK
2PRESC
where fHFPERCLK is the HFPERCLK frequency. One conversion takes 2 DAC_CLK cycles and the DAC_CLK should not be set higher
than 1 MHz.
Normally the PRESCALER runs continuously when either of the channels are enabled. When running with a prescaler setting higher
than 0, there will be an unpredictable delay from the time the conversion was triggered to the time the actual conversion takes place.
This is because the conversions is controlled by the prescaled clock and the conversion can arrive at any time during a prescaled clock
(DAC_CLK) period. However, if the CH0PRESCRST bit in DACn_CTRL is set, the prescaler will be reset every time a conversion is
triggered on channel 0. This leads to a predictable latency between channel 0 trigger and conversion.
29.3.2 Reference Selection
Three internal voltage references are available and are selected by setting the REFSEL bits in DACn_CTRL:
• Internal 2.5V
• Internal 1.25V
• VDD
The reference selection can only be changed while both channels are disabled. The references for the DAC need to be enabled for
some time before they can be used. This is called the warm-up period, and starts when one of the channels is enabled. For a bandgap
reference, this period is 5 DAC_CLK cycles while the VDD reference needs 1 DAC_CLK cycle. The DAC will time this period automati-
cally (given that the prescaler is set correctly) and delay any conversion triggers received during the warm-up until the references have
stabilized.
29.3.3 Programming of Bias Current
The bias current of the bandgap reference and the DAC output buffer can be scaled by the BIASPROG and HALFBIAS bit fields of the
DACn_BIASPROG register as illustrated in the following figure.
BIASPROG
HALFBIAS
Reference
Current
Internal bandgap
reference
DAC output
buffer
Figure 29.2. DAC Bias Programming
The minimum value of the BIASPROG bit-field of the DACn_BIASPROG register (i.e. BIASPROG=0b0000) represents the minimum
bias current. Similarly BIASPROG=0b1111 represents the maximum bias current. The bias current defined by the BIASPROG setting
can be halved by setting the HALFBIAS bit of the DACn_BIASPROG register.
The bias current settings should only be changed while both DAC channels are disabled. The electrical characteristics given in the da-
tasheet require the bias configuration to be set to the default values, where no other bias values are given.
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29.3.4 Mode
The two DAC channels can act as two separate single ended channels or be combined into one differential channel. This is selected
through the DIFF bit in DACn_CTRL.
29.3.4.1 Single Ended Output
When operating in single ended mode, the channel 0 output is on DACn_OUT0 and the channel 1 output is on DACn_OUT1. The out-
put voltage can be calculated using the following equation.
VOUT =VDACn_OUTx -VSS =Vref ×CHxDATA
4095
where CHxDATA is a 12-bit unsigned integer.
29.3.4.2 Differential Output
When operating in differential mode, both DAC outputs are used as output for the bipolar voltage. The differential conversion uses
DACn_CH0DATA as source. The positive output is on DACn_OUT1 and the negative output is on DACn_OUT0. Since the output can
be negative, it is expected that the data is written in 2’s complement form with the MSB of the 12-bit value being the signed bit. The
output voltage can be calculated using the following equation:
VOUT =VDACn_OUT1 -VDACn_OUT0 =Vref ×CH0DATA
2047
where CH0DATA is a 12-bit signed integer. The common mode voltage is VDD/2.
29.3.5 Sine Generation Mode
The DAC contains an automatic sine-generation mode, which is enabled by setting the SINEMODE bit in DACn_CTRL. In this mode,
the DAC data is overridden with a conversion data taken from a sine lookup table. The sine signal is controlled by the PRS line selected
by CH0PRSSEL in DACn_CH0CTRL. When the PRS line is low, a voltage of Vref/2 will be produced. When the line is high, a sine
wave will be produced. Each period, starting at 0 degrees, is made up of 16 samples and the frequency is given by the following equa-
tion:
fsine =
fHFPERCLK
32 ×(PRESC + 1)
The SINE wave will be output on channel 0. If DIFF is set in DACn_CTRL, the sine wave will be output on both channels (if enabled),
but inverted (see the following figure). Note that when OUTENPRS in DACn_CTRL is set, the sine output will be reset to 0 degrees
when the PRS line selected by CH1PRSSEL is low.
CH1 PRS
DACn_OUT1
DACn_OUT0
Hi-Z
Hi-Z
CH0 PRS
Vref
0
Vref/2
Vref
0
Vref/2
Figure 29.3. DAC Sine Mode
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29.3.6 Interrupts and PRS Output
Both DAC channels have separate interrupt flags (in DACn_IF) indicating that a conversion has finished on the channel and that new
data can be written to the data registers. Setting one of these flags will result in a DAC interrupt if the corresponding interrupt enable bit
is set in DACn_IEN. All generated interrupts from the DAC will activate the same interrupt vector when enabled.
The DAC has two PRS outputs which will carry a one cycle (HFPERCLK) high pulse when the corresponding channel has finished a
conversion.
29.3.7 DMA Request
The DAC sends out a DMA request when a conversion on a channel is complete. This request is cleared when the corresponding chan-
nel’s data register is written.
29.3.8 Analog Output
Each DAC channel has its own output pin (DACn_OUT0 and DACn_OUT1) in addition to an internal loopback to the ADC and ACMP.
These outputs can be enabled and disabled individually in the EN field in DACn_CHxCTRL registers in combination with OUTPUTSEL
in DACn_CTRL. The DAC outputs can also be directed to the ADC and ACMP, which is also configurable in the OUTPUTSEL field in
DACn_CTRL.
The DAC outputs are tri-stated when the channels are not enabled. By setting the OUTENPRS bit in DACn_CTRL, the outputs are also
tri-stated when the PRS line selected by CH1PRSSEL in DACn_CH1CTRL is low. When the PRS signal is high, the outputs are ena-
bled as normal.
The DAC channels can also drive an alternative output network, which is described in the Opamp chapter in 30.3.1.2 Output Configura-
tion. To enable this network, OUTMODE must be configured to ADC in DACn_CTRL. The actual output network can be configred by
configuring DACn_OPAxMUX registers.
29.3.9 Calibration
The DAC contains a calibration register, DACn_CAL, where calibration values for both offset and gain correction can be written. Offset
calibration is done separately for each channel through the CHxOFFSET bit-fields. Gain is calibrated in one common register field,
GAIN. The gain calibration is linked to the reference and when the reference is changed, the gain must be re-calibrated. Gain and offset
for the 1V25, 2V5 and VDD references are calibrated during production and the calibration values for these can be found in the Device
Information page. During reset, the gain and offset calibration registers are loaded with the production calibration values for the 1V25
reference.
29.3.10 Opamps
The DAC includes a set of three highly configurable opamps that can be accessed in the DAC module. Two of the opamps are located
in the DAC, while the third opamp is a standalone opamp. For detailed description see the OPAMP chapter. The register description
can be found in Register Description section of this chapter.
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29.4 Register Map
The offset register address is relative to the registers base address.
Offset Name Type Description
0x000 DACn_CTRL RW Control Register
0x004 DACn_STATUS RStatus Register
0x008 DACn_CH0CTRL RW Channel 0 Control Register
0x00C DACn_CH1CTRL RW Channel 1 Control Register
0x010 DACn_IEN RW Interrupt Enable Register
0x014 DACn_IF RInterrupt Flag Register
0x018 DACn_IFS W1 Interrupt Flag Set Register
0x01C DACn_IFC (R)W1 Interrupt Flag Clear Register
0x020 DACn_CH0DATA RW Channel 0 Data Register
0x024 DACn_CH1DATA RW Channel 1 Data Register
0x028 DACn_COMBDATA WCombined Data Register
0x02C DACn_CAL RW Calibration Register
0x030 DACn_BIASPROG RW Bias Programming Register
0x054 DACn_OPACTRL RW Operational Amplifier Control Register
0x058 DACn_OPAOFFSET RW Operational Amplifier Offset Register
0x05C DACn_OPA0MUX RW Operational Amplifier Mux Configuration Register
0x060 DACn_OPA1MUX RW Operational Amplifier Mux Configuration Register
0x064 DACn_OPA2MUX RW Operational Amplifier Mux Configuration Register
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29.5 Register Description
29.5.1 DACn_CTRL - Control Register
Offset Bit Position
0x000
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
16
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
Reset
0x0
0x0
0x0
0
0
0x1
0x0
0
0
Access
RW
RW
RW
RW
RW
RW
RW
RW
RW
Name
REFRSEL
PRESC
REFSEL
CH0PRESCRST
OUTENPRS
OUTMODE
CONVMODE
SINEMODE
DIFF
Bit Name Reset Access Description
31:22 Reserved To ensure compatibility with future devices, always write bits to 0. More information in 2.1 Conven-
tions.
21:20 REFRSEL 0x0 RW Refresh Interval Select
Select refresh counter timeout value. A channel x will be refreshed with the interval set in this register if the REFREN bit in
DACn_CHxCTRL is set.
Value Mode Description
0 8CYCLES All channels with enabled refresh are refreshed every 8 prescaled cy-
cles
1 16CYCLES All channels with enabled refresh are refreshed every 16 prescaled cy-
cles
2 32CYCLES All channels with enabled refresh are refreshed every 32 prescaled cy-
cles
3 64CYCLES All channels with enabled refresh are refreshed every 64 prescaled cy-
cles
19 Reserved To ensure compatibility with future devices, always write bits to 0. More information in 2.1 Conven-
tions.
18:16 PRESC 0x0 RW Prescaler Setting
Select clock division factor.
Value Description
PRESC Clock division factor of
2^PRESC.
15:10 Reserved To ensure compatibility with future devices, always write bits to 0. More information in 2.1 Conven-
tions.
9:8 REFSEL 0x0 RW Reference Selection
Select reference.
Value Mode Description
0 1V25 Internal 1.25 V bandgap reference
1 2V5 Internal 2.5 V bandgap reference
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Bit Name Reset Access Description
2 VDD VDD reference
7 CH0PRESCRST 0 RW Channel 0 Start Reset Prescaler
Select if prescaler is reset on channel 0 start.
Value Description
0 Prescaler not reset on channel 0 start
1 Prescaler reset on channel 0 start
6 OUTENPRS 0 RW PRS Controlled Output Enable
Enable PRS Control of DAC output enable.
Value Description
0 DAC output enable always on
1 DAC output enable controlled by PRS signal selected for CH1.
5:4 OUTMODE 0x1 RW Output Mode
Select output mode.
Value Mode Description
0 DISABLE DAC output to pin and ADC disabled
1 PIN DAC output to pin enabled. DAC output to ADC and ACMP disabled
2 ADC DAC output to pin disabled. DAC output to ADC and ACMP enabled
3 PINADC DAC output to pin, ADC, and ACMP enabled
3:2 CONVMODE 0x0 RW Conversion Mode
Configure conversion mode.
Value Mode Description
0 CONTINUOUS DAC is set in continuous mode
1 SAMPLEHOLD DAC is set in sample/hold mode
2 SAMPLEOFF DAC is set in sample/shut off mode
1 SINEMODE 0 RW Sine Mode
Enable/disable sine mode.
Value Description
0 Sine mode disabled. Sine reset to 0 degrees
1 Sine mode enabled
0 DIFF 0 RW Differential Mode
Select single ended or differential mode.
Value Description
0 Single ended output
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Bit Name Reset Access Description
1 Differential output
29.5.2 DACn_STATUS - Status Register
Offset Bit Position
0x004
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
16
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
Reset
0
0
Access
R
R
Name
CH1DV
CH0DV
Bit Name Reset Access Description
31:2 Reserved To ensure compatibility with future devices, always write bits to 0. More information in 2.1 Conven-
tions.
1 CH1DV 0 R Channel 1 Data Valid
This bit is set high when CH1DATA is written and is set low when CH1DATA is used in conversion.
0 CH0DV 0 R Channel 0 Data Valid
This bit is set high when CH0DATA is written and is set low when CH0DATA is used in conversion.
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29.5.3 DACn_CH0CTRL - Channel 0 Control Register
Offset Bit Position
0x008
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
16
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
Reset
0x0
0
0
0
Access
RW
RW
RW
RW
Name
PRSSEL
PRSEN
REFREN
EN
Bit Name Reset Access Description
31:8 Reserved To ensure compatibility with future devices, always write bits to 0. More information in 2.1 Conven-
tions.
7:4 PRSSEL 0x0 RW Channel 0 PRS Trigger Select
Select Channel 0 PRS input channel.
Value Mode Description
0 PRSCH0 PRS ch 0 triggers channel 0 conversion.
1 PRSCH1 PRS ch 1 triggers channel 0 conversion.
2 PRSCH2 PRS ch 2 triggers channel 0 conversion.
3 PRSCH3 PRS ch 3 triggers channel 0 conversion.
4 PRSCH4 PRS ch 4 triggers channel 0 conversion.
5 PRSCH5 PRS ch 5 triggers channel 0 conversion.
6 PRSCH6 PRS ch 6 triggers channel 0 conversion.
7 PRSCH7 PRS ch 7 triggers channel 0 conversion.
8 PRSCH8 PRS ch 8 triggers channel 0 conversion.
9 PRSCH9 PRS ch 9 triggers channel 0 conversion.
10 PRSCH10 PRS ch 10 triggers channel 0 conversion.
11 PRSCH11 PRS ch 11 triggers channel 0 conversion.
3 Reserved To ensure compatibility with future devices, always write bits to 0. More information in 2.1 Conven-
tions.
2 PRSEN 0 RW Channel 0 PRS Trigger Enable
Select Channel 0 conversion trigger.
Value Description
0 Channel 0 is triggered by CH0DATA or COMBDATA write
1 Channel 0 is triggered by PRS input
1 REFREN 0 RW Channel 0 Automatic Refresh Enable
Set to enable automatic refresh of channel 0. Refresh period is set by REFRSEL in DACn_CTRL.
Value Description
0 Channel 0 is not refreshed automatically
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Bit Name Reset Access Description
1 Channel 0 is refreshed automatically
0 EN 0 RW Channel 0 Enable
Enable/disable channel 0.
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29.5.4 DACn_CH1CTRL - Channel 1 Control Register
Offset Bit Position
0x00C
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
16
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
Reset
0x0
0
0
0
Access
RW
RW
RW
RW
Name
PRSSEL
PRSEN
REFREN
EN
Bit Name Reset Access Description
31:8 Reserved To ensure compatibility with future devices, always write bits to 0. More information in 2.1 Conven-
tions.
7:4 PRSSEL 0x0 RW Channel 1 PRS Trigger Select
Select Channel 1 PRS input channel.
Value Mode Description
0 PRSCH0 PRS ch 0 triggers channel 1 conversion.
1 PRSCH1 PRS ch 1 triggers channel 1 conversion.
2 PRSCH2 PRS ch 2 triggers channel 1 conversion.
3 PRSCH3 PRS ch 3 triggers channel 1 conversion.
4 PRSCH4 PRS ch 4 triggers channel 1 conversion.
5 PRSCH5 PRS ch 5 triggers channel 1 conversion.
6 PRSCH6 PRS ch 6 triggers channel 1 conversion.
7 PRSCH7 PRS ch 7 triggers channel 1 conversion.
8 PRSCH8 PRS ch 8 triggers channel 1 conversion.
9 PRSCH9 PRS ch 9 triggers channel 1 conversion.
10 PRSCH10 PRS ch 10 triggers channel 1 conversion.
11 PRSCH11 PRS ch 11 triggers channel 1 conversion.
3 Reserved To ensure compatibility with future devices, always write bits to 0. More information in 2.1 Conven-
tions.
2 PRSEN 0 RW Channel 1 PRS Trigger Enable
Select Channel 1 conversion trigger.
Value Description
0 Channel 1 is triggered by CH1DATA or COMBDATA write
1 Channel 1 is triggered by PRS input
1 REFREN 0 RW Channel 1 Automatic Refresh Enable
Set to enable automatic refresh of channel 1. Refresh period is set by REFRSEL in DACn_CTRL.
Value Description
0 Channel 1 is not refreshed automatically
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Bit Name Reset Access Description
1 Channel 1 is refreshed automatically
0 EN 0 RW Channel 1 Enable
Enable/disable channel 1.
29.5.5 DACn_IEN - Interrupt Enable Register
Offset Bit Position
0x010
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
16
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
Reset
0
0
0
0
Access
RW
RW
RW
RW
Name
CH1UF
CH0UF
CH1
CH0
Bit Name Reset Access Description
31:6 Reserved To ensure compatibility with future devices, always write bits to 0. More information in 2.1 Conven-
tions.
5 CH1UF 0 RW Channel 1 Conversion Data Underflow Interrupt Enable
Enable/disable channel 1 data underflow interrupt.
4 CH0UF 0 RW Channel 0 Conversion Data Underflow Interrupt Enable
Enable/disable channel 0 data underflow interrupt.
3:2 Reserved To ensure compatibility with future devices, always write bits to 0. More information in 2.1 Conven-
tions.
1 CH1 0 RW Channel 1 Conversion Complete Interrupt Enable
Enable/disable channel 1 conversion complete interrupt.
0 CH0 0 RW Channel 0 Conversion Complete Interrupt Enable
Enable/disable channel 0 conversion complete interrupt.
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29.5.6 DACn_IF - Interrupt Flag Register
Offset Bit Position
0x014
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
16
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
Reset
0
0
0
0
Access
R
R
R
R
Name
CH1UF
CH0UF
CH1
CH0
Bit Name Reset Access Description
31:6 Reserved To ensure compatibility with future devices, always write bits to 0. More information in 2.1 Conven-
tions.
5 CH1UF 0 R Channel 1 Data Underflow Interrupt Flag
Indicates channel 1 data underflow.
4 CH0UF 0 R Channel 0 Data Underflow Interrupt Flag
Indicates channel 0 data underflow.
3:2 Reserved To ensure compatibility with future devices, always write bits to 0. More information in 2.1 Conven-
tions.
1 CH1 0 R Channel 1 Conversion Complete Interrupt Flag
Indicates channel 1 conversion complete and that new data can be written to the data register.
0 CH0 0 R Channel 0 Conversion Complete Interrupt Flag
Indicates channel 0 conversion complete and that new data can be written to the data register.
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29.5.7 DACn_IFS - Interrupt Flag Set Register
Offset Bit Position
0x018
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
16
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
Reset
0
0
0
0
Access
W1
W1
W1
W1
Name
CH1UF
CH0UF
CH1
CH0
Bit Name Reset Access Description
31:6 Reserved To ensure compatibility with future devices, always write bits to 0. More information in 2.1 Conven-
tions.
5 CH1UF 0 W1 Channel 1 Data Underflow Interrupt Flag Set
Write to 1 to set channel 1 Data Underflow interrupt flag.
4 CH0UF 0 W1 Channel 0 Data Underflow Interrupt Flag Set
Write to 1 to set channel 0 Data Underflow interrupt flag.
3:2 Reserved To ensure compatibility with future devices, always write bits to 0. More information in 2.1 Conven-
tions.
1 CH1 0 W1 Channel 1 Conversion Complete Interrupt Flag Set
Write to 1 to set channel 1 conversion complete interrupt flag.
0 CH0 0 W1 Channel 0 Conversion Complete Interrupt Flag Set
Write to 1 to set channel 0 conversion complete interrupt flag.
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29.5.8 DACn_IFC - Interrupt Flag Clear Register
Offset Bit Position
0x01C
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
16
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
Reset
0
0
0
0
Access
(R)W1
(R)W1
(R)W1
(R)W1
Name
CH1UF
CH0UF
CH1
CH0
Bit Name Reset Access Description
31:6 Reserved To ensure compatibility with future devices, always write bits to 0. More information in 2.1 Conven-
tions.
5 CH1UF 0 (R)W1 Channel 1 Data Underflow Interrupt Flag Clear
Write to 1 to clear channel 1 data underflow interrupt flag.
4 CH0UF 0 (R)W1 Channel 0 Data Underflow Interrupt Flag Clear
Write to 1 to clear channel 0 data underflow interrupt flag.
3:2 Reserved To ensure compatibility with future devices, always write bits to 0. More information in 2.1 Conven-
tions.
1 CH1 0 (R)W1 Channel 1 Conversion Complete Interrupt Flag Clear
Write to 1 to clear channel 1 conversion complete interrupt flag.
0 CH0 0 (R)W1 Channel 0 Conversion Complete Interrupt Flag Clear
Write to 1 to clear channel 0 conversion complete interrupt flag.
29.5.9 DACn_CH0DATA - Channel 0 Data Register
Offset Bit Position
0x020
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
16
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
Reset
0x000
Access
RW
Name
DATA
Bit Name Reset Access Description
31:12 Reserved To ensure compatibility with future devices, always write bits to 0. More information in 2.1 Conven-
tions.
11:0 DATA 0x000 RW Channel 0 Data
This register contains the value which will be converted by channel 0.
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29.5.10 DACn_CH1DATA - Channel 1 Data Register
Offset Bit Position
0x024
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
16
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
Reset
0x000
Access
RW
Name
DATA
Bit Name Reset Access Description
31:12 Reserved To ensure compatibility with future devices, always write bits to 0. More information in 2.1 Conven-
tions.
11:0 DATA 0x000 RW Channel 1 Data
This register contains the value which will be converted by channel 1.
29.5.11 DACn_COMBDATA - Combined Data Register
Offset Bit Position
0x028
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
16
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
Reset
0x000
0x000
Access
W
W
Name
CH1DATA
CH0DATA
Bit Name Reset Access Description
31:28 Reserved To ensure compatibility with future devices, always write bits to 0. More information in 2.1 Conven-
tions.
27:16 CH1DATA 0x000 W Channel 1 Data
Data written to this register will be written to DATA in DACn_CH1DATA.
15:12 Reserved To ensure compatibility with future devices, always write bits to 0. More information in 2.1 Conven-
tions.
11:0 CH0DATA 0x000 W Channel 0 Data
Data written to this register will be written to DATA in DACn_CH0DATA.
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29.5.12 DACn_CAL - Calibration Register
Offset Bit Position
0x02C
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
16
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
Reset
0x40
0x00
0x00
Access
RW
RW
RW
Name
GAIN
CH1OFFSET
CH0OFFSET
Bit Name Reset Access Description
31:23 Reserved To ensure compatibility with future devices, always write bits to 0. More information in 2.1 Conven-
tions.
22:16 GAIN 0x40 RW Gain Calibration Value
This register contains the gain calibration value. This field is set to the production gain calibration value for the 1V25 inter-
nal reference during reset, hence the reset value might differ from device to device. The field is unsigned. Higher values
lead to lower DAC results.
15:14 Reserved To ensure compatibility with future devices, always write bits to 0. More information in 2.1 Conven-
tions.
13:8 CH1OFFSET 0x00 RW Channel 1 Offset Calibration Value
This register contains the offset calibration value used with channel 1 conversions. This field is set to the production chan-
nel 1 offset calibration value for the 1V25 internal reference during reset, hence the reset value might differ from device to
device. The field is sign-magnitude encoded. Higher values lead to lower DAC results.
7:6 Reserved To ensure compatibility with future devices, always write bits to 0. More information in 2.1 Conven-
tions.
5:0 CH0OFFSET 0x00 RW Channel 0 Offset Calibration Value
This register contains the offset calibration value used with channel 0 conversions. This field is set to the production chan-
nel 0 offset calibration value for the 1V25 internal reference during reset, hence the reset value might differ from device to
device. The field is sign-magnitude encoded. Higher values lead to lower DAC results.
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29.5.13 DACn_BIASPROG - Bias Programming Register
Offset Bit Position
0x030
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
16
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
Reset
1
0x7
1
0x7
Access
RW
RW
RW
RW
Name
OPA2HALFBIAS
OPA2BIASPROG
HALFBIAS
BIASPROG
Bit Name Reset Access Description
31:15 Reserved To ensure compatibility with future devices, always write bits to 0. More information in 2.1 Conven-
tions.
14 OPA2HALFBIAS 1 RW Half Bias Current
Set this bit to halve the bias current.
13:12 Reserved To ensure compatibility with future devices, always write bits to 0. More information in 2.1 Conven-
tions.
11:8 OPA2BIASPROG 0x7 RW Bias Programming Value for OPA2
These bits control the bias current level.
7 Reserved To ensure compatibility with future devices, always write bits to 0. More information in 2.1 Conven-
tions.
6 HALFBIAS 1 RW Half Bias Current
Set this bit to halve the bias current.
5:4 Reserved To ensure compatibility with future devices, always write bits to 0. More information in 2.1 Conven-
tions.
3:0 BIASPROG 0x7 RW Bias Programming Value
These bits control the bias current level.
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29.5.14 DACn_OPACTRL - Operational Amplifier Control Register
Offset Bit Position
0x054
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
16
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
Reset
0
0
0
0x0
0x0
0x0
0
0
0
0
0
0
Access
RW
RW
RW
RW
RW
RW
RW
RW
RW
RW
RW
RW
Name
OPA2SHORT
OPA1SHORT
OPA0SHORT
OPA2LPFDIS
OPA1LPFDIS
OPA0LPFDIS
OPA2HCMDIS
OPA1HCMDIS
OPA0HCMDIS
OPA2EN
OPA1EN
OPA0EN
Bit Name Reset Access Description
31:25 Reserved To ensure compatibility with future devices, always write bits to 0. More information in 2.1 Conven-
tions.
24 OPA2SHORT 0 RW Short the non-inverting and inverting input.
Set to short the non-inverting and inverting input.
23 OPA1SHORT 0 RW Short the non-inverting and inverting input.
Set to short the non-inverting and inverting input.
22 OPA0SHORT 0 RW Short the non-inverting and inverting input.
Set to short the non-inverting and inverting input.
21:18 Reserved To ensure compatibility with future devices, always write bits to 0. More information in 2.1 Conven-
tions.
17:16 OPA2LPFDIS 0x0 RW Disables Low Pass Filter.
Disables the low pass filter between pad and the positive and negative input mux.
LPF DISABLE VALUE Description
PLPFDIS x1 Disables the low pass filter between positive pad and positive input.
NLPFDIS 1x Disables the low pass filter between negative pad and negative input.
15:14 OPA1LPFDIS 0x0 RW Disables Low Pass Filter.
Disables the low pass filter between pad and the positive and negative input mux.
LPF DISABLE VALUE Description
PLPFDIS x1 Disables the low pass filter between positive pad and positive input.
NLPFDIS 1x Disables the low pass filter between negative pad and negative input.
13:12 OPA0LPFDIS 0x0 RW Disables Low Pass Filter.
Disables the low pass filter between pad and the positive and negative input mux.
LPF DISABLE VALUE Description
PLPFDIS x1 Disables the low pass filter between positive pad and positive input.
NLPFDIS 1x Disables the low pass filter between negative pad and negative input.
11:9 Reserved To ensure compatibility with future devices, always write bits to 0. More information in 2.1 Conven-
tions.
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Bit Name Reset Access Description
8 OPA2HCMDIS 0 RW High Common Mode Disable.
Set to disable high common mode. Disables rail-to-rail on input, while output still remains rail-to-rail. The input voltage to
the opamp while HCM is disabled is restricted between VSS and VDD-1.2V.
7 OPA1HCMDIS 0 RW High Common Mode Disable.
Set to disable high common mode. Disables rail-to-rail on input, while output still remains rail-to-rail. The input voltage to
the opamp while HCM is disabled is restricted between VSS and VDD-1.2V.
6 OPA0HCMDIS 0 RW High Common Mode Disable.
Set to disable high common mode. Disables rail-to-rail on input, while output still remains rail-to-rail. The input voltage to
the opamp while HCM is disabled is restricted between VSS and VDD-1.2V.
5:3 Reserved To ensure compatibility with future devices, always write bits to 0. More information in 2.1 Conven-
tions.
2 OPA2EN 0 RW OPA2 Enable
Set to enable OPA2, clear to disable.
1 OPA1EN 0 RW OPA1 Enable
Set to enable OPA1, clear to disable. CH1EN in DAC_CH1CTRL must also be set.
0 OPA0EN 0 RW OPA0 Enable
Set to enable OPA0, clear to disable. CH0EN in DAC_CH0CTRL must also be set.
29.5.15 DACn_OPAOFFSET - Operational Amplifier Offset Register
Offset Bit Position
0x058
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
16
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
Reset
0x20
Access
RW
Name
OPA2OFFSET
Bit Name Reset Access Description
31:6 Reserved To ensure compatibility with future devices, always write bits to 0. More information in 2.1 Conven-
tions.
5:0 OPA2OFFSET 0x20 RW OPA2 Offset Configuration Value
This register contains the offset calibration value for OPA2. This field is set to the production OPA2 offset calibration value,
hence the reset value might differ from device to device. The field is sign-magnitude encoded. Higher values lead to lower
OPA results. The resolution of the LSB is 1.6mV/LSB
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29.5.16 DACn_OPA0MUX - Operational Amplifier Mux Configuration Register
Offset Bit Position
0x05C
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
16
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
Reset
0x0
0
0x1
0x00
0
0
0x0
0x0
0x0
Access
RW
RW
RW
RW
RW
RW
RW
RW
RW
Name
RESSEL
NEXTOUT
OUTMODE
OUTPEN
NPEN
PPEN
RESINMUX
NEGSEL
POSSEL
Bit Name Reset Access Description
31 Reserved To ensure compatibility with future devices, always write bits to 0. More information in 2.1 Conven-
tions.
30:28 RESSEL 0x0 RW OPA0 Resistor Ladder Select
Configures the resistor ladder tap for OPA0.
Value Mode Resistor Value
0 RES0 R2 = 1/3 x R1
1 RES1 R2 = R1
2 RES2 R2 = 1 2/3 x R1
3 RES3 R2 = 2 x R1
4 RES4 R2 = 3 x R1
5 RES5 R2 = 4 1/3 x R1
6 RES6 R2 = 7 x R1
7 RES7 R2 = 15 x R1
27 Reserved To ensure compatibility with future devices, always write bits to 0. More information in 2.1 Conven-
tions.
26 NEXTOUT 0 RW OPA0 Next Enable
Makes output of OPA0 available to OPA1.
25:24 Reserved To ensure compatibility with future devices, always write bits to 0. More information in 2.1 Conven-
tions.
23:22 OUTMODE 0x1 RW Output Select
Select output channel.
Value Mode Description
0 DISABLE OPA0 output is disabled
1 MAIN Main OPA0 output to pin enabled
2 ALT OPA0 alternative output enabled.
3 ALL Main OPA0 output drives both main and alternative outputs.
21:19 Reserved To ensure compatibility with future devices, always write bits to 0. More information in 2.1 Conven-
tions.
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Bit Name Reset Access Description
18:14 OUTPEN 0x00 RW OPA0 Output Enable Value
Set to enable output, clear to disable output
OUT ENABLE VALUE Description
OUT0 xxxx1 Alternate Output 0
OUT1 xxx1x Alternate Output 1
OUT2 xx1xx Alternate Output 2
OUT3 x1xxx Alternate Output 3
OUT4 1xxxx Alternate Output 4
13 NPEN 0 RW OPA0 Negative Pad Input Enable
Connects pad to the negative input mux
12 PPEN 0 RW OPA0 Positive Pad Input Enable
Connects pad to the positive input mux
11 Reserved To ensure compatibility with future devices, always write bits to 0. More information in 2.1 Conven-
tions.
10:8 RESINMUX 0x0 RW OPA0 Resistor Ladder Input Mux
These bits selects the source for the input mux to the resistor ladder
Value Mode Description
0 DISABLE Set for Unity Gain
1 OPA0INP Set for OPA0 input
2 NEGPAD NEG pad connected
3 POSPAD POS pad connected
4 VSS VSS connected
7:6 Reserved To ensure compatibility with future devices, always write bits to 0. More information in 2.1 Conven-
tions.
5:4 NEGSEL 0x0 RW OPA0 inverting Input Mux
These bits selects the source for the inverting input on OPA0
Value Mode Description
0 DISABLE Input disabled
1 UG Unity Gain feedback path
2 OPATAP OPA0 Resistor ladder as input
3 NEGPAD Input from NEG PAD
3 Reserved To ensure compatibility with future devices, always write bits to 0. More information in 2.1 Conven-
tions.
2:0 POSSEL 0x0 RW OPA0 non-inverting Input Mux
These bits selects the source for the non-inverting input on OPA0
Value Mode Description
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Bit Name Reset Access Description
0 DISABLE Input disabled
1 DAC DAC as input
2 POSPAD POS PAD as input
3 OPA0INP OPA0 as input
4 OPATAP OPA0 Resistor ladder as input
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29.5.17 DACn_OPA1MUX - Operational Amplifier Mux Configuration Register
Offset Bit Position
0x060
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
16
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
Reset
0x0
0
0x0
0x00
0
0
0x0
0x0
0x0
Access
RW
RW
RW
RW
RW
RW
RW
RW
RW
Name
RESSEL
NEXTOUT
OUTMODE
OUTPEN
NPEN
PPEN
RESINMUX
NEGSEL
POSSEL
Bit Name Reset Access Description
31 Reserved To ensure compatibility with future devices, always write bits to 0. More information in 2.1 Conven-
tions.
30:28 RESSEL 0x0 RW OPA1 Resistor Ladder Select
Configures the resistor ladder tap for OPA1.
Value Mode Resistor Value
0 RES0 R2 = 1/3 x R1
1 RES1 R2 = R1
2 RES2 R2 = 1 2/3 x R1
3 RES3 R2 = 2 x R1
4 RES4 R2 = 3 x R1
5 RES5 R2 = 4 1/3 x R1
6 RES6 R2 = 7 x R1
7 RES7 R2 = 15 x R1
27 Reserved To ensure compatibility with future devices, always write bits to 0. More information in 2.1 Conven-
tions.
26 NEXTOUT 0 RW OPA1 Next Enable
Makes output of OPA1 available to OPA2.
25:24 Reserved To ensure compatibility with future devices, always write bits to 0. More information in 2.1 Conven-
tions.
23:22 OUTMODE 0x0 RW Output Select
Select output channel.
Value Mode Description
0 DISABLE OPA0 output is disabled
1 MAIN Main OPA1 output to pin enabled
2 ALT OPA1 alternative output enabled.
3 ALL Main OPA1 output drives both main and alternative outputs.
21:19 Reserved To ensure compatibility with future devices, always write bits to 0. More information in 2.1 Conven-
tions.
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Bit Name Reset Access Description
18:14 OUTPEN 0x00 RW OPA1 Output Enable Value
Set to enable output, clear to disable output
OUT ENABLE VALUE Description
OUT0 xxxx1 Alternate Output 0
OUT1 xxx1x Alternate Output 1
OUT2 xx1xx Alternate Output 2
OUT3 x1xxx Alternate Output 3
OUT4 1xxxx Alternate Output 4
13 NPEN 0 RW OPA1 Negative Pad Input Enable
Connects pad to the negative input mux
12 PPEN 0 RW OPA1 Positive Pad Input Enable
Connects pad to the positive input mux
11 Reserved To ensure compatibility with future devices, always write bits to 0. More information in 2.1 Conven-
tions.
10:8 RESINMUX 0x0 RW OPA1 Resistor Ladder Input Mux
These bits selects the source for the input mux to the resistor ladder
Value Mode Description
0 DISABLE Set for Unity Gain
1 OPA0INP Set for OPA0 input
2 NEGPAD NEG PAD connected
3 POSPAD POS PAD connected
4 VSS VSS connected
7:6 Reserved To ensure compatibility with future devices, always write bits to 0. More information in 2.1 Conven-
tions.
5:4 NEGSEL 0x0 RW OPA1 inverting Input Mux
These bits selects the source for the inverting input on OPA1
Value Mode Description
0 DISABLE Input disabled
1 UG Unity Gain feedback path
2 OPATAP OPA1 Resistor ladder as input
3 NEGPAD Input from NEG PAD
3 Reserved To ensure compatibility with future devices, always write bits to 0. More information in 2.1 Conven-
tions.
2:0 POSSEL 0x0 RW OPA1 non-inverting Input Mux
These bits selects the source for the non-inverting input on OPA1
Value Mode Description
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Bit Name Reset Access Description
0 DISABLE Input disabled
1 DAC DAC as input
2 POSPAD POS PAD as input
3 OPA0INP OPA0 as input
4 OPATAP OPA 1 Resistor ladder as input
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29.5.18 DACn_OPA2MUX - Operational Amplifier Mux Configuration Register
Offset Bit Position
0x064
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
16
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
Reset
0x0
0
0
0x0
0
0
0x0
0x0
0x0
Access
RW
RW
RW
RW
RW
RW
RW
RW
RW
Name
RESSEL
NEXTOUT
OUTMODE
OUTPEN
NPEN
PPEN
RESINMUX
NEGSEL
POSSEL
Bit Name Reset Access Description
31 Reserved To ensure compatibility with future devices, always write bits to 0. More information in 2.1 Conven-
tions.
30:28 RESSEL 0x0 RW OPA2 Resistor Ladder Select
Configures the resistor ladder tap for OPA2.
Value Mode Resistor Value
0 RES0 R2 = 1/3 x R1
1 RES1 R2 = R1
2 RES2 R2 = 1 2/3 x R1
3 RES3 R2 = 2 x R1
4 RES4 R2 = 3 x R1
5 RES5 R2 = 4 1/3 x R1
6 RES6 R2 = 7 x R1
7 RES7 R2 = 15 x R1
27 Reserved To ensure compatibility with future devices, always write bits to 0. More information in 2.1 Conven-
tions.
26 NEXTOUT 0 RW OPA2 Next Enable
OPA2 does not have an next output.
25:23 Reserved To ensure compatibility with future devices, always write bits to 0. More information in 2.1 Conven-
tions.
22 OUTMODE 0 RW Output Select
Enables OPA2 main output.
21:16 Reserved To ensure compatibility with future devices, always write bits to 0. More information in 2.1 Conven-
tions.
15:14 OUTPEN 0x0 RW OPA2 Output Location
Select location for main output
Value Mode Description
1 OUT0 Main Output 0
2 OUT1 Main Output 1
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Bit Name Reset Access Description
13 NPEN 0 RW OPA2 Negative Pad Input Enable
Connects pad to the negative input mux
12 PPEN 0 RW OPA2 Positive Pad Input Enable
Connects pad to the positive input mux
11 Reserved To ensure compatibility with future devices, always write bits to 0. More information in 2.1 Conven-
tions.
10:8 RESINMUX 0x0 RW OPA2 Resistor Ladder Input Mux
These bits selects the source for the input mux to the resistor ladder
Value Mode Description
0 DISABLE Set for Unity Gain
1 OPA1INP Set for OPA1 input
2 NEGPAD NEG PAD connected
3 POSPAD POS PAD connected
4 VSS VSS connected
7:6 Reserved To ensure compatibility with future devices, always write bits to 0. More information in 2.1 Conven-
tions.
5:4 NEGSEL 0x0 RW OPA2 inverting Input Mux
These bits selects the source for the inverting input on OPA2
Value Mode Description
0 DISABLE Input disabled
1 UG Unity Gain feedback path
2 OPATAP OPA2 Resistor ladder as input
3 NEGPAD Input from NEG PAD
3 Reserved To ensure compatibility with future devices, always write bits to 0. More information in 2.1 Conven-
tions.
2:0 POSSEL 0x0 RW OPA2 non-inverting Input Mux
These bits selects the source for the non-inverting input on OPA2
Value Mode Description
0 DISABLE Input disabled
2 POSPAD POS PAD as input
3 OPA1INP OPA1 as input
4 OPATAP OPA0 Resistor ladder as input
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30. OPAMP - Operational Amplifier
43210
VIN
-
+
VOUT
Quick Facts
What?
The opamps are low power amplifiers with a high
degree of flexibility targeting a wide variety of stand-
ard opamp application areas. With flexible gain and
interconnection builtin programming they can be
configured to support multiple common opamp func-
tions, with all pins available externally for filter con-
figurations. Each opamp has a rail to rail input and a
rail to rail output.
Why?
The opamps are included to save energy on a pcb
compared to standalone opamps, but also reduce
system cost by replacing external opamps.
How?
Two of the opamps are made available as part of the
DAC, while the third opamp is standalone. An ADC
unity gain buffer mode configuration makes it possi-
ble to isolate kickback noise, in addition to popular
differential to single ended and differential to differ-
ential driver modes. The opamps can also be config-
ured as a one, two- or three-step cascaded PGA,
and for all of the built-in modes no external compo-
nents are necessary.
30.1 Introduction
The opamps are highly configurable general purpose opamps, suitable for simple filters and buffer applications. The three opamps can
be configured to support various operational amplifier functions through a network of muxes, with possibilities of selecting ranges of on-
chip non-inverting and inverting gain configurations, and selecting between outputs to various destinations. The opamps can also be
configured with external feedback in addition to supporting cascade connections between two or three opamps. The opamps are rail-to-
rail in and out. A user selectable mode has been added to optimize linearity, in which case the input voltage to the opamp is restricted
between VSS and VDD-1.2V.
30.2 Features
• 3 individually configurable opamps
• Opamps support rail-to-rail inputs and outputs
• Supports the following functions
• General Opamp Mode
• Voltage Follower Unity Gain
• Inverting Input PGA
• Non-inverting PGA
• Cascaded Inverting PGA
• Cascaded Non-inverting PGA
• Two Opamp Differential Amplifier
• Three Opamp Differential Amplifier
• Dual Buffer ADC Driver
• Programmable gain
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30.3 Functional Description
The three opamps can be configured to perform various opamp functions through a network of muxes. An overview of the opamps are
shown in the following figure. Two of the three opamps are part of the DAC, while the third opamp is standalone. The output of OPA0
can be routed to ADC CH0, OPA1 and various pin outputs. The output of OPA1 can be routed to ADC CH1, OPA2, and various pin
outputs. The output of OPA2 can be routed to ADC CH0, CH5, and various pin output destinations. All three opamps can also take
input from pins. Since OPA0 and OPA1 are part of the DAC, special considerations needs to be taken when both the DAC Ch0/Ch1
and OPA0/OPA1 are being used. For detailed explanation the reader is referred to 30.3.3 Opamp DAC Combination.
OPA0
DAC OPA0 Alternative
outputs
OPA0 Main
output
OPA0NEXT
OPA1
OPA1 Alternative
outputs
OPA1 Main
output
OPA1NEXT
OPA2
OPA2 Main
outputs
ADC CH5
input mux
POS0
NEG0
POS1
NEG1
POS2
NEG2
ADC CH0
input mux
ADC CH1
input mux
ADC CH0
input mux
Figure 30.1. OPAMP System Overview
A more detailed view of the three opamps, including the mux network is shown in the following figure. There is a set of input muxes for
each opamp, making it possible to select various input sources. The POSSEL mux connected to the positive input makes it possible to
select pin, another opamp output, or tap from the resistor network. Similarly, the NEGSEL mux on the negative input makes it possible
to select pin or a feedback path as its source. The feedback path can be a unity gain configuration, or selected from the resistor net-
work for programmable gain. The output of the opamp have different sets of outputs, a main output, an alternative output network and a
next output. These outputs make it possible to route the output to pin, another opamp input, ADC, or into the feedback path. For details
regarding configuring the outputs, the reader is referred to 30.3.1.2 Output Configuration. In addition, there is also a mux to configure
the resistor ladder to be connected to vss, pin, or another opamp output.
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4»
4»
+
mm 7+
V—‘/,
V—‘/,
4»
+
Mn 7*
J,
XE
Ehi
H
-
+
OPA0TAP
OPA0TAP
NEXTOUT0
NEXTOUT0
VSS
OPA0
POSSEL[2:0]
NEGSEL[1:0]
POS0
NEG0
PPEN
NPEN
Main output
Alternative output network
R1 R2
Unity gain
POSPAD
NEXTOUT0
NEGPAD
RESINMUX[3:0]
-
+
OPA1TAP
OPA1TAP
NEXTOUT0
NEXTOUT0
VSS
OPA1
POSSEL[2:0]
NEGSEL[1:0]
POS1
NEG1
PPEN
NPEN
Main output
Alternative output network
R1 R2
Unity gain
POSPAD
NEXTOUT1
NEGPAD
RESINMUX[3:0]
-
+
OPA2TAP
OPA0TAP
NEXTOUT1
NEXTOUT1
VSS
OPA2
POSSEL[2:0]
NEGSEL[1:0]
POS2
NEG2
PPEN
NPEN
Main output
R1 R2
Unity gain
POSPAD
NEGPAD
RESINMUX[3:0]
Figure 30.2. OPAMP Overview
30.3.1 Opamp Configuration
Since two of the three opamps (OPA0, OPA1) are part of the DAC, the opamp configuration registers are located in the DAC. The mux
registers for OPA0/OPA1 together with OPA2 registers are separate registers, also located under the DAC module. OPA0 and OPA1
can be enabled by setting OPAxEN in DACn_OPACTRL and CHxEN in CHxCTRL. OPA2 can be enabled by only setting OPA2EN in
DACn_OPACTRL.
30.3.1.1 Input Configuration
The inputs to the opamps are controlled through a set of input muxes. The mux connected to the positive input is configured by the
POSSEL bit-field in the DACn_OPAxMUX register. Similarly, the mux connected to the negative input is configured by setting the NEG-
SEL bit-field in DACn_OPAxMUX. To connect the pins to the input muxes, the pin switches must also be enabled. Setting the PPEN
bitfield enables to POSPADx, while setting the NPEN bit-field enables the NEGPADx, both located in DACn_OPAxMUX. The input into
the resistor ladder can be configured by setting the RESINMUX bitfield in DACn_OPAxMUX.
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30.3.1.2 Output Configuration
The opamp have two outputs, one main output and one alternative output with lower drive strength. These two outputs can be used to
drive the different outputs as shown in the following figure. The main opamp output can be used to drive the main output by setting
OUTMODE to MAIN in DACn_OPAxMUX. The alternative opamp output can drive the alternative output network by setting OUTMODE
to ALT in DACn_OPAxMUX. In addition, it is also possible to use the main opamp output to drive both the main output and the alterna-
tive output network by setting OUTMODE to ALL in DACn_OPAxMUX.
OPA0 Main output
OPA0 Alternative
output network
-
+
OPA0
OPA0
output MAIN/ALL
ALT/ALL
OUT0
OUT1
OUT2
OUT3
OUT4
NEXTOUT
ADC CH0
input mux
OPA1 Main output
OPA1 Alternative
output network
-
+
OPA1
OPA1
output MAIN/ALL
ALT/ALL
OUT0
OUT1
OUT2
OUT3
OUT4
NEXTOUT
ADC CH1
input mux
OPA2 Main outputs
-
+
OPA2
OPA2
output OUT0
OUT1
ADC CH5
input mux
ADC CH0
input mux
MAIN
Figure 30.3. Opamp Output State Overview
The alternative output network consists of connections to pins, ADC, and a connection to the next opamp (OPA0 to OPA1, and OPA1
to OPA2). The connections to pins can be individually enabled by configuring OUTPEN in DACn_OPAxMUX register. To enable casca-
ded opamp configurations, each opamp has a NEXTOUT connection. This output makes it possible to connect OPA0 to OPA1, and
OPA1 to OPA2. This output connection is enabled by setting NEXTOUT in DACn_OPAxMUX.
The opamps can also be routed to the ADC. OPA0 can be connected to ADC CH0, OPA1 to ADC CH1 and OPA2 can be connected to
both ADC CH1 and CH5. The ADC connections are created by routing the OPA output by setting corresponding bits in OUTPEN in
DACn_OPAxMUX. For OPA0 alternative output 4 is connected to ADC input mux CH0 when enabled. OPA1's alternative output 4 is
connected to ADC input mux CH1 when enabled. For OPA2, the two main outputs can be connected to ADC input mux CH0 and ADC
input mux CH5 respectively when enabled. See 28.3.4 Input Selection, in the ADC chapter for information on how to configure the ADC
input mux.
30.3.1.3 Gain Programming
The feedback path of each mux includes a resistor ladder, which can be used to select a set of gain values. The gain can be selected
by the RESSEL bit-field located in DACn_OPAxMUX register. The gain values are taken from tappings of the resistor ladder based on
ratio of R2/R1. It is also possible to bypass the resistor ladder in Unity Gain (UG) mode.
30.3.1.4 Offset Calibration
The offset calibration registers are located in different registers for the opamps. OPA0 and OPA1's offset can be set through the
CH0OFFSET and CH1OFFSET bit-fields respectively in DACn_CAL. The offset for OPA2 can be set through OPA2OFFSET in
DACn_OPAOFFSET.
30.3.1.5 Shorting Non-Inverting and Inverting Input
Functionality for offset calibration of the opamps has been added, this functionality is enabled by setting the OPAxSHORT bit-field in
DACn_OPAxCTRL. Setting this bit-field enables a switch that shorts between the inverting and non-inverting input of the OPA, effec-
tively driving the offset voltage of the opamp to the output. Using the ADC to measure this offset, the calibration register can be adjus-
ted to minimize the output offset.
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30.3.1.6 Low Pass Filter
The low pass filter is located between the pad and the positive input. The low-pass filter is designed to couple the input signal to local
VSS for high frequencies and has a 3 dB frequency of approximately 130 MHz when driven from a 50 ohm source. The filter adds a
parasitic capacitance of approximately 1.2 pF towards local VSS when enabled. The filter is enabled out of reset and can be disabled
by setting OPAxLPFDIS in DACn_OPAxCTRL.
30.3.1.7 Disabling of Rail-to-Rail Operation
Each opamp can have the input rail-to-rail stage disabled by setting the OPAxHCMDIS bit-field in DACn_OPACTRL. Disabling the rail-
to-rail input stage improves linearity of the opamp, thus improving the Total Harmonic Distortion, THD, at the cost of reduced input sig-
nal swing.
30.3.2 Opamp Modes
The opamp can be configured to perform different Operational Amplifier functions by configuring the internal signal routing between the
opamps. The modes available are described in the following sections.
30.3.2.1 General Opamp Mode
In this mode the resistor ladder is isolated from the feedback path and input signal routing is defined by OPAxPOSSEL and OPAxNEG-
SEL in DACn_OPAxMUX. The output signal routing is defined by OUTPEN in DACn_OPAxMUX.
Table 30.1. General Opamp Mode Configuration
OPA bit-fields OPA Configuration
OPAx POSSEL POSPADx
OPAx NEGSEL OPATAP, UG, NEGPADx
OPAx RESINMUX NEXTOUT, POSPADx, NEGPADx VSS
30.3.2.2 Voltage Follower Unity Gain
In this mode the unity gain feedback path is selected for the negative input by setting the OPAxNEGSEL bit-field to UG in the
DACn_OPAxMUX register as shown in the following figure. The positive input is selected by the OPAxPOSSEL bit-field, and the output
is configured by the OUTPEN bit-field, both in the DACn_OPAxMUX register.
VIN
-
+
VOUT
Figure 30.4. Voltage Follower Unity Gain Overview
Table 30.2. Voltage Follower Unity Gain Configuration
OPA bit-fields OPA Configuration
OPAx POSSEL OPATAP, NEXTOUT, POSPADx
OPAx NEGSEL UG
OPAx RESINMUX DISABLE
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30.3.2.3 Inverting Input PGA
The following figure shows the inverting input PGA configuration. In this mode the negative input is connected to the resistor ladder by
setting the OPAxNEGSEL bit-field to OPATAP in the DACn_OPAxMUX register. This setting provides a programmable gain on the neg-
ative input, which can be set by choosing the wanted gain value in the RESSEL bit-field in DACn_OPAxMUX. Signal ground for the
positive input can be generated off-chip through the pad by setting OPAxPOSSEL bitfield to PAD in DACn_OPAxMUX. In addition the
output is configured by the OUTPEN bit-field, located in DACn_OPAxMUX.
VOUT
VOUT=-(VIN-POS) R2/R1 + POS
R1 R2
POS
VIN
-
+
Figure 30.5. Inverting Input PGA Overview
Table 30.3. Inverting Input PGA Configuration
OPA bit-fields OPA Configuration
OPAx POSSEL POSPADx
OPAx NEGSEL OPATAP
OPAx RESINMUX NEXTOUT, NEGPADx, POSPADx
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30.3.2.4 Non-Inverting PGA
The following figure shows the non-inverting input configuration. In this mode the negative input is connected to the resistor ladder by
setting the OPAxNEGSEL bit-field to OPATAP in DACn_OPAxMUX. This setting provides a programmable gain on the negative input,
which can be set by choosing the wanted gain value in the RESSEL bit-field in DACn_OPAxMUX. In addition the OPAxRESINMUX bit-
field must be set to VSS or NEGPAD in DACn_OPAxMUX. The positive input is selected by the OPAxPOSSEL bit-field, and the output
is configured by the OUTPEN bit-field, both located in DACn_OPAxMUX.
R1 R2
VIN
VOUT
VOUT=VIN(1+ R2/R1)
-
+
Figure 30.6. Non-Inverting PGA Overview
Table 30.4. Non-Inverting PGA Configuration
OPA bit-fields OPA Configuration
OPAx POSSEL NEXTOUT, POSPADx
OPAx NEGSEL OPATAP
OPAx RESINMUX VSS, NEGPAD
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30.3.2.5 Cascaded Inverting PGA
This mode enables the opamp signals to be internally configured to cascade two or three opamps in inverting mode as shown in the
following figure. In both cases the positive input will be configured to signal ground by setting OPAxPOSSEL bit-field to PAD in
DACn_OPAx_MUX. When cascaded, the negative input is connected to the resistor ladder by setting the OPAxNEGSEL bit-field to
OPATAP in DACn_OPAxMUX. The input to the resistor ladder can be configured in the OPAxRESINMUX bit-field in DAC_nOPAxMUX.
The output from OPA0 can be connected to OPA1 to create the second stage by setting the NEXTOUT bit-field in DACn_OPAxMUX.
To complete the stage, OPA1RESINMUX field must be set to OPA0INP. Similarly, the last stage can be created by setting the NEXT-
OUT bit-field in DACn_OPA1MUX and OPA2RESINMUX bit-field to OPA1INP in DACn_OPA2MUX.
R1 R2
VIN
POS0
VOUT1=-(VIN-POS0) x R2/R1 + POS0
VOUT2=-(VOUT1-POS1) x R2/R1 + POS1
VOUT3=-(VOUT2-POS3) x R2/R1 + POS3
R1 R2
POS1
R1 R2
POS2
-
+
-
+
-
+
Figure 30.7. Cascaded Inverting PGA Overview
Table 30.5. Cascaded Inverting PGA Configuration
OPA OPA bit-fields OPA Configuration
OPA0 POSSEL POSPAD0
OPA0 NEGSEL OPA0TAP
OPA0 RESINMUX NEGPAD0
OPA0 NEXTOUT 1
OPA1 POSSEL POSPAD1
OPA1 NEGSEL OPATAP
OPA1 RESINMUX OPA0INP
OPA1 NEXTOUT 1
OPA2 POSSEL POSPAD2
OPA2 NEGSEL OPATAP
OPA2 RESINMUX OPA1INP
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30.3.2.6 Cascaded Non-Inverting PGA
This mode enables the opamp signals to be internally configured to cascade two or three opamps in noninverting mode as shown in the
following figure. In both cases the negative input for all opamps will be connected to the resistor ladder by setting the OPAxNEGSEL
bit-field to OPATAP. In addition the resistor ladder input must be set to VSS or NEGPADx in the OPAxRESINMUX in DACn_OPAx-
MUX. When cascaded, the positive input on OPA0 is configured by the OPA0POSSEL bit-field. The output from OPA0 can be connec-
ted to OPA1 to create the second stage by setting NEXTOUT in DACn_OPA0MUX. To complete the stage, the OPA1POSSEL bit-field
must be set to OPA0INP in DACn_OPA1MUX. Similarly, the last stage can be created by setting NEXTOUT in DACn_OPA1MUX and
OPA2POSSEL bit-field to OPA1INP in DACn_OPA2MUX.
R1 R2
VIN VOUT1=VIN(1+ R2/R1)
VOUT2=VIN(1+ R2/R1)
VOUT3=VIN(1+ R2/R1)
R1 R2 R1 R2
-
+
-
+
-
+
Figure 30.8. Cascaded Non-Inverting PGA Overview
Table 30.6. Cascaded Non-Inverting PGA Configuration
OPA OPA bit-fields OPA Configuration
OPA0 POSSEL POSPAD0
OPA0 NEGSEL OPATAP
OPA0 RESINMUX VSS, NEGPAD0
OPA0 NEXTOUT 1
OPA1 POSSEL OPA0INP
OPA1 NEGSEL OPATAP
OPA1 RESINMUX VSS, NEGPAD1
OPA1 NEXTOUT 1
OPA2 POSSEL OPA1INP
OPA2 NEGSEL OPATAP
OPA2 RESINMUX VSS, NEGPAD2
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30.3.2.7 Two Opamp Differential Amplifier
This mode enables OPA0 and OPA1 or OPA1 and OPA2 to be internally configured to form a two opamp differential amplifier as shown
in the following figure. When using OPA0 and OPA1, the positive input of OPA0 can be connected to any input by configuring the
OPA0POSSEL bit-field in DACn_OPA0MUX. The OPA0 feedback path must be configured to unity gain by setting the OPA0NEGSEL
bit-field to UG in DACn_OPA0MUX. In addition, the OPA0RESINMUX bit-field must be set to DISABLED. The OPA0OUT must be con-
nected to OPA1 by setting NEXTOUT in DACn_OPA0MUX, and OPA1RESINMUX to OPA0INP. The positive input on OPA1 can be set
by configuring OPA1POSSEL. The OPA1 output can be configured by configuring the OUTPEN and OUTMODE bit-field.
When using OPA1 and OPA2, the positive input of OPA1 can be connected to any input by configuring the OPA1POSSEL bit-field in
DACn_OPA1MUX. The OPA1 feedback path must be configured to unity gain by setting the OPA1NEGSEL bit-field to UG in
DACn_OPA1MUX. In addition, the OPA1RESINMUX bit-field must be set to DISABLED. The OPA1OUT must be connected to OPA2
by setting NEXTOUT in DACn_OPA1MUX, and OPA2RESINMUX to OPA1INP. The positive input on OPA2 can be set by configuring
OPA2POSSEL. The OPA2 output can be configured by configuring the OUTPEN and OUTMODE bit-field.
Note: When making a differential connection with the ADC, only OPA1 and OPA2 can be used
R1 R2
V2
V1 VDIFF=(V2-V1)R2/R1
R1 R2
V2
V1 VDIFF=(V2-V1)R2/R1
OPA1
-
+
OPA2
-
+
OPA1
-
+
OPA0
-
+
Figure 30.9. Two Opamp Differential Amplifier Overview
Table 30.7. OPA0/OPA1 Differential Amplifier Configuration
OPA OPA bit-fields OPA Configuration
OPA0 POSSEL POSPAD1
OPA0 NEGSEL UG
OPA0 RESINMUX DISABLE
OPA0 NEXTOUT 1
OPA1 POSSEL POSPAD1
OPA1 NEGSEL OPATAP
OPA1 RESINMUX OPA1INP
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Table 30.8. OPA1/OPA2 Differential Amplifier Configuration
OPA OPA bit-fields OPA Configuration
OPA1 POSSEL POSPAD1
OPA1 NEGSEL UG
OPA1 RESINMUX DISABLE
OPA1 NEXTOUT 1
OPA2 POSSEL POSPAD1
OPA2 NEGSEL OPATAP
OPA2 RESINMUX OPA1INP
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30.3.2.8 Three Opamp Differential Amplifier
This mode enables the three opamps to be internally configured to form a three opamp differential amplifier as shown in the following
figure. Both OPA0 and OPA1 can be configured in the same unity gain mode. For both OPA0/OPA1 the positive input can be connec-
ted to any input by configuring the OPA0POSSEL/OPA1POSSEL bit-field. The OPA0/OPA1 feedback path must be configured to unity
gain by setting the OPA0NEGSEL/OPA1NEGSEL bit-field to UG. In addition the OPA0RESINMUX/ OPA1RESINMUX bit-fields must be
set to DISABLED. The OPA1 output must be connected to OPA2 by setting the NEXTOUT bit-field in DACn_OPA1MUX and
OPA2RESINMUX to OPA1INP in DACn_OPA2MUX. In addition the OPA2POSSEL must be set to 0PATAP. The OPA2 output can be
configured by configuring the OUTPEN and OUTMODE bit-field.
R1 R2
V2
VOUT
VOUT=(V2-V1)R2/R1
R1 R2
V1
OPA0
-
+
OPA1
-
+
OPA2
-
+
Figure 30.10. Three Opamp Differential Amplifier Overview
The gain values for the Three Opamp Differential Amplifier is determined by the combination of the gain settings of OPA0 and OPA2.
The 3 different gain values available, 1/3, 1 and 3, can be programmed as shown in the table below.
Table 30.9. Three Opamp Differential Amplifier Gain Programming
Gain OPA0 RESSEL OPA2 RESSEL
1/3 4 0
1 1 1
3 0 4
Table 30.10. Three Opamp Differential Amplifier Configuration
OPA OPA bit-fields OPA Configuration
OPA0 POSSEL POSPAD
OPA0 NEGSEL UG
OPA0 RESINMUX DISABLE
OPA1 POSSEL POSPAD
OPA1 NEGSEL UG
OPA1 RESINMUX DISABLE
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OPA OPA bit-fields OPA Configuration
OPA1 NEXTOUT 1
OPA2 POSSEL OPATAP
OPA2 NEGSEL OPATAP
OPA2 RESINMUX OPA1INP
30.3.2.9 Dual Buffer ADC Driver
It is possible to use OPA0 and OPA1 to form a Dual Buffer ADC driver as shown in the following figure. Both opamps used can be
configured in the same way. The positive input is configured by setting the 0PAxPOSSEL to PAD and the negative input can be con-
nected to the resistor ladder by setting OPATAP in DACn_OPAxMUX. The output from the opamps can be configured to connect to the
ADC by setting OUTMODE to ALT or ALL in DACn_OPAxMUX.
R1 R2
VIP
VOUTP=VIP(1+ R2/R1)
or
VOUTP = VIP (Unity Gain)
-
+
R1 R2
VIN
VOUTN=VIN(1+ R2/R1)
or
VOUTN = VIN (Unity Gain)
-
+
Figure 30.11. Dual Buffer ADC Driver Overview
Table 30.11. Dual Buffer ADC Driver Configuration
OPA OPA bit-fields OPA Configuration
OPA0 POSSEL POSPAD0
OPA0 NEGSEL OPATAP
OPA0 RESINMUX VSS
OPA1 POSSEL POSPAD1
OPA1 NEGSEL OPATAP
OPA1 RESINMUX VSS
30.3.3 Opamp DAC Combination
Since two of the opamps are part of the DAC it is not possible to use both DAC channels and all three opamps at the same time. If both
DAC channels are used, only OPA2 is available out of the 3 opamps. However, it is possible to use one of the DAC channels in combi-
nation with OPA0/OPA1. OPA1 is available when DAC channel 0 is in use and OPA0 is available when DAC channel 1 is used. When
using the opamp DAC combination, the DAC CONVMODE can only be configured to either CONTINUOUS or SAMPLEHOLD mode.
The CONVMODE bitfield can be configured in DACn_CTRL register. In the opamp/DAC combination, the DAC channel enabled is con-
figured through the DAC registers while the opamp is controlled through the opamp registers.
30.4 Register Description
The register description of the opamp can be found in 29.5 Register Description in the DAC chapter.
30.5 Register Map
The register map of the opamp can be found in 29.5 Register Description in the DAC chapter.
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31. AES - Advanced Encryption Standard Accelerator
43210
How are you? AES &G#%5
!T4/#2I am fine AES
Quick Facts
What?
A fast and energy efficient hardware accelerator for
AES-128 and AES-256 encryption and decryption.
Why?
Efficient encryption/decryption with little or no CPU
intervention helps to meet the speed and energy de-
mands of the application.
How?
High AES throughput allows the EFM32WG to
spend more time in lower energy modes. In addition,
specialized data access functions allow autonomous
DMA/AES operation in both EM0 and EM1.
31.1 Introduction
The Advanced Encryption Standard (FIPS-197) is a symmetric block cipher operating on 128-bit blocks of data and 128-, 192- or 256-
bit keys.
The AES accelerator performs AES encryption and decryption with 128-bit or 256-bit keys. Encrypting or decrypting one 128-bit data
block takes 54 HFCORECLK cycles with 128-bit keys and 75 HFCORECLK cycles with 256-bit keys. The AES module is an AHB slave
which enables efficient access to the data and key registers. All write accesses to the AES module must be 32-bit operations, i.e. 8- or
16-bit operations are not supported.
31.2 Features
• AES hardware encryption/decryption
• 128-bit key (54 HFCORECLK cycles)
• 256-bit key (75 HFCORECLK cycles)
• Efficient CPU/DMA support
• Interrupt on finished encryption/decryption
• DMA request on finished encryption/decryption
• Key buffer in AES128 mode
• Optional XOR on Data write
• Configurable byte ordering
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En v «Jan
De: on
31.3 Functional Description
Some data and a key must be loaded into the KEY and DATA registers before an encryption or decryption can take place. The input
data before encryption is called the PlainText and output from the encryption is called CipherText. For encryption, the key is called
PlainKey. After one encryption, the resulting key in the KEY registers is the CipherKey. This key must be loaded into the KEY registers
before every decryption. After one decryption, the resulting key will be the PlainKey. The resulting PlainKey/CipherKey is only depend-
ent on the value in the KEY registers before encryption/decryption. The resulting keys and data are shown in the following figure.
PlainText CipherText
PlainKey CipherKey
Encryption
Decryption
Encryption
Decryption
Figure 31.1. AES Key and Data Definitions
31.3.1 Encryption/Decryption
The AES module can be set to encrypt or decrypt by clearing/setting the DECRYPT bit in AES_CTRL. The AES256 bit in AES_CTRL
configures the size of the key used for encryption/decryption. The AES_CTRL register should not be altered while AES is running, as
this may lead to unpredictable behaviour.
An AES encryption/decryption can be started in the following ways:
• Writing a 1 to the START bit in AES_CMD
• Writing 4 times 32 bits to AES_DATA when the DATASTART control bit is set
• Writing 4 times 32 bits to AES_XORDATA when the XORSTART control bit is set
An AES encryption/decryption can be stopped by writing a 1 to the STOP bit in AES_CMD. The RUNNING bit in AES_STATUS indi-
cates that an AES encryption/decryption is ongoing.
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31.3.2 Data and Key Access
The AES module contains a 128-bit DATA (State) register and two 128-bit KEY registers defined as DATA3-DATA0, KEY3-KEY0
(KEYL) and KEY7-KEY4 (KEYH). In AES128 mode, the 128-bit key is read from KEYL, while both KEYH and KEYL are used in
AES256 mode. The AES module has configurable byte ordering which is configured in BYTEORDER in AES_CTRL. The following fig-
ure illustrates how data written to the AES registers is mapped to the key and state defined in the Advanced Encryption Standard
(FIPS-197). The figure presents the key byte order for 256-bit keys. In 128-bit mode with BYTEORDER cleared, a16 represents the first
byte of the 128-bit key. When BYTEORDER is set, a0 represents the first byte in the key. AES encryption/decryption takes two extra
cycles when BYTEORDER is set. BYTEORDER has to be set prior to loading the data and key registers.
BYTEORDER = 1
DATA3
DATA2
DATA1
DATA0
KEY4
KEY5
KEY6
KEY7
DATA KEYH
[7:0]
[15:8]
[23:16]
[31:24]
a0a4
a1a5
a2a6
a8a12
a9a13
a10 a14
a11 a15
a3a7
Byte order in word
S0,0 S0,1
S1,0 S1,1
S2,0 S2,1
S0,2 S0,3
S1,2 S1,3
S2,2 S2,3
S3,2 S3,3
S3,0 S3,1
KEY0
KEY1
KEY2
KEY3
KEYL
a16 a20
a17 a21
a18 a22
a24 a28
a25 a29
a26 a30
a27 a31
a19 a23
DATA0
DATA1
DATA2
DATA3
KEY3
KEY2
KEY1
KEY0
DATA KEYL
[31:24]
[23:16]
[15:8]
[7:0]
a0a4
a1a5
a2a6
a8a12
a9a13
a10 a14
a11 a15
a3a7
Byte order in word
S0,0 S0,1
S1,0 S1,1
S2,0 S2,1
S0,2 S0,3
S1,2 S1,3
S2,2 S2,3
S3,2 S3,3
S3,0 S3,1
KEY7
KEY6
KEY5
KEY4
KEYH
a16 a20
a17 a21
a18 a22
a24 a28
a25 a29
a26 a30
a27 a31
a19 a23
BYTEORDER = 0
Figure 31.2. AES Data and Key Orientation as Defined in the Advanced Encryption Standard
The registers DATA3-DATA0, are not memory mapped directly, but can be written/read by accessing AES_DATA or AES_XORDATA.
The same applies for the key registers, KEY3-KEY0 which are accessed through AES_KEYLn (n=A, B, C or D), while KEY7-KEY4 are
accessed through KEYHn (n=A, B, C or D). Writing DATA3-DATA0 is then done through 4 consecutive writes to AES_DATA (or
AES_XORDATA), starting with the word which is to be written to DATA0. For each write, the words will be word wise barrel shifted
towards the least significant word. Accessing the KEY registers are done in the same fashion through KEYLn and KEYHn. See the
following figure. Note that KEYHA, KEYHB, KEYHC and KEYHD are really the same register, just mapped to four different addresses.
You can then choose freely which of these addresses you want to use to update the KEY7-KEY4 registers. The same principle applies
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to the KEYLn registers. Mapping the same registers to multiple addresses like this, allows the DMA controller to write a full 256-bit key
in one sweep, when incrementing the address between each word write.
DATA3Write data Read data
Shift on write and read
DATA2 DATA1 DATA0
AES_DATA/
AES_XORDATA
KEY3Write data Read data
Shift on write and read
KEY2 KEY1 KEY0
AES_KEYLn
KEY7Write data Read data
Shift on write and read
KEY6 KEY5 KEY4
AES_KEYHn
Figure 31.3. AES Data and Key Register Operation
31.3.2.1 Key Buffer
When encrypting multiple blocks of data in a row, the PlainKey must be written to the key register between each encryption, since the
contents of the key registers will be turned into the CipherKey during the encryption. The opposite applies when decrypting, where you
have to re-supply the CipherKey between each block. However, in AES128 mode, KEY4-KEY7 can be used as a buffer register, to hold
an extra copy of the KEY3-KEY0 registers. When KEYBUFEN is set in AES_CTRL, the contents of KEY7-KEY4 are copied to KEY3-
KEY0, when an encryption/decryption is started. This eliminates the need for re-loading the KEY for every encrypted/decrypted block
when running in AES128 mode.
31.3.2.2 Data Write XOR
The AES module contains an array of XOR gates connected to the DATA registers, which can be used during a data write to XOR the
existing contents of the registers with the new data written. To use the XOR function, the data must be written to AES_XORDATA loca-
tion.
Reading data from AES_XORDATA is equivalent to reading data from AES_DATA.
31.3.2.3 Start on Data Write
The AES module can be configured to start an encryption/decryption when the new data has been written to AES_DATA and/or
AES_XORDATA. A 2-bit counter is incremented each time the AES_DATA or AES_XORDATA registers are written. This counter indi-
cates which data word is written. If DATASTART/ XORSTART in AES_CTRL is set, an encryption will start each time the counter over-
flows (DATA3 is written). Writing to the AES_CTRL register will reset the counter to 0.
31.3.3 Interrupt Request
The DONE interrupt flag is set when an encryption/ decryption has finished.
31.3.4 DMA Request
The AES module has 4 DMA requests which are all set on a finished encryption/decryption and cleared on the following conditions:
• DATAWR: Cleared on a AES_DATA write or AES_CTRL write
• XORDATAWR: Cleared on a AES_XORDATA write or AES_CTRL write
• DATARD: Cleared on a AES_DATA read or AES_CTRL write
• KEYWR: Cleared on a AES_KEYHn write or AES_CTRL write
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31.3.5 Block Chaining Example
The example below illustrates how the AES module could be configured to perform Cipher Block Chaining with 128-bit keys.
1. Configure module to encryption, key buffer enabled and XORSTART in AES_CTRL.
2. Write 128-bit initialization vector to AES_DATA, starting with least significant word.
3. Write PlainKey to AES_KEYHn, starting with least significant word.
4. Write PlainText to AES_XORDATA, starting with least significant word. Encryption will be started when the DATA3 is written.
KEYH (PlainKey) will be copied to KEYL before encryption starts.
5. When encryption finished, read CipherText from AES_DATA, starting with least significant word.
6. Loop to step 4, if new PlainText is available.
31.4 Register Map
The offset register address is relative to the registers base address.
Offset Name Type Description
0x000 AES_CTRL RW Control Register
0x004 AES_CMD W1 Command Register
0x008 AES_STATUS RStatus Register
0x00C AES_IEN RW Interrupt Enable Register
0x010 AES_IF RInterrupt Flag Register
0x014 AES_IFS W1 Interrupt Flag Set Register
0x018 AES_IFC (R)W1 Interrupt Flag Clear Register
0x01C AES_DATA RW(a) DATA Register
0x020 AES_XORDATA RW(a) XORDATA Register
0x030 AES_KEYLA RW(a) KEY Low Register
0x034 AES_KEYLB RW(a) KEY Low Register
0x038 AES_KEYLC RW(a) KEY Low Register
0x03C AES_KEYLD RW(a) KEY Low Register
0x040 AES_KEYHA RW(a) KEY High Register
0x044 AES_KEYHB RW(a) KEY High Register
0x048 AES_KEYHC RW(a) KEY High Register
0x04C AES_KEYHD RW(a) KEY High Register
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31.5 Register Description
31.5.1 AES_CTRL - Control Register
Offset Bit Position
0x000
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
16
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
Reset
0
0
0
0
0
0
Access
RW
RW
RW
RW
RW
RW
Name
BYTEORDER
XORSTART
DATASTART
KEYBUFEN
AES256
DECRYPT
Bit Name Reset Access Description
31:7 Reserved To ensure compatibility with future devices, always write bits to 0. More information in 2.1 Conven-
tions.
6 BYTEORDER 0 RW Configure byte order in data and key registers
When set, the byte orders in the data and key registers are swapped before and after encryption/decryption.
5 XORSTART 0 RW AES_XORDATA Write Start
Set this bit to start encryption/decryption when DATA3 is written through AES_XORDATA.
4 DATASTART 0 RW AES_DATA Write Start
Set this bit to start encryption/decryption when DATA3 is written through AES_DATA.
3 Reserved To ensure compatibility with future devices, always write bits to 0. More information in 2.1 Conven-
tions.
2 KEYBUFEN 0 RW Key Buffer Enable
Enable/disable key buffer in AES-128 mode.
1 AES256 0 RW AES-256 Mode
Select AES-128 or AES-256 mode.
Value Description
0 AES-128 mode
1 AES-256 mode
0 DECRYPT 0 RW Decryption/Encryption Mode
Select encryption or decryption.
Value Description
0 AES Encryption
1 AES Decryption
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31.5.2 AES_CMD - Command Register
Offset Bit Position
0x004
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
16
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
Reset
0
0
Access
W1
W1
Name
STOP
START
Bit Name Reset Access Description
31:2 Reserved To ensure compatibility with future devices, always write bits to 0. More information in 2.1 Conven-
tions.
1 STOP 0 W1 Encryption/Decryption Stop
Set to stop encryption/decryption.
0 START 0 W1 Encryption/Decryption Start
Set to start encryption/decryption.
31.5.3 AES_STATUS - Status Register
Offset Bit Position
0x008
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
16
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
Reset
0
Access
R
Name
RUNNING
Bit Name Reset Access Description
31:1 Reserved To ensure compatibility with future devices, always write bits to 0. More information in 2.1 Conven-
tions.
0 RUNNING 0 R AES Running
This bit indicates that the AES module is running an encryption/decryption.
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31.5.4 AES_IEN - Interrupt Enable Register
Offset Bit Position
0x00C
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
16
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
Reset
0
Access
RW
Name
DONE
Bit Name Reset Access Description
31:1 Reserved To ensure compatibility with future devices, always write bits to 0. More information in 2.1 Conven-
tions.
0 DONE 0 RW Encryption/Decryption Done Interrupt Enable
Enable/disable interrupt on encryption/decryption done.
31.5.5 AES_IF - Interrupt Flag Register
Offset Bit Position
0x010
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
16
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
Reset
0
Access
R
Name
DONE
Bit Name Reset Access Description
31:1 Reserved To ensure compatibility with future devices, always write bits to 0. More information in 2.1 Conven-
tions.
0 DONE 0 R Encryption/Decryption Done Interrupt Flag
Set when an encryption/decryption has finished.
31.5.6 AES_IFS - Interrupt Flag Set Register
Offset Bit Position
0x014
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
16
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
Reset
0
Access
W1
Name
DONE
Bit Name Reset Access Description
31:1 Reserved To ensure compatibility with future devices, always write bits to 0. More information in 2.1 Conven-
tions.
0 DONE 0 W1 Encryption/Decryption Done Interrupt Flag Set
Write to 1 to set encryption/decryption done interrupt flag
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31.5.7 AES_IFC - Interrupt Flag Clear Register
Offset Bit Position
0x018
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
16
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
Reset
0
Access
(R)W1
Name
DONE
Bit Name Reset Access Description
31:1 Reserved To ensure compatibility with future devices, always write bits to 0. More information in 2.1 Conven-
tions.
0 DONE 0 (R)W1 Encryption/Decryption Done Interrupt Flag Clear
Write to 1 to clear encryption/decryption done interrupt flag
31.5.8 AES_DATA - DATA Register (Actionable Reads)
Offset Bit Position
0x01C
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
16
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
Reset
0x00000000
Access
RW
Name
DATA
Bit Name Reset Access Description
31:0 DATA 0x00000000 RW Data Access
Access data through this register.
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31.5.9 AES_XORDATA - XORDATA Register (Actionable Reads)
Offset Bit Position
0x020
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
16
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
Reset
0x00000000
Access
RW
Name
XORDATA
Bit Name Reset Access Description
31:0 XORDATA 0x00000000 RW XOR Data Access
Access data with XOR function through this register.
31.5.10 AES_KEYLA - KEY Low Register (Actionable Reads)
Offset Bit Position
0x030
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
16
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
Reset
0x00000000
Access
RW
Name
KEYLA
Bit Name Reset Access Description
31:0 KEYLA 0x00000000 RW Key Low Access A
Access the low key words through this register.
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31.5.11 AES_KEYLB - KEY Low Register (Actionable Reads)
Offset Bit Position
0x034
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
16
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
Reset
0x00000000
Access
RW
Name
KEYLB
Bit Name Reset Access Description
31:0 KEYLB 0x00000000 RW Key Low Access B
Access the low key words through this register.
31.5.12 AES_KEYLC - KEY Low Register (Actionable Reads)
Offset Bit Position
0x038
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
16
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
Reset
0x00000000
Access
RW
Name
KEYLC
Bit Name Reset Access Description
31:0 KEYLC 0x00000000 RW Key Low Access C
Access the low key words through this register.
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31.5.13 AES_KEYLD - KEY Low Register (Actionable Reads)
Offset Bit Position
0x03C
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
16
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
Reset
0x00000000
Access
RW
Name
KEYLD
Bit Name Reset Access Description
31:0 KEYLD 0x00000000 RW Key Low Access D
Access the low key words through this register.
31.5.14 AES_KEYHA - KEY High Register (Actionable Reads)
Offset Bit Position
0x040
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
16
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
Reset
0x00000000
Access
RW
Name
KEYHA
Bit Name Reset Access Description
31:0 KEYHA 0x00000000 RW Key High Access A
Access the high key words through this register.
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31.5.15 AES_KEYHB - KEY High Register (Actionable Reads)
Offset Bit Position
0x044
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
16
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
Reset
0x00000000
Access
RW
Name
KEYHB
Bit Name Reset Access Description
31:0 KEYHB 0x00000000 RW Key High Access B
Access the high key words through this register.
31.5.16 AES_KEYHC - KEY High Register (Actionable Reads)
Offset Bit Position
0x048
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
16
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
Reset
0x00000000
Access
RW
Name
KEYHC
Bit Name Reset Access Description
31:0 KEYHC 0x00000000 RW Key High Access C
Access the high key words through this register.
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31.5.17 AES_KEYHD - KEY High Register (Actionable Reads)
Offset Bit Position
0x04C
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
16
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
Reset
0x00000000
Access
RW
Name
KEYHD
Bit Name Reset Access Description
31:0 KEYHD 0x00000000 RW Key High Access D
Access the high key words through this register.
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32. GPIO - General Purpose Input/Output
43210
Device
GPIO
Peripherals
Peripherals
ARM
Cortex-M4
Quick Facts
What?
The GPIO (General Purpose Input/Output) is used
for pin configuration and direct pin manipulation and
sensing as well as routing for peripheral pin connec-
tions.
Why?
Easy to use and highly configurable input/ output
pins are important to fit many communication proto-
cols as well as minimizing software control over-
head. Flexible routing of peripheral functions helps
to ease PCB layout.
How?
Each pin on the device can be individually config-
ured as either an input or an output with several dif-
ferent drive modes. Also, individual bit manipulation
registers minimizes control overhead. Peripheral
connections to pins can be routed to several differ-
ent locations, thus solving congestion issues that
may arise with multiple functions on the same pin.
Fully asynchronous interrupts can also be generated
from any pin.
32.1 Introduction
In the EFM32WG devices the General Purpose Input/Output (GPIO) pins are organized into ports with up to 16 pins each. These pins
can individually be configured as either an output or input. More advanced configurations like open-drain, filtering and drive strength
can also be configured individually for the pins. The GPIO pins can also be overridden by peripheral pin connections, like Timer PWM
outputs or USART communication, which can be routed to several locations on the device. The GPIO supports up to 16 asynchronous
external pin interrupts, which enables interrupts from any pin on the device. Also, the input value of a pin can be routed through the
Peripheral Reflex System to other peripherals.
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32.2 Features
• Individual configuration for each pin
• Tristate (reset state)
• Push-pull
• Open-drain
• Pull-up resistor
• Pull-down resistor
• Four drive strength modes
• HIGH
• STANDARD
• LOW
• LOWEST
• EM4 IO pin retention. This includes
• Output enable
• Output value
• Pull enable
• Pull direction
• EM4 wake-up on selected GPIO pins
• Glitch suppression input filter.
• Analog connection to e.g. ADC or LCD.
• Alternate functions (e.g. peripheral outputs and inputs)
• Routed to several locations on the device
• Pin connections can be enabled individually
• Output data can be overridden by peripheral
• Output enable can be overridden by peripheral
• Toggle, set and clear registers for output data
• Dedicated data input register (read-only)
• Interrupts
• 2 interrupt lines from up to 16 pending sources
• All GPIO pins are selectable
• Separate enable, status, set and clear registers
• Asynchronous sensing
• Rising, falling or both edges
• Wake up from EM0-EM3
• Peripheral Reflex System producer
• All GPIO pins are selectable
• Configuration lock functionality to avoid accidental changes
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32.3 Functional Description
An overview of the GPIO module is shown in Figure 32.1 Pin Configuration on page 971.The GPIO pins are grouped into 16- pin
ports. Each individual GPIO pin is called Pxn where x indicates the port (A, B, C ...) and n indicates the pin number (0,1,....,15). Fewer
than 16 bits may be available on some ports, depending on the total number of I/O pins on the package. After a reset both input and
output is disabled for all pins on the device, except for debug pins. To use a pin, the port GPIO_Px_MODEL/GPIO_Px_MODEH regis-
ters must be configured for the pin to make it an input or output. These registers can also do more advanced configuration, which is
covered in 32.3.1 Pin Configuration. When the port is either configured as an input or an output, the Data In Register (GPIO_Px_DIN)
can be used to read the level of each pin in the port (bit n in the register is connected to pin n on the port). When configured as an
output, the value of the Data Out Register (GPIO_Px_DOUT) will be driven to the pin.
The DOUT value can be changed in 4 different ways
• Writing to the GPIO_Px_DOUT register.
• Writing a 1 to a bit in the GPIO_Px_DOUTSET register sets the corresponding DOUT bit
• Writing a 1 to a bit in the GPIO_Px_DOUTCLR register clears the corresponding DOUT bit
• Writing a 1 to a bit in the GPIO_Px_DOUTTGL register toggles the corresponding DOUT bit
Reading the GPIO_Px_DOUT register will return its contents. Reading the GPIO_Px_DOUTSET, GPIO_Px_CLR or GPIO_Px_TGL will
return 0.
Port Control
VSS
MODEn[3:0]
DOUT
VDD
Output enable
Input enable
Data out
DIN
Pull-down enable
Pull-up enable
Output enable
Output value
1
Glitch
suppressio
n filter
Filter enable
ESD
protection
ESD
protection
Alternate function override
Alternate function output enable
Alternate function data out
Alternate function input
Interrupt input
PRS
Analog connection
Figure 32.1. Pin Configuration
Note: There is no ESD diode to Vdd because if using LCD voltage boost the pin voltage will be higher than Vdd. Nevertheless there is
an ESD protection block against over voltage.
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32.3.1 Pin Configuration
In addition to setting the pins as either outputs or inputs, the GPIO_Px_MODEL and GPIO_Px_MODEH registers can be used for more
advanced configurations. GPIO_Px_MODEL contains 8 bit fields named MODEn (n=0,1,..7) which control pins 0-7, while
GPIO_Px_MODEH contains 8 bit fields named MODEn (n=8,9,..15) which control pins 8-15. In some modes GPIO_Px_DOUT is also
used for extra configurations like pull-up/down and glitch suppression filter enable. The following table shows the available configura-
tions.
MODEn Input Output DOUT Pulldown Pullup Alt. strength Input
Filter
Description
0b0000 Disabled Disabled 0 Input disabled
1 On Input disabled with pull-up
0b0001 Enabled 0 Input enabled
1 On Input enabled with filter
0b0010 0 On Input enabled with pull-down
1 On Input enabled with pull-up
0b0011 0 On On Input enabled with pull-down and fil-
ter
1 On On Input enabled with pull-up and filter
0b0100 Push-pull x Push-pull
0b0101 x On Push-pull with alt. drive strength
0b0110 Open Source (Wired-
OR)
x Open-source
0b0111 x On Open-source with pull-down
0b1000 Open Drain (Wired-
AND)
Open-drain
0b1001 x On Open-drain with filter
0b1010 x On Open-drain with pull-up
0b1011 x On On Open-drain with pull-up and filter
0b1100 x On Open-drain with alt. drive strength
0b1101 x On On Open-drain with alt. drive strength
and filter
0b1110 x On On Open-drain with alt. drive strength
and pull-up
0b1111 x On On On Open-drain with alt. drive strength,
pull-up and filter
MODEn determines which mode the pin is in at a given time. Setting MODEn to 0b0000 disables the pin, reducing power consumption
to a minimum. When the output driver is disabled, the pin can be used as a connection for an analog module (e.g. ADC, LCD...). Input
is enabled by setting MODEn to any value other than 0b0000. The pull-up, pull-down and filter function can optionally be applied to the
input, see Figure 32.2 Tristated Output with Optional Pull-up or Pull-down on page 973.
The internal pull-up resistance, RPU, and pull-down resistance, RPD, are defined in the device datasheet. When the filter is enabled it
suppresses glitches with pulse widths as defined by the parameter tIOGLITCH in the device datasheet.
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VDD
DIN
Optional
pull-up
VSS
Optional
pull-down
Input enable
Analog connection
Glitch
suppression
filter
Filter enable
Figure 32.2. Tristated Output with Optional Pull-up or Pull-down
When MODEn=0b0100 or MODEn=0b0101, the pin operates in push-pull mode. In this mode, the pin is driven either high or low, de-
pendent on the value of GPIO_Px_DOUT. The push-pull configuration is shown in Figure 32.3 Push-Pull Configuration on page 973.
Input Enable
DOUT
DIN
Output Enable
Figure 32.3. Push-Pull Configuration
When MODEn is 0110 or 0111, the pin operates in open-source mode, the latter with a pull-down resistor. When driving a high value in
open-source mode, the pull-down is disconnected to save power.
For the remaining MODEn values, i.e. MODEn >= 1000, the pin operates in open-drain mode as shown in Figure 32.4 Open-Drain on
page 974. In open-drain mode, the pin can have an input filter, a pull-up, different driver strengths or any combination of these. When
driving a low value in open-drain mode, the pull-up is disconnected to save power.
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VSS
DOUT
VDD
DIN
Optional
pull-up
Glitch
suppression
filter
Filter enable
Figure 32.4. Open-Drain
When MODEn=0b0101 or 0b11xx, the output driver uses the drive strength specified in DRIVEMODE in GPIO_Px_CTRL. In all other
output modes, the drive strength is set to STANDARD.
32.3.1.1 Configuration Lock
GPIO_Px_MODEL, GPIO_Px_MODEH, GPIO_Px_CTRL, GPIO_Px_PINLOCKN, GPIO_EXTIPSELL, GPIO_EXTIPSELH, GPIO_IN-
SENSE and GPIO_ROUTE can be locked by writing any other value than 0xA534 to GPIO_LOCK. Writing the value 0xA534 to the
GPIOx_LOCK register unlocks the configuration registers.
In addition to configuration lock, GPIO_Px_MODEL, GPIO_Px_MODEH, GPIO_Px_DOUT, GPIO_Px_DOUTSET,
GPIO_Px_DOUTCLR, and GPIO_Px_DOUTTGL can be locked individually for each pin by clearing the corresponding bit in
GPIO_Px_PINLOCKN. Bits in the GPIO_Px_PINLOCKN register can only be cleared, they are set high again after reset.
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32.3.2 EM4 Wake-Up
It is possible to wake-up from EM4 through reset triggered from any of up to 6 selectable GPIO pins. For the wake-up logic to work
correctly, EM4 retention needs to be enabled before entering EM4, as described in 32.3.3 EM4 Retention The wake-up request can be
triggered through the pins by enabling the corresponding bit in the GPIO_EM4WUEN register. When EM4 wake-up is enabled for the
pin, the input filter is enabled during EM4. This is done to avoid false wake-up caused by glitches. In addition, the polarity of the EM4
wake-up request can be selected using the GPIO_EM4WUPOL register.
GPIO_EM4WUPOL
Wake-up Logic
GPIO_EM4WUEN
GPIO_EM4WUCAUSE
GPIO_CMD
Wake-up request
Figure 32.5. EM4 Wake-Up Logic
The pins used for EM4 wake-up must be configured as inputs using the GPIO_Px_MODEL/ GPIO_Px_MODEH register. Before going
down to EM4, it is important to clear the wake-up logic by setting the EM4WUCLR bitfield in the GPIO_CMD register, which clears the
complete wake-up logic, including the GPIO_EM4WUCAUSE register. When the chip comes out of reset, it is possible to determine
what caused the reset by reading the RMU_RSTCAUSE register. If an EM4 wake-up reset occurred, the EM4RST (indicating the chip
was in EM4) and the EM4WU (indicating the EM4 wake-up reset) bits should be set. It is possible to determine which pin caused the
reset by reading the GPIO_EM4WUCAUSE register. The mapping between pins and the bits in the GPIO_EM4WUEN, GPIO_EM4WU-
POL, and GPIO_EM4WUCAUSE registers are described in Table 32.1 EM4 WU Register Bits to Pin Mapping on page 975
Table 32.1. EM4 WU Register Bits to Pin Mapping
Wake-Up Registers Bits Pin
bit 0 A0
bit 1 A6
bit 2 C9
bit 3 F1
bit 4 F2
bit 5 E13
32.3.3 EM4 Retention
It is possible to enable retention of output enable, output value, pull enable and pull direction when in EM4. EM4 retention also makes it
possible to wake up from EM4 on pin reset as described in 32.3.2 EM4 Wake-Up EM4 retention can be enabled by setting the EM4RET
field in GPIO_CTRL register before going down in EM4.
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32.3.4 Alternate Functions
Alternate functions are connections to pins from Timers, USARTs etc. These modules contain route registers, where the pin connec-
tions are enabled. In addition, these registers contain a location bit field, which configures which pins the outputs of that module will be
connected to if they are enabled. If an alternate signal output is enabled for a pin and output is enabled for the pin, the alternate func-
tion’s output data and output enable signals override the data output and output enable signals from the GPIO. However, the pin config-
uration stays as set in GPIO_Px_MODEL, GPIO_Px_MODEH and GPIO_Px_DOUT registers. I.e. the pin configuration must be set to
output enable in GPIO for a peripheral to be able to use the pin as an output.
It is possible, but not recommended to select two or more peripherals as output on the same pin. These signals will then be OR'ed
together. However, TIMER CCx and CDTIx outputs, which are routed as alternate functions, have priority, and will never be OR'ed with
other alternate functions. The reader is referred to the pin map section of the device datasheet for more information on the possible
locations of each alternate function and any priority settings.
32.3.4.1 Serial Wire Debug Port Connection
The SW Debug Port is routed as an alternate function and the SWDIO and SWCLK pin connections are enabled by default with internal
pull-up and pull-down resistors, respectively. It is possible to disable these pin connections (and disable the pull resistors) by setting the
SWDIOPEN and SWCLKPEN bits in GPIO_ROUTE to 0.
When the debug pins are disabled, the device can no longer be accessed by a debugger. A reset will set the debug pins back to their
default state as enabled. If you do disable the debug pins, make sure you have at least a 3 second timeout at the start of your program
code before you disable the debug pins. This way the debugger will have time to halt the device after a reset before the pins are disa-
bled.
The Serial Wire Viewer Output pin (SWO) can be enabled by setting the SWOPEN bit in GPIO_ROUTE. This bit can also be routed to
alternate locations by configuring the LOCATION bitfield in GPIO_ROUTE.
32.3.4.2 ETM Trace Ports
There are five trace pins available on the device. One trace clock which can be enabled by setting the TCLKPEN bitfield in
GPIO_ROUTE. The four data pins can be enabled individually by setting TD0PEN, TD1PEN, TD2PEN, and TD3PEN respectively in
GPIO_ROUTE. It is possible to choose which pins the trace data will be exported to. The lowest trace bit will be routed to the first ena-
bled trace pin. For example, if the ETM data port size is 2 bits and TD0 and TD3 are enabled, will make bit 0 be routed to TD0 while bit
1 will be routed to TD3.
Both the TCLK and all the TD pins can also be routed to alternate locations by configuring the ETMLOCATION bitifeld in
GPIO_ROUTE.
32.3.4.3 Analog Connections
When using the GPIO pin for analog functionality, it is recommended to disable the digital output and set the MODEn in
GPIO_Px_MODEL/GPIO_Px_MODEH equal to 0b0000 to disable the input sense and pull resistors.
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32.3.5 Interrupt Generation
The GPIO can generate an interrupt from the input of any GPIO pin on a device. The interrupts have asynchronous sense capability,
enabling wake-up from energy modes as low as EM3, see Figure 32.6 Pin n Interrupt Generation on page 977.
IRQ_GPIO_EVEN/
IRQ_GPIO_ODD
PAn
EXTIRISE[n] IEN[n]EXTIPSELn[2:0]
PBn
PCn
PDn
PEn
IF[n]
set clear
IFS[n] IFC[n]
wakeup
PFn
EXTIFALL[n]
PRS
Odd/even inputs
Synch
Figure 32.6. Pin n Interrupt Generation
All pins with the same pin number (n) are grouped together to trigger one interrupt flag (EXT[n] in GPIO_IF). The EXTIPSELn[2:0] bits
in GPIO_EXTIPSELL or GPIO_EXTIPSELH select which port will trigger the interrupt flag. The GPIO_EXTIRISE[n] and GPIO_EXTI-
FALL[n] registers enables sensing of rising and falling edges. By setting the EXT[n] bit in GPIO_IEN, a high interrupt flag n, will trigger
one of two interrupt lines. The even interrupt line is triggered by any enabled even numbered interrupt flag, while the odd is triggered by
odd flags. The interrupt flags can be set and cleared by software by writing the GPIO_IFS and GPIO_IFC registers, see the following
example. Since the external interrupts are asynchronous, they are sensitive to noise. To increase noise tolerance, the MODEL and
MODEH fields in the GPIO_Px_MODEL and GPIO_Px_MODEH registers, respectively, should be set to include filtering for pins that
have external interrupts enabled.
GPIO Interrupt Example
Setting EXTIPSEL3 in GPIO_EXTIPSELL to 2 (Port C) and setting the GPIO_EXTIRISE[3] bit, the interrupt flag EXT[3] in GPIO_IF will
be triggered by a rising edge on pin 3 on PORT C. If EXT[3] in GPIO_IEN is set as well, a interrupt request will be sent on
IRQ_GPIO_ODD.
32.3.6 Output to PRS
All pins with the same pin number (n) are grouped together to form one PRS producer output, giving a total of 16 outputs to the PRS.
The port on which the output n should be taken is selected by the EXTIPSELn[3:0] bits in the GPIO_EXTIPSELL or the GPIO_EXTIP-
SELH registers.
32.3.7 Synchronization
To avoid metastability in synchronous logic connected to the pins, all inputs are synchronized with double flip-flops. The flip-flops for the
input data run on the HFCORECLK. Consequently, when a pin changes state, the change will have propagated to GPIO_Px_DIN after
2 positive HFCORECLK edges, or maximum 2 HFCORECLK cycles.
Synchronization (also running on the HFCORECLK) is also added for interrupt input. The input to the PRS generation is also synchron-
ized, but these flip-flops run on the HFPERCLK. To save power when the external interrupts or PRS generation is not used, the syn-
chronization flip-flops for these can be turned off by clearing the INTSENSE or PRSSENSE, respectively, in GPIO_INSENSE register.
Note: To use the GPIO, the GPIO clock must first be enabled in CMU_HFPERCLKEN0. Setting this bit enables the HFCORECLK and
the HFPERCLK for the GPIO. HFCORECLK is used for updating registers, while HFPERCLK is only used to synchronize PRS and
interrupts. The PRS and interrupt synchronization can also be disabled through GPIO_INSENSE, if these are not used.
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32.4 Register Map
The offset register address is relative to the registers base address.
Offset Name Type Description
0x000 GPIO_PA_CTRL RW Port Control Register
0x004 GPIO_PA_MODEL RW Port Pin Mode Low Register
0x008 GPIO_PA_MODEH RW Port Pin Mode High Register
0x00C GPIO_PA_DOUT RW Port Data Out Register
0x010 GPIO_PA_DOUTSET W1 Port Data Out Set Register
0x014 GPIO_PA_DOUTCLR W1 Port Data Out Clear Register
0x018 GPIO_PA_DOUTTGL W1 Port Data Out Toggle Register
0x01C GPIO_PA_DIN RPort Data In Register
0x020 GPIO_PA_PINLOCKN RW Port Unlocked Pins Register
... GPIO_Px_CTRL RW Port Control Register
... GPIO_Px_MODEL RW Port Pin Mode Low Register
... GPIO_Px_MODEH RW Port Pin Mode High Register
... GPIO_Px_DOUT RW Port Data Out Register
... GPIO_Px_DOUTSET W1 Port Data Out Set Register
... GPIO_Px_DOUTCLR W1 Port Data Out Clear Register
... GPIO_Px_DOUTTGL W1 Port Data Out Toggle Register
... GPIO_Px_DIN RPort Data In Register
... GPIO_Px_PINLOCKN RW Port Unlocked Pins Register
0x0B4 GPIO_PF_CTRL RW Port Control Register
0x0B8 GPIO_PF_MODEL RW Port Pin Mode Low Register
0x0BC GPIO_PF_MODEH RW Port Pin Mode High Register
0x0C0 GPIO_PF_DOUT RW Port Data Out Register
0x0C4 GPIO_PF_DOUTSET W1 Port Data Out Set Register
0x0C8 GPIO_PF_DOUTCLR W1 Port Data Out Clear Register
0x0CC GPIO_PF_DOUTTGL W1 Port Data Out Toggle Register
0x0D0 GPIO_PF_DIN RPort Data In Register
0x0D4 GPIO_PF_PINLOCKN RW Port Unlocked Pins Register
0x100 GPIO_EXTIPSELL RW External Interrupt Port Select Low Register
0x104 GPIO_EXTIPSELH RW External Interrupt Port Select High Register
0x108 GPIO_EXTIRISE RW External Interrupt Rising Edge Trigger Register
0x10C GPIO_EXTIFALL RW External Interrupt Falling Edge Trigger Register
0x110 GPIO_IEN RW Interrupt Enable Register
0x114 GPIO_IF RInterrupt Flag Register
0x118 GPIO_IFS W1 Interrupt Flag Set Register
0x11C GPIO_IFC (R)W1 Interrupt Flag Clear Register
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Offset Name Type Description
0x120 GPIO_ROUTE RW I/O Routing Register
0x124 GPIO_INSENSE RW Input Sense Register
0x128 GPIO_LOCK RW Configuration Lock Register
0x12C GPIO_CTRL RW GPIO Control Register
0x130 GPIO_CMD W1 GPIO Command Register
0x134 GPIO_EM4WUEN RW EM4 Wake-up Enable Register
0x138 GPIO_EM4WUPOL RW EM4 Wake-up Polarity Register
0x13C GPIO_EM4WUCAUSE REM4 Wake-up Cause Register
32.5 Register Description
32.5.1 GPIO_Px_CTRL - Port Control Register
Offset Bit Position
0x000
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
16
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
Reset
0x0
Access
RW
Name
DRIVEMODE
Bit Name Reset Access Description
31:2 Reserved To ensure compatibility with future devices, always write bits to 0. More information in 2.1 Conven-
tions.
1:0 DRIVEMODE 0x0 RW Drive Mode Select
Select drive mode for all pins on port configured with alternate drive strength.
Value Mode Description
0 STANDARD 6 mA drive current
1 LOWEST 0.1 mA drive current
2 HIGH 20 mA drive current
3 LOW 1 mA drive current
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32.5.2 GPIO_Px_MODEL - Port Pin Mode Low Register
Offset Bit Position
0x004
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
16
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
Reset
0x0
0x0
0x0
0x0
0x0
0x0
0x0
0x0
Access
RW
RW
RW
RW
RW
RW
RW
RW
Name
MODE7
MODE6
MODE5
MODE4
MODE3
MODE2
MODE1
MODE0
Bit Name Reset Access Description
31:28 MODE7 0x0 RW Pin 7 Mode
Configure mode for pin 7. Enumeration is equal to MODE0.
27:24 MODE6 0x0 RW Pin 6 Mode
Configure mode for pin 6. Enumeration is equal to MODE0.
23:20 MODE5 0x0 RW Pin 5 Mode
Configure mode for pin 5. Enumeration is equal to MODE0.
19:16 MODE4 0x0 RW Pin 4 Mode
Configure mode for pin 4. Enumeration is equal to MODE0.
15:12 MODE3 0x0 RW Pin 3 Mode
Configure mode for pin 3. Enumeration is equal to MODE0.
11:8 MODE2 0x0 RW Pin 2 Mode
Configure mode for pin 2. Enumeration is equal to MODE0.
7:4 MODE1 0x0 RW Pin 1 Mode
Configure mode for pin 1. Enumeration is equal to MODE0.
3:0 MODE0 0x0 RW Pin 0 Mode
Configure mode for pin 0.
Value Mode Description
0 DISABLED Input disabled. Pullup if DOUT is set.
1 INPUT Input enabled. Filter if DOUT is set
2 INPUTPULL Input enabled. DOUT determines pull direction
3 INPUTPULLFILTER Input enabled with filter. DOUT determines pull direction
4 PUSHPULL Push-pull output
5 PUSHPULLDRIVE Push-pull output with drive-strength set by DRIVEMODE
6 WIREDOR Wired-or output
7 WIREDORPULLDOWN Wired-or output with pull-down
8 WIREDAND Open-drain output
9 WIREDANDFILTER Open-drain output with filter
10 WIREDANDPULLUP Open-drain output with pullup
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Bit Name Reset Access Description
11 WIREDANDPULLUP-
FILTER
Open-drain output with filter and pullup
12 WIREDANDDRIVE Open-drain output with drive-strength set by DRIVEMODE
13 WIREDANDDRIVEFIL-
TER
Open-drain output with filter and drive-strength set by DRIVEMODE
14 WIREDANDDRIVE-
PULLUP
Open-drain output with pullup and drive-strength set by DRIVEMODE
15 WIREDANDDRIVEPUL-
LUPFILTER
Open-drain output with filter, pullup and drive-strength set by DRIVE-
MODE
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32.5.3 GPIO_Px_MODEH - Port Pin Mode High Register
Offset Bit Position
0x008
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
16
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
Reset
0x0
0x0
0x0
0x0
0x0
0x0
0x0
0x0
Access
RW
RW
RW
RW
RW
RW
RW
RW
Name
MODE15
MODE14
MODE13
MODE12
MODE11
MODE10
MODE9
MODE8
Bit Name Reset Access Description
31:28 MODE15 0x0 RW Pin 15 Mode
Configure mode for pin 15. Enumeration is equal to MODE8.
27:24 MODE14 0x0 RW Pin 14 Mode
Configure mode for pin 14. Enumeration is equal to MODE8.
23:20 MODE13 0x0 RW Pin 13 Mode
Configure mode for pin 13. Enumeration is equal to MODE8.
19:16 MODE12 0x0 RW Pin 12 Mode
Configure mode for pin 12. Enumeration is equal to MODE8.
15:12 MODE11 0x0 RW Pin 11 Mode
Configure mode for pin 11. Enumeration is equal to MODE8.
11:8 MODE10 0x0 RW Pin 10 Mode
Configure mode for pin 10. Enumeration is equal to MODE8.
7:4 MODE9 0x0 RW Pin 9 Mode
Configure mode for pin 9. Enumeration is equal to MODE8.
3:0 MODE8 0x0 RW Pin 8 Mode
Configure mode for pin 8.
Value Mode Description
0 DISABLED Input disabled. Pullup if DOUT is set.
1 INPUT Input enabled. Filter if DOUT is set
2 INPUTPULL Input enabled. DOUT determines pull direction
3 INPUTPULLFILTER Input enabled with filter. DOUT determines pull direction
4 PUSHPULL Push-pull output
5 PUSHPULLDRIVE Push-pull output with drive-strength set by DRIVEMODE
6 WIREDOR Wired-or output
7 WIREDORPULLDOWN Wired-or output with pull-down
8 WIREDAND Open-drain output
9 WIREDANDFILTER Open-drain output with filter
10 WIREDANDPULLUP Open-drain output with pullup
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Bit Name Reset Access Description
11 WIREDANDPULLUP-
FILTER
Open-drain output with filter and pullup
12 WIREDANDDRIVE Open-drain output with drive-strength set by DRIVEMODE
13 WIREDANDDRIVEFIL-
TER
Open-drain output with filter and drive-strength set by DRIVEMODE
14 WIREDANDDRIVE-
PULLUP
Open-drain output with pullup and drive-strength set by DRIVEMODE
15 WIREDANDDRIVEPUL-
LUPFILTER
Open-drain output with filter, pullup and drive-strength set by DRIVE-
MODE
32.5.4 GPIO_Px_DOUT - Port Data Out Register
Offset Bit Position
0x00C
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
16
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
Reset
0x0000
Access
RW
Name
DOUT
Bit Name Reset Access Description
31:16 Reserved To ensure compatibility with future devices, always write bits to 0. More information in 2.1 Conven-
tions.
15:0 DOUT 0x0000 RW Data Out
Data output on port.
32.5.5 GPIO_Px_DOUTSET - Port Data Out Set Register
Offset Bit Position
0x010
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
16
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
Reset
0x0000
Access
W1
Name
DOUTSET
Bit Name Reset Access Description
31:16 Reserved To ensure compatibility with future devices, always write bits to 0. More information in 2.1 Conven-
tions.
15:0 DOUTSET 0x0000 W1 Data Out Set
Write bits to 1 to set corresponding bits in GPIO_Px_DOUT. Bits written to 0 will have no effect.
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32.5.6 GPIO_Px_DOUTCLR - Port Data Out Clear Register
Offset Bit Position
0x014
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
16
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
Reset
0x0000
Access
W1
Name
DOUTCLR
Bit Name Reset Access Description
31:16 Reserved To ensure compatibility with future devices, always write bits to 0. More information in 2.1 Conven-
tions.
15:0 DOUTCLR 0x0000 W1 Data Out Clear
Write bits to 1 to clear corresponding bits in GPIO_Px_DOUT. Bits written to 0 will have no effect.
32.5.7 GPIO_Px_DOUTTGL - Port Data Out Toggle Register
Offset Bit Position
0x018
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
16
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
Reset
0x0000
Access
W1
Name
DOUTTGL
Bit Name Reset Access Description
31:16 Reserved To ensure compatibility with future devices, always write bits to 0. More information in 2.1 Conven-
tions.
15:0 DOUTTGL 0x0000 W1 Data Out Toggle
Write bits to 1 to toggle corresponding bits in GPIO_Px_DOUT. Bits written to 0 will have no effect.
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32.5.8 GPIO_Px_DIN - Port Data In Register
Offset Bit Position
0x01C
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
16
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
Reset
0x0000
Access
R
Name
DIN
Bit Name Reset Access Description
31:16 Reserved To ensure compatibility with future devices, always write bits to 0. More information in 2.1 Conven-
tions.
15:0 DIN 0x0000 R Data In
Port data input.
32.5.9 GPIO_Px_PINLOCKN - Port Unlocked Pins Register
Offset Bit Position
0x020
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
16
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
Reset
0xFFFF
Access
RW
Name
PINLOCKN
Bit Name Reset Access Description
31:16 Reserved To ensure compatibility with future devices, always write bits to 0. More information in 2.1 Conven-
tions.
15:0 PINLOCKN 0xFFFF RW Unlocked Pins
Shows unlocked pins in the port. To lock pin n, clear bit n. The pin is then locked until reset.
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32.5.10 GPIO_EXTIPSELL - External Interrupt Port Select Low Register
Offset Bit Position
0x100
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
16
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
Reset
0x0
0x0
0x0
0x0
0x0
0x0
0x0
0x0
Access
RW
RW
RW
RW
RW
RW
RW
RW
Name
EXTIPSEL7
EXTIPSEL6
EXTIPSEL5
EXTIPSEL4
EXTIPSEL3
EXTIPSEL2
EXTIPSEL1
EXTIPSEL0
Bit Name Reset Access Description
31 Reserved To ensure compatibility with future devices, always write bits to 0. More information in 2.1 Conven-
tions.
30:28 EXTIPSEL7 0x0 RW External Interrupt 7 Port Select
Select input port for external interrupt 7.
Value Mode Description
0 PORTA Port A pin 7 selected for external interrupt 7
1 PORTB Port B pin 7 selected for external interrupt 7
2 PORTC Port C pin 7 selected for external interrupt 7
3 PORTD Port D pin 7 selected for external interrupt 7
4 PORTE Port E pin 7 selected for external interrupt 7
5 PORTF Port F pin 7 selected for external interrupt 7
27 Reserved To ensure compatibility with future devices, always write bits to 0. More information in 2.1 Conven-
tions.
26:24 EXTIPSEL6 0x0 RW External Interrupt 6 Port Select
Select input port for external interrupt 6.
Value Mode Description
0 PORTA Port A pin 6 selected for external interrupt 6
1 PORTB Port B pin 6 selected for external interrupt 6
2 PORTC Port C pin 6 selected for external interrupt 6
3 PORTD Port D pin 6 selected for external interrupt 6
4 PORTE Port E pin 6 selected for external interrupt 6
5 PORTF Port F pin 6 selected for external interrupt 6
23 Reserved To ensure compatibility with future devices, always write bits to 0. More information in 2.1 Conven-
tions.
22:20 EXTIPSEL5 0x0 RW External Interrupt 5 Port Select
Select input port for external interrupt 5.
Value Mode Description
0 PORTA Port A pin 5 selected for external interrupt 5
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Bit Name Reset Access Description
1 PORTB Port B pin 5 selected for external interrupt 5
2 PORTC Port C pin 5 selected for external interrupt 5
3 PORTD Port D pin 5 selected for external interrupt 5
4 PORTE Port E pin 5 selected for external interrupt 5
5 PORTF Port F pin 5 selected for external interrupt 5
19 Reserved To ensure compatibility with future devices, always write bits to 0. More information in 2.1 Conven-
tions.
18:16 EXTIPSEL4 0x0 RW External Interrupt 4 Port Select
Select input port for external interrupt 4.
Value Mode Description
0 PORTA Port A pin 4 selected for external interrupt 4
1 PORTB Port B pin 4 selected for external interrupt 4
2 PORTC Port C pin 4 selected for external interrupt 4
3 PORTD Port D pin 4 selected for external interrupt 4
4 PORTE Port E pin 4 selected for external interrupt 4
5 PORTF Port F pin 4 selected for external interrupt 4
15 Reserved To ensure compatibility with future devices, always write bits to 0. More information in 2.1 Conven-
tions.
14:12 EXTIPSEL3 0x0 RW External Interrupt 3 Port Select
Select input port for external interrupt 3.
Value Mode Description
0 PORTA Port A pin 3 selected for external interrupt 3
1 PORTB Port B pin 3 selected for external interrupt 3
2 PORTC Port C pin 3 selected for external interrupt 3
3 PORTD Port D pin 3 selected for external interrupt 3
4 PORTE Port E pin 3 selected for external interrupt 3
5 PORTF Port F pin 3 selected for external interrupt 3
11 Reserved To ensure compatibility with future devices, always write bits to 0. More information in 2.1 Conven-
tions.
10:8 EXTIPSEL2 0x0 RW External Interrupt 2 Port Select
Select input port for external interrupt 2.
Value Mode Description
0 PORTA Port A pin 2 selected for external interrupt 2
1 PORTB Port B pin 2 selected for external interrupt 2
2 PORTC Port C pin 2 selected for external interrupt 2
3 PORTD Port D pin 2 selected for external interrupt 2
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Bit Name Reset Access Description
4 PORTE Port E pin 2 selected for external interrupt 2
5 PORTF Port F pin 2 selected for external interrupt 2
7 Reserved To ensure compatibility with future devices, always write bits to 0. More information in 2.1 Conven-
tions.
6:4 EXTIPSEL1 0x0 RW External Interrupt 1 Port Select
Select input port for external interrupt 1.
Value Mode Description
0 PORTA Port A pin 1 selected for external interrupt 1
1 PORTB Port B pin 1 selected for external interrupt 1
2 PORTC Port C pin 1 selected for external interrupt 1
3 PORTD Port D pin 1 selected for external interrupt 1
4 PORTE Port E pin 1 selected for external interrupt 1
5 PORTF Port F pin 1 selected for external interrupt 1
3 Reserved To ensure compatibility with future devices, always write bits to 0. More information in 2.1 Conven-
tions.
2:0 EXTIPSEL0 0x0 RW External Interrupt 0 Port Select
Select input port for external interrupt 0.
Value Mode Description
0 PORTA Port A pin 0 selected for external interrupt 0
1 PORTB Port B pin 0 selected for external interrupt 0
2 PORTC Port C pin 0 selected for external interrupt 0
3 PORTD Port D pin 0 selected for external interrupt 0
4 PORTE Port E pin 0 selected for external interrupt 0
5 PORTF Port F pin 0 selected for external interrupt 0
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32.5.11 GPIO_EXTIPSELH - External Interrupt Port Select High Register
Offset Bit Position
0x104
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
16
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
Reset
0x0
0x0
0x0
0x0
0x0
0x0
0x0
0x0
Access
RW
RW
RW
RW
RW
RW
RW
RW
Name
EXTIPSEL15
EXTIPSEL14
EXTIPSEL13
EXTIPSEL12
EXTIPSEL11
EXTIPSEL10
EXTIPSEL9
EXTIPSEL8
Bit Name Reset Access Description
31 Reserved To ensure compatibility with future devices, always write bits to 0. More information in 2.1 Conven-
tions.
30:28 EXTIPSEL15 0x0 RW External Interrupt 15 Port Select
Select input port for external interrupt 15.
Value Mode Description
0 PORTA Port A pin 15 selected for external interrupt 15
1 PORTB Port B pin 15 selected for external interrupt 15
2 PORTC Port C pin 15 selected for external interrupt 15
3 PORTD Port D pin 15 selected for external interrupt 15
4 PORTE Port E pin 15 selected for external interrupt 15
5 PORTF Port F pin 15 selected for external interrupt 15
27 Reserved To ensure compatibility with future devices, always write bits to 0. More information in 2.1 Conven-
tions.
26:24 EXTIPSEL14 0x0 RW External Interrupt 14 Port Select
Select input port for external interrupt 14.
Value Mode Description
0 PORTA Port A pin 14 selected for external interrupt 14
1 PORTB Port B pin 14 selected for external interrupt 14
2 PORTC Port C pin 14 selected for external interrupt 14
3 PORTD Port D pin 14 selected for external interrupt 14
4 PORTE Port E pin 14 selected for external interrupt 14
5 PORTF Port F pin 14 selected for external interrupt 14
23 Reserved To ensure compatibility with future devices, always write bits to 0. More information in 2.1 Conven-
tions.
22:20 EXTIPSEL13 0x0 RW External Interrupt 13 Port Select
Select input port for external interrupt 13.
Value Mode Description
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Bit Name Reset Access Description
0 PORTA Port A pin 13 selected for external interrupt 13
1 PORTB Port B pin 13 selected for external interrupt 13
2 PORTC Port C pin 13 selected for external interrupt 13
3 PORTD Port D pin 13 selected for external interrupt 13
4 PORTE Port E pin 13 selected for external interrupt 13
5 PORTF Port F pin 13 selected for external interrupt 13
19 Reserved To ensure compatibility with future devices, always write bits to 0. More information in 2.1 Conven-
tions.
18:16 EXTIPSEL12 0x0 RW External Interrupt 12 Port Select
Select input port for external interrupt 12.
Value Mode Description
0 PORTA Port A pin 12 selected for external interrupt 12
1 PORTB Port B pin 12 selected for external interrupt 12
2 PORTC Port C pin 12 selected for external interrupt 12
3 PORTD Port D pin 12 selected for external interrupt 12
4 PORTE Port E pin 12 selected for external interrupt 12
5 PORTF Port F pin 12 selected for external interrupt 12
15 Reserved To ensure compatibility with future devices, always write bits to 0. More information in 2.1 Conven-
tions.
14:12 EXTIPSEL11 0x0 RW External Interrupt 11 Port Select
Select input port for external interrupt 11.
Value Mode Description
0 PORTA Port A pin 11 selected for external interrupt 11
1 PORTB Port B pin 11 selected for external interrupt 11
2 PORTC Port C pin 11 selected for external interrupt 11
3 PORTD Port D pin 11 selected for external interrupt 11
4 PORTE Port E pin 11 selected for external interrupt 11
5 PORTF Port F pin 11 selected for external interrupt 11
11 Reserved To ensure compatibility with future devices, always write bits to 0. More information in 2.1 Conven-
tions.
10:8 EXTIPSEL10 0x0 RW External Interrupt 10 Port Select
Select input port for external interrupt 10.
Value Mode Description
0 PORTA Port A pin 10 selected for external interrupt 10
1 PORTB Port B pin 10 selected for external interrupt 10
2 PORTC Port C pin 10 selected for external interrupt 10
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Bit Name Reset Access Description
3 PORTD Port D pin 10 selected for external interrupt 10
4 PORTE Port E pin 10 selected for external interrupt 10
5 PORTF Port F pin 10 selected for external interrupt 10
7 Reserved To ensure compatibility with future devices, always write bits to 0. More information in 2.1 Conven-
tions.
6:4 EXTIPSEL9 0x0 RW External Interrupt 9 Port Select
Select input port for external interrupt 9.
Value Mode Description
0 PORTA Port A pin 9 selected for external interrupt 9
1 PORTB Port B pin 9 selected for external interrupt 9
2 PORTC Port C pin 9 selected for external interrupt 9
3 PORTD Port D pin 9 selected for external interrupt 9
4 PORTE Port E pin 9 selected for external interrupt 9
5 PORTF Port F pin 9 selected for external interrupt 9
3 Reserved To ensure compatibility with future devices, always write bits to 0. More information in 2.1 Conven-
tions.
2:0 EXTIPSEL8 0x0 RW External Interrupt 8 Port Select
Select input port for external interrupt 8.
Value Mode Description
0 PORTA Port A pin 8 selected for external interrupt 8
1 PORTB Port B pin 8 selected for external interrupt 8
2 PORTC Port C pin 8 selected for external interrupt 8
3 PORTD Port D pin 8 selected for external interrupt 8
4 PORTE Port E pin 8 selected for external interrupt 8
5 PORTF Port F pin 8 selected for external interrupt 8
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32.5.12 GPIO_EXTIRISE - External Interrupt Rising Edge Trigger Register
Offset Bit Position
0x108
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
16
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
Reset
0x0000
Access
RW
Name
EXTIRISE
Bit Name Reset Access Description
31:16 Reserved To ensure compatibility with future devices, always write bits to 0. More information in 2.1 Conven-
tions.
15:0 EXTIRISE 0x0000 RW External Interrupt n Rising Edge Trigger Enable
Set bit n to enable triggering of external interrupt n on rising edge.
Value Description
EXTIRISE[n] = 0 Rising edge trigger disa-
bled
EXTIRISE[n] = 1 Rising edge trigger ena-
bled
32.5.13 GPIO_EXTIFALL - External Interrupt Falling Edge Trigger Register
Offset Bit Position
0x10C
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
16
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
Reset
0x0000
Access
RW
Name
EXTIFALL
Bit Name Reset Access Description
31:16 Reserved To ensure compatibility with future devices, always write bits to 0. More information in 2.1 Conven-
tions.
15:0 EXTIFALL 0x0000 RW External Interrupt n Falling Edge Trigger Enable
Set bit n to enable triggering of external interrupt n on falling edge.
Value Description
EXTIFALL[n] = 0 Falling edge trigger dis-
abled
EXTIFALL[n] = 1 Falling edge trigger ena-
bled
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32.5.14 GPIO_IEN - Interrupt Enable Register
Offset Bit Position
0x110
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
16
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
Reset
0x0000
Access
RW
Name
EXT
Bit Name Reset Access Description
31:16 Reserved To ensure compatibility with future devices, always write bits to 0. More information in 2.1 Conven-
tions.
15:0 EXT 0x0000 RW External Interrupt n Enable
Set bit n to enable external interrupt from pin n.
Value Description
EXT[n] = 0 Pin n external interrupt
disabled
EXT[n] = 1 Pin n external interrupt
enabled
32.5.15 GPIO_IF - Interrupt Flag Register
Offset Bit Position
0x114
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
16
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
Reset
0x0000
Access
R
Name
EXT
Bit Name Reset Access Description
31:16 Reserved To ensure compatibility with future devices, always write bits to 0. More information in 2.1 Conven-
tions.
15:0 EXT 0x0000 R External Interrupt Flag n
Pin n external interrupt flag.
Value Description
EXT[n] = 0 Pin n external interrupt
flag cleared
EXT[n] = 1 Pin n external interrupt
flag set
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32.5.16 GPIO_IFS - Interrupt Flag Set Register
Offset Bit Position
0x118
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
16
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
Reset
0x0000
Access
W1
Name
EXT
Bit Name Reset Access Description
31:16 Reserved To ensure compatibility with future devices, always write bits to 0. More information in 2.1 Conven-
tions.
15:0 EXT 0x0000 W1 External Interrupt Flag n Set
Write bit n to 1 to set interrupt flag n.
Value Description
EXT[n] = 0 Pin n external interrupt
flag unchanged
EXT[n] = 1 Pin n external interrupt
flag set
32.5.17 GPIO_IFC - Interrupt Flag Clear Register
Offset Bit Position
0x11C
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
16
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
Reset
0x0000
Access
(R)W1
Name
EXT
Bit Name Reset Access Description
31:16 Reserved To ensure compatibility with future devices, always write bits to 0. More information in 2.1 Conven-
tions.
15:0 EXT 0x0000 (R)W1 External Interrupt Flag Clear
Write bit n to 1 to clear external interrupt flag n.
Value Description
EXT[n] = 0 Pin n external interrupt
flag unchanged
EXT[n] = 1 Pin n external interrupt
flag cleared
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32.5.18 GPIO_ROUTE - I/O Routing Register
Offset Bit Position
0x120
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
16
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
Reset
0x0
0
0
0
0
0
0x0
0
1
1
Access
RW
RW
RW
RW
RW
RW
RW
RW
RW
RW
Name
ETMLOCATION
TD3PEN
TD2PEN
TD1PEN
TD0PEN
TCLKPEN
SWLOCATION
SWOPEN
SWDIOPEN
SWCLKPEN
Bit Name Reset Access Description
31:26 Reserved To ensure compatibility with future devices, always write bits to 0. More information in 2.1 Conven-
tions.
25:24 ETMLOCATION 0x0 RW I/O Location
Decides the location of the TCLK and TD pins.
Value Mode Description
0 LOC0 Location 0
1 LOC1 Location 1
2 LOC2 Location 2
3 LOC3 Location 3
23:17 Reserved To ensure compatibility with future devices, always write bits to 0. More information in 2.1 Conven-
tions.
16 TD3PEN 0 RW ETM Trace Data Pin Enable
Enable ETM Trace Data Output 3 connection to pin.
15 TD2PEN 0 RW ETM Trace Data Pin Enable
Enable ETM Trace Data Output 2 connection to pin.
14 TD1PEN 0 RW ETM Trace Data Pin Enable
Enable ETM Trace Data Output 1 connection to pin.
13 TD0PEN 0 RW ETM Trace Data Pin Enable
Enable ETM Trace Data Output 0 connection to pin.
12 TCLKPEN 0 RW ETM Trace Clock Pin Enable
Enable ETM Trace Clock Output connection to pin.
11:10 Reserved To ensure compatibility with future devices, always write bits to 0. More information in 2.1 Conven-
tions.
9:8 SWLOCATION 0x0 RW I/O Location
Decides the location of the SW pins.
Value Mode Description
0 LOC0 Location 0
1 LOC1 Location 1
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Bit Name Reset Access Description
2 LOC2 Location 2
3 LOC3 Location 3
7:3 Reserved To ensure compatibility with future devices, always write bits to 0. More information in 2.1 Conven-
tions.
2 SWOPEN 0 RW Serial Wire Viewer Output Pin Enable
Enable Serial Wire Viewer Output connection to pin.
1 SWDIOPEN 1 RW Serial Wire Data Pin Enable
Enable Serial Wire Data connection to pin. WARNING: When this pin is disabled, the device can no longer be accessed by
a debugger. A reset will set the pin back to a default state as enabled. If you disable this pin, make sure you have at least a
3 second timeout at the start of you program code before you disable the pin. This way, the debugger will have time to halt
the device after a reset before the pin is disabled.
0 SWCLKPEN 1 RW Serial Wire Clock Pin Enable
Enable Serial Wire Clock connection to pin. WARNING: When this pin is disabled, the device can no longer be accessed by
a debugger. A reset will set the pin back to a default state as enabled. If you disable this pin, make sure you have at least a
3 second timeout at the start of you program code before you disable the pin. This way, the debugger will have time to halt
the device after a reset before the pin is disabled.
32.5.19 GPIO_INSENSE - Input Sense Register
Offset Bit Position
0x124
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
16
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
Reset
1
1
Access
RW
RW
Name
PRS
INT
Bit Name Reset Access Description
31:2 Reserved To ensure compatibility with future devices, always write bits to 0. More information in 2.1 Conven-
tions.
1 PRS 1 RW PRS Sense Enable
Set this bit to enable input sensing for PRS.
0 INT 1 RW Interrupt Sense Enable
Set this bit to enable input sensing for interrupts.
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32.5.20 GPIO_LOCK - Configuration Lock Register
Offset Bit Position
0x128
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
16
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
Reset
0x0000
Access
RW
Name
LOCKKEY
Bit Name Reset Access Description
31:16 Reserved To ensure compatibility with future devices, always write bits to 0. More information in 2.1 Conven-
tions.
15:0 LOCKKEY 0x0000 RW Configuration Lock Key
Write any other value than the unlock code to lock MODEL, MODEH, CTRL, PINLOCKN, EPISELL, EIPSELH, INSENSE
and SWDPROUTE from editing. Write the unlock code to unlock. When reading the register, bit 0 is set when the lock is
enabled.
Mode Value Description
Read Operation
UNLOCKED 0 GPIO registers are unlocked
LOCKED 1 GPIO registers are locked
Write Operation
LOCK 0 Lock GPIO registers
UNLOCK 0xA534 Unlock GPIO registers
32.5.21 GPIO_CTRL - GPIO Control Register
Offset Bit Position
0x12C
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
16
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
Reset
0
Access
RW
Name
EM4RET
Bit Name Reset Access Description
31:1 Reserved To ensure compatibility with future devices, always write bits to 0. More information in 2.1 Conven-
tions.
0 EM4RET 0 RW Enable EM4 retention
Set to enable EM4 retention of output enable, output value and pull enable.
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32.5.22 GPIO_CMD - GPIO Command Register
Offset Bit Position
0x130
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
16
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
Reset
0
Access
W1
Name
EM4WUCLR
Bit Name Reset Access Description
31:1 Reserved To ensure compatibility with future devices, always write bits to 0. More information in 2.1 Conven-
tions.
0 EM4WUCLR 0 W1 EM4 Wake-up clear
Write 1 to clear all wake-up requests.
32.5.23 GPIO_EM4WUEN - EM4 Wake-up Enable Register
Offset Bit Position
0x134
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
16
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
Reset
0x00
Access
RW
Name
EM4WUEN
Bit Name Reset Access Description
31:6 Reserved To ensure compatibility with future devices, always write bits to 0. More information in 2.1 Conven-
tions.
5:0 EM4WUEN 0x00 RW EM4 Wake-up enable
Write 1 to enable wake-up request, write 0 to disable wake-up request.
Value Mode Description
0x01 A0 Enable em4 wakeup on pin A0
0x02 A6 Enable em4 wakeup on pin A6
0x04 C9 Enable em4 wakeup on pin C9
0x08 F1 Enable em4 wakeup on pin F1
0x10 F2 Enable em4 wakeup on pin F2
0x20 E13 Enable em4 wakeup on pin E13
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32.5.24 GPIO_EM4WUPOL - EM4 Wake-up Polarity Register
Offset Bit Position
0x138
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
16
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
Reset
0x00
Access
RW
Name
EM4WUPOL
Bit Name Reset Access Description
31:6 Reserved To ensure compatibility with future devices, always write bits to 0. More information in 2.1 Conven-
tions.
5:0 EM4WUPOL 0x00 RW EM4 Wake-up Polarity
Write bit n to 1 for high wake-up request. Write bit n to 0 for low wake-up request
Value Mode Description
0x01 A0 Determines polarity on pin A0
0x02 A6 Determines polarity on pin A6
0x04 C9 Determines polarity on pin C9
0x08 F1 Determines polarity on pin F1
0x10 F2 Determines polarity on pin F2
0x20 E13 Determines polarity on pin E13
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32.5.25 GPIO_EM4WUCAUSE - EM4 Wake-up Cause Register
Offset Bit Position
0x13C
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
16
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
Reset
0x00
Access
R
Name
EM4WUCAUSE
Bit Name Reset Access Description
31:6 Reserved To ensure compatibility with future devices, always write bits to 0. More information in 2.1 Conven-
tions.
5:0 EM4WUCAUSE 0x00 R EM4 wake-up cause
Bit n indicates which pin the wake-up request occurred.
Value Mode Description
0x01 A0 This bit indicates an em4 wake-up request occurred on pin A0
0x02 A6 This bit indicates an em4 wake-up request occurred on pin A6
0x04 C9 This bit indicates an em4 wake-up request occurred on pin C9
0x08 F1 This bit indicates an em4 wake-up request occurred on pin F1
0x10 F2 This bit indicates an em4 wake-up request occurred on pin F2
0x20 E13 This bit indicates an em4 wake-up request occurred on pin E13
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33. LCD - Liquid Crystal Display Driver
43210
LCD
Driver
Quick Facts
What?
The LCD driver can drive up to 8x36 segmented
LCD directly. The LCD driver consumes less than
900 nA in EM2. The animation feature makes it pos-
sible to have active animations without CPU inter-
vention.
Why?
Segmented LCD displays are common way to dis-
play information. The extreme low-power LCD driver
enables a lot of applications to utilize an LCD display
even in energy critical systems.
How?
The low frequency clock signal, low-power wave-
form, animation and blink capabilities enable the
LCD driver to run autonomously in EM2 for long pe-
riods. Adding the flexible frame rate setting, contrast
control, and different multiplexing modes make the
EFM32WG the optimal choice for battery-driven sys-
tems with LCD panels.
33.1 Introduction
The LCD driver is capable of driving a segmented LCD display combination of: 1x40, 2x40, 3x40, 4x40, 6x38 or 8x36 segments. A
voltage boost function enables it to provide the LCD display with higher voltage than the supply voltage for the device. In addition, an
animation feature can run custom animations on the LCD display without any CPU intervention. The LCD driver can also remain active
even in Energy Mode 2 and provides a Frame Counter interrupt that can wake-up the device on a regular basis for updating data.
33.2 Features
• Up to 8x36 segments
• Configurable multiplexing (1, 2, 3, 4, 6, 8)
• LCD supports the following COM/SEG combinations
• 1x40, 2x40, 3x40, 4x40, 6x38, 8x36
• Configurable bias/voltage levels settings
• Configurable clock source prescaler
• Configurable Frame rate
• Segment lines can be enabled or disabled individually
• Blink capabilities
• Integrated animation functionality
• Available on SEG0-SEG7 or SEG8-SEG15
• Voltage boost capabilities
• Possible to run on external power
• Programmable contrast
• Frame Counter
• LCD frame interrupt
• Direct segment control
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33.3 Functional Description
An overview of the LCD module is shown in the following figure. In its simplest form, an LCD driver would apply a voltage above a
certain threshold voltage in order to darken a segment and a voltage below threshold to make a segment clear. However, the LCD
display segment will degrade if the applied voltage has a DC-component. To avoid this, the applied waveforms are arranged such that
the differential voltage seen by each segment has an average value of zero, and such that the RMS voltage (or differential sum of the
two waveforms for fast response LCDs) is below the segment threshold voltage if the segment shall be transparent, and above the
segment threshold voltage when the segment shall be dark.
The waveforms are multiplexed between eight (1-8) different common lines and 20-36 segment lines to support up to 288 different LCD
segments. The common lines and segment lines can be enabled or disabled individually to prevent the LCD driver from occupying more
I/O resources than required.
4x
32x SEG
4x SEG/COM
LCD
voltage
generator
VINT
VEXT
VBOOST
VLC1
VLC0
VLC1
VLC0
Disable
SEG out
Disable
COM out
LCD_SEGx
LCD_COMx
VLCDSEL
LCD control and
status
LCD segment
data register
LCD animation
registers
LCD
sequence
generator
Contrast and bias setting
Mux and framerate setting
Display data
Special
effects
LCD_BEXT
Data bus
LFACLKLCD
LCD_BCAP_P
LCD_BCAP_N
VLC2
VLC4
VLC3
VLC2
VLC3
VLC4
Figure 33.1. LCD Block Diagram
For simplicity, only one segment pin and one common terminal is shown in the figure.
33.3.1 LCD Driver Enable
Setting the EN bit in LCD_CTRL enables the LCD driver. The MUX bit-field in LCD_DISPCTRL determines which COM lines are driven
by the LCD driver. By default, LCD_COM0 is driven whenever the LCD driver is enabled.
The LCD_SEGEN register determines which segment lines are enabled. Segment lines can be enabled in groups of 4 and disabled in
groups of 4 or individually disabled. To enable output on segment lines 0-7 for instance, the two lowest segment groups, set the two
lowest bits in LCD_SEGEN. Each LCD segment pin can also be individually disabled by setting the pin to any other state than DISA-
BLED in the GPIO pin configuration.
Each LCD segment pin can also be individually disabled by setting the pin to any other state than DISABLED in the GPIO pin configura-
tion.
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33.3.2 Multiplexing, Bias, and Wave Settings
The LCD driver supports different multiplexing and bias settings, and these can be set individually in the MUX and BIAS bits in
LCD_DISPCTRL respectively, see the following two tables.
Note: If the MUX and BIAS settings in LCD_DISPCTRL are changed while the LCD driver is enabled, the output waveform is unpredict-
able and may lead to a DC-component for one LCD frame.
The MUX setting determines the number of LCD COM lines that are enabled. When using octaplex or sextaplex multiplexing, the addi-
tional COM lines used (COM4-COM7) are actually located on the SEG (SEG20-SEG23) lines. When static multiplexing is selected,
LCD output is enabled on LCD_COM0, when duplex multiplexing is used, LCD_COM0-LCD_COM1 are used, when triplex multiplexing
is selected, LCD_COM0-LCD_COM2 are used, when quadruplex multiplexing is selected, LCD_COM0- LCD_COM3 are used, when
sextaplex multiplexing is selected, LCD_COM0-LCD_COM3 together with SEG20-SEG21 as LCD_COM4-LCD_COM5 are used, mak-
ing 38 segments available, located in SEG0- SEG19, and SEG22-SEG39. Finally when octaplex multiplexing is selected, LCD_COM0-
LCD_COM3 together with SEG20-SEG23 as LCD_COM4-LCD_COM7 are used, making the 36 segments available, located in SEG0-
SEG19, and SEG24-SEG39.
See 33.3.3 Waveform Examples for waveforms for the different bias and multiplexing settings.
The waveforms generated by the LCD controller can be generated in two different versions, regular and low-power. The low power
mode waveforms have a lower switching frequency than the regular waveforms, and thus consume less power. The WAVE bit in
LCD_DISPCTRL decides which waveforms to generate. An example of a low-power waveform is shown in Figure 33.2 LCD Low-power
Waveform for LCD_COM0 in Quadruples Multiplex Mode, 1/3 Bias on page 1004, and an example of a regular waveform is shown in
Figure 33.3 LCD Normal Waveform for LCD_COM0 in Quadruples Multiplex Mode, 1/3 Bias on page 1004.
Table 33.1. LCD Mux Settings
MUXE MUX Mode Multiplexing
0 00 Static Static (segments can be multiplexed with LCD_COM[0])
0 01 Duplex Duplex (segments can be multiplexed with LCD_COM[1:0])
0 10 Triplex Triplex (segments can be multiplexed with LCD_COM[2:0])
0 11 Quadruplex Quadruplex (segments can be multiplexed with LCD_COM[3:0])
1 01 Sextaplex Sextaplex (segments can be multiplexed with LCD_COM[3:0] and
SEG[21:20])
1 11 Octaplex Octaplex (segments can be multiplexed with LCD_COM[3:0]) and
SEG[23:20]
Table 33.2. LCD BIAS Settings
BIAS Mode Bias setting
00 Static Static (2 levels)
01 Half Bias 1/2 Bias (3 levels)
10 Third Bias 1/3 Bias (4 levels)
11 Fourth Bias 1/4 Bias (5 levels)
Table 33.3. LCD Wave Settings
WAVE Mode Wave mode
0 LowPower Low power optimized waveform output
1 Normal Regular waveform output
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VLC0 (VLCD)
VLC1 (2/3VLCD)
VLC3 (VSS)
VLC2 (1/3VLCD)
Frame Start Frame End
Figure 33.2. LCD Low-power Waveform for LCD_COM0 in Quadruples Multiplex Mode, 1/3 Bias
VLC0 (VLCD)
VLC1 (2/3VLCD)
VLC3 (VSS)
VLC2 (1/3VLCD)
Frame Start Frame End
Figure 33.3. LCD Normal Waveform for LCD_COM0 in Quadruples Multiplex Mode, 1/3 Bias
33.3.3 Waveform Examples
The numbers on the illustration's y-axes in the following sections only indicate different voltage levels. All examples are shown with low-
power waveforms.
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33.3.3.1 Waveforms with Static Bias and Multiplexing
• With static bias and multiplexing, each segment line can be connected to LCD_COM0. When the segment line has the same wave-
form as LCD_COM0, the LCD panel pixel is turned off, while when the segment line has the opposite waveform, the LCD panel pixel
is turned on.
• DC voltage = 0 (over one frame)
• VRMS (on) = VLCD_OUT
• VRMS (off) = 0 (VSS)
Frame Start Frame End
VLC0 (VLCD)
VLC3 (VSS)
Figure 33.4. LCD Static Bias and Multiplexing - LCD_COM0
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33.3.3.2 Waveforms with 1/2 Bias and Duplex Multiplexing
In this mode, each frame is divided into 4 periods. LCD_COM[1:0] lines can be multiplexed with all segment lines. Figures show 1/2
bias and duplex multiplexing (waveforms show two frames)
VLC0 (VLCD)
VLC1 (1/2VLCD)
VLC3 (VSS)
Frame Start Frame End
Figure 33.5. LCD 1/2 Bias and Duplex Multiplexing - LCD_COM0
VLC0 (VLCD)
VLC1 (1/2VLCD)
VLC3 (VSS)
Frame Start Frame End
Figure 33.6. LCD 1/2 Bias and Duplex Multiplexing - LCD_COM1
1/2 bias and duplex multiplexing - LCD_SEG0
The LCD_SEG0 waveform on the left is just an example to illustrate how different segment waveforms can be multiplexed with the
LCD_COM lines in order to turn on and off LCD pixels. As illustrated in the figures below, this waveform will turn ON pixels connected
to LCD_COM0, while pixels connected to LCD_COM1 will be turned OFF.
VLC0 (VLCD)
VLC1 (1/2VLCD)
VLC3 (VSS)
Frame Start Frame End
Figure 33.7. LCD 1/2 Bias and Duplex Multiplexing - LCD_SEG0
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com1
com0
seg0
Figure 33.8. LCD 1/2 Bias and Duplex Multiplexing - LCD_SEG0 Connection
1/2 bias and duplex multiplexing - LCD_SEG0-LCD_COM0
• DC voltage = 0 (over one frame)
• VRMS = 0.79 × VLCD_OUT
• The LCD display pixel that is connected to LCD_SEG0 and LCD_COM0 will be ON with this waveform.
VLC0 (VLCD)
VLC3 (VSS)
-VLC0 (VLCD)
Frame Start Frame End
VLC1 (1/2VLCD)
-VLC1 (1/2VLCD)
Figure 33.9. LCD 1/2 Bias and Duplex Multiplexing - LCD_SEG0-LCD_COM0
1/2 bias and duplex multiplexing - LCD_SEG0-LCD_COM1
• DC voltage = 0 (over one frame)
• VRMS = 0.35 × VLCD_OUT
• The LCD display pixel that is connected to LCD_SEG0 and LCD_COM0 will be OFF with this waveform
VLC0 (VLCD)
VLC3 (VSS)
-VLC0 (VLCD)
Frame Start Frame End
VLC1 (1/2VLCD)
-VLC1 (1/2VLCD)
Figure 33.10. LCD 1/2 Bias and Duplex Multiplexing - LCD_SEG0-LCD_COM1
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33.3.3.3 Waveforms with 1/3 Bias and Duplex Multiplexing
In this mode, each frame is divided into 4 periods. LCD_COM[1:0] lines can be multiplexed with all segment lines. Figures show 1/3
bias and duplex multiplexing (waveforms show two frames).
VLC0 (VLCD)
VLC1 (2/3VLCD)
VLC3 (VSS)
VLC2 (1/3VLCD)
Frame Start Frame End
Figure 33.11. LCD 1/3 Bias and Duplex Multiplexing - LCD_COM0
VLC0 (VLCD)
VLC3 (VSS)
Frame Start Frame End
VLC1 (2/3VLCD)
VLC2 (1/3VLCD)
Figure 33.12. LCD 1/3 Bias and Duplex Multiplexing - LCD_COM1
1/3 bias and duplex multiplexing - LCD_SEG0
The LCD_SEG0 waveform on the left is just an example to illustrate how different segment waveforms can be multiplexed with the
COM lines in order to turn on and off LCD pixels. As illustrated in the figures below, this waveform will turn ON pixels connected to
LCD_COM0, while pixels connected to LCD_COM1 will be turned OFF.
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VLC0 (VLCD)
VLC3 (VSS)
Frame Start Frame End
VLC1 (2/3VLCD)
VLC2 (1/3VLCD)
Figure 33.13. LCD 1/3 Bias and Duplex Multiplexing - LCD_SEG0
com1
com0
seg0
Figure 33.14. LCD 1/3 Bias and Duplex Multiplexing - LCD_SEG0 Connection
1/3 bias and duplex multiplexing - LCD_SEG0-LCD_COM0
• DC voltage = 0 (over one frame)
• VRMS = 0.75 × VLCD_OUT
• The LCD display pixel that is connected to LCD_SEG0 and LCD_COM0 will be ON with this waveform
VLC3 (VSS)
VLC0 (VLCD)
VLC1 (2/3VLCD)
VLC2 (1/3VLCD)
-VLC0 (VLCD)
-VLC1 (2/3VLCD)
-VLC2 (1/3VLCD)
Frame Start Frame End
Figure 33.15. LCD 1/3 Bias and Duplex Multiplexing - LCD_SEG0-LCD_COM0
1/3 bias and duplex multiplexing - LCD_SEG0-LCD_COM0
• DC voltage = 0 (over one frame)
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• VRMS = 0.33 × VLCD_OUT
• The LCD display pixel that is connected to LCD_SEG0 and LCD_COM1 will be OFF with this waveform
VLC3 (VSS)
VLC0 (VLCD)
VLC1 (2/3VLCD)
VLC2 (1/3VLCD)
-VLC0 (VLCD)
-VLC1 (2/3VLCD)
-VLC2 (1/3VLCD)
Frame Start Frame End
Figure 33.16. LCD 1/3 Bias and Duplex Multiplexing - LCD_SEG0-LCD_COM1
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33.3.3.4 Waveforms with 1/2 Bias and Triplex Multiplexing
In this mode, each frame is divided into 6 periods. LCD_COM[2:0] lines can be multiplexed with all segment lines. Figures show 1/2
bias and triplex multiplexing (waveforms show two frames).
VLC0 (VLCD)
VLC1 (1/2VLCD)
VLC3 (VSS)
Frame Start Frame End
Figure 33.17. LCD 1/2 Bias and Triplex Multiplexing - LCD_COM0
VLC0 (VLCD)
VLC1 (1/2VLCD)
VLC3 (VSS)
Frame Start Frame End
Figure 33.18. CD 1/2 Bias and Triplex Multiplexing - LCD_COM1
VLC0 (VLCD)
VLC1 (1/2VLCD)
VLC3 (VSS)
Frame Start Frame End
Figure 33.19. LCD 1/2 Bias and Triplex Multiplexing - LCD_COM2
1/2 bias and triplex multiplexing - LCD_SEG0
The LCD_SEG0 waveform on the left is just an example to illustrate how different segment waveforms can be multiplexed with the
COM lines in order to turn on and off LCD pixels. As illustrated in the figures below, this waveform will turn ON pixels connected to
LCD_COM1, while pixels connected to LCD_COM0 and LCD_COM2 will be turned OFF.
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VLC0 (VLCD)
VLC1 (1/2VLCD)
VLC3 (VSS)
Frame Start Frame End
Figure 33.20. LCD 1/2 Bias and Triplex Multiplexing - LCD_SEG0
com1
com2
com0
seg0
Figure 33.21. LCD 1/2 Bias and Triplex Multiplexing - LCD_SEG0 Connection
1/2 bias and triplex multiplexing - LCD_SEG0-LCD_COM0
• DC voltage = 0 (over one frame)
• VRMS = 0.4 × VLCD_OUT
• The LCD display pixel that is connected to LCD_SEG0 and LCD_COM0 will be OFF with this waveform
VLC0 (VLCD)
VLC3 (VSS)
-VLC0 (VLCD)
VLC1 (1/2VLCD)
-VLC1 (1/2VLCD)
Frame Start Frame End
Figure 33.22. LCD 1/2 Bias and Triplex Multiplexing - LCD_SEG0-LCD_COM0
1/2 bias and triplex multiplexing - LCD_SEG0-LCD_COM1
• DC voltage = 0 (over one frame)
• VRMS = 0.7 VLCD_OUT
• The LCD display pixel that is connected to LCD_SEG0 and LCD_COM1 will be ON with this waveform
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VLC0 (VLCD)
VLC3 (VSS)
-VLC0 (VLCD)
VLC1 (1/2VLCD)
-VLC1 (1/2VLCD)
Frame Start Frame End
Figure 33.23. LCD 1/2 Bias and Triplex Multiplexing - LCD_SEG0-LCD_COM1
1/2 bias and triplex multiplexing - LCD_SEG0-LCD_COM2
• DC voltage = 0 (over one frame)
• VRMS = 0.4 × VLCD_OUT
• The LCD display pixel that is connected to LCD_SEG0 and LCD_COM2 will be OFF with this waveform
VLC0 (VLCD)
VLC3 (VSS)
-VLC0 (VLCD)
VLC1 (1/2VLCD)
-VLC1 (1/2VLCD)
Frame Start Frame End
Figure 33.24. LCD 1/2 Bias and Triplex Multiplexing - LCD_SEG0-LCD_COM2
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33.3.3.5 Waveforms with 1/3 Bias and Triplex Multiplexing
In this mode, each frame is divided into 6 periods. LCD_COM[2:0] lines can be multiplexed with all segment lines. Figures show 1/3
bias and triplex multiplexing (waveforms show two frames).
VLC0 (VLCD)
VLC3 (VSS)
VLC1 (2/3VLCD)
VLC2 (1/3VLCD)
Frame Start Frame End
Figure 33.25. LCD 1/3 Bias and Triplex Multiplexing - LCD_COM0
VLC0 (VLCD)
VLC3 (VSS)
VLC1 (2/3VLCD)
VLC2 (1/3VLCD)
Frame Start Frame End
Figure 33.26. LCD 1/3 Bias and Triplex Multiplexing - LCD_COM1
VLC0 (VLCD)
VLC3 (VSS)
VLC1 (2/3VLCD)
VLC2 (1/3VLCD)
Frame Start Frame End
Figure 33.27. LCD 1/3 Bias and Triplex Multiplexing - LCD_COM2
1/3 bias and triplex multiplexing - LCD_SEG0
The LCD_SEG0 waveform illustrates how different segment waveforms can be multiplexed with the COM lines in order to turn on and
off LCD pixels. As illustrated in the figures below, this waveform will turn ON pixels connected to LCD_COM1, while pixels connected to
LCD_COM0 and LCD_COM2 will be turned OFF.
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VLC0 (VLCD)
VLC3 (VSS)
VLC1 (2/3VLCD)
VLC2 (1/3VLCD)
Frame Start Frame End
Figure 33.28. LCD 1/3 Bias and Triplex Multiplexing - LCD_SEG0
com1
com2
com0
seg0
Figure 33.29. LCD 1/3 Bias and Triplex Multiplexing - LCD_SEG0 Connection
1/3 bias and triplex multiplexing - LCD_SEG0-LCD_COM0
• DC voltage = 0 (over one frame)
• VRMS = 0.33 VLCD_OUT
• The LCD display pixel that is connected to LCD_SEG0 and LCD_COM0 will be OFF with this waveform
VLC3 (VSS)
VLC0 (VLCD)
VLC1 (2/3VLCD)
VLC2 (1/3VLCD)
-VLC0 (VLCD)
-VLC1 (2/3VLCD)
-VLC2 (1/3VLCD)
Frame Start Frame End
Figure 33.30. LCD 1/3 Bias and Triplex Multiplexing - LCD_SEG0-LCD_COM0
1/3 bias and triplex multiplexing - LCD_SEG0-LCD_COM1
• DC voltage = 0 (over one frame)
• VRMS = 0.64 × VLCD_OUT
• The LCD display pixel that is connected to LCD_SEG0 and LCD_COM1 will be ON with this waveform
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VLC3 (VSS)
VLC0 (VLCD)
VLC1 (2/3VLCD)
VLC2 (1/3VLCD)
-VLC0 (VLCD)
-VLC1 (2/3VLCD)
-VLC2 (1/3VLCD)
Frame Start Frame End
Figure 33.31. LCD 1/3 Bias and Triplex Multiplexing - LCD_SEG0-LCD_COM1
1/3 bias and triplex multiplexing - LCD_SEG0-LCD_COM2
• DC voltage = 0 (over one frame)
• VRMS = 0.33 × VLCD_OUT
• The LCD display pixel that is connected to LCD_SEG0 and LCD_COM2 will be OFF with this waveform
VLC3 (VSS)
VLC0 (VLCD)
VLC1 (2/3VLCD)
VLC2 (1/3VLCD)
-VLC0 (VLCD)
-VLC1 (2/3VLCD)
-VLC2 (1/3VLCD)
Frame Start Frame End
Figure 33.32. LCD 1/3 Bias and Triplex Multiplexing - LCD_SEG0-LCD_COM2
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33.3.3.6 Waveforms with 1/3 Bias and Quadruplex Multiplexing
In this mode, each frame is divided into 8 periods. All COM lines can be multiplexed with all segment lines. Figures show 1/3 bias and
quadruplex multiplexing (waveforms show two frames).
VLC0 (VLCD)
VLC1 (2/3VLCD)
VLC3 (VSS)
VLC2 (1/3VLCD)
Frame Start Frame End
Figure 33.33. LCD 1/3 Bias and Quadruplex Multiplexing - LCD_COM0
VLC0 (VLCD)
VLC1 (2/3VLCD)
VLC3 (VSS)
VLC2 (1/3VLCD)
Frame Start Frame End
Figure 33.34. LCD 1/3 Bias and Quadruplex Multiplexing - LCD_COM1
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VLC0 (VLCD)
VLC1 (2/3VLCD)
VLC3 (VSS)
VLC2 (1/3VLCD)
Frame Start Frame End
Figure 33.35. LCD 1/3 Bias and Quadruplex Multiplexing - LCD_COM2
VLC0 (VLCD)
VLC1 (2/3VLCD)
VLC3 (VSS)
VLC2 (1/3VLCD)
Frame Start Frame End
Figure 33.36. LCD 1/3 Bias and Quadruplex Multiplexing - LCD_COM3
1/3 bias and quadruplex multiplexing - LCD_SEG0
The LCD_SEG0 waveform on the left is just an example to illustrate how different segment waveforms can be multiplexed with the
COM lines in order to turn on and off LCD pixels. As illustrated in the figures below, this wave form will turn ON pixels connected to
LCD_COM0 and LCD_COM2, while pixels connected to LCD_COM1 and LCD_COM3 will be turned OFF.
VLC0 (VLCD)
VLC1 (2/3VLCD)
VLC3 (VSS)
VLC2 (1/3VLCD)
Frame Start Frame End
Figure 33.37. LCD 1/3 Bias and Quadruplex Multiplexing - LCD_SEG0
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com1
com2
com3
com0
seg0
Figure 33.38. LCD 1/3 Bias and Quadruplex Multiplexing - LCD_SEG0 Connection
1/3 bias and quadruplex multiplexing - LCD_SEG0-LCD_COM0
• DC voltage = 0 (over one frame)
• VRMS = 0.58 × VLCD_OUT
• The LCD display pixel that is connected to LCD_SEG0 and LCD_COM0 will be ON with this waveform
VLC3 (VSS)
VLC0 (VLCD)
VLC1 (2/3VLCD)
VLC2 (1/3VLCD)
-VLC0 (VLCD)
-VLC1 (2/3VLCD)
-VLC2 (1/3VLCD)
Frame Start Frame End
Figure 33.39. LCD 1/3 Bias and Quadruplex Multiplexing - LCD_SEG0-LCD_COM0
1/3 bias and quadruplex multiplexing - LCD_SEG0-LCD_COM1
• DC voltage = 0 (over one frame)
• VRMS = 0.33 × VLCD_OUT
• The LCD display pixel that is connected to LCD_SEG0 and LCD_COM1 will be OFF with this waveform
VLC3 (VSS)
VLC0 (VLCD)
VLC1 (2/3VLCD)
VLC2 (1/3VLCD)
-VLC0 (VLCD)
-VLC1 (2/3VLCD)
-VLC2 (1/3VLCD)
Frame Start Frame End
Figure 33.40. LCD 1/3 Bias and Quadruplex Multiplexing - LCD_SEG0-LCD_COM1
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1/3 bias and quadruplex multiplexing - LCD_SEG0-LCD_COM2
• DC voltage = 0 (over one frame)
• VRMS = 0.58 × VLCD_OUT
• The LCD display pixel that is connected to LCD_SEG0 and LCD_COM2 will be ON with this waveform
VLC3 (VSS)
VLC0 (VLCD)
VLC1 (2/3VLCD)
VLC2 (1/3VLCD)
-VLC0 (VLCD)
-VLC1 (2/3VLCD)
-VLC2 (1/3VLCD)
Frame Start Frame End
Figure 33.41. LCD 1/3 Bias and Quadruplex Multiplexing - LCD_SEG0-LCD_COM2
1/3 bias and quadruplex multiplexing - LCD_SEG0-LCD_COM2
• DC voltage = 0 (over one frame)
• VRMS = 0.33 × VLCD_OUT
• The LCD display pixel that is connected to LCD_SEG0 and LCD_COM3 will be OFF with this waveform
VLC3 (VSS)
VLC0 (VLCD)
VLC1 (2/3VLCD)
VLC2 (1/3VLCD)
-VLC0 (VLCD)
-VLC1 (2/3VLCD)
-VLC2 (1/3VLCD)
Frame Start Frame End
Figure 33.42. LCD 1/3 Bias and Quadruplex Multiplexing- LCD_SEG0-LCD_COM3
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33.3.4 LCD Contrast
Different LCD panels have different characteristics and also temperature may affect the characteristics of the LCD panels. To compen-
sate for such variations, the LCD driver has a programmable contrast that adjusts the VLCD_OUT. The contrast is set by CONLEV in
LCD_DISPCTRL, and can be adjusted relative to either VDD (VLCD) or Ground using CONCONF in LCD_DISPCTRL. See the following
tables.
Table 33.4. LCD Contrast
BIAS CONLEV Equation Range
00 00000-11111 VLCD_OUT = VLCD x (0.61 x (1 + CONLEV/(25 - 1))) CONLEV = 0 => VLCD_OUT = 0.61VLCD
CONLEV = 31 => VLCD_OUT = VLCD
01 00000-11111 VLCD_OUT = VLCD x (0.53 x (1 + CONLEV/(25 - 1))) CONLEV = 0 => VLCD_OUT = 0.53VLCD
CONLEV = 31 => VLCD_OUT = VLCD
10 00000-11111 VLCD_OUT = VLCD x (0.61 x (1 + CONLEV/(25 - 1))) CONLEV = 0 => VLCD_OUT = 0.61VLCD
CONLEV = 31 => VLCD_OUT = VLCD
11 00000-11111 VLCD_OUT = VLCD x (0.61 x (1 + CONLEV/(25 - 1))) CONLEV = 0 => VLCD_OUT = 0.61VLCD
CONLEV = 31 => VLCD_OUT = VLCD
Note: Reset value is maximum contrast
Table 33.5. LCD Contrast Function
CONCONF Function
0 Contrast is adjusted relative to VDD (VLCD)
1 Contrast is adjusted relative to Ground
Table 33.6. LCD Principle of Contrast Adjustment for Different Bias Settings
Contrast adjustment relative
to VDD (VLCD) (CONCONF = 0)
Contrast adjustment relative
to VND (CONCONF = 0)
No contrast adjustment (CON-
LEV = 11111)
1/4 bias
VLC0
VLC1
VLC2
VLC3
R0
R1
R2
Rx
VLCD_OUT
VLCD
R3
VLC4
VLC0
VLC1
VLC2
VLC3
R0
R1
R2
VLCD
Rx
VLCD_OUT
R3
VLC4
VLC0
VLC1
VLC2
VLC3
R0
R1
R2
VLCD
VLCD_OUT
R3
VLC4
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Contrast adjustment relative
to VDD (VLCD) (CONCONF = 0)
Contrast adjustment relative
to VND (CONCONF = 0)
No contrast adjustment (CON-
LEV = 11111)
1/3 bias
VLC0
VLC1
VLC2
VLC3
R0
R1
R2
Rx
VLCD_OUT
VLCD
VLC0
VLC1
VLC2
VLC3
R0
R1
R2
VLCD
Rx
VLCD_OUT
VLC0
VLC1
VLC2
VLC3
R0
R1
R2
VLCD
VLCD_OUT
1/2 bias
VLC0
VLC1
VLC3
VLCD
R0
R1
Rx
VLCD_OUT
VLC0
VLC1
VLC3
VLCD
R0
R1
Rx
VLCD_OUT
VLC0
VLC1
VLC3
VLCD
R0
R1
VLCD_OUT
Static VLC0
VLC3
VLCD
R0
Rx
VLCD_OUT
VLC0
VLC3
R0
VLCD
Rx
VLCD_OUT VLC0
VLC3
VLCD
VLCD_OUT
R0 = R1 = R2 = R3 in the figure, while Rx is adjusted by changing the CONLEV bits.
33.3.5 VLCD Selection
By default, the LCD driver runs on main external power (VLCD = VDD), see the following table. An internal boost circuit can be enabled
by setting VBOOSTEN in CMU_LCDCTRL and selecting the boosted voltage by setting VLCDSEL in LCD_DISPCTRL. This will boosts
VLCD to VBOOST. VBOOST can be selected in the range of 3.0 V – 3.6 V by configuring VBLEV in LCD_DISPCTRL. Note that the boost
circuit is not designed to operate with the selected boost voltage, VBOOST, smaller than VDD. The boost circuit can boost the VLCD up to
3.6 V when VDD is as low as 2.0 V.
When using the voltage booster, the LCD_BEXT pin must be connected through a 1 μF capacitor to VSS, and the LCD_BCAP_P and
LCD_BCAP_N pins must be connected to each other through a 22 nF capacitor.
It is also possible to connect a dedicated power supply to the LCD module. The LCD external power supply must be connected to the
LCD_BEXT pin and VLCDSEL in LCD_DISPCTRL must be set. In this mode, the voltage booster should be disabled.
Table 33.7. LCD VLCD
VLCDSEL Mode VLCD
0 VDD VDD (same as main external power)
1 VBOOST Voltage booster/External VDD
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33.3.6 VBOOST Control
The boost voltage is configurable. By programming the VBLEV bits in LCD_DISPCTRL, the boost voltage level can be adjusted be-
tween 3.0V and 3.6V.
The boost circuit will use an update frequency given by the VBFDIV bits in CMU_LCDCTRL, see the following table. It is possible to
adjust the frequency to optimize performance for all kinds of LCD panels (large capacitors may require less frequent updates, while
small capacitors may require more frequent updates). A lower update frequency would in general lead to smaller current consumption.
Table 33.8. LCD VBOOST Frequency
VBFDIV VBOOST Update Frequency
000 LFACLK
001 LFACLK/2
010 LFACLK/4
011 LFACLK/8
100 LFACLK/16
101 LFACLK/32
110 LFACLK/64
111 LFACLK/128
33.3.7 Frame Rate
It is important to choose the correct frame rate for the LCD display. Normally, the frame rate should be between 30 and 100 Hz. A
frame rate below 30 Hz may lead to flickering, while a frame rate above 100 Hz may lead to ghostering and unnecessarily high power
consumption.
33.3.7.1 Clock Selection and Prescaler
The LFACLK is prescaled to LFACLKLCDpre in the CMU. The available prescaler settings are:
• LFCLK16: LFACLKLCDpre = LFACLK/16
• LFCLK32: LFACLKLCDpre = LFACLK/32
• LFCLK64: LFACLKLCDpre = LFACLK/64
• LFCLK128: LFACLKLCDpre = LFACLK/128
In addition to selecting the correct prescaling, the clock source can be selected in the CMU.
To use this module, the LE interface clock must be enabled in CMU_HFCORECLKEN0, in addition to the module clock.
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33.3.7.2 Frame Rate Division Register
The frame rate is set in the CMU by programming the frame rate division bits FDIV in CMU_LCDCTRL. This setting should not be
changed while the LCD driver is running. The equation for calculating the resulting frame rate is:
LFACLKLCD =
LFACLKLCDpre
1 + FDIV
Table 33.9. LCD Frame Rate Conversion Table
MUX Mode Frame-Rate Rormula
Resulting Frame rate, CLKFRAME (Hz)
LFACLKLCDpre = 2
kHz
LFACLKLCDpre = 1
kHz
LFACLKLCDpre = 0.5
kHz
LFACLKLCDpre = 0.25
kHz
Min Max Min Max Min Max Min Max
Static LFACLKLCD/2 128 1024 64 512 32 256 16 128
Duplex LFACLKLCD/4 64 512 32 256 16 128 8 64
Triplex LFACLKLCD/6 43 341 21 171 11 85 5 43
Quadruplex LFACLKLCD/8 32 256 16 128 8 64 4 32
Sextaplex LFACLKLCD/12 21.33 170.67 10.67 85.33 5.33 42.67 2..67 21.33
Octaplex LFACLKLCD/16 16 128 8 64 4 32 2 16
Table settings: Min: FDIV = 7, Max: FDIV = 0
33.3.8 Data Update
The LCD Driver logic that controls the output waveforms is clocked on LFACLKLCDpre. The LCD data and Control Registers are clocked
on the HFCORECLK. To avoid metastability and unpredictable behavior, the data in the Segment Data (SEGDn) registers must be
synchronized to the LCD driver logic. Also, it is important that data is updated at the beginning of an LCD frame since the segment
waveform depends on the segment data and a change in the middle of a frame may lead to a DC-component in that frame. The LCD
driver has dedicated functionality to synchronize data transfer to the LCD frames. The synchronization logic is applied to all data that
need to be updated at the beginning of the LCD frames:
• LCD_SEGDn
• LCD_AREGA
• LCD_AREGB
• LCD_BACTRL
The different methods to update data are controlled by the UDCTRL bits in LCD_CTRL.
Table 33.10. LCD Update Data Control (UDCTRL) Bits
UDCTRL Mode Description
00 REGULAR The data transfer is controlled by SW and data synchronization is initiated by writing data
to the buffers. Data is transferred as soon as possible, possibly creating a frame with a
DC component on the LCD.
01 FCEVENT The data transfer is done at the next event triggered by the Frame Counter (FC). See
Section 33.3.10 Frame Counter (FC) for details on how to configure the Frame Counter.
Optionally, the Frame Counter can also generate an interrupt at every event.
10 FRAMESTART The data transfer is done at frame-start.
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33.3.9 Direct Segment Control (DSC)
It is possible to gain direct control over the bias levels for each SEG/COM line by setting DSC in LCD_CTRL, overwriting the BIAS
settings in LCD_DISPCTRL. The SEG lines bias levels can be set in SEGD0-SEGD3, while the COM line bias levels can be set in
SEGD4. To represent the different bias levels, 2-bits per SEG lines are needed. For example, SEG0's bias levels can be set using
SEGD0[1:0], and SEG1 can be controlled through SEGD0[3:2] etc. Bias level encoding is shown in the table below.
Table 33.11. DSC BIAS Encoding
SEGD Mode Bias setting
00 Static Static (2 levels)
01 Half Bias 1/2 Bias (3 levels)
10 Third Bias 1/3 Bias (4 levels)
11 Fourth Bias 1/4 Bias (5 levels)
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33.3.10 Frame Counter (FC)
The Frame Counter is synchronized to the LCD frame start and will generate an event after a programmable number of frames. An FC
event can trigger:
• LCD ready interrupt
• Blink (controlling the blink frequency)
• Next state in the Animation State Machine
• Data update if UDCTRL = 01
The Frame Counter is a down counter. It is enabled by writing FCEN in LCD_BACTRL. Optionally, the Frame Counter can be prescaled
so that the Frame Counter is decremented at:
• Every frame
• Every second frame
• Every fourth frame
• Every eight frame
This is controlled by the FCPRESC in LCD_BACTRL, see the following table.
Table 33.12. FCPRESC
FCPRESC Mode Description General Equation
00 Div1 CLKFRAME/1
CLKFC =
CLKFRAME
2FCPRESC
01 Div2 CLKFRAME/2
10 Div4 CLKFRAME/4
11 Div8 CLKFRAME/8
The top value for the Frame Counter is set by FCTOP in LCD_BACTRL. Every time the frame counter reaches zero, it is reloaded with
the top value, and at the same time an event, which can cause an interrupt, data update, blink, or an animation state transition is trig-
gered.
CLKEVENT =
CLKFC
1 + FCTOP[5:0] Hz
The previous equation shows how to set-up the LCD event frequency. In this example, the frame rate is 64Hz, and the LCD event fre-
quency should be set-up to 2 seconds.
• Write FCPRESC to 3 => CLKFC = 8Hz (0.125 seconds)
• Write FCTOP to 15 => CLKEVENT = 0.5Hz (2 seconds)
If higher resolution is required, configure a lower prescaler value and increase the FCPRESC in LCD_BACTRL accordingly (e.g.
FCPRESC = 2, FCTOP = 31).
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ero 4»
mm 4»
mam“
CMU_lFAPRESOn
FDIVI 0]
1“ch
LFXO
LFRCO
Counter
FDIV[2:0]
LCD Frame
Counter
FCTOP[5:0]
LFACLKLCDpre
CLKFC
CLKEVENT
div2
CLKFRAME
MUX in
LCD_DISPCTRL
LFACLKLCD
LCD in
CMU_LFAPRESC0
CMU
div16
div32
div64
div128
div1
div2
div4
div8 FCPRESC in
LCD_BACTRL
LFACLK
div4
div6
div8
div12
div16
static
duplex
triplex
quadruplex
sextaplex
octaplex
Figure 33.43. LCD Clock System in LCD Driver
33.3.11 LCD Interrupt
The LCD interrupt can be used to synchronize data update. The FC interrupt flag is set at every LCD Frame Counter Event, which must
be set-up separately. The interrupt is enabled by setting FC bit in LCD_IEN.
33.3.12 Blink, Blank, and Animation Features
33.3.12.1 Blink
The LCD driver can be configured to blink, alternating all enabled segments between on and off. The blink frequency is given by the
CLKEVENT frequency, see 33.3.10 Frame Counter (FC). See 33.3.8 Data Update for details regarding synchronization of the blink fea-
ture. The FC must be on for blink to work.
33.3.12.2 Blank
Setting BLANK in LCD_BACTRL will output the “OFF” waveform on all enabled segments, effectively blanking the entire display. Writ-
ing the BLANK bit to zero disables the blanking and segment data will be output as normal. See 33.3.8 Data Update for details regard-
ing synchronization of blank.
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33.3.12.3 Animation State Machine
The Animation State Machine makes it possible to enable different animations without updating the data registers, allowing specialized
patterns running on the LCD panel while the microcontroller remains in Low Energy Mode and thus saving power consumption. The
animation feature is available on 8 segments multiplexed with LCD_COM0. The 8 segments can be either segments 0 to 7 or 8 to 15,
depending on ALOC in LCD_BACTRL. The animation is implemented as two programmable 8 bits registers that are shifted left or right
every other Animation state for a total of 16 states.
The shift operations applied to the shift registers are controlled by AREGASC and AREGBSC in LCD_BACTRL as shown in the follow-
ing table. Note also that the FC must be on for animation to work, as it is the FC event that drives the animation state machine.
Table 33.13. LCD Animation Shift Register
AREGnSC, n = A or
B
Mode Description
00 NOSHIFT No Shift operation
01 SHIFTLEFT Animation register is shifted left (LCD_AREGA is shifted every odd state, LCD_AREGB
is shifted every even state)
10 SHIFTRIGHT Animation register is shifted right (LCD_AREGA is shifted every odd state, LCD_AREGB
is shifted every even state)
11 Reserved Reserved
The two registers are either OR’ed or AND’ed to achieve the displayed animation pattern. This is controlled by ALOGSEL in
LCD_BACTRL as shown in the following table. In addition, the regular segment data SEGD0[7:0] / SEGD0[15:8] is OR’ed with the ani-
mation pattern to generate the resulting output.
Table 33.14. LCD Animation Pattern
ALOGSEL Mode Description
0 AND LCD_AREGA and LCD_AREGB are AND’ed together
1 OR LCD_AREGA and LCD_AREGB are OR’ed together
Each state is displayed one CLKEVENT period, see 33.3.10 Frame Counter (FC). By reading ASTATE in LCD_STATUS, software can
identify which state that is currently active in the state sequence. Note that the shifting operation is performed on internal registers that
are not accessible in SW (when reading LCD_AREGA and LCD_AREGB, the data that was original written will also be read back). The
SW must utilize the knowledge about the current state (ASTATE) to calculate what is currently output. ASTATE is cleared when
LCD_AREGA or LCD_AREGB are updated with new values. See the following table for an example.
Table 33.15. LCD Animation Example
ASTATE LCD_AREGA LCD_AREGB Resulting Data
0 11000000 11000000 11000000
1 01100000 11000000 11100000
2 01100000 01100000 01100000
3 00110000 01100000 01110000
4 00110000 00110000 00110000
5 00011000 00110000 00111000
6 00011000 00011000 00011000
7 00001100 00011000 00011100
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A e
4»
4»
A «
ASTATE LCD_AREGA LCD_AREGB Resulting Data
8 00001100 00001100 00001100
9 00000110 00001100 00001110
10 00000110 00000110 00000110
11 00000011 00000110 00000111
12 00000011 00000011 00000011
13 10000001 00000011 10000011
14 10000001 10000001 10000001
15 11000000 10000001 11000001
In the table, AREGASC = 10, AREGBSC = 10, ALOGSEL = 1 and the resulting data is to be displayed on segment lines 7-0 or 15-8
multiplexed with LCD_COM0.
AREGA
AREGB
AREGASC = 1 => shift left
AREGASC = 2 => shift right
Odd animation states
AREGBSC = 1 => shift left
AREGBSC = 2 => shift right
Even animation states
ALOGSEL
Data Out[7:0] / [15:8]
CLKEVENT
SEGD0[7:0] / SEGD0[15:8]
Figure 33.44. LCD Block Diagram of the Animation Circuit
LCD Animation Enable Example
• Write data into the animation registers LCD_AREGA, LCD_AREGB
• Enable the correct shift direction (if any)
• Decide which logical function to perform on the registers
• ALOGSEL = 0: Data_out = LCD_AREGA & LCD_AREGB
• ALOGSEL = 1:Data_out = LCD_AREGA | LCD_AREGB
• Configure the right animation period (CLKEVENT)
• Enable the animation pattern and frame counter (AEN = 1, FCEN = 1)
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LCD Animation Dependence Example
For updating data in the LCD while it is running an animation, and the new animation data depends on the pattern visible on the LCD,
see the following example.
• Enable the LCD interrupt (the interrupt will be triggered simultaneously as the Animation State machine changes state)
• In the interrupt handler, read back the current state (ASTATE)
• Knowing the current state of the Animation State Machine makes it possible to calculate what data that is currently output
• Modify data as required (Data will be updated at the next Frame Counter Event). It is important that new data is written before the
next Frame Counter Event.
33.3.13 LCD in Low Energy Modes
As long as the LFACLK is running (EM0-EM2), the LCD controller continues to output LCD waveforms according to the data that is
currently synchronized to the LCD Driver logic. In addition, the following features are still active if enabled:
• Animation State Machine
• Blink
• LCD Event Interrupt
33.3.14 Register Access
Since this module is a Low Energy Peripheral, and runs off a clock which is asynchronous to the HFCORECLK, special considerations
must be taken when accessing registers. Please refer to 5.2.4 Access to Low Energy Peripherals (Asynchronous Registers) for a de-
scription on how to perform register accesses to Low Energy Peripherals.
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33.4 Register Map
The offset register address is relative to the registers base address.
Offset Name Type Description
0x000 LCD_CTRL RW Control Register
0x004 LCD_DISPCTRL RW Display Control Register
0x008 LCD_SEGEN RW Segment Enable Register
0x00C LCD_BACTRL RW Blink and Animation Control Register
0x010 LCD_STATUS RStatus Register
0x014 LCD_AREGA RW Animation Register A
0x018 LCD_AREGB RW Animation Register B
0x01C LCD_IF RInterrupt Flag Register
0x020 LCD_IFS W1 Interrupt Flag Set Register
0x024 LCD_IFC (R)W1 Interrupt Flag Clear Register
0x028 LCD_IEN RW Interrupt Enable Register
0x040 LCD_SEGD0L RW Segment Data Low Register 0
0x044 LCD_SEGD1L RW Segment Data Low Register 1
0x048 LCD_SEGD2L RW Segment Data Low Register 2
0x04C LCD_SEGD3L RW Segment Data Low Register 3
0x050 LCD_SEGD0H RW Segment Data High Register 0
0x054 LCD_SEGD1H RW Segment Data High Register 1
0x058 LCD_SEGD2H RW Segment Data High Register 2
0x05C LCD_SEGD3H RW Segment Data High Register 3
0x060 LCD_FREEZE RW Freeze Register
0x064 LCD_SYNCBUSY RSynchronization Busy Register
0x0B4 LCD_SEGD4H RW Segment Data High Register 4
0x0B8 LCD_SEGD5H RW Segment Data High Register 5
0x0BC LCD_SEGD6H RW Segment Data High Register 6
0x0C0 LCD_SEGD7H RW Segment Data High Register 7
0x0CC LCD_SEGD4L RW Segment Data Low Register 4
0x0D0 LCD_SEGD5L RW Segment Data Low Register 5
0x0D4 LCD_SEGD6L RW Segment Data Low Register 6
0x0D8 LCD_SEGD7L RW Segment Data Low Register 7
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33.5 Register Description
33.5.1 LCD_CTRL - Control Register (Async Reg)
For more information about Asynchronous Registers, see 5.2.4 Access to Low Energy Peripherals (Asynchronous Registers).
Offset Bit Position
0x000
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
16
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
Reset
0
0x0
0
Access
RW
RW
RW
Name
DSC
UDCTRL
EN
Bit Name Reset Access Description
31:24 Reserved To ensure compatibility with future devices, always write bits to 0. More information in 2.1 Conven-
tions.
23 DSC 0 RW Direct Segment Control
This bit enables direct control over bias levels for each SEG/COM line.
Value Description
0 DSC disable
1 DSC enable
22:3 Reserved To ensure compatibility with future devices, always write bits to 0. More information in 2.1 Conven-
tions.
2:1 UDCTRL 0x0 RW Update Data Control
These bits control how data from the SEGDn registers are transferred to the LCD driver.
Value Mode Description
0 REGULAR The data transfer is controlled by SW. Transfer is performed as soon
as possible
1 FCEVENT The data transfer is done at the next event triggered by the Frame
Counter
2 FRAMESTART The data transfer is done continuously at every LCD frame start
0 EN 0 RW LCD Enable
When this bit is set, the LCD driver is enabled and the driver will start outputting waveforms on the com/segment lines.
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33.5.2 LCD_DISPCTRL - Display Control Register
Offset Bit Position
0x004
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
16
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
Reset
0
0x3
0
0
0x1F
0
0x0
0x0
Access
RW
RW
RW
RW
RW
RW
RW
RW
Name
MUXE
VBLEV
VLCDSEL
CONCONF
CONLEV
WAVE
BIAS
MUX
Bit Name Reset Access Description
31:23 Reserved To ensure compatibility with future devices, always write bits to 0. More information in 2.1 Conven-
tions.
22 MUXE 0 RW Extended Mux Configuration
This bit redefines the meaning of the MUX field.
Value Mode Description
0 MUX Multiplex mode determined by MUX field.
1 MUXE Mux extended mode. Extends the meaning of the MUX field.
21 Reserved To ensure compatibility with future devices, always write bits to 0. More information in 2.1 Conven-
tions.
20:18 VBLEV 0x3 RW Voltage Boost Level
These bits control Voltage Boost level. Please refer to datasheet for further details of the boost levels.
Value Mode Description
0 LEVEL0 Minimum boost level
1 LEVEL1
2 LEVEL2
3 LEVEL3
4 LEVEL4
5 LEVEL5
6 LEVEL6
7 LEVEL7 Maximum boost level
17 Reserved To ensure compatibility with future devices, always write bits to 0. More information in 2.1 Conven-
tions.
16 VLCDSEL 0 RW VLCD Selection
This bit controls which Voltage source that is connected to VLCD.
Value Mode Description
0 VDD VDD
1 VEXTBOOST Voltage Booster/External VDD
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Bit Name Reset Access Description
15 CONCONF 0 RW Contrast Configuration
This bit selects whether the contrast adjustment is done relative to VLCD or Ground.
Value Mode Description
0 VLCD Contrast is adjusted relative to VLCD
1 GND Contrast is adjusted relative to Ground
14:13 Reserved To ensure compatibility with future devices, always write bits to 0. More information in 2.1 Conven-
tions.
12:8 CONLEV 0x1F RW Contrast Level
These bits control the contrast setting according to this formula: VLCD_OUT = VLCD × 0.5(1+CONLEV/31).
Value Mode Description
0 MIN Minimum contrast
31 MAX Maximum contrast
7:5 Reserved To ensure compatibility with future devices, always write bits to 0. More information in 2.1 Conven-
tions.
4 WAVE 0 RW Waveform Selection
This bit configures the output waveform.
Value Mode Description
0 LOWPOWER Low power waveform
1 NORMAL Normal waveform
3:2 BIAS 0x0 RW Bias Configuration
These bits set the bias mode for the LCD Driver.
Value Mode Description
0 STATIC Static
1 ONEHALF 1/2 Bias
2 ONETHIRD 1/3 Bias
3 ONEFOURTH 1/4 Bias
1:0 MUX 0x0 RW Mux Configuration
These bits set the multiplexing mode for the LCD Driver. The field is dependent on the value of MUXE field
MUX MUXE Mode
0 0 STATIC
1 0 DUPLEX
2 0 TRIPLEX
3 0 QUADRUPLEX
1 1 SEXTAPLEX
3 1 OCTAPLEX
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33.5.3 LCD_SEGEN - Segment Enable Register
Offset Bit Position
0x008
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
16
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
Reset
0x000
Access
RW
Name
SEGEN
Bit Name Reset Access Description
31:10 Reserved To ensure compatibility with future devices, always write bits to 0. More information in 2.1 Conven-
tions.
9:0 SEGEN 0x000 RW Segment Enable
Determines which segment lines are enabled. Each bit represents a group of 4 segment lines. To enable segment lines X
to X+3, set bit X/4, i.e. to enable output on segment lines 4,5,6 and 7, set bit 1. Each LCD segment pin can also be individ-
ually disabled by setting the pin to any other state than DISABLED in the GPIO pin configuration.
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33.5.4 LCD_BACTRL - Blink and Animation Control Register (Async Reg)
For more information about Asynchronous Registers, see 5.2.4 Access to Low Energy Peripherals (Asynchronous Registers).
Offset Bit Position
0x00C
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
16
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
Reset
0
0x00
0x0
0
0
0x0
0x0
0
0
0
Access
RW
RW
RW
RW
RW
RW
RW
RW
RW
RW
Name
ALOC
FCTOP
FCPRESC
FCEN
ALOGSEL
AREGBSC
AREGASC
AEN
BLANK
BLINKEN
Bit Name Reset Access Description
31:29 Reserved To ensure compatibility with future devices, always write bits to 0. More information in 2.1 Conven-
tions.
28 ALOC 0 RW Animation Location
Set the LCD segments which animation applies to
Value Mode Description
0 SEG0TO7 Animation appears on segments 0 to 7
1 SEG8TO15 Animation appears on segments 8 to 15
27:24 Reserved To ensure compatibility with future devices, always write bits to 0. More information in 2.1 Conven-
tions.
23:18 FCTOP 0x00 RW Frame Counter Top Value
These bits contain the Top Value for the Frame Counter: CLKEVENT = CLKFC / (1 + FCTOP[5:0]).
17:16 FCPRESC 0x0 RW Frame Counter Prescaler
These bits controls the prescaling value for the Frame Counter input clock.
Value Mode Description
0 DIV1 CLKFC = CLKFRAME / 1
1 DIV2 CLKFC = CLKFRAME / 2
2 DIV4 CLKFC = CLKFRAME / 4
3 DIV8 CLKFC = CLKFRAME / 8
15:9 Reserved To ensure compatibility with future devices, always write bits to 0. More information in 2.1 Conven-
tions.
8 FCEN 0 RW Frame Counter Enable
When this bit is set, the frame counter is enabled.
7 ALOGSEL 0 RW Animate Logic Function Select
When this bit is set, the animation registers are AND'ed together. When this bit is cleared, the animation registers are
OR'ed together.
Value Mode Description
0 AND AREGA and AREGB AND'ed
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Bit Name Reset Access Description
1 OR AREGA and AREGB OR'ed
6:5 AREGBSC 0x0 RW Animate Register B Shift Control
These bits controls the shift operation that is performed on Animation register B.
Value Mode Description
0 NOSHIFT No Shift operation on Animation Register B
1 SHIFTLEFT Animation Register B is shifted left
2 SHIFTRIGHT Animation Register B is shifted right
4:3 AREGASC 0x0 RW Animate Register A Shift Control
These bits controls the shift operation that is performed on Animation register A.
Value Mode Description
0 NOSHIFT No Shift operation on Animation Register A
1 SHIFTLEFT Animation Register A is shifted left
2 SHIFTRIGHT Animation Register A is shifted right
2 AEN 0 RW Animation Enable
When this bit is set, the animate function is enabled.
1 BLANK 0 RW Blank Display
When this bit is set, all segment output waveforms are configured to blank the LCD display. The Segment Data Registers
are not affected when writing this bit.
Value Description
0 Display is not "blanked"
1 Display is "blanked"
0 BLINKEN 0 RW Blink Enable
When this bit is set, the Blink function is enabled. Every "ON" segment will alternate between on and off at every Frame
Counter Event.
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33.5.5 LCD_STATUS - Status Register
Offset Bit Position
0x010
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
16
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
Reset
0
0x0
Access
R
R
Name
BLINK
ASTATE
Bit Name Reset Access Description
31:9 Reserved To ensure compatibility with future devices, always write bits to 0. More information in 2.1 Conven-
tions.
8 BLINK 0 R Blink State
This bits indicates the blink status. If this bit is 1, all segments are off. If this bit is 0, the segments(LCD_SEGDxn) which are
set to 1 are on.
7:4 Reserved To ensure compatibility with future devices, always write bits to 0. More information in 2.1 Conven-
tions.
3:0 ASTATE 0x0 R Current Animation State
Contains the current animation state (0-15).
33.5.6 LCD_AREGA - Animation Register A (Async Reg)
For more information about Asynchronous Registers, see 5.2.4 Access to Low Energy Peripherals (Asynchronous Registers).
Offset Bit Position
0x014
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
16
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
Reset
0x00
Access
RW
Name
AREGA
Bit Name Reset Access Description
31:8 Reserved To ensure compatibility with future devices, always write bits to 0. More information in 2.1 Conven-
tions.
7:0 AREGA 0x00 RW Animation Register A Data
This register contains the A data for generating animation pattern.
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33.5.7 LCD_AREGB - Animation Register B (Async Reg)
For more information about Asynchronous Registers, see 5.2.4 Access to Low Energy Peripherals (Asynchronous Registers).
Offset Bit Position
0x018
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
16
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
Reset
0x00
Access
RW
Name
AREGB
Bit Name Reset Access Description
31:8 Reserved To ensure compatibility with future devices, always write bits to 0. More information in 2.1 Conven-
tions.
7:0 AREGB 0x00 RW Animation Register B Data
This register contains the B data for generating animation pattern.
33.5.8 LCD_IF - Interrupt Flag Register
Offset Bit Position
0x01C
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
16
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
Reset
0
Access
R
Name
FC
Bit Name Reset Access Description
31:1 Reserved To ensure compatibility with future devices, always write bits to 0. More information in 2.1 Conven-
tions.
0 FC 0 R Frame Counter Interrupt Flag
Set when Frame Counter is zero.
33.5.9 LCD_IFS - Interrupt Flag Set Register
Offset Bit Position
0x020
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
16
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
Reset
0
Access
W1
Name
FC
Bit Name Reset Access Description
31:1 Reserved To ensure compatibility with future devices, always write bits to 0. More information in 2.1 Conven-
tions.
0 FC 0 W1 Frame Counter Interrupt Flag Set
Write to 1 to set FC interrupt flag.
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33.5.10 LCD_IFC - Interrupt Flag Clear Register
Offset Bit Position
0x024
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
16
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
Reset
0
Access
(R)W1
Name
FC
Bit Name Reset Access Description
31:1 Reserved To ensure compatibility with future devices, always write bits to 0. More information in 2.1 Conven-
tions.
0 FC 0 (R)W1 Frame Counter Interrupt Flag Clear
Write to 1 to clear FC interrupt flag.
33.5.11 LCD_IEN - Interrupt Enable Register
Offset Bit Position
0x028
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
16
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
Reset
0
Access
RW
Name
FC
Bit Name Reset Access Description
31:1 Reserved To ensure compatibility with future devices, always write bits to 0. More information in 2.1 Conven-
tions.
0 FC 0 RW Frame Counter Interrupt Enable
Set to enable interrupt on frame counter interrupt flag.
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33.5.12 LCD_SEGD0L - Segment Data Low Register 0 (Async Reg)
For more information about Asynchronous Registers, see 5.2.4 Access to Low Energy Peripherals (Asynchronous Registers).
Offset Bit Position
0x040
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
16
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
Reset
0x00000000
Access
RW
Name
SEGD0L
Bit Name Reset Access Description
31:0 SEGD0L 0x00000000 RW COM0 Segment Data Low
This register contains segment data for segment lines 0-31 for COM0.
33.5.13 LCD_SEGD1L - Segment Data Low Register 1 (Async Reg)
For more information about Asynchronous Registers, see 5.2.4 Access to Low Energy Peripherals (Asynchronous Registers).
Offset Bit Position
0x044
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
16
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
Reset
0x00000000
Access
RW
Name
SEGD1L
Bit Name Reset Access Description
31:0 SEGD1L 0x00000000 RW COM1 Segment Data Low
This register contains segment data for segment lines 0-31 for COM1.
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33.5.14 LCD_SEGD2L - Segment Data Low Register 2 (Async Reg)
For more information about Asynchronous Registers, see 5.2.4 Access to Low Energy Peripherals (Asynchronous Registers).
Offset Bit Position
0x048
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
16
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
Reset
0x00000000
Access
RW
Name
SEGD2L
Bit Name Reset Access Description
31:0 SEGD2L 0x00000000 RW COM2 Segment Data Low
This register contains segment data for segment lines 0-31 for COM2.
33.5.15 LCD_SEGD3L - Segment Data Low Register 3 (Async Reg)
For more information about Asynchronous Registers, see 5.2.4 Access to Low Energy Peripherals (Asynchronous Registers).
Offset Bit Position
0x04C
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
16
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
Reset
0x00000000
Access
RW
Name
SEGD3L
Bit Name Reset Access Description
31:0 SEGD3L 0x00000000 RW COM3 Segment Data Low
This register contains segment data for segment lines 0-31 for COM3.
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33.5.16 LCD_SEGD0H - Segment Data High Register 0 (Async Reg)
For more information about Asynchronous Registers, see 5.2.4 Access to Low Energy Peripherals (Asynchronous Registers).
Offset Bit Position
0x050
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
16
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
Reset
0x00
Access
RW
Name
SEGD0H
Bit Name Reset Access Description
31:8 Reserved To ensure compatibility with future devices, always write bits to 0. More information in 2.1 Conven-
tions.
7:0 SEGD0H 0x00 RW COM0 Segment Data High
This register contains segment data for segment lines 32-39 for COM0.
33.5.17 LCD_SEGD1H - Segment Data High Register 1 (Async Reg)
For more information about Asynchronous Registers, see 5.2.4 Access to Low Energy Peripherals (Asynchronous Registers).
Offset Bit Position
0x054
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
16
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
Reset
0x00
Access
RW
Name
SEGD1H
Bit Name Reset Access Description
31:8 Reserved To ensure compatibility with future devices, always write bits to 0. More information in 2.1 Conven-
tions.
7:0 SEGD1H 0x00 RW COM1 Segment Data High
This register contains segment data for segment lines 32-39 for COM1.
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33.5.18 LCD_SEGD2H - Segment Data High Register 2 (Async Reg)
For more information about Asynchronous Registers, see 5.2.4 Access to Low Energy Peripherals (Asynchronous Registers).
Offset Bit Position
0x058
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
16
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
Reset
0x00
Access
RW
Name
SEGD2H
Bit Name Reset Access Description
31:8 Reserved To ensure compatibility with future devices, always write bits to 0. More information in 2.1 Conven-
tions.
7:0 SEGD2H 0x00 RW COM2 Segment Data High
This register contains segment data for segment lines 32-39 for COM2.
33.5.19 LCD_SEGD3H - Segment Data High Register 3 (Async Reg)
For more information about Asynchronous Registers, see 5.2.4 Access to Low Energy Peripherals (Asynchronous Registers).
Offset Bit Position
0x05C
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
16
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
Reset
0x00
Access
RW
Name
SEGD3H
Bit Name Reset Access Description
31:8 Reserved To ensure compatibility with future devices, always write bits to 0. More information in 2.1 Conven-
tions.
7:0 SEGD3H 0x00 RW COM3 Segment Data High
This register contains segment data for segment lines 32-39 for COM3.
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33.5.20 LCD_FREEZE - Freeze Register
Offset Bit Position
0x060
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
16
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
Reset
0
Access
RW
Name
REGFREEZE
Bit Name Reset Access Description
31:1 Reserved To ensure compatibility with future devices, always write bits to 0. More information in 2.1 Conven-
tions.
0 REGFREEZE 0 RW Register Update Freeze
When set, the update of the LCD is postponed until this bit is cleared. Use this bit to update several registers simultaneous-
ly.
Value Mode Description
0 UPDATE Each write access to an LCD register is updated into the Low Frequen-
cy domain as soon as possible.
1 FREEZE The LCD is not updated with the new written value.
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33.5.21 LCD_SYNCBUSY - Synchronization Busy Register
Offset Bit Position
0x064
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
16
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
Reset
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
Access
R
R
R
R
R
R
R
R
R
R
R
R
R
R
R
R
R
R
R
R
Name
SEGD7L
SEGD6L
SEGD5L
SEGD4L
SEGD7H
SEGD6H
SEGD5H
SEGD4H
SEGD3H
SEGD2H
SEGD1H
SEGD0H
SEGD3L
SEGD2L
SEGD1L
SEGD0L
AREGB
AREGA
BACTRL
CTRL
Bit Name Reset Access Description
31:20 Reserved To ensure compatibility with future devices, always write bits to 0. More information in 2.1 Conven-
tions.
19 SEGD7L 0 R SEGD7L Register Busy
Set when the value written to SEGD7L is being synchronized.
18 SEGD6L 0 R SEGD6L Register Busy
Set when the value written to SEGD6L is being synchronized.
17 SEGD5L 0 R SEGD5L Register Busy
Set when the value written to SEGD5L is being synchronized.
16 SEGD4L 0 R SEGD4L Register Busy
Set when the value written to SEGD4L is being synchronized.
15 SEGD7H 0 R SEGD7H Register Busy
Set when the value written to SEGD7H is being synchronized.
14 SEGD6H 0 R SEGD6H Register Busy
Set when the value written to SEGD6H is being synchronized.
13 SEGD5H 0 R SEGD5H Register Busy
Set when the value written to SEGD5H is being synchronized.
12 SEGD4H 0 R SEGD4H Register Busy
Set when the value written to SEGD4H is being synchronized.
11 SEGD3H 0 R SEGD3H Register Busy
Set when the value written to SEGD3H is being synchronized.
10 SEGD2H 0 R SEGD2H Register Busy
Set when the value written to SEGD2H is being synchronized.
9 SEGD1H 0 R SEGD1H Register Busy
Set when the value written to SEGD1H is being synchronized.
8 SEGD0H 0 R SEGD0H Register Busy
Set when the value written to SEGD0H is being synchronized.
7 SEGD3L 0 R SEGD3L Register Busy
Set when the value written to SEGD3L is being synchronized.
6 SEGD2L 0 R SEGD2L Register Busy
Set when the value written to SEGD2L is being synchronized.
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Bit Name Reset Access Description
5 SEGD1L 0 R SEGD1L Register Busy
Set when the value written to SEGD1L is being synchronized.
4 SEGD0L 0 R SEGD0L Register Busy
Set when the value written to SEGD0L is being synchronized.
3 AREGB 0 R AREGB Register Busy
Set when the value written to AREGB is being synchronized.
2 AREGA 0 R AREGA Register Busy
Set when the value written to AREGA is being synchronized.
1 BACTRL 0 R BACTRL Register Busy
Set when the value written to BACTRL is being synchronized.
0 CTRL 0 R CTRL Register Busy
Set when the value written to CTRL is being synchronized.
33.5.22 LCD_SEGD4H - Segment Data High Register 4 (Async Reg)
For more information about Asynchronous Registers, see 5.2.4 Access to Low Energy Peripherals (Asynchronous Registers).
Offset Bit Position
0x0B4
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
16
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
Reset
0x00
Access
RW
Name
SEGD4H
Bit Name Reset Access Description
31:8 Reserved To ensure compatibility with future devices, always write bits to 0. More information in 2.1 Conven-
tions.
7:0 SEGD4H 0x00 RW COM0 Segment Data High
This register contains segment data for segment lines 32-39 for COM0.
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33.5.23 LCD_SEGD5H - Segment Data High Register 5 (Async Reg)
For more information about Asynchronous Registers, see 5.2.4 Access to Low Energy Peripherals (Asynchronous Registers).
Offset Bit Position
0x0B8
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
16
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
Reset
0x00
Access
RW
Name
SEGD5H
Bit Name Reset Access Description
31:8 Reserved To ensure compatibility with future devices, always write bits to 0. More information in 2.1 Conven-
tions.
7:0 SEGD5H 0x00 RW COM1 Segment Data High
This register contains segment data for segment lines 32-39 for COM1.
33.5.24 LCD_SEGD6H - Segment Data High Register 6 (Async Reg)
For more information about Asynchronous Registers, see 5.2.4 Access to Low Energy Peripherals (Asynchronous Registers).
Offset Bit Position
0x0BC
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
16
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
Reset
0x00
Access
RW
Name
SEGD6H
Bit Name Reset Access Description
31:8 Reserved To ensure compatibility with future devices, always write bits to 0. More information in 2.1 Conven-
tions.
7:0 SEGD6H 0x00 RW COM2 Segment Data High
This register contains segment data for segment lines 32-39 for COM2.
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33.5.25 LCD_SEGD7H - Segment Data High Register 7 (Async Reg)
For more information about Asynchronous Registers, see 5.2.4 Access to Low Energy Peripherals (Asynchronous Registers).
Offset Bit Position
0x0C0
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
16
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
Reset
0x00
Access
RW
Name
SEGD7H
Bit Name Reset Access Description
31:8 Reserved To ensure compatibility with future devices, always write bits to 0. More information in 2.1 Conven-
tions.
7:0 SEGD7H 0x00 RW COM3 Segment Data High
This register contains segment data for segment lines 32-39 for COM3.
33.5.26 LCD_SEGD4L - Segment Data Low Register 4 (Async Reg)
For more information about Asynchronous Registers, see 5.2.4 Access to Low Energy Peripherals (Asynchronous Registers).
Offset Bit Position
0x0CC
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
16
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
Reset
0x00000000
Access
RW
Name
SEGD4L
Bit Name Reset Access Description
31:0 SEGD4L 0x00000000 RW COM4 Segment Data
This register contains segment data for segment lines 0-23 for COM4.
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33.5.27 LCD_SEGD5L - Segment Data Low Register 5 (Async Reg)
For more information about Asynchronous Registers, see 5.2.4 Access to Low Energy Peripherals (Asynchronous Registers).
Offset Bit Position
0x0D0
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
16
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
Reset
0x00000000
Access
RW
Name
SEGD5L
Bit Name Reset Access Description
31:0 SEGD5L 0x00000000 RW COM5 Segment Data
This register contains segment data for segment lines 0-23 for COM5.
33.5.28 LCD_SEGD6L - Segment Data Low Register 6 (Async Reg)
For more information about Asynchronous Registers, see 5.2.4 Access to Low Energy Peripherals (Asynchronous Registers).
Offset Bit Position
0x0D4
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
16
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
Reset
0x00000000
Access
RW
Name
SEGD6L
Bit Name Reset Access Description
31:0 SEGD6L 0x00000000 RW COM6 Segment Data
This register contains segment data for segment lines 0-23 for COM6.
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33.5.29 LCD_SEGD7L - Segment Data Low Register 7 (Async Reg)
For more information about Asynchronous Registers, see 5.2.4 Access to Low Energy Peripherals (Asynchronous Registers).
Offset Bit Position
0x0D8
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
16
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
Reset
0x00000000
Access
RW
Name
SEGD7L
Bit Name Reset Access Description
31:0 SEGD7L 0x00000000 RW COM7 Segment Data
This register contains segment data for segment lines 0-23 for COM7.
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34. FPUEH - Floating Point Unit Exception Handler
43210
Floating-Point
Unit
Exception IRQ ARM Cortex-
M4
FPU Exception
Handler
Quick Facts
What?
FPU exception handler allows user defined handling
of FPU exceptions.
Why?
Proper handling of exceptions is crucial in many ap-
plications.
How?
The FPU exception handler monitors status flags
from the FPU and issues an interrupt when excep-
tions occur.
34.1 Functional Description
The Floating Point Unit, FPU, included in the Cortex-M4 has a set of status flags indicating mathematical errors that cause floating-point
exceptions. Available status flags are:
• FPIOC - FPU invalid operation.
• FPDZC - FPU divide-by-zero exception.
• FPUFC - FPU underflow exception.
• FPOFC - FPU overflow exception.
• FPIDC - FPU input denormal exception.
• FPIXC - FPU inexact exception.
Refer to the ARM Cortex-M4 Devices Generic User Guide for more information about the FPU status flags. The FPU exception handler,
FPUEH, monitors these status flags and sets the corresponding interrupt flag in FPUEH_IF when they are asserted. An interrupt re-
quest will be set if the corresponding bit in FPUEH_IEN is set. The interrupt flags can also be set and cleared using the FPUEH_IFS
and FPUEH_IFC registers, respectively.
Note: Before the FPUEH interrupt flags can be cleared, the corresponding status flag in the FPU has to be cleared. Refer to ARM Cor-
tex-M4 Devices Generic User Guide for information on how to do this.
34.2 Register Map
The offset register address is relative to the registers base address.
Offset Name Type Description
0x000 FPUEH_IF RInterrupt Flag Register
0x004 FPUEH_IFS W1 Interrupt Flag Set Register
0x008 FPUEH_IFC (R)W1 Interrupt Flag Clear Register
0x00C FPUEH_IEN RW Interrupt Enable Register
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34.3 Register Description
34.3.1 FPUEH_IF - Interrupt Flag Register
Offset Bit Position
0x000
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
16
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
Reset
0
0
0
0
0
0
Access
R
R
R
R
R
R
Name
FPIXC
FPIDC
FPOFC
FPUFC
FPDZC
FPIOC
Bit Name Reset Access Description
31:6 Reserved To ensure compatibility with future devices, always write bits to 0. More information in 2.1 Conven-
tions.
5 FPIXC 0 R FPU inexact exception
Set upon FPU inexact exception
4 FPIDC 0 R FPU input denormal exception
Set upon FPU input denormal exception
3 FPOFC 0 R FPU overflow exception
Set upon FPU overflow exception
2 FPUFC 0 R FPU underflow exception
Set upon FPU underflow exception
1 FPDZC 0 R FPU divide-by-zero exception
Set upon FPU divide-by-zero exception
0 FPIOC 0 R FPU invalid operation
Set upon FPU invalid operation
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34.3.2 FPUEH_IFS - Interrupt Flag Set Register
Offset Bit Position
0x004
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
16
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
Reset
0
0
0
0
0
0
Access
W1
W1
W1
W1
W1
W1
Name
FPIXC
FPIDC
FPOFC
FPUFC
FPDZC
FPIOC
Bit Name Reset Access Description
31:6 Reserved To ensure compatibility with future devices, always write bits to 0. More information in 2.1 Conven-
tions.
5 FPIXC 0 W1 Set FPIXC Interrupt Flag
Write 1 to set the FPIXC interrupt flag
4 FPIDC 0 W1 Set FPIDC Interrupt Flag
Write 1 to set the FPIDC interrupt flag
3 FPOFC 0 W1 Set FPOFC Interrupt Flag
Write 1 to set the FPOFC interrupt flag
2 FPUFC 0 W1 Set FPUFC Interrupt Flag
Write 1 to set the FPUFC interrupt flag
1 FPDZC 0 W1 Set FPDZC Interrupt Flag
Write 1 to set the FPDZC interrupt flag
0 FPIOC 0 W1 Set FPIOC Interrupt Flag
Write 1 to set the FPIOC interrupt flag
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34.3.3 FPUEH_IFC - Interrupt Flag Clear Register
Offset Bit Position
0x008
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
16
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
Reset
0
0
0
0
0
0
Access
(R)W1
(R)W1
(R)W1
(R)W1
(R)W1
(R)W1
Name
FPIXC
FPIDC
FPOFC
FPUFC
FPDZC
FPIOC
Bit Name Reset Access Description
31:6 Reserved To ensure compatibility with future devices, always write bits to 0. More information in 2.1 Conven-
tions.
5 FPIXC 0 (R)W1 Clear FPIXC Interrupt Flag
Write 1 to clear the FPIXC interrupt flag
4 FPIDC 0 (R)W1 Clear FPIDC Interrupt Flag
Write 1 to clear the FPIDC interrupt flag
3 FPOFC 0 (R)W1 Clear FPOFC Interrupt Flag
Write 1 to clear the FPOFC interrupt flag
2 FPUFC 0 (R)W1 Clear FPUFC Interrupt Flag
Write 1 to clear the FPUFC interrupt flag
1 FPDZC 0 (R)W1 Clear FPDZC Interrupt Flag
Write 1 to clear the FPDZC interrupt flag
0 FPIOC 0 (R)W1 Clear FPIOC Interrupt Flag
Write 1 to clear the FPIOC interrupt flag
EFM32WG Reference Manual
FPUEH - Floating Point Unit Exception Handler
silabs.com | Building a more connected world. Rev. 1.1 | 1055
34.3.4 FPUEH_IEN - Interrupt Enable Register
Offset Bit Position
0x00C
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
16
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
Reset
0
0
0
0
0
0
Access
RW
RW
RW
RW
RW
RW
Name
FPIXC
FPIDC
FPOFC
FPUFC
FPDZC
FPIOC
Bit Name Reset Access Description
31:6 Reserved To ensure compatibility with future devices, always write bits to 0. More information in 2.1 Conven-
tions.
5 FPIXC 0 RW FPIXC Interrupt Enable
Enable/disable the FPIXC interrupt
4 FPIDC 0 RW FPIDC Interrupt Enable
Enable/disable the FPIDC interrupt
3 FPOFC 0 RW FPOFC Interrupt Enable
Enable/disable the FPOFC interrupt
2 FPUFC 0 RW FPUFC Interrupt Enable
Enable/disable the FPUFC interrupt
1 FPDZC 0 RW FPDZC Interrupt Enable
Enable/disable the FPDZC interrupt
0 FPIOC 0 RW FPIOC Interrupt Enable
Enable/disable the FPIOC interrupt
EFM32WG Reference Manual
FPUEH - Floating Point Unit Exception Handler
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35. Revision History
35.1 Revision 1.10
January 31, 2017
Updated formatting.
Removed mention of 20 mV hysteresis in 27. VCMP - Voltage Comparator, since this value can vary from 20 mV and is specified in the
device data sheet.
Removed the Internal Data Flow sections from 15.4.4.2.2.11 Generic Isochronous OUT Data Transfers Using Periodic Transfer Inter-
rupt Feature and 15.4.4.2.3.14 Generic Periodic IN Data Transfers Using the Periodic Transfer Interrupt Feature.
35.2 Revision 1.00
July 2nd, 2014
Removed "Preliminary" markings.
Updated block diagram.
Updated current numbers and voltage supply range.
Moved chapter "Device Revision" to section 3.
35.3 Revision 0.60
August 29th, 2013
Updated LETIMER Async Support in Reflex Producers table.
Updated the I2C Clock Mode table and added the Maximum Data Hold Time formula.
Added the minimum HFPERCLK requirement for I2C Slave Operation.
Added a new register access type RW1H.
Updated RMU Reset Cause Register Interpretation table.
Updated the register description of CMU_CTRL.
Updated CMU_CALCNT description.
Updated DMA_CHENC register description.
Updated description of number of wait-states for Immediate Synchronization.
Updated description of the Excite Phase timing in LESENSE.
Updated the LETIMER PRS description.
Updated OPAMP description.
Updated the EM4 with RTC and Data Retention with BURTC description.
Added LPFMODE recommendation for the ADC Input Filtering.
Updated the LETIMER description for usage in EM3.
Updated the RTC description for usage in EM3.
Updated WRITEONCE bitfield description in MSC_WRITECMD register.
Updated the MSC_TIMEBASE register description.
Updated the DMA and USB DMA access description.
Updated trademark, disclaimer and contact information.
Other minor corrections.
EFM32WG Reference Manual
Revision History
silabs.com | Building a more connected world. Rev. 1.1 | 1057
35.4 Revision 0.51
May 10th, 2013
Fixed missing "MHz" in relation to the core clock frequency.
35.5 Revision 0.50
April 26th, 2013
Initial preliminary revision.
EFM32WG Reference Manual
Revision History
silabs.com | Building a more connected world. Rev. 1.1 | 1058
36. Abbreviations
This section lists abbreviations used in this document.
Table 36.1. Abbreviations
Abbreviation Description
ACMP Analog Comparator
ADC Analog to Digital Converter
AHB AMBA Advanced High-performance Bus. AMBA is short for "Advanced Microcontroller Bus Architecture".
APB AMBA Advanced Peripheral Bus. AMBA is short for "Advanced Microcontroller Bus Architecture".
ALE Address Latch Enable
AUXHFRCO Auxiliary High Frequency RC Oscillator.
CC Compare / Capture
CLK Clock
CMD Command
CMU Clock Management Unit
CTRL Control
DAC Digital to Analog Converter
DBG Debug
DMA Direct Memory Access
DRD Dual Role Device
DTI Dead Time Insertion
EBI External Bus Interface
EFM Energy Friendly Microcontroller
EM Energy Mode
EM0 Energy Mode 0 (also called active mode)
EM1 to EM4 Energy Mode 1 to Energy Mode 4 (also called low energy modes)
EMU Energy Management Unit
ENOB Effective Number of Bits
FS Full-speed
GPIO General Purpose Input / Output
HFRCO High Frequency RC Oscillator
HFXO High Frequency Crystal Oscillator
HW Hardware
I2C Inter-Integrated Circuit interface
LCD Liquid Crystal Display
LESENSE Low Energy Sensor Interface
LETIMER Low Energy Timer
EFM32WG Reference Manual
Abbreviations
silabs.com | Building a more connected world. Rev. 1.1 | 1059
Abbreviation Description
LEUART Low Energy Universal Asynchronous Receiver Transmitter
LFRCO Low Frequency RC Oscillator
LFXO Low Frequency Crystal Oscillator
LS Low-speed
MAC Media Access Controller
NVIC Nested Vector Interrupt Controller
OPA/OPAMP Operational Amplifier
OSR Oversampling Ratio
OTG On-the-go
PCNT Pulse Counter
PGA Programmable Gain Array
PHY Physical Layer
PRS Peripheral Reflex System
PSRR Power Supply Rejection Ratio
PWM Pulse Width Modulation
RC Resistance and Capacitance
RMU Reset Management Unit
RTC Real Time Clock
SAR Successive Approximation Register
SOF Start of Frame
SPI Serial Peripheral Interface
SW Software
THD Total Harmonic Distortion
UART Universal Asynchronous Receiver Transmitter
USART Universal Synchronous Asynchronous Receiver Transmitter
USB Universal Serial Bus
VCMP Voltage supply Comparator
WDOG Watchdog timer
XTAL Crystal
EFM32WG Reference Manual
Abbreviations
silabs.com | Building a more connected world. Rev. 1.1 | 1060
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