Datenblatt für CSD17551Q3A von Texas Instruments

N w TEXAS INSTRUMENTS
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0 2 4 6 8 10 12
VGS - Gate-to- Source Voltage (V)
RDS(on) - On-State Resistance (mΩ)
TC = 25°C Id = 11A
TC = 125ºC Id = 11A
G001
0
2
4
6
8
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0 3 6 9 12 15
Qg - Gate Charge (nC)
VGS - Gate-to-Source Voltage (V)
ID = 11A
VDS =15V
G001
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P0093-01
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CSD17551Q3A
SLPS386B –SEPTEMBER 2012–REVISED JANUARY 2016
CSD17551Q3A 30-V N-Channel NexFET™ Power MOSFETs
1 Features Product Summary
1• Ultra-Low Qgand Qgd TA= 25°C TYPICAL VALUE UNIT
• Low Thermal Resistance VDS Drain-to-Source Voltage 30 V
• Avalanche Rated QgGate Charge Total (4.5 V) 6.0 nC
Qgd Gate Charge Gate-to-Drain 1.5 nC
• Pb Free
VGS = 4.5 V 9.6 mΩ
• RoHS Compliant RDS(on) Drain-to-Source On Resistance VGS = 10 V 7.8 mΩ
• Halogen Free VGS(th) Threshold Voltage 1.6 V
• SON 3.3 mm × 3.3 mm Plastic Package
Ordering Information(1)
2 Applications DEVICE QTY MEDIA PACKAGE SHIP
• Point-of-Load Synchronous Buck in Networking, CSD17551Q3A 2500 13-Inch Reel SON Tape and
3.3 mm × 3.3 mm
Telecom, and Computing Systems Reel
CSD17551Q3AT 250 7-Inch Reel Plastic Package
• Optimized for Control FET Applications (1) For all available packages, see the orderable addendum at
the end of the data sheet.
3 Description
This 30 V, 7.8 mΩ, 3.3 mm × 3.3 mm NexFET™ Absolute Maximum Ratings
power MOSFET is designed to minimize losses in TA= 25°C unless otherwise stated VALUE UNIT
power conversion applications. VDS Drain-to-Source Voltage 30 V
VGS Gate-to-Source Voltage ±20 V
Top View Continuous Drain Current, TC= 25°C 48 A
IDContinuous Drain Current, Silicon Limited 48 A
Continuous Drain Current, TA= 25°C(1) 12 A
IDM Pulsed Drain Current, TA= 25°C(2) 71 A
PDPower Dissipation(1) 2.6 W
TJ, Operating Junction Temperature, –55 to 150 °C
Tstg Storage Temperature
Avalanche Energy, single pulse
EAS 31 mJ
ID= 25 A, L = 0.1 mH, RG= 25 Ω
(1) Typical RθJA = 48°C/W on a 1 inch2(6.45 cm2),
SPACE 2 oz. (0.071 mm thick) Cu pad on a 0.06 inch (1.52 mm) thick
FR4 PCB.
SPACE (2) Pulse duration ≤300 μs, duty cycle ≤2%
RDS(on) vs VGS Gate Charge
1
An IMPORTANT NOTICE at the end of this data sheet addresses availability, warranty, changes, use in safety-critical applications,
intellectual property matters and other important disclaimers. PRODUCTION DATA.
l TEXAS INSTRUMENTS
CSD17551Q3A
SLPS386B –SEPTEMBER 2012–REVISED JANUARY 2016
www.ti.com
Table of Contents
6.1 Community Resources.............................................. 7
1 Features.................................................................. 16.2 Trademarks............................................................... 7
2 Applications ........................................................... 16.3 Electrostatic Discharge Caution................................ 7
3 Description ............................................................. 16.4 Glossary.................................................................... 7
4 Revision History..................................................... 27 Mechanical, Packaging, and Orderable
5 Specifications......................................................... 3Information ............................................................. 8
5.1 Electrical Characteristics........................................... 37.1 Q3A Package Dimensions........................................ 8
5.2 Thermal Information.................................................. 37.2 Q3A Recommended PCB Pattern ............................ 9
5.3 Typical MOSFET Characteristics.............................. 47.3 Q3A Recommended Stencil Pattern......................... 9
6 Device and Documentation Support.................... 77.4 Q3A Tape and Reel Information ............................. 10
4 Revision History
NOTE: Page numbers for previous revisions may differ from page numbers in the current version.
Changes from Revision A (June 2014) to Revision B Page
• Enhanced Description text. .................................................................................................................................................... 1
• Added Community Resources section .................................................................................................................................. 7
• Updated package drawing. .................................................................................................................................................... 8
• Updated PCB drawing. .......................................................................................................................................................... 9
• Updated Stencil Pattern drawing. .......................................................................................................................................... 9
Changes from Original (September 2012) to Revision A Page
• Changed "Pb-Free terminal plating" feature to state "Pb Free". ........................................................................................... 1
• Updated package dimensions. .............................................................................................................................................. 8
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SLPS386B –SEPTEMBER 2012–REVISED JANUARY 2016
5 Specifications
5.1 Electrical Characteristics
(TA= 25°C unless otherwise stated)
PARAMETER TEST CONDITIONS MIN TYP MAX UNIT
STATIC CHARACTERISTICS
BVDSS Drain-to-source voltage VGS = 0 V, ID= 250 μA 30 V
IDSS Drain-to-source leakage current VGS = 0 V, VDS = 24 V 1 μA
IGSS Gate-to-source leakage current VDS = 0V, VGS = 20 V 100 nA
VGS(th) Gate-to-source threshold voltage VDS = VGS, ID= 250 μA 1.1 1.6 2.1 V
VGS = 4.5 V, ID= 11 A 9.6 11.8 mΩ
RDS(on) Drain-to-source on-resistance VGS = 10 V, ID= 11 A 7.8 9 mΩ
gfs Transconductance VDS = 15 V, ID= 11 A 101 S
DYNAMIC CHARACTERISTICS
Ciss Input capacitance 1050 1370 pF
Coss Output capacitance VGS = 0 V, VDS = 15 V, ƒ = 1 MHz 244 317 pF
Crss Reverse transfer capacitance 24 31 pF
RGSeries gate resistance 1.5 3 Ω
QgGate charge total (4.5 V) 6 7.8 nC
Qgd Gate charge gate to drain 1.5 nC
VDS = 15 V, ID= 11 A
Qgs Gate charge gate to source 2.3 nC
Qg(th) Gate charge at Vth 1.4 nC
Qoss Output charge VDS = 15 V, VGS = 0 V 7.4 nC
td(on) Turn on delay time 8 ns
trRise time 24 ns
VDS = 15 V, VGS = 4.5 V,
IDS = 11 A, RG= 2 Ω
td(off) Turn off delay time 12 ns
tfFall time 3.4 ns
DIODE CHARACTERISTICS
VSD Diode forward voltage ISD = 11 A, VGS = 0 V 0.8 1 V
Qrr Reverse recovery charge 13 nC
VDS= 13.5 V, IF= 11 A,
di/dt = 300 A/μs
trr Reverse recovery time 14 ns
5.2 Thermal Information
(TA= 25°C unless otherwise stated)
THERMAL METRIC MIN TYP MAX UNIT
RθJC Junction-to-case thermal resistance(1) 3.9 °C/W
RθJA Junction-to-ambient thermal resistance (1)(2) 60 °C/W
(1) RθJC is determined with the device mounted on a 1 inch2(6.45 cm2), 2 oz. (0.071 mm thick) Cu pad on a 1.5 inches × 1.5 inches
(3.81 cm × 3.81 cm), 0.06 inch (1.52 mm) thick FR4 PCB. RθJC is specified by design, whereas RθJA is determined by the user’s board
design.
(2) Device mounted on FR4 material with 1 inch2(6.45 cm2), 2 oz. (0.071 mm thick) Cu.
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l TEXAS INSTRUMENTS O GATE Source 0 am Source E E 1mm 3 DRAIN 1n — 5mg: Pulse — 2% — m — 5% on Duty cycle =th L 0.0I a—xZ—> Typ Rm“: 144ch 0700‘ AT, = P ' z».JA - mm, ZIUJA] - Normallzlfl Thor-mm Impndancl 0,0001 [[001 Ill" 01 I lo 100 1000 v, , Pulse Damion (s)
GATE Source
DRAIN
M0161-01
GATE Source
DRAIN
M0161-02
CSD17551Q3A
SLPS386B –SEPTEMBER 2012–REVISED JANUARY 2016
www.ti.com
Max RθJA = 60°C/W Max RθJA = 144°C/W
when mounted on when mounted on a
1 inch2(6.45 cm2) of minimum pad area of 2
2 oz. (0.071 mm thick) oz. (0.071 mm thick)
Cu. Cu.
5.3 Typical MOSFET Characteristics
(TA= 25°C unless otherwise stated)
Figure 1. Transient Thermal Impedance
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SLPS386B –SEPTEMBER 2012–REVISED JANUARY 2016
Typical MOSFET Characteristics (continued)
(TA= 25°C unless otherwise stated)
Figure 2. Saturation Characteristics Figure 3. Transfer Characteristics
Figure 4. Gate Charge Figure 5. Capacitance
Figure 6. Threshold Voltage vs Temperature Figure 7. On-State Resistance vs Gate-to-Source Voltage
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SLPS386B –SEPTEMBER 2012–REVISED JANUARY 2016
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Typical MOSFET Characteristics (continued)
(TA= 25°C unless otherwise stated)
Figure 8. Normalized On-State Resistance vs Temperature Figure 9. Typical Diode Forward Voltage
Figure 10. Maximum Safe Operating Area Figure 11. Single Pulse Unclamped Inductive Switching
Figure 12. Maximum Drain Current vs Temperature
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SLPS386B –SEPTEMBER 2012–REVISED JANUARY 2016
6 Device and Documentation Support
6.1 Community Resources
The following links connect to TI community resources. Linked contents are provided "AS IS" by the respective
contributors. They do not constitute TI specifications and do not necessarily reflect TI's views; see TI's Terms of
Use.
TI E2E™ Online Community TI's Engineer-to-Engineer (E2E) Community. Created to foster collaboration
among engineers. At e2e.ti.com, you can ask questions, share knowledge, explore ideas and help
solve problems with fellow engineers.
Design Support TI's Design Support Quickly find helpful E2E forums along with design support tools and
contact information for technical support.
6.2 Trademarks
NexFET, E2E are trademarks of Texas Instruments.
All other trademarks are the property of their respective owners.
6.3 Electrostatic Discharge Caution
These devices have limited built-in ESD protection. The leads should be shorted together or the device placed in conductive foam
during storage or handling to prevent electrostatic damage to the MOS gates.
6.4 Glossary
SLYZ022 —TI Glossary.
This glossary lists and explains terms, acronyms, and definitions.
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‘5‘ TEXAS INSTRUMENTS
C
TYP
3.5
3.1
2X 0.15 MAX
0.9 MAX
0.05
0.00
(0.2)
1.74±0.1
2.45±0.1
0.565±0.1
4X 0.52
0.32
4X 0.55
0.25
0.65 TYP
2X 1.95
8X 0.35
0.25
(0.15) TYP
2X (0.2)
4X 1.45
B3.1
2.9 A
3.25
3.05
4222499/A 12/2015
9
PIN 1 INDEX AREA
SEATING PLANE
0.1 C B A
0.05 C
2X
NOTE 4
EXPOSED THERMAL PAD
NOTE 3
1
45
8
CSD17551Q3A
SLPS386B –SEPTEMBER 2012–REVISED JANUARY 2016
www.ti.com
7 Mechanical, Packaging, and Orderable Information
The following pages include mechanical packaging and orderable information. This information is the most
current data available for the designated devices. This data is subject to change without notice and revision of
this document. For browser-based versions of this data sheet, refer to the left-hand navigation.
7.1 Q3A Package Dimensions
1. All linear dimensions are in millimeters. Any dimensions in parenthesis are for reference only. Dimensioning
and tolerancing per ASME Y14.5M.
2. This drawing is subject to change without notice.
3. The package thermal pad must be soldered to the printed circuit board for thermal and mechanical
performance.
4. Metalized features are supplier options and may not be on the package.
5. All dimensions do not include mold flash or protrusions.
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*9 TEXAS INSTRUMENTS
(3.1)
4X 0.705
4X 1.125
(R ) TYP0.05
8X (0.6)
8X (0.3)
6X (0.65)
(0.208)
(0.905)
(0.663)
(1.325)
SYMM
SOLDER MASK EDGE
PKG
1
45
8
9
METAL
TYP
4X (0.6)
4X (0.3)
(1.775)
(2.45)
0.05 MIN
ALL SIDES
3X (0.65) 3X (0.65)
(0.207)
(0.975)
TYP
(R )
TYP
0.05
(0.245)
(0.905)
TYP
(R ) TYP0.05
(1.55)
(0.56)
(0.635)
TYP
( ) VIA
TYP
0.2
4X (0.3)
LAND PATTERN EXAMPLE
SYMM
SOLDER MASK
OPENING
METAL UNDER
SOLDER MASK
1
45
8
9
PKG
CSD17551Q3A
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SLPS386B –SEPTEMBER 2012–REVISED JANUARY 2016
7.2 Q3A Recommended PCB Pattern
1. This package is designed to be soldered to a thermal pad on the board. For more information, see the
QFN/SON PCB Attachment application report, SLUA271.
2. Vias are optional depending on application, refer to device data sheet. If some or all are implemented,
recommended via locations are shown.
text added for spacing
For recommended circuit layout for PCB designs, see application note SLPA005 –Reducing Ringing Through
PCB Layout Techniques.
7.3 Q3A Recommended Stencil Pattern
1. Laser cutting apertures with trapezoidal walls and rounded corners may offer better paste release. IPC-7525
may have alternate design recommendations.
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4.00 ±0.10 (See Note 1) 2.00 ±0.05
3.60
3.60
1.30
1.75 ±0.10
M0144-01
8.00 ±0.10
12.00 +0.30
–0.10
5.50 ±0.05
Ø 1.50 +0.10
–0.00
CSD17551Q3A
SLPS386B –SEPTEMBER 2012–REVISED JANUARY 2016
www.ti.com
7.4 Q3A Tape and Reel Information
Notes: 1. 10-sprocket hole-pitch cumulative tolerance ±0.2
2. Camber not to exceed 1 mm in 100 mm, noncumulative over 250 mm
3. Material: black static-dissipative polystyrene
4. All dimensions are in mm, unless otherwise specified.
5. Thickness: 0.30 ±0.05 mm
6. MSL1 260°C (IR and convection) PbF-reflow compatible
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I TEXAS INSTRUMENTS Samples
PACKAGE OPTION ADDENDUM
www.ti.com 10-Dec-2020
Addendum-Page 1
PACKAGING INFORMATION
Orderable Device Status
(1)
Package Type Package
Drawing Pins Package
Qty Eco Plan
(2)
Lead finish/
Ball material
(6)
MSL Peak Temp
(3)
Op Temp (°C) Device Marking
(4/5)
Samples
CSD17551Q3A ACTIVE VSONP DNH 8 2500 RoHS & Green SN Level-1-260C-UNLIM -55 to 150 17551
(1) The marketing status values are defined as follows:
ACTIVE: Product device recommended for new designs.
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design.
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.
OBSOLETE: TI has discontinued the production of the device.
(2) RoHS: TI defines "RoHS" to mean semiconductor products that are compliant with the current EU RoHS requirements for all 10 RoHS substances, including the requirement that RoHS substance
do not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, "RoHS" products are suitable for use in specified lead-free processes. TI may
reference these types of products as "Pb-Free".
RoHS Exempt: TI defines "RoHS Exempt" to mean products that contain lead but are compliant with EU RoHS pursuant to a specific EU RoHS exemption.
Green: TI defines "Green" to mean the content of Chlorine (Cl) and Bromine (Br) based flame retardants meet JS709B low halogen requirements of <=1000ppm threshold. Antimony trioxide based
flame retardants must also meet the <=1000ppm threshold requirement.
(3) MSL, Peak Temp. - The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature.
(4) There may be additional marking, which relates to the logo, the lot trace code information, or the environmental category on the device.
(5) Multiple Device Markings will be inside parentheses. Only one Device Marking contained in parentheses and separated by a "~" will appear on a device. If a line is indented then it is a continuation
of the previous line and the two combined represent the entire Device Marking for that device.
(6) Lead finish/Ball material - Orderable Devices may have multiple material finish options. Finish options are separated by a vertical ruled line. Lead finish/Ball material values may wrap to two
lines if the finish value exceeds the maximum column width.
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