Datenblatt für SI1330EDL von Vishay Siliconix

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Vishay Siliconix

Si1330EDL

Document Number: 72861

S10-0721-Rev. B, 29-Mar-10

www.vishay.com

N-Channel 60 V (D-S) MOSFET

FEATURES

• Halogen-free According to IEC 61249-2-21

Definition

• TrenchFET® Power MOSFET

• ESD Protected: 2000 V

• Compliant to RoHS Directive 2002/95/EC

APPLICATIONS

• P-Channel Driver

- Notebook PC

- Servers

PRODUCT SUMMARY

VDS (V) RDS(on) (Ω)I

D (A)

2.5 at VGS = 10 V 0.25

3 at VGS = 4.5 V 0.23

8 at VGS = 3 V 0.05

SOT-323

SC-70 (3-LEADS)

Top V i ew

Marking Code

KD XX

Lot Traceability

and Date Code

Part # Code

Ordering Information: Si1330EDL-T1-E3 (Lead (Pb)-free)

Si1330EDL-T1-GE3 (Lead (Pb)-free and Halogen-free)

Notes:

a. Surface mounted on 1" x 1" FR4 board.

ABSOLUTE MAXIMUM RATINGS TA = 25 °C, unless otherwise noted

Parameter Symbol 5 s Steady State Unit

Drain-Source Voltage VDS 60 V

Gate-Source Voltage VGS ± 20

Continuous Drain Current (TJ = 150 °C)aTA = 25 °C ID

0.25 0.24

TA = 70 °C 0.2 0.19

Pulsed Drain Current IDM 1.0

Continuous Source Current (Diode Conduction)aIS0.26 0.23

Maximum Power DissipationaTA = 25 °C PD

0.31 0.28 W

TA = 70 °C 0.20 0.18

Operating Junction and Storage Temperature Range TJ, Tstg - 55 to 150 °C

THERMAL RESISTANCE RATINGS

Parameter Symbol Typical Maximum Unit

Maximum Junction-to-Ambientat ≤ 5 s RthJA

355 400

°C/WSteady State 380 450

Maximum Junction-to-Foot (Drain) Steady State RthJF 285 340

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Document Number: 72861

S10-0721-Rev. B, 29-Mar-10

Vishay Siliconix

Si1330EDL

Notes:

a. Pulse test: PW ≤ 300 µs, duty cycle ≤ 2 %.

b. Guaranteed by design, not subject to production testing.

Stresses beyond those listed under “Absolute Maximum Ratings” may cause permanent damage to the device. These are stress ratings only, and functional operation

of the device at these or any other conditions beyond those indicated in the operational sections of the specifications is not implied. Exposure to absolute maximum

rating conditions for extended periods may affect device reliability.

TYPICAL CHARACTERISTICS 25 °C, unless otherwise noted

SPECIFICATIONS TJ = 25 °C, unless otherwise noteda

Parameter Symbol Test Conditions

Limits

Unit Min. Typ. Max.

Static

Drain-Source Breakdown Voltage VDS VGS = 0 V, ID = 10 µA 60 V

Gate-Threshold Voltage VGS(th) VDS = VGS, ID = 250 µA 1 2.0 2.5

Gate-Body Leakage IGSS VDS = 0 V, VGS = ± 10 V ± 1

µA

Zero Gate Voltage Drain Current IDSS

VDS = 60 V, VGS = 0 V 1

VDS = 60 V, VGS = 0 V, TJ = 55 °C 10

On-State Drain CurrentbID(on)

VGS = 10 V, VDS = 7.5 V 0.5

AVGS = 4.5 V, VDS = 10 V 0.4

VGS = 3 V, VDS = 10 V 0.05

Drain-Source On-ResistancebRDS(on)

VGS = 10 V, ID = 0.25 A 1.0 2.5

ΩVGS = 4.5 V, ID = 0.2 A 1.4 3

VGS = 3 V, ID = 0.025 A 3.0 8

Forward Transconductancebgfs VDS = 10 V, ID = 0.25 A 350 mS

Diode Forward Voltage VSD IS = 0.23 A, VGS = 0 V 0.83 1.2 V

Dynamicb

Total Gate Charge Qg

VDS = 10 V, VGS = 4.5 V

ID ≅ 0.25 A

0.4 0.6

nCGate-Source Charge Qgs 0.11

Gate-Drain Charge Qgd 0.15

Gate Resistance Rg173 Ω

Tur n - On T ime td(on)

VDD = 30 V, RL = 150 Ω

ID ≅ 0.2 A, VGEN = 10 V

Rg = 10 Ω

3.8 10

tr4.8 15

Turn-Off Time td(off) 12.8 20

tf9.6 15

Output Characteristics

0.0

0.2

0.4

0.6

0.8

1.0

012345

VDS

- Drain-to-Source Voltage (V)

- Drain Current (A)ID

VGS = 10 V, 7 V

3 V

5 V

4 V

6 V

Transfer Characteristics

012345

VGS

- Gate-to-Source Voltage (V)

- Drain Current (A)ID

TJ = - 55 °C

125 °C

25 °C

1.0

0.8

0.6

0.2

0.4

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Document Number: 72861

S10-0721-Rev. B, 29-Mar-10

www.vishay.com

Vishay Siliconix

Si1330EDL

TYPICAL CHARACTERISTICS 25 °C, unless otherwise noted

On-Resistance vs. Drain Current

On-Resistance vs. Junction Temperature

On-Resistance vs. Gate-Source Voltage

0.0

0.5

1.0

1.5

2.0

2.5

3.0

3.5

4.0

0.0 0.2 0.4 0.6 0.8 1.0

ID- Drain Current (mA)

VGS = 4.5 V

VGS = 10 V

- On-Resistance (Ω)RDS(on)

0.0

0.4

0.8

1.2

1.6

2.0

- 50 - 25 0 25 50 75 100 125 150

- Junction Temperature (°C)

VGS = 10 V at 250 mA

VGS = 4.5 V

at 200 mA

RDS(on) - On-Resistance

(Normalized)

0246810

VGS

- Gate-to-Source Voltage (V)

ID = 200 mA

- On-Resistance (Ω)RDS(on)

Gate Charge

Source-Drain Diode Forward Voltage

Threshold Voltage Variance over Temperature

0.0 0.1 0.2 0.3 0.4 0.5 0.6

VDS = 10 V

ID = 250 mA

- Gate-to-Source Voltage (V)

- Total Gate Charge (nC)

VGS

1.2 1.5

100

1000

0 0.3 0.6 0.9

TJ = 25 °C

TJ = 125 °C

VSD

- Source-to-Drain Voltage (V)

- Source Current (A)IS

TJ = - 55 °C

VGS = 0 V

- 0.8

- 0.6

- 0.4

- 0.2

0.0

0.2

0.4

- 50 - 25 0 25 50 75 100 125 150

ID = 250 µA

Variance (V)VGS(th)

TJ - Temperature (°C)

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www.vishay.com

Document Number: 72861

S10-0721-Rev. B, 29-Mar-10

Vishay Siliconix

Si1330EDL

TYPICAL CHARACTERISTICS 25 °C, unless otherwise noted

Vishay Siliconix maintains worldwide manufacturing capability. Products may be manufactured at one of several qualified locations. Reliability data for Silicon

Technology and Package Reliability represent a composite of all qualified locations. For related documents such as package/tape drawings, part marking, and

reliability data, see www.vishay.com/ppg?72861.

Single Pulse Power

Power (W)

Time (s)

1 100 6001010-1

10-2

TA = 25 °C

Safe Operating Area

0.1

0.1 1 10 100

0.001

TA = 25 °C

Single Pulse

0.01

ID(on)

Limited

DS(on)

Limited by R

BVDSS Limited

IDM

Limited

1 ms

10 ms

100 ms

1 s

VDS - Drain-to-Source Voltage (V)

GS > minimum VGS at which RDS(on) is specified

- Drain Current (A)

10 s, D

Normalized Thermal Transient Impedance, Junction-to-Ambient

10-3 10-2 1 10 60010-1

10-4 100

0.1

0.01

0.2

0.1

0.05

0.02

Single Pulse

Duty Cycle = 0.5

Square Wave Pulse Duration (s)

Normalized Effective Transient

Thermal Impedance

1. Duty Cycle, D =

2. Per Unit Base = RthJA = 380 °C/W

3. TJM - TA = PDMZthJA(t)

Notes:

4. Surface Mounted

PDM

Normalized Thermal Transient Impedance, Junction-to-Foot

10-310-211010-1

10-4

0.1

0.01

0.2

0.1

0.05

0.02

Single Pulse

Duty Cycle = 0.5

Square Wave Pulse Duration (s)

Normalized Effective Transient

Thermal Impedance

VISHAY \ _,_ b-- kg J

EE1

A2A

0.08 c

Package Information

Vishay Siliconix

Document Number: 71153

06-Jul-01 www.vishay.com

SCĆ70: 3ĆLEADS

MILLIMETERS INCHES

Dim Min Nom Max Min Nom Max

A0.90 – 1.10 0.035 – 0.043

A1– – 0.10 – – 0.004

A20.80 – 1.00 0.031 – 0.039

b0.25 – 0.40 0.010 – 0.016

c0.10 – 0.25 0.004 – 0.010

D1.80 2.00 2.20 0.071 0.079 0.087

E1.80 2.10 2.40 0.071 0.083 0.094

E11.15 1.25 1.35 0.045 0.049 0.053

e0.65BSC 0.026BSC

e11.20 1.30 1.40 0.047 0.051 0.055

L0.10 0.20 0.30 0.004 0.008 0.012

7_Nom 7_Nom

ECN: S-03946—Rev. C, 09-Jul-01

DWG: 5549

VISHAY a EH @ m |—|_ TIT L._l ,_ G G D D S S SC70-3 SINGLE Uishau Silicunix REU. ﬂ SC70-6 SINGLE Dacumem Numbev 71236 12702003

AN813

Vishay Siliconix

Document Number: 71236

12-Dec-03

www.vishay.com

Single-Channel LITTLE FOOTR SC-70 3-Pin and 6-Pin MOSFET

Recommended Pad Pattern and Thermal Peformance

INTRODUCTION BASIC PAD PATTERNS

This technical note discusses pin-outs, package outlines, pad

patterns, evaluation board layout, and thermal performance

for single-channel LITTLE FOOT power MOSFETs in the

SC-70 package. These new Vishay Siliconix devices are

intended for small-signal applications where a miniaturized

package is needed and low levels of current (around 350 mA)

need to be switched, either directly or by using a level shift

configuration. Vishay provides these single devices with a

range of on-resistance specifications and in both traditional

3-pin and new 6-pin versions. The new 6-pin SC-70 package

enables improved on-resistance values and enhanced

thermal performance compared to the 3-pin package.

PIN-OUT

Figure 1 shows the pin-out description and Pin 1 identification

for the single-channel SC-70 device in both 3-pin and 6-pin

configurations. The pin-out of the 6-pin device allows the use

of four pins as drain leads, which helps to reduce on-resistance

and junction-to-ambient thermal resistance.

SOT-323

SC-70 (3-LEADS)

Top View

SOT-363

SC-70 (6-LEADS)

Top View

FIGURE 1.

For package dimensions see outline drawings:

SC-70 (3-Leads) (http://www.vishay.com/doc?71153)

SC-70 (6-Leads) (http://www.vishay.com/doc?71154)

See Application Note 826, Recommended Minimum Pad

Patterns With Outline Drawing Access for Vishay Siliconix

MOSFETs, (http://www.vishay.com/doc?72286) for the basic

pad layout and dimensions for the 3-pin SC-70 and the 6-pin

SC-70. These pad patterns are sufficient for the low-power

applications for which this package is intended. Increasing the

pad pattern has little effect on thermal resistance for the 3-pin

device, reducing it by only 10% to 15%. But for the 6-pin

device, increasing the pad patterns yields a reduction in

thermal resistance on the order of 35% when using a 1-inch

square with full copper on both sides of the printed circuit board

(PCB). The availability of four drain leads rather than the

traditional single drain lead allows a better thermal path from

the package to the PCB and external environment.

EVALUATION BOARDS FOR THE SINGLE

SC70-3 AND SC70-6

Figure 2 shows the 3-pin and 6-pin SC-70 evaluation boards

(EVB). Both measure 0.6 inches by 0.5 inches. Their copper

pad traces are the same as described in the previous section,

Basic Pad Patterns. Both boards allow interrogation from the

outer pins to 6-pin DIP connections, permitting test sockets to

be used in evaluation testing.

The thermal performance of the single SC-70 has been

measured on the EVB for both the 3-pin and 6-pin devices, the

results shown in Figures 3 and 4. The minimum recommended

footprint on the evaluation board was compared with the

industry standard of 1-inch square FR4 PCB with copper on

both sides of the board.

FIGURE 2.

Front of Board SC70-3 Front of Board SC70-6

Back of Board, SC70-3 and SC70-6

ChipFETrChipFETr

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AN813

Vishay Siliconix

www.vishay.com

Document Number: 71236

12-Dec-03

THERMAL PERFORMANCE

Junction-to-Foot Thermal Resistance

(the Package Performance)

Thermal performance for the 3-pin SC-70 measured as

junction-to-foot thermal resistance is 285_C/W typical,

340_C/W maximum. Junction-to-foot thermal resistance for

the 6-pin SC70-6 is 105_C/W typical, 130_C/W maximum —

a nearly two-thirds reduction compared with the 3-pin device.

The “foot” is the drain lead of the device as it connects with the

body. This improved performance is obtained by the increase

in drain leads from one to four on the 6-pin SC-70. Note that

these numbers are somewhat higher than other LITTLE FOOT

devices due to the limited thermal performance of the Alloy 42

lead-frame compared with a standard copper lead-frame.

Junction-to-Ambient Thermal Resistance

(dependent on PCB size)

The typical RθJAfor the single 3-pin SC-70 is 360_C/W steady

state, compared with 180_C/W for the 6-pin SC-70. Maximum

ratings are 430_C/W for the 3-pin device versus 220_C/W for

the 6-pin device. All figures are based on the 1-inch square

FR4 test board.The following table shows how the thermal

resistance impacts power dissipation for the two different

pin-outs at two different ambient temperatures.

SC-70 (3-PIN)

Room Ambient 25 _CElevated Ambient 60 _C

PD+TJ(max) *TA

RqJA

PD+150oC*25oC

360oCńW

PD+347 mW

PD+TJ(max) *TA

RqJA

PD+150oC*60oC

360oCńW

PD+250 mW

SC-70 (6-PIN)

Room Ambient 25 _CElevated Ambient 60 _C

PD+TJ(max) *TA

RqJA

PD+150oC*25oC

180oCńW

PD+694 mW

PD+TJ(max) *TA

RqJA

PD+150oC*60oC

180oCńW

PD+500 mW

NOTE: Although they are intended for low-power applications,

devices in the 6-pin SC-70 will handle power dissipation in

excess of 0.5 W.

Testing

To aid comparison further, Figures 3 and 4 illustrate

single-channel SC-70 thermal performance on two different

board sizes and two different pad patterns. The results display

the thermal performance out to steady state and produce a

graphic account of the thermal performance variation between

the two packages. The measured steady state values of RθJA

for the single 3-pin and 6-pin SC-70 are as follows:

LITTLE FOOT SC-70

3-Pin 6-Pin

1) Minimum recommended pad pattern

(see Figure 4) on the EVB. 410.31_C/W 329.7_C/W

2) Industry standard 1” square PCB with

maximum copper both sides. 360_C/W 211.8_C/W

The results show that designers can reduce thermal

resistance RθJA on the order of 20% simply by using the 6-pin

device rather than the 3-pin device. In this example, a 80_C/W

reduction was achieved without an increase in board area. If

increasing board size is an option, a further 118_C/W reduction

could be obtained by utilizing a 1-inch square PCB area.

Time (Secs)

FIGURE 3. Comparison of SC70-3 and SC70-6 on EVB

Thermal Resistance (C/W)

400

160

100 1000

240

1010-1

10-2

10-3

10-4

10-5

0.5 in x 0.6 in EVB

3-pin

320

Time (Secs)

FIGURE 4. Comparison of SC70-3 and SC70-6 on 1”

Square FR4 PCB

Thermal Resistance (C/W)

400

160

100 1000

240

1010-1

10-2

10-3

10-4

10-5

1” Square FR4 PCB

320

6-pin

3-pin

6-pin

m Application Note 826 Vishay Siliconix RECOMMENDED MINIMUM PADS FOR 50-70: 3-Lead n 022 (n 559) 09 (2 438) Recommended Mwmmum Pads Dwmensmns m Inches/(mm) shay com 17

Application Note 826

Vishay Siliconix

Document Number: 72601 www.vishay.com

Revision: 21-Jan-08 17

APPLICATION NOTE

RECOMMENDED MINIMUM PADS FOR SC-70: 3-Lead

0.022

(0.559)

0.096

(2.438)

Recommended Minimum Pads

Dimensions in Inches/(mm)

0.025

(0.622)

0.027

(0.686)

0.071

(1.803)

0.045

(1.143)

0.026

(0.648)

Return to Index

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Revision: 08-Feb-17 1Document Number: 91000

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