Datenblatt für SN74AUC1G32YZPR von Texas Instruments

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An IMPORTANT NOTICE at the end of this data sheet addresses availability, warranty, changes, use in safety-critical applications,
intellectual property matters and other important disclaimers. UNLESS OTHERWISE NOTED, this document contains PRODUCTION
DATA.
SN74AUC1G32
SCES377P –SEPTEMBER 2001–REVISED JUNE 2017
SN74AUC1G32 Single 2-Input Positive-OR Gate
1
1 Features
1• Latch-Up Performance Exceeds 100 mA Per
JESD 78, Class II
• ESD Protection Exceeds JESD 22
– 2000-V Human-Body Model (A114-A)
– 1000-V Charged-Device Model (C101)
• Available in the Texas Instruments NanoFree™
Package
• Optimized for 1.8-V Operation and Is 3.6-V I/O
Tolerant to Support Mixed-Mode Signal Operation
• Ioff Partial-Power-Down Mode and Back Drive
Protection
• Sub-1-V Operable
• Max tpd of 2.4 ns at 1.8 V
• Low Power Consumption, 10-μA Maximum ICC
• ±8-mA Output Drive at 1.8 V
2 Applications
• AV Receiver
• Audio Dock: Portable
• Blu-ray Player and Home Theater
• Embedded PC
• MP3 Player/Recorder (Portable Audio)
• Personal Digital Assistant (PDA)
• Power: Telecom/Server AC/DC Supply: Single
Controller: Analog and Digital
• Solid State Drive (SSD): Client and Enterprise
• TV: LCD/Digital and High-Definition (HDTV)
• Tablet: Enterprise
• Video Analytics: Server
• Wireless Headset, Keyboard, and Mouse
3 Description
This single 2-input positive-OR gate is operational at
0.8-V to 2.7-V VCC, but is designed specifically for
1.65-V to 1.95-V VCC operation.
The SN74AUC1G32 device performs the Boolean
function in positive logic.
NanoFree™ package technology is a major
breakthrough in IC packaging concepts, using the die
as the package.
This device is fully specified for partial-power-down
applications using Ioff. The Ioff circuitry disables the
outputs, preventing damaging current backflow
through the device when it is powered down.
For more information about AUC Little Logic devices,
see Applications of Texas Instruments AUC Sub-1-V
Little Logic Devices, SCEA027.
Device Information(1)
PART NUMBER PACKAGE BODY SIZE (NOM)
SN74AUC1G32DBV SOT-23 (5) 2.90 mm × 1.60 mm
SN74AUC1G32DCK SC70 (5) 2.00 mm × 1.25 mm
SN74AUC1G32DRL SOT-5X3 (5) 1.60 mm × 1.20 mm
SN74AUC1G32YZP DSBGA (5) 1.39 mm × 0.89 mm
(1) For all available packages, see the orderable addendum at
the end of the data sheet.
Logic Diagram (Positive Logic)
l TEXAS INSTRUMENTS
2
SN74AUC1G32
SCES377P –SEPTEMBER 2001–REVISED JUNE 2017
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Table of Contents
1 Features.................................................................. 1
2 Applications ........................................................... 1
3 Description ............................................................. 1
4 Revision History..................................................... 2
5 Pin Configuration and Functions......................... 3
6 Specifications......................................................... 4
6.1 Absolute Maximum Ratings ..................................... 4
6.2 ESD Ratings ............................................................ 4
6.3 Recommended Operating Conditions ...................... 4
6.4 Thermal Information.................................................. 5
6.5 Electrical Characteristics........................................... 5
6.6 Switching Characteristics: CL= 15 pF ...................... 5
6.7 Switching Characteristics: CL= 30 pF ...................... 5
6.8 Operating Characteristics.......................................... 6
7 Parameter Measurement Information .................. 7
8 Detailed Description.............................................. 8
8.1 Functional Block Diagram ......................................... 8
8.2 Device Functional Modes.......................................... 8
9 Device and Documentation Support.................... 9
9.1 Documentation Support ........................................... 9
9.2 Receiving Notification of Documentation Updates.... 9
9.3 Community Resources.............................................. 9
9.4 Trademarks............................................................... 9
9.5 Electrostatic Discharge Caution................................ 9
9.6 Glossary.................................................................... 9
10 Mechanical, Packaging, and Orderable
Information ............................................................. 9
4 Revision History
NOTE: Page numbers for previous revisions may differ from page numbers in the current version.
Changes from Revision O (September 2009) to Revision P Page
• Added Application section, Pin Configuration and Functions section, ESD Ratings table, Feature Description
section, Device Functional Modes,Application and Implementation Power Supply Recommendations section,
Layout section, Device and Documentation Support section, and Mechanical, Packaging, and Orderable Information
section. .................................................................................................................................................................................. 1
• Deleted Ordering Information table, see Mechanical, Packaging, and Orderable Information at the end of the data sheet. 1
• Deleted DRY package throughout data sheet........................................................................................................................ 1
Changes from Revision N (September 2001) to Revision O Page
• Updated document to new TI data sheet format - no specification changes. ........................................................................ 1
• Removed Ordering Information. ............................................................................................................................................. 1
‘5‘ TEXAS INSTRUMENTS
34
GND
2
B
Y
1
A5VCC
1 2
C
B
A
Not to scale
GND Y
B
A VCC
2
5
34Y
1
B
GND
AVCC
3
SN74AUC1G32
www.ti.com
SCES377P –SEPTEMBER 2001–REVISED JUNE 2017
Product Folder Links: SN74AUC1G32
Submit Documentation FeedbackCopyright © 2001–2017, Texas Instruments Incorporated
5 Pin Configuration and Functions
DBV Package
SOT-23
Top View
DCK Package
5-Pin SC70
Top View
See mechanical drawings for dimensions.
NC No internal connections
DRL Package
5-Pin SOT-5X3
Top View
YZP Package
5-Pin DSBGA
Bottom View
Pin Functions
PIN
I/O DESCRIPTION
NAME DBV, DCK,
DRL YZP
A 1 A1 I Input A
B 2 B1 I Input B
GND 3 C1 — Ground
VCC 5 A2 — Positive Supply
Y 4 C2 O Output Y
l TEXAS INSTRUMENTS
4
SN74AUC1G32
SCES377P –SEPTEMBER 2001–REVISED JUNE 2017
www.ti.com
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(1) Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. These are stress ratings
only, which do not imply functional operation of the device at these or any other conditions beyond those indicated under Recommended
Operating Conditions. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
(2) The input negative-voltage and output voltage ratings may be exceeded if the input and output current ratings are observed.
6 Specifications
6.1 Absolute Maximum Ratings
over operating free-air temperature range (unless otherwise noted)(1)
MIN MAX UNIT
VCC Supply voltage –0.5 3.6 V
VIInput voltage(2) –0.5 3.6 V
VOVoltage range applied to any output in the high-impedance or power-off state(2) –0.5 3.6 V
VOOutput voltage range(2) –0.5 VCC + 0.5 V
IIK Input clamp current VI< 0 –50 mA
IOK Output clamp current VO< 0 –50 mA
IOContinuous output current ±20 mA
Continuous current through VCC or GND ±100 mA
Tstg Storage temperature –65 150 °C
(1) JEDEC document JEP155 states that 500-V HBM allows safe manufacturing with a standard ESD control process.
(2) JEDEC document JEP157 states that 250-V CDM allows safe manufacturing with a standard ESD control process.
6.2 ESD Ratings
VALUE UNIT
V(ESD) Electrostatic discharge Human body model (HBM), per ANSI/ESDA/JEDEC JS-001(1) ±2000 V
Charged device model (CDM), per JEDEC specification JESD22-C101(2) ±1000
(1) All unused inputs of the device must be held at VCC or GND to ensure proper device operation. See Implications of Slow or Floating
CMOS Inputs, SCBA004.
6.3 Recommended Operating Conditions
See (1)
MIN MAX UNIT
VCC Supply voltage 0.8 2.7 V
VIInput voltage 0 3.6 V
VOOutput voltage 0 VCC V
VIH High-level input voltage
VCC = 0.8 V VCC
VVCC = 1.1 V to 1.95 V 0.65 × VCC
VCC = 2.3 V to 2.7 V 1.7
VIL Low-level input voltage
VCC = 0.8 V 0
VVCC = 1.1 V to 1.95 V 0.35 × VCC
VCC = 2.3 V to 2.7 V 0.7
IOH High-level output current
VCC = 0.8 V –0.7
mA
VCC = 1.1 V –3
VCC = 1.4 V –5
VCC = 1.65 V –8
VCC = 2.3 V –9
IOL Low-level output current
VCC = 0.8 V 0.7
mA
VCC = 1.1 V 3
VCC = 1.4 V 5
VCC = 1.65 V 8
VCC = 2.3 V 9
Δt/Δv Input transition rise or fall rate 20 ns/V
l TEXAS INSTRUMENTS
5
SN74AUC1G32
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Recommended Operating Conditions (continued)
See (1)
MIN MAX UNIT
TAOperating free-air temperature –40 85 °C
(1) For more information about traditional and new thermal metrics, see the Semiconductor and IC Package Thermal Metrics application
report.
6.4 Thermal Information
THERMAL METRIC(1)
SN74AUC1G32
UNITDBV DCK DRL YZP
5 PINS 5 PINS 5 PINS 5 PINS
RθJA Junction-to-ambient thermal resistance 206 252 142 132 °C/W
(1) All typical values are at TA= 25°C.
6.5 Electrical Characteristics
over recommended operating free-air temperature range (unless otherwise noted)
PARAMETER TEST CONDITIONS VCC MIN TYP(1) MAX UNIT
VOH
IOH = –100 µA 0.8 V to 2.7 V VCC – 0.1
V
IOH = –0.7 mA 0.8 V 0.55
IOH = –3 mA 1.1 V 0.8
IOH = –5 mA 1.4 V 1
IOH = –8 mA 1.65 V 1.2
IOH = –9 mA 2.3 V 1.8
VOL
IOL = 100 µA 0.8 V to 2.7 V 0.2
V
IOL = 0.7 mA 0.8 V 0.25
IOL = 3 mA 1.1 V 0.3
IOL = 5 mA 1.4 V 0.4
IOL = 8 mA 1.65 V 0.45
IOL = 9 mA 2.3 V 0.6
IIA or B input VI= VCC or GND 0 to 2.7 V ±5 µA
Ioff VIor VO= 2.7 V 0 ±10 µA
ICC VI= VCC or GND, IO= 0 0.8 V to 2.7 V 10 µA
CiVI= VCC or GND 2.5 V 4 pF
6.6 Switching Characteristics: CL= 15 pF
over recommended operating free-air temperature range, CL= 15 pF (unless otherwise noted) (see Figure 1)
PARAMETER FROM
(INPUT) TO
(OUTPUT)
VCC = 0.8 V VCC = 1.2 V
± 0.1 V VCC = 1.5 V
± 0.1 V VCC = 1.8 V
± 0.15 V VCC = 2.5 V
± 0.2 V UNIT
TYP MIN MAX MIN MAX MIN TYP MAX MIN MAX
tpd A or B Y 4.8 1 3.5 0.6 2.3 0.5 0.9 1.5 0.3 1.4 ns
6.7 Switching Characteristics: CL= 30 pF
over recommended operating free-air temperature range, CL= 30 pF (unless otherwise noted) (see Figure 1)
PARAMETER FROM
(INPUT) TO
(OUTPUT)
VCC = 1.8 V
± 0.15 V VCC = 2.5 V
± 0.2 V UNIT
MIN TYP MAX MIN MAX
tpd A or B Y 0.8 1.4 2.4 0.6 2.1 ns
l TEXAS INSTRUMENTS
6
SN74AUC1G32
SCES377P –SEPTEMBER 2001–REVISED JUNE 2017
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Product Folder Links: SN74AUC1G32
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6.8 Operating Characteristics
TA= 25°C
PARAMETER TEST
CONDITIONS
VCC = 0.8 V VCC = 1.2 V VCC = 1.5 V VCC = 1.8 V VCC = 2.5 V UNIT
TYP TYP TYP TYP TYP
Cpd Power dissipation
capacitance f = 10 MHz 14 14 15 15 20 pF
*9 TEXAS INSTRUMENTS
NOTES: A. C includesprobeandjigcapacitance.
B. Waveform1isforanoutputwithinternalconditionssuchthattheoutputislow,exceptwhendisabledbytheoutputcontrol.
Waveform2isforanoutputwithinternalconditionssuchthattheoutputishigh,exceptwhendisabledbytheoutputcontrol.
C. Allinputpulsesaresuppliedbygeneratorshavingthefollowingcharacteristics:PRR 10MHz,Z =50 ,
slewrate 1V/ns.
D. Theoutputsaremeasuredoneatatime,withonetransitionpermeasurement.
E. t andt arethesameast .
F. t andt arethesameast .
G. t andt arethesameast .
H. Allparametersandwaveformsarenotapplicabletoalldevices.
L
O
PLZ PHZ dis
PZL PZH en
PLH PHL pd
£ W
³
FromOutput
UnderTest
C
(seeNote A)
L
LOADCIRCUIT
S1
2×VCC
Open
GND
RL
RL
t /t
PLH PHL Open
TEST S1
2×VCC
t /t
PLZ PZL
GND
t /t
PHZ PZH
0V
tW
Input
0V
Input
Output
Output
VOLTAGEWAVEFORMS
PROPAGATIONDELAY TIMES
INVERTING ANDNONINVERTINGOUTPUTS
VOLTAGEWAVEFORMS
PULSEDURATION
VCC/2
VCC/2 VCC/2
VCC/2
VOL
VOH
VCC
VCC
VOH
VOL
VCC/2
VCC/2
VCC/2
VCC/2
tPLH tPHL
tPLH
tPHL
th
tsu
DataInput
TimingInput
0V
0V
Output
Waveform1
S1at2×V
(seeNoteB)
CC
Output
Waveform2
S1atGND
(seeNoteB)
VOL
VOH
0V
»0V
Output
Control
VCC/2
VCC/2 VCC/2
VCC/2
VCC/2
VOLTAGEWAVEFORMS
ENABLE ANDDISABLETIMES
LOW- ANDHIGH-LEVEL ENABLING
VOLTAGEWAVEFORMS
SETUP ANDHOLDTIMES
VCC
VCC
VCC
VCC/2
VCC/2
VCC
tPZL tPLZ
tPHZ
tPZH
V – V
OH D
V +V
OL D
0.8V
1.2V 0.1V±
1.5V 0.1V±
1.8V 0.15V±
2.5V 0.2V±
1.8V 0.15V±
2.5V 0.2V±
VCC
2kW
2kW
2kW
2kW
2kW
1kW
500 W
RL
0.1V
0.1V
0.1V
0.15V
0.15V
0.15V
0.15V
VD
CL
15pF
15pF
15pF
15pF
15pF
30pF
30pF
7
SN74AUC1G32
www.ti.com
SCES377P –SEPTEMBER 2001–REVISED JUNE 2017
Product Folder Links: SN74AUC1G32
Submit Documentation FeedbackCopyright © 2001–2017, Texas Instruments Incorporated
7 Parameter Measurement Information
Figure 1. Load Circuit and Voltage Waveforms
l TEXAS INSTRUMENTS
8
SN74AUC1G32
SCES377P –SEPTEMBER 2001–REVISED JUNE 2017
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Product Folder Links: SN74AUC1G32
Submit Documentation Feedback Copyright © 2001–2017, Texas Instruments Incorporated
8 Detailed Description
8.1 Functional Block Diagram
Figure 2. Logic Diagram (Positive Logic)
8.2 Device Functional Modes
Table 1 lists the functional modes of SN74AUC1G32.
Table 1. Function Table
(Each Inverter)
INPUTS OUTPUT
Y
A B
H X H
X H H
L L L
l TEXAS INSTRUMENTS
9
SN74AUC1G32
www.ti.com
SCES377P –SEPTEMBER 2001–REVISED JUNE 2017
Product Folder Links: SN74AUC1G32
Submit Documentation FeedbackCopyright © 2001–2017, Texas Instruments Incorporated
9 Device and Documentation Support
9.1 Documentation Support
9.1.1 Related Documentation
For related documentation see the following:
•Applications of Texas Instruments AUC Sub-1-V Little Logic Devices, SCEA027
•Implications of Slow or Floating CMOS Inputs, SCBA004
9.2 Receiving Notification of Documentation Updates
To receive notification of documentation updates, navigate to the device product folder on ti.com. In the upper
right corner, click on Alert me to register and receive a weekly digest of any product information that has
changed. For change details, review the revision history included in any revised document.
9.3 Community Resources
The following links connect to TI community resources. Linked contents are provided "AS IS" by the respective
contributors. They do not constitute TI specifications and do not necessarily reflect TI's views; see TI's Terms of
Use.
TI E2E™ Online Community TI's Engineer-to-Engineer (E2E) Community. Created to foster collaboration
among engineers. At e2e.ti.com, you can ask questions, share knowledge, explore ideas and help
solve problems with fellow engineers.
Design Support TI's Design Support Quickly find helpful E2E forums along with design support tools and
contact information for technical support.
9.4 Trademarks
NanoFree, E2E are trademarks of Texas Instruments.
All other trademarks are the property of their respective owners.
9.5 Electrostatic Discharge Caution
This integrated circuit can be damaged by ESD. Texas Instruments recommends that all integrated circuits be handled with
appropriate precautions. Failure to observe proper handling and installation procedures can cause damage.
ESD damage can range from subtle performance degradation to complete device failure. Precision integrated circuits may be more
susceptible to damage because very small parametric changes could cause the device not to meet its published specifications.
9.6 Glossary
SLYZ022 —TI Glossary.
This glossary lists and explains terms, acronyms, and definitions.
10 Mechanical, Packaging, and Orderable Information
The following pages include mechanical, packaging, and orderable information. This information is the most
current data available for the designated devices. This data is subject to change without notice and revision of
this document. For browser-based versions of this data sheet, refer to the left-hand navigation.
I TEXAS INSTRUMENTS
PACKAGE OPTION ADDENDUM
www.ti.com 14-Oct-2022
PACKAGING INFORMATION
Orderable Device Status
(1)
Package Type Package
Drawing Pins Package
Qty Eco Plan
(2)
Lead finish/
Ball material
(6)
MSL Peak Temp
(3)
Op Temp (°C) Device Marking
(4/5)
Samples
SN74AUC1G32DBVR ACTIVE SOT-23 DBV 5 3000 RoHS & Green NIPDAU | SN Level-1-260C-UNLIM -40 to 85 (U32F, U32R) Samples
SN74AUC1G32DBVRG4 ACTIVE SOT-23 DBV 5 3000 RoHS & Green NIPDAU Level-1-260C-UNLIM -40 to 85 U32F Samples
SN74AUC1G32DCKR ACTIVE SC70 DCK 5 3000 RoHS & Green NIPDAU Level-1-260C-UNLIM -40 to 85 (UG5, UGF, UGR) Samples
SN74AUC1G32DCKRG4 ACTIVE SC70 DCK 5 3000 RoHS & Green NIPDAU Level-1-260C-UNLIM -40 to 85 (UG5, UGF, UGR) Samples
SN74AUC1G32DRLR ACTIVE SOT-5X3 DRL 5 4000 RoHS & Green NIPDAU | NIPDAUAG Level-1-260C-UNLIM -40 to 85 (UG7, UGR) Samples
SN74AUC1G32YZPR ACTIVE DSBGA YZP 5 3000 RoHS & Green SNAGCU Level-1-260C-UNLIM -40 to 85 UGN Samples
(1) The marketing status values are defined as follows:
ACTIVE: Product device recommended for new designs.
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design.
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.
OBSOLETE: TI has discontinued the production of the device.
(2) RoHS: TI defines "RoHS" to mean semiconductor products that are compliant with the current EU RoHS requirements for all 10 RoHS substances, including the requirement that RoHS substance
do not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, "RoHS" products are suitable for use in specified lead-free processes. TI may
reference these types of products as "Pb-Free".
RoHS Exempt: TI defines "RoHS Exempt" to mean products that contain lead but are compliant with EU RoHS pursuant to a specific EU RoHS exemption.
Green: TI defines "Green" to mean the content of Chlorine (Cl) and Bromine (Br) based flame retardants meet JS709B low halogen requirements of <=1000ppm threshold. Antimony trioxide based
flame retardants must also meet the <=1000ppm threshold requirement.
(3) MSL, Peak Temp. - The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature.
(4) There may be additional marking, which relates to the logo, the lot trace code information, or the environmental category on the device.
(5) Multiple Device Markings will be inside parentheses. Only one Device Marking contained in parentheses and separated by a "~" will appear on a device. If a line is indented then it is a continuation
of the previous line and the two combined represent the entire Device Marking for that device.
(6) Lead finish/Ball material - Orderable Devices may have multiple material finish options. Finish options are separated by a vertical ruled line. Lead finish/Ball material values may wrap to two
lines if the finish value exceeds the maximum column width.
Addendum-Page 1
TEXAS INSTRUMENTS
PACKAGE OPTION ADDENDUM
www.ti.com 14-Oct-2022
Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information
provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and
continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals.
TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited information may not be available for release.
In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI to Customer on an annual basis.
Addendum-Page 2
I TEXAS INSTRUMENTS REEL DIMENSIONS TAPE DIMENSIONS ’ I‘KO '«Pt» Reel DlameIer A0 Dimension designed to accommodate the component Width Bo Dimension designed to accommodate the component Iength K0 Dimension designed to accommodate the component thickness 7 w Overau Wiotn ot the carrier Iape i P1 Pitch between successive cawty centers f T Reel Width (W1) QUADRANT ASSIGNMENTS FOR PIN 1 ORIENTATION IN TAPE DOODOOOD ,,,,,,,,,,, ‘ User Direcllon 0' Feed SprockeI Hoies Pockel Quadrams
TAPE AND REEL INFORMATION
*All dimensions are nominal
Device Package
Type Package
Drawing Pins SPQ Reel
Diameter
(mm)
Reel
Width
W1 (mm)
A0
(mm) B0
(mm) K0
(mm) P1
(mm) W
(mm) Pin1
Quadrant
SN74AUC1G32DBVR SOT-23 DBV 5 3000 178.0 9.0 3.23 3.17 1.37 4.0 8.0 Q3
SN74AUC1G32DBVR SOT-23 DBV 5 3000 180.0 8.4 3.23 3.17 1.37 4.0 8.0 Q3
SN74AUC1G32DBVRG4 SOT-23 DBV 5 3000 178.0 9.0 3.23 3.17 1.37 4.0 8.0 Q3
SN74AUC1G32DCKR SC70 DCK 5 3000 178.0 9.0 2.4 2.5 1.2 4.0 8.0 Q3
SN74AUC1G32DCKR SC70 DCK 5 3000 178.0 9.2 2.4 2.4 1.22 4.0 8.0 Q3
SN74AUC1G32DCKR SC70 DCK 5 3000 180.0 8.4 2.47 2.3 1.25 4.0 8.0 Q3
SN74AUC1G32DRLR SOT-5X3 DRL 5 4000 180.0 8.4 1.98 1.78 0.69 4.0 8.0 Q3
SN74AUC1G32DRLR SOT-5X3 DRL 5 4000 180.0 9.5 1.78 1.78 0.69 4.0 8.0 Q3
SN74AUC1G32YZPR DSBGA YZP 5 3000 178.0 9.2 1.02 1.52 0.63 4.0 8.0 Q1
PACKAGE MATERIALS INFORMATION
www.ti.com 24-Jul-2020
Pack Materials-Page 1
I TEXAS INSTRUMENTS TAPE AND REEL BOX DIMENSIONS
*All dimensions are nominal
Device Package Type Package Drawing Pins SPQ Length (mm) Width (mm) Height (mm)
SN74AUC1G32DBVR SOT-23 DBV 5 3000 180.0 180.0 18.0
SN74AUC1G32DBVR SOT-23 DBV 5 3000 202.0 201.0 28.0
SN74AUC1G32DBVRG4 SOT-23 DBV 5 3000 180.0 180.0 18.0
SN74AUC1G32DCKR SC70 DCK 5 3000 180.0 180.0 18.0
SN74AUC1G32DCKR SC70 DCK 5 3000 180.0 180.0 18.0
SN74AUC1G32DCKR SC70 DCK 5 3000 202.0 201.0 28.0
SN74AUC1G32DRLR SOT-5X3 DRL 5 4000 202.0 201.0 28.0
SN74AUC1G32DRLR SOT-5X3 DRL 5 4000 184.0 184.0 19.0
SN74AUC1G32YZPR DSBGA YZP 5 3000 220.0 220.0 35.0
PACKAGE MATERIALS INFORMATION
www.ti.com 24-Jul-2020
Pack Materials-Page 2
www.ti.com
PACKAGE OUTLINE
C
1.7
1.5
2X 0.5
2X 1
5X 0.3
0.1
0.6 MAX
5X 0.18
0.08
5X 0.4
0.2
0.05
0.00 TYP
5X 0.27
0.15
B1.3
1.1
A
1.7
1.5
NOTE 3
SOT - 0.6 mm max heightDRL0005A
PLASTIC SMALL OUTLINE
4220753/B 12/2020
NOTES:
1. All linear dimensions are in millimeters. Any dimensions in parenthesis are for reference only. Dimensioning and tolerancing
per ASME Y14.5M.
2. This drawing is subject to change without notice.
3. This dimension does not include mold flash, protrusions, or gate burrs. Mold flash, protrusions, or gate burrs shall not
exceed 0.15 mm per side.
4. Reference JEDEC registration MO-293 Variation UAAD-1
15
PIN 1
ID AREA
34
SEATING PLANE
0.05 C
SCALE 8.000
0.1 C A B
0.05
SYMM
SYMM
www.ti.com
EXAMPLE BOARD LAYOUT
0.05 MAX
AROUND 0.05 MIN
AROUND
5X (0.67)
5X (0.3)
(1.48)
2X (0.5)
(R0.05) TYP
(1)
4220753/B 12/2020
SOT - 0.6 mm max heightDRL0005A
PLASTIC SMALL OUTLINE
NOTES: (continued)
5. Publication IPC-7351 may have alternate designs.
6. Solder mask tolerances between and around signal pads can vary based on board fabrication site.
SYMM
LAND PATTERN EXAMPLE
SCALE:30X
SYMM
1
34
5
SOLDER MASK
OPENING
METAL UNDER
SOLDER MASK
SOLDER MASK
DEFINED
METAL
SOLDER MASK
OPENING
NON SOLDER MASK
DEFINED
(PREFERRED)
SOLDERMASK DETAILS
vi“‘+\‘\‘\
www.ti.com
EXAMPLE STENCIL DESIGN
(1.48)
2X (0.5)
5X (0.67)
5X (0.3)
(R0.05) TYP
(1)
SOT - 0.6 mm max heightDRL0005A
PLASTIC SMALL OUTLINE
4220753/B 12/2020
NOTES: (continued)
7. Laser cutting apertures with trapezoidal walls and rounded corners may offer better paste release. IPC-7525 may have alternate
design recommendations.
8. Board assembly site may have different recommendations for stencil design.
SOLDER PASTE EXAMPLE
BASED ON 0.1 mm THICK STENCIL
SCALE:30X
SYMM
SYMM
1
34
5
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LAND PATTERN DATA DC< (="" 7pjsoic5=""> PLASTC SMALL OU’LME Exc'm‘e Boc'd LuyuM stem Openings Based or a stencfl tn'ckndss uf 127mm (005m) /23\\der Musk Cpen'v‘g d d s W \‘ ‘\“=bd Geometry \ v y \ NOTES- A M \meur dimensmns are m miHWete's a. In: druwv‘q is sweat (a chc'vge mud: 'vuhce c Custume's snodd p‘uce d note 01 me mm: buurd (abr'cahun c'awmg nm :0 mm the ce'fle' smder musk denned Dad, n mundmn many is reco'n'nended (Dr uHernme designs EV Laser cumrq opc'mvcs wnn "apczmda wuHs and mo rouncmq corners wm am bcncr dosxc readscv Cdstomcrs shou‘c can thew Guard asse’na‘y me for Ska design recom’nencnhons EXONP‘S s‘ercfl des‘g’v baSeC on a 50% vo‘umemc \Dud su‘der paste M‘cr m H’C’ bk) Var other S‘cncfl rccowmcwdatnrs. ' hams Q‘ INSTRUMENTS www.li.com
www.ti.com
PACKAGE OUTLINE
C
0.22
0.08 TYP
0.25
3.0
2.6
2X 0.95
1.9
1.45
0.90
0.15
0.00 TYP
5X 0.5
0.3
0.6
0.3 TYP
8
0 TYP
1.9
A
3.05
2.75
B
1.75
1.45
(1.1)
SOT-23 - 1.45 mm max heightDBV0005A
SMALL OUTLINE TRANSISTOR
4214839/F 06/2021
NOTES:
1. All linear dimensions are in millimeters. Any dimensions in parenthesis are for reference only. Dimensioning and tolerancing
per ASME Y14.5M.
2. This drawing is subject to change without notice.
3. Refernce JEDEC MO-178.
4. Body dimensions do not include mold flash, protrusions, or gate burrs. Mold flash, protrusions, or gate burrs shall not
exceed 0.25 mm per side.
0.2 C A B
1
34
5
2
INDEX AREA
PIN 1
GAGE PLANE
SEATING PLANE
0.1 C
SCALE 4.000
www.ti.com
EXAMPLE BOARD LAYOUT
0.07 MAX
ARROUND 0.07 MIN
ARROUND
5X (1.1)
5X (0.6)
(2.6)
(1.9)
2X (0.95)
(R0.05) TYP
4214839/F 06/2021
SOT-23 - 1.45 mm max heightDBV0005A
SMALL OUTLINE TRANSISTOR
NOTES: (continued)
5. Publication IPC-7351 may have alternate designs.
6. Solder mask tolerances between and around signal pads can vary based on board fabrication site.
SYMM
LAND PATTERN EXAMPLE
EXPOSED METAL SHOWN
SCALE:15X
PKG
1
34
5
2
SOLDER MASK
OPENING
METAL UNDER
SOLDER MASK
SOLDER MASK
DEFINED
EXPOSED METAL
METAL
SOLDER MASK
OPENING
NON SOLDER MASK
DEFINED
(PREFERRED)
SOLDER MASK DETAILS
EXPOSED METAL
www.ti.com
EXAMPLE STENCIL DESIGN
(2.6)
(1.9)
2X(0.95)
5X (1.1)
5X (0.6)
(R0.05) TYP
SOT-23 - 1.45 mm max heightDBV0005A
SMALL OUTLINE TRANSISTOR
4214839/F 06/2021
NOTES: (continued)
7. Laser cutting apertures with trapezoidal walls and rounded corners may offer better paste release. IPC-7525 may have alternate
design recommendations.
8. Board assembly site may have different recommendations for stencil design.
SOLDER PASTE EXAMPLE
BASED ON 0.125 mm THICK STENCIL
SCALE:15X
SYMM
PKG
1
34
5
2
‘ ‘ E g ***** $1 Li, ‘0 Q) / n ‘ --II- (£4
www.ti.com
PACKAGE OUTLINE
C
0.5 MAX
0.19
0.15
1
TYP
0.5 TYP
5X 0.25
0.21
0.5
TYP
B E A
D
4219492/A 05/2017
DSBGA - 0.5 mm max heightYZP0005
DIE SIZE BALL GRID ARRAY
NOTES:
1. All linear dimensions are in millimeters. Any dimensions in parenthesis are for reference only. Dimensioning and tolerancing
per ASME Y14.5M.
2. This drawing is subject to change without notice.
BALL A1
CORNER
SEATING PLANE
BALL TYP 0.05 C
B
1 2
0.015 C A B
SYMM
SYMM
C
A
SCALE 8.000
D: Max =
E: Max =
1.418 mm, Min =
0.918 mm, Min =
1.358 mm
0.858 mm
www.ti.com
EXAMPLE BOARD LAYOUT
5X ( 0.23)
(0.5) TYP
(0.5) TYP
( 0.23)
METAL
0.05 MAX ( 0.23)
SOLDER MASK
OPENING
0.05 MIN
4219492/A 05/2017
DSBGA - 0.5 mm max heightYZP0005
DIE SIZE BALL GRID ARRAY
NOTES: (continued)
3. Final dimensions may vary due to manufacturing tolerance considerations and also routing constraints.
For more information, see Texas Instruments literature number SNVA009 (www.ti.com/lit/snva009).
SYMM
SYMM
LAND PATTERN EXAMPLE
SCALE:40X
12
A
B
C
NON-SOLDER MASK
DEFINED
(PREFERRED)
SOLDER MASK DETAILS
NOT TO SCALE
SOLDER MASK
OPENING
SOLDER MASK
DEFINED
METAL UNDER
SOLDER MASK
www.ti.com
EXAMPLE STENCIL DESIGN
(0.5)
TYP
(0.5) TYP
5X ( 0.25) (R0.05) TYP
METAL
TYP
4219492/A 05/2017
DSBGA - 0.5 mm max heightYZP0005
DIE SIZE BALL GRID ARRAY
NOTES: (continued)
4. Laser cutting apertures with trapezoidal walls and rounded corners may offer better paste release.
SYMM
SYMM
SOLDER PASTE EXAMPLE
BASED ON 0.1 mm THICK STENCIL
SCALE:40X
12
A
B
C
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