Datenblatt für TCA9548A von Texas Instruments

V'.‘ 1!. B X E I TEXAS INSTRUMENTS
TCA9548A
Slaves A0, A1...AN
Slaves B0, B1...BN
Slaves H0, H1...HN
I2C or SMBus
Master
(processor)
SDA
SCL
SD0
SC0
Channel 0
Channel 1
Channel 7
RESET SD1
SC1
SD7
SC7
VCC
A1
A2
GND
A0
Slaves C0, C1...CN
Channel 2
SD2
SC2
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An IMPORTANT NOTICE at the end of this data sheet addresses availability, warranty, changes, use in safety-critical applications,
intellectual property matters and other important disclaimers. PRODUCTION DATA.
TCA9548A
SCPS207G –MAY 2012–REVISED NOVEMBER 2019
TCA9548A Low-Voltage 8-Channel I
2
C Switch with Reset
1
1 Features
1• 1-to-8 Bidirectional translating switches
• I2C Bus and SMBus compatible
• Active-low reset input
• Three address pins, allowing up to eight
TCA9548A devices on the I2C bus
• Channel selection through an I2C Bus, in any
combination
• Power up with all switch channels deselected
• Low RON switches
• Allows voltage-level translation between 1.8-V,
2.5-V, 3.3-V, and 5-V buses
• No glitch on power up
• Supports hot insertion
• Low standby current
• Operating power-supply voltage range of
1.65 V to 5.5 V
• 5-V Tolerant inputs
• 0- to 400-kHz Clock frequency
• Latch-up performance exceeds 100 mA Per JESD
78, class II
• ESD Protection exceeds JESD 22
– ±2000-V Human-body model (A114-A)
– 200-V Machine model (A115-A)
– ±1000-V Charged-device model (C101)
2 Applications
• Servers
• Routers (telecom switching equipment)
•Factory Automation
• Products with I2C slave address conflicts (such as
multiple, identical temperature sensors)
3 Description
The TCA9548A device has eight bidirectional
translating switches that can be controlled through
the I2C bus. The SCL/SDA upstream pair fans out to
eight downstream pairs, or channels. Any individual
SCn/SDn channel or combination of channels can be
selected, determined by the contents of the
programmable control register. These downstream
channels can be used to resolve I2C slave address
conflicts. For example, if eight identical digital
temperature sensors are needed in the application,
one sensor can be connected at each channel: 0-7.
The system master can reset the TCA9548A in the
event of a time-out or other improper operation by
asserting a low in the RESET input. Similarly, the
power-on reset deselects all channels and initializes
the I2C/SMBus state machine. Asserting RESET
causes the same reset and initialization to occur
without powering down the part. This allows recovery
should one of the downstream I2C buses get stuck in
a low state.
The pass gates of the switches are constructed so
that the VCC pin can be used to limit the maximum
high voltage, which is passed by the TCA9548A.
Limiting the maximum high voltage allows the use of
different bus voltages on each pair, so that 1.8-V, 2.5-
V or 3.3-V parts can communicate with 5-V parts,
without any additional protection. External pullup
resistors pull the bus up to the desired voltage level
for each channel. All I/O pins are 5-V tolerant.
Device Information(1)
PART NUMBER PACKAGE BODY SIZE (NOM)
TCA9548A TSSOP (24) 7.80 mm × 4.40 mm
VQFN (24) 4.00 mm × 4.00 mm
(1) For all available packages, see the orderable addendum at
the end of the data sheet.
Simplified Application Diagram
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Table of Contents
1 Features.................................................................. 1
2 Applications ........................................................... 1
3 Description ............................................................. 1
4 Revision History..................................................... 2
5 Pin Configuration and Functions......................... 4
6 Specifications......................................................... 5
6.1 Absolute Maximum Ratings ..................................... 5
6.2 ESD Ratings ............................................................ 5
6.3 Recommended Operating Conditions....................... 5
6.4 Thermal Information.................................................. 5
6.5 Electrical Characteristics........................................... 6
6.6 I2C Interface Timing Requirements........................... 7
6.7 Reset Timing Requirements ..................................... 8
6.8 Switching Characteristics.......................................... 8
6.9 Typical Characteristics.............................................. 9
7 Parameter Measurement Information ................ 10
8 Detailed Description............................................ 12
8.1 Overview ................................................................. 12
8.2 Functional Block Diagram....................................... 13
8.3 Feature Description................................................. 14
8.4 Device Functional Modes........................................ 14
8.5 Programming........................................................... 14
9 Application and Implementation ........................ 20
9.1 Application Information............................................ 20
9.2 Typical Application .................................................. 20
10 Power Supply Recommendations ..................... 24
10.1 Power-On Reset Requirements ........................... 24
11 Layout................................................................... 26
11.1 Layout Guidelines ................................................. 26
11.2 Layout Example .................................................... 26
12 Device and Documentation Support ................. 27
12.1 Documentation Support ........................................ 27
12.2 Receiving Notification of Documentation Updates 27
12.3 Support Resources ............................................... 27
12.4 Trademarks........................................................... 27
12.5 Electrostatic Discharge Caution............................ 27
12.6 Glossary................................................................ 27
13 Mechanical, Packaging, and Orderable
Information ........................................................... 27
4 Revision History
NOTE: Page numbers for previous revisions may differ from page numbers in the current version.
Changes from Revision F (November 2016) to Revision G Page
• Changed the appearance of the PW package and the RGE package images ..................................................................... 4
• Changed TJfrom 90 C to 130 C in lower voltage VCC conditions ......................................................................................... 5
• Changed TAfrom 85 C to 125C for lower voltage VCC conditions ......................................................................................... 5
• Changed From: VCC = 2.3 V to 3.6 V To: VCC = 1.65 V to 5.5 V in the Electrical Characteristics conditions........................ 6
• Changed VOmin from 0.9V to 0.6 V....................................................................................................................................... 6
• Added standby mode specifications for > 85 C TA................................................................................................................. 6
• Changed RL= 1 kW To: RL= 1 KΩin Figure 6 ................................................................................................................... 11
Changes from Revision E (October 2015) to Revision F Page
• Updated the Description section............................................................................................................................................. 1
• Added new orderable part number, TCA9548AMRGER........................................................................................................ 1
Changes from Revision D (January 2015) to Revision E Page
• Updated Pin Functions table. ................................................................................................................................................ 4
• Added new I2C Sections and read/write description ........................................................................................................... 16
Changes from Revision C (November 2013) to Revision D Page
• Added Pin Configuration and Functions section, ESD Ratings table, Feature Description section, Device Functional
Modes,Application and Implementation section, Power Supply Recommendations section, Layout section, Device
and Documentation Support section, and Mechanical, Packaging, and Orderable Information section .............................. 1
• Updated Typical Application schematic. .............................................................................................................................. 21
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Changes from Revision B (November 2013) to Revision C Page
• Updated VPOR and ICC standby specification. ......................................................................................................................... 6
Changes from Revision A (July 2012) to Revision B Page
• Updated document formatting. ............................................................................................................................................... 1
• Removed ordering information. .............................................................................................................................................. 1
*9 TEXAS INSTRUMENTS
1A0 24 VCC
2A1 23 SDA
3RESET 22 SCL
4SD0 21 A2
5SC0 20 SC7
6SD1 19 SD7
7SC1 18 SC6
8SD2 17 SD6
9SC2 16 SC5
10SD3 15 SD5
11SC3 14 SC4
12GND 13 SD4
Not to scale
24 RESET7SD3
1SD0 18 A2
23 A18SC3
2SC0 17 SC7
22 A09GND
3SD1 16 SD7
21 VCC10SD4
4SC1 15 SC6
20 SDA11SC4
5SD2 14 SD6
19 SCL12SD5
6SC2 13 SC5
Not to scale
Thermal
Pad
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5 Pin Configuration and Functions
PW Package
24-Pin TSSOP
Top View
RGE Package
24-Pin VQFN
Top View
(1) VDPUX is the pull-up reference voltage for the associated data line. VDPUM is the master I2C reference voltage and VDPU0-VDPU7 are the
slave channel reference voltages.
Pin Functions
PIN
TYPE DESCRIPTION
NAME TSSOP
(PW) QFN
(RGE)
A0 1 22 I Address input 0. Connect directly to VCC or ground
A1 2 23 I Address input 1. Connect directly to VCC or ground
A2 21 18 I Address input 2. Connect directly to VCC or ground
GND 12 9 — Ground
RESET 3 24 I Active-low reset input. Connect to VCC or VDPUM(1) through a pull-up resistor, if not used
SD0 4 1 I/O Serial data 0. Connect to VDPU0(1) through a pull-up resistor
SC0 5 2 I/O Serial clock 0. Connect to VDPU0(1) through a pull-up resistor
SD1 6 3 I/O Serial data 1. Connect to VDPU1(1) through a pull-up resistor
SC1 7 4 I/O Serial clock 1. Connect to VDPU1(1) through a pull-up resistor
SD2 8 5 I/O Serial data 2. Connect to VDPU2(1) through a pull-up resistor
SC2 9 6 I/O Serial clock 2. Connect to VDPU2(1) through a pull-up resistor
SD3 10 7 I/O Serial data 3. Connect to VDPU3(1) through a pull-up resistor
SC3 11 8 I/O Serial clock 3. Connect to VDPU3(1) through a pull-up resistor
SD4 13 10 I/O Serial data 4. Connect to VDPU4(1) through a pull-up resistor
SC4 14 11 I/O Serial clock 4. Connect to VDPU4(1) through a pull-up resistor
SD5 15 12 I/O Serial data 5. Connect to VDPU5(1) through a pull-up resistor
SC5 16 13 I/O Serial clock 5. Connect to VDPU5(1) through a pull-up resistor
SD6 17 14 I/O Serial data 6. Connect to VDPU6(1) through a pull-up resistor
SC6 18 15 I/O Serial clock 6. Connect to VDPU6(1) through a pull-up resistor
SD7 19 16 I/O Serial data 7. Connect to VDPU7(1) through a pull-up resistor
SC7 20 17 I/O Serial clock 7. Connect to VDPU7(1) through a pull-up resistor
SCL 22 19 I/O Serial clock bus. Connect to VDPUM(1) through a pull-up resistor
SDA 23 20 I/O Serial data bus. Connect to VDPUM(1) through a pull-up resistor
VCC 24 21 Power Supply voltage
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(1) Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. These are stress ratings
only, which do not imply functional operation of the device at these or any other conditions beyond those indicated under Recommended
Operating Conditions. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
(2) The input negative-voltage and output voltage ratings may be exceeded if the input and output current ratings are observed.
6 Specifications
6.1 Absolute Maximum Ratings(1)
over operating free-air temperature range (unless otherwise noted)
MIN MAX UNIT
VCC Supply voltage –0.5 7 V
VIInput voltage(2) –0.5 7 V
IIInput current –20 20 mA
IOOutput current –25 mA
ICC Supply current –100 100 mA
Tstg Storage temperature –65 150 °C
TJMax Junction Temperature VCC ≤3.6 V 130 ℃
VCC ≤5.5 V 90
(1) JEDEC document JEP155 states that 500-V HBM allows safe manufacturing with a standard ESD control process.
(2) JEDEC document JEP157 states that 250-V CDM allows safe manufacturing with a standard ESD control process.
6.2 ESD Ratings
VALUE UNIT
V(ESD) Electrostatic discharge Human body model (HBM), per ANSI/ESDA/JEDEC JS-001(1) ±2000 V
Charged-device model (CDM), per JEDEC specification JESD22-C101(2) ±1000
6.3 Recommended Operating Conditions
MIN MAX UNIT
VCC Supply voltage -40 ℃≤TA≤85 ℃1.65 5.5 V
85 ℃< TA≤125 ℃1.65 3.6
VIH High-level input voltage SCL, SDA 0.7 × VCC 6V
A2–A0, RESET 0.7 × VCC VCC + 0.5
VIL Low-level input voltage SCL, SDA –0.5 0.3 × VCC V
A2–A0, RESET –0.5 0.3 × VCC
TAOperating free-air temperature 3.6 V < VCC ≤5.5 V –40 85 °C
1.65 V ≤VCC ≤3.6 V –40 125
(1) For more information about traditional and new thermal metrics, see the Semiconductor and IC Package Thermal Metrics application
report.
6.4 Thermal Information
THERMAL METRIC(1)
TCA9548A
UNITPW (TSSOP) RGE (VQFN)
24 PINS 24 PINS
RθJA Junction-to-ambient thermal resistance 108.8 57.2 °C/W
RθJC(top) Junction-to-case (top) thermal resistance 54.1 62.5 °C/W
RθJB Junction-to-board thermal resistance 62.7 34.4 °C/W
ψJT Junction-to-top characterization parameter 10.9 3.8 °C/W
ψJB Junction-to-board characterization parameter 62.3 34.4 °C/W
RθJC(bot) Junction-to-case (bottom) thermal resistance N/A 15.5 °C/W
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(1) For operation between specified voltage ranges, refer to the worst-case parameter in both applicable ranges.
(2) All typical values are at nominal supply voltage (1.8-, 2.5-, 3.3-, or 5-V VCC), TA= 25°C.
(3) RESET = VCC (held high) when all other input voltages, VI= GND.
(4) The power-on reset circuit resets the I2C bus logic with VCC < VPORF.
6.5 Electrical Characteristics(1)
VCC = 1.65 V to 5.5 V, over recommended operating free-air temperature ranges supported by Recommended Operating
Conditions (unless otherwise noted)
PARAMETER TEST CONDITIONS VCC MIN TYP(2) MAX UNIT
VPORR Power-on reset voltage, VCC rising No load, VI= VCC or GND(3) 1.2 1.5 V
VPORF Power-on reset voltage, VCC
falling(4) No load, VI= VCC or GND(3) 0.8 1 V
Vo(sw) Switch output voltage Vi(sw) = VCC, ISWout = –100 μA
5 V 3.6
V
4.5 V to 5.5 V 2.6 4.5
3.3 V 1.9
3 V to 3.6 V 1.6 2.8
2.5 V 1.5
2.3 V to 2.7 V 1.1 2
1.8 V 1.1
1.65 V to 1.95 V 0.6 1.25
IOL SDA VOL = 0.4 V 1.65 V to 5.5 V 3 6 mA
VOL = 0.6 V 6 9
II
SCL, SDA
VI= VCC or GND(3) 1.65 V to 5.5 V
–1 1
μA
SC7–SC0, SD7–SD0 –1 1
A2–A0 –1 1
RESET –1 1
ICC
Operating mode
fSCL = 400 kHz VI= VCC or GND(3), IO= 0
5.5 V 50 80
μA
3.6 V 20 35
2.7 V 11 20
1.65 V 6 10
fSCL = 100 kHz VI= VCC or GND(3), IO= 0
5.5 V 9 30
3.6 V 6 15
2.7 V 4 8
1.65 V 2 4
Standby mode
Low inputs VI= GND(3), IO= 0, -40 ℃≤TA≤
85 ℃
5.5 V 0.2 2
3.6 V 0.1 2
2.7 V 0.1 1
1.65 V 0.1 1
High inputs VI= VCC, IO= 0, -40 ℃≤TA≤
85 ℃
5.5 V 0.2 2
3.6 V 0.1 2
2.7 V 0.1 1
1.65 V 0.1 1
Low and High
Inputs VI= VCC or GND, IO= 0, 85 ℃<
TA≤125 ℃
3.6 V 1 2
2.7 V 0.7 1.5
1.65 V 0.4 1
ΔICC Supply-current
change SCL, SDA
SCL or SDA input at 0.6 V,
Other inputs at VCC or GND(3) 1.65 V to 5.5 V
3 20
μA
SCL or SDA input at VCC – 0.6 V,
Other inputs at VCC or GND(3) 3 20
Ci
A2–A0 VI= VCC or GND(3) 1.65 V to 5.5 V
4 5
pFRESET 4 5
SCL VI= VCC or GND(3), Switch OFF 20 28
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Electrical Characteristics(1) (continued)
VCC = 1.65 V to 5.5 V, over recommended operating free-air temperature ranges supported by Recommended Operating
Conditions (unless otherwise noted)
PARAMETER TEST CONDITIONS VCC MIN TYP(2) MAX UNIT
(5) Cio(ON) depends on internal capacitance and external capacitance added to the SCn lines when channels(s) are ON.
Cio(off) (5) SDA VI= VCC or GND(3), Switch OFF 1.65 V to 5.5 V 20 28 pF
SC7–SC0, SD7–SD0 5.5 7.5
RON Switch-on resistance
VO= 0.4 V, IO= 15 mA 4.5 V to 5.5 V 4 10 20
Ω
3 V to 3.6 V 5 12 30
VO= 0.4 V, IO= 10 mA 2.3 V to 2.7 V 7 15 45
1.65 V to 1.95 V 10 25 70
(1) A device internally must provide a hold time of at least 300 ns for the SDA signal (referred to the VIH min of the SCL signal), to bridge
the undefined region of the falling edge of SCL.
(2) Data taken using a 1-kΩpull-up resistor and 50-pF load (see Figure 6)
(3) Cb= total bus capacitance of one bus line in pF
6.6 I2C Interface Timing Requirements
over recommended operating free-air temperature range (unless otherwise noted) (see Figure 5)
MIN MAX UNIT
STANDARD MODE
fscl I2C clock frequency 0 100 kHz
tsch I2C clock high time 4 μs
tscl I2C clock low time 4.7 μs
tsp I2C spike time 50 ns
tsds I2C serial-data setup time 250 ns
tsdh I2C serial-data hold time 0(1) μs
ticr I2C input rise time 1000 ns
ticf I2C input fall time 300 ns
tocf I2C output (SDn) fall time (10-pF to 400-pF bus) 300 ns
tbuf I2C bus free time between stop and start 4.7 μs
tsts I2C start or repeated start condition setup 4.7 μs
tsth I2C start or repeated start condition hold 4 μs
tsps I2C stop condition setup 4 μs
tvdL(Data) Valid-data time (high to low)(2) SCL low to SDA output low valid 1 μs
tvdH(Data) Valid-data time (low to high)(2) SCL low to SDA output high valid 0.6 μs
tvd(ack) Valid-data time of ACK condition ACK signal from SCL low
to SDA output low 1μs
CbI2C bus capacitive load 400 pF
FAST MODE
fscl I2C clock frequency 0 400 kHz
tsch I2C clock high time 0.6 μs
tscl I2C clock low time 1.3 μs
tsp I2C spike time 50 ns
tsds I2C serial-data setup time 100 ns
tsdh I2C serial-data hold time 0(1) μs
ticr I2C input rise time 20 + 0.1Cb
(3) 300 ns
ticf I2C input fall time 20 + 0.1Cb
(3) 300 ns
tocf I2C output (SDn) fall time (10-pF to 400-pF bus) 20 + 0.1Cb
(3) 300 ns
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I2C Interface Timing Requirements (continued)
over recommended operating free-air temperature range (unless otherwise noted) (see Figure 5)
MIN MAX UNIT
tbuf I2C bus free time between stop and start 1.3 μs
tsts I2C start or repeated start condition setup 0.6 μs
tsth I2C start or repeated start condition hold 0.6 μs
tsps I2C stop condition setup 0.6 μs
tvdL(Data) Valid-data time (high to low)(2) SCL low to SDA output low valid 1 μs
tvdH(Data) Valid-data time (low to high)(2) SCL low to SDA output high valid 0.6 μs
tvd(ack) Valid-data time of ACK condition ACK signal from SCL low
to SDA output low 1μs
CbI2C bus capacitive load 400 pF
6.7 Reset Timing Requirements
over recommended operating free-air temperature range (unless otherwise noted)
PARAMETER MIN MAX UNIT
tW(L) Pulse duration, RESET low 6 ns
tREC(STA) Recovery time from RESET to start 0 ns
(1) The propagation delay is the calculated RC time constant of the typical ON-state resistance of the switch and the specified load
capacitance, when driven by an ideal voltage source (zero output impedance).
(2) trst is the propagation delay measured from the time the RESET pin is first asserted low to the time the SDA pin is asserted high,
signaling a stop condition. It must be a minimum of tWL.
6.8 Switching Characteristics
over recommended operating free-air temperature range, CL≤100 pF (unless otherwise noted) (see Figure 5)
PARAMETER FROM
(INPUT) TO
(OUTPUT) MIN MAX UNIT
tpd (1) Propagation delay time RON = 20 Ω, CL= 15 pF SDA or SCL SDn or SCn 0.3 ns
RON = 20 Ω, CL= 50 pF 1
trst (2) RESET time (SDA clear) RESET SDA 500 ns
l TEXAS INSTRUMENTS sou so //
VCC (V)
CIO(OFF) (pF)
0 0.5 1 1.5 2 2.5 3 3.5 4 4.5 5 5.5
4
4.2
4.4
4.6
4.8
5
5.2
5.4
5.6
5.8
6
D006
25ºC (Room Temperature)
85ºC
-40º
IOL (mA)
VOL (mV)
0 2 4 6 8 10 12
0
100
200
300
400
500
600
700
800
D003
VCC = 5.5V
VCC = 3.3V
VCC = 1.65V
VCC (V)
ICC, Standby Mode (µA)
1.5 2 2.5 3 3.5 4 4.5 5 5.5
0.2
0.4
0.6
0.8
1
1.2
1.4
1.6
1.8
D004
25ºC (Room Temperature)
85ºC
-40ºC
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6.9 Typical Characteristics
Figure 1. SDA Output Low Voltage (VOL) vs Load Current
(IOL) at Three VCC Levels Figure 2. Standby Current (ICC) vs Supply Voltage (VCC) at
Three Temperature Points
Figure 3. Slave Channel (SCn/SDn) Capacitance (Cio(OFF)) vs
Supply Voltage (VCC) at Three Temperature Points Figure 4. On-Resistance (RON) vs Supply Voltage (VCC) at
Three Temperatures
\
‘5‘ TEXAS INSTRUMENTS iii:
SCL
SDA
SDA LOADCONFIGURATION
1
2,3
VCC
R =1k
LW
C =50pF
(seeNote A)
L
DUT
SDA
ThreeBytesforComplete
DeviceProgramming
Stop
Condition
(P)
Start
Condition
(S)
Address
Bit7
(MSB)
Address
Bit6
Address
Bit1
R/
Bit0
(LSB)
WACK
(A)
Data
Bit7
(MSB)
Data
Bit0
(LSB)
Stop
Condition
(P)
0.7 V´CC
0.3 V´CC
VOLTAGEWAVEFORMS
Startor
RepeatStart
Condition
RepeatStart
Condition Stop
Condition
BYTE DESCRIPTION
I Caddress
2
P-portdata
0.7 V´CC
0.3 V´CC
tscl tsch
tbuf
ticf
ticf
ticr
tsth
ticr
tsds
tsp
tsdh
tvd(ack)
tvdH(Data)
tsts
tsps
tvdL(Data)
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7 Parameter Measurement Information
A. CLincludes probe and jig capacitance.
B. All inputs are supplied by generators having the following characteristics: PRR ≤10 MHz, ZO= 50 Ω, tr/tf≤30 ns.
C. Not all parameters and waveforms are applicable to all devices.
Figure 5. I2C Load Circuit and Voltage Waveforms
‘5‘ TEXAS INSTRUMENTS
SDA
SCL
Start
ACK or Read Cycle
tw
tREC
RESET
0.3 VCC
0.3 VCC
tRESET
SDn, SCn
RL= 1 kW
VCC
CL= 50 pF
(see Note A)
SDA LOAD CONFIGURATION
DUT SDA
VCC/2
tRESET
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Parameter Measurement Information (continued)
A. CLincludes probe and jig capacitance.
B. All inputs are supplied by generators having the following characteristics: PRR ≤10 MHz, ZO= 50 Ω, tr/tf≤30 ns.
C. I/Os are configured as inputs.
D. Not all parameters and waveforms are applicable to all devices.
Figure 6. Reset Load Circuit and Voltage Waveforms
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8 Detailed Description
8.1 Overview
The TCA9548A is an 8-channel, bidirectional translating I2C switch. The master SCL/SDA signal pair is directed
to eight channels of slave devices, SC0/SD0-SC7/SD7. Any individual downstream channel can be selected as
well as any combination of the eight channels.
The device offers an active-low RESET input which resets the state machine and allows the TCA9548A to
recover must one of the downstream I2C buses get stuck in a low state. The state machine of the device can
also be reset by cycling the power supply, VCC, also known as a power-on reset (POR). Both the RESET function
and a POR cause all channels to be deselected.
The connections of the I2C data path are controlled by the same I2C master device that is switched to
communicate with multiple I2C slaves. After the successful acknowledgment of the slave address (hardware
selectable by A0, A1, and A2 pins), a single 8-bit control register is written to or read from to determine the
selected channels.
The TCA9548A may also be used for voltage translation, allowing the use of different bus voltages on each
SCn/SDn pair such that 1.8-V, 2.5-V, or 3.3-V parts can communicate with 5-V parts. This is achieved by using
external pull-up resistors to pull the bus up to the desired voltage for the master and each slave channel.
l TEXAS INSTRUMENTS L, L, L ‘ L, L, L, L L L 74] J , .— +41— ‘— .— AL A A a
SC0
SC1
SC2
SC3
SC4
SC5
SC6
SC7
SD0
SD1
SD2
SD3
SD4
SD5
SD6
SD7
GND
VCC
RESET
SCL
SDA
Switch Control Logic
Reset Circuit
Input Filter
I C Bus Control
2
A0
A1
A2
TCA9548A
1
2
21
5
7
9
11
14
16
18
20
4
6
8
10
13
15
17
19
12
24
3
22
23
13
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8.2 Functional Block Diagram
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8.3 Feature Description
The TCA9548A is an 8-channel, bidirectional translating switch for I2C buses that supports Standard-Mode (100
kHz) and Fast-Mode (400 kHz) operation. The TCA9548A features I2C control using a single 8-bit control register
in which each bit controls the enabling and disabling of one of the corresponding 8 switch channels for I2C data
flow. Depending on the application, voltage translation of the I2C bus can also be achieved using the TCA9548A
to allow 1.8-V, 2.5-V, or 3.3-V parts to communicate with 5-V parts. Additionally, in the event that communication
on the I2C bus enters a fault state, the TCA9548A can be reset to resume normal operation using the RESET pin
feature or by a power-on reset which results from cycling power to the device.
8.4 Device Functional Modes
8.4.1 RESET Input
The RESET input is an active-low signal that may be used to recover from a bus-fault condition. When this signal
is asserted low for a minimum of tWL, the TCA9548A resets its registers and I2C state machine and deselects all
channels. The RESET input must be connected to VCC through a pull-up resistor.
8.4.2 Power-On Reset
When power is applied to the VCC pin, an internal power-on reset holds the TCA9548A in a reset condition until
VCC has reached VPORR. At this point, the reset condition is released, and the TCA9548A registers and I2C state
machine are initialized to their default states, all zeroes, causing all the channels to be deselected. Thereafter,
VCC must be lowered below VPORF to reset the device.
8.5 Programming
8.5.1 I2C Interface
The TCA9548A has a standard bidirectional I2C interface that is controlled by a master device in order to be
configured or read the status of this device. Each slave on the I2C bus has a specific device address to
differentiate between other slave devices that are on the same I2C bus. Many slave devices require configuration
upon startup to set the behavior of the device. This is typically done when the master accesses internal register
maps of the slave, which have unique register addresses. A device can have one or multiple registers where
data is stored, written, or read.
The physical I2C interface consists of the serial clock (SCL) and serial data (SDA) lines. Both SDA and SCL lines
must be connected to VCC through a pull-up resistor. The size of the pull-up resistor is determined by the amount
of capacitance on the I2C lines. (For further details, see the I2C Pull-up Resistor Calculation application report.
Data transfer may be initiated only when the bus is idle. A bus is considered idle if both SDA and SCL lines are
high after a STOP condition (See Figure 7 and Figure 8).
The following is the general procedure for a master to access a slave device:
1. If a master wants to send data to a slave:
– Master-transmitter sends a START condition and addresses the slave-receiver.
– Master-transmitter sends data to slave-receiver.
– Master-transmitter terminates the transfer with a STOP condition.
2. If a master wants to receive or read data from a slave:
– Master-receiver sends a START condition and addresses the slave-transmitter.
– Master-receiver sends the requested register to read to slave-transmitter.
– Master-receiver receives data from the slave-transmitter.
‘5‘ TEXAS INSTRUMENTS \shwgh able while SClee SDA line 51 \_V_/\_V_/
1 1 1 0 A1A2 A0
Slave Address
R/W
Fixed Hardware
Selectable
SCL
SDA
MSB Bit Bit Bit Bit Bit Bit LSB
Byte: 1010 1010 ( 0xAAh )
1 0 101010
SDA line stable while SCL line is high
ACK
ACK
SCL
SDA
STAR T
Condition
STOP
Condition
Data Transfer
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Programming (continued)
– Master-receiver terminates the transfer with a STOP condition.
Figure 7. Definition of Start and Stop Conditions
Figure 8. Bit Transfer
8.5.2 Device Address
Figure 9 shows the address byte of the TCA9548A.
Figure 9. TCA9548A Address
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Programming (continued)
The last bit of the slave address defines the operation (read or write) to be performed. When it is high (1), a read
is selected, while a low (0) selects a write operation.
Table 1 shows the TCA9548A address reference.
Table 1. Address Reference
INPUTS I2C BUS SLAVE ADDRESS
A2 A1 A0
L L L 112 (decimal), 70 (hexadecimal)
L L H 113 (decimal), 71 (hexadecimal)
L H L 114 (decimal), 72 (hexadecimal)
L H H 115 (decimal), 73 (hexadecimal)
H L L 116 (decimal), 74 (hexadecimal)
H L H 117 (decimal), 75 (hexadecimal)
H H L 118 (decimal), 76 (hexadecimal)
H H H 119 (decimal), 77 (hexadecimal)
8.5.3 Bus Transactions
Data must be sent to and received from the slave devices, and this is accomplished by reading from or writing to
registers in the slave device.
Registers are locations in the memory of the slave which contain information, whether it be the configuration
information or some sampled data to send back to the master. The master must write information to these
registers in order to instruct the slave device to perform a task.
While it is common to have registers in I2C slaves, note that not all slave devices have registers. Some devices
are simple and contain only 1 register, which may be written to directly by sending the register data immediately
after the slave address, instead of addressing a register. The TCA9548A is example of a single-register device,
which is controlled via I2C commands. Since it has 1 bit to enable or disable a channel, there is only 1 register
needed, and the master merely writes the register data after the slave address, skipping the register number.
8.5.3.1 Writes
To write on the I2C bus, the master sends a START condition on the bus with the address of the slave, as well
as the last bit (the R/W bit) set to 0, which signifies a write. The slave acknowledges, letting the master know it is
ready. After this, the master starts sending the control register data to the slave until the master has sent all the
data necessary (which is sometimes only a single byte), and the master terminates the transmission with a STOP
condition.
There is no limit to the number of bytes sent, but the last byte sent is what is in the register.
Figure 10 shows an example of writing a single byte to a slave register.
l TEXAS INSTRUMENTS Write to one register in a device F—% /—/% T TT TT START R/W=0 ACK ACK STOP f—% f—j% T TT TT START R/W=1 ACK NACK STOP
S 1 1 1 0 A2 A1 A0 1
Device (Slave) Address (7 bits)
B7 B6 B5 B4 B3 B2 B1 B0 NA
Control Register (8 bits)
AP
START R/W=1 ACK NACK STOP
Master controls SDA line
Slave controls SDA line
S 1 1 1 0 A2 A1 A0 0
Device (Slave) Address (7 bits)
B7 B6 B5 B4 B3 B2 B1 B0 A
Control Register (8 bits)
AP
START R/W=0 ACK ACK STOP
Write to one register in a device
Master controls SDA line
Slave controls SDA line
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Figure 10. Write to Register
8.5.3.2 Reads
Reading from a slave is very similar to writing, but the master sends a START condition, followed by the slave
address with the R/W bit set to 1 (signifying a read). The slave acknowledges the read request, and the master
releases the SDA bus but continues supplying the clock to the slave. During this part of the transaction, the
master becomes the master-receiver, and the slave becomes the slave-transmitter.
The master continues to send out the clock pulses, but releases the SDA line so that the slave can transmit data.
At the end of every byte of data, the master sends an ACK to the slave, letting the slave know that it is ready for
more data. Once the master has received the number of bytes it is expecting, it sends a NACK, signaling to the
slave to halt communications and release the bus. The master follows this up with a STOP condition.
Figure 11 shows an example of reading a single byte from a slave register.
Figure 11. Read from Control Register
l TEXAS INSTRUMENTS cmm 7
ChannelSelectionBits(Read/Write)
Channel1
Channel0
Channel2
Channel3
Channel4
Channel5
Channel6
Channel7
B7 B6 B5 B4 B3 B2 B1 B0
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8.5.4 Control Register
Following the successful acknowledgment of the address byte, the bus master sends a command byte that is
stored in the control register in the TCA9548A (see Figure 12). This register can be written and read via the I2C
bus. Each bit in the command byte corresponds to a SCn/SDn channel and a high (or 1) selects this channel.
Multiple SCn/SDn channels may be selected at the same time. When a channel is selected, the channel
becomes active after a stop condition has been placed on the I2C bus. This ensures that all SCn/SDn lines are in
a high state when the channel is made active, so that no false conditions are generated at the time of
connection. A stop condition always must occur immediately after the acknowledge cycle. If multiple bytes are
received by the TCA9548A, it saves the last byte received.
Figure 12. Control Register
Table 2 shows the TCA9548A Command Byte Definition.
Table 2. Command Byte Definition
CONTROL REGISTER BITS COMMAND
B7 B6 B5 B4 B3 B2 B1 B0
XXXXXXX0 Channel 0 disabled
1 Channel 0 enabled
XXXXXX0XChannel 1 disabled
1 Channel 1 enabled
XXXXX0X X Channel 2 disabled
1 Channel 2 enabled
XXXX0X X X Channel 3 disabled
1 Channel 3 enabled
XXX0X X X X Channel 4 disabled
1 Channel 4 enabled
X X 0XXXXXChannel 5 disabled
1 Channel 5 enabled
X0XXXXXXChannel 6 disabled
1 Channel 6 enabled
0XXXXXXXChannel 7 disabled
1 Channel 7 enabled
00000000No channel selected, power-up/reset
default state
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8.5.5 RESET Input
The RESET input is an active-low signal that may be used to recover from a bus-fault condition. When this signal
is asserted low for a minimum of tWL, the TCA9548A resets its registers and I2C state machine and deselects all
channels. The RESET input must be connected to VCC through a pull-up resistor.
8.5.6 Power-On Reset
When power (from 0 V) is applied to VCC, an internal power-on reset holds the TCA9548A in a reset condition
until VCC has reached VPOR. At that point, the reset condition is released and the TCA9548A registers and I2C
state machine initialize to their default states. After that, VCC must be lowered to below VPOR and then back up to
the operating voltage for a power-reset cycle.
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9 Application and Implementation
NOTE
Information in the following applications sections is not part of the TI component
specification, and TI does not warrant its accuracy or completeness. TI’s customers are
responsible for determining suitability of components for their purposes. Customers should
validate and test their design implementation to confirm system functionality.
9.1 Application Information
Applications of the TCA9548A contain an I2C (or SMBus) master device and up to eight I2C slave devices. The
downstream channels are ideally used to resolve I2C slave address conflicts. For example, if eight identical
digital temperature sensors are needed in the application, one sensor can be connected at each channel: 0-7.
When the temperature at a specific location needs to be read, the appropriate channel can be enabled and all
other channels switched off, the data can be retrieved, and the I2C master can move on and read the next
channel.
In an application where the I2C bus contains many additional slave devices that do not result in I2C slave address
conflicts, these slave devices can be connected to any desired channel to distribute the total bus capacitance
across multiple channels. If multiple switches are enabled simultaneously, additional design requirements must
be considered (see the Design Requirements section and Detailed Design Procedure section).
9.2 Typical Application
Figure 13 shows an application in which the TCA9548A can be used.
WWWWWVVK v 5. 5 m v 5 a. __
TCA9548A
SD1
SDA Channel 0
Channel 1
Channel 2
Channel 3
I2C/SMBus
Master
SCL
RESET
SC1
SD2
SC2
SD3
SC3
SD0
SC0
VDPUM = 1.65 V to 5.5 V
VCC
VDPU0 = V to 5.5 V1.65
VDPU1 = V to 5.5 V1.65
VDPU2 = V to 5.5 V1.65
VDPU3 = V to 5.5 V1.65
SDA
SCL
A2
A1
A0
GND
23
22
3
12
1
2
21
11
10
9
8
7
6
5
4
SD5
Channel 4
Channel 5
Channel 6
Channel 7
SC5
SD6
SC6
SD7
SC7
SD4
SC4
VDPU4 = V to 5.5 V1.65
VDPU5 = V to 5.5 V1.65
VDPU6 = V to 5.5 V1.65
VDPU7 = V to 5.5 V1.65
20
19
18
17
16
15
14
13
RESET
VCC
24
21
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Typical Application (continued)
Pin numbers shown are for the PW package.
Figure 13. Typical Application Schematic
l TEXAS INSTRUMENTS
r
p(max)
b
t
R0.8473 C
u
DPUX OL(max)
p(min)
OL
V V
RI
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Typical Application (continued)
9.2.1 Design Requirements
A typical application of the TCA9548A contains one or more data pull-up voltages, VDPUX, one for the master
device (VDPUM) and one for each of the selectable slave channels (VDPU0 – VDPU7). In the event where the master
device and all slave devices operate at the same voltage, then VDPUM = VDPUX = VCC. In an application where
voltage translation is necessary, additional design requirements must be considered to determine an appropriate
VCC voltage.
The A0, A1, and A2 pins are hardware selectable to control the slave address of the TCA9548A. These pins may
be tied directly to GND or VCC in the application.
If multiple slave channels are activated simultaneously in the application, then the total IOL from SCL/SDA to
GND on the master side is the sum of the currents through all pull-up resistors, Rp.
The pass-gate transistors of the TCA9548A are constructed such that the VCC voltage can be used to limit the
maximum voltage that is passed from one I2C bus to another.
Figure 14 shows the voltage characteristics of the pass-gate transistors (note that the graph was generated using
data specified in the Electrical Characteristics table). In order for the TCA9548A to act as a voltage translator, the
Vpass voltage must be equal to or lower than the lowest bus voltage. For example, if the main bus is running at 5
V and the downstream buses are 3.3 V and 2.7 V, Vpass must be equal to or below 2.7 V to effectively clamp the
downstream bus voltages. As shown in Figure 14, Vpass(max) is 2.7 V when the TCA9548A supply voltage is 4 V
or lower, so the TCA9548A supply voltage could be set to 3.3 V. Pull-up resistors then can be used to bring the
bus voltages to their appropriate levels (see Figure 13).
9.2.2 Detailed Design Procedure
Once all the slaves are assigned to the appropriate slave channels and bus voltages are identified, the pull-up
resistors, Rp, for each of the buses need to be selected appropriately. The minimum pull-up resistance is a
function of VDPUX, VOL,(max), and IOL as shown in Equation 1:
(1)
The maximum pull-up resistance is a function of the maximum rise time, tr(300 ns for fast-mode operation, fSCL =
400 kHz) and bus capacitance, Cbas shown in Equation 2:
(2)
The maximum bus capacitance for an I2C bus must not exceed 400 pF for fast-mode operation. The bus
capacitance can be approximated by adding the capacitance of the TCA9548A, Cio(OFF), the capacitance of wires,
connections and traces, and the capacitance of each individual slave on a given channel. If multiple channels are
activated simultaneously, each of the slaves on all channels contribute to total bus capacitance.
l TEXAS INSTRUMENTS
VDPUX (V)
Rp(min) (kOhm)
0 0.5 1 1.5 2 2.5 3 3.5 4 4.5 5 5.5
0
0.2
0.4
0.6
0.8
1
1.2
1.4
1.6
1.8
D009
VDPUX > 2V
VDPUX <= 2
VCC (V)
Vpass (V)
0 0.5 1 1.5 2 2.5 3 3.5 4 4.5 5 5.5
0
1
2
3
4
5
D007
25ºC (Room Temperature)
85ºC
-40ºC
Cb (pF)
Rp(max) (kOhm)
0 50 100 150 200 250 300 350 400 450
0
5
10
15
20
25
D008
Standard-mode
Fast-mode
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Typical Application (continued)
9.2.3 Application Curves
Standard-mode
(fSCL kHz, tr
SPACE
(fSCL kHz, tr)
Figure 14. Pass-Gate Voltage (Vpass) vs Supply Voltage
(VCC) at Three Temperature Points
Standard-mode
(fSCL = 100 kHz, tr= 1 µs) Fast-mode
(fSCL = 400 kHz, tr= 300 ns)
Figure 15. Maximum Pull-Up Resistance (Rp(max)) vs Bus
Capacitance (Cb)
VOL = 0.2*VDPUX, IOL = 2 mA when VDPUX ≤2 V
VOL = 0.4 V, IOL = 3 mA when VDPUX > 2 V
Figure 16. Minimum Pullup Resistance (Rp(min)) vs Pullup Reference Voltage (VDPUX)
‘5‘ TEXAS INSTRUMENTS
VCC
Time
VCC_GH
VCC_GW
VCC
Ramp-Up
Time to Re-Ramp
Time
Ramp-Down
VCC drops below V 50 mV
PORF –
VCC_RT
VCC_FT
VCC_TRR
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(1) All supply sequencing and ramp rate values are measured at TA= 25°C
10 Power Supply Recommendations
The operating power-supply voltage range of the TCA9548A is 1.65 V to 5.5 V applied at the VCC pin. When the
TCA9548A is powered on for the first time or anytime the device must be reset by cycling the power supply, the
power-on reset requirements must be followed to ensure the I2C bus logic is initialized properly.
10.1 Power-On Reset Requirements
In the event of a glitch or data corruption, TCA9548A can be reset to its default conditions by using the power-on
reset feature. Power-on reset requires that the device go through a power cycle to be completely reset. This
reset also happens when the device is powered on for the first time in an application.
A power-on reset is shown in Figure 17.
VCC is Lowered Below the POR Threshold, Then Ramped Back Up to VCC
Figure 17. Power-On Reset Waveform
Table 3 specifies the performance of the power-on reset feature for TCA9548A for both types of power-on reset.
Table 3. Recommended Supply Sequencing and Ramp Rates(1)
PARAMETER MIN MAX UNIT
VCC_FT Fall time See Figure 17 1 100 ms
VCC_RT Rise time See Figure 17 0.1 100 ms
VCC_TRR Time to re-ramp (when VCC drops below VPORF(min) – 50 mV or
when VCC drops to GND) See Figure 17 40 μs
VCC_GH Level that VCC can glitch down to, but not cause a functional
disruption when VCC_GW = 1 μsSee Figure 18 1.2 V
VCC_GW Glitch width that does not cause a functional disruption when
VCC_GH = 0.5 × VCC See Figure 18 10 μs
Glitches in the power supply can also affect the power-on reset performance of this device. The glitch width
(VCC_GW) and height (VCC_GH) are dependent on each other. The bypass capacitance, source impedance, and
device impedance are factors that affect power-on reset performance. Figure 18 and Table 3 provide more
information on how to measure these specifications.
Figure 18. Glitch Width and Glitch Height
‘5‘ TEXAS INSTRUMENTS
VCC
VPORR
VPORF
Time
POR
Time
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VPOR is critical to the power-on reset. VPOR is the voltage level at which the reset condition is released and all the
registers and the I2C/SMBus state machine are initialized to their default states. The value of VPOR differs based
on the VCC being lowered to or from 0. Figure 19 and Table 3 provide more details on this specification.
Figure 19. VPOR
l TEXAS INSTRUMENTS LEGEND
SD7
SC7
SD6
SC6
SC4
SD4
SD0
A0
A1
RESET
SC0
SD1
SC1
GND
VCC
SDA
SCL
A2
SD3
SC3
SD2
SC2
VDPU0
Via to Power Plane
Partial Power Plane
VDPUM
Via to GND Plane
Copper Pour
VCC
GND
By-pass/de-coupling
capacitors
TCA9548A
GND
To I2C Master
To Slave Channel 0
LEGEND
SC5
SD5
(inner layer)
(outer layer)
VDPU2
To Slave Channel 2
VDPU1
To Slave Channel 1
VDPU6
To Slave Channel 6
VDPU5
To Slave Channel 5
VDPU3
To Slave Channel 3
VDPU4
To Slave Channel 4
VDPU7
To Slave Channel 7
1
2
3
4
5
6
7
8
9
10
11
12 13
14
15
16
17
18
19
20
21
22
23
24
PW package
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11 Layout
11.1 Layout Guidelines
For PCB layout of the TCA9548A, common PCB layout practices must be followed but additional concerns
related to high-speed data transfer such as matched impedances and differential pairs are not a concern for I2C
signal speeds. It is common to have a dedicated ground plane on an inner layer of the board and pins that are
connected to ground must have a low-impedance path to the ground plane in the form of wide polygon pours and
multiple vias. By-pass and de-coupling capacitors are commonly used to control the voltage on the VCC pin,
using a larger capacitor to provide additional power in the event of a short power supply glitch and a smaller
capacitor to filter out high-frequency ripple.
In an application where voltage translation is not required, all VDPUX voltages and VCC could be at the same
potential and a single copper plane could connect all of pull-up resistors to the appropriate reference voltage. In
an application where voltage translation is required, VDPUM and VDPU0 – VDPU7, may all be on the same layer of
the board with split planes to isolate different voltage potentials.
To reduce the total I2C bus capacitance added by PCB parasitics, data lines (SCn and SDn) must be a short as
possible and the widths of the traces must also be minimized (for example, 5-10 mils depending on copper
weight).
11.2 Layout Example
Figure 20. Layout Schematic
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12 Device and Documentation Support
12.1 Documentation Support
12.1.1 Related Documentation
For related documentation see the following:
•I2C Bus Pull-Up Resistor Calculation
•Maximum Clock Frequency of I2C Bus Using Repeaters
•Introduction to Logic
•Understanding the I2C Bus
•Choosing the Correct I2C Device for New Designs
•TCA9548AEVM User's Guide
12.2 Receiving Notification of Documentation Updates
To receive notification of documentation updates, navigate to the device product folder on ti.com. In the upper
right corner, click on Alert me to register and receive a weekly digest of any product information that has
changed. For change details, review the revision history included in any revised document.
12.3 Support Resources
TI E2E™ support forums are an engineer's go-to source for fast, verified answers and design help — straight
from the experts. Search existing answers or ask your own question to get the quick design help you need.
Linked content is provided "AS IS" by the respective contributors. They do not constitute TI specifications and do
not necessarily reflect TI's views; see TI's Terms of Use.
12.4 Trademarks
E2E is a trademark of Texas Instruments.
All other trademarks are the property of their respective owners.
12.5 Electrostatic Discharge Caution
This integrated circuit can be damaged by ESD. Texas Instruments recommends that all integrated circuits be handled with
appropriate precautions. Failure to observe proper handling and installation procedures can cause damage.
ESD damage can range from subtle performance degradation to complete device failure. Precision integrated circuits may be more
susceptible to damage because very small parametric changes could cause the device not to meet its published specifications.
12.6 Glossary
SLYZ022 —TI Glossary.
This glossary lists and explains terms, acronyms, and definitions.
13 Mechanical, Packaging, and Orderable Information
The following pages include mechanical, packaging, and orderable information. This information is the most
current data available for the designated devices. This data is subject to change without notice and revision of
this document. For browser-based versions of this data sheet, refer to the left-hand navigation.
I TEXAS INSTRUMENTS Sample: Sample: Sample:
PACKAGE OPTION ADDENDUM
www.ti.com 10-Dec-2020
Addendum-Page 1
PACKAGING INFORMATION
Orderable Device Status
(1)
Package Type Package
Drawing Pins Package
Qty Eco Plan
(2)
Lead finish/
Ball material
(6)
MSL Peak Temp
(3)
Op Temp (°C) Device Marking
(4/5)
Samples
TCA9548AMRGER ACTIVE VQFN RGE 24 3000 RoHS & Green NIPDAU Level-2-260C-1 YEAR -40 to 85 PW548A
TCA9548APWR ACTIVE TSSOP PW 24 2000 RoHS & Green NIPDAU Level-1-260C-UNLIM -40 to 85 PW548A
TCA9548ARGER ACTIVE VQFN RGE 24 3000 RoHS & Green NIPDAU Level-2-260C-1 YEAR -40 to 85 PW548A
(1) The marketing status values are defined as follows:
ACTIVE: Product device recommended for new designs.
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design.
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.
OBSOLETE: TI has discontinued the production of the device.
(2) RoHS: TI defines "RoHS" to mean semiconductor products that are compliant with the current EU RoHS requirements for all 10 RoHS substances, including the requirement that RoHS substance
do not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, "RoHS" products are suitable for use in specified lead-free processes. TI may
reference these types of products as "Pb-Free".
RoHS Exempt: TI defines "RoHS Exempt" to mean products that contain lead but are compliant with EU RoHS pursuant to a specific EU RoHS exemption.
Green: TI defines "Green" to mean the content of Chlorine (Cl) and Bromine (Br) based flame retardants meet JS709B low halogen requirements of <=1000ppm threshold. Antimony trioxide based
flame retardants must also meet the <=1000ppm threshold requirement.
(3) MSL, Peak Temp. - The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature.
(4) There may be additional marking, which relates to the logo, the lot trace code information, or the environmental category on the device.
(5) Multiple Device Markings will be inside parentheses. Only one Device Marking contained in parentheses and separated by a "~" will appear on a device. If a line is indented then it is a continuation
of the previous line and the two combined represent the entire Device Marking for that device.
(6) Lead finish/Ball material - Orderable Devices may have multiple material finish options. Finish options are separated by a vertical ruled line. Lead finish/Ball material values may wrap to two
lines if the finish value exceeds the maximum column width.
Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information
provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and
continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals.
TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited information may not be available for release.
I TEXAS INSTRUMENTS
PACKAGE OPTION ADDENDUM
www.ti.com 10-Dec-2020
Addendum-Page 2
In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI to Customer on an annual basis.
OTHER QUALIFIED VERSIONS OF TCA9548A :
•Automotive: TCA9548A-Q1
NOTE: Qualified Version Definitions:
•Automotive - Q100 devices qualified for high-reliability automotive applications targeting zero defects
I TEXAS INSTRUMENTS ‘3‘ V.'
PACKAGE MATERIALS INFORMATION
www.ti.com 3-Jun-2022
TAPE AND REEL INFORMATION
Reel Width (W1)
REEL DIMENSIONS
A0
B0
K0
W
Dimension designed to accommodate the component length
Dimension designed to accommodate the component thickness
Overall width of the carrier tape
Pitch between successive cavity centers
Dimension designed to accommodate the component width
TAPE DIMENSIONS
K0 P1
B0 W
A0
Cavity
QUADRANT ASSIGNMENTS FOR PIN 1 ORIENTATION IN TAPE
Pocket Quadrants
Sprocket Holes
Q1 Q1Q2 Q2
Q3 Q3Q4 Q4 User Direction of Feed
P1
Reel
Diameter
*All dimensions are nominal
Device Package
Type Package
Drawing Pins SPQ Reel
Diameter
(mm)
Reel
Width
W1 (mm)
A0
(mm) B0
(mm) K0
(mm) P1
(mm) W
(mm) Pin1
Quadrant
TCA9548AMRGER VQFN RGE 24 3000 330.0 12.4 4.25 4.25 1.15 8.0 12.0 Q1
TCA9548APWR TSSOP PW 24 2000 330.0 16.4 6.95 8.3 1.6 8.0 16.0 Q1
TCA9548ARGER VQFN RGE 24 3000 330.0 12.4 4.25 4.25 1.15 8.0 12.0 Q2
Pack Materials-Page 1
PACKAGE MATERIALS INFORMATION
www.ti.com 3-Jun-2022
TAPE AND REEL BOX DIMENSIONS
Width (mm)
W
L
H
*All dimensions are nominal
Device Package Type Package Drawing Pins SPQ Length (mm) Width (mm) Height (mm)
TCA9548AMRGER VQFN RGE 24 3000 356.0 356.0 35.0
TCA9548APWR TSSOP PW 24 2000 356.0 356.0 35.0
TCA9548ARGER VQFN RGE 24 3000 356.0 356.0 35.0
Pack Materials-Page 2
I TEXAS INSTRUMENTS
GENERIC PACKAGE VIEW
Images above are just a representation of the package family, actual package may vary.
Refer to the product data sheet for package details.
RGE 24 VQFN - 1 mm max height
PLASTIC QUAD FLATPACK - NO LEAD
4204104/H
nnm :) ‘ W # gnmnmnAT Q NOTES: INSTRUMBU'S
NOTES:
1. All linear dimensions are in millimeters. Any dimensions in parenthesis are for reference only. Dimensioning and tolerancing
per ASME Y14.5M.
2. This drawing is subject to change without notice.
3. The package thermal pad must be soldered to the printed circuit board for thermal and mechanical performance.
PACKAGE OUTLINE
www.ti.com
4224376 / C 07/2021
VQFN - 1 mm max height
PLASTIC QUAD FLATPACK- NO LEAD
RGE0024C
A
0.08 C
0.1 C A B
0.05 C
B
SYMM
SYMM
4.1
3.9
4.1
3.9
PIN 1 INDEX AREA
1 MAX
0.05
0.00
SEATING PLANE
C
2X 2.5
2.1±0.1
2X
2.5
20X 0.5
1
6
712
13
18
19
24
24X 0.30
0.18
24X 0.50
0.30
(0.2) TYP
PIN 1 ID
(OPTIONAL)
25
{mm ~~~~~~~~~ J
NOTES: (continued)
4. This package is designed to be soldered to a thermal pad on the board. For more information, see Texas Instruments
literature number SLUA271 (www.ti.com/lit/slua271).
5. Solder mask tolerances between and around signal pads can vary based on board fabrication site.
EXAMPLE BOARD LAYOUT
4224376 / C 06/2021
www.ti.com
VQFN - 1 mm max height
RGE0024C
PLASTIC QUAD FLATPACK- NO LEAD
SYMM
SYMM
LAND PATTERN EXAMPLE
SCALE: 20X
2X
(0.8)
2X(0.8)
(3.8)
( 2.1)
1
6
712
13
18
19
24
25
24X (0.6)
24X (0.24)
20X (0.5)
(R0.05)
SOLDER MASK DETAILS
NON SOLDER MASK
DEFINED
(PREFERRED)
SOLDER MASK
DEFINED
0.07 MAX
ALL AROUND
0.07 MIN
ALL AROUND
METAL
SOLDER MASK
OPENING
SOLDER MASK
OPENING
METAL UNDER
SOLDER MASK
(Ø0.2) VIA
TYP
(3.8)
NOTES: (continued)
6. Laser cutting apertures with trapezoidal walls and rounded corners may offer better paste release. IPC-7525 may have alternate
design recommendations..
EXAMPLE STENCIL DESIGN
4224376 / C 06/2021
www.ti.com
VQFN - 1 mm max height
RGE0024C
PLASTIC QUAD FLATPACK- NO LEAD
SYMM
SYMM
SOLDER PASTE EXAMPLE
BASED ON 0.125 mm THICK STENCIL
EXPOSED PAD
80% PRINTED COVERAGE BY AREA
SCALE: 20X
(3.8)
(0.57)
TYP
(0.57)
TYP
4X ( 0.94)
1
6
712
13
18
1924
24X (0.24)
24X (0.6)
20X (0.5)
(R0.05) TYP
METAL
TYP
25
(3.8)
I ,/ x /. \_ , ‘ .\ ,, /x ,, S 1 EL fig
www.ti.com
PACKAGE OUTLINE
C
22X 0.65
2X
7.15
24X 0.30
0.19
TYP
6.6
6.2
1.2 MAX
0.15
0.05
0.25
GAGE PLANE
-80
B
NOTE 4
4.5
4.3
A
NOTE 3
7.9
7.7
0.75
0.50
(0.15) TYP
TSSOP - 1.2 mm max heightPW0024A
SMALL OUTLINE PACKAGE
4220208/A 02/2017
1
12 13
24
0.1 C A B
PIN 1 INDEX AREA
SEE DETAIL A
0.1 C
NOTES:
1. All linear dimensions are in millimeters. Any dimensions in parenthesis are for reference only. Dimensioning and tolerancing
per ASME Y14.5M.
2. This drawing is subject to change without notice.
3. This dimension does not include mold flash, protrusions, or gate burrs. Mold flash, protrusions, or gate burrs shall not
exceed 0.15 mm per side.
4. This dimension does not include interlead flash. Interlead flash shall not exceed 0.25 mm per side.
5. Reference JEDEC registration MO-153.
SEATING
PLANE
A 20
DETAIL A
TYPICAL
SCALE 2.000
gmmmflgmmfij ‘w“““‘+“‘w““‘ Emma—5% R
www.ti.com
EXAMPLE BOARD LAYOUT
0.05 MAX
ALL AROUND 0.05 MIN
ALL AROUND
24X (1.5)
24X (0.45)
22X (0.65)
(5.8)
(R0.05) TYP
TSSOP - 1.2 mm max heightPW0024A
SMALL OUTLINE PACKAGE
4220208/A 02/2017
NOTES: (continued)
6. Publication IPC-7351 may have alternate designs.
7. Solder mask tolerances between and around signal pads can vary based on board fabrication site.
LAND PATTERN EXAMPLE
EXPOSED METAL SHOWN
SCALE: 10X
SYMM
SYMM
1
12 13
24
15.000
METAL
SOLDER MASK
OPENING METAL UNDER
SOLDER MASK SOLDER MASK
OPENING
EXPOSED METAL
EXPOSED METAL
SOLDER MASK DETAILS
NON-SOLDER MASK
DEFINED
(PREFERRED)
SOLDER MASK
DEFINED
fiflmmmmmfimmmfi$% Emma—5%g
www.ti.com
EXAMPLE STENCIL DESIGN
24X (1.5)
24X (0.45)
22X (0.65)
(5.8)
(R0.05) TYP
TSSOP - 1.2 mm max heightPW0024A
SMALL OUTLINE PACKAGE
4220208/A 02/2017
NOTES: (continued)
8. Laser cutting apertures with trapezoidal walls and rounded corners may offer better paste release. IPC-7525 may have alternate
design recommendations.
9. Board assembly site may have different recommendations for stencil design.
SOLDER PASTE EXAMPLE
BASED ON 0.125 mm THICK STENCIL
SCALE: 10X
SYMM
SYMM
1
12 13
24
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