Datenblatt für NCP1593A,9B von onsemi

Datenblatt - Kommentare/Fehler melden

0N Semiconducior® 0 41414141 41414141 [CECE [CECE _||||||_ _||||||_ _ _ _ _ r _ r _ rIIIL rIIIL _..:..:..:J] _..__.._1.:..:.._ FTFFKF FFFFF

August, 2019 − Rev. 2

1Publication Order Number:

NCP1593/D

NCP1593A, NCP1593B

Synchronous Buck

Regulator

1 MHz, 3 A

The NCP1593 is a fixed 1 MHz, high−output−current, synchronous

PWM converter that integrates a low−resistance, high−side P−channel

MOSFET and a low−side N−channel MOSFET. The NCP1593 utilizes

internally compensated current mode control to provide good transient

response, ease of implementation and excellent loop stability. It

regulates input voltages from 4.0 V to 5.5 V down to an output voltage

as low as 0.6 V and is able to supply up to 3 A of load current.

The NCP1593 includes an internally fixed switching frequency

(FSW), and an internal soft−start to limit inrush current. Other features

include cycle−by−cycle current limiting, 100% duty cycle operation,

short− circuit protection, power saving mode and thermal shutdown.

Features

•Wide Input Voltage Range: from 4.0 V to 5.5 V

•Internal 90 mW High−Side P−Channel MOSFET and 60 mW

Low−Side N−Channel MOSFET

•Fixed 1 MHz Switching Frequency

•Cycle−by−Cycle Current Limiting

•Hiccup Mode Short−Circuit Protection

•Overtemperature Protection

•Internal Soft−Start

•Start−up with Pre−Biased Output Load

•Adjustable Output Voltage Down to 0.6 V

•Diode Emulation During Light Load

•100% Duty Cycle Operation to Extend the Battery Life

•These are Pb−Free Devices

Applications

•Set−Top Boxes

•DVD Drives and HDD

•LCD Monitors and TVs

•Cable Modems

•USB Modems

•Telecom/Networking/Datacom Equipment

Device Package Shipping†

ORDERING INFORMATION

NCP1593AMNTWG DFN10

(Pb−Free)

3000 / Tape &

Reel

DFN10

CASE 485C

MARKING

DIAGRAMS

http://onsemi.com

†For information on tape and reel specifications,

including part orientation and tape sizes, please

refer to our Tape and Reel Packaging Specifications

Brochure, BRD8011/D.

VCCP

VCCA

NCP1593A

(Top View)

PIN CONNECTIONS

A = Assembly Location

L = Wafer Lot

Y = Year

W = Work Week

G= Pb−Free Package

1593A

ALYWG

(Note: Microdot may be in either location)

SSPG 4 7

FBEN 5 6

NCP1593BMNTWG

VCCP

VCCA

NCP1593B

(Top View)

NCPG 4 7

FBEN 5 6

1593B

ALYWG

DFN10

(Pb−Free)

3000 / Tape &

Reel

GND

EN FE PG —I CA 13L L ” (J 036 I )— Sun Sun Figure 1. Block Diagram hllp://onsemi.com 2

NCP1593A, NCP1593B

http://onsemi.com

BLOCK DIAGRAM

Figure 1. Block Diagram

−

Soft−Start

Power Reset

UVLO

THD

Hiccup

PWM Control

Logic

OSC

−

NCP1593A

VCCP

PGND

VCC

Vref

PMOS

Power

Good 0.9 x Vref

Rc1

Cc1

Cc2

PIN DESCRIPTIONS

Pin No Symbol Description

1NC / LX No connect pin for NCP1593A. The user may ground this pin or leave it floating. / LX pin for NCP1593B

2, 3 LX The drains of the internal MOSFETs. The output inductor should be connected to these pins.

4 PG Open drain output from the Power Good logic. When the FB voltage is within regulation, this is a high

impedance pin. Otherwise it is pulled low.

5 EN Logic input to enable the part. Logic high to turn on the part and a logic low to shut off the part. An intern-

al pullup forces the part into an enable state when no external bias is present on the pin.

6 FB Feedback input pin of the Error Amplifier. Connect a resistor divider from the converter’s output voltage

to this pin to set the converter’s regulated voltage.

7SS / NC An external capacitor on this pin sets the soft−start ramp time. Leaving this pin open sets the soft−start

time at 500 ms. For NCP1593B this pin is a no connect and should be left floating.

8 VCC Input supply pin for internal bias circuitry. Connect a 0.1 mF ceramic bypass capacitor to this pin. Directly

connect the VCC pin to the VCCP pin on the board.

9, 10 VCCP Input for the power stage

EP GND Exposed pad of the package provides both electrical contact to the ground and good thermal contact to

the PCB. This pad must be soldered to the PCB for proper operation.

E VCCA :2“: _5. EN .—4Pe 7ss 3 g LX “5 6 5 FB 2 NC —‘ PGND EF J.— __.:L_T Figure 2. Recommended Application Circuit hilp://onsemi.com 3

NCP1593A, NCP1593B

http://onsemi.com

APPLICATION CIRCUIT

Figure 2. Recommended Application Circuit

VCCP

VCCA

4.0 V − 5.5 V

Vin Vout

PGND

9,10

NCP1593

22 mF

22 mF22

2.2 mH

ABSOLUTE MAXIMUM RATINGS

Rating Symbol Value Unit

Power Supply Pin (Pins 8, 9, 10) to GND Vin 6.5

−0.3 (DC)

−1.0 (t < 100 ns)

LX to GND Vin + 0.7

Vin + 1.0 (t < 20 ns)

−0.7 (DC)

−5.0 (t < 100 ns)

All other pins 6.0

−0.3 (DC)

−1.0 (t < 100 ns)

Operating Ambient Temperature Range (Note 1) TA−40 to +85 °C

Operating Junction Temperature Range (Note 1) TJ−40 to +125 °C

Maximum Junction Temperature TJ(MAX) +150 °C

Storage Temperature Range TS−55 to +150 °C

Thermal Resistance Junction−to−Air (Note 2) RqJA 68 °C/W

Stresses exceeding Maximum Ratings may damage the device. Maximum Ratings are stress ratings only. Functional operation above the

Recommended Operating Conditions is not implied. Extended exposure to stresses above the Recommended Operating Conditions may affect

device reliability.

1. The maximum package power dissipation limit must not be exceeded.

PD+

TJ(max) *TA

RqJA

2. RqJA measured on approximately 1x1 inch sq. of 1 oz. Copper FR−4 or G−10 board.

NCP1593A, NCP1593B

http://onsemi.com

ELECTRICAL CHARACTERISTICS (−40°C < TJ < 125°C, VCC = 4.0 V − 5.5 V, for min/max values unless noted otherwise)

Parameter Symbol Test Conditions Min Typ Max Unit

Input Voltage Range VIN 4.0 5.5 V

VCC UVLO Threshold VUVLO 2.4 2.5 2.9 V

UVLO Hysteresis VUVLO_hys 320 mV

VCC Quiescent Current IINVCC 1.0 1.5 mA

VCCP Quiescent Current IINVCCP 20 50 mA

Shutdown Supply Current IQSHDN 1.8 3.0 mA

FEEDBACK VOLTAGE

Reference Voltage VFB 0.591 0.6 0.609 V

Reference Voltage VFB TJ = 25°C 0.594 0.6 0.606 V

Feedback Input Bias Current IFB 10 100 nA

Feedback Voltage Line Regulation (Note 3) VCC = 4.0 V to 5.5 V −65 dB

PWM

Maximum Duty Cycle (Regulating) d.c.MAX 95 %

Maximum Duty Cycle (LDO mode) d.c.LDO Vout > d.c.MAX * VIN 100 %

Minimum Controllable On Time tONmin 35 ns

Current Limit

Cycle-by-cycle Current Limit (Note 3) ILIM VCC = 5.0 V, TJ = 25°C 5.1 A

Oscillator

Switching Frequency fSW 0.87 1.0 1.13 MHz

MOSFET’s

High-Side MOSFET On Resistance RDSonH IDS = 100 mA, VIN = 5.0 V 90 190 mW

High-Side MOSFET Leakage IlkgH LX = 0 V 10 mA

Low-Side MOSFET On Resistance RDSonL IDS = 100 mA, VIN = 5.0 V 60 90 mW

Low-Side MOSFET Leakage IlkgL LX = 5 V 10 mA

POWER GOOD

Power Good Rising Threshold VPGH 0.51 0.54 V

Power Good Falling Threshold VPHL 0.48 0.51 V

Power Good Hysteresis (High-to-Low) VPGhys 30 mV

Power Good Pulldown Voltage VRPG IPG = 2.5 mA 130 250 mV

ENABLE

Enable High Threshold VENHI 1.4 V

Enable Low Threshold VENLO 0.4 V

Enable Hysteresis VENhys 200 mV

Enable Pullup Current IEN 1.4 3.0 mA

Soft-Start

Default Soft-start Ramp Time tSS SS = open; fSW = 1MHz 0.5 0.58 0.65 ms

Maximum Soft-start Ramp time tSS SS = max cap; fSW = 1MHz 10 ms

Hiccup Timer 4 * tSS ms

Soft-start Current ISS 0.51 0.7 0.87 mA

Thermal Shutdown

Thermal Shutdown Threshold 185 °C

Thermal Shutdown Hysteresis 30 °C

3. Guaranteed by Characterization.

NCP1593A, NCP1593B

http://onsemi.com

TYPICAL CHARACTERISTICS

Figure 3. Efficiency vs. Output Current (3.3 V) Figure 4. Efficiency vs. Output Current (1.8 V)

IOUT

, OUTPUT CURRENT (A) IOUT

, OUTPUT CURRENT (A)

1010.10.01

100

Figure 5. Efficiency vs. Output Current (1.05 V) Figure 6. Load Regulation (3.3 V)

IOUT

, OUTPUT CURRENT (A) IOUT

, OUTPUT CURRENT (A)

2.01.61.21.00.80.60.20

3.20

3.22

3.26

3.28

3.32

3.34

3.38

3.40

Figure 7. Load Regulation (1.8 V) Figure 8. Load Regulation (1.05 V)

IOUT

, OUTPUT CURRENT (A) IOUT

, OUTPUT CURRENT (A)

2.01.41.20.80.60.40.20

1.70

1.72

1.76

1.78

1.82

1.84

1.88

1.90

2.01.61.00.80.60.40.20

0.95

0.97

1.01

1.03

1.05

1.09

1.11

1.15

EFFICIENCY (%)

VOUT

, OUTPUT VOLTAGE (V)

VOUT

, OUTPUT VOLTAGE (V)

VOUT

, OUTPUT VOLTAGE (V)

VIN = 4.5 V

VIN = 5.0 V

1010.10.01

100

VIN = 4.0 V

VIN = 5.0 V

3.24

3.30

3.36

0.4 1.4 1.8

VIN = 4.5 V

VIN = 5.0 V

1010.10.01

100

VIN = 4.0 V

VIN = 5.0 V

VIN = 4.5 V

VIN = 5.0 V

1.0 1.6 1.8

1.74

1.80

1.86

1.2 1.4 1.8

0.99

1.07

1.13

VIN = 4.5 V

VIN = 5.0 V

/ \V / / P-MOSFET (Hsp / ‘ / ‘l / / ~—......_..___. // ‘ /

NCP1593A, NCP1593B

http://onsemi.com

TYPICAL CHARACTERISTICS

Figure 9. Current Limit vs. Temperature Figure 10. Current Limit vs. Input Voltage

TJ, JUNCTION TEMPERATURE (°C) INPUT VOLTAGE (V)

1108065205−10−25−40

3.50

3.75

4.00

4.25

4.50

4.75

5.00

5.505.255.004.754.504.254.00

3.50

3.75

4.00

4.25

4.75

5.00

5.25

5.50

Figure 11. RDS(ON) vs. Temperature

Figure 12. Load Transient Response

TJ, JUNCTION TEMPERATURE (°C)

11085603510−15−40

105

115

125

Figure 13. Load Transient Response Figure 14. No Load Switching (1.05 V)

PEAK CURRENT LIMIT (A)

RDS(ON) (mW)

35 50 95 125

VIN = 5.0 V

P−MOSFET (HS)

N−MOSFET (LS)

4.50

(VIN = 5 V, VOUT = 1.05 V, IOUT = 0.5 A to 3.0 A)

Upper Trace: Output Voltage, 50 mV / div

Lower Trace: Output Current, 2 A / div

Time = 200 ms/div

(VIN = 5 V, VOUT = 1.05 V, IOUT = 0.5 A to 3.0 A)

Upper Trace: Output Voltage, 50 mV / div

Lower Trace: Output Current, 2 A / div

Time = 200 ms/div

(VIN = 5 V, VOUT = 1.05 V, IOUT = 0 A)

Upper Trace: LX Pin Switching Waveforms, 5 V / div

Middle Trace: Output Voltage, 20 mV / div

Lower Trace: Inductor Current, 100 mA / div

Time = 20 ms / div

:‘ P-v-vu' PW” _""v’ ‘ ,m, ,_..

NCP1593A, NCP1593B

http://onsemi.com

TYPICAL CHARACTERISTICS

Figure 15. No Load Switching (1.8 V) Figure 16. No Load Switching (3.3 V)

Figure 17. DCM Switching (1.05 V) Figure 18. DCM Switching (1.8 V)

Figure 19. DCM Switching (3.3 V) Figure 20. CCM Switching (1.8 V)

(VIN = 5 V, VOUT = 1.8 V, IOUT = 0 A)

Upper Trace: LX Pin Switching Waveforms, 5 V / div

Middle Trace: Output Voltage, 20 mV / div

Lower Trace: Inductor Current, 100 mA / div

Time = 10 ms / div

(VIN = 5 V, VOUT = 3.3 V, IOUT = 0 A)

Upper Trace: LX Pin Switching Waveforms, 5 V / div

Middle Trace: Output Voltage, 20 mV / div

Lower Trace: Inductor Current, 200 mA / div

Time = 10 ms / div

(VIN = 5 V, VOUT = 1.05 V, IOUT = 100 mA)

Upper Trace: LX Pin Switching Waveforms, 5 V / div

Middle Trace: Output Voltage, 20 mV / div

Lower Trace: Inductor Current, 200 mA / div

Time = 500 ns / div

(VIN = 5 V, VOUT = 1.8 V, IOUT = 150 A)

Upper Trace: LX Pin Switching Waveforms, 5 V / div

Middle Trace: Output Voltage, 20 mV / div

Lower Trace: Inductor Current, 200 mA / div

Time = 500 ns / div

(VIN = 5 V, VOUT = 3.3 V, IOUT = 100 mA)

Upper Trace: LX Pin Switching Waveforms, 5 V / div

Middle Trace: Output Voltage, 20 mV / div

Lower Trace: Inductor Current, 200 mA / div

Time = 500 ns / div

(VIN = 5 V, VOUT = 1.8 V, IOUT = 3 A)

Upper Trace: LX Pin Switching Waveforms, 5 V / div

Middle Trace: Output Voltage, 20 mV / div

Lower Trace: Inductor Current, 2 A / div

Time = 500 ns / div

NCP1593A, NCP1593B

http://onsemi.com

TYPICAL CHARACTERISTICS

Figure 21. Power On from Input Voltage Figure 22. Power Off from Input Voltage

Figure 23. Power On from Enable Figure 24. Power On from Enable CSS = 4.7 n

Figure 25. Power Off from Enable Figure 26. Short Circuit Operation

(VIN = 5 V, VOUT = 1.8 V, IOUT = 3 A)

Upper Trace: Input Voltage, 5 V / div

Second Trace: Power Good Pin Voltage, 5 V / div

Third Trace: Output Voltage, 2 V / div

Lower Trace: Inductor Current, 2 A / div

Time = 1 ms / div

(VIN = 5 V, VOUT = 1.8 V, IOUT = 3 A)

Upper Trace: Input Voltage, 5 V / div

Second Trace: Power Good Pin Voltage, 5 V / div

Third Trace: Output Voltage, 2 V / div

Lower Trace: Inductor Current, 2 A / div

Time = 200 ms / div

(VIN = 5 V, VOUT = 1.8 V, IOUT = 3 A, no CSS)

Upper Trace: Enable Pin Voltage, 5 V / div

Second Trace: Power Good Pin Voltage, 5 V / div

Third Trace: Output Voltage, 2 V / div

Lower Trace: Inductor Current, 2 A / div

Time = 2 ms / div

(VIN = 5 V, VOUT = 1.8 V, IOUT = 3 A, CSS = 4.7 nF)

Upper Trace: Enable Pin Voltage, 5 V / div

Second Trace: Power Good Pin Voltage, 5 V / div

Third Trace: Output Voltage, 2 V / div

Lower Trace: Inductor Current, 2 A / div

Time = 2 ms / div

(VIN = 5 V, VOUT = 1.8 V, IOUT = 3 A)

Upper Trace: Enable Pin Voltage, 5 V / div

Second Trace: Power Good Pin Voltage, 5 V / div

Third Trace: Output Voltage, 2 V / div

Lower Trace: Inductor Current, 2 A / div

Time = 200 ms / div

(VIN = 5 V, VOUT = 1.8 V, IOUT = Current Limit, no CSS)

Upper Trace: LX Pin Voltage, 5 V / div

Middle Trace: Output Voltage, 2 V / div

Lower Trace: Inductor Current, 2 A / div

Time = 500 ms / div

NCP1593A, NCP1593B

http://onsemi.com

DETAILED DESCRIPTION

Overview

The NCP1593 is a synchronous PWM controller that

incorporates all the control and protection circuitry

necessary to satisfy a wide range of applications. The

NCP1593 employs current mode control to provide fast

transient response, simple compensation, and excellent

stability. The features of the NCP1593 include a precision

reference, fixed 1 MHz switching frequency, a

transconductance error amplifier, an integrated high−side

P−channel MOSFET and low−side N−Channel MOSFET,

internal soft−start, and very low shutdown current. The

protection features of the NCP1593 include internal

soft−start, pulse−by−pulse current limit, and thermal

shutdown.

Reference Voltage

The NCP1593 incorporates an internal reference that

allows output voltages as low as 0.6 V. The tolerance of the

internal reference is guaranteed over the entire operating

temperature range of the controller. The reference voltage is

trimmed using a test configuration that accounts for error

amplifier offset and bias currents.

Oscillator Frequency

A fixed precision oscillator is provided. The oscillator

frequency range is 1 MHz with $13% variation.

Transconductance Error Amplifier

The transconductance error amplifier’s primary function

is to regulate the converter’s output voltage using a resistor

divider connected from the converter’s output to the FB pin

of the controller, as shown in the applications schematic. If

a Fault occurs, the amplifier’s output is immediately pulled

to GND and PWM switching is inhibited.

Soft−Start

To limit the startup inrush current, a soft−start circuit is

used to ramp up the reference voltage from 0 V to its final

value linearly. This soft−start time is internally set to a typical

value of 500 ms, or it can be externally adjusted by adding a

capacitor (CSS) from the SS pin to GND. The following

formulas show how to set the externally adjustable soft-start

time. The maximum allowable CSS is 10 nF.

tSS +ǒCSS VFBǓ

ISS

(eq. 1)

Where:

VFB: Reference voltage, typically 0.6 V

ISS: Soft−start current, typically 0.7 mA

Output MOSFETs

The NCP1593 includes low RDS(on), both high−side

P−channel and low−side N−channel MOSFETs capable of

delivering up to 3.0 A of current. When the controller is

disabled or during a Fault condition, the controller’s output

stage is tri−stated by turning OFF both the upper and lower

MOSFETs.

Pulse Width Modulation

A high−speed PWM comparator, capable of pulse widths

as low as 35 ns, is included in the NCP1593. The inverting

input of the comparator is connected to the output of the

error amplifier. The non−inverting input is connected to the

the current sense signal. At the beginning of each PWM

cycle, the CLK signal sets the PWM flip−flop and the upper

MOSFET is turned ON. When the current sense signal rises

above the error amplifier’s voltage then the comparator will

reset the PWM flip−flop and the upper MOSFET will be

turned OFF.

Current Sense

The NCP1593 monitors the current in the upper

MOSFET. The current signal is required by the PWM

comparator and the pulse−by−pulse current limiter.

NCP1593A, NCP1593B

http://onsemi.com

PROTECTIONS

Undervoltage Lockout (UVLO)

The under voltage lockout feature prevents the controller

from switching when the input voltage is too low to power

the internal power supplies and reference. Hysteresis is

incorporated in the UVLO comparator to prevent resistive

drops in the wiring or PCB traces from causing ON/OFF

cycling of the controller during heavy loading at power up

or power down.

Overcurrent Protection (OCP)

NCP1593 detects high side switch current and then

compares to a voltage level representing the overcurrent

threshold limit. If the current through the high side FET

exceeds the overcurrent threshold limit for seven

consecutive switching cycles, overcurrent protection is

triggered.

Once the overcurrent protection occurs, hiccup mode

engages. First, hiccup mode, turns off both FETs and

discharges the internal compensation network at the output

of the OTA. Next, the IC waits typically 4 x tSS ms and then

resets the overcurrent counter. After this reset, the circuit

attempts another normal soft−start. Hiccup mode reduces

input supply current and power dissipation during a short

circuit. It also allows for much improved system up−time,

allowing auto−restart upon removal of a temporary

short−circuit.

Pre−Bias Startup

In some applications the controller will be required to start

switching when it’s output capacitors are charged anywhere

from slightly above 0 V to just below the regulation voltage.

This situation occurs for a number of reasons: the

converter’s output capacitors may have residual charge on

them or the converter’s output may be held up by a low

current standby power supply. NCP1593 supports pre−bias

start up by holding off switching off until the soft start ramp

reaches the FB Pin voltage.

Power Good

Power Good (PG) is an open-drain output that requires a

pull−up resistor. It is actively held low in soft−start, standby,

and shutdown. PG releases when the FB voltage and thus the

output voltage rises above 90% of nominal regulation point.

The PG goes low when the FB voltage falls below 85% of

the regulation point.

Thermal Shutdown

The NCP1593 protects itself from over heating with an

internal thermal monitoring circuit. If the junction

temperature exceeds the thermal shutdown threshold both

the upper and lower MOSFETs will be shut OFF.

F iiiiii

NCP1593A, NCP1593B

http://onsemi.com

APPLICATION INFORMATION

Programming the Output Voltage

The output voltage is set using a resistive voltage divider

from the output voltage to FB pin (see Figure 27). So the

output voltage is calculated according to Eq.1.

Vout +VFB @

R1)R2

(eq. 2)

Figure 27. Output divider

Vout

Inductor Selection

The inductor is the key component in the switching

regulator. The selection of inductor involves trade−offs

among size, cost and efficiency. The inductor value is

selected according to the equation 2.

L+

Vout

f@Iripple

@ǒ1*

Vout

Vin(max)Ǔ(eq. 3)

Where Vout − the output voltage;

f − switching frequency, 1.0 MHz;

Iripple − Ripple current, usually it’s 20% − 30% of output

current;

Vin(max) − maximum input voltage.

Choose a standard value close to the calculated value to

maintain a maximum ripple current within 30% of the

maximum load current. If the ripple current exceeds this

30% limit, the next larger value should be selected.

The inductor’s RMS current rating must be greater than

the maximum load current and its saturation current should

be about 30% higher. For robust operation in fault conditions

(start−up or short circuit), the saturation current should be

high enough. To keep the efficiency high, the series

resistance (DCR) should be less than 0.1 W, and the core

material should be intended for high frequency applications.

Output Capacitor Selection

The output capacitor acts to smooth the dc output voltage

and also provides energy storage. So the major parameter

necessary to define the output capacitor is the maximum

allowed output voltage ripple of the converter. This ripple is

related to capacitance and the ESR. The minimum

capacitance required for a certain output ripple can be

calculated by Equation 4.

COUT(min) +

Iripple

8@f@Vripple

(eq. 4)

Where Vripple is the allowed output voltage ripple.

The required ESR for this amount of ripple can be

calculated by equation 5.

ESR +

Vripple

Iripple

(eq. 5)

Based on Equation 3 to choose capacitor and check its

ESR according to Equation 4. If ESR exceeds the value from

Eq.4, multiple capacitors should be used in parallel.

Ceramic capacitor can be used in most of the applications.

In addition, both surface mount tantalum and through−hole

aluminum electrolytic capacitors can be used as well.

Input Capacitor Selection

The input capacitor can be calculated by Equation 6.

Cin(min) +Iout(max) @Dmax @1

f@Vin(ripple)

(eq. 6)

Where Vin(ripple) is the required input ripple voltage.

Dmax +

Vout

Vin(min)

is the maximum duty cycle. (eq. 7)

Power Dissipation

The NCP1593 is available in a thermally enhanced

10−pin, DFN package. When the die temperature reaches

+185°C, the NCP1593 shuts down (see the

Thermal−Overload Protection section). The power

dissipated in the device is the sum of the power dissipated

from supply current (PQ), power dissipated due to switching

the internal power MOSFET (PSW), and the power

dissipated due to the RMS current through the internal

power MOSFET (PON). The total power dissipated in the

package must be limited so the junction temperature does

not exceed its absolute maximum rating of +150°C at

maximum ambient temperature. Calculate the power lost in

the NCP1593 using the following equations:

1. High side MOSFET

The conduction loss in the top switch is:

PHSON +I2RMS_HSFET RDS(on)HS (eq. 8)

Where:

IRMS_FET +ǒIout 2)

DIPP 2

12 Ǔ D

Ǹ(eq. 9)

DIPP is the peak−to−peak inductor current ripple.

The power lost due to switching the internal power high side

MOSFET is:

NCP1593A, NCP1593B

http://onsemi.com

PHSSW +

Vin @Iout @ǒtr)tfǓ@fSW

(eq. 10)

tr and tf are the rise and fall times of the internal power

MOSFET measured at SW node. Typical rise times are 4 ns

(rising) and 2 ns (falling).

2. Low side MOSFET

The power dissipated in the top switch is:

PLSON +IRMS_LSFET 2@RDS(on)LS (eq. 11)

Where:

IRMS_LSFET +ǒIout 2)

DIPP 2

12 Ǔ@(1*D)

Ǹ(eq. 12)

DIPP is the peak−to−peak inductor current ripple.

The switching loss for the low side MOSFET can be

ignored.

The power lost due to the quiescent current (IQ) of the device

is:

PQ+Vin @IQ(eq. 13)

IQ is the switching quiescent current of the NCP1593.

PTOTAL +PHSON )PHSSW )PLSON )PQ(eq. 14)

Calculate the temperature rise of the die using the following

equation:

TJ+TC)ǒPTOTAL @qJAǓ(eq. 15)

qJC is the junction−to−case thermal resistance equal to

68°C/W. TA is the ambient temperature and TJ is the junction

temperature, or die temperature. Solder the

underside−exposed pad to a large copper GND plane. If the

die temperature reaches the thermal shutdown threshold the

NCP1593 shut down and does not restart again until the die

temperature cools by 30°C.

Layout Consideration

As with all high frequency switchers, when considering

layout, care must be taken in order to achieve optimal

electrical, thermal and noise performance. For 1.0MHz

switching frequency, switch rise and fall times are typically

in few nanosecond range. To prevent noise both radiated and

conducted the high speed switching current path must be

kept as short as possible. Shortening the current path will

also reduce the parasitic trace inductance of approximately

25 nH/inch. At switch off, this parasitic inductance

produces a flyback spike across the NCP1593 switch. When

operating at higher currents and input voltages, with poor

layout, this spike can generate voltages across the NCP1593

that may exceed its absolute maximum rating. A ground

plane should always be used under the switcher circuitry to

prevent interplane coupling and overall noise.

The FB component should be kept as far away as possible

from the switch node. The ground for these components

should be separated from the switch current path. Failure to

do so will result in poor stability or subharmonic like

oscillation.

Board layout also has a significant effect on thermal

resistance. Reducing the thermal resistance from ground pin

and exposed pad onto the board will reduce die temperature

and increase the power capability of the NCP1593. This is

achieved by providing as much copper area as possible

around the exposed pad. Adding multiple thermal vias under

and around this pad to an internal ground plane will also

help. Similar treatment to the inductor pads will reduce any

additional heating effects.

MECHANICAL CASE OUTLINE PACKAGE DIMENSIONS 0N Semiwndudw" DFN10, 3x3, 0.5P 0 CASE 4350 ISSUE E SCALE 2:1 DATE 11 FEB 2016 <7 @="" %="" notes="" l="" l="" i="" dimensioningandtolerancingperasmeviasm.1590="" i3="" 2="" controlling="" dimension="" millimeters="" i="" j="" t="" dimension="" d="" applies="" to="" plated="" terminalano="" is="" i="" l1="" measdred="" detineen="" d="" e.="" and="" d="" td="" mm="" erom="" terminal="" a="" coplanaritv="" applies="" to="" the="" exposed="" pad="" as="" well="" as="" i="" alternate="" a.i="" alternate="" a—z="" itie="" terminals="" i="" 5="" terminal="" d="" may="" have="" mold="" oompodnd="" material="" alono="" detail="" a="" side="" edge="" mold="" flashing="" may="" not="" exceed="" td="" microns="" fin="" on:="" e="" 7="" 7="" 7="" ’="" e="" alternate="" 1erminal="" on="" bottom="" surface="" of="" terminal="" d="" reference="" consyrmcyions="" s="" for="" device="" opn="" coniaining="" w="" option="" detaila="" and="" d="" alternate="" oonstrdotion="" are="" not="" applioadle="" wet="" tadle="" flank="" construction="" is="" detail="" d="" as="" shown="" on="" 2x="" q="" 0.i5="" c="" side="" view="" of="" package="" i="" ~="" \="" a3="" exposed="" cd="" mold="" cmpd="" millimeters="" 2x="" dim="" min="" max="" e.="" c="" top="" view="" 11%="" wa/="" a="" ddd="" idd="" t="" l="" l="" at="" d="" dd="" d="" de="" a1="" \="" a}="" d="" 2d="" ref="" detail="" b="" (ajie="" alternate="" d.i="" alternate="" 3.2="" d="" did="" i="" d="" 30="" 0.iii="" c="" i="" d="" jddesc="" detailb="" dd="" sad="" i="" edd="" alternate="" e="" t="" dd="" esc="" sonstpitdttons="" e2="" i="" 70="" i="" i="" sd="" ‘nx="" e="" n="" 50="" e50="" a1="" a="" m="" k="" d="" is="" wp="" side="" view="" \="" l="" (135="" i="" n45="" i="" i:i="" lt="" d="" dd="" i="" d="" id="" ”eva“="" d="" w="" l="" m="" generic="" i="" \="" i="" s="" i="" marking="" diagram‘="" detail="" a="" v="" wetiable="" flank="" opyion="" °="" consyrucyion="" xxxxx="" i="" xxxxx="" 7="" +="" e="" e2="" ava-="" i="" .="" xxxxx="" deciiie="" device="" code="" a="" e="" asseitidiy="" location="" id="" i="" d="" id="" b="" l="" waiet="" lot="" o.iti="" c="" aibi="" v="" 495'="" a)="" w="" work="" week="" bottom="" vtew="" 0.05="" 0="" note="" s="" pb="" f="" -="" —="" tee="" package="" soldering="" footprint“="" inx="" i="" 055="" it="" «2644»="" ‘e'ei'eij'ei'ei="" package="" outline="" i80="" i="" +="" i="" 3="" 30="" j_l="" i="" idx="" 7="" 0,30="" 0.50»="" pitch="" dimensions="" millimeters="" ~fot="" addttiottei="" inioimaiion="" oti="" odt="" pb-free="" sitaiegy="" and="" soideting="" deiaiisi="" piease="" download="" the="" on="" semlcondudol="" soidetitig="" and="" mouniing="" teaniodes="" reietettce="" manuaii="" solderrm/d,="" (noie.="" mtctant="" may="" be="" in="" eimet="" iocatiotii="" “iris="" iniotmeiiott="" ts="" genenc.="" please="" teiet="" m="" device="" daia="" sneet="" tot="" actual="" pen="" markmg.="" pd—ftee="" indlcamn="" “a“="" ot="" mietani="" “="" may="" or="" may="" noi="" be="" present.="" on="" semieaaddddi="" sad="" j="" tsdemsms="" oi="" semddrdddtat="" odmdaaens="" mas...e="" tidtiis="" di="" dttiets="" s.="" llc="" dba="" on="" settiiddtidddtdt="" dt="" its="" sddsididties="" iti="" ttie="" otiited="" stetes="" etididt="" ditiei="" dddtiities="" on="" settiiddtidddtdt="" iesewes="" ttie="" tidtii="" td="" make="" dtietides="" nittiddt="" idtttiet="" tidtlde="" to="" any="" dtddddts="" neieiti="" on="" settiiddtidddidi="" makes="" tid="" wetietiiy.="" tedtesetitetidti="" di="" ddetetitee="" tegstditid="" itie="" sdiiddiiity="" di="" ils="" dtdd="" ts="" idt="" any="" ddniddidi="" ddtddse="" tidi="" ddes="" on="" settiiddtidddtdi="" essdttie="" etiy="" iiediiity="" eiisitid="" ddt="" di="" ttie="" eddtideiidti="" dt="" dse="" di="" any="" dtddddt="" di="" ditddit="" etid="" sdediiidetiy="" disdieittis="" etiy="" etid="" eti="" iie="" ity="" itididditid="" witdddi="" iitiiiidiidti="" sdediei="" ddtiseddetiiiei="" dt="" itididentei="" demedes="" on="" setiiimtidddtdt="" ddes="" tidt="" ddtwey="" etiy="" iidetise="" dtidet="" its="" detetii="" tidtits="" tidt="" ttie="">

DFN10, 3x3, 0.5P

CASE 485C

ISSUE E

DATE 11 FEB 2016

SCALE 2:1

10X

SEATING

PLANE

0.15 C

10 6

NOTES:

1. DIMENSIONING AND TOLERANCING PER ASME Y14.5M, 1994.

2. CONTROLLING DIMENSION: MILLIMETERS.

3. DIMENSION b APPLIES TO PLATED TERMINAL AND IS

MEASURED BETWEEN 0.25 AND 0.30 MM FROM TERMINAL.

4. COPLANARITY APPLIES TO THE EXPOSED PAD AS WELL AS

THE TERMINALS.

5. TERMINAL b MAY HAVE MOLD COMPOUND MATERIAL ALONG

SIDE EDGE. MOLD FLASHING MAY NOT EXCEED 30 MICRONS

ONTO BOTTOM SURFACE OF TERMINAL b.

6. FOR DEVICE OPN CONTAINING W OPTION, DETAIL A AND B

ALTERNATE CONSTRUCTION ARE NOT APPLICABLE. WET-

TABLE FLANK CONSTRUCTION IS DETAIL B AS SHOWN ON

SIDE VIEW OF PACKAGE.

0.15 CTOP VIEW

SIDE VIEW

BOTTOM VIEW

PIN ONE

REFERENCE

0.10 C

0.08 C

(A3)

10X

0.10 C

0.05 C

A B

NOTE 3

DIM MIN MAX

MILLIMETERS

A0.80 1.00

A1 0.00 0.05

A3 0.20 REF

b0.18 0.30

D3.00 BSC

D2 2.40 2.60

E3.00 BSC

E2 1.70 1.90

e0.50 BSC

L0.35 0.45

L1 0.00 0.03

DETAIL A

K0.19 TYP

DETAIL B

*For additional information on our Pb−Free strategy and soldering

details, please download the ON Semiconductor Soldering and

Mounting Techniques Reference Manual, SOLDERRM/D.

SOLDERING FOOTPRINT*

GENERIC

MARKING DIAGRAM*

XXXXX = Specific Device Code

A = Assembly Location

L = Wafer Lot

Y = Year

W = Work Week

G= Pb−Free Package

XXXXX

ALYWG

*This information is generic. Please refer to

device data sheet for actual part marking.

Pb−Free indicator, “G” or microdot “ G”,

may or may not be present.

(Note: Microdot may be in either location)

DETAIL B

MOLD CMPDEXPOSED Cu

ALTERNATE

CONSTRUCTIONS

2.64

1.90

0.50

0.55

10X

3.30

0.30

10X

DIMENSIONS: MILLIMETERS

PITCH

PACKAGE

OUTLINE

DETAIL A

ALTERNATE TERMINAL

CONSTRUCTIONS

ALTERNATE B−2ALTERNATE B−1

ALTERNATE A−2ALTERNATE A−1

DETAIL B

WETTABLE FLANK OPTION

CONSTRUCTION

MECHANICAL CASE OUTLINE

PACKAGE DIMENSIONS

ON Semiconductor and are trademarks of Semiconductor Components Industries, LLC dba ON Semiconductor or its subsidiaries in the United States and/or other countries.

ON Semiconductor reserves the right to make changes without further notice to any products herein. ON Semiconductor makes no warranty, representation or guarantee regarding

the suitability of its products for any particular purpose, nor does ON Semiconductor assume any liability arising out of the application or use of any product or circuit, and specifically

disclaims any and all liability, including without limitation special, consequential or incidental damages. ON Semiconductor does not convey any license under its patent rights nor the

rights of others.

98AON03161D

DOCUMENT NUMBER:

DESCRIPTION:

Electronic versions are uncontrolled except when accessed directly from the Document Repository.

Printed versions are uncontrolled except when stamped “CONTROLLED COPY” in red.

PAGE 1 OF 1

DFN10, 3X3 MM, 0.5 MM PITCH

a a e lrademavks av Semxcunduclm Cnmvnnems In "sine \ghlsmanumhernlpalems \rademavks Dav www menu cumrsuerguwaxem Mavkmg gm 9 www nnserm cum

www.onsemi.com

ON Semiconductor and are trademarks of Semiconductor Components Industries, LLC dba ON Semiconductor or its subsidiaries in the United States and/or other countries.

ON Semiconductor owns the rights to a number of patents, trademarks, copyrights, trade secrets, and other intellectual property. A listing of ON Semiconductor’s product/patent

coverage may be accessed at www.onsemi.com/site/pdf/Patent−Marking.pdf. ON Semiconductor reserves the right to make changes without further notice to any products herein.

ON Semiconductor makes no warranty, representation or guarantee regarding the suitability of its products for any particular purpose, nor does ON Semiconductor assume any liability

arising out of the application or use of any product or circuit, and specifically disclaims any and all liability, including without limitation special, consequential or incidental damages.

Buyer is responsible for its products and applications using ON Semiconductor products, including compliance with all laws, regulations and safety requirements or standards,

regardless of any support or applications information provided by ON Semiconductor. “Typical” parameters which may be provided in ON Semiconductor data sheets and/or

specifications can and do vary in different applications and actual performance may vary over time. All operating parameters, including “Typicals” must be validated for each customer

application by customer’s technical experts. ON Semiconductor does not convey any license under its patent rights nor the rights of others. ON Semiconductor products are not

designed, intended, or authorized for use as a critical component in life support systems or any FDA Class 3 medical devices or medical devices with a same or similar classification

in a foreign jurisdiction or any devices intended for implantation in the human body. Should Buyer purchase or use ON Semiconductor products for any such unintended or unauthorized

application, Buyer shall indemnify and hold ON Semiconductor and its officers, employees, subsidiaries, affiliates, and distributors harmless against all claims, costs, damages, and

expenses, and reasonable attorney fees arising out of, directly or indirectly, any claim of personal injury or death associated with such unintended or unauthorized use, even if such

claim alleges that ON Semiconductor was negligent regarding the design or manufacture of the part. ON Semiconductor is an Equal Opportunity/Affirmative Action Employer. This

literature is subject to all applicable copyright laws and is not for resale in any manner.

PUBLICATION ORDERING INFORMATION

TECHNICAL SUPPORT

North American Technical Support:

Voice Mail: 1 800−282−9855 Toll Free USA/Canada

Phone: 011 421 33 790 2910

LITERATURE FULFILLMENT:

Email Requests to: orderlit@onsemi.com

ON Semiconductor Website: www.onsemi.com

Europe, Middle East and Africa Technical Support:

Phone: 00421 33 790 2910

For additional information, please contact your local Sales Representative

◊

Datenblatt für NCP1593A,9B von onsemi

INFORMATION

HILFE

KONTAKT

FOLGEN SIE UNS