Datenblatt für NTHC5513 von onsemi

MOSFET as.» U Designed for Power Management Applications in Portable, Battery Powered Products MAXIMUM RATINGS (TJ : 25§C untess otherwtse noled) Parameter Symbol Value Unlt Drain—m-Source Voltage vD55 20 v Gate—to—Source Vottage v95 :12 v Continuous Dram N—Ch TA : 25°C 1.; 2,9 A Current (Note 1) Sleady 5.3m TA : 85°C 21 I S 5 TA : 25°C 39 P-Ch TA : 25cc 1.; —2.2 A Sleady SIaIe TA : 55°C -I .6 IS 5 TA : 25°C -3.0 Pulsed Drarn Current N—Ch to us IBM 12 A mate 1) P-Ch te to us —9.0 Power nrssrpatron Sleady a PD 11 w tNote 1) State TA : 25 C I S 5 TA : 25°C 21 ooeratmg Junction and Storage Tu, —55 to no Temperature 15m t 50 Lead Temperature for Sotdermg Purposes TL 250 cc 11/5" trom case for to seconds) Stresses exceedrng those tisted 1n Ihe Maxrmum Ratmgs table may damage Ihe devrce, It any at these time are exceeded device Iuncltonamy should nol be assumed damage may occur and retranitiry may be attected. 1 Surface Mounted on FRA board usrng1 m so pad size (Cu area : 1.1271n sq [1 oz] 1nclud1ng traces). n Semmunduclurcamvunenu nous-"es LLC 2016 May, 2019— Rev. 5 0N Semiconductor® www.0nsemi.com s‘ D N-Channel MOSFET P—Channel MOS ChlpFET CASE tzoeA STVLE 2 PIN CONNECTIONS O ORDERING INFORMATION Devlce Package Shlpplng' PubhcaIion Oldel Num NTHCSS
© Semiconductor Components Industries, LLC, 2016
May, 2019− Rev. 5
1Publication Order Number:
NTHC5513/D
NTHC5513
MOSFET – Power,
Complementary ChipFET
20 V, +3.9 A / -3.0 A
Features
•Complementary N−Channel and P−Channel MOSFET
•Small Size, 40% Smaller than TSOP−6 Package
•Leadless SMD Package Featuring Complementary Pair
•ChipFET Package Provides Great Thermal Characteristics Similar to
Larger Packages
•Low RDS(on) in a ChipFET Package for High Efficiency Performance
•Low Profile (< 1.10 mm) Allows Placement in Extremely Thin
Environments Such as Portable Electronics
•These Devices are Pb−Free, Halogen Free/BFR Free and are RoHS
Compliant
Applications
•Load Switch Applications Requiring Level Shift
•DC−DC Conversion Circuits
•Drive Small Brushless DC Motors
•Designed for Power Management Applications in Portable, Battery
Powered Products
MAXIMUM RATINGS (TJ = 25°C unless otherwise noted)
Parameter Symbol Value Unit
Drain−to−Source Voltage VDSS 20 V
Gate−to−Source Voltage VGS ±12 V
Continuous Drain
Current (Note 1)
N−Ch
Steady
State
TA = 25°CID2.9 A
TA = 85°C 2.1
t v 5 TA = 25°C 3.9
P−Ch
Steady
State
TA = 25°CID−2.2 A
TA = 85°C−1.6
t v 5 TA = 25°C−3.0
Pulsed Drain Current
(Note 1)
N−Ch t = 10 msIDM 12 A
P−Ch t = 10 ms−9.0
Power Dissipation
(Note 1)
Steady
State TA = 25°CPD1.1 W
t v 5 TA = 25°C 2.1
Operating Junction and Storage
Temperature
TJ,
TSTG
−55 to
150
°C
Lead Temperature for Soldering Purposes
(1/8” from case for 10 seconds)
TL260 °C
Stresses exceeding those listed in the Maximum Ratings table may damage the
device. If any of these limits are exceeded, device functionality should not be
assumed, damage may occur and reliability may be affected.
1. Surface Mounted on FR4 board using 1 in sq pad size (Cu area = 1.127 in sq
[1 oz] including traces).
G
D
S
N−Channel MOSFET
1
1
1
G
D
2
2
P−Channel MOSFET
S2
Device Package Shipping†
ORDERING INFORMATION
ChipFET
CASE 1206A
STYLE 2
1
2
3
45
6
7
8
PIN
CONNECTIONS
MARKING
DIAGRAM
C1M
G
C1 = Specific Device Code
M = Month Code
G= Pb−Free Package
1
2
3
4
8
7
6
5
S1
G1
S2
G2
D1
D1
D2
D2
www.onsemi.com
N−Channel
20 V
P−Channel
−20 V
80 mW @ 2.5 V
60 mW @ 4.5 V
130 mW @ −4.5 V
200 mW @ −2.5 V
RDS(on) TYP
3.9 A
−3.0 A
ID MAXV(BR)DSS
NTHC5513T1G ChipFET
(Pb−Free)
3000/Tape & Reel
†For information on tape and reel specifications,
including part orientation and tape sizes, please
refer to our Tape and Reel Packaging Specifications
Brochure, BRD8011/D.
www.cnsemi.com
NTHC5513
www.onsemi.com
2
THERMAL RESISTANCE RATINGS
Parameter Symbol Max Unit
Junction−to−Ambient (Note 1) Steady State
TA = 25°C
RqJA 110 °C/W
t v 5 60
2. Surface Mounted on FR4 board using 1 in sq pad size (Cu area = 1.127 in sq [1 oz] including traces).
ELECTRICAL CHARACTERISTICS (TJ = 25°C unless otherwise noted)
Parameter Symbol N/P Test Conditions Min Typ Max Unit
OFF CHARACTERISTICS (Note 3)
Drain−to−Source Breakdown Voltage V(BR)DSS N
VGS = 0 V
ID = 250 mA20 V
PID = −250 mA−20
Zero Gate Voltage Drain Current IDSS N VGS = 0 V, VDS = 16 V 1.0 mA
P VGS = 0 V, VDS = −16 V −1.0
N VGS = 0 V, VDS = 16 V, TJ = 85 °C 5
P VGS = 0 V, VDS = −16 V, TJ = 85 °C−5
Gate−to−Source Leakage Current IGSS VDS = 0 V, VGS = ±12 V ±100 nA
ON CHARACTERISTICS (Note 3)
Gate Threshold Voltage VGS(TH) N
VGS = VDS
ID = 250 mA0.6 1.2 V
PID = −250 mA−0.6 −1.2
Drain−to−Source On Resistance RDS(on) N VGS = 4.5 V , ID = 2.9 A 0.058 0.080
W
P VGS = −4.5 V , ID = −2.2 A 0.130 0.155
N VGS = 2.5 V , ID = 2.3 A 0.077 0.115
P VGS = −2.5 V, ID = −1.7 A 0.200 0.240
Forward Transconductance gFS N VDS = 10 V, ID = 2.9A 6.0 S
P VDS = −10 V , ID = −2.2 A 6.0
CHARGES AND CAPACITANCES
Input Capacitance CISS N
f = 1 MHz, VGS = 0 V
VDS = 10 V 180 pF
P VDS = −10 V 185
Output Capacitance COSS N VDS = 10 V 80
P VDS = −10 V 95
Reverse Transfer Capacitance CRSS N VDS = 10 V 25
P VDS = −10 V 30
Total Gate Charge QG(TOT) N VGS = 4.5 V, VDS = 10 V, ID = 2.9 A 2.6 4.0 nC
P VGS = −4.5 V, VDS = −10 V, ID = −2.2 A 3.0 6.0
Gate−to−Source Gate Charge QGS N VGS = 4.5 V, VDS = 10 V, ID = 2.9 A 0.6
P VGS = −4.5 V, VDS = −10 V, ID = −2.2 A 0.5
Gate−to−Drain “Miller” Charge QGD N VGS = 4.5 V, VDS = 10 V, ID = 2.9 A 0.7
P VGS = −4.5 V, VDS = −10 V, ID = −2.2 A 0.9
Product parametric performance is indicated in the Electrical Characteristics for the listed test conditions, unless otherwise noted. Product
performance may not be indicated by the Electrical Characteristics if operated under different conditions.
3. Pulse Test: Pulse Width v 250 ms, Duty Cycle v 2%.
www.cnsemi.com
NTHC5513
www.onsemi.com
3
ELECTRICAL CHARACTERISTICS (TJ = 25°C unless otherwise noted)
Parameter Symbol N/P Test Conditions Min Typ Max Unit
SWITCHING CHARACTERISTICS (Note 4)
Turn−On Delay Time td(ON)
NVDD = 16 V, VGS = 4.5 V, ID = 2.9 A,
RG = 2.5 W
5.0 10 ns
Rise Time tr9.0 18
Turn−Off Delay Time td(OFF) 10 20
Fall Time tf3.0 6.0
Turn−On Delay Time td(ON)
PVDD = −16 V, VGS = −4.5 V, ID = −2.2 A,
RG = 2.5 W
7.0 12
Rise Time tr13 25
Turn−Off Delay Time td(OFF) 33 50
Fall Time tf27 40
DRAIN−SOURCE DIODE CHARACTERISTICS
Forward Diode Voltage (Note 5) VSD N
VGS = 0 V
IS = 2.6 A 0.8 1.15 V
P IS = −2.1 A −0.8 −1.15
Reverse Recovery Time (Note 4) tRR N
VGS = 0 V,
dIS / dt = 100 A/ms
IS = 1.5 A 12.5 ns
P IS = −1.5 A 32
Charge Time taN IS = 1.5 A 9.0
P IS = −1.5 A 10
Discharge Time tbN IS = 1.5 A 3.5
P IS = −1.5 A 22
Reverse Recovery Charge QRR N IS = 1.5 A 6.0 nC
P IS = −1.5 A 15
Product parametric performance is indicated in the Electrical Characteristics for the listed test conditions, unless otherwise noted. Product
performance may not be indicated by the Electrical Characteristics if operated under different conditions.
4. Switching characteristics are independent of operating junction temperatures.
5. Pulse Test: Pulse Width v 250 ms, Duty Cycle v 2%.
// vGS : 2.5 v www.cnsemi.com
NTHC5513
www.onsemi.com
4
TYPICAL N−CHANNEL PERFORMANCE CURVES
(TJ = 25°C unless otherwise noted)
2 V
100°C
0
8
5
6
632
VDS, DRAIN−TO−SOURCE VOLTAGE (VOLTS)
ID, DRAIN CURRENT (AMPS)
4
2
0
1
Figure 1. On−Region Characteristics
0
8
21.5 2.5
6
4
2
1
0
3
Figure 2. Transfer Characteristics
VGS, GATE−TO−SOURCE VOLTAGE (VOLTS)
35
0.1
0.05
0
Figure 3. On−Resistance vs. Gate−to−Source
Voltage
VGS, GATE−TO−SOURCE VOLTAGE (VOLTS)
RDS(on), DRAIN−TO−SOURCE RESISTANCE (W)
ID, DRAIN CURRENT (AMPS)
17
Figure 4. On−Resistance vs. Drain Current and
Gate Voltage
ID, DRAIN CURRENT (AMPS)
−50 0−25 25
1.5
1.3
1.1
0.9
0.7
50 125100
Figure 5. On−Resistance Variation with
Temperature
TJ, JUNCTION TEMPERATURE (°C)
TJ = 25°C
0.15
24
TC = −55°C
ID = 2.7 A
TJ = 25°C
0.1
0.04
75 150
TJ = 25°C
ID = 2.7 A
VGS = 4.5 V
RDS(on), DRAIN−TO−SOURCE
RESISTANCE (NORMALIZED)
4
25°C
RDS(on), DRAIN−TO−SOURCE RESISTANCE (W)
1.7
VGS = 4.5 V
16
24 8
1
2016
Figure 6. Drain−to−Source Leakage Current
vs. Voltage
VDS, DRAIN−TO−SOURCE VOLTAGE (VOLTS)
12
VGS = 0 V
IDSS, LEAKAGE (nA)
TJ = 100°C
1.4 V
1.6 V
1.8 V
VGS = 2.5 V
10
100
78
2.2 V
VDS ≥ 10 V
35
0.07
610 1814
VGS = 2.4 V
VGS = 5 V to 3 V
910 0.5
0
www onsem' com
NTHC5513
www.onsemi.com
5
TYPICAL N−CHANNEL PERFORMANCE CURVES
(TJ = 25°C unless otherwise noted)
VDS = 0 V VGS = 0 V
510 10
400
300
200
100
0
20
GATE−TO−SOURCE OR DRAIN−TO−SOURCE VOLTAGE (VOLTS)
Figure 7. Capacitance Variation
C, CAPACITANCE (pF)
Figure 8. Gate−to−Source and
Drain−to−Source Voltage vs. Total Charge
QG, TOTAL GATE CHARGE (nC)
VGS, GATE−TO−SOURCE VOLTAGE (VOLTS)
TJ = 25°C
COSS
CISS
CRSS
VDS, DRAIN−TO−SOURCE VOLTAGE (VOLTS)
101
10
1
100
RG, GATE RESISTANCE (OHMS)
Figure 9. Resistive Switching Time Variation
vs. Gate Resistance
t, TIME (ns)
VDD = 16 V
ID = 2.7 A
VGS = 4.5 V
100
50
td(OFF
)
td(ON)
tf
tr
VGS VDS
15
0.9
3
0
VSD, SOURCE−TO−DRAIN VOLTAGE (VOLTS)
Figure 10. Diode Forward Voltage vs. Current
IS, SOURCE CURRENT (AMPS)
VGS = 0 V
TJ = 25°C
7
0.75
0.45
0.3
1
4
2
1.20.6 1.05
5
6
0
0.5
1
1.5
2
2.5
3
3.5
4
4.5
5
0 0.5 1 1.5 2 2.5 3
0
4
8
12
16
20
ID = 2.7 A
TJ = 25°C
QG
QGD
QGS
: -2.5 v
NTHC5513
www.onsemi.com
6
TYPICAL P−CHANNEL PERFORMANCE CURVES
(TJ = 25°C unless otherwise noted)
−2 V
100°C
0
4
5
3
632
−VDS, DRAIN−TO−SOURCE VOLTAGE (VOLTS)
−ID, DRAIN CURRENT (AMPS)
2
1
0
1
Figure 11. On−Region Characteristics
0.5
4
21.5 2.5
3
2
1
1
0
3
Figure 12. Transfer Characteristics
−VGS, GATE−TO−SOURCE VOLTAGE (VOLTS)
0.1
35
0.3
0.2
0
Figure 13. On−Resistance vs. Gate−to−Source
Voltage
−VGS, GATE−TO−SOURCE VOLTAGE (VOLTS)
RDS(on), DRAIN−TO−SOURCE RESISTANCE (W)
−ID, DRAIN CURRENT (AMPS)
Figure 14. On−Resistance vs. Drain Current
and Gate Voltage
−ID, DRAIN CURRENT (AMPS)
−50 0−25 25
1.4
1.2
1
0.8
0.6
50 125100
Figure 15. On−Resistance Variation with
Temperature
−TJ, JUNCTION TEMPERATURE (°C)
TJ = 25°C
0.5
24
TC = −55°C
ID = −2.1 A
TJ = 25°C
75 150
ID = −2.1 A
VGS = −4.5 V
RDS(on), DRAIN−TO−SOURCE
RESISTANCE (NORMALIZED)
4
25°C
RDS(on), DRAIN−TO−SOURCE RESISTANCE (W)
1.6
−1.2 V
16
24 8
10
2016
Figure 16. Drain−to−Source Leakage Current
vs. Voltage
−VDS, DRAIN−TO−SOURCE VOLTAGE (VOLTS)
12
VGS = 0 V
−IDSS, LEAKAGE (A)
TJ = 150°C
TJ = 100°C
−1.4 V
−1.6 V
−1.8 V
100
1000
10000
78
−2.2 V
VDS ≥ −10 V
0.4
610 1814
VGS = −2.4 V
VGS = −6 V to −3 V
0.1
0.125
0.15
0.175
0.2
0.225
0.25
0.5 1.5 2.5 3.5
TJ = 25°C
VGS = −4.5 V
VGS = −2.5 V
"+1 7‘ I 2. Per Umt Base : R
NTHC5513
www.onsemi.com
7
VDS = 0 V VGS = 0 V
510 10
600
300
200
100
0
20
GATE−TO−SOURCE OR DRAIN−TO−SOURCE VOLTAGE (VOLTS)
Figure 17. Capacitance Variation
C, CAPACITANCE (pF)
Figure 18. Gate−to−Source and
Drain−to−Source Voltage vs. Total Charge
TJ = 25°C
COSS
CISS
CRSS
500
RG, GATE RESISTANCE (OHMS)
Figure 19. Resistive Switching Time Variation
vs. Gate Resistance
t, TIME (ns)
50
400
−VGS −VDS
15
0.9
0.5
0
−VSD, SOURCE−TO−DRAIN VOLTAGE (VOLTS)
Figure 20. Diode Forward Voltage vs. Current
−IS, SOURCE CURRENT (AMPS)
VGS = 0 V
TJ = 25°C
2.5
0.70.5
0.3
1
1.5
2
TYPICAL P−CHANNEL PERFORMANCE CURVES
(TJ = 25°C unless otherwise noted)
0
1
2
3
4
5
01234
0
3
6
9
12
15
−VGS
−VGS, GATE−TO−SOURCE VOLTAGE (V)
ID = −2.1 A
TJ = 25°C
−VDS, DRAIN−TO−SOURCE VOLTAGE (V)
QGD
QGS
−VDS
QT
QG, TOTAL GATE CHARGE (nC)
1
10
100
1000
1 10 100
VDD = −16 V
ID = −2.1 A
VGS = −4.5 V
td(OFF)
td(ON)
tf
tr
Figure 21. Thermal Response
TYPICAL PERFORMANCE CURVES
(TJ = 25°C unless otherwise noted)
2
1
0.1
0.01
10 1010
−4−3−2−1
10 1 10 100 600
Square Wave Pulse Duration (sec)
Normalized Effective Transient
Thermal Impedance
Duty Cycle = 0.5
0.2
Single Pulse
0.1
0.05
0.02
1. Duty Cycle, D =
2. Per Unit Base = RthJA = 90°C/W
3. TJM − TA = PDMZqJA(t)
4. Surface Mounted
t1
t2
PDM
Notes:
t1
t2
4% www.cnsemi.com
NTHC5513
www.onsemi.com
8
Figure 22. Basic Figure 23. Style 2
0.457
0.018
2.032
0.08
0.635
0.025
0.66
0.026
0.711
0.028
0.457
0.018
2.032
0.08
0.635
0.025
0.66
0.026
0.254
0.010
1.092
0.043
0.178
0.007
*For additional information on our Pb−Free strategy and soldering
details, please download the ON Semiconductor Soldering and
Mounting Techniques Reference Manual, SOLDERRM/D.
SOLDERING FOOTPRINT*
BASIC PAD PATTERNS
The basic pad layout with dimensions is shown in
Figure 22. This is sufficient for low power dissipation
MOSFET applications, but power semiconductor
performance requires a greater copper pad area, particularly
for the drain leads.
The minimum recommended pad pattern shown in
Figure 23 improves the thermal area of the drain
connections (pins 5, 6, 7, 8) while remaining within the
confines of the basic footprint. The drain copper area is
0.0019 sq. in. (or 1.22 sq. mm). This will assist the power
dissipation path away from the device (through the copper
lead−frame) and into the board and exterior chassis (if
applicable) for the single device. The addition of a further
copper area and/or the addition of vias to other board layers
will enhance the performance still further.
ChipFET is a trademark of Vishay Siliconix.
0N Semiwndudw" DIM MOM A 1 Us u an n u :m u m2 a u 15 u Una n 3 Us a 12a 2 1 55 u was a 55 as .125 Esc el 55 as uzz Esc L U28 \ was \ 042 mm \ num‘ mm IED \ 19D \ 2m) aun‘ ums‘ ems \ \ y a \ \ \ \ i * iiiii + iiiii i 7 \ ‘ "WW l y y \ \ \ y ij 9 7 e (We; ON Semmanduclar vesewe: ma th‘ [a make change: wxmnuHunhev nauca [a any pmduc‘s havem 0N Sannwnamm makes nu wanamy represenlalmn m guavanlee regardmg ma sumamhly at us pmducls can any pamcu‘av purpase nnv am ON Semanduchv assume any Mammy ansmg am the apphcalmn m we no any pmducl m cm and apecmcaHy macxanns any and 5H Mammy mchmmg wmnam hmwahan spema‘ cansequenha‘ m \nmdenla‘ damages ON Sannaanaacxar dues nmwnyay any hcense under \Ls pa|em ”QM: nar xna nams av n|hers
E
A
b
e
e1
D
1234
8765
c
L
1234
8765
NOTES:
1. DIMENSIONING AND TOLERANCING PER ANSI Y14.5M, 1982.
2. CONTROLLING DIMENSION: MILLIMETER.
3. MOLD GATE BURRS SHALL NOT EXCEED 0.13 MM PER SIDE.
4. LEADFRAME TO MOLDED BODY OFFSET IN HORIZONTAL
AND VERTICAL SHALL NOT EXCEED 0.08 MM.
5. DIMENSIONS A AND B EXCLUSIVE OF MOLD GATE BURRS.
6. NO MOLD FLASH ALLOWED ON THE TOP AND BOTTOM LEAD
SURFACE.
0.05 (0.002)
SCALE 1:1
xxx MG
G
xxx = Specific Device Code
M = Month Code
G= Pb−Free Package
(Note: Microdot may be in either location)
GENERIC
MARKING DIAGRAM*
*This information is generic. Please refer to
device data sheet for actual part marking.
Pb−Free indicator, “G” or microdot “ G”,
may or may not be present.
OPTIONAL SOLDERING FOOTPRINTS ON PAGE 2
1
8
DIM
A
MIN NOM MAX MIN
MILLIMETERS
1.00 1.05 1.10 0.039
INCHES
b0.25 0.30 0.35 0.010
c0.10 0.15 0.20 0.004
D2.95 3.05 3.10 0.116
E1.55 1.65 1.70 0.061
e0.65 BSC
e1 0.55 BSC
L0.28 0.35 0.42 0.011
0.041 0.043
0.012 0.014
0.006 0.008
0.120 0.122
0.065 0.067
0.025 BSC
0.022 BSC
0.014 0.017
NOM MAX
1.80 1.90 2.00 0.071 0.075 0.079
HE
5°NOM
q5°NOM
HE
q
STYLE 1:
PIN 1. DRAIN
2. DRAIN
3. DRAIN
4. GATE
5. SOURCE
6. DRAIN
7. DRAIN
8. DRAIN
STYLE 2:
PIN 1. SOURCE 1
2. GATE 1
3. SOURCE 2
4. GATE 2
5. DRAIN 2
6. DRAIN 2
7. DRAIN 1
8. DRAIN 1
STYLE 3:
PIN 1. ANODE
2. ANODE
3. SOURCE
4. GATE
5. DRAIN
6. DRAIN
7. CATHODE
8. CATHODE
STYLE 4:
PIN 1. COLLECTOR
2. COLLECTOR
3. COLLECTOR
4. BASE
5. EMITTER
6. COLLECTOR
7. COLLECTOR
8. COLLECTOR
STYLE 5:
PIN 1. ANODE
2. ANODE
3. DRAIN
4. DRAIN
5. SOURCE
6. GATE
7. CATHODE
8. CATHODE
SOLDERING FOOTPRINT
0.457
0.018
2.032
0.08
0.65
0.025
PITCH
0.66
0.026 ǒmm
inchesǓ
Basic Style
2.362
0.093
1
8X
8X
STYLE 6:
PIN 1. ANODE
2. DRAIN
3. DRAIN
4. GATE
5. SOURCE
6. DRAIN
7. DRAIN
8. CATHODE / DRAIN
RESET
ChipFETt
CASE1206A−03
ISSUE K
DATE 19 MAY 2009
MECHANICAL CASE OUTLINE
PACKAGE DIMENSIONS
ON Semiconductor and are trademarks of Semiconductor Components Industries, LLC dba ON Semiconductor or its subsidiaries in the United States and/or other countries.
ON Semiconductor reserves the right to make changes without further notice to any products herein. ON Semiconductor makes no warranty, representation or guarantee regarding
the suitability of its products for any particular purpose, nor does ON Semiconductor assume any liability arising out of the application or use of any product or circuit, and specifically
disclaims any and all liability, including without limitation special, consequential or incidental damages. ON Semiconductor does not convey any license under its patent rights nor the
rights of others.
98AON03078D
DOCUMENT NUMBER:
DESCRIPTION:
Electronic versions are uncontrolled except when accessed directly from the Document Repository.
Printed versions are uncontrolled except when stamped “CONTROLLED COPY” in red.
PAGE 1 OF 2
ChipFET
© Semiconductor Components Industries, LLC, 2019 www.onsemi.com
‘ i i 1 \ \ 1 7 1 i i , ,,,,, 4 ,,,,,,,,,, i ,,,,, , ¢ a 1 L,,,,, 1 ¢ 1 1 . , 1 i a 7 «my; a i «e i a ma 17E 775 \ \ \ i \ \ \ \ \ \ \ ; 7::T 77777 i ’ 77777 T111114 a 1 1 1 if ‘T”””’i 3”””’T’ a] «7» ea» a] (n3; (n31, ON Semxcunduchv and are Mademavk: av Semmanduclur Campunenls Inuwnaa LLC dba ON Samanauaxar Dr H: suaamanas m xna Umled sxaxaa andJm mhev comma: ON Semxcunduclar vesewe: we th| [a make change: wuhum Yunhev name [a any prnduns havem ON Semanduc‘m makes m7 wanamy represenlalmn m guarantee regardmg ma sumahmy at W; manuals can any pamcu‘av purpase nnv dues ON Semumndudm assume any Mammy ansmg mac xna apphcahan m we no any pmduclnv mum and :pecmcafly dwsc‘axms any and au Mammy mcmdmg wmnam hmma‘mn spema‘ cansequenha‘ m \nmdenla‘ damages ON Sammnauaxar dues nn| aanyay any hcense under Ms pa|em thls nar xna
*For additional information on our Pb−Free strategy and soldering
details, please download the ON Semiconductor Soldering and
Mounting Techniques Reference Manual, SOLDERRM/D.
2.032
0.08
1.727
0.068
0.66
0.026
2.362
0.093
ǒmm
inchesǓ
0.457
0.018
2.032
0.08
0.65
0.025
PITCH
0.66
0.026
1.118
0.044 ǒmm
inchesǓ
1.092
0.043
2.362
0.093
Styles 1 and 4
Style 5
Style 2
0.457
0.018
ChipFETt
CASE 1206A−03
ISSUE K
DATE 19 MAY 2009
ADDITIONAL SOLDERING FOOTPRINTS*
0.457
0.018
2.032
0.08
0.66
0.026
1.118
0.044
ǒmm
inchesǓ
1.092
0.043
Style 3
1
2X
2X
1
2X4X
2X
4X
1
2X
2X
0.65
0.025
PITCH
2.362
0.093
0.457
0.018
2.032
0.08
0.66
0.026
1.118
0.044
ǒmm
inchesǓ
1.092
0.043
1
2X
2X
0.65
0.025
PITCH
2.362
0.093
ON Semiconductor and are trademarks of Semiconductor Components Industries, LLC dba ON Semiconductor or its subsidiaries in the United States and/or other countries.
ON Semiconductor reserves the right to make changes without further notice to any products herein. ON Semiconductor makes no warranty, representation or guarantee regarding
the suitability of its products for any particular purpose, nor does ON Semiconductor assume any liability arising out of the application or use of any product or circuit, and specifically
disclaims any and all liability, including without limitation special, consequential or incidental damages. ON Semiconductor does not convey any license under its patent rights nor the
rights of others.
98AON03078D
DOCUMENT NUMBER:
DESCRIPTION:
Electronic versions are uncontrolled except when accessed directly from the Document Repository.
Printed versions are uncontrolled except when stamped “CONTROLLED COPY” in red.
PAGE 2 OF 2
ChipFET
© Semiconductor Components Industries, LLC, 2019 www.onsemi.com
a a e lrademavks av Semxcunduclm Cnmvnnems In "sine \ghlsmanumhernlpalems \rademavks Dav www menu cumrsuerguwaxem Mavkmg gm 9 www nnserm cum
www.onsemi.com
1
ON Semiconductor and are trademarks of Semiconductor Components Industries, LLC dba ON Semiconductor or its subsidiaries in the United States and/or other countries.
ON Semiconductor owns the rights to a number of patents, trademarks, copyrights, trade secrets, and other intellectual property. A listing of ON Semiconductor’s product/patent
coverage may be accessed at www.onsemi.com/site/pdf/Patent−Marking.pdf. ON Semiconductor reserves the right to make changes without further notice to any products herein.
ON Semiconductor makes no warranty, representation or guarantee regarding the suitability of its products for any particular purpose, nor does ON Semiconductor assume any liability
arising out of the application or use of any product or circuit, and specifically disclaims any and all liability, including without limitation special, consequential or incidental damages.
Buyer is responsible for its products and applications using ON Semiconductor products, including compliance with all laws, regulations and safety requirements or standards,
regardless of any support or applications information provided by ON Semiconductor. “Typical” parameters which may be provided in ON Semiconductor data sheets and/or
specifications can and do vary in different applications and actual performance may vary over time. All operating parameters, including “Typicals” must be validated for each customer
application by customer’s technical experts. ON Semiconductor does not convey any license under its patent rights nor the rights of others. ON Semiconductor products are not
designed, intended, or authorized for use as a critical component in life support systems or any FDA Class 3 medical devices or medical devices with a same or similar classification
in a foreign jurisdiction or any devices intended for implantation in the human body. Should Buyer purchase or use ON Semiconductor products for any such unintended or unauthorized
application, Buyer shall indemnify and hold ON Semiconductor and its officers, employees, subsidiaries, affiliates, and distributors harmless against all claims, costs, damages, and
expenses, and reasonable attorney fees arising out of, directly or indirectly, any claim of personal injury or death associated with such unintended or unauthorized use, even if such
claim alleges that ON Semiconductor was negligent regarding the design or manufacture of the part. ON Semiconductor is an Equal Opportunity/Affirmative Action Employer. This
literature is subject to all applicable copyright laws and is not for resale in any manner.
PUBLICATION ORDERING INFORMATION
TECHNICAL SUPPORT
North American Technical Support:
Voice Mail: 1 800−282−9855 Toll Free USA/Canada
Phone: 011 421 33 790 2910
LITERATURE FULFILLMENT:
Email Requests to: orderlit@onsemi.com
ON Semiconductor Website: www.onsemi.com
Europe, Middle East and Africa Technical Support:
Phone: 00421 33 790 2910
For additional information, please contact your local Sales Representative
◊