Datenblatt für NSS20201MR6T1G von onsemi

0N Semiconductor®
© Semiconductor Components Industries, LLC, 2006
January, 2006 − Rev. 0 1Publication Order Number:
NSS20201MR6/D
NSS20201MR6T1G
20 V, 3 A, Low VCE(sat)
NPN Transistor
ON Semiconductor’s e2PowerEdge family of low VCE(sat)
transistors are miniature surface mount devices featuring ultra low
saturation voltage (VCE(sat)) and high current gain capability. These
are designed for use in low voltage, high speed switching applications
where affordable efficient energy control is important.
Typical application are DC−DC converters and power management
in portable and battery powered products such as cellular and cordless
phones, PDAs, computers, printers, digital cameras and MP3 players.
Other applications are low voltage motor controls in mass storage
products such as disc drives and tape drives. In the automotive
industry they can be used in air bag deployment and in the instrument
cluster. The high current gain allows e2PowerEdge devices to be
driven directly from PMU’s control outputs, and the Linear Gain
(Beta) makes them ideal components in analog amplifiers.
MAXIMUM RATINGS (TA = 25°C)
Rating Symbol Max Unit
Collector-Emitter Voltage VCEO 20 V
Collector-Base Voltage VCBO 40 V
Emitter-Base Voltage VEBO 5.0 V
Collector Current − Continuous IC2.0 A
Collector Current − Peak ICM 3.0 A
THERMAL CHARACTERISTICS
Characteristic Symbol Max Unit
Total Device Dissipation
TA = 25°C
Derate above 25°C
PD (Note 1) 460
3.7
mW
mW/°C
Thermal Resistance,
Junction−to−Ambient RqJA (Note 1) 272 °C/W
Total Device Dissipation
TA = 25°C
Derate above 25°C
PD (Note 2) 780
6.3
mW
mW/°C
Thermal Resistance,
Junction−to−Ambient RqJA (Note 2) 160 °C/W
Thermal Resistance,
Junction−to−Lead #1 RqJL (Note 1)
RqJL (Note 2) 48
40
°C/W
°C/W
Total Device Dissipation
(Single Pulse < 10 s) PDsingle
(Note 2) 1.5 W
Junction and Storage
Temperature Range TJ, Tstg −55 to
+150
°C
Maximum ratings are those values beyond which device damage can occur.
Maximum ratings applied to the device are individual stress limit values (not
normal operating conditions) and are not valid simultaneously. If these limits are
exceeded, device functional operation is not implied, damage may occur and
reliability may be affected.
1. FR−4 @ 100 mm2, 2 oz copper traces.
2. FR−4 @ 500 mm2, 2 oz copper traces.
Device Package Shipping†
ORDERING INFORMATION
NSS20201MR6T1G TSOP−6
(Pb−Free)
CASE 318G
TSOP−6
STYLE 6
3000/Tape & Ree
l
DEVICE MARKING
4
5
6
3
2
1
COLLECTOR
1, 2, 5, 6
3
BASE
4
EMITTER
VS0 MG
G
VS0 = Specific Device Code
M = Date Code
G= Pb−Free Package
(Note: Microdot may be in either location)
†For information on tape and reel specifications,
including part orientation and tape sizes, please
refer to our Tape and Reel Packaging Specification
s
Brochure, BRD8011/D.
http://onsemi.com
20 VOLTS
3.0 AMPS
NPN LOW VCE(sat) TRANSISTOR
EQUIVALENT RDS(on) 100 mW
NSS20201MR6T1G
http://onsemi.com
2
ELECTRICAL CHARACTERISTICS (TA = 25°C unless otherwise noted)
Characteristic Symbol Min Typ Max Unit
OFF CHARACTERISTICS
Collector−Emitter Breakdown Voltage
(IC = 10 mA, IB = 0) V(BR)CEO 20 − − V
Collector−Base Breakdown Voltage
(IC = 0.1 mA, IE = 0) V(BR)CBO 40 − − V
Emitter−Base Breakdown Voltage
(IE = 0.1 mA, IC = 0) V(BR)EBO 5.0 − − V
Collector Cutoff Current
(VCB = 40 V, IE = 0) ICBO − − 0.1 mA
Collector−Emitter Cutoff Current
(VCES = 20 V) ICES − − 0.1 mA
Emitter Cutoff Current
(VEB = 5.0 V) IEBO − 0.1 mA
ON CHARACTERISTICS
DC Current Gain (Note 3)
(IC = 1.0 mA, VCE = 5.0 V)
(IC = 0.5 A, VCE = 5.0 V)
(IC = 1.0 A, VCE = 5.0 V)
hFE 300
300
200
−
−
−
−
−
−
Collector−Emitter Saturation Voltage (Note 3)
(IC = 1.0 A, IB = 100 mA)
(IC = 0.5 A, IB = 50 mA)
(IC = 0.1 A, IB = 10 mA)
VCE(sat) −
−
−
−
−
−
0.150
0.100
0.025
V
Base−Emitter Saturation Voltage (Note 3)
(IC = 1.0 A, IB = 0.1 A) VBE(sat) − − 0.95
V
Base−Emitter Turn−on Voltage (Note 3)
(IC = 1.0 A, VCE = 2.0 V) VBE(on) − − 0.90 V
Cutoff Frequency
(IC = 100 mA, VCE = 5.0 V, f = 100 MHz fT200 − − MHz
Output Capacitance (f = 1.0 MHz) Cobo − − 15 pF
3. Pulsed Condition: Pulse Width ≤ 300 msec, Duty Cycle ≤ 2%.
0N Semiwndudw" NDTES l DlMENSloNle AND ToLERANclNe FER AS $ 2 CONTROLLING DlMENSloN MlLLlMETERS S MAleuM LEAD IHICKNESS lNcLUDES LEAD ElNlSH MlNlMuM LEAD TchKNESS lS TNE MINIMUM TNchNESS OF EASE MATERlAL 4 DlMENSloNS D AND E1 DO NoT lNcLuDE MoLD FLASH. l PROTRUSWONS‘ OR GATE BURRS MOLD FLASH‘ PRoTRuSloNS 0R GATE BURRS SHALL NoT EXCEED a ls. FER SlDE DlMENSloNS D AND El ARE DETERMlNED AT DATuM N 5 PW oNE lNchAToR MDST EE LocATED IN TNE lNchATED zoNE I: E¥23 M MILLIMEYERS L47 pm MIN no». MAX A 090 i on HD Al um REE am I: E2E EEE ESE ‘ c DID ms 025 \ u 29E am am A C1 1 \ E 25a 275 Sun \ i J U2 E1 1 an 1 5n T70 / e DES 095 m5 j 1‘ T f L EEE m EEE u E2EESE n l e l H!" 2 SWLE a STVLE 4 STVLE E SIVLE E EMlTTE RlNi ENABLE Rim Ric PlNl EMlTTERZ RlNi coLLEcmR BASE‘ 2 WC 2 Vin 2 EASE2 2 coLLEcmR coLLEcToRi 3 new a NOTUSED a coLLEcToRi 3 eASE EMlTTE 4 V1 4 eRounp 4 EMlTTERl 4 EMH’TER EASE2 E Vln E ENABLE E BASE‘ E coLLEcmR coLLEcToR2 E vEei E Ler E coLLEcToR2 E coLLEcmR SWLE E STVLE m STVLE n SIVLE i2 RlNi LowvoLTAeEEAiE Rim mouns PlNl SOURCE] am no 2 DRAlN 2 GND 2 pRAlN2 2 GROUND 3 SOURCE a meme a pRAlN2 3 no 4 DRAlN 4 mime 4 eouREE2 4 no E DRAlN E VBUS E GATEl E vcc E HlGH VOLIAGEGATE E mini. E pRAlNileATE2 E no SWLE‘S RlNi ANODE 2 SOURCE 3 GALE RAlN 4 DRAlN N E WC N E CATHODE ED GENERIC “ERIN-p. MARKING DIAGRAM" XXXAYW- xxx M- D D D o I o - l U LI U 1U U LI lc STANDARD [I j xxx e Specific Device Code xxx e Specific Device Code A :Assemhly Locatlon M Dale Dgae v a Year - : Pb-Free Package 41 le w e Walk Week . e Pb-Free Package “For addlllonal inlormalipn on our Pia-Flee Slralegy and solderlng aeLalls, please download the ON Semlconducmr Sglgenng and Mgunling Techniques Releience Manual, SOLDERRM/D *‘rhls inlormamn iS generic. Please Teler Lo gel/ice data Sheet for actual pan marking PD-Free indicalpl, “e“ or mlcmdo “ may or may not be plesenl, 0N Semlemaeam Eaa J ave Eaaemaiks al SemEEEEEExE cEmEEEems mEEsmes. LLC EEa ON SememaenE E .E seEsEEnes m the Dmiea Siaies aEEiEEEmem eammes 0N SemeaaEeEE iesesEE me "En la make EnEEEes WEE. We. Renee la any ETEEEas keem 0N SemEEEEEaE mekes EE wanamy. meEmesemalEE Em Eleanee TEEamEmE the sulleEniy El Es Eaaeee 4E EmY Danlculal EEEEse does ON SemEEEEEEai asseme any leEniY EEEEE ml the EEEEEEEE E. use El anY Emmi amen EEE sEEEnEEny Eseiame ERY an en laEniY menamgmen lmleian sEEEai EEEseEEEEnal E. meaemal EamEEes ON Semeaaeem EEes RE. EEEEEE Em leense EEEE ls Eeiem EEEE [he
TSOP−6
CASE 318G−02
ISSUE V
DATE 12 JUN 2012
SCALE 2:1
STYLE 1:
PIN 1. DRAIN
2. DRAIN
3. GATE
4. SOURCE
5. DRAIN
6. DRAIN
23
456
D
1
e
b
E1
A1
A
0.05
NOTES:
1. DIMENSIONING AND TOLERANCING PER ASME Y14.5M, 1994.
2. CONTROLLING DIMENSION: MILLIMETERS.
3. MAXIMUM LEAD THICKNESS INCLUDES LEAD FINISH. MINIMUM
LEAD THICKNESS IS THE MINIMUM THICKNESS OF BASE MATERIAL.
4. DIMENSIONS D AND E1 DO NOT INCLUDE MOLD FLASH,
PROTRUSIONS, OR GATE BURRS. MOLD FLASH, PROTRUSIONS, OR
GATE BURRS SHALL NOT EXCEED 0.15 PER SIDE. DIMENSIONS D
AND E1 ARE DETERMINED AT DATUM H.
5. PIN ONE INDICATOR MUST BE LOCATED IN THE INDICATED ZONE.
c
STYLE 2:
PIN 1. EMITTER 2
2. BASE 1
3. COLLECTOR 1
4. EMITTER 1
5. BASE 2
6. COLLECTOR 2
STYLE 3:
PIN 1. ENABLE
2. N/C
3. R BOOST
4. Vz
5. V in
6. V out
STYLE 4:
PIN 1. N/C
2. V in
3. NOT USED
4. GROUND
5. ENABLE
6. LOAD
XXX MG
G
XXX = Specific Device Code
A =Assembly Location
Y = Year
W = Work Week
G= Pb−Free Package
STYLE 5:
PIN 1. EMITTER 2
2. BASE 2
3. COLLECTOR 1
4. EMITTER 1
5. BASE 1
6. COLLECTOR 2
STYLE 6:
PIN 1. COLLECTOR
2. COLLECTOR
3. BASE
4. EMITTER
5. COLLECTOR
6. COLLECTOR
STYLE 7:
PIN 1. COLLECTOR
2. COLLECTOR
3. BASE
4. N/C
5. COLLECTOR
6. EMITTER
STYLE 8:
PIN 1. Vbus
2. D(in)
3. D(in)+
4. D(out)+
5. D(out)
6. GND
GENERIC
MARKING DIAGRAM*
STYLE 9:
PIN 1. LOW VOLTAGE GATE
2. DRAIN
3. SOURCE
4. DRAIN
5. DRAIN
6. HIGH VOLTAGE GATE
STYLE 10:
PIN 1. D(OUT)+
2. GND
3. D(OUT)−
4. D(IN)−
5. VBUS
6. D(IN)+
1
1
*For additional information on our Pb−Free strategy and soldering
details, please download the ON Semiconductor Soldering and
Mounting Techniques Reference Manual, SOLDERRM/D.
SOLDERING FOOTPRINT*
STYLE 11:
PIN 1. SOURCE 1
2. DRAIN 2
3. DRAIN 2
4. SOURCE 2
5. GATE 1
6. DRAIN 1/GATE 2
STYLE 12:
PIN 1. I/O
2. GROUND
3. I/O
4. I/O
5. VCC
6. I/O
*This information is generic. Please refer to device data sheet
for actual part marking. Pb−Free indicator, “G” or microdot “
G”, may or may not be present.
XXXAYWG
G
1
STANDARDIC
XXX = Specific Device Code
M = Date Code
G= Pb−Free Package
DIM
A
MIN NOM MAX
MILLIMETERS
0.90 1.00 1.10
A1 0.01 0.06 0.10
b0.25 0.38 0.50
c0.10 0.18 0.26
D2.90 3.00 3.10
E2.50 2.75 3.00
e0.85 0.95 1.05
L0.20 0.40 0.60
0.25 BSC
L2
−
0°10°
STYLE 13:
PIN 1. GATE 1
2. SOURCE 2
3. GATE 2
4. DRAIN 2
5. SOURCE 1
6. DRAIN 1
STYLE 14:
PIN 1. ANODE
2. SOURCE
3. GATE
4. CATHODE/DRAIN
5. CATHODE/DRAIN
6. CATHODE/DRAIN
STYLE 15:
PIN 1. ANODE
2. SOURCE
3. GATE
4. DRAIN
5. N/C
6. CATHODE
1.30 1.50 1.70
E1
E
RECOMMENDED
NOTE 5
L
C
M
H
L2
SEATING
PLANE
GAUGE
PLANE
DETAIL Z
DETAIL Z
0.60
6X
3.20 0.95
6X
0.95
PITCH
DIMENSIONS: MILLIMETERS
M
STYLE 16:
PIN 1. ANODE/CATHODE
2. BASE
3. EMITTER
4. COLLECTOR
5. ANODE
6. CATHODE
STYLE 17:
PIN 1. EMITTER
2. BASE
3. ANODE/CATHODE
4. ANODE
5. CATHODE
6. COLLECTOR
MECHANICAL CASE OUTLINE
PACKAGE DIMENSIONS
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ON Semiconductor reserves the right to make changes without further notice to any products herein. ON Semiconductor makes no warranty, representation or guarantee regarding
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